diff --git a/.github/dangerjs/.gitignore b/.github/dangerjs/.gitignore deleted file mode 100644 index 0471eff2c21..00000000000 --- a/.github/dangerjs/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -# Transpiled JavaScript (if any) -dist - -# Installed dependencies -node_modules diff --git a/.github/dangerjs/README.md b/.github/dangerjs/README.md deleted file mode 100644 index fc027a45514..00000000000 --- a/.github/dangerjs/README.md +++ /dev/null @@ -1,47 +0,0 @@ -# DangerJS pull request automatic review tool - GitHub - -## Implementation -The main development is done in Espressif Gitlab project. -Espressif [GitHub project espressif/esp-idf](https://github.com/espressif/esp-idf) is only a public mirror. - -Therefore, all changes and updates to DangerJS files (`.github/dangerjs`) must be made via MR in the **Gitlab** repository by Espressif engineer. - -When adding a new Danger rule or updating existing one, might be a good idea to test it on the developer's fork of GitHub project. This way, the new feature can be tested using a GitHub action without concern of damaging Espressif's GitHub repository. - -Danger for Espressif GitHub is implemented in TypeScript. This makes the code more readable and robust than plain JavaScript. -Compilation to JavaScript code (using `tsc`) is not necessary; Danger handles TypeScript natively. - -A good practice is to store each Danger rule in a separate module, and then import these modules into the main Danger file `.github/dangerjs/dangerfile.ts` (see how this is done for currently present modules when adding a new one). - -If the Danger module (new check/rule) uses an external NPM module (e.g. `axios`), be sure to add this dependency to `.github/dangerjs/package.json` and also update `.github/dangerjs/package-lock.json`. - -In the GitHub action, `danger` is not installed globally (nor are its dependencies) and the `npx` call is used to start the `danger` checks in CI. - - -## Adding new Danger rule -For local development you can use following strategy - -#### Install dependencies -```sh -cd .github/dangerjs -npm install -``` -(If the IDE still shows compiler/typing errors, reload the IDE window.) - -#### Add new code as needed or make updates - -#### Test locally -Danger rules can be tested locally (without running the GitHub action pipeline). -To do this, you have to first export the ENV variables used by Danger in the local terminal: - -```sh -export GITHUB_TOKEN='**************************************' -``` - -Then you can call Danger by: -```sh -cd .github/dangerjs - -danger pr https://github.com/espressif/esp-idf/pull/ -``` -The result will be displayed in your terminal. diff --git a/.github/dangerjs/dangerfile.ts b/.github/dangerjs/dangerfile.ts deleted file mode 100644 index fbb6efe6d6b..00000000000 --- a/.github/dangerjs/dangerfile.ts +++ /dev/null @@ -1,48 +0,0 @@ -import { DangerResults } from "danger"; -declare const results: DangerResults; -declare const message: (message: string, results?: DangerResults) => void; -declare const markdown: (message: string, results?: DangerResults) => void; - -// Import modules with danger rules -// (Modules with checks are stored in ".github/dangerjs/.ts". To import them, use path relative to "dangerfile.ts") -import prCommitsTooManyCommits from "./prCommitsTooManyCommits"; -import prDescription from "./prDescription"; -import prTargetBranch from "./prTargetBranch"; -import prInfoContributor from "./prInfoContributor"; -import prCommitMessage from "./prCommitMessage"; - -async function runDangerRules(): Promise { - // Message to contributor about review and merge process - const prInfoContributorMessage: string = await prInfoContributor(); - markdown(prInfoContributorMessage); - - // Run danger checks - prCommitsTooManyCommits(); - prDescription(); - prTargetBranch(); - prCommitMessage(); - - // Add success log if no issues - const dangerFails: number = results.fails.length; - const dangerWarns: number = results.warnings.length; - const dangerInfos: number = results.messages.length; - if (!dangerFails && !dangerWarns && !dangerInfos) { - return message("Good Job! All checks are passing!"); - } - - // Add retry link - addRetryLink(); -} - -runDangerRules(); - -function addRetryLink(): void { - const serverUrl: string | undefined = process.env.GITHUB_SERVER_URL; - const repoName: string | undefined = process.env.GITHUB_REPOSITORY; - const runId: string | undefined = process.env.GITHUB_RUN_ID; - - const retryLinkUrl: string = `${serverUrl}/${repoName}/actions/runs/${runId}`; - const retryLink: string = `:repeat: You can re-run automatic PR checks by retrying the DangerJS action`; - - markdown(retryLink); -} diff --git a/.github/dangerjs/package-lock.json b/.github/dangerjs/package-lock.json deleted file mode 100644 index 5229aed3f92..00000000000 --- a/.github/dangerjs/package-lock.json +++ /dev/null @@ -1,1999 +0,0 @@ -{ - "name": "dangerjs-github", - "lockfileVersion": 3, - "requires": true, - "packages": { - "": { - "name": "dangerjs-github", - "license": "ISC", - "dependencies": { - "axios": "^1.3.3", - "danger": "^11.2.3", - "request": "^2.88.2", - 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-declare const danger: DangerDSLType; -declare const warn: (message: string, results?: DangerResults) => void; - -interface Commit { - message: string; -} - -/** - * Check if commit messages are sufficiently descriptive (not too short). - * - * Search for commit messages that appear to be automatically generated or temporary messages and report them. - * - * @dangerjs WARN - */ -export default function (): void { - const prCommits: Commit[] = danger.git.commits; - - const detectRegexes: RegExp[] = [ - /^Merge pull request #\d+ from .*/i, // Automatically generated message by GitHub - /^Merged .+:.+ into .+/i, // Automatically generated message by GitHub - /^Automatic merge by GitHub Action/i, // Automatically generated message by GitHub - /^Merge branch '.*' of .+ into .+/i, // Automatically generated message by GitHub - /^Create\s[a-zA-Z0-9_.-]+(\.[a-zA-Z0-9]{1,4})?(?=\s|$)/, // Automatically generated message by GitHub using UI - /^Delete\s[a-zA-Z0-9_.-]+(\.[a-zA-Z0-9]{1,4})?(?=\s|$)/, // Automatically generated message by GitHub using UI - /^Update\s[a-zA-Z0-9_.-]+(\.[a-zA-Z0-9]{1,4})?(?=\s|$)/, // Automatically generated message by GitHub using UI - /^Initial commit/i, // Automatically generated message by GitHub - /^WIP.*/i, // Message starts with prefix "WIP" - /^Cleaned.*/i, // Message starts "Cleaned", , probably temporary - /^Test:.*/i, // Message starts with "test" prefix, probably temporary - /clean ?up/i, // Message contains "clean up", probably temporary - /^[^A-Za-z0-9\s].*/, // Message starts with special characters - ]; - - let partMessages: string[] = []; - - for (const commit of prCommits) { - const commitMessage: string = commit.message; - const commitMessageTitle: string = commit.message.split("\n")[0]; - - // Check if the commit message matches any regex from "detectRegexes" - if (detectRegexes.some((regex) => commitMessage.match(regex))) { - partMessages.push( - `- the commit message \`${commitMessageTitle}\` appears to be a temporary or automatically generated message` - ); - continue; - } - - // Check if the commit message is not too short - const shortCommitMessageThreshold: number = 20; // commit message is considered too short below this number of characters - if (commitMessage.length < shortCommitMessageThreshold) { - partMessages.push( - `- the commit message \`${commitMessageTitle}\` may not be sufficiently descriptive` - ); - } - } - - // Create report - if (partMessages.length) { - partMessages.sort(); - let dangerMessage = `\nSome issues found for the commit messages in this MR:\n${partMessages.join( - "\n" - )} - \nPlease consider updating these commit messages.`; - warn(dangerMessage); - } -} diff --git a/.github/dangerjs/prCommitsTooManyCommits.ts b/.github/dangerjs/prCommitsTooManyCommits.ts deleted file mode 100644 index a973752a063..00000000000 --- a/.github/dangerjs/prCommitsTooManyCommits.ts +++ /dev/null @@ -1,19 +0,0 @@ -import { DangerDSLType, DangerResults } from "danger"; -declare const danger: DangerDSLType; -declare const message: (message: string, results?: DangerResults) => void; - -/** - * Check if pull request has not an excessive numbers of commits (if squashed) - * - * @dangerjs INFO - */ -export default function (): void { - const tooManyCommitThreshold: number = 2; // above this number of commits, squash commits is suggested - const prCommits: number = danger.github.commits.length; - - if (prCommits > tooManyCommitThreshold) { - return message( - `You might consider squashing your ${prCommits} commits (simplifying branch history).` - ); - } -} diff --git a/.github/dangerjs/prDescription.ts b/.github/dangerjs/prDescription.ts deleted file mode 100644 index 06fe2780a0b..00000000000 --- a/.github/dangerjs/prDescription.ts +++ /dev/null @@ -1,19 +0,0 @@ -import { DangerDSLType, DangerResults } from "danger"; -declare const danger: DangerDSLType; -declare const warn: (message: string, results?: DangerResults) => void; - -/** - * Check if pull request has has a sufficiently accurate description - * - * @dangerjs WARN - */ -export default function (): void { - const prDescription: string = danger.github.pr.body; - const shortPrDescriptionThreshold: number = 100; // Description is considered too short below this number of characters - - if (prDescription.length < shortPrDescriptionThreshold) { - return warn( - "The PR description looks very brief, please check if more details can be added." - ); - } -} diff --git a/.github/dangerjs/prInfoContributor.ts b/.github/dangerjs/prInfoContributor.ts deleted file mode 100644 index 1d4f9be56a1..00000000000 --- a/.github/dangerjs/prInfoContributor.ts +++ /dev/null @@ -1,58 +0,0 @@ -import { DangerDSLType } from "danger"; -declare const danger: DangerDSLType; - -interface Contributor { - login?: string; -} - -const authorLogin = danger.github.pr.user.login; -const messageKnownContributor: string = ` -*** -👋 **Hi ${authorLogin}**, thank you for your another contribution to \`espressif/esp-idf\` project! - -If the change is approved and passes the tests in our internal git repository, it will appear in this public Github repository on the next sync. -*** -`; - -const messageFirstContributor: string = ` -*** -👋 **Welcome ${authorLogin}**, thank you for your first contribution to \`espressif/esp-idf\` project! - -📘 Please check [Contributions Guide](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/contribute/index.html#contributions-guide) for the contribution checklist, information regarding code and documentation style, testing and other topics. - -🖊️ Please also make sure you have **read and signed** the [Contributor License Agreement for espressif/esp-idf project](https://cla-assistant.io/espressif/esp-idf). - -#### Pull request review and merge process you can expect -Espressif develops the ESP-IDF project in an internal repository (Gitlab). We do welcome contributions in the form of bug reports, feature requests and pull requests via this public GitHub repository. - -1. An internal issue has been created for the PR, we assign it to the relevant engineer -2. They review the PR and either approve it or ask you for changes or clarifications -3. Once the Github PR is approved, we synchronize it into our internal git repository -4. In the internal git repository we do the final review, collect approvals from core owners and make sure all the automated tests are passing - - At this point we may do some adjustments to the proposed change, or extend it by adding tests or documentation. -5. If the change is approved and passes the tests it is merged into the \`master\` branch -6. On next sync from the internal git repository merged change will appear in this public Github repository - -*** -`; - -/** - * Check whether the author of the pull request is known or a first-time contributor, and add a message to the PR with information about the review and merge process. - */ -export default async function (): Promise { - const contributors = await danger.github.api.repos.listContributors({ - owner: danger.github.thisPR.owner, - repo: danger.github.thisPR.repo, - }); - - const contributorsData: Contributor[] = contributors.data; - const knownContributors: (string | undefined)[] = contributorsData.map( - (contributor: Contributor) => contributor.login - ); - - if (knownContributors.includes(authorLogin)) { - return messageKnownContributor; - } else { - return messageFirstContributor; - } -} diff --git a/.github/dangerjs/prTargetBranch.ts b/.github/dangerjs/prTargetBranch.ts deleted file mode 100644 index 93b9bd81030..00000000000 --- a/.github/dangerjs/prTargetBranch.ts +++ /dev/null @@ -1,19 +0,0 @@ -import { DangerDSLType, DangerResults } from "danger"; -declare const danger: DangerDSLType; -declare const fail: (message: string, results?: DangerResults) => void; - -/** - * Check if the target branch is "master" - * - * @dangerjs FAIL - */ -export default function (): void { - const prTargetBranch: string = danger.github?.pr?.base?.ref; - - if (prTargetBranch !== "master") { - return fail(` - The target branch for this pull request should be \`master\`.\n - If you would like to add this feature to the release branch, please state this in the PR description and we will consider backporting it. - `); - } -} diff --git a/.github/dangerjs/tsconfig.json b/.github/dangerjs/tsconfig.json deleted file mode 100644 index d09fc72a690..00000000000 --- a/.github/dangerjs/tsconfig.json +++ /dev/null @@ -1,17 +0,0 @@ -{ - "compilerOptions": { - "module": "commonjs", - "moduleResolution": "node", - "esModuleInterop": true, - "target": "es6", - "noImplicitAny": true, - "noUnusedParameters": true, - "strictNullChecks": true, - "sourceMap": true, - "removeComments": true, - "outDir": "./dist" - }, - "include": [ - "./*.ts" - ] -} diff --git a/.github/dependabot.yml b/.github/dependabot.yml deleted file mode 100644 index a34982945ac..00000000000 --- a/.github/dependabot.yml +++ /dev/null @@ -1,15 +0,0 @@ -version: 2 -updates: - - package-ecosystem: "all" - directory: "/" - schedule: - interval: "weekly" - ignore: - - directory: ".gitlab/dangerjs" - patterns: - - "package-lock.json" - - directory: ".github/dangerjs" - patterns: - - "package-lock.json" - # Disable "version updates" (keep only "security updates") - open-pull-requests-limit: 0 diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml index b2c078ae1dd..07871a79a9a 100644 --- a/.github/workflows/dangerjs.yml +++ b/.github/workflows/dangerjs.yml @@ -9,28 +9,19 @@ permissions: contents: write jobs: - danger-check: + pull-request-style-linter: runs-on: ubuntu-latest - defaults: - run: - working-directory: .github/dangerjs steps: - name: Check out PR head - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: ref: ${{ github.event.pull_request.head.sha }} - - name: Setup NodeJS environment - uses: actions/setup-node@v3 - with: - node-version: 18 - cache: npm - cache-dependency-path: .github/dangerjs/package-lock.json - - - name: Install DangerJS dependencies - run: npm install - - - name: Run DangerJS - run: npx danger ci --failOnErrors -v + - name: DangerJS pull request linter + uses: espressif/shared-github-dangerjs@v1 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + instructions-gitlab-mirror: 'true' + instructions-contributions-file: 'CONTRIBUTING.md' + instructions-cla-link: 'https://cla-assistant.io/espressif/esp-idf' diff --git a/.github/workflows/vulnerability_scan.yml b/.github/workflows/vulnerability_scan.yml new file mode 100644 index 00000000000..fe775576e5a --- /dev/null +++ b/.github/workflows/vulnerability_scan.yml @@ -0,0 +1,34 @@ +name: Vulnerability scan + +on: + schedule: + - cron: '0 0 * * *' + workflow_dispatch: + +jobs: + vulnerability-scan: + strategy: + # We don't want to run all jobs in parallel, because this would + # overload NVD and we would get 503 + max-parallel: 1 + matrix: + # References/branches which should be scanned for vulnerabilities are + # defined in the VULNERABILITY_SCAN_REFS variable as json list. + # For example: ['master', 'release/v5.2', 'release/v5.1', 'release/v5.0', 'release/v4.4'] + ref: ${{ fromJSON(vars.VULNERABILITY_SCAN_REFS) }} + name: Vulnerability scan + runs-on: ubuntu-latest + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + submodules: recursive + ref: ${{ matrix.ref }} + + - name: Vulnerability scan + env: + SBOM_MATTERMOST_WEBHOOK: ${{ secrets.SBOM_MATTERMOST_WEBHOOK }} + NVDAPIKEY: ${{ secrets.NVDAPIKEY }} + uses: espressif/esp-idf-sbom-action@master + with: + ref: ${{ matrix.ref }} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d0d8d827163..d8f4c3eadf9 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -3,8 +3,8 @@ workflow: # Disable those non-protected push triggered pipelines - if: '$CI_COMMIT_REF_NAME != "master" && $CI_COMMIT_BRANCH !~ /^release\/v/ && $CI_COMMIT_TAG !~ /^v\d+\.\d+(\.\d+)?($|-)/ && $CI_COMMIT_TAG !~ /^qa-test/ && $CI_PIPELINE_SOURCE == "push"' when: never - # when running merged result pipelines, it would create a temp commit id. use $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA instead of $CI_COMMIT_SHA. - # Please use PIPELINE_COMMIT_SHA at all places that require a commit sha + # when running merged result pipelines, CI_COMMIT_SHA represents the temp commit it created. + # Please use PIPELINE_COMMIT_SHA at all places that require a commit sha of the original commit. - if: $CI_OPEN_MERGE_REQUESTS != null variables: PIPELINE_COMMIT_SHA: $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA @@ -18,6 +18,7 @@ workflow: # Place the default settings in `.gitlab/ci/common.yml` instead include: + - '.gitlab/ci/danger.yml' - '.gitlab/ci/common.yml' - '.gitlab/ci/rules.yml' - '.gitlab/ci/upload_cache.yml' diff --git a/.gitlab/CODEOWNERS b/.gitlab/CODEOWNERS index 17ea1094728..4cc21ca35c8 100644 --- a/.gitlab/CODEOWNERS +++ b/.gitlab/CODEOWNERS @@ -47,12 +47,9 @@ * @esp-idf-codeowners/other /.* @esp-idf-codeowners/tools -/.github/dangerjs/ @esp-idf-codeowners/ci @esp-idf-codeowners/tools -/.github/dependabot.yml @esp-idf-codeowners/ci /.github/workflows/ @esp-idf-codeowners/ci /.gitlab-ci.yml @esp-idf-codeowners/ci /.gitlab/ci/ @esp-idf-codeowners/ci -/.gitlab/dangerjs/ @esp-idf-codeowners/ci @esp-idf-codeowners/tools /.pre-commit-config.yaml @esp-idf-codeowners/ci /.readthedocs.yml @esp-idf-codeowners/docs /.vale.ini @esp-idf-codeowners/docs @@ -88,6 +85,7 @@ /components/esp_coex/ @esp-idf-codeowners/wifi @esp-idf-codeowners/bluetooth @esp-idf-codeowners/ieee802154 /components/esp_common/ @esp-idf-codeowners/system /components/esp_driver_*/ @esp-idf-codeowners/peripherals +/components/esp_driver_sdmmc/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/storage /components/esp_eth/ @esp-idf-codeowners/network /components/esp_event/ @esp-idf-codeowners/system /components/esp_gdbstub/ @esp-idf-codeowners/debugging diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index be1761cb155..b58a008f392 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -21,8 +21,7 @@ needs: - job: fast_template_app artifacts: false - - job: mr_variables - optional: true # only MR pipelines would have this + - pipeline_variables artifacts: paths: # The other artifacts patterns are defined under tools/ci/artifacts_handler.py @@ -46,8 +45,8 @@ examples/bluetooth/esp_ble_mesh/ble_mesh_console examples/bluetooth/hci/controller_hci_uart_esp32 examples/wifi/iperf - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} # for detailed documents, please refer to .gitlab/ci/README.md#uploaddownload-artifacts-to-internal-minio-server - python tools/ci/artifacts_handler.py upload @@ -65,8 +64,8 @@ --copy-sdkconfig --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} $TEST_BUILD_OPTS_EXTRA - python tools/ci/artifacts_handler.py upload @@ -82,8 +81,8 @@ --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt" - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - python tools/ci/artifacts_handler.py upload .build_pytest_no_jtag_template: @@ -98,8 +97,8 @@ --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt" - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - python tools/ci/artifacts_handler.py upload .build_pytest_jtag_template: @@ -114,8 +113,8 @@ --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt" - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - python tools/ci/artifacts_handler.py upload build_pytest_examples_esp32: @@ -264,8 +263,8 @@ build_only_components_apps: -t all --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - python tools/ci/artifacts_handler.py upload build_pytest_test_apps_esp32: @@ -336,8 +335,8 @@ build_only_tools_test_apps: -t all --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - python tools/ci/artifacts_handler.py upload .build_template_app_template: @@ -551,6 +550,38 @@ pytest_build_system_macos: reports: junit: XUNIT_RESULT.xml +.test_build_system_template_win: + stage: host_test + variables: + # Enable ccache for all build jobs. See configure_ci_environment.sh for more ccache related settings. + IDF_CCACHE_ENABLE: "1" + PYTHONPATH: "$PYTHONPATH;$IDF_PATH\\tools;$IDF_PATH\\tools\\esp_app_trace;$IDF_PATH\\components\\partition_table;$IDF_PATH\\tools\\ci\\python_packages" + before_script: [] + after_script: [] + timeout: 4 hours + script: + - .\install.ps1 --enable-ci --enable-pytest + - . .\export.ps1 + - python "${SUBMODULE_FETCH_TOOL}" -s "all" + - cd ${IDF_PATH}\tools\test_build_system + - pytest --junitxml=${CI_PROJECT_DIR}\XUNIT_RESULT.xml + +pytest_build_system_win: + extends: + - .test_build_system_template_win + - .rules:labels:windows_pytest_build_system + needs: [] + tags: + - windows-target + artifacts: + paths: + - XUNIT_RESULT.xml + - test_build_system + when: always + expire_in: 2 days + reports: + junit: XUNIT_RESULT.xml + build_docker: extends: - .before_script:minimal diff --git a/.gitlab/ci/common.yml b/.gitlab/ci/common.yml index fbecbacab89..e8583318981 100644 --- a/.gitlab/ci/common.yml +++ b/.gitlab/ci/common.yml @@ -21,15 +21,20 @@ variables: # GitLab-CI environment - # XXX_ATTEMPTS variables (https://docs.gitlab.com/ee/ci/runners/configure_runners.html#job-stages-attempts) are not defined here. - # Use values from "CI / CD Settings" - "Variables". - - # GIT_STRATEGY is not defined here. - # Use an option from "CI / CD Settings" - "General pipelines". - + # now we have pack-objects cache, so clone strategy is faster than fetch + GIT_STRATEGY: clone # we will download archive for each submodule instead of clone. # we don't do "recursive" when fetch submodule as they're not used in CI now. GIT_SUBMODULE_STRATEGY: none + # since we're using merged-result pipelines, the last commit should work for most cases + GIT_DEPTH: 1 + # --no-recurse-submodules: we use cache for submodules + # --prune --prune-tags: in case remote branch or tag is force pushed + GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags" + # we're using .cache folder for caches + GIT_CLEAN_FLAGS: -ffdx -e .cache/ + LATEST_GIT_TAG: v5.3-dev + SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py" # by default we will fetch all submodules # jobs can overwrite this variable to only fetch submodules they required @@ -39,20 +44,16 @@ variables: IDF_SKIP_CHECK_SUBMODULES: 1 IDF_PATH: "$CI_PROJECT_DIR" - BATCH_BUILD: "1" V: "0" CHECKOUT_REF_SCRIPT: "$CI_PROJECT_DIR/tools/ci/checkout_project_ref.py" PYTHON_VER: 3.8.17 # Docker images - ESP_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-env-v5.3:1" - ESP_IDF_DOC_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-idf-doc-env-v5.3:1-1" - QEMU_IMAGE: "${CI_DOCKER_REGISTRY}/qemu-v5.3:1-20230522" - TARGET_TEST_ENV_IMAGE: "$CI_DOCKER_REGISTRY/target-test-env-v5.3:1" - + ESP_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-env-v5.3:1" + ESP_IDF_DOC_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-doc-env-v5.3:1-1" + TARGET_TEST_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/target-test-env-v5.3:1" SONARQUBE_SCANNER_IMAGE: "${CI_DOCKER_REGISTRY}/sonarqube-scanner:5" - - PRE_COMMIT_IMAGE: "$CI_DOCKER_REGISTRY/esp-idf-pre-commit:1" + PRE_COMMIT_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-pre-commit:1" # target test repo parameters TEST_ENV_CONFIG_REPO: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/qa/ci-test-runner-configs.git" @@ -138,6 +139,15 @@ variables: $IDF_PATH/tools/idf_tools.py --non-interactive install esp-clang fi + # Install QEMU if necessary + if [[ ! -z "$INSTALL_QEMU" ]]; then + $IDF_PATH/tools/idf_tools.py --non-interactive install qemu-xtensa qemu-riscv32 + fi + + # Since the version 3.21 CMake passes source files and include dirs to ninja using absolute paths. + # Needed for pytest junit reports. + $IDF_PATH/tools/idf_tools.py --non-interactive install cmake + source ./export.sh # Custom clang @@ -170,10 +180,9 @@ variables: test "$CI_CCACHE_STATS" == 1 && test -n "$(which ccache)" && ccache --show-stats || true .upload_failed_job_log_artifacts: &upload_failed_job_log_artifacts | - - | - if [ $CI_JOB_STATUS = "failed" ]; then - python tools/ci/artifacts_handler.py upload --type logs - fi + if [ $CI_JOB_STATUS = "failed" ]; then + python tools/ci/artifacts_handler.py upload --type logs + fi .before_script:minimal: before_script: @@ -203,6 +212,116 @@ variables: - *show_ccache_statistics - *upload_failed_job_log_artifacts +############################## +# Git Strategy Job Templates # +############################## +.git_init: &git_init | + mkdir -p "${CI_PROJECT_DIR}" + cd "${CI_PROJECT_DIR}" + git init + +.git_fetch_from_mirror_url_if_exists: &git_fetch_from_mirror_url_if_exists | + # check if set mirror + if [ -n "${LOCAL_GITLAB_HTTPS_HOST:-}" ] && [ -n "${ESPCI_TOKEN:-}" ]; then + MIRROR_REPO_URL="https://bot:${ESPCI_TOKEN}@${LOCAL_GITLAB_HTTPS_HOST}/${CI_PROJECT_PATH}" + elif [ -n "${LOCAL_GIT_MIRROR:-}" ]; then + MIRROR_REPO_URL="${LOCAL_GIT_MIRROR}/${CI_PROJECT_PATH}" + fi + + # fetch from mirror first if set + if [ -n "${MIRROR_REPO_URL:-}" ]; then + if git remote -v | grep origin; then + git remote set-url origin "${MIRROR_REPO_URL}" + else + git remote add origin "${MIRROR_REPO_URL}" + fi + # mirror url may fail with authentication issue + git fetch origin --no-recurse-submodules || true + fi + + # set remote url to CI_REPOSITORY_URL + if git remote -v | grep origin; then + git remote set-url origin "${CI_REPOSITORY_URL}" + else + git remote add origin "${CI_REPOSITORY_URL}" + fi + +.git_checkout_fetch_head: &git_checkout_fetch_head | + git checkout FETCH_HEAD + git clean ${GIT_CLEAN_FLAGS} + +# git diff requires two commits, with different CI env var +# +# By default, we use git strategy "clone" with depth 1 to speed up the clone process. +# But for jobs requires running `git diff`, we need to fetch more commits to get the correct diffs. +# +# Since there's no way to get the correct git_depth before the job starts, +# we can't set `GIT_DEPTH` in the job definition. +# +# Set git strategy to "none" and fetch manually instead. +.before_script:fetch:git_diff: + variables: + GIT_STRATEGY: none + before_script: + - *git_init + - *git_fetch_from_mirror_url_if_exists + - | + # merged results pipelines, by default + if [[ -n $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA ]]; then + git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + git fetch origin $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_MERGE_REQUEST_DIFF_BASE_SHA $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA) + # merge request pipelines, when the mr got conflicts + elif [[ -n $CI_MERGE_REQUEST_DIFF_BASE_SHA ]]; then + git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + git fetch origin $CI_COMMIT_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_MERGE_REQUEST_DIFF_BASE_SHA $CI_COMMIT_SHA) + # other pipelines, like the protected branches pipelines + elif [[ "$CI_COMMIT_BEFORE_SHA" != "0000000000000000000000000000000000000000" ]]; then + git fetch origin $CI_COMMIT_BEFORE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + git fetch origin $CI_COMMIT_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_COMMIT_BEFORE_SHA $CI_COMMIT_SHA) + else + # pipeline source could be web, scheduler, etc. + git fetch origin $CI_COMMIT_SHA --depth=2 ${GIT_FETCH_EXTRA_FLAGS} + export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_COMMIT_SHA~1 $CI_COMMIT_SHA) + fi + - *git_checkout_fetch_head + - *common-before_scripts + - *setup_tools_and_idf_python_venv + - add_gitlab_ssh_keys + +# git describe requires commit history until the latest tag +.before_script:fetch:git_describe: + variables: + GIT_STRAEGY: none + before_script: + - *git_init + - *git_fetch_from_mirror_url_if_exists + - | + git fetch origin refs/tags/"${LATEST_GIT_TAG}":refs/tags/"${LATEST_GIT_TAG}" --depth=1 + git repack -d + git fetch origin $CI_COMMIT_SHA --shallow-since=$(git log -1 --format=%as "${LATEST_GIT_TAG}") + - *git_checkout_fetch_head + - *common-before_scripts + - *setup_tools_and_idf_python_venv + - add_gitlab_ssh_keys + +# target test runners may locate in different places +# for runners set git mirror, we fetch from the mirror first, then fetch the HEAD commit +.before_script:fetch:target_test: + variables: + GIT_STRATEGY: none + before_script: + - *git_init + - *git_fetch_from_mirror_url_if_exists + - git fetch origin "${CI_COMMIT_SHA}" --depth=1 ${GIT_FETCH_EXTRA_FLAGS} + - *git_checkout_fetch_head + - *common-before_scripts + - *setup_tools_and_idf_python_venv + - add_gitlab_ssh_keys + # no submodules + ############# # `default` # ############# @@ -210,11 +329,15 @@ default: cache: # pull only for most of the use cases since it's cache dir. # Only set "push" policy for "upload_cache" stage jobs - - key: pip-cache + - key: pip-cache-${LATEST_GIT_TAG} + fallback_keys: + - pip-cache paths: - .cache/pip policy: pull - - key: submodule-cache + - key: submodule-cache-${LATEST_GIT_TAG} + fallback_keys: + - submodule-cache paths: - .cache/submodule_archives policy: pull diff --git a/.gitlab/ci/danger.yml b/.gitlab/ci/danger.yml new file mode 100644 index 00000000000..1775d5f8c65 --- /dev/null +++ b/.gitlab/ci/danger.yml @@ -0,0 +1,18 @@ +# Extenal DangerJS +include: + - project: espressif/shared-ci-dangerjs + ref: master + file: danger.yaml + +run-danger-mr-linter: + stage: pre_check + variables: + GIT_STRATEGY: none # no repo checkout + ENABLE_CHECK_AREA_LABELS: 'true' + ENABLE_CHECK_DOCS_TRANSLATION: 'true' + ENABLE_CHECK_RELEASE_NOTES_DESCRIPTION: 'true' + ENABLE_CHECK_UPDATED_CHANGELOG: 'false' + before_script: [] + cache: [] + tags: + - dangerjs diff --git a/.gitlab/ci/dependencies/dependencies.yml b/.gitlab/ci/dependencies/dependencies.yml index 5905f5be9fb..217e701db58 100644 --- a/.gitlab/ci/dependencies/dependencies.yml +++ b/.gitlab/ci/dependencies/dependencies.yml @@ -181,3 +181,9 @@ "labels:nvs_coverage": # host_test labels: - nvs_coverage + +"labels:windows_pytest_build_system": + labels: + - windows + specific_rules: + - if-schedule-test-build-system-windows diff --git a/.gitlab/ci/deploy.yml b/.gitlab/ci/deploy.yml index c059ce88dd7..1df1004ee82 100644 --- a/.gitlab/ci/deploy.yml +++ b/.gitlab/ci/deploy.yml @@ -1,8 +1,7 @@ .deploy_job_template: stage: deploy image: $ESP_ENV_IMAGE - tags: - - deploy + tags: [ deploy ] # Check this before push_to_github check_submodule_sync: @@ -10,11 +9,11 @@ check_submodule_sync: - .deploy_job_template - .rules:test:submodule stage: test_deploy - tags: - - github_sync + tags: [ brew, github_sync ] retry: 2 variables: - GIT_STRATEGY: clone + # for brew runners, we always set GIT_STRATEGY to fetch + GIT_STRATEGY: fetch SUBMODULES_TO_FETCH: "none" PUBLIC_IDF_URL: "https://github.com/espressif/esp-idf.git" dependencies: [] @@ -35,6 +34,12 @@ push_to_github: - .rules:push_to_github needs: - check_submodule_sync + tags: [ brew, github_sync ] + variables: + # for brew runners, we always set GIT_STRATEGY to fetch + GIT_STRATEGY: fetch + # github also need full record of commits + GIT_DEPTH: 0 script: - add_github_ssh_keys - git remote remove github &>/dev/null || true @@ -47,6 +52,9 @@ deploy_update_SHA_in_esp-dockerfiles: - .before_script:minimal - .rules:protected-no_label-always dependencies: [] + variables: + GIT_DEPTH: 2 + tags: [ shiny, build ] script: - 'curl --header "PRIVATE-TOKEN: ${ESPCI_SCRIPTS_TOKEN}" -o create_MR_in_esp_dockerfile.sh $GITLAB_HTTP_SERVER/api/v4/projects/1260/repository/files/create_MR_in_esp_dockerfile%2Fcreate_MR_in_esp_dockerfile.sh/raw\?ref\=master' - chmod +x create_MR_in_esp_dockerfile.sh diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml index 95141ffdb94..6e77737a365 100644 --- a/.gitlab/ci/docs.yml +++ b/.gitlab/ci/docs.yml @@ -93,6 +93,7 @@ check_docs_lang_sync: tags: - build_docs script: + - if [ -n "${BREATHE_ALT_INSTALL_URL}" ]; then pip uninstall -y breathe && pip install -U ${BREATHE_ALT_INSTALL_URL}; fi - cd docs - build-docs -t $DOCTGT -bs $DOC_BUILDERS -l $DOCLANG build parallel: diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml index f4911dfebaf..ab1d62e588e 100644 --- a/.gitlab/ci/host-test.yml +++ b/.gitlab/ci/host-test.yml @@ -13,8 +13,7 @@ - job: upload-submodules-cache optional: true artifacts: false - - job: mr_variables - optional: true # only MR pipelines would have this + - pipeline_variables test_nvs_on_host: extends: .host_test_template @@ -100,18 +99,9 @@ test_gdbstub_on_host: - cd components/esp_gdbstub/test_gdbstub_host - make test -test_idf_py: - extends: .host_test_template - variables: - LC_ALL: C.UTF-8 - script: - - cd ${IDF_PATH}/tools/test_idf_py - - ./test_idf_py.py - - ./test_hints.py - # Test for create virtualenv. It must be invoked from Python, not from virtualenv. # Use docker image system python without any extra dependencies -test_idf_tools: +test_cli_installer: extends: - .host_test_template - .before_script:minimal @@ -200,45 +190,39 @@ test_sysviewtrace_proc: - cd ${IDF_PATH}/tools/esp_app_trace/test/sysview - ./test.sh -test_mkdfu: - extends: .host_test_template - variables: - LC_ALL: C.UTF-8 - script: - - cd ${IDF_PATH}/tools/test_mkdfu - - ./test_mkdfu.py - -test_sbom: - extends: - - .host_test_template - - .rules:patterns:sbom - script: - - cd ${IDF_PATH}/tools/test_sbom - - pytest - -test_autocomplete: +test_tools: extends: - .host_test_template artifacts: - when: on_failure + when: always paths: - ${IDF_PATH}/*.out + - ${IDF_PATH}/XUNIT_*.xml + reports: + junit: ${IDF_PATH}/XUNIT_*.xml expire_in: 1 week + variables: + LC_ALL: C.UTF-8 + INSTALL_QEMU: 1 # for test_idf_qemu.py script: - - ${IDF_PATH}/tools/ci/test_autocomplete.py - -test_detect_python: - extends: - - .host_test_template - script: + - stat=0 + - cd ${IDF_PATH}/tools/ci/test_autocomplete + - pytest --noconftest test_autocomplete.py --junitxml=${IDF_PATH}/XUNIT_AUTOCOMP.xml || stat=1 + - cd ${IDF_PATH}/tools/test_idf_py + - pytest --noconftest test_idf_py.py --junitxml=${IDF_PATH}/XUNIT_IDF_PY.xml || stat=1 + - pytest --noconftest test_hints.py --junitxml=${IDF_PATH}/XUNIT_HINTS.xml || stat=1 + - pytest --noconftest test_idf_qemu.py --junitxml=${IDF_PATH}/XUNIT_IDF_PY_QEMU.xml || stat=1 + - cd ${IDF_PATH}/tools/test_mkdfu + - pytest --noconftest test_mkdfu.py --junitxml=${IDF_PATH}/XUNIT_MKDFU.xml || stat=1 - cd ${IDF_PATH} - - shellcheck -s sh tools/detect_python.sh - - shellcheck -s bash tools/detect_python.sh - - shellcheck -s dash tools/detect_python.sh + - shellcheck -s sh tools/detect_python.sh || stat=1 + - shellcheck -s bash tools/detect_python.sh || stat=1 + - shellcheck -s dash tools/detect_python.sh || stat=1 - "bash -c '. tools/detect_python.sh && echo Our Python: ${ESP_PYTHON?Python is not set}'" - "dash -c '. tools/detect_python.sh && echo Our Python: ${ESP_PYTHON?Python is not set}'" - "zsh -c '. tools/detect_python.sh && echo Our Python: ${ESP_PYTHON?Python is not set}'" - "fish -c 'source tools/detect_python.fish && echo Our Python: $ESP_PYTHON'" + - exit "$stat" test_split_path_by_spaces: extends: .host_test_template @@ -295,7 +279,6 @@ test_pytest_qemu: extends: - .host_test_template - .before_script:build - image: $QEMU_IMAGE artifacts: when: always paths: @@ -308,14 +291,16 @@ test_pytest_qemu: parallel: matrix: - IDF_TARGET: [esp32, esp32c3] + variables: + INSTALL_QEMU: 1 script: - run_cmd python tools/ci/ci_build_apps.py . -vv --target $IDF_TARGET --pytest-apps -m qemu --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt" - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - retry_failed git clone $KNOWN_FAILURE_CASES_REPO known_failure_cases - run_cmd pytest --target $IDF_TARGET @@ -324,6 +309,7 @@ test_pytest_qemu: --junitxml=XUNIT_RESULT.xml --ignore-result-files known_failure_cases/known_failure_cases.txt --app-info-filepattern \"list_job_*.txt\" + --qemu-extra-args \"-global driver=timer.$IDF_TARGET.timg,property=wdt_disable,value=true\" test_pytest_linux: extends: @@ -344,8 +330,8 @@ test_pytest_linux: --pytest-apps -m host_test --collect-app-info "list_job_${CI_JOB_NAME_SLUG}.txt" - --modified-components ${MR_MODIFIED_COMPONENTS} - --modified-files ${MR_MODIFIED_FILES} + --modified-components ${MODIFIED_COMPONENTS} + --modified-files ${MODIFIED_FILES} - retry_failed git clone $KNOWN_FAILURE_CASES_REPO known_failure_cases - run_cmd pytest --target linux diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index 4fba65c59ec..b4a96cf73c1 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -5,54 +5,16 @@ - host_test dependencies: [] -.check_pre_commit_template: +check_pre_commit: extends: - .pre_check_template - .before_script:minimal image: $PRE_COMMIT_IMAGE - -check_pre_commit_master_release: - extends: - - .check_pre_commit_template - - .rules:protected - script: - - fetch_submodules - - git diff-tree --no-commit-id --name-only -r $PIPELINE_COMMIT_SHA | xargs pre-commit run --files - -check_pre_commit_MR: - extends: - - .check_pre_commit_template - - .rules:mr + needs: + - pipeline_variables script: - fetch_submodules - - python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py files ${CI_MERGE_REQUEST_SOURCE_BRANCH_NAME} | xargs pre-commit run --files - -check_MR_style_dangerjs: - extends: - - .pre_check_template - image: node:18.15.0-alpine3.16 - variables: - DANGER_GITLAB_API_TOKEN: ${ESPCI_TOKEN} - DANGER_GITLAB_HOST: ${GITLAB_HTTP_SERVER} - DANGER_GITLAB_API_BASE_URL: ${GITLAB_HTTP_SERVER}/api/v4 - DANGER_JIRA_USER: ${DANGER_JIRA_USER} - DANGER_JIRA_PASSWORD: ${DANGER_JIRA_PASSWORD} - cache: - # pull only for most of the use cases since it's cache dir. - # Only set "push" policy for "upload_cache" stage jobs - key: - files: - - .gitlab/dangerjs/package-lock.json - paths: - - .gitlab/dangerjs/node_modules/ - policy: pull - before_script: - - cd .gitlab/dangerjs - - npm install --no-progress --no-update-notifier # Install danger dependencies - script: - - npx danger ci --failOnErrors -v - rules: - - if: '$CI_PIPELINE_SOURCE == "merge_request_event"' + - pre-commit run --files $MODIFIED_FILES check_version: # Don't run this for feature/bugfix branches, so that it is possible to modify @@ -60,6 +22,7 @@ check_version: extends: - .pre_check_template - .rules:protected + - .before_script:fetch:git_describe script: - export IDF_PATH=$PWD - tools/ci/check_idf_version.sh @@ -148,10 +111,12 @@ check_esp_system: # For release tag pipelines only, make sure the tag was created with 'git tag -a' so it will update # the version returned by 'git describe' +# Don't forget to update the env var `LATEST_GIT_TAG` in .gitlab/ci/common.yml check_version_tag: extends: - .pre_check_template - .rules:tag:release + - .before_script:fetch:git_describe script: - (git cat-file -t $CI_COMMIT_REF_NAME | grep tag) || (echo "ESP-IDF versions must be annotated tags." && exit 1) @@ -179,22 +144,23 @@ check_configure_ci_environment_parsing: - cd tools/ci - python -m unittest ci_build_apps.py -mr_variables: +pipeline_variables: extends: - .pre_check_template - - .rules:mr - - .before_script:minimal + - .before_script:fetch:git_diff tags: - build script: - - echo "MR_MODIFIED_FILES=$(python tools/ci/ci_get_mr_info.py files ${CI_MERGE_REQUEST_SOURCE_BRANCH_NAME} | xargs)" >> mr.env - - echo "MR_MODIFIED_COMPONENTS=$(python tools/ci/ci_get_mr_info.py components ${CI_MERGE_REQUEST_SOURCE_BRANCH_NAME} | xargs)" >> mr.env - - > + - MODIFIED_FILES=$(echo $GIT_DIFF_OUTPUT | xargs) + - echo "MODIFIED_FILES=$MODIFIED_FILES" >> pipeline.env + - echo "MODIFIED_COMPONENTS=$(run_cmd python tools/ci/ci_get_mr_info.py components --modified-files $MODIFIED_FILES | xargs)" >> pipeline.env + - | if echo "$CI_MERGE_REQUEST_LABELS" | egrep "(^|,)BUILD_AND_TEST_ALL_APPS(,|$)"; then - echo "BUILD_AND_TEST_ALL_APPS=1" >> mr.env + echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env fi - - cat mr.env + - cat pipeline.env + - python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report artifacts: reports: - dotenv: mr.env + dotenv: pipeline.env expire_in: 4 days diff --git a/.gitlab/ci/rules.yml b/.gitlab/ci/rules.yml index 9202f59ddc0..589a89528ff 100644 --- a/.gitlab/ci/rules.yml +++ b/.gitlab/ci/rules.yml @@ -67,9 +67,6 @@ - "tools/ci/ci_build_apps.py" - "tools/test_build_system/**/*" -.patterns-sbom: &patterns-sbom - - "tools/test_sbom/*" - .patterns-custom_test: &patterns-custom_test - "tools/ci/idf_pytest/**/*" - "tools/ci/python_packages/gitlab_api.py" @@ -129,7 +126,7 @@ - "components/**/*" - - "tools/ci/test_autocomplete.py" + - "tools/ci/test_autocomplete/*" - "tools/mass_mfg/**/*" @@ -197,11 +194,9 @@ - "components/unity/unity" - "components/heap/tlsf" - "components/bt/controller/lib_esp32c6/esp32c6-bt-lib" + - "components/bt/esp_ble_mesh/lib/lib" - ".gitmodules" -.patterns-danger-npm: &patterns-danger-npm - - ".gitlab/dangerjs/package-lock.json" - # for jobs: flash_encryption_wifi_high_traffic .patterns-example_test-ota-nightly_run: &patterns-example_test-ota-nightly_run - "examples/system/ota/**/*" @@ -242,31 +237,31 @@ .patterns-custom_test-wifi: &patterns-custom_test-wifi - "tools/test_apps/phy/**/*" -# for jobs: example_test_pytest_sdio related +# for jobs: SDIO related example_test .patterns-example_test-sdio: &patterns-example_test-sdio - "components/hal/sdio*.c" - "components/hal/include/hal/sdio*.h" - - "components/driver/sdspi*.c" - - "components/driver/sdio*.c" - - "components/driver/sdmmc*.c" - - "components/driver/include/driver/sdspi*.h" - - "components/driver/include/driver/sdio*.h" - - "components/driver/include/driver/sdmmc*.h" + - "components/esp_driver_sdspi/src/sdspi*.c" + - "components/esp_driver_sdio/src/sdio*.c" + - "components/esp_driver_sdmmc/src/sdmmc*.c" + - "components/esp_driver_sdspi/include/driver/sdspi*.h" + - "components/esp_driver_sdio/include/driver/sdio*.h" + - "components/esp_driver_sdmmc/include/driver/sdmmc*.h" - "components/sdmmc/??[!s][!t]*/**/*" - "components/sdmmc/???/**/*" - "components/sdmmc/*" - "examples/peripherals/sdio/**/*" -# for jobs: component_ut_pytest_sdio related +# for jobs: SDIO related component_test .patterns-component_ut-sdio: &patterns-component_ut-sdio - "components/hal/sdio*.c" - "components/hal/include/hal/sdio*.h" - - "components/driver/sdspi*.c" - - "components/driver/sdio*.c" - - "components/driver/sdmmc*.c" - - "components/driver/include/driver/sdspi*.h" - - "components/driver/include/driver/sdio*.h" - - "components/driver/include/driver/sdmmc*.h" + - "components/esp_driver_sdspi/src/sdspi*.c" + - "components/esp_driver_sdio/src/sdio*.c" + - "components/esp_driver_sdmmc/src/sdmmc*.c" + - "components/esp_driver_sdspi/include/driver/sdspi*.h" + - "components/esp_driver_sdio/include/driver/sdio*.h" + - "components/esp_driver_sdmmc/include/driver/sdmmc*.h" - "components/sdmmc/**/*" # for jobs: component_ut_pytest_flash_multi @@ -339,6 +334,10 @@ .if-protected-no_label: &if-protected-no_label if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/) && $BOT_TRIGGER_WITH_LABEL == null' +.if-protected-ref-push: &if-protected-ref-push + # rules:changes always evaluates to true for new branch pipelines or when there is no Git push event + if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/) && $CI_PIPELINE_SOURCE == "push"' + .if-qa-test-tag: &if-qa-test-tag if: '$CI_COMMIT_TAG =~ /^qa-test/' @@ -351,6 +350,12 @@ .if-schedule: &if-schedule if: '$CI_PIPELINE_SOURCE == "schedule"' +.if-schedule-nightly: &if-schedule-nightly + if: '$CI_PIPELINE_SOURCE == "schedule" && $INCLUDE_NIGHTLY_RUN == "1"' + +.if-schedule-test-build-system-windows: &if-schedule-test-build-system-windows + if: '$CI_PIPELINE_SOURCE == "schedule" && $SCHEDULED_BUILD_SYSTEM_TEST_WIN == "true"' + .if-trigger: &if-trigger if: '$CI_PIPELINE_SOURCE == "trigger"' @@ -401,29 +406,26 @@ rules: - <<: *if-tag-release -### Patterns ### -.rules:patterns:python-cache: +# Do not upload caches on dev branches by default +.rules:upload-python-cache: rules: - - *if-schedule - - <<: *if-label-upload_cache - when: manual - - <<: *if-dev-push + - <<: *if-tag-release + - <<: *if-schedule-nightly + - <<: *if-protected-ref-push changes: *patterns-python-cache - -.rules:patterns:submodule: - rules: - <<: *if-label-upload_cache when: manual - - <<: *if-dev-push - changes: *patterns-submodule -.rules:patterns:dangerjs: +.rules:upload-submodule-cache: rules: + # Needn't upload submodule cache in schedule pipeline + - <<: *if-tag-release + - <<: *if-protected-ref-push + changes: *patterns-submodule - <<: *if-label-upload_cache when: manual - - <<: *if-dev-push - changes: *patterns-danger-npm +### Patterns ### .rules:patterns:clang_tidy: rules: - <<: *if-protected @@ -445,14 +447,6 @@ - <<: *if-dev-push changes: *patterns-sonarqube-files -.rules:patterns:sbom: - rules: - - <<: *if-protected - - <<: *if-dev-push - changes: *patterns-sbom - - <<: *if-dev-push - changes: *patterns-submodule - # !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! # DO NOT place comments or maintain any code from this line # @@ -570,6 +564,9 @@ .if-label-target_test: &if-label-target_test if: '$BOT_LABEL_TARGET_TEST || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*target_test(?:,[^,\n\r]+)*$/i' +.if-label-windows: &if-label-windows + if: '$BOT_LABEL_WINDOWS || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*windows(?:,[^,\n\r]+)*$/i' + .rules:build: rules: - <<: *if-revert-branch @@ -1619,6 +1616,13 @@ when: never - <<: *if-label-nvs_coverage +.rules:labels:windows_pytest_build_system: + rules: + - <<: *if-revert-branch + when: never + - <<: *if-schedule-test-build-system-windows + - <<: *if-label-windows + .rules:test:component_ut-esp32: rules: - <<: *if-revert-branch diff --git a/.gitlab/ci/static-code-analysis.yml b/.gitlab/ci/static-code-analysis.yml index 0ceb6d7ca46..2ce8a1bfc19 100644 --- a/.gitlab/ci/static-code-analysis.yml +++ b/.gitlab/ci/static-code-analysis.yml @@ -20,6 +20,8 @@ check_pylint: extends: - .pre_check_template - .rules:patterns:python-files + needs: + - pipeline_variables artifacts: when: always reports: @@ -28,7 +30,7 @@ check_pylint: script: - | if [ -n "$CI_MERGE_REQUEST_IID" ]; then - export files=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py files ${CI_MERGE_REQUEST_SOURCE_BRANCH_NAME} | grep ".py$"); + export files=$(echo $GIT_DIFF_OUTPUT | grep ".py$" | xargs); else export files=$(git ls-files "*.py" | xargs); fi @@ -82,7 +84,7 @@ code_quality_check: allow_failure: true # since now it's using exit code to indicate the code analysis result, # we don't want to block ci when critical issues founded script: - - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits ${CI_COMMIT_REF_NAME} | tr '\n' ',') + - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits --src-branch ${CI_COMMIT_REF_NAME} | tr '\n' ',') # test if this branch have merge request, if not, exit 0 - test -n "$CI_MERGE_REQUEST_IID" || exit 0 - test -n "$CI_MERGE_REQUEST_COMMITS" || exit 0 diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index 7f1ebfcc21e..8e7892eb117 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -1,14 +1,13 @@ .target_test_template: image: $TARGET_TEST_ENV_IMAGE + extends: + - .before_script:fetch:target_test stage: target_test timeout: 1 hour dependencies: [] - variables: - GIT_DEPTH: 1 - SUBMODULES_TO_FETCH: "none" cache: # Usually do not need submodule-cache in target_test - - key: pip-cache + - key: pip-cache-${LATEST_GIT_TAG} paths: - .cache/pip policy: pull @@ -230,6 +229,15 @@ pytest_examples_esp32c6_generic: artifacts: false tags: [ esp32c6, generic ] +pytest_examples_esp32c6_usj_device: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32c6 + needs: + - job: build_pytest_examples_esp32c6 + artifacts: false + tags: [ esp32c6, usj_device ] + pytest_examples_esp32h2_generic: extends: - .pytest_examples_dir_template @@ -716,6 +724,24 @@ pytest_components_esp32_adc: artifacts: false tags: [ esp32, adc ] +pytest_components_esp32_sdmmc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - job: build_pytest_components_esp32 + artifacts: false + tags: [ esp32, sdcard ] + +pytest_components_esp32s3_sdmmc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s3 + needs: + - job: build_pytest_components_esp32s3 + artifacts: false + tags: [ esp32s3, sdcard ] + pytest_components_esp32_sdio: extends: - .pytest_components_dir_template @@ -725,6 +751,37 @@ pytest_components_esp32_sdio: artifacts: false tags: [ esp32, sdio_master_slave ] +pytest_components_esp32_esp32c6_sdio: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32-sdio + needs: + - job: build_pytest_components_esp32 + artifacts: false + - job: build_pytest_components_esp32c6 + artifacts: false + tags: [ esp32c6, sdio_multidev_32_c6 ] + script: + - retry_failed git clone $KNOWN_FAILURE_CASES_REPO known_failure_cases + # get runner env config file + - retry_failed git clone $TEST_ENV_CONFIG_REPO + - python $CHECKOUT_REF_SCRIPT ci-test-runner-configs ci-test-runner-configs + # using runner tags as markers to filter the test cases + # Runner tags are comma separated, replace the comma with " and " for markers + - job_tags=$(python tools/ci/python_packages/gitlab_api.py get_job_tags $CI_PROJECT_ID --job_id $CI_JOB_ID) + - markers=$(echo $job_tags | sed -e "s/,/ and /g") + # download the artifacts, requires esp32 and esp32c6 chips + - run_cmd python tools/ci/artifacts_handler.py download --job-name "build_pytest_components_esp32" + - run_cmd python tools/ci/artifacts_handler.py download --job-name "build_pytest_components_esp32c6" + - run_cmd pytest $TEST_DIR + -m \"${markers}\" + --junitxml=XUNIT_RESULT.xml + --ignore-result-files known_failure_cases/known_failure_cases.txt + --parallel-count ${CI_NODE_TOTAL:-1} + --parallel-index ${CI_NODE_INDEX:-1} + ${PYTEST_EXTRA_FLAGS} + --app-info-filepattern \"list_job_*.txt\" + pytest_components_esp32_ip101: extends: - .pytest_components_dir_template @@ -1141,15 +1198,6 @@ pytest_components_esp32c3_flash_multi: artifacts: false tags: [ esp32c3, flash_multi ] -pytest_components_esp32_sdmmc: - extends: - - .pytest_components_dir_template - - .rules:test:component_ut-esp32 - needs: - - job: build_pytest_components_esp32 - artifacts: false - tags: [ esp32, sdcard_sdmode ] - pytest_components_esp32_sdspi: extends: - .pytest_components_dir_template diff --git a/.gitlab/ci/upload_cache.yml b/.gitlab/ci/upload_cache.yml index c523078be9e..173b63224b4 100644 --- a/.gitlab/ci/upload_cache.yml +++ b/.gitlab/ci/upload_cache.yml @@ -10,12 +10,12 @@ upload-pip-cache: extends: - .upload_cache_template - .before_script:minimal - - .rules:patterns:python-cache + - .rules:upload-python-cache tags: - $GEO - cache cache: - key: pip-cache + key: pip-cache-${LATEST_GIT_TAG} paths: - .cache/pip policy: push @@ -30,12 +30,12 @@ upload-submodules-cache: extends: - .upload_cache_template - .before_script:minimal - - .rules:patterns:submodule + - .rules:upload-submodule-cache tags: - $GEO - cache cache: - key: submodule-cache + key: submodule-cache-${LATEST_GIT_TAG} paths: - .cache/submodule_archives policy: push @@ -48,27 +48,3 @@ upload-submodules-cache: parallel: matrix: - GEO: [ 'shiny', 'brew' ] - -upload-danger-npm-cache: - stage: upload_cache - image: node:18.15.0-alpine3.16 - extends: - - .rules:patterns:dangerjs - tags: - - $GEO - - cache - cache: - key: - files: - - .gitlab/dangerjs/package-lock.json - paths: - - .gitlab/dangerjs/node_modules/ - policy: push - before_script: - - echo "Skip before scripts ...." - script: - - cd .gitlab/dangerjs - - npm install --no-progress --no-update-notifier - parallel: - matrix: - - GEO: [ 'shiny', 'brew' ] diff --git a/.gitlab/dangerjs/aiGenerateGitMessage.js b/.gitlab/dangerjs/aiGenerateGitMessage.js deleted file mode 100644 index 1ce39d03510..00000000000 --- a/.gitlab/dangerjs/aiGenerateGitMessage.js +++ /dev/null @@ -1,172 +0,0 @@ -const { - minimumSummaryChars, - maximumSummaryChars, - maximumBodyLineChars, - allowedTypes, -} = require("./mrCommitsConstants.js"); -const { gptStandardModelTokens } = require("./mrCommitsConstants.js"); - -const { ChatPromptTemplate } = require("langchain/prompts"); -const { SystemMessagePromptTemplate } = require("langchain/prompts"); -const { LLMChain } = require("langchain/chains"); -const { ChatOpenAI } = require("langchain/chat_models/openai"); -const openAiTokenCount = require("openai-gpt-token-counter"); - -module.exports = async function () { - let outputDangerMessage = `\n\nPerhaps you could use an AI-generated suggestion for your commit message. Here is one `; - - let mrDiff = await getMrGitDiff(danger.git.modified_files); - const mrCommitMessages = getCommitMessages(danger.gitlab.commits); - const inputPrompt = getInputPrompt(); - const inputLlmTokens = getInputLlmTokens( - inputPrompt, - mrDiff, - mrCommitMessages - ); - console.log(`Input tokens for LLM: ${inputLlmTokens}`); - - if (inputLlmTokens >= gptStandardModelTokens) { - mrDiff = ""; // If the input mrDiff is larger than 16k model, don't use mrDiff, use only current commit messages - outputDangerMessage += `(based only on your current commit messages, git-diff of this MR is too big (${inputLlmTokens} tokens) for the AI models):\n\n`; - } else { - outputDangerMessage += `(based on your MR git-diff and your current commit messages):\n\n`; - } - - // Generate AI commit message - let generatedCommitMessage = ""; - try { - const rawCommitMessage = await createAiGitMessage( - inputPrompt, - mrDiff, - mrCommitMessages - ); - generatedCommitMessage = postProcessCommitMessage(rawCommitMessage); - } catch (error) { - console.error("Error in generating AI commit message: ", error); - outputDangerMessage += - "\nCould not generate commit message due to an error.\n"; - } - - // Append closing statements ("Closes https://github.com/espressif/esp-idf/issues/XXX") to the generated commit message - let closingStatements = extractClosingStatements(mrCommitMessages); - if (closingStatements.length > 0) { - generatedCommitMessage += "\n\n" + closingStatements; - } - - // Add the generated git message, format to the markdown code block - outputDangerMessage += `\n\`\`\`\n${generatedCommitMessage}\n\`\`\`\n`; - outputDangerMessage += - "\n**NOTE: AI-generated suggestions may not always be correct, please review the suggestion before using it.**"; // Add disclaimer - return outputDangerMessage; -}; - -async function getMrGitDiff(mrModifiedFiles) { - const fileDiffs = await Promise.all( - mrModifiedFiles.map((file) => danger.git.diffForFile(file)) - ); - return fileDiffs.map((fileDiff) => fileDiff.diff.trim()).join(" "); -} - -function getCommitMessages(mrCommits) { - return mrCommits.map((commit) => commit.message); -} - -function getInputPrompt() { - return `You are a helpful assistant that creates suggestions for single git commit message, that user can use to describe all the changes in their merge request. - Use git diff: {mrDiff} and users current commit messages: {mrCommitMessages} to get the changes made in the commit. - - Output should be git commit message following the conventional commit format. - - Output only git commit message in desired format, without comments and other text. - - Do not include the closing statements ("Closes https://....") in the output. - - Here are the strict rules you must follow: - - - Avoid mentioning any JIRA tickets (e.g., "Closes JIRA-123"). - - Be specific. Don't use vague terms (e.g., "some checks", "add new ones", "few changes"). - - The commit message structure should be: <(scope/component)>: - - Types allowed: ${allowedTypes.join(", ")} - - If 'scope/component' is used, it must start with a lowercase letter. - - The 'summary' must NOT end with a period. - - The 'summary' must be between ${minimumSummaryChars} and ${maximumSummaryChars} characters long. - - If a 'body' of commit message is used: - - - Each line must be no longer than ${maximumBodyLineChars} characters. - - It must be separated from the 'summary' by a blank line. - - Examples of correct commit messages: - - - With scope and body: - fix(freertos): Fix startup timeout issue - - This is a text of commit message body... - - adds support for wifi6 - - adds validations for logging script - - - Without scope and body: - ci: added target test job for ESP32-Wifi6`; -} - -function getInputLlmTokens(inputPrompt, mrDiff, mrCommitMessages) { - const mrCommitMessagesTokens = openAiTokenCount(mrCommitMessages.join(" ")); - const gitDiffTokens = openAiTokenCount(mrDiff); - const promptTokens = openAiTokenCount(inputPrompt); - return mrCommitMessagesTokens + gitDiffTokens + promptTokens; -} - -async function createAiGitMessage(inputPrompt, mrDiff, mrCommitMessages) { - const chat = new ChatOpenAI({ engine: "gpt-3.5-turbo", temperature: 0 }); - const chatPrompt = ChatPromptTemplate.fromPromptMessages([ - SystemMessagePromptTemplate.fromTemplate(inputPrompt), - ]); - const chain = new LLMChain({ prompt: chatPrompt, llm: chat }); - - const response = await chain.call({ - mrDiff: mrDiff, - mrCommitMessages: mrCommitMessages, - }); - return response.text; -} - -function postProcessCommitMessage(rawCommitMessage) { - // Split the result into lines - let lines = rawCommitMessage.split("\n"); - - // Format each line - for (let i = 0; i < lines.length; i++) { - let line = lines[i].trim(); - - // If the line is longer than maximumBodyLineChars, split it into multiple lines - if (line.length > maximumBodyLineChars) { - let newLines = []; - while (line.length > maximumBodyLineChars) { - let lastSpaceIndex = line.lastIndexOf( - " ", - maximumBodyLineChars - ); - newLines.push(line.substring(0, lastSpaceIndex)); - line = line.substring(lastSpaceIndex + 1); - } - newLines.push(line); - lines[i] = newLines.join("\n"); - } - } - - // Join the lines back into a single string with a newline between each one - return lines.join("\n"); -} - -function extractClosingStatements(mrCommitMessages) { - let closingStatements = []; - mrCommitMessages.forEach((message) => { - const lines = message.split("\n"); - lines.forEach((line) => { - if (line.startsWith("Closes")) { - closingStatements.push(line); - } - }); - }); - return closingStatements.join("\n"); -} diff --git a/.gitlab/dangerjs/configParameters.js b/.gitlab/dangerjs/configParameters.js deleted file mode 100644 index 9fb27960c58..00000000000 --- a/.gitlab/dangerjs/configParameters.js +++ /dev/null @@ -1,56 +0,0 @@ -let outputStatuses = []; - -/** - * Logs the status of a rule with padded formatting and stores it in the `outputStatuses` array. - * If the rule already exists in the array, its status is updated. - * @param message The name of the rule - * @param status The output (exit) status of the rule - */ -function recordRuleExitStatus(message, status) { - // Check if the rule already exists in the array - const existingRecord = outputStatuses.find( - (rule) => rule.message === message - ); - - if (existingRecord) { - // Update the status of the existing rule - existingRecord.status = status; - } else { - // If the rule doesn't exist, add it to the array - outputStatuses.push({ message, status }); - } -} - -/** - * Displays all the rule output statuses stored in the `outputStatuses` array. - * Filters out any empty lines, sorts them alphabetically, and prints the statuses - * with a header and separator. - * These statuses are later displayed in CI job tracelog. - */ -function displayAllOutputStatuses() { - const lineLength = 100; - const sortedStatuses = outputStatuses.sort((a, b) => - a.message.localeCompare(b.message) - ); - - const formattedLines = sortedStatuses.map((statusObj) => { - const paddingLength = - lineLength - statusObj.message.length - statusObj.status.length; - const paddedMessage = statusObj.message.padEnd( - statusObj.message.length + paddingLength, - "." - ); - return `${paddedMessage} ${statusObj.status}`; - }); - - console.log( - "DangerJS checks (rules) output states:\n" + "=".repeat(lineLength + 2) - ); - console.log(formattedLines.join("\n")); - console.log("=".repeat(lineLength + 2)); -} - -module.exports = { - displayAllOutputStatuses, - recordRuleExitStatus, -}; diff --git a/.gitlab/dangerjs/dangerfile.js b/.gitlab/dangerjs/dangerfile.js deleted file mode 100644 index 544afcfa857..00000000000 --- a/.gitlab/dangerjs/dangerfile.js +++ /dev/null @@ -1,51 +0,0 @@ -const { displayAllOutputStatuses } = require("./configParameters.js"); - -/* - * Modules with checks are stored in ".gitlab/dangerjs/". To import them, use path relative to "dangerfile.js" - */ -async function runChecks() { - // Checks for merge request title - require("./mrTitleNoDraftOrWip.js")(); - - // Checks for merge request description - require("./mrDescriptionLongEnough.js")(); - require("./mrDescriptionReleaseNotes.js")(); - await require("./mrDescriptionJiraLinks.js")(); - - // Checks for documentation - await require("./mrDocsTranslation.js")(); - - // Checks for MR commits - require("./mrCommitsTooManyCommits.js")(); - await require("./mrCommitsCommitMessage.js")(); - require("./mrCommitsEmail.js")(); - - // Checks for MR code - require("./mrSizeTooLarge.js")(); - - // Checks for MR area labels - await require("./mrAreaLabels.js")(); - - // Checks for Source branch name - require("./mrSourceBranchName.js")(); - - // Show DangerJS individual checks statuses - visible in CI job tracelog - displayAllOutputStatuses(); - - // Add success log if no issues - if ( - results.fails.length === 0 && - results.warnings.length === 0 && - results.messages.length === 0 - ) { - return message("🎉 Good Job! All checks are passing!"); - } -} - -runChecks(); - -// Add retry link -const retryLink = `${process.env.DANGER_GITLAB_HOST}/${process.env.CI_PROJECT_PATH}/-/jobs/${process.env.CI_JOB_ID}`; -markdown( - `***\n#### :repeat: You can enforce automatic MR checks by retrying the [DangerJS job](${retryLink})\n***` -); diff --git a/.gitlab/dangerjs/mrAreaLabels.js b/.gitlab/dangerjs/mrAreaLabels.js deleted file mode 100644 index 159d5bc0740..00000000000 --- a/.gitlab/dangerjs/mrAreaLabels.js +++ /dev/null @@ -1,27 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if MR has area labels (light blue labels) - * - * @dangerjs WARN - */ -module.exports = async function () { - const ruleName = "Merge request area labels"; - const projectId = 103; // ESP-IDF - const areaLabelColor = /^#d2ebfa$/i; // match color code (case-insensitive) - const projectLabels = await danger.gitlab.api.Labels.all(projectId); // Get all project labels - const areaLabels = projectLabels - .filter((label) => areaLabelColor.test(label.color)) - .map((label) => label.name); // Filter only area labels - const mrLabels = danger.gitlab.mr.labels; // Get MR labels - - if (!mrLabels.some((label) => areaLabels.includes(label))) { - recordRuleExitStatus(ruleName, "Failed"); - return warn( - `Please add some [area labels](${process.env.DANGER_GITLAB_HOST}/espressif/esp-idf/-/labels) to this MR.` - ); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, "Passed"); -}; diff --git a/.gitlab/dangerjs/mrCommitsCommitMessage.js b/.gitlab/dangerjs/mrCommitsCommitMessage.js deleted file mode 100644 index 6d90dbaf6a9..00000000000 --- a/.gitlab/dangerjs/mrCommitsCommitMessage.js +++ /dev/null @@ -1,165 +0,0 @@ -const { - minimumSummaryChars, - maximumSummaryChars, - maximumBodyLineChars, - allowedTypes, -} = require("./mrCommitsConstants.js"); -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check that commit messages are based on the Espressif ESP-IDF project's rules for git commit messages. - * - * @dangerjs WARN - */ -module.exports = async function () { - const ruleName = "Commit messages style"; - const mrCommits = danger.gitlab.commits; - const lint = require("@commitlint/lint").default; - - const lintingRules = { - // rule definition: [(0-1 = off/on), (always/never = must be/mustn't be), (value)] - "body-max-line-length": [1, "always", maximumBodyLineChars], // Max length of the body line - "footer-leading-blank": [1, "always"], // Always have a blank line before the footer section - "footer-max-line-length": [1, "always", maximumBodyLineChars], // Max length of the footer line - "subject-max-length": [1, "always", maximumSummaryChars], // Max length of the "Summary" - "subject-min-length": [1, "always", minimumSummaryChars], // Min length of the "Summary" - "scope-case": [1, "always", "lower-case"], // "scope/component" must start with lower-case - "subject-full-stop": [1, "never", "."], // "Summary" must not end with a full stop (period) - "subject-empty": [1, "never"], // "Summary" is mandatory - "type-case": [1, "always", "lower-case"], // "type/action" must start with lower-case - "type-empty": [1, "never"], // "type/action" is mandatory - "type-enum": [1, "always", allowedTypes], // "type/action" must be one of the allowed types - "body-leading-blank": [1, "always"], // Always have a blank line before the body section - }; - - // Switcher for AI suggestions (for poor messages) - let generateAISuggestion = false; - - // Search for the messages in each commit - let issuesAllCommitMessages = []; - - for (const commit of mrCommits) { - const commitMessage = commit.message; - const commitMessageTitle = commit.title; - - let issuesSingleCommitMessage = []; - let reportSingleCommitMessage = ""; - - // Check if the commit message contains any Jira ticket references - const jiraTicketRegex = /[A-Z0-9]+-[0-9]+/g; - const jiraTicketMatches = commitMessage.match(jiraTicketRegex); - if (jiraTicketMatches) { - const jiraTicketNames = jiraTicketMatches.join(", "); - issuesSingleCommitMessage.push( - `- probably contains Jira ticket reference (\`${jiraTicketNames}\`). Please remove Jira tickets from commit messages.` - ); - } - - // Lint commit messages with @commitlint (Conventional Commits style) - const result = await lint(commit.message, lintingRules); - - for (const warning of result.warnings) { - // Custom messages for each rule with terminology used by Espressif conventional commits guide - switch (warning.name) { - case "subject-max-length": - issuesSingleCommitMessage.push( - `- *summary* appears to be too long` - ); - break; - case "type-empty": - issuesSingleCommitMessage.push( - `- *type/action* looks empty` - ); - break; - case "type-case": - issuesSingleCommitMessage.push( - `- *type/action* should start with a lowercase letter` - ); - - break; - case "scope-empty": - issuesSingleCommitMessage.push( - `- *scope/component* looks empty` - ); - break; - case "scope-case": - issuesSingleCommitMessage.push( - `- *scope/component* should be lowercase without whitespace, allowed special characters are \`_\` \`/\` \`.\` \`,\` \`*\` \`-\` \`.\`` - ); - break; - case "subject-empty": - issuesSingleCommitMessage.push(`- *summary* looks empty`); - generateAISuggestion = true; - break; - case "subject-min-length": - issuesSingleCommitMessage.push( - `- *summary* looks too short` - ); - generateAISuggestion = true; - break; - case "subject-case": - issuesSingleCommitMessage.push( - `- *summary* should start with a capital letter` - ); - break; - case "subject-full-stop": - issuesSingleCommitMessage.push( - `- *summary* should not end with a period (full stop)` - ); - break; - case "type-enum": - issuesSingleCommitMessage.push( - `- *type/action* should be one of [${allowedTypes - .map((type) => `\`${type}\``) - .join(", ")}]` - ); - break; - - default: - issuesSingleCommitMessage.push(`- ${warning.message}`); - } - } - - if (issuesSingleCommitMessage.length) { - reportSingleCommitMessage = `- the commit message \`"${commitMessageTitle}"\`:\n${issuesSingleCommitMessage - .map((message) => ` ${message}`) // Indent each issue by 2 spaces - .join("\n")}`; - issuesAllCommitMessages.push(reportSingleCommitMessage); - } - } - - // Create report - if (issuesAllCommitMessages.length) { - issuesAllCommitMessages.sort(); - const basicTips = [ - `- correct format of commit message should be: \`(): \`, for example \`fix(esp32): Fixed startup timeout issue\``, - `- allowed types are: \`${allowedTypes}\``, - `- sufficiently descriptive message summary should be between ${minimumSummaryChars} to ${maximumSummaryChars} characters and start with upper case letter`, - `- avoid Jira references in commit messages (unavailable/irrelevant for our customers)`, - `- follow this [commit messages guide](${process.env.DANGER_GITLAB_HOST}/espressif/esp-idf/-/wikis/dev-proc/Commit-messages)`, - ]; - let dangerMessage = `\n**Some issues found for the commit messages in this MR:**\n${issuesAllCommitMessages.join( - "\n" - )} - \n*** - \n**Please consider updating these commit messages** - here are some basic tips:\n${basicTips.join( - "\n" - )} - \n \`TIP:\` You can install commit-msg pre-commit hook (\`pre-commit install -t pre-commit -t commit-msg\`) to run this check when committing. - \n*** - `; - - if (generateAISuggestion) { - // Create AI generated suggestion for git commit message based of gitDiff and current commit messages - const AImessageSuggestion = - await require("./aiGenerateGitMessage.js")(); - dangerMessage += AImessageSuggestion; - } - - recordRuleExitStatus(ruleName, "Failed"); - return warn(dangerMessage); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, "Passed"); -}; diff --git a/.gitlab/dangerjs/mrCommitsConstants.js b/.gitlab/dangerjs/mrCommitsConstants.js deleted file mode 100644 index 373722465e5..00000000000 --- a/.gitlab/dangerjs/mrCommitsConstants.js +++ /dev/null @@ -1,16 +0,0 @@ -module.exports = { - gptStandardModelTokens: 4096, - minimumSummaryChars: 20, - maximumSummaryChars: 72, - maximumBodyLineChars: 100, - allowedTypes: [ - "change", - "ci", - "docs", - "feat", - "fix", - "refactor", - "remove", - "revert", - ], -}; diff --git a/.gitlab/dangerjs/mrCommitsEmail.js b/.gitlab/dangerjs/mrCommitsEmail.js deleted file mode 100644 index 8adfc743ef5..00000000000 --- a/.gitlab/dangerjs/mrCommitsEmail.js +++ /dev/null @@ -1,23 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if the author is accidentally making a commit using a personal email - * - * @dangerjs INFO - */ -module.exports = function () { - const ruleName = 'Commits from outside Espressif'; - const mrCommitAuthorEmails = danger.gitlab.commits.map(commit => commit.author_email); - const mrCommitCommitterEmails = danger.gitlab.commits.map(commit => commit.committer_email); - const emailPattern = /.*@espressif\.com/; - const filteredEmails = [...mrCommitAuthorEmails, ...mrCommitCommitterEmails].filter((email) => !emailPattern.test(email)); - if (filteredEmails.length) { - recordRuleExitStatus(ruleName, "Failed"); - return message( - `Some of the commits were authored or committed by developers outside Espressif: ${filteredEmails.join(', ')}. Please check if this is expected.` - ); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, 'Passed'); -}; diff --git a/.gitlab/dangerjs/mrCommitsTooManyCommits.js b/.gitlab/dangerjs/mrCommitsTooManyCommits.js deleted file mode 100644 index 1cd49e1ad03..00000000000 --- a/.gitlab/dangerjs/mrCommitsTooManyCommits.js +++ /dev/null @@ -1,22 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if MR has not an excessive numbers of commits (if squashed) - * - * @dangerjs INFO - */ -module.exports = function () { - const ruleName = 'Number of commits in merge request'; - const tooManyCommitThreshold = 2; // above this number of commits, squash commits is suggested - const mrCommits = danger.gitlab.commits; - - if (mrCommits.length > tooManyCommitThreshold) { - recordRuleExitStatus(ruleName, "Passed (with suggestions)"); - return message( - `You might consider squashing your ${mrCommits.length} commits (simplifying branch history).` - ); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, 'Passed'); -}; diff --git a/.gitlab/dangerjs/mrDescriptionJiraLinks.js b/.gitlab/dangerjs/mrDescriptionJiraLinks.js deleted file mode 100644 index 53d929da681..00000000000 --- a/.gitlab/dangerjs/mrDescriptionJiraLinks.js +++ /dev/null @@ -1,238 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** Check that there are valid JIRA links in MR description. - * - * This check extracts the "Related" section from the MR description and - * searches for JIRA ticket references in the format "Closes [JIRA ticket key]". - * - * It then extracts the closing GitHub links from the corresponding JIRA tickets and - * checks if the linked GitHub issues are still in open state. - * - * Finally, it checks if the required GitHub closing links are present in the MR's commit messages. - * - */ -module.exports = async function () { - const ruleName = 'Jira ticket references'; - const axios = require("axios"); - const mrDescription = danger.gitlab.mr.description; - const mrCommitMessages = danger.gitlab.commits.map( - (commit) => commit.message - ); - const jiraTicketRegex = /[A-Z0-9]+-[0-9]+/; - - let partMessages = []; // Create a blank field for future records of individual issues - - // Parse section "Related" from MR Description - const sectionRelated = extractSectionRelated(mrDescription); - - if ( - !sectionRelated.header || // No section Related in MR description or ... - !jiraTicketRegex.test(sectionRelated.content) // no Jira links in section Related - ) { - recordRuleExitStatus(ruleName, 'Passed (with suggestions)'); - return message( - "Please consider adding references to JIRA issues in the `Related` section of the MR description." - ); - } - - // Get closing (only) JIRA tickets - const jiraTickets = findClosingJiraTickets(sectionRelated.content); - - for (const ticket of jiraTickets) { - ticket.jiraUIUrl = `https://jira.espressif.com:8443/browse/${ticket.ticketName}`; - - if (!ticket.correctFormat) { - partMessages.push( - `- closing ticket \`${ticket.record}\` seems to be in the wrong format (or inaccessible to Jira DangerBot).. The correct format is for example \`- Closes JIRA-123\`.` - ); - } - - // Get closing GitHub issue links from JIRA tickets - const closingGithubLink = await getGitHubClosingLink(ticket.ticketName); - if (closingGithubLink) { - ticket.closingGithubLink = closingGithubLink; - } else if (closingGithubLink === null) { - partMessages.push( - `- the Jira issue number [\`${ticket.ticketName}\`](${ticket.jiraUIUrl}) seems to be invalid (please check if the ticket number is correct)` - ); - continue; // Handle unreachable JIRA tickets; skip the following checks - } else { - continue; // Jira ticket have no GitHub closing link; skip the following checks - } - - // Get still open GitHub issues - const githubIssueStatusOpen = await isGithubIssueOpen( - ticket.closingGithubLink - ); - ticket.isOpen = githubIssueStatusOpen; - if (githubIssueStatusOpen === null) { - // Handle unreachable GitHub issues - partMessages.push( - `- the GitHub issue [\`${ticket.closingGithubLink}\`](${ticket.closingGithubLink}) does not seem to exist on GitHub (referenced from JIRA ticket [\`${ticket.ticketName}\`](${ticket.jiraUIUrl}) )` - ); - continue; // skip the following checks - } - - // Search in commit message if there are all GitHub closing links (from Related section) for still open GH issues - if (ticket.isOpen) { - if ( - !mrCommitMessages.some((item) => - item.includes(`Closes ${ticket.closingGithubLink}`) - ) - ) { - partMessages.push( - `- please add \`Closes ${ticket.closingGithubLink}\` to the commit message` - ); - } - } - } - - // Create report / DangerJS check feedback if issues with Jira links found - if (partMessages.length) { - createReport(); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, 'Passed'); - - // --------------------------------------------------------------- - - /** - * This function takes in a string mrDescription which contains a Markdown-formatted text - * related to a Merge Request (MR) in a GitLab repository. It searches for a section titled "Related" - * and extracts the content of that section. If the section is not found, it returns an object - * indicating that the header and content are null. If the section is found but empty, it returns - * an object indicating that the header is present but the content is null. If the section is found - * with content, it returns an object indicating that the header is present and the content of the - * "Related" section. - * - * @param {string} mrDescription - The Markdown-formatted text related to the Merge Request. - * @returns {{ - * header: string | boolean | null, - * content: string | null - * }} - An object containing the header and content of the "Related" section, if present. - */ - - function extractSectionRelated(mrDescription) { - const regexSectionRelated = /## Related([\s\S]*?)(?=## |$)/; - const sectionRelated = mrDescription.match(regexSectionRelated); - if (!sectionRelated) { - return { header: null, content: null }; // Section "Related" is missing - } - - const content = sectionRelated[1].replace(/(\r\n|\n|\r)/gm, ""); // Remove empty lines - if (!content.length) { - return { header: true, content: null }; // Section "Related" is present, but empty - } - - return { header: true, content: sectionRelated[1] }; // Found section "Related" with content - } - - /** - * Finds all JIRA tickets that are being closed in the given sectionRelatedcontent. - * The function searches for lines that start with - Closes and have the format Closes [uppercase letters]-[numbers]. - * @param {string} sectionRelatedcontent - A string that contains lines with mentions of JIRA tickets - * @returns {Array} An array of objects with ticketName property that has the correct format - */ - - function findClosingJiraTickets(sectionRelatedcontent) { - let closingTickets = []; - const lines = sectionRelatedcontent.split("\n"); - for (const line of lines) { - if (!line.startsWith("- Closes")) { - continue; // Not closing-type ticket, skip - } - - const correctJiraClosingLinkFormat = new RegExp( - `^- Closes ${jiraTicketRegex.source}$` - ); - const matchedJiraTicket = line.match(jiraTicketRegex); - if (matchedJiraTicket) { - if (!correctJiraClosingLinkFormat.test(line)) { - closingTickets.push({ - record: line, - ticketName: matchedJiraTicket[0], - correctFormat: false, - }); - } else { - closingTickets.push({ - record: line, - ticketName: matchedJiraTicket[0], - correctFormat: true, - }); - } - } - } - return closingTickets; - } - - /** - * This function takes a JIRA issue key and retrieves the description from JIRA's API. - * It then searches the description for a GitHub closing link in the format "Closes https://github.com/owner/repo/issues/123". - * If a GitHub closing link is found, it is returned. If no GitHub closing link is found, it returns null. - * @param {string} jiraIssueKey - The key of the JIRA issue to search for the GitHub closing link. - * @returns {Promise} - A promise that resolves to a string containing the GitHub closing link if found, - * or null if not found. - */ - async function getGitHubClosingLink(jiraIssueKey) { - let jiraDescription = ""; - - // Get JIRA ticket description content - try { - const response = await axios({ - url: `https://jira.espressif.com:8443/rest/api/latest/issue/${jiraIssueKey}`, - auth: { - username: process.env.DANGER_JIRA_USER, - password: process.env.DANGER_JIRA_PASSWORD, - }, - }); - jiraDescription = response.data.fields.description - ? response.data.fields.description - : ""; // if the Jira ticket has an unfilled Description, the ".description" property is missing in API response - in that case set "jiraDescription" to an empty string - } catch (error) { - return null; - } - - // Find GitHub closing link in description - const regexClosingGhLink = - /Closes\s+(https:\/\/github.com\/\S+\/\S+\/issues\/\d+)/; - const closingGithubLink = jiraDescription.match(regexClosingGhLink); - - if (closingGithubLink) { - return closingGithubLink[1]; - } else { - return false; // Jira issue has no GitHub closing link in description - } - } - - /** - * Check if a GitHub issue linked in a merge request is still open. - * - * @param {string} link - The link to the GitHub issue. - * @returns {Promise} A promise that resolves to a boolean indicating if the issue is open. - * @throws {Error} If the link is invalid or if there was an error fetching the issue. - */ - async function isGithubIssueOpen(link) { - const parsedUrl = new URL(link); - const [owner, repo] = parsedUrl.pathname.split("/").slice(1, 3); - const issueNumber = parsedUrl.pathname.split("/").slice(-1)[0]; - - try { - const response = await axios.get( - `https://api.github.com/repos/${owner}/${repo}/issues/${issueNumber}` - ); - return response.data.state === "open"; // return True if GitHub issue is open - } catch (error) { - return null; // GET request to issue fails - } - } - - function createReport() { - partMessages.sort(); - let dangerMessage = `Some issues found for the related JIRA tickets in this MR:\n${partMessages.join( - "\n" - )}`; - recordRuleExitStatus(ruleName, "Failed"); - return warn(dangerMessage); - } -}; diff --git a/.gitlab/dangerjs/mrDescriptionLongEnough.js b/.gitlab/dangerjs/mrDescriptionLongEnough.js deleted file mode 100644 index abd098204dd..00000000000 --- a/.gitlab/dangerjs/mrDescriptionLongEnough.js +++ /dev/null @@ -1,24 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if MR Description has accurate description". - * - * @dangerjs WARN - */ -module.exports = function () { - const ruleName = "Merge request sufficient description"; - const mrDescription = danger.gitlab.mr.description; - const descriptionChunk = mrDescription.match(/^([^#]*)/)[1].trim(); // Extract all text before the first section header (i.e., the text before the "## Release notes") - - const shortMrDescriptionThreshold = 50; // Description is considered too short below this number of characters - - if (descriptionChunk.length < shortMrDescriptionThreshold) { - recordRuleExitStatus(ruleName, "Failed"); - return warn( - "The MR description looks very brief, please check if more details can be added." - ); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, "Passed"); -}; diff --git a/.gitlab/dangerjs/mrDescriptionReleaseNotes.js b/.gitlab/dangerjs/mrDescriptionReleaseNotes.js deleted file mode 100644 index 88ead239cd8..00000000000 --- a/.gitlab/dangerjs/mrDescriptionReleaseNotes.js +++ /dev/null @@ -1,103 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if MR Description contains mandatory section "Release notes" - * - * Extracts the content of the "Release notes" section from the GitLab merge request description. - * - * @dangerjs WARN (if section missing, is empty or wrong markdown format) - */ -module.exports = function () { - const ruleName = 'Merge request Release Notes section'; - const mrDescription = danger.gitlab.mr.description; - const wiki_link = `${process.env.DANGER_GITLAB_HOST}/espressif/esp-idf/-/wikis/rfc/How-to-write-release-notes-properly`; - - const regexSectionReleaseNotes = /## Release notes([\s\S]*?)(?=## |$)/; - const regexValidEntry = /^\s*[-*+]\s+.+/; - const regexNoReleaseNotes = /no release note/i; - - const sectionReleaseNotes = mrDescription.match(regexSectionReleaseNotes); - if (!sectionReleaseNotes) { - recordRuleExitStatus(ruleName, "Failed"); - return warn(`The \`Release Notes\` section seems to be missing. Please check if the section header in MR description is present and in the correct markdown format ("## Release Notes").\n\nSee [Release Notes Format Rules](${wiki_link}).`); - } - - const releaseNotesLines = sectionReleaseNotes[1].replace(//g, '') - - const lines = releaseNotesLines.split("\n").filter(s => s.trim().length > 0); - let valid_entries_found = 0; - let no_release_notes_found = false; - let violations = []; - - lines.forEach((line) => { - if (line.match(regexValidEntry)) { - valid_entries_found++; - const error_msg = check_entry(line); - if (error_msg) { - violations.push(error_msg); - } - } else if (line.match(regexNoReleaseNotes)) { - no_release_notes_found = true; - } - }); - - let error_output = []; - if (violations.length > 0) { - error_output = [...error_output, 'Invalid release note entries:', violations.join('\n')]; - } - if (no_release_notes_found) { - if (valid_entries_found > 0) { - error_output.push('`No release notes` comment shows up when there is valid entry. Remove bullets before comments in release notes section.'); - } - } else { - if (!valid_entries_found) { - error_output.push('The `Release Notes` section seems to have no valid entries. Add bullets before valid entries, or add `No release notes` comment to suppress this error if you mean to have no release notes.'); - } - } - - if (error_output.length > 0) { - // Paragraphs joined by double `\n`s. - error_output = [...error_output, `See [Release Notes Format Guide](${wiki_link}).`].join('\n\n'); - recordRuleExitStatus(ruleName, "Failed"); - return warn(error_output); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, 'Passed'); -}; - -function check_entry(entry) { - const entry_str = `- \`${entry}\``; - const indent = " "; - - if (entry.match(/no\s+release\s+note/i)) { - return [entry_str, `${indent}- \`No release notes\` comment shouldn't start with bullet.`].join('\n'); - } - - // Remove a leading escaping backslash of the special characters, https://www.markdownguide.org/basic-syntax/#characters-you-can-escape - const escapeCharRegex = /\\([\\`*_{}[\]<>()+#-.!|])/g; - entry = entry.replace(escapeCharRegex, '$1'); - - const regex = /^(\s*)[-*+]\s+\[([^\]]+)\]\s+(.*)$/; - const match = regex.exec(entry); - if (!match) { - return [entry_str, `${indent}- Please specify the [area] to which the change belongs (see guide). If this line is just a comment, remove the bullet.`].join('\n'); - } - - // area is in match[2] - const description = match[3].trim(); - let violations = []; - - if (match[1]) { - violations.push(`${indent}- Release note entry should start from the beginning of line. (Nested release note not allowed.)`); - } - - if (!/^[A-Z0-9]/.test(description)) { - violations.push(`${indent}- Release note statement should start with a capital letter or digit.`); - } - - if (violations.length > 0) { - return [entry_str, ...violations].join('\n'); - } - return null; -} diff --git a/.gitlab/dangerjs/mrDocsTranslation.js b/.gitlab/dangerjs/mrDocsTranslation.js deleted file mode 100644 index 7c9412a2af8..00000000000 --- a/.gitlab/dangerjs/mrDocsTranslation.js +++ /dev/null @@ -1,280 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check the documentation files in this MR. - * - * Generate an object with all docs/ files found in this MR with paths to their EN/CN versions. - * - * For common files (both language versions exist in this MR), compare the lines of both files. - * Ignore if the CN file is only a single line file with an "include" reference to the EN version. - * - * For files that only have a CN version in this MR, add a message to the message that an EN file also needs to be created. - * - * For a file that only has an EN version in this MR, try loading its CN version from the target Gitlab branch. - * If its CN version doesn't exist in the repository or it does exist, - * but its contents are larger than just an "include" link to the EN version (it's a full-size file), - * add a message to the report - * - * Create a compiled report with the docs/ files issues found and set its severity (WARN/INFO). - * Severity is based on the presence of "needs translation: ??" labels in this MR - * - * @dangerjs WARN (if docs translation issues in the MR) - * @dangerjs INFO (if docs translation issues in the MR and the user has already added translation labels). - * Adding translation labels "needs translation: XX" automatically notifies the Documentation team - * - * @dangerjs WARN (if there are no docs issues in MR, but translation labels have been added anyway) - * - */ -module.exports = async function () { - const ruleName = 'Documentation translation'; - let partMessages = []; // Create a blank field for future records of individual issues - const pathProject = "espressif/esp-idf"; - const regexIncludeLink = /\.\.\sinclude::\s((\.\.\/)+)en\//; - const allMrFiles = [ - ...danger.git.modified_files, - ...danger.git.created_files, - ...danger.git.deleted_files, - ]; - - const docsFilesMR = parseMrDocsFiles(allMrFiles); // Create single object of all doc files in MR with names, paths and groups - - // Both versions (EN and CN) of document found changed in this MR - for (const file of docsFilesMR.bothFilesInMr) { - file.contentEn = await getContentFileInMR(file.fileEnPath); // Get content of English file - file.linesEn = file.contentEn.split("\n").length; // Get number of lines of English file - - file.contentCn = await getContentFileInMR(file.fileCnPath); // Get content of Chinese file - file.linesCn = file.contentCn.split("\n").length; // Get number of lines of English file - - // Compare number of lines in both versions - if (file.linesEn !== file.linesCn) { - // Check if CN file is only link to EN file - if (!regexIncludeLink.test(file.contentCn)) { - // if not just a link ... - partMessages.push( - `- please synchronize the EN and CN version of \`${file.fileName}\`. [\`${file.fileEnPath}\`](${file.fileUrlRepoEN}) has ${file.linesEn} lines; [\`${file.fileCnPath}\`](${file.fileUrlRepoCN}) has ${file.linesCn} lines.` - ); - } - } - } - - // Only Chinese version of document found changed in this MR - for (const file of docsFilesMR.onlyCnFilesInMr) { - partMessages.push( - `- file \`${file.fileEnPath}\` doesn't exist in this MR or in the GitLab repo. Please add \`${file.fileEnPath}\` into this MR.` - ); - } - - // Only English version of document found in this MR - for (const file of docsFilesMR.onlyEnFilesInMr) { - const targetBranch = danger.gitlab.mr.target_branch; - file.contentCn = await getContentFileInGitlab( - file.fileCnPath, - targetBranch - ); // Try to fetch CN file from target branch of Gitlab repository and store content - - if (file.contentCn) { - // File found on target branch in Gitlab repository - if (!regexIncludeLink.test(file.contentCn)) { - // File on Gitlab master is NOT just an ..include:: link to ENG version - file.fileUrlRepoMasterCN = `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${targetBranch}/${file.fileCnPath}`; - partMessages.push( - `- file \`${file.fileCnPath}\` was not updated in this MR, but found unchanged full document (not just link to EN) in target branch of Gitlab repository [\`${file.fileCnPath}\`](${file.fileUrlRepoMasterCN}). Please update \`${file.fileCnPath}\` into this MR.` - ); - } - } else { - // File failed to fetch, probably does not exist in the target branch - partMessages.push( - `- file \`${file.fileCnPath}\` probably doesn't exist in this MR or in the GitLab repo. Please add \`${file.fileCnPath}\` into this MR.` - ); - } - } - - // Create a report with found issues with documents in MR - createReport(); - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, 'Passed'); - - /** - * Generates an object that represents the relationships between files in two different languages found in this MR. - * - * @param {string[]} docsFilesEN - An array of file paths for documents in English. - * @param {string[]} docsFilesCN - An array of file paths for documents in Chinese. - * @returns {Object} An object with the following properties: - * - bothFilesInMr: An array of objects that represent files that found in MR in both languages. Each object has the following properties: - * - fileName: The name of the file. - * - fileEnPath: The path to the file in English. - * - fileCnPath: The path to the file in Chinese. - * - fileUrlRepoEN: The URL link to MR branch path to the file in English. - * - fileUrlRepoCN: The URL link to MR branch path to the file in Chinese. - * - onlyCnFilesInMr: An array of objects that represent files that only found in MR in English. Each object has the following properties: - * - fileName: The name of the file. - * - fileEnPath: The path to the file in English. - * - fileCnPath: The FUTURE path to the file in Chinese. - * - fileUrlRepoEN: The URL link to MR branch path to the file in English. - * - fileUrlRepoCN: The URL link to MR branch path to the file in Chinese. - * - onlyEnFilesInMr: An array of objects that represent files that only found in MR in Chinese. Each object has the following properties: - * - fileName: The name of the file. - * - fileEnPath: The FUTURE path to the file in English. - * - fileCnPath: The path to the file in Chinese. - * - fileUrlRepoEN: The URL link to MR branch path to the file in English. - * - fileUrlRepoCN: The URL link to MR branch path to the file in Chinese. - */ - function parseMrDocsFiles(allMrFiles) { - const path = require("path"); - const mrBranch = danger.gitlab.mr.source_branch; - - const docsEnFilesMrPath = allMrFiles.filter((file) => - file.startsWith("docs/en") - ); // Filter all English doc files in MR - const docsCnFilesMrPath = allMrFiles.filter((file) => - file.startsWith("docs/zh_CN") - ); // Filter all Chinese doc files in MR - - const docsEnFileNames = docsEnFilesMrPath.map((filePath) => - path.basename(filePath) - ); // Get (base) file names for English docs - const docsCnFileNames = docsCnFilesMrPath.map((filePath) => - path.basename(filePath) - ); // Get (base) file names for Chinese docs - - const bothFileNames = docsEnFileNames.filter((fileName) => - docsCnFileNames.includes(fileName) - ); // Get file names that are common to both English and Chinese docs - const onlyEnFileNames = docsEnFileNames.filter( - (fileName) => !docsCnFileNames.includes(fileName) - ); // Get file names that are only present in English version - const onlyCnFileNames = docsCnFileNames.filter( - (fileName) => !docsEnFileNames.includes(fileName) - ); // Get file names that are only present in Chinese version - - return { - bothFilesInMr: bothFileNames.map((fileName) => { - const fileEnPath = - docsEnFilesMrPath[docsEnFileNames.indexOf(fileName)]; - const fileCnPath = - docsCnFilesMrPath[docsCnFileNames.indexOf(fileName)]; - - return { - fileName, - fileEnPath, - fileCnPath, - fileUrlRepoEN: `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${mrBranch}/${fileEnPath}`, - fileUrlRepoCN: `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${mrBranch}/${fileCnPath}`, - }; - }), - onlyEnFilesInMr: onlyEnFileNames.map((fileName) => { - const fileEnPath = - docsEnFilesMrPath[docsEnFileNames.indexOf(fileName)]; - const fileCnPath = fileEnPath.replace("en", "zh_CN"); // Generate future CN file path - - return { - fileName, - fileEnPath, - fileCnPath, - fileUrlRepoEN: `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${mrBranch}/${fileEnPath}`, - fileUrlRepoCN: `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${mrBranch}/${fileCnPath}`, - }; - }), - onlyCnFilesInMr: onlyCnFileNames.map((fileName) => { - const fileCnPath = - docsCnFilesMrPath[docsCnFileNames.indexOf(fileName)]; - const fileEnPath = fileCnPath.replace("zh_CN", "en"); // Generate future EN file path - - return { - fileName, - fileEnPath, - fileCnPath, - fileUrlRepoEN: `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${mrBranch}/${fileEnPath}`, - fileUrlRepoCN: `${process.env.DANGER_GITLAB_HOST}/${pathProject}/-/blob/${mrBranch}/${fileCnPath}`, - }; - }), - }; - } - - /** - * Retrieves the contents of a file from GitLab using the GitLab API. - * - * @param {string} filePath - The path of the file to retrieve. - * @param {string} branch - The branch where the file is located. - * @returns {string|null} - The contents of the file, with any trailing new lines trimmed, or null if the file cannot be retrieved. - */ - async function getContentFileInGitlab(filePath, branch) { - const axios = require("axios"); - - const encFilePath = encodeURIComponent(filePath); - const encBranch = encodeURIComponent(branch); - const urlApi = `${process.env.DANGER_GITLAB_API_BASE_URL}/projects/${danger.gitlab.mr.project_id}/repository/files/${encFilePath}/raw?ref=${encBranch}`; - - try { - const response = await axios.get(urlApi, { - headers: { - "Private-Token": process.env.DANGER_GITLAB_API_TOKEN, - }, - }); - return response.data.trim(); // Trim trailing new line - } catch (error) { - return null; - } - } - - /** - * Retrieves the contents of a file in a DangerJS merge request object. - * - * @param {string} filePath - The path of the file to retrieve. - * @returns {string|null} - The contents of the file, with any trailing new lines trimmed, or null if the file cannot be retrieved. - */ - async function getContentFileInMR(filePath) { - try { - const content = await danger.git.diffForFile(filePath); - const fileContentAfter = content.after.trim(); // Trim trailing new lines - return fileContentAfter; - } catch (error) { - console.error(`Error while getting file content MR: ${error}`); - return null; - } - } - - /** - * Creates a compiled report for found documentation issues in the current MR and alerts the Documentation team if there are any "needs translation" labels present. - * - * Report if documentation labels have been added by mistake. - */ - function createReport() { - const mrLabels = danger.gitlab.mr.labels; // Get MR labels - const regexTranslationLabel = /needs translation:/i; - - const translationLabelsPresent = mrLabels.some((label) => - regexTranslationLabel.test(label) - ); // Check if any of MR labels are "needs translation: XX" - - // No docs issues found in MR, but translation labels have been added anyway - if (!partMessages.length && translationLabelsPresent) { - recordRuleExitStatus(ruleName, "Failed"); - return warn( - `Please remove the \`needs translation: XX\` labels. For documents that need to translate from scratch, Doc team will translate them in the future. For the current stage, we only focus on updating exiting EN and CN translation to make them in sync.` - ); - } - - // Docs issues found in this MR - partMessages.sort(); - let dangerMessage = `Some of the documentation files in this MR seem to have translations issues:\n${partMessages.join( - "\n" - )}\n`; - - if (partMessages.length) { - if (!translationLabelsPresent) { - dangerMessage += ` - \nWhen synchronizing the EN and CN versions, please follow the [Documentation Code](https://docs.espressif.com/projects/esp-idf/zh_CN/latest/esp32/contribute/documenting-code.html#standardize-document-format). The total number of lines of EN and CN should be same.\n - \nIf you have difficulty in providing translation, you can contact Documentation team by adding needs translation: CN or needs translation: EN labels into this MR and retrying Danger CI job. The documentation team will be automatically notified and will help you with the translations before the merge.\n`; - recordRuleExitStatus(ruleName, "Failed"); - return warn(dangerMessage); // no "needs translation: XX" labels in MR; report issues as warn - } else { - dangerMessage += `\nTranslation labels needs translation: CN or needs translation: EN were added - this will automatically notify the Documentation team to help you with translation issues.`; - recordRuleExitStatus(ruleName, 'Passed (with suggestions)'); - return message(dangerMessage); // "needs translation: XX" labels were found in MR and Docs team was notified; report issues as info - } - } - } -}; diff --git a/.gitlab/dangerjs/mrSizeTooLarge.js b/.gitlab/dangerjs/mrSizeTooLarge.js deleted file mode 100644 index 4be6ba1e933..00000000000 --- a/.gitlab/dangerjs/mrSizeTooLarge.js +++ /dev/null @@ -1,22 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if MR is too large (more than 1000 lines of changes) - * - * @dangerjs INFO - */ -module.exports = async function () { - const ruleName = "Merge request size (number of changed lines)"; - const bigMrLinesOfCodeThreshold = 1000; - const totalLines = await danger.git.linesOfCode(); - - if (totalLines > bigMrLinesOfCodeThreshold) { - recordRuleExitStatus(ruleName, "Passed (with suggestions)"); - return message( - `This MR seems to be quite large (total lines of code: ${totalLines}), you might consider splitting it into smaller MRs` - ); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, "Passed"); -}; diff --git a/.gitlab/dangerjs/mrSourceBranchName.js b/.gitlab/dangerjs/mrSourceBranchName.js deleted file mode 100644 index 9512d13ec20..00000000000 --- a/.gitlab/dangerjs/mrSourceBranchName.js +++ /dev/null @@ -1,31 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Throw Danger WARN if branch name contains more than one slash or uppercase letters - * - * @dangerjs INFO - */ -module.exports = function () { - const ruleName = "Source branch name"; - const sourceBranch = danger.gitlab.mr.source_branch; - - // Check if the source branch name contains more than one slash - const slashCount = (sourceBranch.match(/\//g) || []).length; - if (slashCount > 1) { - recordRuleExitStatus(ruleName, "Failed"); - return warn( - `The source branch name \`${sourceBranch}\` contains more than one slash. This can cause troubles with git sync. Please rename the branch.` - ); - } - - // Check if the source branch name contains any uppercase letters - if (sourceBranch !== sourceBranch.toLowerCase()) { - recordRuleExitStatus(ruleName, "Failed"); - return warn( - `The source branch name \`${sourceBranch}\` contains uppercase letters. This can cause troubles on case-insensitive file systems (macOS). Please use only lowercase letters.` - ); - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, "Passed"); -}; diff --git a/.gitlab/dangerjs/mrTitleNoDraftOrWip.js b/.gitlab/dangerjs/mrTitleNoDraftOrWip.js deleted file mode 100644 index 222383ac03a..00000000000 --- a/.gitlab/dangerjs/mrTitleNoDraftOrWip.js +++ /dev/null @@ -1,31 +0,0 @@ -const { recordRuleExitStatus } = require("./configParameters.js"); - -/** - * Check if MR Title contains prefix "WIP: ...". - * - * @dangerjs WARN - */ -module.exports = function () { - const ruleName = 'Merge request not in Draft or WIP state'; - const mrTitle = danger.gitlab.mr.title; - const regexes = [ - { prefix: "WIP", regex: /^WIP:/i }, - { prefix: "W.I.P", regex: /^W\.I\.P/i }, - { prefix: "[WIP]", regex: /^\[WIP/i }, - { prefix: "[W.I.P]", regex: /^\[W\.I\.P/i }, - { prefix: "(WIP)", regex: /^\(WIP/i }, - { prefix: "(W.I.P)", regex: /^\(W\.I\.P/i }, - ]; - - for (const item of regexes) { - if (item.regex.test(mrTitle)) { - recordRuleExitStatus(ruleName, "Failed"); - return warn( - `Please remove the \`${item.prefix}\` prefix from the MR name before merging this MR.` - ); - } - } - - // At this point, the rule has passed - recordRuleExitStatus(ruleName, "Passed"); -}; diff --git a/.gitlab/dangerjs/package-lock.json b/.gitlab/dangerjs/package-lock.json deleted file mode 100644 index 8cf835cefc3..00000000000 --- a/.gitlab/dangerjs/package-lock.json +++ /dev/null @@ -1,2745 +0,0 @@ -{ - "name": "dangerjs-esp-idf", - "lockfileVersion": 3, - "requires": true, - "packages": { - "": { - "name": "dangerjs-esp-idf", - "dependencies": { - "@commitlint/lint": "^13.1.0", - "axios": "^1.3.3", - "danger": "^11.2.3", - "langchain": "^0.0.53", - "openai-gpt-token-counter": "^1.0.3" - } - }, - "node_modules/@anthropic-ai/sdk": { - "version": "0.4.3", - "resolved": "https://registry.npmjs.org/@anthropic-ai/sdk/-/sdk-0.4.3.tgz", - "integrity": "sha512-SZrlXvjUUYT9rPmSzlTtmVk1OjVNpkCzILRluhiYwNcxXfQyvPJDi0CI6PyymygcgtqEF5EVqhKmC/PtPsNEIw==", - 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"openai-gpt-token-counter": "^1.0.3", - "@commitlint/lint": "^13.1.0" - } -} diff --git a/.gitlab/merge_request_templates/Mixed Template.md b/.gitlab/merge_request_templates/Mixed Template.md index 1fef13e90e4..34521ebb83d 100644 --- a/.gitlab/merge_request_templates/Mixed Template.md +++ b/.gitlab/merge_request_templates/Mixed Template.md @@ -42,7 +42,7 @@ _For other small/non-public changes, which are not expected to be in the release _Don't touch the subsection titles below, they will be parsed by scripts._ -## Release notes (Mandatory) +## Release notes _Changes made in this MR that should go into the **Release Notes** should be listed here. Please use **past tense** and *specify the area (see maintainers page of IDF internal wiki)*. If there is a subscope, include it and separate with slash (`/`). Minor changes can go to the descriptions above without a release notes entry._ diff --git a/.gitmodules b/.gitmodules index e944b5da373..43d84427b01 100644 --- a/.gitmodules +++ b/.gitmodules @@ -81,11 +81,11 @@ [submodule "components/unity/unity"] path = components/unity/unity url = ../../ThrowTheSwitch/Unity.git - sbom-version = v2.4.3-51-g7d2bf62b7e6a + sbom-version = v2.6.0-RC1 sbom-supplier = Organization: ThrowTheSwitch community sbom-url = https://github.com/ThrowTheSwitch/Unity sbom-description = Simple Unit Testing for C - sbom-hash = 7d2bf62b7e6afaf38153041a9d53c21aeeca9a25 + sbom-hash = bf560290f6020737eafaa8b5cbd2177c3956c03f [submodule "components/bt/host/nimble/nimble"] path = components/bt/host/nimble/nimble @@ -143,3 +143,7 @@ [submodule "components/esp_coex/lib"] path = components/esp_coex/lib url = ../../espressif/esp-coex-lib.git + +[submodule "components/bt/esp_ble_mesh/lib/lib"] + path = components/bt/esp_ble_mesh/lib/lib + url = ../../espressif/esp-ble-mesh-lib.git diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index ff91755bade..0e2ac147c4d 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,6 +1,10 @@ # See https://pre-commit.com for more information # See https://pre-commit.com/hooks.html for more hooks +minimum_pre_commit_version: 3.3.0 +default_install_hook_types: [pre-commit, post-commit, commit-msg] +default_stages: [pre-commit] + repos: - repo: https://github.com/pre-commit/pre-commit-hooks rev: v4.0.1 @@ -177,12 +181,6 @@ repos: always_run: true pass_filenames: false require_serial: true - - id: submodule-sbom-hash-check - name: Check if sbom-hash values for submodules in .gitmodules match submodules checkout hash in git tree - entry: python tools/test_sbom/test_submodules.py - language: python - always_run: true - pass_filenames: false - id: cleanup-ignore-lists name: Remove non-existing patterns from ignore lists entry: tools/ci/cleanup_ignore_lists.py @@ -200,12 +198,12 @@ repos: - id: check-copyright args: ['--ignore', 'tools/ci/check_copyright_ignore.txt', '--config', 'tools/ci/check_copyright_config.yaml'] - repo: https://github.com/espressif/conventional-precommit-linter - rev: v1.2.1 + rev: v1.4.1 hooks: - id: conventional-precommit-linter stages: [commit-msg] - repo: https://github.com/espressif/astyle_py.git - rev: v1.0.2 + rev: v1.0.5 hooks: - id: astyle_py # If you are modifying astyle version, update tools/format.sh as well @@ -221,3 +219,8 @@ repos: name: shellcheck dash (export.sh) args: ['--shell', 'dash', '-x'] files: 'export.sh' + - repo: https://github.com/espressif/esp-idf-sbom.git + rev: v0.13.0 + hooks: + - id: validate-sbom-manifest + stages: [post-commit] diff --git a/CMakeLists.txt b/CMakeLists.txt index a033c3d4786..153d9e24f06 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -121,8 +121,10 @@ if(CMAKE_C_COMPILER_ID MATCHES "Clang") list(APPEND compile_options "-Wno-c2x-extensions") # warning on xMPU_SETTINGS for esp32s2 has size 0 for C and 1 for C++ list(APPEND compile_options "-Wno-extern-c-compat") - # warning: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 - list(APPEND compile_options "-Wno-single-bit-bitfield-constant-conversion") + if(NOT (CONFIG_IDF_TARGET_LINUX AND CMAKE_HOST_SYSTEM_NAME STREQUAL "Darwin")) + # warning: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 + list(APPEND compile_options "-Wno-single-bit-bitfield-constant-conversion") + endif() endif() # More warnings may exist in unit tests and example projects. diff --git a/Kconfig b/Kconfig index 99c7a7dc078..5b3f7424a60 100644 --- a/Kconfig +++ b/Kconfig @@ -22,7 +22,6 @@ mainmenu "Espressif IoT Development Framework Configuration" config IDF_ENV_BRINGUP bool - default "y" if IDF_TARGET_ESP32P4 help - This option is ONLY used when doing new chip bringup. - This option will only enable necessary hw / sw settings for running @@ -114,6 +113,13 @@ mainmenu "Espressif IoT Development Framework Configuration" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV + config IDF_TARGET_ESP32C5 + bool + default "y" if IDF_TARGET="esp32c5" + select FREERTOS_UNICORE + select IDF_TARGET_ARCH_RISCV + select IDF_ENV_BRINGUP + config IDF_TARGET_ESP32P4 bool default "y" if IDF_TARGET="esp32p4" @@ -139,6 +145,7 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x000D if IDF_TARGET_ESP32C6 default 0x0010 if IDF_TARGET_ESP32H2 default 0x0012 if IDF_TARGET_ESP32P4 + default 0x0013 if IDF_TARGET_ESP32C5 default 0xFFFF diff --git a/components/app_trace/CMakeLists.txt b/components/app_trace/CMakeLists.txt index ff17766baea..c4b31ca7dc8 100644 --- a/components/app_trace/CMakeLists.txt +++ b/components/app_trace/CMakeLists.txt @@ -63,8 +63,7 @@ endif() idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "${include_dirs}" PRIV_INCLUDE_DIRS "${priv_include_dirs}" - PRIV_REQUIRES soc esp_driver_gptimer esp_driver_gpio - driver # TODO: replace with esp_driver_uart (IDF-8384) + PRIV_REQUIRES esp_driver_gptimer esp_driver_gpio esp_driver_uart REQUIRES esp_timer LDFRAGMENTS linker.lf) diff --git a/components/app_trace/Kconfig b/components/app_trace/Kconfig index 260fe517a5c..9ff09cdb595 100644 --- a/components/app_trace/Kconfig +++ b/components/app_trace/Kconfig @@ -231,7 +231,7 @@ menu "Application Level Tracing" choice APPTRACE_SV_CPU prompt "CPU to trace" - depends on APPTRACE_SV_DEST_UART && !FREERTOS_UNICORE + depends on APPTRACE_SV_DEST_UART && !ESP_SYSTEM_SINGLE_CORE_MODE default APPTRACE_SV_DEST_CPU_0 help Define the CPU to trace by SystemView. @@ -252,8 +252,8 @@ menu "Application Level Tracing" choice APPTRACE_SV_TS_SOURCE prompt "Timer to use as timestamp source" depends on APPTRACE_SV_ENABLE - default APPTRACE_SV_TS_SOURCE_CCOUNT if FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3 - default APPTRACE_SV_TS_SOURCE_GPTIMER if !FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3 + default APPTRACE_SV_TS_SOURCE_CCOUNT if ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3 + default APPTRACE_SV_TS_SOURCE_GPTIMER if !ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3 default APPTRACE_SV_TS_SOURCE_ESP_TIMER if PM_ENABLE || IDF_TARGET_ESP32C3 help SystemView needs to use a hardware timer as the source of timestamps @@ -261,7 +261,7 @@ menu "Application Level Tracing" config APPTRACE_SV_TS_SOURCE_CCOUNT bool "CPU cycle counter (CCOUNT)" - depends on FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3 + depends on ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3 config APPTRACE_SV_TS_SOURCE_GPTIMER bool "General Purpose Timer (Timer Group)" diff --git a/components/app_trace/app_trace.c b/components/app_trace/app_trace.c index 6a18087690c..16b3ae3336d 100644 --- a/components/app_trace/app_trace.c +++ b/components/app_trace/app_trace.c @@ -77,7 +77,7 @@ esp_err_t esp_apptrace_init(void) return ESP_OK; } -ESP_SYSTEM_INIT_FN(esp_apptrace_init, ESP_SYSTEM_INIT_ALL_CORES, 115) +ESP_SYSTEM_INIT_FN(esp_apptrace_init, SECONDARY, ESP_SYSTEM_INIT_ALL_CORES, 115) { return esp_apptrace_init(); } diff --git a/components/app_trace/port/xtensa/port.c b/components/app_trace/port/xtensa/port.c index 8d0d5f3fe3a..80a2efcd9ab 100644 --- a/components/app_trace/port/xtensa/port.c +++ b/components/app_trace/port/xtensa/port.c @@ -298,7 +298,7 @@ static inline void esp_apptrace_trax_memory_enable(void) #if CONFIG_IDF_TARGET_ESP32 /* Enable trace memory on PRO CPU */ DPORT_WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M); -#if CONFIG_FREERTOS_UNICORE == 0 +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE == 0 /* Enable trace memory on APP CPU */ DPORT_WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M); #endif diff --git a/components/app_trace/sys_view/esp/SEGGER_RTT_esp.c b/components/app_trace/sys_view/esp/SEGGER_RTT_esp.c index 9963aced9d7..493cde5e0e7 100644 --- a/components/app_trace/sys_view/esp/SEGGER_RTT_esp.c +++ b/components/app_trace/sys_view/esp/SEGGER_RTT_esp.c @@ -35,7 +35,7 @@ static uint8_t s_down_buf[SYSVIEW_DOWN_BUF_SIZE]; #if CONFIG_APPTRACE_SV_DEST_UART #define ESP_APPTRACE_DEST_SYSVIEW ESP_APPTRACE_DEST_UART -#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_FREERTOS_UNICORE +#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #define APPTRACE_SV_DEST_CPU 0 #else #define APPTRACE_SV_DEST_CPU 1 @@ -296,7 +296,7 @@ int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* p * linked whenever SystemView is used. */ -ESP_SYSTEM_INIT_FN(sysview_init, BIT(0), 120) +ESP_SYSTEM_INIT_FN(sysview_init, SECONDARY, BIT(0), 120) { SEGGER_SYSVIEW_Conf(); return ESP_OK; diff --git a/components/app_update/esp_ota_ops.c b/components/app_update/esp_ota_ops.c index 2b76f7b69a5..52bba6c4987 100644 --- a/components/app_update/esp_ota_ops.c +++ b/components/app_update/esp_ota_ops.c @@ -31,24 +31,6 @@ #include "esp_bootloader_desc.h" #include "esp_flash.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32C3 -#include "esp32c3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32C2 -#include "esp32c2/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32C6 -#include "esp32c6/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H2 -#include "esp32h2/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32P4 -#include "esp32p4/rom/secure_boot.h" -#endif - #define SUB_TYPE_ID(i) (i & 0x0F) /* Partial_data is word aligned so no reallocation is necessary for encrypted flash write */ @@ -199,13 +181,18 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size) return ESP_ERR_INVALID_ARG; } + if (size == 0) { + ESP_LOGD(TAG, "write data size is 0"); + return ESP_OK; + } + // find ota handle in linked list for (it = LIST_FIRST(&s_ota_ops_entries_head); it != NULL; it = LIST_NEXT(it, entries)) { if (it->handle == handle) { if (it->need_erase) { // must erase the partition before writing to it - uint32_t first_sector = it->wrote_size / SPI_FLASH_SEC_SIZE; - uint32_t last_sector = (it->wrote_size + size) / SPI_FLASH_SEC_SIZE; + uint32_t first_sector = it->wrote_size / SPI_FLASH_SEC_SIZE; // first affected sector + uint32_t last_sector = (it->wrote_size + size - 1) / SPI_FLASH_SEC_SIZE; // last affected sector ret = ESP_OK; if ((it->wrote_size % SPI_FLASH_SEC_SIZE) == 0) { @@ -960,6 +947,7 @@ esp_err_t esp_ota_revoke_secure_boot_public_key(esp_ota_secure_boot_public_key_i } const esp_partition_t *running_app_part = esp_ota_get_running_partition(); + esp_err_t ret = ESP_FAIL; #ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE esp_ota_img_states_t running_app_state; ret = esp_ota_get_state_partition(running_app_part, &running_app_state); @@ -974,7 +962,7 @@ esp_err_t esp_ota_revoke_secure_boot_public_key(esp_ota_secure_boot_public_key_i #endif esp_secure_boot_key_digests_t trusted_keys; - esp_err_t ret = esp_secure_boot_read_key_digests(&trusted_keys); + ret = esp_secure_boot_read_key_digests(&trusted_keys); if (ret != ESP_OK) { ESP_LOGE(TAG, "Could not read the secure boot key digests from efuse. Aborting.."); return ESP_FAIL; diff --git a/components/app_update/include/esp_ota_ops.h b/components/app_update/include/esp_ota_ops.h index baad1a2157f..7ff948b25d1 100644 --- a/components/app_update/include/esp_ota_ops.h +++ b/components/app_update/include/esp_ota_ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,7 +111,7 @@ esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp * @param size Size of data buffer in bytes. * * @return - * - ESP_OK: Data was written to flash successfully. + * - ESP_OK: Data was written to flash successfully, or size = 0 * - ESP_ERR_INVALID_ARG: handle is invalid. * - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte. * - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed. diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index ccccee451b7..1e698db89ea 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -105,7 +105,6 @@ menu "Bootloader config" config BOOTLOADER_FLASH_XMC_SUPPORT bool "Enable the support for flash chips of XMC (READ DOCS FIRST)" default y - depends on !IDF_ENV_BRINGUP help Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow. XMC chips will be forbidden to be used, when this option is disabled. @@ -833,7 +832,6 @@ menu "Security features" bool "Enable flash encryption on boot (READ DOCS FIRST)" default N select SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE - select NVS_ENCRYPTION help If this option is set, flash contents will be encrypted by the bootloader on first boot. @@ -1072,6 +1070,22 @@ menu "Security features" DIS_DOWNLOAD_MANUAL_ENCRYPT, DIS_USB_JTAG, DIS_USB_SERIAL_JTAG, STRAP_JTAG_SEL, USB_PHY_SEL. endmenu # Potentially Insecure + config SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART + bool "Encrypt only the app image that is present in the partition of type app" + depends on SECURE_FLASH_ENC_ENABLED && !SECURE_FLASH_REQUIRE_ALREADY_ENABLED + default y + help + If set (default), optimise encryption time for the partition of type APP, + by only encrypting the app image that is present in the partition, + instead of the whole partition. + The image length used for encryption is derived from the image metadata, which + includes the size of the app image, checksum, hash and also the signature sector + when secure boot is enabled. + + If not set, the whole partition of type APP would be encrypted, + which increases the encryption time but might be useful if there + is any custom data appended to the firmware image. + config SECURE_FLASH_CHECK_ENC_EN_IN_APP bool "Check Flash Encryption enabled on app startup" depends on SECURE_FLASH_ENC_ENABLED diff --git a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld index 14d68cf7770..e430d04575c 100644 --- a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld @@ -9,9 +9,9 @@ * Make sure the bootloader can load into main memory without overwriting itself. * * ESP32-P4 ROM static data usage is as follows: - * - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only - * - 0x4087c610 - 0x4087e610: CPU1 stack, can be reclaimed as heap after RTOS startup - * - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable) + * - 0x4ff296b8 - 0x4ff3afc0: Shared buffers, used in UART/USB/SPI download mode only + * - 0x4ff3afc0 - 0x4ff3fba4: CPU1 stack, can be reclaimed as heap after RTOS startup + * - 0x4ff3fba4 - 0x4ff40000: ROM .bss and .data (not easily reclaimable) * * The 2nd stage bootloader can take space up to the end of ROM shared * buffers area (0x4087c610). @@ -217,34 +217,38 @@ SECTIONS /** * Appendix: Memory Usage of ROM bootloader * - * 0x4086ad08 ------------------> _dram0_0_start + * 0x4ff296b8 ------------------> _dram0_0_start * | | * | | * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h * | | * | | - * 0x4087c610 ------------------> __stack_sentry + * 0x4ff3afc0 ------------------> __stack_sentry * | | * | | 2. Startup pro cpu stack (freed when IDF app is running) * | | - * 0x4087e610 ------------------> __stack (pro cpu) + * 0x4ff3cfc0 ------------------> __stack (pro cpu) + * | | + * | | Startup app cpu stack + * | | + * 0x4ff3efc0 ------------------> __stack_app (app cpu) * | | * | | * | | 3. Shared memory only used in startup code or nonos/early boot* * | | (can be freed when IDF runs) * | | * | | - * 0x4087f564 ------------------> _dram0_rtos_reserved_start + * 0x4ff3fba4 ------------------> _dram0_rtos_reserved_start * | | * | | * | | 4. Shared memory used in startup code and when IDF runs * | | * | | - * 0x4087fab0 ------------------> _dram0_rtos_reserved_end + * 0x4ff3ff94 ------------------> _dram0_rtos_reserved_end * | | - * 0x4087fce8 ------------------> _data_start_interface + * 0x4ff3ffc8 ------------------> _data_start_interface * | | * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) * | | - * 0x40880000 ------------------> _data_end_interface + * 0x4ff40000 ------------------> _data_end_interface */ diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/bootloader_support/include/bootloader_memory_utils.h b/components/bootloader_support/include/bootloader_memory_utils.h index d2134843a27..bb81697a89f 100644 --- a/components/bootloader_support/include/bootloader_memory_utils.h +++ b/components/bootloader_support/include/bootloader_memory_utils.h @@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) { */ __attribute__((always_inline)) inline static bool esp_ptr_in_iram(const void *p) { -#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE +#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH); #else return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH); diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 33990e65cd3..e4df425b462 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -21,6 +21,7 @@ typedef enum { ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */ ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */ ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */ + ESP_CHIP_ID_ESP32C5 = 0x0013, /*!< chip ID: ESP32-C5 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h index 9250ca0bd57..fdb757db3bb 100644 --- a/components/bootloader_support/include/esp_secure_boot.h +++ b/components/bootloader_support/include/esp_secure_boot.h @@ -15,6 +15,24 @@ #include "esp_rom_crc.h" #include "hal/efuse_ll.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/secure_boot.h" +#endif + #ifdef CONFIG_SECURE_BOOT_V1_ENABLED #if !defined(CONFIG_SECURE_SIGNED_ON_BOOT) || !defined(CONFIG_SECURE_SIGNED_ON_UPDATE) || !defined(CONFIG_SECURE_SIGNED_APPS) #error "internal sdkconfig error, secure boot should always enable all signature options" @@ -192,6 +210,24 @@ typedef struct { esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig_block_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest); #if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300 + +#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT + +/** @brief Verify the secure boot signature block for Secure Boot V2. + * + * Performs RSA-PSS or ECDSA verification of the SHA-256 image based on the public key + * in the signature block, compared against the public key digest stored in efuse. + * + * Similar to esp_secure_boot_verify_signature(), but can be used when the digest is precalculated. + * @param[in] sig_block Pointer to signature block data + * @param[in] image_digest Pointer to 32 byte buffer holding SHA-256 hash. + * @param[out] verified_digest Pointer to 32 byte buffer that will receive verified digest if verification completes. (Used during bootloader implementation only, result is invalid otherwise.) + * + */ +esp_err_t esp_secure_boot_verify_sbv2_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest); + +#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */ + /** * @brief Structure to hold public key digests calculated from the signature blocks of a single image. * diff --git a/components/bootloader_support/private_include/bootloader_signature.h b/components/bootloader_support/private_include/bootloader_signature.h index 3582db60647..1821995c7ad 100644 --- a/components/bootloader_support/private_include/bootloader_signature.h +++ b/components/bootloader_support/private_include/bootloader_signature.h @@ -31,19 +31,6 @@ #if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT -/** @brief Verify the secure boot signature block for Secure Boot V2. - * - * Performs RSA-PSS or ECDSA verification of the SHA-256 image based on the public key - * in the signature block, compared against the public key digest stored in efuse. - * - * Similar to esp_secure_boot_verify_signature(), but can be used when the digest is precalculated. - * @param sig_block Pointer to signature block data - * @param image_digest Pointer to 32 byte buffer holding SHA-256 hash. - * @param verified_digest Pointer to 32 byte buffer that will receive verified digest if verification completes. (Used during bootloader implementation only, result is invalid otherwise.) - * - */ -esp_err_t esp_secure_boot_verify_sbv2_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest); - /** @brief Legacy function to verify RSA secure boot signature block for Secure Boot V2. * * @note This is kept for backward compatibility. It internally calls esp_secure_boot_verify_sbv2_signature_block. diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 086394a876b..f248434e59b 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -38,6 +38,7 @@ void bootloader_console_init(void) void bootloader_console_init(void) { const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM; + int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV // Install rom uart printf as console. esp_rom_install_uart_printf(); @@ -59,8 +60,8 @@ void bootloader_console_init(void) uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM || uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) { // Change default UART pins back to GPIOs - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, PIN_FUNC_GPIO); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[UART_NUM_0_RXD_DIRECT_GPIO_NUM], PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[UART_NUM_0_TXD_DIRECT_GPIO_NUM], PIN_FUNC_GPIO); // Route GPIO signals to/from pins const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX); const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX); @@ -71,7 +72,11 @@ void bootloader_console_init(void) esp_rom_gpio_connect_in_signal(uart_rx_gpio, rx_idx, 0); gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[uart_tx_gpio], PIN_FUNC_GPIO); // Enable the peripheral - periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + uart_num); + uart_ll_enable_bus_clock(uart_num, true); + uart_ll_reset_register(uart_num); + // Reset TX and RX FIFOs + uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num)); + uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num)); } #endif // CONFIG_ESP_CONSOLE_UART_CUSTOM @@ -80,7 +85,6 @@ void bootloader_console_init(void) #if ESP_ROM_UART_CLK_IS_XTAL clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM #endif - int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); } #endif // CONFIG_ESP_CONSOLE_UART @@ -102,6 +106,7 @@ void bootloader_console_init(void) esp_rom_uart_set_as_console(ESP_ROM_USB_OTG_NUM); esp_rom_install_channel_putc(1, bootloader_console_write_char_usb); #if SOC_USB_SERIAL_JTAG_SUPPORTED + usb_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true); usb_phy_ll_int_otg_enable(&USB_WRAP); #endif } diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index a68e57543bd..796417016f6 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -103,7 +103,7 @@ void bootloader_print_banner(void) #endif } -#if CONFIG_FREERTOS_UNICORE +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #if (SOC_CPU_CORES_NUM > 1) ESP_EARLY_LOGW(TAG, "Unicore bootloader"); #endif diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index ea3f37531ba..a1e688f67e4 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -17,34 +17,27 @@ #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" #include "esp32/rom/cache.h" -#include "esp32/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/efuse.h" #include "esp32c3/rom/crc.h" #include "esp32c3/rom/uart.h" -#include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/efuse.h" #include "esp32c2/rom/crc.h" #include "esp32c2/rom/rtc.h" #include "esp32c2/rom/uart.h" -#include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/efuse.h" #include "esp32c6/rom/crc.h" #include "esp32c6/rom/rtc.h" #include "esp32c6/rom/uart.h" -#include "esp32c6/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/efuse.h" #include "esp32h2/rom/crc.h" #include "esp32h2/rom/rtc.h" #include "esp32h2/rom/uart.h" -#include "esp32h2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32P4 #else // CONFIG_IDF_TARGET_* @@ -884,7 +877,7 @@ static void set_cache_and_start_app( bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size); cache_ll_l1_enable_bus(0, bus_mask); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size); cache_ll_l1_enable_bus(1, bus_mask); bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size); diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index fd6441023b7..18b1b107188 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -44,15 +44,15 @@ static void bootloader_reset_mmu(void) { /* completely reset MMU in case serial bootloader was running */ Cache_Read_Disable(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE Cache_Read_Disable(1); #endif Cache_Flush(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE Cache_Flush(1); #endif mmu_init(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are necessary to work around a hardware bug. */ DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR); @@ -63,7 +63,7 @@ static void bootloader_reset_mmu(void) /* normal ROM boot exits with DROM0 cache unmasked, but serial bootloader exits with it masked. */ DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0); #endif } @@ -104,7 +104,7 @@ static void wdt_reset_info_dump(int cpu) lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG); lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG); } else { -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG); pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG); inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG); @@ -154,7 +154,7 @@ static void bootloader_check_wdt_reset(void) if (wdt_rst) { // if reset by WDT dump info from trace port wdt_reset_info_dump(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE wdt_reset_info_dump(1); #endif } diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index aa515759ec9..d0d841fd8ce 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -72,7 +72,7 @@ static void bootloader_check_wdt_reset(void) if (wdt_rst) { // if reset by WDT dump info from trace port wdt_reset_info_dump(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE wdt_reset_info_dump(1); #endif } diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index 368aa648b4d..8151769ea71 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -70,7 +70,7 @@ static void wdt_reset_info_dump(int cpu) lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG); lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG); } else { -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG); dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG); data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG); @@ -115,7 +115,7 @@ static void bootloader_check_wdt_reset(void) if (wdt_rst) { // if reset by WDT dump info from trace port wdt_reset_info_dump(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE wdt_reset_info_dump(1); #endif } diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index e45c6c2d7ec..0e9928d0aff 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -22,26 +21,14 @@ #include "bootloader_memory_utils.h" #include "soc/soc_caps.h" #include "hal/cache_ll.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32C3 -#include "esp32c3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" -#include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/rtc.h" -#include "esp32c6/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/rtc.h" -#include "esp32h2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32P4 #include "esp32p4/rom/rtc.h" -#include "esp32p4/rom/secure_boot.h" #endif #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) @@ -932,9 +919,13 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han return ESP_ERR_IMAGE_INVALID; } -#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME || CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME // Adjust image length result to include the appended signature +#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME || CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME data->image_len = end - data->start_addr + sizeof(ets_secure_boot_signature_t); +#elif defined(CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME) + if (data->start_addr != ESP_BOOTLOADER_OFFSET) { + data->image_len = end - data->start_addr + sizeof(esp_secure_boot_sig_block_t); + } #endif #endif // SECURE_BOOT_CHECK_SIGNATURE diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c index 40f70a86588..27f10317cb9 100644 --- a/components/bootloader_support/src/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encrypt.c @@ -137,16 +137,14 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void) } #else if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT) -#if CONFIG_IDF_TARGET_ESP32P4 - //TODO: IDF-7545 +#if SOC_EFUSE_DIS_DOWNLOAD_MSPI && esp_efuse_read_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS) -#else +#endif #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE) #endif #if SOC_EFUSE_DIS_DOWNLOAD_DCACHE && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE) -#endif #endif ) { mode = ESP_FLASH_ENC_MODE_RELEASE; @@ -192,17 +190,15 @@ void esp_flash_encryption_set_release_mode(void) esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_DECRYPT); #else esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); -#if CONFIG_IDF_TARGET_ESP32P4 - //TODO: IDF-7545 +#if SOC_EFUSE_DIS_DOWNLOAD_MSPI esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS); -#else +#endif #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); #endif #if SOC_EFUSE_DIS_DOWNLOAD_DCACHE esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE); #endif -#endif #ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED // For AES128_DERIVED, FE key is 16 bytes and XTS_KEY_LENGTH_256 is 0. // It is important to protect XTS_KEY_LENGTH_256 from further changing it to 1. Set write protection for this bit. @@ -345,14 +341,13 @@ bool esp_flash_encryption_cfg_verify_release_mode(void) } #endif -#if CONFIG_IDF_TARGET_ESP32P4 - //TODO: IDF-7545 +#if SOC_EFUSE_DIS_DOWNLOAD_MSPI secure = esp_efuse_read_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS); result &= secure; if (!secure) { ESP_LOGW(TAG, "Not disabled UART bootloader download mspi (set DIS_DOWNLOAD_MSPI->1)"); } -#else +#endif #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); result &= secure; @@ -360,7 +355,6 @@ bool esp_flash_encryption_cfg_verify_release_mode(void) ESP_LOGW(TAG, "Not disabled UART bootloader cache (set DIS_DOWNLOAD_ICACHE->1)"); } #endif -#endif #if SOC_EFUSE_DIS_PAD_JTAG secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_PAD_JTAG); diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c index daf920564a0..8bd1352b738 100644 --- a/components/bootloader_support/src/flash_encryption/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encryption/flash_encrypt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,11 @@ #include "esp_efuse_table.h" #include "esp_log.h" #include "hal/wdt_hal.h" + +#if CONFIG_IDF_TARGET_ESP32P4 //TODO-IDF-7925 +#include "soc/keymng_reg.h" +#endif + #ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK #include "soc/sensitive_reg.h" #endif @@ -209,6 +214,12 @@ static esp_err_t check_and_generate_encryption_keys(void) } ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse"); } + +#if CONFIG_IDF_TARGET_ESP32P4 //TODO - IDF-7925 + // Force Key Manager to use eFuse key for XTS-AES operation + REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2); +#endif + return ESP_OK; } @@ -393,14 +404,21 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit { esp_err_t err; bool should_encrypt = (partition->flags & PART_FLAG_ENCRYPTED); + uint32_t size = partition->pos.size; if (partition->type == PART_TYPE_APP) { /* check if the partition holds a valid unencrypted app */ - esp_image_metadata_t data_ignored; + esp_image_metadata_t image_data = {}; err = esp_image_verify(ESP_IMAGE_VERIFY, &partition->pos, - &data_ignored); + &image_data); should_encrypt = (err == ESP_OK); +#ifdef SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART + if (should_encrypt) { + // Encrypt only the app image instead of encrypting the whole partition + size = image_data.image_len; + } +#endif } else if ((partition->type == PART_TYPE_DATA && partition->subtype == PART_SUBTYPE_DATA_OTA) || (partition->type == PART_TYPE_DATA && partition->subtype == PART_SUBTYPE_DATA_NVS_KEYS)) { /* check if we have ota data partition and the partition should be encrypted unconditionally */ @@ -411,9 +429,9 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit return ESP_OK; } else { /* should_encrypt */ - ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%x (length 0x%x)...", index, partition->pos.offset, partition->pos.size); + ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%x (length 0x%x)...", index, partition->pos.offset, size); - err = esp_flash_encrypt_region(partition->pos.offset, partition->pos.size); + err = esp_flash_encrypt_region(partition->pos.offset, size); ESP_LOGI(TAG, "Done encrypting"); if (err != ESP_OK) { ESP_LOGE(TAG, "Failed to encrypt partition %d", index); diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml index 701cbd55187..1dbe91f9132 100644 --- a/components/bootloader_support/test_apps/.build-test-rules.yml +++ b/components/bootloader_support/test_apps/.build-test-rules.yml @@ -4,7 +4,3 @@ components/bootloader_support/test_apps/rtc_custom_section: enable: - if: SOC_RTC_MEM_SUPPORTED == 1 reason: this feature is supported on chips that have RTC memory - disable: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: this feature on esp32p4 isn't supported yet # TODO: IDF-8069 diff --git a/components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c b/components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c index 0db667699a7..d927a66e454 100644 --- a/components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c +++ b/components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c @@ -22,7 +22,7 @@ #include "esp_ota_ops.h" #include "esp_image_format.h" -TEST_CASE("Verify bootloader image in flash", "[bootloader_support][qemu-ignore-c3]") +TEST_CASE("Verify bootloader image in flash", "[bootloader_support]") { const esp_partition_pos_t fake_bootloader_partition = { .offset = ESP_BOOTLOADER_OFFSET, @@ -37,7 +37,7 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support][qemu-ignore- TEST_ASSERT_EQUAL(data.image_len, bootloader_length); } -TEST_CASE("Verify unit test app image", "[bootloader_support][qemu-ignore-c3]") +TEST_CASE("Verify unit test app image", "[bootloader_support]") { esp_image_metadata_t data = { 0 }; const esp_partition_t *running = esp_ota_get_running_partition(); diff --git a/components/bootloader_support/test_apps/rtc_custom_section/README.md b/components/bootloader_support/test_apps/rtc_custom_section/README.md index 19f1d19a549..a79fcf4c5ea 100644 --- a/components/bootloader_support/test_apps/rtc_custom_section/README.md +++ b/components/bootloader_support/test_apps/rtc_custom_section/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py b/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py index 89e457af4fd..7016cd6b94a 100644 --- a/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py +++ b/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py @@ -12,5 +12,6 @@ @pytest.mark.esp32h2 @pytest.mark.esp32s2 @pytest.mark.esp32s3 +@pytest.mark.esp32p4 def test_rtc_reserved_memory(dut: Dut) -> None: dut.expect_exact('SUCCESS: data were saved across reboot', timeout=10) diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 80395ed0295..b950d79dbd3 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -45,10 +45,10 @@ set(ble_mesh_include_dirs "esp_ble_mesh/api/core/include" "esp_ble_mesh/api/models/include" "esp_ble_mesh/api" + "esp_ble_mesh/lib/include" "esp_ble_mesh/v1.1/api/core/include" "esp_ble_mesh/v1.1/api/models/include" "esp_ble_mesh/v1.1/btc/include" - "esp_ble_mesh/v1.1/include" ) set(bluedroid_include_dirs host/bluedroid/api/include/api) @@ -550,7 +550,7 @@ if(CONFIG_BT_ENABLED) "esp_ble_mesh/v1.1/btc/btc_ble_mesh_rpr_model.c" "esp_ble_mesh/v1.1/btc/btc_ble_mesh_sar_model.c" "esp_ble_mesh/v1.1/btc/btc_ble_mesh_srpl_model.c" - "esp_ble_mesh/v1.1/ext.c") + "esp_ble_mesh/lib/ext.c") if(CONFIG_BLE_MESH_SAR_ENHANCEMENT) list(APPEND srcs "esp_ble_mesh/core/transport.enh.c") @@ -621,6 +621,8 @@ if(CONFIG_BT_ENABLED) host/nimble/nimble/nimble/host/services/prox/include host/nimble/nimble/nimble/host/services/cts/include host/nimble/nimble/nimble/host/services/tps/include + host/nimble/nimble/nimble/host/services/hid/include + host/nimble/nimble/nimble/host/services/sps/include host/nimble/nimble/nimble/host/util/include host/nimble/nimble/nimble/host/store/ram/include host/nimble/nimble/nimble/host/store/config/include @@ -641,6 +643,8 @@ if(CONFIG_BT_ENABLED) "host/nimble/nimble/nimble/host/services/lls/src/ble_svc_lls.c" "host/nimble/nimble/nimble/host/services/prox/src/ble_svc_prox.c" "host/nimble/nimble/nimble/host/services/cts/src/ble_svc_cts.c" + "host/nimble/nimble/nimble/host/services/hid/src/ble_svc_hid.c" + "host/nimble/nimble/nimble/host/services/sps/src/ble_svc_sps.c" "host/nimble/nimble/nimble/host/src/ble_hs_conn.c" "host/nimble/nimble/nimble/host/src/ble_store_util.c" "host/nimble/nimble/nimble/host/src/ble_sm.c" @@ -785,7 +789,7 @@ idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "${include_dirs}" PRIV_INCLUDE_DIRS "${priv_include_dirs}" REQUIRES esp_timer esp_wifi - PRIV_REQUIRES nvs_flash soc esp_pm esp_phy esp_coex mbedtls driver vfs + PRIV_REQUIRES nvs_flash soc esp_pm esp_phy esp_coex mbedtls esp_driver_uart vfs esp_ringbuf LDFRAGMENTS "${ldfragments}") if(CONFIG_BT_ENABLED) @@ -826,20 +830,20 @@ endif() if(CONFIG_BLE_MESH) if(CONFIG_IDF_TARGET_ESP32) - add_prebuilt_library(mesh_v11 "esp_ble_mesh/v1.1/lib/esp32/libmesh_v1.1.a") - target_link_libraries(${COMPONENT_LIB} PRIVATE mesh_v11) + add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32/libble_mesh.a") + target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh) elseif(CONFIG_IDF_TARGET_ESP32S3) - add_prebuilt_library(mesh_v11 "esp_ble_mesh/v1.1/lib/esp32s3/libmesh_v1.1.a") - target_link_libraries(${COMPONENT_LIB} PRIVATE mesh_v11) + add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32s3/libble_mesh.a") + target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh) elseif(CONFIG_IDF_TARGET_ESP32C3) - add_prebuilt_library(mesh_v11 "esp_ble_mesh/v1.1/lib/esp32c3/libmesh_v1.1.a") - target_link_libraries(${COMPONENT_LIB} PRIVATE mesh_v11) + add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32c3/libble_mesh.a") + target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh) elseif(CONFIG_IDF_TARGET_ESP32C6) - add_prebuilt_library(mesh_v11 "esp_ble_mesh/v1.1/lib/esp32c6/libmesh_v1.1.a") - target_link_libraries(${COMPONENT_LIB} PRIVATE mesh_v11) + add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32c6/libble_mesh.a") + target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh) elseif(CONFIG_IDF_TARGET_ESP32H2) - add_prebuilt_library(mesh_v11 "esp_ble_mesh/v1.1/lib/esp32h2/libmesh_v1.1.a") - target_link_libraries(${COMPONENT_LIB} PRIVATE mesh_v11) + add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32h2/libble_mesh.a") + target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh) endif() endif() diff --git a/components/bt/common/osi/config.c b/components/bt/common/osi/config.c index 02d6345a579..fb6727a7a3d 100644 --- a/components/bt/common/osi/config.c +++ b/components/bt/common/osi/config.c @@ -264,13 +264,13 @@ bool config_update_newest_section(config_t *config, const char *section) return false; } section_t *first_sec = list_node(first_node); - if (!strcmp(first_sec->name, section)) { + if (strcmp(first_sec->name, section) == 0) { return true; } for (const list_node_t *node = list_begin(config->sections); node != list_end(config->sections); node = list_next(node)) { section_t *sec = list_node(node); - if (!strcmp(sec->name, section)) { + if (strcmp(sec->name, section) == 0) { list_delete(config->sections, sec); list_prepend(config->sections, sec); return true; diff --git a/components/bt/controller/esp32/bt.c b/components/bt/controller/esp32/bt.c index 2a8c553b9e2..d8792e0f486 100644 --- a/components/bt/controller/esp32/bt.c +++ b/components/bt/controller/esp32/bt.c @@ -16,8 +16,8 @@ #include "freertos/task.h" #include "freertos/queue.h" #include "freertos/semphr.h" -#include "freertos/xtensa_api.h" #include "freertos/portmacro.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) #include "xtensa/core-macros.h" #include "esp_types.h" #include "esp_mac.h" @@ -1197,23 +1197,12 @@ static int coex_register_wifi_channel_change_callback_wrapper(void *cb) static int coex_version_get_wrapper(unsigned int *major, unsigned int *minor, unsigned int *patch) { #if CONFIG_SW_COEXIST_ENABLE - const char *ver_str = esp_coex_version_get(); - if (ver_str != NULL) { - unsigned int _major = 0, _minor = 0, _patch = 0; - if (sscanf(ver_str, "%u.%u.%u", &_major, &_minor, &_patch) != 3) { - return -1; - } - if (major != NULL) { - *major = _major; - } - if (minor != NULL) { - *minor = _minor; - } - if (patch != NULL) { - *patch = _patch; - } - return 0; - } + coex_version_t version; + ESP_ERROR_CHECK(coex_version_get_value(&version)); + *major = (unsigned int)version.major; + *minor = (unsigned int)version.minor; + *patch = (unsigned int)version.patch; + return 0; #endif return -1; } diff --git a/components/bt/controller/esp32/hli_vectors.S b/components/bt/controller/esp32/hli_vectors.S index 7e0cd528fe7..2af6ffae7c4 100644 --- a/components/bt/controller/esp32/hli_vectors.S +++ b/components/bt/controller/esp32/hli_vectors.S @@ -8,7 +8,7 @@ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "sdkconfig.h" #include "soc/soc.h" diff --git a/components/bt/controller/esp32c2/Kconfig.in b/components/bt/controller/esp32c2/Kconfig.in index 8c6a97fee8f..f834701471c 100644 --- a/components/bt/controller/esp32c2/Kconfig.in +++ b/components/bt/controller/esp32c2/Kconfig.in @@ -253,7 +253,7 @@ config BT_LE_CONTROLLER_TASK_STACK_SIZE help This configures stack size of NimBLE controller task -config BT_LE_CONTROLLER_LOG_ENABLED +menuconfig BT_LE_CONTROLLER_LOG_ENABLED bool "Controller log enable" default n help @@ -264,21 +264,42 @@ config BT_LE_CONTROLLER_LOG_CTRL_ENABLED depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Enable controller log module + Enable controller log module config BT_LE_CONTROLLER_LOG_HCI_ENABLED bool "enable HCI log module" depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Enable hci log module + Enable hci log module config BT_LE_CONTROLLER_LOG_DUMP_ONLY bool "Controller log dump mode only" depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Only operate in dump mode + Only operate in dump mode + +config BT_LE_LOG_CTRL_BUF1_SIZE + int "size of the first BLE controller LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 4096 + help + Configure the size of the first BLE controller LOG buffer. + +config BT_LE_LOG_CTRL_BUF2_SIZE + int "size of the second BLE controller LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 1024 + help + Configure the size of the second BLE controller LOG buffer. + +config BT_LE_LOG_HCI_BUF_SIZE + int "size of the BLE HCI LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 4096 + help + Configure the size of the BLE HCI LOG buffer. config BT_LE_LL_RESOLV_LIST_SIZE int "BLE LL Resolving list size" @@ -443,3 +464,23 @@ config BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD config BT_LE_RELEASE_IRAM_SUPPORTED bool default y + +config BT_LE_TX_CCA_ENABLED + bool "BLE enable TX CCA feature" + default n + help + Enable the BLE (Bluetooth Low Energy) LBT (Listen Before Talk) function. Before transmitting a packet, + monitor the in-band CCA (Clear Channel Assessment). If the airborne carrier energy is too high, abandon + the packet transmission. Enabling this feature may potentially decrease BLE performance. In certain + countries and regions, when the maximum transmission power exceeds a certain limit, support for LBT + interference avoidance mechanisms is required. If the maximum transmission power does not reach the limit, + it may not be necessary to enable this function. + Please refer to the relevant certification regulations for details. + +config BT_LE_CCA_RSSI_THRESH + int "Power threshold to refrain packet transmission in unit of -1 dBm" + depends on BT_LE_TX_CCA_ENABLED + range 1 100 + default 75 + help + If a carrier signal above the threshold is detected in the air, refrain from packet transmission. diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index c78cef1e2b9..e06655269ea 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -78,7 +78,6 @@ #define ACL_DATA_MBUF_LEADINGSPCAE 4 #endif // CONFIG_BT_BLUEDROID_ENABLED - /* Types definition ************************************************************************ */ @@ -127,6 +126,7 @@ extern int ble_controller_init(esp_bt_controller_config_t *cfg); extern int ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size); extern int ble_log_deinit_async(void); extern void ble_log_async_output_dump_all(bool output); +extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED extern int ble_controller_deinit(void); extern int ble_controller_enable(uint8_t mode); @@ -201,7 +201,7 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -const static uint32_t log_bufs_size[] = {2048, 1024, 1024}; +const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE}; #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED /* This variable tells if BLE is running */ @@ -644,6 +644,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) coex_init(); #endif + ret = ble_controller_init(cfg); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); + goto modem_deint; + } + #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED interface_func_t bt_controller_log_interface; bt_controller_log_interface = esp_bt_controller_log_interface; @@ -661,16 +667,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) #endif // CONFIG_BT_CONTROLLER_LOG_DUMP if (ret != ESP_OK) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret); - goto modem_deint; + goto controller_init_err; } #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED - ret = ble_controller_init(cfg); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); - goto modem_deint; - } - ret = controller_sleep_init(); if (ret != ESP_OK) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret); @@ -691,11 +691,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) return ESP_OK; free_controller: controller_sleep_deinit(); - ble_controller_deinit(); -modem_deint: #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED +controller_init_err: ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED + ble_controller_deinit(); +modem_deint: esp_phy_modem_deinit(); periph_module_disable(PERIPH_BT_MODULE); #if CONFIG_BT_NIMBLE_ENABLED @@ -1012,9 +1013,10 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b void esp_ble_controller_log_dump_all(bool output) { - portMUX_TYPE spinlock; + portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED; portENTER_CRITICAL_SAFE(&spinlock); + esp_panic_handler_reconfigure_wdts(5000); BT_ASSERT_PRINT("\r\n[DUMP_START:"); ble_log_async_output_dump_all(output); BT_ASSERT_PRINT("]\r\n"); diff --git a/components/bt/controller/esp32c2/esp_bt_cfg.h b/components/bt/controller/esp32c2/esp_bt_cfg.h index 1e44212071c..308d79e3eb0 100644 --- a/components/bt/controller/esp32c2/esp_bt_cfg.h +++ b/components/bt/controller/esp32c2/esp_bt_cfg.h @@ -40,6 +40,11 @@ extern "C" { #define DEFAULT_BT_NIMBLE_WHITELIST_SIZE MYNEWT_VAL(BLE_LL_WHITELIST_SIZE) #define DEFAULT_BT_LE_HCI_EVT_HI_BUF_COUNT MYNEWT_VAL(BLE_TRANSPORT_EVT_COUNT) #define DEFAULT_BT_LE_HCI_EVT_LO_BUF_COUNT MYNEWT_VAL(BLE_TRANSPORT_EVT_DISCARDABLE_COUNT) + #if defined(CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT) + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) + #else + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) + #endif #else @@ -114,6 +119,11 @@ extern "C" { #else #define DEFAULT_BT_LE_HCI_EVT_LO_BUF_COUNT (8) #endif + #if defined(CONFIG_BT_LE_50_FEATURE_SUPPORT) + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) + #else + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) + #endif #endif diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 66764b5b421..6dabe7fb24c 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -43,8 +43,6 @@ #include "riscv/interrupt.h" #include "esp32c3/rom/rom_layout.h" #else //CONFIG_IDF_TARGET_ESP32S3 -#include "freertos/xtensa_api.h" -#include "xtensa/core-macros.h" #include "esp32s3/rom/rom_layout.h" #endif #if CONFIG_BT_ENABLED diff --git a/components/bt/controller/esp32c5/Kconfig.in b/components/bt/controller/esp32c5/Kconfig.in new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/bt/controller/esp32c6/Kconfig.in b/components/bt/controller/esp32c6/Kconfig.in index 41619efd334..560e5ada4e7 100644 --- a/components/bt/controller/esp32c6/Kconfig.in +++ b/components/bt/controller/esp32c6/Kconfig.in @@ -269,7 +269,7 @@ config BT_LE_CONTROLLER_TASK_STACK_SIZE help This configures stack size of NimBLE controller task -config BT_LE_CONTROLLER_LOG_ENABLED +menuconfig BT_LE_CONTROLLER_LOG_ENABLED bool "Controller log enable" default n help @@ -280,21 +280,42 @@ config BT_LE_CONTROLLER_LOG_CTRL_ENABLED depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Enable controller log module + Enable controller log module config BT_LE_CONTROLLER_LOG_HCI_ENABLED bool "enable HCI log module" depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Enable hci log module + Enable hci log module config BT_LE_CONTROLLER_LOG_DUMP_ONLY bool "Controller log dump mode only" depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Only operate in dump mode + Only operate in dump mode + +config BT_LE_LOG_CTRL_BUF1_SIZE + int "size of the first BLE controller LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 4096 + help + Configure the size of the first BLE controller LOG buffer. + +config BT_LE_LOG_CTRL_BUF2_SIZE + int "size of the second BLE controller LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 1024 + help + Configure the size of the second BLE controller LOG buffer. + +config BT_LE_LOG_HCI_BUF_SIZE + int "size of the BLE HCI LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 4096 + help + Configure the size of the BLE HCI LOG buffer. config BT_LE_LL_RESOLV_LIST_SIZE int "BLE LL Resolving list size" @@ -550,3 +571,23 @@ config BT_LE_SCAN_DUPL_CACHE_REFRESH_PERIOD config BT_LE_MSYS_INIT_IN_CONTROLLER bool "Msys Mbuf Init in Controller" default y + +config BT_LE_TX_CCA_ENABLED + bool "BLE enable TX CCA feature" + default n + help + Enable the BLE (Bluetooth Low Energy) LBT (Listen Before Talk) function. Before transmitting a packet, + monitor the in-band CCA (Clear Channel Assessment). If the airborne carrier energy is too high, abandon + the packet transmission. Enabling this feature may potentially decrease BLE performance. In certain + countries and regions, when the maximum transmission power exceeds a certain limit, support for LBT + interference avoidance mechanisms is required. If the maximum transmission power does not reach the limit, + it may not be necessary to enable this function. + Please refer to the relevant certification regulations for details. + +config BT_LE_CCA_RSSI_THRESH + int "Power threshold to refrain packet transmission in unit of -1 dBm" + depends on BT_LE_TX_CCA_ENABLED + range 1 100 + default 75 + help + If a carrier signal above the threshold is detected in the air, refrain from packet transmission. diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index a58c92c99bf..c189f2c824a 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -127,6 +127,7 @@ extern int ble_log_init_async(interface_func_t bt_controller_log_interface, bool extern int ble_log_deinit_async(void); extern void ble_log_async_select_dump_buffers(uint8_t buffers); extern void ble_log_async_output_dump_all(bool output); +extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED extern int ble_controller_deinit(void); extern int ble_controller_enable(uint8_t mode); @@ -202,7 +203,7 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -const static uint32_t log_bufs_size[] = {6144, 1024, 2048}; +const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE}; #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED /* This variable tells if BLE is running */ @@ -488,9 +489,6 @@ IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) } #if CONFIG_FREERTOS_USE_TICKLESS_IDLE r_ble_rtc_wake_up_state_clr(); -#if SOC_PM_RETENTION_HAS_CLOCK_BUG - sleep_retention_do_extra_retention(true); -#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ esp_phy_disable(PHY_MODEM_BT); #ifdef CONFIG_PM_ENABLE @@ -507,9 +505,6 @@ IRAM_ATTR void controller_wakeup_cb(void *arg) #ifdef CONFIG_PM_ENABLE esp_pm_lock_acquire(s_pm_lock); r_ble_rtc_wake_up_state_clr(); -#if CONFIG_FREERTOS_USE_TICKLESS_IDLE && SOC_PM_RETENTION_HAS_CLOCK_BUG - sleep_retention_do_extra_retention(false); -#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE && SOC_PM_RETENTION_HAS_CLOCK_BUG */ #endif //CONFIG_PM_ENABLE esp_phy_enable(PHY_MODEM_BT); s_ble_active = true; @@ -570,12 +565,21 @@ esp_err_t controller_sleep_init(void) if (rc != ESP_OK) { goto error; } + +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + sleep_modem_register_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare, + sleep_modem_mac_bb_power_up_prepare); +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ return rc; error: #if CONFIG_FREERTOS_USE_TICKLESS_IDLE +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare, + sleep_modem_mac_bb_power_up_prepare); +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD esp_sleep_disable_bt_wakeup(); esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ @@ -592,6 +596,10 @@ esp_err_t controller_sleep_init(void) void controller_sleep_deinit(void) { #if CONFIG_FREERTOS_USE_TICKLESS_IDLE +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare, + sleep_modem_mac_bb_power_up_prepare); +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD r_ble_rtc_wake_up_state_clr(); esp_sleep_disable_bt_wakeup(); sleep_modem_ble_mac_modem_state_deinit(); @@ -771,6 +779,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) coex_init(); #endif // CONFIG_SW_COEXIST_ENABLE + ret = ble_controller_init(cfg); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); + goto modem_deint; + } + #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED interface_func_t bt_controller_log_interface; bt_controller_log_interface = esp_bt_controller_log_interface; @@ -788,16 +802,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) #endif // CONFIG_BT_CONTROLLER_LOG_DUMP if (ret != ESP_OK) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret); - goto modem_deint; + goto controller_init_err; } #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED - ret = ble_controller_init(cfg); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); - goto modem_deint; - } - esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); @@ -825,12 +833,13 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) free_controller: controller_sleep_deinit(); - os_msys_deinit(); - ble_controller_deinit(); -modem_deint: #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED +controller_init_err: ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED + os_msys_deinit(); + ble_controller_deinit(); +modem_deint: esp_phy_modem_deinit(); modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE); modem_clock_module_disable(PERIPH_BT_MODULE); @@ -950,11 +959,6 @@ esp_err_t esp_bt_controller_disable(void) esp_pm_lock_release(s_pm_lock); #endif // CONFIG_PM_ENABLE s_ble_active = false; - } else { -#if CONFIG_FREERTOS_USE_TICKLESS_IDLE - /* Avoid consecutive backup of register cause assertion */ - sleep_retention_module_deinit(); -#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE } ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; return ESP_OK; @@ -1182,9 +1186,10 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b void esp_ble_controller_log_dump_all(bool output) { - portMUX_TYPE spinlock; + portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED; portENTER_CRITICAL_SAFE(&spinlock); + esp_panic_handler_reconfigure_wdts(5000); BT_ASSERT_PRINT("\r\n[DUMP_START:"); ble_log_async_output_dump_all(output); BT_ASSERT_PRINT("]\r\n"); diff --git a/components/bt/controller/esp32c6/esp_bt_cfg.h b/components/bt/controller/esp32c6/esp_bt_cfg.h index 12b8f87f470..9e341e32290 100644 --- a/components/bt/controller/esp32c6/esp_bt_cfg.h +++ b/components/bt/controller/esp32c6/esp_bt_cfg.h @@ -40,6 +40,11 @@ extern "C" { #define DEFAULT_BT_LE_HCI_EVT_HI_BUF_COUNT MYNEWT_VAL(BLE_TRANSPORT_EVT_COUNT) #define DEFAULT_BT_LE_HCI_EVT_LO_BUF_COUNT MYNEWT_VAL(BLE_TRANSPORT_EVT_DISCARDABLE_COUNT) #define DEFAULT_BT_LE_POWER_CONTROL_ENABLED MYNEWT_VAL(BLE_POWER_CONTROL) + #if defined(CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT) + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) + #else + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) + #endif #else #if CONFIG_BT_LE_LL_CFG_FEAT_LE_CODED_PHY @@ -119,6 +124,11 @@ extern "C" { #else #define DEFAULT_BT_LE_POWER_CONTROL_ENABLED (0) #endif + #if defined(CONFIG_BT_LE_50_FEATURE_SUPPORT) + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) + #else + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) + #endif #endif #define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF diff --git a/components/bt/controller/esp32h2/Kconfig.in b/components/bt/controller/esp32h2/Kconfig.in index a2ff7e8b768..ee7106ad899 100644 --- a/components/bt/controller/esp32h2/Kconfig.in +++ b/components/bt/controller/esp32h2/Kconfig.in @@ -260,7 +260,7 @@ config BT_LE_CONTROLLER_TASK_STACK_SIZE help This configures stack size of NimBLE controller task -config BT_LE_CONTROLLER_LOG_ENABLED +menuconfig BT_LE_CONTROLLER_LOG_ENABLED bool "Controller log enable" default n help @@ -271,21 +271,42 @@ config BT_LE_CONTROLLER_LOG_CTRL_ENABLED depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Enable controller log module + Enable controller log module config BT_LE_CONTROLLER_LOG_HCI_ENABLED bool "enable HCI log module" depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Enable hci log module + Enable hci log module config BT_LE_CONTROLLER_LOG_DUMP_ONLY bool "Controller log dump mode only" depends on BT_LE_CONTROLLER_LOG_ENABLED default y help - Only operate in dump mode + Only operate in dump mode + +config BT_LE_LOG_CTRL_BUF1_SIZE + int "size of the first BLE controller LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 4096 + help + Configure the size of the first BLE controller LOG buffer. + +config BT_LE_LOG_CTRL_BUF2_SIZE + int "size of the second BLE controller LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 1024 + help + Configure the size of the second BLE controller LOG buffer. + +config BT_LE_LOG_HCI_BUF_SIZE + int "size of the BLE HCI LOG buffer" + depends on BT_LE_CONTROLLER_LOG_ENABLED + default 4096 + help + Configure the size of the BLE HCI LOG buffer. config BT_LE_LL_RESOLV_LIST_SIZE int "BLE LL Resolving list size" @@ -543,3 +564,23 @@ config BT_LE_SCAN_DUPL_CACHE_REFRESH_PERIOD config BT_LE_MSYS_INIT_IN_CONTROLLER bool default y + +config BT_LE_TX_CCA_ENABLED + bool "BLE enable TX CCA feature" + default n + help + Enable the BLE (Bluetooth Low Energy) LBT (Listen Before Talk) function. Before transmitting a packet, + monitor the in-band CCA (Clear Channel Assessment). If the airborne carrier energy is too high, abandon + the packet transmission. Enabling this feature may potentially decrease BLE performance. In certain + countries and regions, when the maximum transmission power exceeds a certain limit, support for LBT + interference avoidance mechanisms is required. If the maximum transmission power does not reach the limit, + it may not be necessary to enable this function. + Please refer to the relevant certification regulations for details. + +config BT_LE_CCA_RSSI_THRESH + int "Power threshold to refrain packet transmission in unit of -1 dBm" + depends on BT_LE_TX_CCA_ENABLED + range 1 100 + default 75 + help + If a carrier signal above the threshold is detected in the air, refrain from packet transmission. diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 636a9bf0320..43a4ba0199e 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -121,6 +121,7 @@ extern int ble_log_init_async(interface_func_t bt_controller_log_interface, bool extern int ble_log_deinit_async(void); extern void ble_log_async_select_dump_buffers(uint8_t buffers); extern void ble_log_async_output_dump_all(bool output); +extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED extern int ble_controller_deinit(void); extern int ble_controller_enable(uint8_t mode); @@ -196,7 +197,7 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -const static uint32_t log_bufs_size[] = {6144, 1024, 2048}; +const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE}; #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED /* This variable tells if BLE is running */ @@ -751,6 +752,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) coex_init(); #endif // CONFIG_SW_COEXIST_ENABLE + ret = ble_controller_init(cfg); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); + goto modem_deint; + } + #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED interface_func_t bt_controller_log_interface; bt_controller_log_interface = esp_bt_controller_log_interface; @@ -768,16 +775,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) #endif // CONFIG_BT_CONTROLLER_LOG_DUMP if (ret != ESP_OK) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret); - goto modem_deint; + goto controller_init_err; } #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED - ret = ble_controller_init(cfg); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); - goto modem_deint; - } - esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); @@ -806,12 +807,13 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) free_controller: controller_sleep_deinit(); - os_msys_deinit(); - ble_controller_deinit(); -modem_deint: #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED +controller_init_err: ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED + os_msys_deinit(); + ble_controller_deinit(); +modem_deint: modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE); modem_clock_module_disable(PERIPH_BT_MODULE); #if CONFIG_BT_NIMBLE_ENABLED @@ -1156,9 +1158,10 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b void esp_ble_controller_log_dump_all(bool output) { - portMUX_TYPE spinlock; + portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED; portENTER_CRITICAL_SAFE(&spinlock); + esp_panic_handler_reconfigure_wdts(5000); BT_ASSERT_PRINT("\r\n[DUMP_START:"); ble_log_async_output_dump_all(output); BT_ASSERT_PRINT("]\r\n"); diff --git a/components/bt/controller/esp32h2/esp_bt_cfg.h b/components/bt/controller/esp32h2/esp_bt_cfg.h index 12b8f87f470..c0c5801af14 100644 --- a/components/bt/controller/esp32h2/esp_bt_cfg.h +++ b/components/bt/controller/esp32h2/esp_bt_cfg.h @@ -40,6 +40,11 @@ extern "C" { #define DEFAULT_BT_LE_HCI_EVT_HI_BUF_COUNT MYNEWT_VAL(BLE_TRANSPORT_EVT_COUNT) #define DEFAULT_BT_LE_HCI_EVT_LO_BUF_COUNT MYNEWT_VAL(BLE_TRANSPORT_EVT_DISCARDABLE_COUNT) #define DEFAULT_BT_LE_POWER_CONTROL_ENABLED MYNEWT_VAL(BLE_POWER_CONTROL) + #if defined(CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT) + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) + #else + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) + #endif #else #if CONFIG_BT_LE_LL_CFG_FEAT_LE_CODED_PHY @@ -119,6 +124,12 @@ extern "C" { #else #define DEFAULT_BT_LE_POWER_CONTROL_ENABLED (0) #endif + + #if defined(CONFIG_BT_LE_50_FEATURE_SUPPORT) + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) + #else + #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) + #endif #endif #define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index cddb921d204..7ef2b1dffc6 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit cddb921d20418cef04de83ddfe3543463dfbc2bc +Subproject commit 7ef2b1dffc6f1f7845013980aa136bfe76ce5af0 diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index ea33fbad1fa..909c8bca55a 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit ea33fbad1fa0879fe0e118359d20463b3e2f126b +Subproject commit 909c8bca55acdcbba1c32620482a7d1a10c28a07 diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family index ec7ef197cb8..393ac4c33b4 160000 --- a/components/bt/controller/lib_esp32c3_family +++ b/components/bt/controller/lib_esp32c3_family @@ -1 +1 @@ -Subproject commit ec7ef197cb8018c468cd59dca893dbe018f47a2a +Subproject commit 393ac4c33b419226aac9d1e8f1b5d553b7f3bc97 diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index a763b33ce1f..8ad84d799a1 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit a763b33ce1f6bdc257947845b0520c3b44de87eb +Subproject commit 8ad84d799a194566be26e487ecfe5e634b8f4248 diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index c8018101d5a..f9b322ffdfe 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit c8018101d5a71162c220782e6c860e9ba33013c4 +Subproject commit f9b322ffdfe7cb6896ac24f59986d601766dd126 diff --git a/components/bt/esp_ble_mesh/Kconfig.in b/components/bt/esp_ble_mesh/Kconfig.in index af76b2240df..b324df84764 100644 --- a/components/bt/esp_ble_mesh/Kconfig.in +++ b/components/bt/esp_ble_mesh/Kconfig.in @@ -6,6 +6,15 @@ if BLE_MESH help It is a temporary solution and needs further modifications. + config BLE_MESH_RANDOM_ADV_INTERVAL + bool "Support using random adv interval for mesh packets" + select BT_BLE_HIGH_DUTY_ADV_INTERVAL if BT_BLUEDROID_ENABLED + default n + help + Enable this option to allow using random advertising interval + for mesh packets. And this could help avoid collision of + advertising packets. + config BLE_MESH_USE_DUPLICATE_SCAN bool "Support Duplicate Scan in BLE Mesh" select BTDM_BLE_SCAN_DUPL if IDF_TARGET_ESP32 @@ -14,6 +23,7 @@ if BLE_MESH select BT_CTRL_BLE_MESH_SCAN_DUPL_EN if IDF_TARGET_ESP32C3 select BT_LE_SCAN_DUPL if IDF_TARGET_ESP32C6 select BT_LE_SCAN_DUPL if IDF_TARGET_ESP32H2 + select BT_NIMBLE_VS_SUPPORT if BT_NIMBLE_ENABLED default y help Enable this option to allow using specific duplicate scan filter diff --git a/components/bt/esp_ble_mesh/common/common.c b/components/bt/esp_ble_mesh/common/common.c index 87f0c6a7bc3..7257db930c7 100644 --- a/components/bt/esp_ble_mesh/common/common.c +++ b/components/bt/esp_ble_mesh/common/common.c @@ -85,3 +85,8 @@ int bt_mesh_rand(void *buf, size_t len) return 0; } + +uint32_t bt_mesh_get_rand(void) +{ + return esp_random(); +} diff --git a/components/bt/esp_ble_mesh/common/include/mesh/common.h b/components/bt/esp_ble_mesh/common/include/mesh/common.h index db6c1d372a7..a1cfa673a2f 100644 --- a/components/bt/esp_ble_mesh/common/include/mesh/common.h +++ b/components/bt/esp_ble_mesh/common/include/mesh/common.h @@ -53,6 +53,8 @@ void bt_mesh_free_buf(struct net_buf_simple *buf); int bt_mesh_rand(void *buf, size_t len); +uint32_t bt_mesh_get_rand(void); + #ifdef __cplusplus } #endif diff --git a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c index 68a768c7941..0e5769ba7d0 100644 --- a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c @@ -324,6 +324,7 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param, tBLE_ADDR_TYPE addr_type_own = 0U; tBLE_BD_ADDR p_dir_bda = {0}; tBTM_BLE_AFP adv_fil_pol = 0U; + uint16_t interval = 0U; uint8_t adv_type = 0U; int err = 0; @@ -387,9 +388,24 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param, adv_fil_pol = BLE_MESH_AP_SCAN_CONN_ALL; p_start_adv_cb = start_adv_completed_cb; + interval = param->interval_min; + +#if CONFIG_BLE_MESH_RANDOM_ADV_INTERVAL + /* If non-connectable mesh packets are transmitted with an adv interval + * not smaller than 10ms, then we will use a random adv interval between + * [interval / 2, interval] for them. + */ + if (adv_type == BLE_MESH_ADV_NONCONN_IND && interval >= 16) { + interval >>= 1; + interval += (bt_mesh_get_rand() % (interval + 1)); + + BT_INFO("%u->%u", param->interval_min, interval); + } +#endif + /* Check if we can start adv using BTM_BleSetAdvParamsStartAdvCheck */ BLE_MESH_BTM_CHECK_STATUS( - BTM_BleSetAdvParamsAll(param->interval_min, param->interval_max, adv_type, + BTM_BleSetAdvParamsAll(interval, interval, adv_type, addr_type_own, &p_dir_bda, channel_map, adv_fil_pol, p_start_adv_cb)); BLE_MESH_BTM_CHECK_STATUS(BTM_BleStartAdv()); diff --git a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c index 806f4e0eb58..510352ce15d 100644 --- a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c @@ -758,15 +758,17 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param, const struct bt_mesh_adv_data *ad, size_t ad_len, const struct bt_mesh_adv_data *sd, size_t sd_len) { + struct ble_gap_adv_params adv_params; + uint8_t buf[BLE_HS_ADV_MAX_SZ]; + uint16_t interval = 0; + uint8_t buf_len = 0; + int err; + #if BLE_MESH_DEV if (bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING)) { return -EALREADY; } #endif - uint8_t buf[BLE_HS_ADV_MAX_SZ]; - uint8_t buf_len = 0; - int err; - struct ble_gap_adv_params adv_params; err = set_ad(ad, ad_len, buf, &buf_len); if (err) { @@ -797,8 +799,6 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param, } memset(&adv_params, 0, sizeof adv_params); - adv_params.itvl_min = param->interval_min; - adv_params.itvl_max = param->interval_max; if (param->options & BLE_MESH_ADV_OPT_CONNECTABLE) { adv_params.conn_mode = BLE_GAP_CONN_MODE_UND; @@ -811,6 +811,25 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param, adv_params.disc_mode = BLE_GAP_DISC_MODE_NON; } + interval = param->interval_min; + +#if CONFIG_BLE_MESH_RANDOM_ADV_INTERVAL + /* If non-connectable mesh packets are transmitted with an adv interval + * not smaller than 10ms, then we will use a random adv interval between + * [interval / 2, interval] for them. + */ + if (adv_params.conn_mode == BLE_GAP_CONN_MODE_NON && + adv_params.disc_mode == BLE_GAP_DISC_MODE_NON && interval >= 16) { + interval >>= 1; + interval += (bt_mesh_get_rand() % (interval + 1)); + + BT_INFO("%u->%u", param->interval_min, interval); + } +#endif + + adv_params.itvl_min = interval; + adv_params.itvl_max = interval; + again: err = ble_gap_adv_start(BLE_OWN_ADDR_PUBLIC, NULL, BLE_HS_FOREVER, &adv_params, gap_event_cb, NULL); @@ -1940,10 +1959,6 @@ int bt_mesh_update_exceptional_list(uint8_t sub_code, uint32_t type, void *info) uint8_t value[6] = {0}; int rc = 0; -#if MYNEWT_VAL(BLE_HCI_VS) - struct ble_hci_vs_duplicate_exception_list_cp cmd; -#endif - if ((sub_code > BLE_MESH_EXCEP_LIST_SUB_CODE_CLEAN) || (sub_code < BLE_MESH_EXCEP_LIST_SUB_CODE_CLEAN && type > BLE_MESH_EXCEP_LIST_TYPE_MESH_PROXY_ADV) || @@ -1974,12 +1989,7 @@ int bt_mesh_update_exceptional_list(uint8_t sub_code, uint32_t type, void *info) BT_DBG("%s exceptional list, type 0x%08x", sub_code ? "Remove" : "Add", type); #if MYNEWT_VAL(BLE_HCI_VS) - cmd.operation = sub_code; - cmd.type = htole32(type); - memcpy(&cmd.device_info, value, 6); - - rc = ble_hs_hci_send_vs_cmd(BLE_HCI_OCF_VS_DUPLICATE_EXCEPTION_LIST, - &cmd, sizeof(cmd), NULL, 0); + rc = ble_gap_duplicate_exception_list(sub_code, type, value, NULL); #endif return rc; diff --git a/components/bt/esp_ble_mesh/v1.1/ext.c b/components/bt/esp_ble_mesh/lib/ext.c similarity index 100% rename from components/bt/esp_ble_mesh/v1.1/ext.c rename to components/bt/esp_ble_mesh/lib/ext.c diff --git a/components/bt/esp_ble_mesh/v1.1/include/mesh_v1.1/utils.h b/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h similarity index 100% rename from components/bt/esp_ble_mesh/v1.1/include/mesh_v1.1/utils.h rename to components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h diff --git a/components/bt/esp_ble_mesh/lib/lib b/components/bt/esp_ble_mesh/lib/lib new file mode 160000 index 00000000000..41bf5fc0926 --- /dev/null +++ b/components/bt/esp_ble_mesh/lib/lib @@ -0,0 +1 @@ +Subproject commit 41bf5fc0926fd6d3fb39cb5107e97f2fc6aed7e5 diff --git a/components/bt/esp_ble_mesh/v1.1/lib/esp32/libmesh_v1.1.a b/components/bt/esp_ble_mesh/v1.1/lib/esp32/libmesh_v1.1.a deleted file mode 100644 index 5cec3f8e909..00000000000 Binary files a/components/bt/esp_ble_mesh/v1.1/lib/esp32/libmesh_v1.1.a and /dev/null differ diff --git a/components/bt/esp_ble_mesh/v1.1/lib/esp32c3/libmesh_v1.1.a b/components/bt/esp_ble_mesh/v1.1/lib/esp32c3/libmesh_v1.1.a deleted file mode 100644 index 0d91c961ad6..00000000000 Binary files a/components/bt/esp_ble_mesh/v1.1/lib/esp32c3/libmesh_v1.1.a and /dev/null differ diff --git a/components/bt/esp_ble_mesh/v1.1/lib/esp32c6/libmesh_v1.1.a b/components/bt/esp_ble_mesh/v1.1/lib/esp32c6/libmesh_v1.1.a deleted file mode 100644 index 0d91c961ad6..00000000000 Binary files a/components/bt/esp_ble_mesh/v1.1/lib/esp32c6/libmesh_v1.1.a and /dev/null differ diff --git a/components/bt/esp_ble_mesh/v1.1/lib/esp32h2/libmesh_v1.1.a b/components/bt/esp_ble_mesh/v1.1/lib/esp32h2/libmesh_v1.1.a deleted file mode 100644 index 0d91c961ad6..00000000000 Binary files a/components/bt/esp_ble_mesh/v1.1/lib/esp32h2/libmesh_v1.1.a and /dev/null differ diff --git a/components/bt/esp_ble_mesh/v1.1/lib/esp32s3/libmesh_v1.1.a b/components/bt/esp_ble_mesh/v1.1/lib/esp32s3/libmesh_v1.1.a deleted file mode 100644 index 5cec3f8e909..00000000000 Binary files a/components/bt/esp_ble_mesh/v1.1/lib/esp32s3/libmesh_v1.1.a and /dev/null differ diff --git a/components/bt/host/bluedroid/Kconfig.in b/components/bt/host/bluedroid/Kconfig.in index 479d0d68975..e63d98447a6 100644 --- a/components/bt/host/bluedroid/Kconfig.in +++ b/components/bt/host/bluedroid/Kconfig.in @@ -221,7 +221,10 @@ config BT_GATTS_ROBUST_CACHING_ENABLED depends on BT_GATTS_ENABLE default n help - This option enable gatt robust caching feature on server + This option enables the GATT robust caching feature on the server. + if turned on, the Client Supported Features characteristic, Database Hash characteristic, + and Server Supported Features characteristic will be included in the GAP SERVICE. + config BT_GATTS_DEVICE_NAME_WRITABLE bool "Allow to write device name by GATT clients" @@ -1051,7 +1054,7 @@ config BT_ACL_CONNECTIONS config BT_MULTI_CONNECTION_ENBALE bool "Enable BLE multi-conections" - depends on BT_BLUEDROID_ENABLED + depends on BT_BLE_ENABLED default y help Enable this option if there are multiple connections @@ -1072,7 +1075,7 @@ config BT_BLE_DYNAMIC_ENV_MEMORY config BT_BLE_HOST_QUEUE_CONG_CHECK bool "BLE queue congestion check" - depends on BT_BLUEDROID_ENABLED + depends on BT_BLE_ENABLED default n help When scanning and scan duplicate is not enabled, if there are a lot of adv packets around @@ -1097,7 +1100,7 @@ config BT_BLE_ACT_SCAN_REP_ADV_SCAN config BT_BLE_ESTAB_LINK_CONN_TOUT int "Timeout of BLE connection establishment" - depends on BT_BLUEDROID_ENABLED + depends on BT_BLE_ENABLED range 1 60 default 30 help @@ -1133,7 +1136,7 @@ config BT_BLE_RPA_SUPPORTED config BT_BLE_RPA_TIMEOUT int "Timeout of resolvable private address" - depends on BT_BLUEDROID_ENABLED + depends on BT_BLE_ENABLED range 1 3600 default 900 help @@ -1142,14 +1145,14 @@ config BT_BLE_RPA_TIMEOUT config BT_BLE_50_FEATURES_SUPPORTED bool "Enable BLE 5.0 features" - depends on (BT_BLUEDROID_ENABLED && ((BT_CONTROLLER_ENABLED && SOC_BLE_50_SUPPORTED) || BT_CONTROLLER_DISABLED)) + depends on (BT_BLE_ENABLED && ((BT_CONTROLLER_ENABLED && SOC_BLE_50_SUPPORTED) || BT_CONTROLLER_DISABLED)) default y help - This enables BLE 5.0 features, this option only support esp32c3/esp32s3 chip + Enabling this option activates BLE 5.0 features. This option is universally supported in chips that support BLE, except for ESP32. config BT_BLE_42_FEATURES_SUPPORTED bool "Enable BLE 4.2 features" - depends on (BT_BLUEDROID_ENABLED && ((BT_CONTROLLER_ENABLED && SOC_BLE_SUPPORTED) || BT_CONTROLLER_DISABLED)) + depends on (BT_BLE_ENABLED && ((BT_CONTROLLER_ENABLED && SOC_BLE_SUPPORTED) || BT_CONTROLLER_DISABLED)) default n help This enables BLE 4.2 features. @@ -1168,9 +1171,16 @@ config BT_BLE_FEAT_PERIODIC_ADV_ENH help Enable the periodic advertising enhancements +config BT_BLE_FEAT_CREATE_SYNC_ENH + bool "Enable create sync enhancements(reporting disable and duplicate filtering enable support)" + depends on (BT_BLUEDROID_ENABLED && BT_BLE_50_FEATURES_SUPPORTED && ((BT_CONTROLLER_ENABLED && SOC_ESP_NIMBLE_CONTROLLER) || BT_CONTROLLER_DISABLED)) + default n + help + Enable the create sync enhancements + config BT_BLE_HIGH_DUTY_ADV_INTERVAL bool "Enable BLE high duty advertising interval feature" - depends on BT_BLUEDROID_ENABLED + depends on BT_BLE_ENABLED default n help This enable BLE high duty advertising interval feature diff --git a/components/bt/host/bluedroid/api/esp_gap_bt_api.c b/components/bt/host/bluedroid/api/esp_gap_bt_api.c index e887ec5261d..3e58847d285 100644 --- a/components/bt/host/bluedroid/api/esp_gap_bt_api.c +++ b/components/bt/host/bluedroid/api/esp_gap_bt_api.c @@ -475,4 +475,23 @@ esp_err_t esp_bt_gap_get_page_timeout(void) return (btc_transfer_context(&msg, NULL, 0, NULL, NULL) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL); } + +esp_err_t esp_bt_gap_set_acl_pkt_types(esp_bd_addr_t remote_bda, uint16_t pkt_types) +{ + btc_msg_t msg; + btc_gap_bt_args_t arg; + + if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { + return ESP_ERR_INVALID_STATE; + } + + msg.sig = BTC_SIG_API_CALL; + msg.pid = BTC_PID_GAP_BT; + msg.act = BTC_GAP_BT_ACT_SET_ACL_PKT_TYPES; + + memcpy(&arg.set_acl_pkt_types.bda, remote_bda, sizeof(bt_bdaddr_t)); + arg.set_acl_pkt_types.pkt_types = pkt_types; + return (btc_transfer_context(&msg, &arg, sizeof(btc_gap_bt_args_t), NULL, NULL) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL); +} + #endif /* #if BTC_GAP_BT_INCLUDED == TRUE */ diff --git a/components/bt/host/bluedroid/api/esp_hf_ag_api.c b/components/bt/host/bluedroid/api/esp_hf_ag_api.c index 3098cd47161..6eb6a6b5232 100644 --- a/components/bt/host/bluedroid/api/esp_hf_ag_api.c +++ b/components/bt/host/bluedroid/api/esp_hf_ag_api.c @@ -173,6 +173,9 @@ esp_err_t esp_hf_ag_volume_control(esp_bd_addr_t remote_addr, esp_hf_volume_cont if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { return ESP_ERR_INVALID_STATE; } + if (volume < 0 || volume > 15) { + return ESP_ERR_INVALID_ARG; + } btc_msg_t msg; msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_HF; @@ -239,6 +242,9 @@ esp_err_t esp_hf_ag_devices_status_indchange(esp_bd_addr_t remote_addr, if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { return ESP_ERR_INVALID_STATE; } + if (signal < 0 || signal > 5) { + return ESP_ERR_INVALID_ARG; + } btc_msg_t msg; msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_HF; @@ -287,6 +293,10 @@ esp_err_t esp_hf_ag_cind_response(esp_bd_addr_t remote_addr, if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { return ESP_ERR_INVALID_STATE; } + if (signal < 0 || signal > 5 || batt_lev < 0 || batt_lev > 5) { + return ESP_ERR_INVALID_ARG; + } + btc_msg_t msg; msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_HF; @@ -365,7 +375,7 @@ esp_err_t esp_hf_ag_cnum_response(esp_bd_addr_t remote_addr, char *number, int n if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { return ESP_ERR_INVALID_STATE; } - if (number == NULL) { + if (number == NULL || number_type < 128 || number_type > 175) { return ESP_ERR_INVALID_ARG; } btc_msg_t msg; diff --git a/components/bt/host/bluedroid/api/include/api/esp_a2dp_api.h b/components/bt/host/bluedroid/api/include/api/esp_a2dp_api.h index f319eb4d523..7020750c203 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_a2dp_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_a2dp_api.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -242,7 +242,7 @@ typedef int32_t (* esp_a2d_source_data_cb_t)(uint8_t *buf, int32_t len); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -259,7 +259,7 @@ esp_err_t esp_a2d_register_callback(esp_a2d_cb_t callback); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -276,7 +276,7 @@ esp_err_t esp_a2d_sink_register_data_callback(esp_a2d_sink_data_cb_t callback); * * @return * - ESP_OK: if the initialization request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -291,7 +291,7 @@ esp_err_t esp_a2d_sink_init(void); * * @return * - ESP_OK: if the deinitialization request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -307,7 +307,7 @@ esp_err_t esp_a2d_sink_deinit(void); * * @return * - ESP_OK: connect request is sent to lower layer successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -323,7 +323,7 @@ esp_err_t esp_a2d_sink_connect(esp_bd_addr_t remote_bda); * * @return * - ESP_OK: disconnect request is sent to lower layer successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -340,7 +340,7 @@ esp_err_t esp_a2d_sink_disconnect(esp_bd_addr_t remote_bda); * * @return * - ESP_OK: delay value is sent to lower layer successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -353,7 +353,7 @@ esp_err_t esp_a2d_sink_set_delay_value(uint16_t delay_value); * * @return * - ESP_OK: if the request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -369,7 +369,7 @@ esp_err_t esp_a2d_sink_get_delay_value(void); * * @return * - ESP_OK: control command is sent to lower layer successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -386,7 +386,7 @@ esp_err_t esp_a2d_media_ctrl(esp_a2d_media_ctrl_t ctrl); * * @return * - ESP_OK: if the initialization request is sent to lower layer successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -401,7 +401,7 @@ esp_err_t esp_a2d_source_init(void); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -418,7 +418,7 @@ esp_err_t esp_a2d_source_deinit(void); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -434,7 +434,7 @@ esp_err_t esp_a2d_source_register_data_callback(esp_a2d_source_data_cb_t callbac * * @return * - ESP_OK: connect request is sent to lower layer successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -449,7 +449,7 @@ esp_err_t esp_a2d_source_connect(esp_bd_addr_t remote_bda); * @param[in] remote_bda: remote bluetooth device address * @return * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h index 94680548bb5..c1ea8b3fd9a 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h @@ -904,12 +904,22 @@ typedef struct { * @brief periodic adv sync parameters */ typedef struct { - esp_ble_gap_sync_t filter_policy; /*!< periodic advertising sync filter policy */ - uint8_t sid; /*!< periodic advertising sid */ - esp_ble_addr_type_t addr_type; /*!< periodic advertising address type */ - esp_bd_addr_t addr; /*!< periodic advertising address */ - uint16_t skip; /*!< the maximum number of periodic advertising events that can be skipped */ - uint16_t sync_timeout; /*!< synchronization timeout */ + esp_ble_gap_sync_t filter_policy; /*!< Configures the filter policy for periodic advertising sync: + 0: Use Advertising SID, Advertiser Address Type, and Advertiser Address parameters to determine the advertiser to listen to. + 1: Use the Periodic Advertiser List to determine the advertiser to listen to. */ + #if (CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH) + esp_ble_gap_sync_t reports_disabled; /*!< Supported only by esp32c2, esp32c6, and esp32h2; can be set by menuconfig: + 0: Reporting initially enabled. + 1: Reporting initially disabled. */ + esp_ble_gap_sync_t filter_duplicates; /*!< Supported only by esp32c2, esp32c6, and esp32h2; can be set by menuconfig: + 0: Duplicate filtering initially disabled. + 1: Duplicate filtering initially enabled. */ + #endif + uint8_t sid; /*!< SID of the periodic advertising */ + esp_ble_addr_type_t addr_type; /*!< Address type of the periodic advertising */ + esp_bd_addr_t addr; /*!< Address of the periodic advertising */ + uint16_t skip; /*!< Maximum number of periodic advertising events that can be skipped */ + uint16_t sync_timeout; /*!< Synchronization timeout */ } esp_ble_gap_periodic_adv_sync_params_t; /** diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h index ea7a4eaf0ae..9f3d46b22a5 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h @@ -91,7 +91,35 @@ typedef struct { typedef uint8_t esp_bt_eir_type_t; - +/* ACL Packet Types */ +#define ESP_BT_ACL_PKT_TYPES_MASK_DM1 0x0008 +#define ESP_BT_ACL_PKT_TYPES_MASK_DH1 0x0010 +#define ESP_BT_ACL_PKT_TYPES_MASK_DM3 0x0400 +#define ESP_BT_ACL_PKT_TYPES_MASK_DH3 0x0800 +#define ESP_BT_ACL_PKT_TYPES_MASK_DM5 0x4000 +#define ESP_BT_ACL_PKT_TYPES_MASK_DH5 0x8000 +#define ESP_BT_ACL_PKT_TYPES_MASK_NO_2_DH1 0x0002 +#define ESP_BT_ACL_PKT_TYPES_MASK_NO_3_DH1 0x0004 +#define ESP_BT_ACL_PKT_TYPES_MASK_NO_2_DH3 0x0100 +#define ESP_BT_ACL_PKT_TYPES_MASK_NO_3_DH3 0x0200 +#define ESP_BT_ACL_PKT_TYPES_MASK_NO_2_DH5 0x1000 +#define ESP_BT_ACL_PKT_TYPES_MASK_NO_3_DH5 0x2000 + +// DM1 cann not be disabled. All options are mandatory to include DM1. +#define ESP_BT_ACL_DM1_ONLY (ESP_BT_ACL_PKT_TYPES_MASK_DM1 | 0x330e) /* 0x330e */ +#define ESP_BT_ACL_DH1_ONLY (ESP_BT_ACL_PKT_TYPES_MASK_DH1 | 0x330e) /* 0x331e */ +#define ESP_BT_ACL_DM3_ONLY (ESP_BT_ACL_PKT_TYPES_MASK_DM3 | 0x330e) /* 0x370e */ +#define ESP_BT_ACL_DH3_ONLY (ESP_BT_ACL_PKT_TYPES_MASK_DH3 | 0x330e) /* 0x3b0e */ +#define ESP_BT_ACL_DM5_ONLY (ESP_BT_ACL_PKT_TYPES_MASK_DM5 | 0x330e) /* 0x730e */ +#define ESP_BT_ACL_DH5_ONLY (ESP_BT_ACL_PKT_TYPES_MASK_DH5 | 0x330e) /* 0xb30e */ +#define ESP_BT_ACL_2_DH1_ONLY (~ESP_BT_ACL_PKT_TYPES_MASK_NO_2_DH1 & 0x330e) /* 0x330c */ +#define ESP_BT_ACL_3_DH1_ONLY (~ESP_BT_ACL_PKT_TYPES_MASK_NO_3_DH1 & 0x330e) /* 0x330a */ +#define ESP_BT_ACL_2_DH3_ONLY (~ESP_BT_ACL_PKT_TYPES_MASK_NO_2_DH3 & 0x330e) /* 0x320e */ +#define ESP_BT_ACL_3_DH3_ONLY (~ESP_BT_ACL_PKT_TYPES_MASK_NO_3_DH3 & 0x330e) /* 0x310e */ +#define ESP_BT_ACL_2_DH5_ONLY (~ESP_BT_ACL_PKT_TYPES_MASK_NO_2_DH5 & 0x330e) /* 0x230e */ +#define ESP_BT_ACL_3_DH5_ONLY (~ESP_BT_ACL_PKT_TYPES_MASK_NO_3_DH5 & 0x330e) /* 0x130e */ + +typedef uint16_t esp_bt_acl_pkt_type_t; /* ESP_BT_EIR_FLAG bit definition */ #define ESP_BT_EIR_FLAG_LIMIT_DISC (0x01 << 0) @@ -220,6 +248,7 @@ typedef enum { ESP_BT_GAP_ACL_DISCONN_CMPL_STAT_EVT, /*!< ACL disconnection complete status event */ ESP_BT_GAP_SET_PAGE_TO_EVT, /*!< Set page timeout event */ ESP_BT_GAP_GET_PAGE_TO_EVT, /*!< Get page timeout event */ + ESP_BT_GAP_ACL_PKT_TYPE_CHANGED_EVT, /*!< Set ACL packet types event */ ESP_BT_GAP_EVT_MAX, } esp_bt_gap_cb_event_t; @@ -394,6 +423,15 @@ typedef union { uint16_t page_to; /*!< page_timeout value to be set, unit is 0.625ms. */ } get_page_timeout; /*!< get page timeout parameter struct */ + /** + * @brief ESP_BT_GAP_ACL_PKT_TYPE_CHANGED_EVT + */ + struct set_acl_pkt_types_param { + esp_bt_status_t status; /*!< set ACL packet types status */ + esp_bd_addr_t bda; /*!< remote bluetooth device address */ + uint16_t pkt_types; /*!< packet types successfully set */ + } set_acl_pkt_types; /*!< set ACL packet types parameter struct */ + /** * @brief ESP_BT_GAP_ACL_CONN_CMPL_STAT_EVT */ @@ -834,6 +872,17 @@ esp_err_t esp_bt_gap_set_page_timeout(uint16_t page_to); */ esp_err_t esp_bt_gap_get_page_timeout(void); +/** + * @brief Set ACL packet types + * An ESP_BT_GAP_SET_ACL_PPKT_TYPES_EVT event will reported to + * the APP layer. + * + * @return - ESP_OK: success + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled + * - other: failed + */ +esp_err_t esp_bt_gap_set_acl_pkt_types(esp_bd_addr_t remote_bda, esp_bt_acl_pkt_type_t pkt_types); + #ifdef __cplusplus } #endif diff --git a/components/bt/host/bluedroid/api/include/api/esp_hf_ag_api.h b/components/bt/host/bluedroid/api/include/api/esp_hf_ag_api.h index 4ce0096b09a..84086118f37 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_hf_ag_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_hf_ag_api.h @@ -274,7 +274,7 @@ typedef void (* esp_hf_cb_t) (esp_hf_cb_event_t event, esp_hf_cb_param_t *param) * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -287,7 +287,7 @@ esp_err_t esp_hf_ag_register_callback(esp_hf_cb_t callback); * * @return * - ESP_OK: if the initialization request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -300,7 +300,7 @@ esp_err_t esp_hf_ag_init(void); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -315,7 +315,7 @@ esp_err_t esp_hf_ag_deinit(void); * * @return * - ESP_OK: connect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -330,7 +330,7 @@ esp_err_t esp_hf_ag_slc_connect(esp_bd_addr_t remote_bda); * * @return * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -344,8 +344,8 @@ esp_err_t esp_hf_ag_slc_disconnect(esp_bd_addr_t remote_bda); * @param[in] remote_bda: remote bluetooth device address * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: audio connect request is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -359,8 +359,8 @@ esp_err_t esp_hf_ag_audio_connect(esp_bd_addr_t remote_bda); * @param[in] remote_bda: remote bluetooth device address * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: audio disconnect request is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -376,8 +376,8 @@ esp_err_t esp_hf_ag_audio_disconnect(esp_bd_addr_t remote_bda); * @param[in] value: 0 - voice recognition disabled, 1- voice recognition enabled * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: response of volume recognition is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -395,8 +395,9 @@ esp_err_t esp_hf_ag_vra_control(esp_bd_addr_t remote_bda, esp_hf_vr_state_t valu * @param[in] volume: gain of the speaker of microphone, ranges 0 to 15 * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: volume synchronization control is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_ARG: if arguments are invalid * - ESP_FAIL: others * */ @@ -412,8 +413,8 @@ esp_err_t esp_hf_ag_volume_control(esp_bd_addr_t remote_bda, esp_hf_volume_contr * @param[in] unat: User AT command response to HF Client. * It will response "ERROR" by default if unat is NULL. * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: response of unknown AT command is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -428,8 +429,8 @@ esp_err_t esp_hf_ag_unknown_at_send(esp_bd_addr_t remote_addr, char *unat); * @param[in] response_code: AT command response code * @param[in] error_code: CME error code * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: extend error code is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -446,8 +447,9 @@ esp_err_t esp_hf_ag_cmee_send(esp_bd_addr_t remote_bda, esp_hf_at_response_code_ * @param[in] ntk_state: network service state * @param[in] signal: signal strength from 0 to 5 * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: device status notification is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_ARG: if arguments are invalid * - ESP_FAIL: others * */ @@ -467,8 +469,8 @@ esp_err_t esp_hf_ag_devices_status_indchange(esp_bd_addr_t remote_addr, esp_hf_c * @param[in] ind_type: indicator type * @param[in] value: indicator value * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: indicator report is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -488,8 +490,9 @@ esp_err_t esp_hf_ag_ciev_report(esp_bd_addr_t remote_addr, esp_hf_ciev_report_ty * @param[in] batt_lev: battery level from 0 to 5 * @param[in] call_held_status: call held status * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: response to device individual indicators is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_ARG: if the arguments are invalid * - ESP_FAIL: others * */ @@ -507,8 +510,8 @@ esp_err_t esp_hf_ag_cind_response(esp_bd_addr_t remote_addr, * @param[in] remote_addr: remote bluetooth device address * @param[in] name: current operator name * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: reponse for AT+COPS command is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -528,8 +531,8 @@ esp_err_t esp_hf_ag_cops_response(esp_bd_addr_t remote_addr, char *name); * @param[in] number: current call number * @param[in] type: international type or unknow * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: response to AT+CLCC command is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -550,8 +553,8 @@ esp_err_t esp_hf_ag_clcc_response(esp_bd_addr_t remote_addr, int index, esp_hf_c * 160-175: national, but no prefix nor escape digits * @param[in] service_type: service type (unknown/voice/fax) * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: response for AT+CNUM command is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -565,8 +568,9 @@ esp_err_t esp_hf_ag_cnum_response(esp_bd_addr_t remote_addr, char *number, int n * @param[in] remote_addr: remote bluetooth device address * @param[in] state: in-band ring tone state * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: information of in-band ring tone is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_ARG: if arguments are invalid * - ESP_FAIL: others * */ @@ -585,8 +589,8 @@ esp_err_t esp_hf_ag_bsir(esp_bd_addr_t remote_addr, esp_hf_in_band_ring_state_t * @param[in] number: number of the incoming call * @param[in] call_addr_type: call address type * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: answer incoming call is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -607,8 +611,8 @@ esp_err_t esp_hf_ag_answer_call(esp_bd_addr_t remote_addr, int num_active, int n * @param[in] number: number of the incoming call * @param[in] call_addr_type: call address type * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: reject incoming call is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -632,8 +636,8 @@ esp_err_t esp_hf_ag_reject_call(esp_bd_addr_t remote_addr, int num_active, int n * @param[in] number: number of the outgoing call * @param[in] call_addr_type: call address type * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: a call initiation is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -654,8 +658,8 @@ esp_err_t esp_hf_ag_out_call(esp_bd_addr_t remote_addr, int num_active, int num_ * @param[in] number: number of the call * @param[in] call_addr_type: call address type * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: end an ongoing call is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -672,7 +676,7 @@ esp_err_t esp_hf_ag_end_call(esp_bd_addr_t remote_addr, int num_active, int num_ * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -689,7 +693,7 @@ esp_err_t esp_hf_ag_register_data_callback(esp_hf_incoming_data_cb_t recv, esp_h * * @return * - ESP_OK: if the request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ diff --git a/components/bt/host/bluedroid/api/include/api/esp_hf_client_api.h b/components/bt/host/bluedroid/api/include/api/esp_hf_client_api.h index 8cf2b0e4930..9353fc032b2 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_hf_client_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_hf_client_api.h @@ -313,7 +313,7 @@ typedef void (* esp_hf_client_cb_t)(esp_hf_client_cb_event_t event, esp_hf_clien * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -326,7 +326,7 @@ esp_err_t esp_hf_client_register_callback(esp_hf_client_cb_t callback); * * @return * - ESP_OK: if the initialization request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -339,7 +339,7 @@ esp_err_t esp_hf_client_init(void); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -354,7 +354,7 @@ esp_err_t esp_hf_client_deinit(void); * * @return * - ESP_OK: connect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -369,7 +369,7 @@ esp_err_t esp_hf_client_connect(esp_bd_addr_t remote_bda); * * @return * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -382,8 +382,8 @@ esp_err_t esp_hf_client_disconnect(esp_bd_addr_t remote_bda); * * @param[in] remote_bda: remote bluetooth device address * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: connect audio request is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -396,8 +396,8 @@ esp_err_t esp_hf_client_connect_audio(esp_bd_addr_t remote_bda); * * @param[in] remote_bda: remote bluetooth device address * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: disconnect audio request is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -409,8 +409,8 @@ esp_err_t esp_hf_client_disconnect_audio(esp_bd_addr_t remote_bda); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: starting voice recognition is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -422,8 +422,8 @@ esp_err_t esp_hf_client_start_voice_recognition(void); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: stoping voice recognition is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -438,8 +438,8 @@ esp_err_t esp_hf_client_stop_voice_recognition(void); * @param[in] volume: gain of the speaker of microphone, ranges 0 to 15 * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: volume update is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -453,8 +453,8 @@ esp_err_t esp_hf_client_volume_update(esp_hf_volume_control_target_t type, int v * @param[in] number: number string of the call. If NULL, the last number is called(aka re-dial) * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: a call placing is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -468,8 +468,8 @@ esp_err_t esp_hf_client_dial(const char *number); * @param[in] location: location of the number in the memory * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: a memory call placing is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -486,8 +486,8 @@ esp_err_t esp_hf_client_dial_memory(int location); * ESP_HF_CHLD_TYPE_REL_X or ESP_HF_CHLD_TYPE_PRIV_X * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: command AT+CHLD is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -501,8 +501,8 @@ esp_err_t esp_hf_client_send_chld_cmd(esp_hf_chld_type_t chld, int idx); * @param[in] btrh: response and hold action to send * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: command AT+BTRH is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -514,8 +514,8 @@ esp_err_t esp_hf_client_send_btrh_cmd(esp_hf_btrh_cmd_t btrh); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: a call answering is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -527,8 +527,8 @@ esp_err_t esp_hf_client_answer_call(void); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: the call rejecting is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -540,8 +540,8 @@ esp_err_t esp_hf_client_reject_call(void); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: query of current calls is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -553,8 +553,8 @@ esp_err_t esp_hf_client_query_current_calls(void); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: query of current operator name is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -566,8 +566,8 @@ esp_err_t esp_hf_client_query_current_operator_name(void); * As a precondition to use this API, Service Level Connection shall exist with AG * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: the retrieving of subscriber information is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -581,8 +581,8 @@ esp_err_t esp_hf_client_retrieve_subscriber_info(void); * @param[in] code: dtmf code, single ascii character in the set 0-9, #, *, A-D * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: the DTMF codes are sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -602,7 +602,7 @@ esp_err_t esp_hf_client_send_dtmf(char code); * * @return * - ESP_OK: Feature enable request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -620,7 +620,7 @@ esp_err_t esp_hf_client_send_xapl(char *information, uint32_t features); * * @return * - ESP_OK: battery level is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -632,8 +632,8 @@ esp_err_t esp_hf_client_send_iphoneaccev(uint32_t bat_level, bool docked); * As a precondition to use this API, Service Level Connection shall exist with AG. * * @return - * - ESP_OK: disconnect request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_OK: the phone number request corresponding to last voice tag recorded is sent to lower layer + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -646,7 +646,7 @@ esp_err_t esp_hf_client_request_last_voice_tag_number(void); * * @return * - ESP_OK: NREC=0 request is sent to lower layer - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ @@ -663,7 +663,7 @@ esp_err_t esp_hf_client_send_nrec(void); * * @return * - ESP_OK: success - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: if callback is a NULL function pointer * */ @@ -680,7 +680,7 @@ esp_err_t esp_hf_client_register_data_callback(esp_hf_client_incoming_data_cb_t * * @return * - ESP_OK: if the request is sent successfully - * - ESP_INVALID_STATE: if bluetooth stack is not yet enabled + * - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled * - ESP_FAIL: others * */ diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c index 0509da0a71b..ff149501c32 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c @@ -577,6 +577,14 @@ void bta_dm_disable (tBTA_DM_MSG *p_data) bta_dm_disable_search_and_disc(); bta_dm_cb.disabling = TRUE; +#if BLE_INCLUDED == TRUE + /* reset scan activity status*/ + btm_cb.ble_ctr_cb.scan_activity = 0; + + /* reset advertising activity status*/ + btm_cb.ble_ctr_cb.inq_var.state = 0; +#endif + #if BLE_INCLUDED == TRUE && BTA_GATT_INCLUDED == TRUE BTM_BleClearBgConnDev(); #endif @@ -874,6 +882,28 @@ void bta_dm_get_page_timeout (tBTA_DM_MSG *p_data) { BTM_ReadPageTimeout(p_data->get_page_timeout.get_page_to_cb); } + +/******************************************************************************* +** +** Function bta_dm_set_acl_pkt_types +** +** Description Sets ACL packet types +** +** +** Returns void +** +*******************************************************************************/ +void bta_dm_set_acl_pkt_types (tBTA_DM_MSG *p_data) +{ + if (p_data->set_acl_pkt_types.set_acl_pkt_types_cb != NULL) { + BTM_SetAclPktTypes(p_data->set_acl_pkt_types.rmt_addr, + p_data->set_acl_pkt_types.pkt_types, + p_data->set_acl_pkt_types.set_acl_pkt_types_cb); + } else { + APPL_TRACE_ERROR("%s(), the callback function can't be NULL.", __func__); + } +} + #endif /******************************************************************************* ** @@ -4257,7 +4287,7 @@ static void bta_dm_set_eir (char *local_name) for (custom_uuid_idx = 0; custom_uuid_idx < BTA_EIR_SERVER_NUM_CUSTOM_UUID; custom_uuid_idx++) { if (bta_dm_cb.custom_uuid[custom_uuid_idx].len == LEN_UUID_128) { if ( num_uuid < max_num_uuid ) { - ARRAY16_TO_STREAM(p, bta_dm_cb.custom_uuid[custom_uuid_idx].uu.uuid128); + ARRAY_TO_STREAM(p, bta_dm_cb.custom_uuid[custom_uuid_idx].uu.uuid128, LEN_UUID_128); num_uuid++; } else { data_type = BTM_EIR_MORE_128BITS_UUID_TYPE; @@ -4461,21 +4491,38 @@ static void bta_dm_eir_search_services( tBTM_INQ_RESULTS *p_result, ** Returns None ** *******************************************************************************/ -void bta_dm_eir_update_uuid(UINT16 uuid16, BOOLEAN adding) +void bta_dm_eir_update_uuid(tBT_UUID uuid, BOOLEAN adding) { - /* if this UUID is not advertised in EIR */ - if ( !BTM_HasEirService( p_bta_dm_eir_cfg->uuid_mask, uuid16 )) { - return; - } + /* 32 and 128-bit UUIDs go to the bta_dm_cb.custom_uuid array */ + if ((uuid.len == LEN_UUID_32) || (uuid.len == LEN_UUID_128)) { + if (adding) { + if (BTM_HasCustomEirService(bta_dm_cb.custom_uuid, uuid)) { + APPL_TRACE_EVENT("UUID is already added for EIR"); + return; + } + APPL_TRACE_EVENT("Adding %d-bit UUID into EIR", uuid.len * 8); - if ( adding ) { - APPL_TRACE_EVENT("Adding UUID=0x%04X into EIR", uuid16); + BTM_AddCustomEirService(bta_dm_cb.custom_uuid, uuid); + } else { + APPL_TRACE_EVENT("Removing %d-bit UUID from EIR", uuid.len * 8); - BTM_AddEirService( bta_dm_cb.eir_uuid, uuid16 ); + BTM_RemoveCustomEirService(bta_dm_cb.custom_uuid, uuid); + } } else { - APPL_TRACE_EVENT("Removing UUID=0x%04X from EIR", uuid16); + /* if this UUID is not advertised in EIR */ + if (!BTM_HasEirService(p_bta_dm_eir_cfg->uuid_mask, uuid.uu.uuid16)) { + return; + } + + if (adding) { + APPL_TRACE_EVENT("Adding UUID=0x%04X into EIR", uuid.uu.uuid16); - BTM_RemoveEirService( bta_dm_cb.eir_uuid, uuid16 ); + BTM_AddEirService(bta_dm_cb.eir_uuid, uuid.uu.uuid16); + } else { + APPL_TRACE_EVENT("Removing UUID=0x%04X from EIR", uuid.uu.uuid16); + + BTM_RemoveEirService(bta_dm_cb.eir_uuid, uuid.uu.uuid16); + } } #if CLASSIC_BT_INCLUDED bta_dm_set_eir (NULL); diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c index 95301cb4038..ecb6b6ee57b 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c @@ -341,6 +341,30 @@ void BTA_DmGetPageTimeout(tBTM_CMPL_CB *p_cb) bta_sys_sendmsg(p_msg); } } + +/******************************************************************************* +** +** Function BTA_DmSetAclPktTypes +** +** Description This function sets the packet types used for ACL traffic. +** +** +** Returns void +** +*******************************************************************************/ +void BTA_DmSetAclPktTypes(BD_ADDR remote_addr, UINT16 pkt_types, tBTM_CMPL_CB *p_cb) +{ + tBTA_DM_API_SET_ACL_PKT_TYPES *p_msg; + + if ((p_msg = (tBTA_DM_API_SET_ACL_PKT_TYPES *) osi_malloc(sizeof(tBTA_DM_API_SET_ACL_PKT_TYPES))) != NULL) { + p_msg->hdr.event = BTA_DM_API_SET_ACL_PKT_TYPES_EVT; + bdcpy(p_msg->rmt_addr, remote_addr); + p_msg->pkt_types = pkt_types; + p_msg->set_acl_pkt_types_cb = p_cb; + + bta_sys_sendmsg(p_msg); + } +} #endif /// CLASSIC_BT_INCLUDED == TRUE #if (SDP_INCLUDED == TRUE) diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_main.c b/components/bt/host/bluedroid/bta/dm/bta_dm_main.c index bff90453290..42e67d77b54 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_main.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_main.c @@ -69,6 +69,7 @@ const tBTA_DM_ACTION bta_dm_action[BTA_DM_MAX_EVT] = { bta_dm_config_eir, /* BTA_DM_API_CONFIG_EIR_EVT */ bta_dm_set_page_timeout, /* BTA_DM_API_PAGE_TO_SET_EVT */ bta_dm_get_page_timeout, /* BTA_DM_API_PAGE_TO_GET_EVT */ + bta_dm_set_acl_pkt_types, /* BTA_DM_API_SET_ACL_PKT_TYPES_EVT */ #endif bta_dm_set_afh_channels, /* BTA_DM_API_SET_AFH_CHANNELS_EVT */ #if (SDP_INCLUDED == TRUE) diff --git a/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h b/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h index 10823c9c96a..a46651d342e 100644 --- a/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h +++ b/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h @@ -61,6 +61,7 @@ enum { BTA_DM_API_CONFIG_EIR_EVT, BTA_DM_API_PAGE_TO_SET_EVT, BTA_DM_API_PAGE_TO_GET_EVT, + BTA_DM_API_SET_ACL_PKT_TYPES_EVT, #endif BTA_DM_API_SET_AFH_CHANNELS_EVT, #if (SDP_INCLUDED == TRUE) @@ -299,6 +300,14 @@ typedef struct { tBTM_CMPL_CB *get_page_to_cb; } tBTA_DM_API_PAGE_TO_GET; +/* data type for BTA_DM_API_SET_ACL_PKT_TYPES_EVT */ +typedef struct { + BT_HDR hdr; + BD_ADDR rmt_addr; + UINT16 pkt_types; + tBTM_CMPL_CB *set_acl_pkt_types_cb; +} tBTA_DM_API_SET_ACL_PKT_TYPES; + /* data type for BTA_DM_API_GET_REMOTE_NAME_EVT */ typedef struct { BT_HDR hdr; @@ -1158,6 +1167,7 @@ typedef union { tBTA_DM_API_SET_AFH_CHANNELS set_afh_channels; tBTA_DM_API_PAGE_TO_SET set_page_timeout; tBTA_DM_API_PAGE_TO_GET get_page_timeout; + tBTA_DM_API_SET_ACL_PKT_TYPES set_acl_pkt_types; #if (SDP_INCLUDED == TRUE) tBTA_DM_API_GET_REMOTE_NAME get_rmt_name; #endif @@ -1670,6 +1680,7 @@ extern void bta_dm_cfg_coex_status(tBTA_DM_MSG *p_data); extern void bta_dm_config_eir (tBTA_DM_MSG *p_data); extern void bta_dm_set_page_timeout (tBTA_DM_MSG *p_data); extern void bta_dm_get_page_timeout (tBTA_DM_MSG *p_data); +extern void bta_dm_set_acl_pkt_types (tBTA_DM_MSG *p_data); #endif extern void bta_dm_set_afh_channels (tBTA_DM_MSG *p_data); extern void bta_dm_read_rmt_name(tBTA_DM_MSG *p_data); @@ -1816,7 +1827,7 @@ extern void bta_dm_search_cancel_notify (tBTA_DM_MSG *p_data); extern void bta_dm_search_cancel_transac_cmpl(tBTA_DM_MSG *p_data); extern void bta_dm_disc_rmt_name (tBTA_DM_MSG *p_data); extern tBTA_DM_PEER_DEVICE *bta_dm_find_peer_device(BD_ADDR peer_addr); -void bta_dm_eir_update_uuid(UINT16 uuid16, BOOLEAN adding); +void bta_dm_eir_update_uuid(tBT_UUID uuid, BOOLEAN adding); extern void bta_dm_enable_test_mode(tBTA_DM_MSG *p_data); extern void bta_dm_disable_test_mode(tBTA_DM_MSG *p_data); diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c b/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c index 97b2d47e7c4..8bd3fecd77a 100644 --- a/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c +++ b/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c @@ -122,8 +122,11 @@ void bta_gattc_reset_discover_st(tBTA_GATTC_SERV *p_srcb, tBTA_GATT_STATUS statu static void bta_gattc_enable(tBTA_GATTC_CB *p_cb) { APPL_TRACE_DEBUG("bta_gattc_enable"); - - if (p_cb->state == BTA_GATTC_STATE_DISABLED) { + /* This is a workaround because the task priority of btc (BTA_GATTC_CLOSE_EVT + in that task) is lower than the priority of the btu task. + Consequently, the p_cb->state fails to be restored to BTA_GATTC_STATE_DISABLED + and remains in the BTA_GATTC_STATE_DISABLING state. */ + if (p_cb->state == BTA_GATTC_STATE_DISABLED || p_cb->state == BTA_GATTC_STATE_DISABLING) { /* initialize control block */ memset(&bta_gattc_cb, 0, sizeof(tBTA_GATTC_CB)); bta_gattc_cb.auto_disc = true; @@ -158,6 +161,7 @@ void bta_gattc_disable(tBTA_GATTC_CB *p_cb) for (i = 0; i < BTA_GATTC_CL_MAX; i ++) { if (p_cb->cl_rcb[i].in_use) { p_cb->state = BTA_GATTC_STATE_DISABLING; + p_cb->cl_rcb[i].in_use = false; /* don't deregister HH GATT IF */ /* HH GATT IF will be deregistered by bta_hh_le_deregister when disable HH */ #if (defined BTA_HH_LE_INCLUDED && BTA_HH_LE_INCLUDED == TRUE) @@ -200,7 +204,11 @@ void bta_gattc_register(tBTA_GATTC_CB *p_cb, tBTA_GATTC_DATA *p_data) cb_data.reg_oper.status = BTA_GATT_NO_RESOURCES; /* check if GATTC module is already enabled . Else enable */ - if (p_cb->state == BTA_GATTC_STATE_DISABLED) { + /* This is a workaround because the task priority of btc (BTA_GATTC_CLOSE_EVT + in that task) is lower than the priority of the btu task. + Consequently, the p_cb->state fails to be restored to BTA_GATTC_STATE_DISABLED + and remains in the BTA_GATTC_STATE_DISABLING state. */ + if (p_cb->state == BTA_GATTC_STATE_DISABLED || p_cb->state == BTA_GATTC_STATE_DISABLING) { bta_gattc_enable (p_cb); } /* todo need to check duplicate uuid */ diff --git a/components/bt/host/bluedroid/bta/hf_ag/bta_ag_act.c b/components/bt/host/bluedroid/bta/hf_ag/bta_ag_act.c index 6bb9de6cc15..c2e2773792c 100644 --- a/components/bt/host/bluedroid/bta/hf_ag/bta_ag_act.c +++ b/components/bt/host/bluedroid/bta/hf_ag/bta_ag_act.c @@ -397,10 +397,6 @@ void bta_ag_rfc_close(tBTA_AG_SCB *p_scb, tBTA_AG_DATA *p_data) bta_sys_conn_close(BTA_ID_AG, p_scb->app_id, p_scb->peer_addr); - /* call close call-out */ -#if (BTM_SCO_HCI_INCLUDED == TRUE) - bta_ag_sco_co_close(); -#endif /* call close cback */ (*bta_ag_cb.p_cback)(BTA_AG_CLOSE_EVT, (tBTA_AG *) &close); diff --git a/components/bt/host/bluedroid/bta/hf_ag/bta_ag_sdp.c b/components/bt/host/bluedroid/bta/hf_ag/bta_ag_sdp.c index 583486126bd..d35ad4f7c1f 100644 --- a/components/bt/host/bluedroid/bta/hf_ag/bta_ag_sdp.c +++ b/components/bt/host/bluedroid/bta/hf_ag/bta_ag_sdp.c @@ -243,13 +243,16 @@ void bta_ag_del_records(tBTA_AG_SCB *p_scb, tBTA_AG_DATA *p_data) UNUSED(p_data); /* get services of all other registered servers */ - for (i = 0; i < BTA_AG_NUM_IDX; i++, p++) { + for (i = 0; i < BTA_AG_NUM_IDX; i++) { if (p_scb == p) { continue; } if (p->in_use && p->dealloc == FALSE) { others |= p->reg_services; } + if (i < BTA_AG_NUM_SCB) { + p++; + } } others >>= BTA_HSP_SERVICE_ID; services = p_scb->reg_services >> BTA_HSP_SERVICE_ID; diff --git a/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_api.c b/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_api.c index 104182412a3..6149d8c4189 100644 --- a/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_api.c +++ b/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_api.c @@ -61,7 +61,8 @@ static const uint8_t bta_hf_client_cb_data_size[] = { sizeof(tBTA_HF_CLIENT_VAL), // #define BTA_HF_CLIENT_BSIR_EVT 19 sizeof(tBTA_HF_CLIENT_NUMBER), // #define BTA_HF_CLIENT_BINP_EVT 20 sizeof(tBTA_HF_CLIENT_VAL), // #define BTA_HF_CLIENT_RING_INDICATION 21 - 0, // #define BTA_HF_CLIENT_DISABLE_EVT 30 + 0, // #define BTA_HF_CLIENT_DISABLE_EVT 22 + sizeof(tBTA_SCO_PKT_STAT_NUMS), // #define BTA_HF_CLIENT_PKT_STAT_NUMS_GET_EVT 23 }; /***************************************************************************** ** External Function Declarations diff --git a/components/bt/host/bluedroid/bta/hf_client/include/bta_hf_client_at.h b/components/bt/host/bluedroid/bta/hf_client/include/bta_hf_client_at.h index caed82861be..2cf38acc2c2 100644 --- a/components/bt/host/bluedroid/bta/hf_client/include/bta_hf_client_at.h +++ b/components/bt/host/bluedroid/bta/hf_client/include/bta_hf_client_at.h @@ -26,15 +26,6 @@ /* ASCII character string of arguments to the AT command */ #define BTA_HF_CLIENT_AT_MAX_LEN 512 -/* AT command table element */ -typedef struct { - const char *p_cmd; /* AT command string */ - UINT8 arg_type; /* allowable argument type syntax */ - UINT8 fmt; /* whether arg is int or string */ - UINT8 min; /* minimum value for int arg */ - INT16 max; /* maximum value for int arg */ -} tBTA_AG_AT_CMD; - /* callback function executed when command is parsed */ typedef void (tBTA_AG_AT_CMD_CBACK)(void *p_user, UINT16 cmd, UINT8 arg_type, char *p_arg, INT16 int_arg); diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_api.h index e59bee7c08e..f362176ed0d 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_api.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_api.h @@ -443,6 +443,8 @@ typedef tBTM_BLE_SET_CHANNELS_RESULTS tBTA_BLE_SET_CHANNELS_RESULTS; typedef tBTM_SET_PAGE_TIMEOUT_RESULTS tBTA_SET_PAGE_TIMEOUT_RESULTS; typedef tBTM_GET_PAGE_TIMEOUT_RESULTS tBTA_GET_PAGE_TIMEOUT_RESULTS; +typedef tBTM_SET_ACL_PKT_TYPES_RESULTS tBTA_SET_ACL_PKT_TYPES_RESULTS; + typedef tBTM_REMOTE_DEV_NAME tBTA_REMOTE_DEV_NAME; /* advertising channel map */ @@ -1537,6 +1539,10 @@ typedef struct { typedef struct { UINT8 filter_policy; + #if (CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH) + UINT8 reports_disabled; + UINT8 filter_duplicates; + #endif UINT8 sid; tBLE_ADDR_TYPE addr_type; BD_ADDR addr; @@ -1804,6 +1810,18 @@ void BTA_DmSetPageTimeout(UINT16 page_to, tBTM_CMPL_CB *p_cb); *******************************************************************************/ void BTA_DmGetPageTimeout(tBTM_CMPL_CB *p_cb); +/******************************************************************************* +** +** Function BTA_DmSetAclPktTypes +** +** Description This function sets the packet types used for ACL traffic. +** +** +** Returns void +** +*******************************************************************************/ +void BTA_DmSetAclPktTypes(BD_ADDR remote_addr, UINT16 pkt_types, tBTM_CMPL_CB *p_cb); + #if (BLE_INCLUDED == TRUE) /******************************************************************************* ** diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_hf_client_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_hf_client_api.h index 30ca233b69f..ac834c7b6f7 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_hf_client_api.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_hf_client_api.h @@ -112,8 +112,8 @@ typedef UINT8 tBTA_HF_CLIENT_AT_RESULT_TYPE; #define BTA_HF_CLIENT_BSIR_EVT 19 /* in-band ring tone setting changed event */ #define BTA_HF_CLIENT_BINP_EVT 20 /* binp number event */ #define BTA_HF_CLIENT_RING_INDICATION 21 /* HF Client ring indication */ -#define BTA_HF_CLIENT_DISABLE_EVT 30 /* HF Client disabled */ -#define BTA_HF_CLIENT_PKT_STAT_NUMS_GET_EVT 31 /* HF Client packet status nums */ +#define BTA_HF_CLIENT_DISABLE_EVT 22 /* HF Client disabled */ +#define BTA_HF_CLIENT_PKT_STAT_NUMS_GET_EVT 23 /* HF Client packet status nums */ typedef UINT8 tBTA_HF_CLIENT_EVT; diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_sys.h b/components/bt/host/bluedroid/bta/include/bta/bta_sys.h index 87359b5a9fa..54376de635a 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_sys.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_sys.h @@ -143,7 +143,7 @@ typedef void (tBTA_SYS_SSR_CFG_CBACK)(UINT8 id, UINT8 app_id, UINT16 latency, UI #if (BTA_EIR_CANNED_UUID_LIST != TRUE) /* eir callback for adding/removeing UUID */ -typedef void (tBTA_SYS_EIR_CBACK)(UINT16 uuid16, BOOLEAN adding); +typedef void (tBTA_SYS_EIR_CBACK)(tBT_UUID uuid, BOOLEAN adding); #endif /* registration structure */ @@ -263,12 +263,20 @@ extern void bta_sys_notify_collision (BD_ADDR_PTR p_bda); #if (BTA_EIR_CANNED_UUID_LIST != TRUE) extern void bta_sys_eir_register(tBTA_SYS_EIR_CBACK *p_cback); -extern void bta_sys_add_uuid(UINT16 uuid16); +extern void bta_sys_add_uuid(UINT16 uuid); +extern void bta_sys_add_uuid_32(UINT32 uuid32); +extern void bta_sys_add_uuid_128(UINT8 *uuid128); extern void bta_sys_remove_uuid(UINT16 uuid16); +extern void bta_sys_remove_uuid_32(UINT32 uuid32); +extern void bta_sys_remove_uuid_128(UINT8 *uuid128); #else #define bta_sys_eir_register(ut) #define bta_sys_add_uuid(ut) +#define bta_sys_add_uuid_32(ut) +#define bta_sys_add_uuid_128(ut) #define bta_sys_remove_uuid(ut) +#define bta_sys_remove_uuid_32(ut) +#define bta_sys_remove_uuid_128(ut) #endif extern void bta_sys_set_policy (UINT8 id, UINT8 policy, BD_ADDR peer_addr); diff --git a/components/bt/host/bluedroid/bta/jv/bta_jv_act.c b/components/bt/host/bluedroid/bta/jv/bta_jv_act.c index c024a2116fc..eabb4ff258a 100644 --- a/components/bt/host/bluedroid/bta/jv/bta_jv_act.c +++ b/components/bt/host/bluedroid/bta/jv/bta_jv_act.c @@ -1248,10 +1248,15 @@ void bta_jv_delete_record(tBTA_JV_MSG *p_data) *******************************************************************************/ static void bta_jv_l2cap_client_cback(UINT16 gap_handle, UINT16 event) { + if (gap_handle >= BTA_JV_MAX_L2C_CONN) { + APPL_TRACE_WARNING("Invalid gap_handle: %u", gap_handle); + return; + } + tBTA_JV_L2C_CB *p_cb = &bta_jv_cb.l2c_cb[gap_handle]; tBTA_JV evt_data = {0}; - if (gap_handle >= BTA_JV_MAX_L2C_CONN && !p_cb->p_cback) { + if (!p_cb->p_cback) { return; } @@ -1402,12 +1407,17 @@ void bta_jv_l2cap_close(tBTA_JV_MSG *p_data) *******************************************************************************/ static void bta_jv_l2cap_server_cback(UINT16 gap_handle, UINT16 event) { + if (gap_handle >= BTA_JV_MAX_L2C_CONN) { + APPL_TRACE_WARNING("Invalid gap_handle: %u", gap_handle); + return; + } + tBTA_JV_L2C_CB *p_cb = &bta_jv_cb.l2c_cb[gap_handle]; tBTA_JV evt_data = {0}; tBTA_JV_L2CAP_CBACK *p_cback; void *user_data; - if (gap_handle >= BTA_JV_MAX_L2C_CONN && !p_cb->p_cback) { + if (!p_cb->p_cback) { return; } diff --git a/components/bt/host/bluedroid/bta/sys/bta_sys_conn.c b/components/bt/host/bluedroid/bta/sys/bta_sys_conn.c index 2d55dec48a3..914df55d9cb 100644 --- a/components/bt/host/bluedroid/bta/sys/bta_sys_conn.c +++ b/components/bt/host/bluedroid/bta/sys/bta_sys_conn.c @@ -527,8 +527,55 @@ void bta_sys_eir_register(tBTA_SYS_EIR_CBACK *p_cback) *******************************************************************************/ void bta_sys_add_uuid(UINT16 uuid16) { + tBT_UUID uuid; + uuid.len = LEN_UUID_16; + uuid.uu.uuid16 = uuid16; + + if (bta_sys_cb.eir_cb) { + bta_sys_cb.eir_cb(uuid, TRUE); + } +} + + +/******************************************************************************* +** +** Function bta_sys_add_uuid_32 +** +** Description Called by BTA subsystems to indicate to DM that new service +** class UUID is added. +** +** Returns void +** +*******************************************************************************/ +void bta_sys_add_uuid_32(UINT32 uuid32) +{ + tBT_UUID uuid; + uuid.len = LEN_UUID_32; + uuid.uu.uuid32 = uuid32; + + if (bta_sys_cb.eir_cb) { + bta_sys_cb.eir_cb(uuid, TRUE); + } +} + +/******************************************************************************* +** +** Function bta_sys_add_uuid_128 +** +** Description Called by BTA subsystems to indicate to DM that new service +** class UUID is added. +** +** Returns void +** +*******************************************************************************/ +void bta_sys_add_uuid_128(UINT8 *uuid128) +{ + tBT_UUID uuid; + uuid.len = LEN_UUID_128; + memcpy(&uuid.uu.uuid128, uuid128, LEN_UUID_128); + if (bta_sys_cb.eir_cb) { - bta_sys_cb.eir_cb(uuid16, TRUE ); + bta_sys_cb.eir_cb(uuid, TRUE); } } @@ -544,10 +591,57 @@ void bta_sys_add_uuid(UINT16 uuid16) *******************************************************************************/ void bta_sys_remove_uuid(UINT16 uuid16) { + tBT_UUID uuid; + uuid.len = LEN_UUID_16; + uuid.uu.uuid16 = uuid16; + + if (bta_sys_cb.eir_cb) { + bta_sys_cb.eir_cb(uuid, FALSE); + } +} + +/******************************************************************************* +** +** Function bta_sys_remove_uuid_32 +** +** Description Called by BTA subsystems to indicate to DM that the service +** class UUID is removed. +** +** Returns void +** +*******************************************************************************/ +void bta_sys_remove_uuid_32(UINT32 uuid32) +{ + tBT_UUID uuid; + uuid.len = LEN_UUID_32; + uuid.uu.uuid32 = uuid32; + if (bta_sys_cb.eir_cb) { - bta_sys_cb.eir_cb(uuid16, FALSE); + bta_sys_cb.eir_cb(uuid, FALSE); } } + +/******************************************************************************* +** +** Function bta_sys_remove_uuid_128 +** +** Description Called by BTA subsystems to indicate to DM that the service +** class UUID is removed. +** +** Returns void +** +*******************************************************************************/ +void bta_sys_remove_uuid_128(UINT8 *uuid128) +{ + tBT_UUID uuid; + uuid.len = LEN_UUID_128; + memcpy(&uuid.uu.uuid128, uuid128, LEN_UUID_128); + + if (bta_sys_cb.eir_cb) { + bta_sys_cb.eir_cb(uuid, FALSE); + } +} + #endif /******************************************************************************* diff --git a/components/bt/host/bluedroid/btc/core/btc_dm.c b/components/bt/host/bluedroid/btc/core/btc_dm.c index b4b0a6e60fe..408ffb9efd2 100644 --- a/components/bt/host/bluedroid/btc/core/btc_dm.c +++ b/components/bt/host/bluedroid/btc/core/btc_dm.c @@ -706,6 +706,7 @@ static void btc_dm_acl_link_stat(tBTA_DM_ACL_LINK_STAT *p_acl_link_stat) } } +#if (SMP_INCLUDED == TRUE) if (p_acl_link_stat->event == BTA_ACL_LINK_STAT_CONN_CMPL && p_acl_link_stat->link_act.conn_cmpl.status == HCI_SUCCESS) { memcpy(bt_addr.address, p_acl_link_stat->link_act.conn_cmpl.bd_addr, sizeof(bt_addr.address)); @@ -716,7 +717,7 @@ static void btc_dm_acl_link_stat(tBTA_DM_ACL_LINK_STAT *p_acl_link_stat) bt_addr.address[4], bt_addr.address[5]); } } - +#endif ///SMP_INCLUDED == TRUE esp_bt_gap_cb_t cb = (esp_bt_gap_cb_t)btc_profile_cb_get(BTC_PID_GAP_BT); if (cb) { cb(event, ¶m); diff --git a/components/bt/host/bluedroid/btc/core/btc_storage.c b/components/bt/host/bluedroid/btc/core/btc_storage.c index dfb61c7281d..1e7a60b63b0 100644 --- a/components/bt/host/bluedroid/btc/core/btc_storage.c +++ b/components/bt/host/bluedroid/btc/core/btc_storage.c @@ -196,6 +196,32 @@ bt_status_t btc_storage_load_bonded_devices(void) BTC_TRACE_DEBUG("Storage load rslt %d\n", status); return status; } + +/******************************************************************************* +** +** Function btc_storage_update_active_device +** +** Description BTC storage API - Once an ACL link is established and remote +** bd_addr is already stored in NVRAM, update the config and update +** the remote device to be the newest active device, The updates will +** not be stored into NVRAM immediately. +** +** Returns BT_STATUS_SUCCESS if successful, BT_STATUS_FAIL otherwise +** +*******************************************************************************/ +bool btc_storage_update_active_device(bt_bdaddr_t *remote_bd_addr) +{ + bdstr_t bdstr; + bdaddr_to_string(remote_bd_addr, bdstr, sizeof(bdstr)); + bool ret = false; + BTC_TRACE_DEBUG("Update active device: Remote device:%s\n", bdstr); + + btc_config_lock(); + ret = btc_config_update_newest_section(bdstr); + btc_config_unlock(); + + return ret ? BT_STATUS_SUCCESS : BT_STATUS_FAIL; +} #endif ///SMP_INCLUDED == TRUE /******************************************************************************* @@ -308,32 +334,6 @@ bt_status_t btc_storage_get_bonded_bt_devices_list(bt_bdaddr_t *bond_dev, int *d return BT_STATUS_SUCCESS; } -/******************************************************************************* -** -** Function btc_storage_update_active_device -** -** Description BTC storage API - Once an ACL link is established and remote -** bd_addr is already stored in NVRAM, update the config and update -** the remote device to be the newest active device, The updates will -** not be stored into NVRAM immediately. -** -** Returns BT_STATUS_SUCCESS if successful, BT_STATUS_FAIL otherwise -** -*******************************************************************************/ -bool btc_storage_update_active_device(bt_bdaddr_t *remote_bd_addr) -{ - bdstr_t bdstr; - bdaddr_to_string(remote_bd_addr, bdstr, sizeof(bdstr)); - bool ret = false; - BTC_TRACE_DEBUG("Update active device: Remote device:%s\n", bdstr); - - btc_config_lock(); - ret = btc_config_update_newest_section(bdstr); - btc_config_unlock(); - - return ret ? BT_STATUS_SUCCESS : BT_STATUS_FAIL; -} - #if (defined BTC_HH_INCLUDED && BTC_HH_INCLUDED == TRUE) /******************************************************************************* * diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c index 99ef66ef724..2e6c7b8d250 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c +++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c @@ -2076,6 +2076,10 @@ void btc_gap_ble_call_handler(btc_msg_t *msg) params.addr_type = arg_5->periodic_adv_create_sync.params.addr_type; params.skip = arg_5->periodic_adv_create_sync.params.skip; params.sync_timeout = arg_5->periodic_adv_create_sync.params.sync_timeout; + #if (CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH) + params.reports_disabled = arg_5->periodic_adv_create_sync.params.reports_disabled; + params.filter_duplicates = arg_5->periodic_adv_create_sync.params.filter_duplicates; + #endif memcpy(params.addr, arg_5->periodic_adv_create_sync.params.addr, sizeof(BD_ADDR)); BTC_TRACE_DEBUG("BTC_GAP_BLE_PERIODIC_ADV_CREATE_SYNC"); diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c index 839678fe892..3dc53f20be7 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c +++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c @@ -770,6 +770,33 @@ static void btc_gap_get_page_timeout(void) BTA_DmGetPageTimeout(btc_gap_bt_get_page_timeout_cmpl_callback); } +static void btc_gap_bt_set_acl_pkt_types_cmpl_callback(void *p_data) +{ + tBTA_SET_ACL_PKT_TYPES_RESULTS *result = (tBTA_SET_ACL_PKT_TYPES_RESULTS *)p_data; + esp_bt_gap_cb_param_t param; + bt_status_t ret; + btc_msg_t msg; + msg.sig = BTC_SIG_API_CB; + msg.pid = BTC_PID_GAP_BT; + msg.act = BTC_GAP_BT_SET_ACL_PKT_TYPES_EVT; + + param.set_acl_pkt_types.status = btc_btm_status_to_esp_status(result->status); + memcpy(param.set_acl_pkt_types.bda, result->rem_bda, sizeof(esp_bd_addr_t)); + param.set_acl_pkt_types.pkt_types = result->pkt_types; + + ret = btc_transfer_context(&msg, ¶m, sizeof(esp_bt_gap_cb_param_t), NULL, NULL); + if (ret != BT_STATUS_SUCCESS) { + BTC_TRACE_ERROR("%s btc_transfer_context failed\n", __func__); + } +} + +static void btc_gap_set_acl_pkt_types(btc_gap_bt_args_t *arg) +{ + BTA_DmSetAclPktTypes(arg->set_acl_pkt_types.bda.address, + arg->set_acl_pkt_types.pkt_types, + btc_gap_bt_set_acl_pkt_types_cmpl_callback); +} + static void btc_gap_bt_read_remote_name_cmpl_callback(void *p_data) { tBTA_REMOTE_DEV_NAME *result = (tBTA_REMOTE_DEV_NAME *)p_data; @@ -844,6 +871,7 @@ void btc_gap_bt_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src) case BTC_GAP_BT_ACT_SET_QOS: case BTC_GAP_BT_ACT_SET_PAGE_TIMEOUT: case BTC_GAP_BT_ACT_GET_PAGE_TIMEOUT: + case BTC_GAP_BT_ACT_SET_ACL_PKT_TYPES: break; case BTC_GAP_BT_ACT_PASSKEY_REPLY: case BTC_GAP_BT_ACT_CONFIRM_REPLY: @@ -910,6 +938,7 @@ void btc_gap_bt_arg_deep_free(btc_msg_t *msg) case BTC_GAP_BT_ACT_SET_QOS: case BTC_GAP_BT_ACT_SET_PAGE_TIMEOUT: case BTC_GAP_BT_ACT_GET_PAGE_TIMEOUT: + case BTC_GAP_BT_ACT_SET_ACL_PKT_TYPES: break; case BTC_GAP_BT_ACT_PASSKEY_REPLY: case BTC_GAP_BT_ACT_CONFIRM_REPLY: @@ -1016,6 +1045,10 @@ void btc_gap_bt_call_handler(btc_msg_t *msg) btc_gap_get_page_timeout(); break; } + case BTC_GAP_BT_ACT_SET_ACL_PKT_TYPES: { + btc_gap_set_acl_pkt_types(arg); + break; + } default: break; } @@ -1060,6 +1093,7 @@ void btc_gap_bt_cb_deep_free(btc_msg_t *msg) case BTC_GAP_BT_QOS_EVT: case BTC_GAP_BT_SET_PAGE_TO_EVT: case BTC_GAP_BT_GET_PAGE_TO_EVT: + case BTC_GAP_BT_SET_ACL_PKT_TYPES_EVT: case BTC_GAP_BT_CFM_REQ_EVT: case BTC_GAP_BT_KEY_NOTIF_EVT: case BTC_GAP_BT_KEY_REQ_EVT: @@ -1149,6 +1183,10 @@ void btc_gap_bt_cb_handler(btc_msg_t *msg) btc_gap_bt_cb_to_app(ESP_BT_GAP_GET_PAGE_TO_EVT, (esp_bt_gap_cb_param_t *)msg->arg); break; } + case BTC_GAP_BT_SET_ACL_PKT_TYPES_EVT: { + btc_gap_bt_cb_to_app(ESP_BT_GAP_ACL_PKT_TYPE_CHANGED_EVT, (esp_bt_gap_cb_param_t *)msg->arg); + break; + } default: BTC_TRACE_ERROR("%s: Unhandled event (%d)!\n", __FUNCTION__, msg->act); break; diff --git a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c index 4aefcd4669d..e69eed48f32 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c +++ b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c @@ -926,6 +926,7 @@ void btc_gattc_cb_handler(btc_msg_t *msg) } case BTA_GATTC_CONNECT_EVT: { tBTA_GATTC_CONNECT *connect = &arg->connect; +#if (SMP_INCLUDED == TRUE) bt_bdaddr_t bt_addr; memcpy(bt_addr.address, connect->remote_bda, sizeof(bt_addr.address)); @@ -935,7 +936,7 @@ void btc_gattc_cb_handler(btc_msg_t *msg) bt_addr.address[2], bt_addr.address[3], bt_addr.address[4], bt_addr.address[5]); } - +#endif ///SMP_INCLUDED == TRUE gattc_if = connect->client_if; param.connect.conn_id = BTC_GATT_GET_CONN_ID(connect->conn_id); param.connect.link_role = connect->link_role; diff --git a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c index 1411965dbc5..df9a4ceb196 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c +++ b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c @@ -901,6 +901,7 @@ void btc_gatts_cb_handler(btc_msg_t *msg) btc_gatts_cb_to_app(ESP_GATTS_STOP_EVT, gatts_if, ¶m); break; case BTA_GATTS_CONNECT_EVT: { +#if (SMP_INCLUDED == TRUE) bt_bdaddr_t bt_addr; memcpy(bt_addr.address, p_data->conn.remote_bda, sizeof(bt_addr.address)); if (btc_storage_update_active_device(&bt_addr)) { @@ -909,7 +910,7 @@ void btc_gatts_cb_handler(btc_msg_t *msg) bt_addr.address[2], bt_addr.address[3], bt_addr.address[4], bt_addr.address[5]); } - +#endif ///SMP_INCLUDED == TRUE gatts_if = p_data->conn.server_if; param.connect.conn_id = BTC_GATT_GET_CONN_ID(p_data->conn.conn_id); param.connect.link_role = p_data->conn.link_role; diff --git a/components/bt/host/bluedroid/btc/profile/std/hf_ag/bta_ag_co.c b/components/bt/host/bluedroid/btc/profile/std/hf_ag/bta_ag_co.c index 84d006647a8..6000f8324c2 100644 --- a/components/bt/host/bluedroid/btc/profile/std/hf_ag/bta_ag_co.c +++ b/components/bt/host/bluedroid/btc/profile/std/hf_ag/bta_ag_co.c @@ -82,7 +82,7 @@ static bta_ag_co_cb_t *bta_ag_co_cb_ptr; #define bta_ag_co_cb (*bta_ag_co_cb_ptr) #endif /* HFP_DYNAMIC_MEMORY == FALSE */ -static UINT8 hf_air_mode = BTM_SCO_AIR_MODE_TRANSPNT; +static UINT8 hf_air_mode = BTM_SCO_AIR_MODE_UNKNOWN; static UINT8 hf_inout_pkt_size = 0; /* ========================================================================= diff --git a/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c b/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c index d04ec79f5c1..129d1b17893 100644 --- a/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c +++ b/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c @@ -68,7 +68,7 @@ static UINT16 btc_max_hf_clients = BTC_HF_NUM_CB; #if HFP_DYNAMIC_MEMORY == FALSE static hf_local_param_t hf_local_param[BTC_HF_NUM_CB]; #else -static hf_local_param_t *hf_local_param; +static hf_local_param_t *hf_local_param = NULL; #endif #if (BTM_WBS_INCLUDED == TRUE) @@ -317,6 +317,19 @@ bt_status_t btc_hf_init(void) int idx = 0; BTC_TRACE_DEBUG("%s - max_hf_clients=%d", __func__, btc_max_hf_clients); + +#if HFP_DYNAMIC_MEMORY == TRUE + if (hf_local_param != NULL) { + return BT_STATUS_FAIL; + } + + if ((hf_local_param = (hf_local_param_t *)osi_malloc(BTC_HF_NUM_CB * sizeof(hf_local_param_t))) == NULL) { + APPL_TRACE_ERROR("%s malloc failed!", __func__); + return BT_STATUS_NOMEM; + } + memset((void *)hf_local_param, 0, BTC_HF_NUM_CB * sizeof(hf_local_param_t)); +#endif + /* Invoke the enable service API to the core to set the appropriate service_id * Internally, the HSP_SERVICE_ID shall also be enabled if HFP is enabled (phone) * othwerwise only HSP is enabled (tablet)*/ @@ -345,13 +358,16 @@ void btc_hf_deinit(void) { BTC_TRACE_EVENT("%s", __FUNCTION__); btc_dm_disable_service(BTA_HFP_SERVICE_ID); + hf_local_param[0].btc_hf_cb.initialized = false; +} + +static void btc_hf_cb_release(void) +{ #if HFP_DYNAMIC_MEMORY == TRUE if (hf_local_param) { osi_free(hf_local_param); hf_local_param = NULL; } -#else - hf_local_param[0].btc_hf_cb.initialized = false; #endif } @@ -1251,9 +1267,12 @@ void btc_hf_cb_handler(btc_msg_t *msg) switch (event) { case BTA_AG_ENABLE_EVT: + break; case BTA_AG_DISABLE_EVT: + { + btc_hf_cb_release(); break; - + } case BTA_AG_REGISTER_EVT: { idx = p_data->hdr.handle - 1; diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_bt.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_bt.h index 1e1d4c474b4..c2e363b7971 100644 --- a/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_bt.h +++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_bt.h @@ -33,6 +33,7 @@ typedef enum { BTC_GAP_BT_QOS_EVT, BTC_GAP_BT_SET_PAGE_TO_EVT, BTC_GAP_BT_GET_PAGE_TO_EVT, + BTC_GAP_BT_SET_ACL_PKT_TYPES_EVT, }btc_gap_bt_evt_t; typedef enum { @@ -55,6 +56,7 @@ typedef enum { BTC_GAP_BT_ACT_SET_QOS, BTC_GAP_BT_ACT_SET_PAGE_TIMEOUT, BTC_GAP_BT_ACT_GET_PAGE_TIMEOUT, + BTC_GAP_BT_ACT_SET_ACL_PKT_TYPES, } btc_gap_bt_act_t; /* btc_bt_gap_args_t */ @@ -156,6 +158,12 @@ typedef union { uint16_t page_to; } set_page_to; + // BTC_GAP_BT_ACT_SET_ACL_PKT_TYPES + struct set_acl_pkt_types_args { + bt_bdaddr_t bda; + uint16_t pkt_types; + } set_acl_pkt_types; + } btc_gap_bt_args_t; void btc_gap_bt_call_handler(btc_msg_t *msg); diff --git a/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c b/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c index 577e341aa41..5cd777c5a3e 100644 --- a/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c +++ b/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,6 +63,7 @@ typedef struct { int tx_mtu; uint8_t *write_data; osi_alarm_t *close_alarm; + void *alarm_arg; uint8_t role; uint16_t security; esp_bd_addr_t addr; @@ -192,6 +193,7 @@ static l2cap_slot_t *l2cap_malloc_slot(void) (*slot)->is_server = false; (*slot)->write_data = NULL; (*slot)->close_alarm = NULL; + (*slot)->alarm_arg = NULL; /* clear the old event bits */ if (l2cap_local_param.tx_event_group) { xEventGroupClearBits(l2cap_local_param.tx_event_group, SLOT_WRITE_BIT(i) | SLOT_CLOSE_BIT(i)); @@ -246,23 +248,41 @@ static void l2cap_free_slot(l2cap_slot_t *slot) free_slot_data(&slot->rx); if (slot->close_alarm) { osi_alarm_free(slot->close_alarm); + if (slot->alarm_arg) { + osi_free(slot->alarm_arg); + slot->alarm_arg = NULL; + } } osi_free(slot); } +static void l2cap_free_pending_slots(void) +{ + l2cap_slot_t *slot = NULL; + for (size_t i = 1; i <= BTA_JV_MAX_L2C_CONN; i++) { + slot = l2cap_local_param.l2cap_slots[i]; + if (slot) { + BTC_TRACE_WARNING("%s found slot(handle=0x%x) pending to close, close it now!", __func__, slot->handle); + l2cap_free_slot(slot); + } + } +} + static void close_timeout_handler(void *arg) { btc_msg_t msg; bt_status_t status; + l2cap_slot_t *slot = (l2cap_slot_t *)arg; msg.sig = BTC_SIG_API_CB; msg.pid = BTC_PID_L2CAP; msg.act = BTA_JV_L2CAP_CLOSE_EVT; - status = btc_transfer_context(&msg, arg, sizeof(tBTA_JV), NULL, NULL); + status = btc_transfer_context(&msg, slot->alarm_arg, sizeof(tBTA_JV), NULL, NULL); - if (arg) { - free(arg); + if (slot->alarm_arg) { + free(slot->alarm_arg); + slot->alarm_arg = NULL; } if (status != BT_STATUS_SUCCESS) { @@ -758,6 +778,7 @@ void btc_l2cap_cb_handler(btc_msg_t *msg) break; case BTA_JV_DISABLE_EVT: param.uninit.status = ESP_BT_L2CAP_SUCCESS; + l2cap_free_pending_slots(); BTA_JvFree(); osi_mutex_free(&l2cap_local_param.l2cap_slot_mutex); if (l2cap_local_param.tx_event_group) { @@ -818,9 +839,11 @@ void btc_l2cap_cb_handler(btc_msg_t *msg) break; } memcpy(p_arg, p_data, sizeof(tBTA_JV)); + slot->alarm_arg = (void *)p_arg; if ((slot->close_alarm = - osi_alarm_new("slot", close_timeout_handler, (void *)p_arg, VFS_CLOSE_TIMEOUT)) == NULL) { + osi_alarm_new("slot", close_timeout_handler, (void *)slot, VFS_CLOSE_TIMEOUT)) == NULL) { free(p_arg); + slot->alarm_arg = NULL; param.close.status = ESP_BT_L2CAP_NO_RESOURCE; osi_mutex_unlock(&l2cap_local_param.l2cap_slot_mutex); BTC_TRACE_ERROR("%s unable to malloc slot close_alarm!", __func__); @@ -828,6 +851,7 @@ void btc_l2cap_cb_handler(btc_msg_t *msg) } if (osi_alarm_set(slot->close_alarm, VFS_CLOSE_TIMEOUT) != OSI_ALARM_ERR_PASS) { free(p_arg); + slot->alarm_arg = NULL; osi_alarm_free(slot->close_alarm); param.close.status = ESP_BT_L2CAP_BUSY; osi_mutex_unlock(&l2cap_local_param.l2cap_slot_mutex); diff --git a/components/bt/host/bluedroid/btc/profile/std/sdp/btc_sdp.c b/components/bt/host/bluedroid/btc/profile/std/sdp/btc_sdp.c index c67dd712038..143ae336ea6 100644 --- a/components/bt/host/bluedroid/btc/profile/std/sdp/btc_sdp.c +++ b/components/bt/host/bluedroid/btc/profile/std/sdp/btc_sdp.c @@ -114,6 +114,44 @@ static void set_sdp_handle(int id, int handle) osi_mutex_unlock(&sdp_local_param.sdp_slot_mutex); } + +static bool get_sdp_record_by_handle(int handle, bluetooth_sdp_record* record) +{ + sdp_slot_t *slot = NULL; + + osi_mutex_lock(&sdp_local_param.sdp_slot_mutex, OSI_MUTEX_MAX_TIMEOUT); + + for (int i = 0; i < SDP_MAX_RECORDS; i++) { + slot = sdp_local_param.sdp_slots[i]; + if ((slot != NULL) && (slot->sdp_handle == handle)) { + memcpy(record, slot->record_data, sizeof(bluetooth_sdp_record)); + osi_mutex_unlock(&sdp_local_param.sdp_slot_mutex); + return true; + } + } + + osi_mutex_unlock(&sdp_local_param.sdp_slot_mutex); + return false; +} + +static int get_sdp_slot_id_by_handle(int handle) +{ + sdp_slot_t *slot = NULL; + + osi_mutex_lock(&sdp_local_param.sdp_slot_mutex, OSI_MUTEX_MAX_TIMEOUT); + + for (int i = 0; i < SDP_MAX_RECORDS; i++) { + slot = sdp_local_param.sdp_slots[i]; + if ((slot != NULL) && (slot->sdp_handle == handle)) { + osi_mutex_unlock(&sdp_local_param.sdp_slot_mutex); + return i; + } + } + + osi_mutex_unlock(&sdp_local_param.sdp_slot_mutex); + return -1; +} + static sdp_slot_t *start_create_sdp(int id) { sdp_slot_t *sdp_slot = NULL; @@ -257,7 +295,6 @@ static int free_sdp_slot(int id) static int add_raw_sdp(const bluetooth_sdp_record* rec) { tSDP_PROTOCOL_ELEM protoList [2]; - UINT16 service = 0; UINT16 browse = UUID_SERVCLASS_PUBLIC_BROWSE_GROUP; bool status = true; // Buffer capable to hold 2, 4 and 16-byte UUIDs @@ -273,18 +310,15 @@ static int add_raw_sdp(const bluetooth_sdp_record* rec) return sdp_handle; } - if (rec->hdr.bt_uuid.len == 16) { - memcpy(&service, &rec->hdr.bt_uuid.uuid.uuid128[2], sizeof(service)); - UINT8_TO_BE_STREAM(p_temp, (UUID_DESC_TYPE << 3) | SIZE_SIXTEEN_BYTES); - ARRAY_TO_BE_STREAM(p_temp, rec->hdr.bt_uuid.uuid.uuid128, LEN_UUID_128); - } else if (rec->hdr.bt_uuid.len == 2) { - memcpy(&service, &rec->hdr.bt_uuid.uuid.uuid16, sizeof(service)); - UINT8_TO_BE_STREAM(p_temp, (UUID_DESC_TYPE << 3) | SIZE_TWO_BYTES); - UINT16_TO_BE_STREAM(p_temp, rec->hdr.bt_uuid.uuid.uuid16); - } else if (rec->hdr.bt_uuid.len == 4) { - memcpy(&service, &rec->hdr.bt_uuid.uuid.uuid16, sizeof(service)); - UINT8_TO_BE_STREAM(p_temp, (UUID_DESC_TYPE << 3) | SIZE_FOUR_BYTES); - UINT32_TO_BE_STREAM(p_temp, rec->hdr.bt_uuid.uuid.uuid32); + if (rec->hdr.bt_uuid.len == ESP_UUID_LEN_16) { + UINT8_TO_BE_STREAM (p_temp, (UUID_DESC_TYPE << 3) | SIZE_TWO_BYTES); + UINT16_TO_BE_STREAM (p_temp, rec->hdr.bt_uuid.uuid.uuid16); + } else if (rec->hdr.bt_uuid.len == ESP_UUID_LEN_32) { + UINT8_TO_BE_STREAM (p_temp, (UUID_DESC_TYPE << 3) | SIZE_FOUR_BYTES); + UINT32_TO_BE_STREAM (p_temp, rec->hdr.bt_uuid.uuid.uuid32); + } else if (rec->hdr.bt_uuid.len == ESP_UUID_LEN_128) { + UINT8_TO_BE_STREAM (p_temp, (UUID_DESC_TYPE << 3) | SIZE_SIXTEEN_BYTES); + ARRAY_TO_BE_STREAM (p_temp, rec->hdr.bt_uuid.uuid.uuid128, LEN_UUID_128); } else { SDP_DeleteRecord(sdp_handle); sdp_handle = 0; @@ -331,7 +365,13 @@ static int add_raw_sdp(const bluetooth_sdp_record* rec) sdp_handle = 0; BTC_TRACE_ERROR("%s() FAILED, status = %d", __func__, status); } else { - bta_sys_add_uuid(service); + if (rec->hdr.bt_uuid.len == ESP_UUID_LEN_16) { + bta_sys_add_uuid(rec->hdr.bt_uuid.uuid.uuid16); + } else if (rec->hdr.bt_uuid.len == ESP_UUID_LEN_32) { + bta_sys_add_uuid_32(rec->hdr.bt_uuid.uuid.uuid32); + } else if (rec->hdr.bt_uuid.len == ESP_UUID_LEN_128) { + bta_sys_add_uuid_128((UINT8 *)&rec->hdr.bt_uuid.uuid.uuid128); + } BTC_TRACE_DEBUG("%s(): SDP Registered (handle 0x%08x)", __func__, sdp_handle); } @@ -842,7 +882,8 @@ static void btc_sdp_dm_cback(tBTA_SDP_EVT event, tBTA_SDP* p_data, void* user_da switch (event) { case BTA_SDP_CREATE_RECORD_USER_EVT: { if (p_data->status == BTA_SDP_SUCCESS) { - if(btc_handle_create_record_event((int)user_data) < 0) { + p_data->sdp_create_record.handle = btc_handle_create_record_event((int)user_data); + if (p_data->sdp_create_record.handle < 0) { p_data->status = BTA_SDP_FAILURE; } } @@ -981,9 +1022,29 @@ static void btc_sdp_remove_record(btc_sdp_args_t *arg) break; } + bluetooth_sdp_record rec; + if (get_sdp_record_by_handle(arg->remove_record.record_handle, &rec)) { + if (rec.hdr.bt_uuid.len == ESP_UUID_LEN_16) { + bta_sys_remove_uuid(rec.hdr.bt_uuid.uuid.uuid16); + } else if (rec.hdr.bt_uuid.len == ESP_UUID_LEN_32) { + bta_sys_remove_uuid_32(rec.hdr.bt_uuid.uuid.uuid32); + } else if (rec.hdr.bt_uuid.len == ESP_UUID_LEN_128) { + bta_sys_remove_uuid_128((UINT8 *)&rec.hdr.bt_uuid.uuid.uuid128); + } + } else { + BTC_TRACE_ERROR("%s SDP record with handle %d not found", + __func__, arg->remove_record.record_handle); + return; + } + /* Get the Record handle, and free the slot */ /* The application layer record_handle is equivalent to the id of the btc layer */ - handle = free_sdp_slot(arg->remove_record.record_handle); + int slot = get_sdp_slot_id_by_handle(arg->remove_record.record_handle); + if (slot < 0) { + return; + } + + handle = free_sdp_slot(slot); BTC_TRACE_DEBUG("Sdp Server %s id=%d to handle=0x%08x", __func__, arg->remove_record.record_handle, handle); diff --git a/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c b/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c index 6a366c65abd..0f3c7d9f081 100644 --- a/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c +++ b/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,6 +63,7 @@ typedef struct { int fd; uint8_t *write_data; osi_alarm_t *close_alarm; + void *alarm_arg; esp_spp_role_t role; esp_spp_sec_t security; esp_bd_addr_t addr; @@ -149,6 +150,7 @@ static spp_slot_t *spp_malloc_slot(void) (*slot)->write_data_len = 0; (*slot)->is_writing = false; (*slot)->close_alarm = NULL; + (*slot)->alarm_arg = NULL; /* clear the old event bits */ if (spp_local_param.tx_event_group) { xEventGroupClearBits(spp_local_param.tx_event_group, SLOT_WRITE_BIT(i) | SLOT_CLOSE_BIT(i)); @@ -252,15 +254,17 @@ static void close_timeout_handler(void *arg) { btc_msg_t msg; bt_status_t status; + spp_slot_t *slot = (spp_slot_t *)arg; msg.sig = BTC_SIG_API_CB; msg.pid = BTC_PID_SPP; msg.act = BTA_JV_RFCOMM_CLOSE_EVT; - status = btc_transfer_context(&msg, arg, sizeof(tBTA_JV), NULL, NULL); + status = btc_transfer_context(&msg, slot->alarm_arg, sizeof(tBTA_JV), NULL, NULL); - if (arg) { - osi_free(arg); + if (slot->alarm_arg) { + osi_free(slot->alarm_arg); + slot->alarm_arg = NULL; } if (status != BT_STATUS_SUCCESS) { @@ -284,10 +288,26 @@ static void spp_free_slot(spp_slot_t *slot) free_slot_data(&slot->rx); if (slot->close_alarm) { osi_alarm_free(slot->close_alarm); + if (slot->alarm_arg) { + osi_free(slot->alarm_arg); + slot->alarm_arg = NULL; + } } osi_free(slot); } +static void spp_free_pending_slots(void) +{ + spp_slot_t *slot = NULL; + for (size_t i = 1; i <= MAX_RFC_PORTS; i++) { + slot = spp_local_param.spp_slots[i]; + if (slot) { + BTC_TRACE_WARNING("%s found slot(rfc_handle=0x%x) pending to close, close it now!", __func__, slot->rfc_handle); + spp_free_slot(slot); + } + } +} + static inline void btc_spp_cb_to_app(esp_spp_cb_event_t event, esp_spp_cb_param_t *param) { esp_spp_cb_t btc_spp_cb = (esp_spp_cb_t)btc_profile_cb_get(BTC_PID_SPP); @@ -1193,9 +1213,11 @@ void btc_spp_cb_handler(btc_msg_t *msg) break; } memcpy(p_arg, p_data, sizeof(tBTA_JV)); + slot->alarm_arg = (void *)p_arg; if ((slot->close_alarm = - osi_alarm_new("slot", close_timeout_handler, (void *)p_arg, VFS_CLOSE_TIMEOUT)) == NULL) { + osi_alarm_new("slot", close_timeout_handler, (void *)slot, VFS_CLOSE_TIMEOUT)) == NULL) { free(p_arg); + slot->alarm_arg = NULL; param.close.status = ESP_SPP_NO_RESOURCE; osi_mutex_unlock(&spp_local_param.spp_slot_mutex); BTC_TRACE_ERROR("%s unable to malloc slot close_alarm!", __func__); @@ -1203,6 +1225,7 @@ void btc_spp_cb_handler(btc_msg_t *msg) } if (osi_alarm_set(slot->close_alarm, VFS_CLOSE_TIMEOUT) != OSI_ALARM_ERR_PASS) { free(p_arg); + slot->alarm_arg = NULL; osi_alarm_free(slot->close_alarm); param.close.status = ESP_SPP_BUSY; osi_mutex_unlock(&spp_local_param.spp_slot_mutex); @@ -1314,6 +1337,7 @@ void btc_spp_cb_handler(btc_msg_t *msg) break; case BTA_JV_DISABLE_EVT: param.uninit.status = ESP_SPP_SUCCESS; + spp_free_pending_slots(); BTA_JvFree(); osi_mutex_free(&spp_local_param.spp_slot_mutex); if (spp_local_param.tx_event_group) { diff --git a/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h b/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h index 101ae800667..898978f6218 100644 --- a/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h +++ b/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h @@ -136,6 +136,12 @@ #define UC_BT_BLE_FEAT_PERIODIC_ADV_ENH FALSE #endif +#ifdef CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH +#define UC_BT_BLE_FEAT_CREATE_SYNC_ENH CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH +#else +#define UC_BT_BLE_FEAT_CREATE_SYNC_ENH FALSE +#endif + #ifdef CONFIG_BT_BLE_HIGH_DUTY_ADV_INTERVAL #define UC_BT_BLE_HIGH_DUTY_ADV_INTERVAL CONFIG_BT_BLE_HIGH_DUTY_ADV_INTERVAL #else diff --git a/components/bt/host/bluedroid/common/include/common/bt_target.h b/components/bt/host/bluedroid/common/include/common/bt_target.h index 21a728e247f..f467d11200f 100644 --- a/components/bt/host/bluedroid/common/include/common/bt_target.h +++ b/components/bt/host/bluedroid/common/include/common/bt_target.h @@ -213,6 +213,12 @@ #define BLE_FEAT_PERIODIC_ADV_ENH FALSE #endif +#if (UC_BT_BLE_FEAT_CREATE_SYNC_ENH == TRUE) +#define BLE_FEAT_CREATE_SYNC_ENH TRUE +#else +#define BLE_FEAT_CREATE_SYNC_ENH FALSE +#endif + #if (UC_BT_BLE_HIGH_DUTY_ADV_INTERVAL == TRUE) #define BLE_HIGH_DUTY_ADV_INTERVAL TRUE #else @@ -1012,7 +1018,7 @@ /* TRUE to include Sniff Subrating */ #if (BTA_DM_PM_INCLUDED == TRUE) #ifndef BTM_SSR_INCLUDED -#define BTM_SSR_INCLUDED TRUE +#define BTM_SSR_INCLUDED FALSE #endif #endif /* BTA_DM_PM_INCLUDED */ diff --git a/components/bt/host/bluedroid/hci/hci_hal_h4.c b/components/bt/host/bluedroid/hci/hci_hal_h4.c index 121a4d51016..46284333eb9 100644 --- a/components/bt/host/bluedroid/hci/hci_hal_h4.c +++ b/components/bt/host/bluedroid/hci/hci_hal_h4.c @@ -600,7 +600,8 @@ int ble_hs_hci_rx_evt(uint8_t *hci_ev, void *arg) { if(esp_bluedroid_get_status() == ESP_BLUEDROID_STATUS_UNINITIALIZED) { - return 0; + ble_hci_trans_buf_free(hci_ev); + return 0; } uint16_t len = hci_ev[1] + 3; uint8_t *data = (uint8_t *)malloc(len); diff --git a/components/bt/host/bluedroid/stack/btm/btm_acl.c b/components/bt/host/bluedroid/stack/btm/btm_acl.c index 96e0b144756..4b7e7eedcea 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_acl.c +++ b/components/bt/host/bluedroid/stack/btm/btm_acl.c @@ -2117,6 +2117,70 @@ tBTM_STATUS BTM_ReadTxPower (BD_ADDR remote_bda, tBT_TRANSPORT transport, tBTM_C return (BTM_UNKNOWN_ADDR); } +tBTM_STATUS BTM_SetAclPktTypes(BD_ADDR remote_bda, UINT16 pkt_types, tBTM_CMPL_CB *p_cb) +{ +#if CLASSIC_BT_INCLUDED == TRUE + tBTM_STATUS ret = BTM_UNKNOWN_ADDR; + tACL_CONN *p; + tBTM_SET_ACL_PKT_TYPES_RESULTS result; + + /* If someone already waiting on the version, do not allow another */ + if (btm_cb.devcb.p_set_acl_pkt_types_cmpl_cb) { + result.status = HCI_ERR_REPEATED_ATTEMPTS; + (*p_cb)(&result); + return (BTM_BUSY);; + } + + p = btm_bda_to_acl(remote_bda, BT_TRANSPORT_BR_EDR); + + if (p != (tACL_CONN *)NULL) { + btu_start_timer (&btm_cb.devcb.set_acl_pkt_types_timer, BTU_TTYPE_BTM_ACL, + BTM_DEV_REPLY_TIMEOUT); + + btm_cb.devcb.p_set_acl_pkt_types_cmpl_cb = p_cb; + if (btm_set_packet_types(p, pkt_types) != BTM_CMD_STARTED) { + btm_cb.devcb.p_set_acl_pkt_types_cmpl_cb = NULL; + btu_stop_timer (&btm_cb.devcb.set_acl_pkt_types_timer); + result.status = HCI_ERR_MEMORY_FULL; + (*p_cb)(&result); + ret = BTM_NO_RESOURCES; + } else { + ret = BTM_CMD_STARTED; + } + } + /* If here, no BD Addr found */ + return ret; +#else + return BTM_NO_RESOURCES; +#endif +} + +void btm_acl_pkt_types_changed(UINT8 status, UINT16 handle, UINT16 pkt_types) +{ +#if CLASSIC_BT_INCLUDED == TRUE + BTM_TRACE_DEBUG ("btm_acl_pkt_types_changed\n"); + tACL_CONN *conn = NULL; + tBTM_SET_ACL_PKT_TYPES_RESULTS results; + btu_stop_timer (&btm_cb.devcb.set_acl_pkt_types_timer); + + /* If there is a callback registered for packet types changed, call it */ + if (btm_cb.devcb.p_set_acl_pkt_types_cmpl_cb) { + if (status == HCI_SUCCESS) { + results.status = BTM_SUCCESS; + } else { + results.status = BTM_BAD_VALUE_RET; + } + results.pkt_types = pkt_types; + /* Search through the list of active channels for the correct BD Addr */ + if ((conn = btm_handle_to_acl(handle)) != NULL) { + memcpy(results.rem_bda, conn->remote_addr, BD_ADDR_LEN); + (*btm_cb.devcb.p_set_acl_pkt_types_cmpl_cb)(&results); + } + btm_cb.devcb.p_set_acl_pkt_types_cmpl_cb = NULL; + } +#endif +} + #if (BLE_INCLUDED == TRUE) tBTM_STATUS BTM_BleReadAdvTxPower(tBTM_CMPL_CB *p_cb) { diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c index 2a4c9ce85e3..e5dc3b42ac1 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c @@ -11,6 +11,7 @@ #include #include "l2c_int.h" #if (BLE_50_FEATURE_SUPPORT == TRUE) +#define SET_BIT(t, n) (t |= 1UL << (n)) tBTM_BLE_EXTENDED_CB extend_adv_cb; tBTM_BLE_5_HCI_CBACK ble_5_hci_cb; @@ -788,14 +789,32 @@ tBTM_STATUS BTM_BlePeriodicAdvCreateSync(tBTM_BLE_Periodic_Sync_Params *params) } if ((params->sync_timeout < 0x0a || params->sync_timeout > 0x4000) - || (params->filter_policy > 0x01) || (params->addr_type > 0x01) || + || (params->filter_policy > 0x01) + #if (CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH) + || (params->reports_disabled > 0x01) + || (params->filter_duplicates > 0x01) + #endif + || (params->addr_type > 0x01) || (params->sid > 0xf) || (params->skip > 0x01F3)) { status = BTM_ILLEGAL_VALUE; BTM_TRACE_ERROR("%s, The sync parameters is invalid.", __func__); goto end; } + uint8_t option = 0x00; + if (params->filter_policy) { + SET_BIT(option, 0); + } + + #if (CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH) + if (params->reports_disabled) { + SET_BIT(option, 1); + } + if (params->filter_duplicates) { + SET_BIT(option, 2); + } + #endif - if (!btsnd_hcic_ble_periodic_adv_create_sync(params->filter_policy, params->sid, params->addr_type, + if (!btsnd_hcic_ble_periodic_adv_create_sync(option, params->sid, params->addr_type, params->addr, params->sync_timeout, 0)) { BTM_TRACE_ERROR("LE PA CreateSync cmd failed"); status = BTM_ILLEGAL_VALUE; diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c b/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c index dd6c0a176ea..4cb282b79ad 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c @@ -298,7 +298,7 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_ addr_type = p_dev_rec->ble.static_addr_type; } - // white list must be public address or static random address + // The device to be added to white list must be public address or random address if(addr_type == BLE_ADDR_RANDOM) { /* A static address is a 48-bit randomly generated address and shall meet the following requirements: @@ -307,8 +307,7 @@ BOOLEAN btm_update_dev_to_white_list(BOOLEAN to_add, BD_ADDR bd_addr, tBLE_ADDR_ • All bits of the random part of the address shall not be equal to 0 */ invalid_rand_addr_b[0] = invalid_rand_addr_b[0] | BT_STATIC_RAND_ADDR_MASK; - if((bd_addr[0] & BT_STATIC_RAND_ADDR_MASK) == BT_STATIC_RAND_ADDR_MASK - && memcmp(invalid_rand_addr_a, bd_addr, BD_ADDR_LEN) != 0 + if(memcmp(invalid_rand_addr_a, bd_addr, BD_ADDR_LEN) != 0 && memcmp(invalid_rand_addr_b, bd_addr, BD_ADDR_LEN) != 0){ // do nothing } else { diff --git a/components/bt/host/bluedroid/stack/btm/btm_inq.c b/components/bt/host/bluedroid/stack/btm/btm_inq.c index 21ebe81b9b2..b8da2327951 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_inq.c +++ b/components/bt/host/bluedroid/stack/btm/btm_inq.c @@ -2535,9 +2535,125 @@ void BTM_AddEirService( UINT32 *p_eir_uuid, UINT16 uuid16 ) } } + +/******************************************************************************* +** +** Function btm_compare_uuid +** +** Description Helper function for custom service managing routines. +** +** Parameters uuid1 - pointer to the first tBT_UUID struct +** uuid2 - pointer to the second tBT_UUID struct +** +** Returns true if UUID structs are identical +** +*******************************************************************************/ +static bool btm_compare_uuid(tBT_UUID *uuid1, tBT_UUID *uuid2) +{ + if (uuid1->len != uuid2->len) { + return FALSE; + } + + return (memcmp(&uuid1->uu, &uuid2->uu, uuid1->len) == 0); +} + +/******************************************************************************* +** +** Function btm_find_empty_custom_uuid_slot +** +** Description Helper function for custom service managing routines. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns Slot number if there is empty slot, +** otherwise - BTA_EIR_SERVER_NUM_CUSTOM_UUID +** +*******************************************************************************/ +static UINT8 btm_find_empty_custom_uuid_slot(tBT_UUID *custom_uuid, tBT_UUID uuid) +{ + for (UINT8 xx = 0; xx < BTA_EIR_SERVER_NUM_CUSTOM_UUID; xx++) { + if (custom_uuid[xx].len == 0) { + return xx; + } + } + return BTA_EIR_SERVER_NUM_CUSTOM_UUID; +} + +/******************************************************************************* +** +** Function btm_find_match_custom_uuid_slot +** +** Description Helper function for custom service managing routines. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns Slot number if given UUID is already in slots array, +** otherwise - BTA_EIR_SERVER_NUM_CUSTOM_UUID +** +*******************************************************************************/ +static UINT8 btm_find_match_custom_uuid_slot(tBT_UUID *custom_uuid, tBT_UUID uuid) +{ + for (UINT8 xx = 0; xx < BTA_EIR_SERVER_NUM_CUSTOM_UUID; xx++) { + if (btm_compare_uuid(&custom_uuid[xx], &uuid)) { + return xx; + } + } + return BTA_EIR_SERVER_NUM_CUSTOM_UUID; +} + +/******************************************************************************* +** +** Function BTM_HasCustomEirService +** +** Description This function is called to know if UUID is already in custom +** UUID list. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns TRUE - if found +** FALSE - if not found +** +*******************************************************************************/ +BOOLEAN BTM_HasCustomEirService(tBT_UUID *custom_uuid, tBT_UUID uuid) +{ + UINT8 match_slot = btm_find_match_custom_uuid_slot(custom_uuid, uuid); + + if (match_slot == BTA_EIR_SERVER_NUM_CUSTOM_UUID) { + return FALSE; + } + return TRUE; +} + /******************************************************************************* ** -** Function BTM_RemoveEirService +** Function BTM_AddCustomEirService +** +** Description This function is called to add a custom UUID. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns None +** +*******************************************************************************/ +void BTM_AddCustomEirService(tBT_UUID *custom_uuid, tBT_UUID uuid) +{ + UINT8 empty_slot = btm_find_empty_custom_uuid_slot(custom_uuid, uuid); + + if (empty_slot == BTA_EIR_SERVER_NUM_CUSTOM_UUID) { + BTM_TRACE_WARNING("No space to add UUID for EIR"); + } else { + memcpy(&(custom_uuid[empty_slot]), &(uuid), sizeof(tBT_UUID)); + BTM_TRACE_EVENT("UUID saved in %d slot", empty_slot); + } +} + +/******************************************************************************* +** +** Function BTM_RemoveCustomEirService ** ** Description This function is called to remove a service in bit map of UUID list. ** @@ -2557,6 +2673,30 @@ void BTM_RemoveEirService( UINT32 *p_eir_uuid, UINT16 uuid16 ) } } +/******************************************************************************* +** +** Function BTM_RemoveCustomEirService +** +** Description This function is called to remove a a custom UUID. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns None +** +*******************************************************************************/ +void BTM_RemoveCustomEirService(tBT_UUID *custom_uuid, tBT_UUID uuid) +{ + UINT8 match_slot = btm_find_match_custom_uuid_slot(custom_uuid, uuid); + + if (match_slot == BTA_EIR_SERVER_NUM_CUSTOM_UUID) { + BTM_TRACE_WARNING("UUID is not found for EIR"); + return; + } else { + memset(&(custom_uuid[match_slot]), 0, sizeof(tBT_UUID)); + } +} + /******************************************************************************* ** ** Function BTM_GetEirSupportedServices diff --git a/components/bt/host/bluedroid/stack/btm/include/btm_int.h b/components/bt/host/bluedroid/stack/btm/include/btm_int.h index 3b7a90d9b1f..b4c6d7c0395 100644 --- a/components/bt/host/bluedroid/stack/btm/include/btm_int.h +++ b/components/bt/host/bluedroid/stack/btm/include/btm_int.h @@ -218,6 +218,9 @@ tBTM_CMPL_CB *p_afh_channels_cmpl_cb; /* Callback function to be called TIMER_LIST_ENT page_timeout_set_timer; tBTM_CMPL_CB *p_page_to_set_cmpl_cb; /* Callback function to be called when */ /* set page timeout is completed */ +TIMER_LIST_ENT set_acl_pkt_types_timer; +tBTM_CMPL_CB *p_set_acl_pkt_types_cmpl_cb; /* Callback function to be called when */ +/* set ACL packet types is completed */ #endif DEV_CLASS dev_class; /* Local device class */ @@ -1046,6 +1049,7 @@ tACL_CONN *btm_handle_to_acl (UINT16 hci_handle); void btm_read_link_policy_complete (UINT8 *p); void btm_read_rssi_complete (UINT8 *p); void btm_read_tx_power_complete (UINT8 *p, BOOLEAN is_ble); +void btm_acl_pkt_types_changed(UINT8 status, UINT16 handle, UINT16 pkt_types); void btm_read_link_quality_complete (UINT8 *p); tBTM_STATUS btm_set_packet_types (tACL_CONN *p, UINT16 pkt_types); void btm_process_clk_off_comp_evt (UINT16 hci_handle, UINT16 clock_offset); diff --git a/components/bt/host/bluedroid/stack/btu/btu_hcif.c b/components/bt/host/bluedroid/stack/btu/btu_hcif.c index 52daeafc06e..1b84115423d 100644 --- a/components/bt/host/bluedroid/stack/btu/btu_hcif.c +++ b/components/bt/host/bluedroid/stack/btu/btu_hcif.c @@ -90,7 +90,7 @@ static void btu_hcif_loopback_command_evt (void); static void btu_hcif_data_buf_overflow_evt (void); static void btu_hcif_max_slots_changed_evt (void); static void btu_hcif_read_clock_off_comp_evt (UINT8 *p); -static void btu_hcif_conn_pkt_type_change_evt (void); +static void btu_hcif_conn_pkt_type_change_evt (UINT8 *p); static void btu_hcif_qos_violation_evt (UINT8 *p); static void btu_hcif_page_scan_mode_change_evt (void); static void btu_hcif_page_scan_rep_mode_chng_evt (void); @@ -282,7 +282,7 @@ void btu_hcif_process_event (UNUSED_ATTR UINT8 controller_id, BT_HDR *p_msg) btu_hcif_read_clock_off_comp_evt (p); break; case HCI_CONN_PKT_TYPE_CHANGE_EVT: - btu_hcif_conn_pkt_type_change_evt (); + btu_hcif_conn_pkt_type_change_evt (p); break; case HCI_QOS_VIOLATION_EVT: btu_hcif_qos_violation_evt (p); @@ -1759,8 +1759,19 @@ static void btu_hcif_read_clock_off_comp_evt (UINT8 *p) ** Returns void ** *******************************************************************************/ -static void btu_hcif_conn_pkt_type_change_evt (void) +static void btu_hcif_conn_pkt_type_change_evt (UINT8 *p) { + UINT8 status; + UINT16 handle; + UINT16 pkt_types; + + STREAM_TO_UINT8 (status, p); + STREAM_TO_UINT16 (handle, p); + STREAM_TO_UINT16 (pkt_types, p); + + handle = HCID_GET_HANDLE (handle); + + btm_acl_pkt_types_changed(status, handle, pkt_types); } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_api.c b/components/bt/host/bluedroid/stack/gatt/gatt_api.c index 31cf6c25449..8d8056f6d0f 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_api.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_api.c @@ -122,6 +122,7 @@ BOOLEAN GATTS_NVRegister (const tGATT_APPL_INFO *p_cb_info) return status; } +#if GATTS_ROBUST_CACHING_ENABLED static void gatt_update_for_database_change(void) { UINT8 i; @@ -135,7 +136,7 @@ static void gatt_update_for_database_change(void) } } } - +#endif /* GATTS_ROBUST_CACHING_ENABLED */ /******************************************************************************* ** ** Function GATTS_CreateService @@ -414,7 +415,9 @@ BOOLEAN GATTS_DeleteService (tGATT_IF gatt_if, tBT_UUID *p_svc_uuid, UINT16 svc_ GATT_TRACE_DEBUG ("Delete a new service changed item - the service has not yet started"); osi_free(fixed_queue_try_remove_from_queue(gatt_cb.pending_new_srv_start_q, p_buf)); } else { +#if GATTS_ROBUST_CACHING_ENABLED gatt_update_for_database_change(); +#endif /* GATTS_ROBUST_CACHING_ENABLED */ if (gatt_cb.srv_chg_mode == GATTS_SEND_SERVICE_CHANGE_AUTO) { gatt_proc_srv_chg(); } @@ -527,7 +530,11 @@ tGATT_STATUS GATTS_StartService (tGATT_IF gatt_if, UINT16 service_handle, if ( (p_buf = gatt_sr_is_new_srv_chg(&p_list->asgn_range.app_uuid128, &p_list->asgn_range.svc_uuid, p_list->asgn_range.svc_inst)) != NULL) { + + #if GATTS_ROBUST_CACHING_ENABLED gatt_update_for_database_change(); + #endif /* GATTS_ROBUST_CACHING_ENABLED */ + if (gatt_cb.srv_chg_mode == GATTS_SEND_SERVICE_CHANGE_AUTO) { gatt_proc_srv_chg(); } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_attr.c b/components/bt/host/bluedroid/stack/gatt/gatt_attr.c index ce3b8028950..3ab573426a9 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_attr.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_attr.c @@ -40,7 +40,13 @@ #define BLE_GATT_CL_SUPP_FEAT_BITMASK 0x07 #define GATTP_MAX_NUM_INC_SVR 0 + +#if GATTS_ROBUST_CACHING_ENABLED #define GATTP_MAX_CHAR_NUM 5 +#else +#define GATTP_MAX_CHAR_NUM 2 +#endif /* GATTS_ROBUST_CACHING_ENABLED */ + #define GATTP_MAX_ATTR_NUM (GATTP_MAX_CHAR_NUM * 2 + GATTP_MAX_NUM_INC_SVR + 1) #define GATTP_MAX_CHAR_VALUE_SIZE 50 @@ -196,14 +202,15 @@ tGATT_STATUS gatt_proc_read (UINT16 conn_id, tGATTS_REQ_TYPE type, tGATT_READ_RE GATT_TRACE_DEBUG("%s handle %x", __func__, p_data->handle); - UINT8 tcb_idx = GATT_GET_TCB_IDX(conn_id); - tGATT_TCB *tcb = gatt_get_tcb_by_idx(tcb_idx); - if (p_data->is_long) { p_rsp->attr_value.offset = p_data->offset; } p_rsp->attr_value.handle = p_data->handle; +#if GATTS_ROBUST_CACHING_ENABLED + + UINT8 tcb_idx = GATT_GET_TCB_IDX(conn_id); + tGATT_TCB *tcb = gatt_get_tcb_by_idx(tcb_idx); /* handle request for reading client supported features */ if (p_data->handle == gatt_cb.handle_of_cl_supported_feat) { @@ -229,7 +236,7 @@ tGATT_STATUS gatt_proc_read (UINT16 conn_id, tGATTS_REQ_TYPE type, tGATT_READ_RE memcpy(p_rsp->attr_value.value, &gatt_cb.gatt_sr_supported_feat_mask, 1); return GATT_SUCCESS; } - +#endif /* GATTS_ROBUST_CACHING_ENABLED */ /* handle request for reading service changed des and the others */ status = GATTS_GetAttributeValue(p_data->handle, &len, &value); if(status == GATT_SUCCESS && len > 0 && value) { @@ -241,7 +248,7 @@ tGATT_STATUS gatt_proc_read (UINT16 conn_id, tGATTS_REQ_TYPE type, tGATT_READ_RE } return status; } - +#if GATTS_ROBUST_CACHING_ENABLED static tGATT_STATUS gatt_sr_write_cl_supp_feat(UINT16 conn_id, tGATT_WRITE_REQ *p_data) { UINT8 val_new; @@ -286,7 +293,7 @@ static tGATT_STATUS gatt_sr_write_cl_supp_feat(UINT16 conn_id, tGATT_WRITE_REQ * #endif return GATT_SUCCESS; } - +#endif /* GATTS_ROBUST_CACHING_ENABLED */ /****************************************************************************** ** ** Function gatt_proc_write_req @@ -301,7 +308,7 @@ tGATT_STATUS gatt_proc_write_req(UINT16 conn_id, tGATTS_REQ_TYPE type, tGATT_WRI if(p_data->len > GATT_MAX_ATTR_LEN) { p_data->len = GATT_MAX_ATTR_LEN; } - +#if GATTS_ROBUST_CACHING_ENABLED if (p_data->handle == gatt_cb.handle_of_h_r) { return GATT_WRITE_NOT_PERMIT; } @@ -317,7 +324,7 @@ tGATT_STATUS gatt_proc_write_req(UINT16 conn_id, tGATTS_REQ_TYPE type, tGATT_WRI if (p_data->handle == gatt_cb.handle_of_sr_supported_feat) { return GATT_WRITE_NOT_PERMIT; } - +#endif /* GATTS_ROBUST_CACHING_ENABLED */ return GATTS_SetAttributeValue(p_data->handle, p_data->len, p_data->value); @@ -470,7 +477,7 @@ void gatt_profile_db_init (void) }; GATTS_AddCharDescriptor (service_handle, GATT_PERM_READ | GATT_PERM_WRITE , &descr_uuid, &attr_val, NULL); - +#if GATTS_ROBUST_CACHING_ENABLED /* add Client Supported Features characteristic */ uuid.uu.uuid16 = GATT_UUID_CLIENT_SUP_FEAT; gatt_cb.handle_of_cl_supported_feat = GATTS_AddCharacteristic(service_handle, &uuid, GATT_PERM_READ | GATT_PERM_WRITE, @@ -483,7 +490,7 @@ void gatt_profile_db_init (void) /* add Server Supported Features characteristic */ uuid.uu.uuid16 = GATT_UUID_SERVER_SUP_FEAT; gatt_cb.handle_of_sr_supported_feat = GATTS_AddCharacteristic(service_handle, &uuid, GATT_PERM_READ, GATT_CHAR_PROP_BIT_READ, NULL, NULL); - +#endif /* GATTS_ROBUST_CACHING_ENABLED */ /* start service */ status = GATTS_StartService (gatt_cb.gatt_if, service_handle, GATTP_TRANSPORT_SUPPORTED ); @@ -689,6 +696,7 @@ void GATT_ConfigServiceChangeCCC (BD_ADDR remote_bda, BOOLEAN enable, tBT_TRANSP gatt_cl_start_config_ccc(p_clcb); } +#if GATTS_ROBUST_CACHING_ENABLED /******************************************************************************* ** ** Function gatt_sr_is_cl_robust_caching_supported @@ -700,14 +708,8 @@ void GATT_ConfigServiceChangeCCC (BD_ADDR remote_bda, BOOLEAN enable, tBT_TRANSP *******************************************************************************/ static BOOLEAN gatt_sr_is_cl_robust_caching_supported(tGATT_TCB *p_tcb) { - // Server robust caching not enabled - if (!GATTS_ROBUST_CACHING_ENABLED) { - return FALSE; - } - return (p_tcb->cl_supp_feat & BLE_GATT_CL_SUPP_FEAT_ROBUST_CACHING_BITMASK); } - /******************************************************************************* ** ** Function gatt_sr_is_cl_change_aware @@ -791,4 +793,5 @@ void gatt_sr_update_cl_status(tGATT_TCB *p_tcb, BOOLEAN chg_aware) GATT_TRACE_DEBUG("%s status %d", __func__, chg_aware); } +#endif /* GATTS_ROBUST_CACHING_ENABLED */ #endif /* BLE_INCLUDED == TRUE && GATTS_INCLUDED == TRUE */ diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_db.c b/components/bt/host/bluedroid/stack/gatt/gatt_db.c index 4aebc30f40e..efae6413ad2 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_db.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_db.c @@ -1241,15 +1241,18 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code, // btla-specific ++ else if ( (p_attr->uuid_type == GATT_ATTR_UUID_TYPE_16) && (p_attr->uuid == GATT_UUID_CHAR_CLIENT_CONFIG || - p_attr->uuid == GATT_UUID_CHAR_SRVR_CONFIG) ) + p_attr->uuid == GATT_UUID_CHAR_SRVR_CONFIG || + p_attr->uuid == GATT_UUID_CLIENT_SUP_FEAT || + p_attr->uuid == GATT_UUID_GAP_ICON + ) ) // btla-specific -- { - if (op_code == GATT_REQ_PREPARE_WRITE && offset != 0) { /* does not allow write blob */ - status = GATT_NOT_LONG; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_NOT_LONG,handle:0x%04x",handle); + if (op_code == GATT_REQ_PREPARE_WRITE) { /* does not allow write blob */ + status = GATT_REQ_NOT_SUPPORTED; + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_REQ_NOT_SUPPORTED,handle:0x%04x",handle); } else if (len != max_size) { /* data does not match the required format */ status = GATT_INVALID_ATTR_LEN; - GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INVALID_PDU,handle:0x%04x",handle); + GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INVALID_ATTR_LEN,handle:0x%04x",handle); } else { status = GATT_SUCCESS; } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_sr.c b/components/bt/host/bluedroid/stack/gatt/gatt_sr.c index 1510f448714..79e161c1e38 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_sr.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_sr.c @@ -1448,8 +1448,9 @@ void gatt_attr_process_prepare_write (tGATT_TCB *p_tcb, UINT8 i_rcb, UINT16 hand } if ((prepare_record->error_code_app == GATT_SUCCESS) - && ((status == GATT_INVALID_OFFSET) || (status == GATT_INVALID_ATTR_LEN))){ - prepare_record->error_code_app = status; + // update prepare write status for excute write request + && (status == GATT_INVALID_OFFSET || status == GATT_INVALID_ATTR_LEN || status == GATT_REQ_NOT_SUPPORTED)) { + prepare_record->error_code_app = status; } } @@ -1680,9 +1681,10 @@ static BOOLEAN gatts_proc_ind_ack(tGATT_TCB *p_tcb, UINT16 ack_handle) gatts_proc_srv_chg_ind_ack(p_tcb); /* there is no need to inform the application since srv chg is handled internally by GATT */ continue_processing = FALSE; - +#if GATTS_ROBUST_CACHING_ENABLED /* after receiving ack of svc_chg_ind, reset client status */ gatt_sr_update_cl_status(p_tcb, true); +#endif /* GATTS_ROBUST_CACHING_ENABLED */ } gatts_chk_pending_ind(p_tcb); @@ -1729,6 +1731,7 @@ void gatts_process_value_conf(tGATT_TCB *p_tcb, UINT8 op_code) } } +#if GATTS_ROBUST_CACHING_ENABLED static BOOLEAN gatts_handle_db_out_of_sync(tGATT_TCB *p_tcb, UINT8 op_code, UINT16 len, UINT8 *p_data) { @@ -1808,6 +1811,7 @@ static BOOLEAN gatts_handle_db_out_of_sync(tGATT_TCB *p_tcb, UINT8 op_code, return should_ignore; } +#endif /* GATTS_ROBUST_CACHING_ENABLED */ /******************************************************************************* ** ** Function gatt_server_handle_client_req @@ -1839,11 +1843,12 @@ void gatt_server_handle_client_req (tGATT_TCB *p_tcb, UINT8 op_code, } /* otherwise, ignore the pkt */ } else { +#if GATTS_ROBUST_CACHING_ENABLED // handle database out of sync if (gatts_handle_db_out_of_sync(p_tcb, op_code, len, p_data)) { return; } - +#endif /* GATTS_ROBUST_CACHING_ENABLED */ switch (op_code) { case GATT_REQ_READ_BY_GRP_TYPE: /* discover primary services */ case GATT_REQ_FIND_TYPE_VALUE: /* discover service by UUID */ diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_utils.c b/components/bt/host/bluedroid/stack/gatt/gatt_utils.c index 2dbbcd8d8ac..621b2468886 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_utils.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_utils.c @@ -1090,9 +1090,9 @@ tGATT_TCB *gatt_allocate_tcb_by_bdaddr(BD_ADDR bda, tBT_TRANSPORT transport) p_tcb->transport = transport; } memcpy(p_tcb->peer_bda, bda, BD_ADDR_LEN); -#if (GATTS_INCLUDED == TRUE) +#if GATTS_ROBUST_CACHING_ENABLED gatt_sr_init_cl_status(p_tcb); -#endif ///GATTS_INCLUDED == TRUE +#endif /* GATTS_ROBUST_CACHING_ENABLED */ } return p_tcb; } diff --git a/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h b/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h index 63bf39ed313..1161da62b52 100644 --- a/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h +++ b/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h @@ -539,6 +539,7 @@ typedef struct { tGATT_PROFILE_CLCB profile_clcb[GATT_MAX_APPS]; #endif ///GATTS_INCLUDED == TRUE UINT16 handle_of_h_r; /* Handle of the handles reused characteristic value */ +#if GATTS_ROBUST_CACHING_ENABLED UINT16 handle_of_database_hash; UINT16 handle_of_cl_supported_feat; UINT16 handle_of_sr_supported_feat; @@ -546,6 +547,7 @@ typedef struct { UINT8 gatt_sr_supported_feat_mask; UINT8 gatt_cl_supported_feat_mask; +#endif tGATT_APPL_INFO cb_info; diff --git a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c index 0324002792c..0f6408f0826 100644 --- a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c +++ b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c @@ -1627,14 +1627,14 @@ BOOLEAN btsnd_hcic_ble_create_ext_conn(tHCI_CreatExtConn *p_conn) } -BOOLEAN btsnd_hcic_ble_periodic_adv_create_sync(UINT8 filter_policy, UINT8 adv_sid, +BOOLEAN btsnd_hcic_ble_periodic_adv_create_sync(UINT8 option, UINT8 adv_sid, UINT8 adv_addr_type, BD_ADDR adv_addr, UINT16 sync_timeout, UINT8 unused) { BT_HDR *p; UINT8 *pp; - HCI_TRACE_EVENT("%s, filter_policy = %d, adv_sid = %d, adv_addr_type = %d, sync_timeout = %d, unused = %d", - __func__, filter_policy, adv_sid, adv_addr_type, sync_timeout, unused); + HCI_TRACE_EVENT("%s, option = %d, adv_sid = %d, adv_addr_type = %d, sync_timeout = %d, unused = %d", + __func__, option, adv_sid, adv_addr_type, sync_timeout, unused); HCI_TRACE_EVENT("addr %02x %02x %02x %02x %02x %02x", adv_addr[0], adv_addr[1], adv_addr[2], adv_addr[3], adv_addr[4], adv_addr[5]); uint16_t skip = 0; @@ -1642,7 +1642,7 @@ BOOLEAN btsnd_hcic_ble_periodic_adv_create_sync(UINT8 filter_policy, UINT8 adv_s UINT16_TO_STREAM(pp, HCI_BLE_PERIOD_ADV_CREATE_SYNC); UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PERIODIC_ADV_CREATE_SYNC + 2); - UINT8_TO_STREAM(pp, filter_policy); + UINT8_TO_STREAM(pp, option); UINT8_TO_STREAM(pp, adv_sid); UINT8_TO_STREAM(pp, adv_addr_type); BDADDR_TO_STREAM(pp, adv_addr); diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_api.h index 9e5b2891530..d85a7aec671 100644 --- a/components/bt/host/bluedroid/stack/include/stack/btm_api.h +++ b/components/bt/host/bluedroid/stack/include/stack/btm_api.h @@ -851,6 +851,15 @@ typedef struct { UINT16 page_to; } tBTM_GET_PAGE_TIMEOUT_RESULTS; +/* Structure returned with set ACL packet types event (in tBTM_CMPL_CB callback function) +** in response to BTM_SetAclPktTypes call. +*/ +typedef struct { + tBTM_STATUS status; + BD_ADDR rem_bda; + UINT16 pkt_types; +} tBTM_SET_ACL_PKT_TYPES_RESULTS; + /* Structure returned with set BLE channels event (in tBTM_CMPL_CB callback function) ** in response to BTM_BleSetChannels call. */ @@ -2275,6 +2284,20 @@ tBTM_STATUS BTM_WritePageTimeout(UINT16 timeout, tBTM_CMPL_CB *p_cb); //extern tBTM_STATUS BTM_ReadPageTimeout(tBTM_CMPL_CB *p_cb); +/******************************************************************************* +** +** Function BTM_SetAclPktTypes +** +** Description Send HCI Change Connection Packet Type +** +** Returns +** BTM_SUCCESS Command sent. +** BTM_NO_RESOURCES If out of resources to send the command. +** +*******************************************************************************/ +//extern +tBTM_STATUS BTM_SetAclPktTypes(BD_ADDR remote_bda, UINT16 pkt_types, tBTM_CMPL_CB *p_cb); + /******************************************************************************* ** ** Function BTM_WriteVoiceSettings @@ -4080,6 +4103,22 @@ BOOLEAN BTM_HasEirService( UINT32 *p_eir_uuid, UINT16 uuid16 ); tBTM_EIR_SEARCH_RESULT BTM_HasInquiryEirService( tBTM_INQ_RESULTS *p_results, UINT16 uuid16 ); +/******************************************************************************* +** +** Function BTM_HasCustomEirService +** +** Description This function is called to know if UUID is already in custom +** UUID list. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns TRUE - if found +** FALSE - if not found +** +*******************************************************************************/ +BOOLEAN BTM_HasCustomEirService( tBT_UUID *custom_uuid, tBT_UUID uuid ); + /******************************************************************************* ** ** Function BTM_AddEirService @@ -4095,6 +4134,20 @@ tBTM_EIR_SEARCH_RESULT BTM_HasInquiryEirService( tBTM_INQ_RESULTS *p_results, //extern void BTM_AddEirService( UINT32 *p_eir_uuid, UINT16 uuid16 ); +/******************************************************************************* +** +** Function BTM_AddCustomEirService +** +** Description This function is called to add a custom UUID. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB +** uuid - UUID struct +** +** Returns None +** +*******************************************************************************/ +void BTM_AddCustomEirService(tBT_UUID *custom_uuid, tBT_UUID uuid); + /******************************************************************************* ** ** Function BTM_RemoveEirService @@ -4110,6 +4163,20 @@ void BTM_AddEirService( UINT32 *p_eir_uuid, UINT16 uuid16 ); //extern void BTM_RemoveEirService( UINT32 *p_eir_uuid, UINT16 uuid16 ); +/******************************************************************************* +** +** Function BTM_RemoveCustomEirService +** +** Description This function is called to remove a a custom UUID. +** +** Parameters custom_uuid - pointer to custom_uuid array in tBTA_DM_CB + uuid - UUID struct +** +** Returns None +** +*******************************************************************************/ +void BTM_RemoveCustomEirService(tBT_UUID *custom_uuid, tBT_UUID uuid); + /******************************************************************************* ** ** Function BTM_GetEirSupportedServices diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h index f64500656be..a3085361da1 100644 --- a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h +++ b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h @@ -809,6 +809,10 @@ typedef struct { typedef struct { UINT8 filter_policy; + #if (CONFIG_BT_BLE_FEAT_CREATE_SYNC_ENH) + UINT8 reports_disabled; + UINT8 filter_duplicates; + #endif UINT8 sid; tBLE_ADDR_TYPE addr_type; BD_ADDR addr; diff --git a/components/bt/host/bluedroid/stack/smp/smp_api.c b/components/bt/host/bluedroid/stack/smp/smp_api.c index df8f4cea213..78e295f4f1f 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_api.c +++ b/components/bt/host/bluedroid/stack/smp/smp_api.c @@ -125,7 +125,7 @@ BOOLEAN SMP_Register (tSMP_CALLBACK *p_cback) SMP_TRACE_EVENT ("SMP_Register state=%d", smp_cb.state); if (smp_cb.p_callback != NULL) { - SMP_TRACE_ERROR ("SMP_Register: duplicate registration, overwrite it"); + SMP_TRACE_WARNING ("SMP_Register: duplicate registration, overwrite it"); } smp_cb.p_callback = p_cback; diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index 38f956e5430..64204c6ea0f 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -818,6 +818,29 @@ menu "GAP Service" endmenu +menu "BLE Services" + menuconfig BT_NIMBLE_HID_SERVICE + bool "HID service" + depends on BT_NIMBLE_ENABLED + default n + help + Enable HID service support + + config BT_NIMBLE_SVC_HID_MAX_INSTANCES + depends on BT_NIMBLE_HID_SERVICE + int "Maximum HID service instances" + default 2 + help + Defines maximum number of HID service instances + + config BT_NIMBLE_SVC_HID_MAX_RPTS + depends on BT_NIMBLE_HID_SERVICE + int "Maximum HID Report characteristics per service instance" + default 3 + help + Defines maximum number of report characteristics per service instance +endmenu + config BT_NIMBLE_VS_SUPPORT bool "Enable support for VSC and VSE" help diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 6a14d2a3ec4..42b16f59a3c 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 6a14d2a3ec43697fa332c5b26b955b8778b8c352 +Subproject commit 42b16f59a3c48f3315af8d903a8f03e3de234482 diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index dff3469ba36..ea4efc7fb8e 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -908,6 +908,20 @@ #ifndef MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_READ_PERM #define MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_READ_PERM (0) #endif + +/*** nimble/host/services/hid */ +#ifndef MYNEWT_VAL_BLE_SVC_HID_SERVICE +#define MYNEWT_VAL_BLE_SVC_HID_SERVICE CONFIG_BT_NIMBLE_HID_SERVICE +#endif + +#ifndef MYNEWT_VAL_BLE_SVC_HID_MAX_RPTS +#define MYNEWT_VAL_BLE_SVC_HID_MAX_RPTS CONFIG_BT_NIMBLE_SVC_HID_MAX_RPTS +#endif + +#ifndef MYNEWT_VAL_BLE_SVC_HID_MAX_SVC_INSTANCES +#define MYNEWT_VAL_BLE_SVC_HID_MAX_SVC_INSTANCES CONFIG_BT_NIMBLE_SVC_HID_MAX_INSTANCES +#endif + #ifndef MYNEWT_VAL_BLE_MESH_ADV_TASK_PRIO #define MYNEWT_VAL_BLE_MESH_ADV_TASK_PRIO (9) #endif @@ -1570,6 +1584,15 @@ #define MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_READ_PERM (-1) #endif +#ifndef MYNEWT_VAL_BLE_SVC_DIS_PNP_ID_DEFAULT +#define MYNEWT_VAL_BLE_SVC_DIS_PNP_ID_DEFAULT (NULL) +#endif + +/* Value copied from BLE_SVC_DIS_DEFAULT_READ_PERM */ +#ifndef MYNEWT_VAL_BLE_SVC_DIS_PNP_ID_READ_PERM +#define MYNEWT_VAL_BLE_SVC_DIS_PNP_ID_READ_PERM (-1) +#endif + /*** @apache-mynewt-nimble/nimble/host/services/gap */ #ifndef MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE #define MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE diff --git a/components/bt/include/esp32c2/include/esp_bt.h b/components/bt/include/esp32c2/include/esp_bt.h index 6939470393e..ee1bede7e4d 100644 --- a/components/bt/include/esp32c2/include/esp_bt.h +++ b/components/bt/include/esp32c2/include/esp_bt.h @@ -15,6 +15,7 @@ #include "nimble/nimble_npl.h" #include "../../../../controller/esp32c2/esp_bt_cfg.h" +#include "hal/efuse_hal.h" #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #include "driver/uart.h" @@ -165,7 +166,7 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po */ uint8_t esp_ble_get_chip_rev_version(void); -#define CONFIG_VERSION 0x20230629 +#define CONFIG_VERSION 0x20231124 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -222,9 +223,10 @@ typedef struct { uint8_t cca_drop_mode; /*!< CCA drop mode */ int8_t cca_low_tx_pwr; /*!< Low TX power setting for CCA */ uint8_t main_xtal_freq; /*!< Main crystal frequency */ - uint8_t version_num; /*!< Version number */ - uint8_t ignore_wl_for_direct_adv; /*!< Ignore the white list for directed advertising */ - uint32_t config_magic; /*!< Configuration magic value */ + uint8_t version_num; /*!< Version number */ + uint8_t ignore_wl_for_direct_adv; /*!< Ignore the white list for directed advertising */ + uint8_t csa2_select; /*!< Select CSA#2 */ + uint32_t config_magic; /*!< Configuration magic value */ } esp_bt_controller_config_t; #define BT_CONTROLLER_INIT_CONFIG_DEFAULT() { \ @@ -276,6 +278,7 @@ typedef struct { .main_xtal_freq = CONFIG_XTAL_FREQ, \ .version_num = esp_ble_get_chip_rev_version(), \ .ignore_wl_for_direct_adv = 0, \ + .csa2_select = DEFAULT_BT_LE_50_FEATURE_SUPPORT, \ .config_magic = CONFIG_MAGIC, \ } diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h index a7e17f4aa17..7376ac83971 100644 --- a/components/bt/include/esp32c3/include/esp_bt.h +++ b/components/bt/include/esp32c3/include/esp_bt.h @@ -144,8 +144,21 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status); #ifdef CONFIG_BT_CTRL_AGC_RECORRECT_EN #define BT_CTRL_AGC_RECORRECT_EN CONFIG_BT_CTRL_AGC_RECORRECT_EN +// ESP32-S3 +#if CONFIG_IDF_TARGET_ESP32S3 +#define BT_CTRL_AGC_RECORRECT_NEW 1 +#else +//Check if chip target is ESP32-C3 101 +#if CONFIG_ESP32C3_REV_MIN_101 +#define BT_CTRL_AGC_RECORRECT_NEW 1 +#else +#define BT_CTRL_AGC_RECORRECT_NEW 0 +#endif // CONFIG_ESP32C3_REV_MIN_101 +#endif // CONFIG_IDF_TARGET_ESP32S3 + #else #define BT_CTRL_AGC_RECORRECT_EN 0 +#define BT_CTRL_AGC_RECORRECT_NEW 0 #endif #ifdef CONFIG_BT_CTRL_CODED_AGC_RECORRECT_EN @@ -175,7 +188,7 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status); #define BT_BLE_CCA_MODE (0) #endif -#define AGC_RECORRECT_EN ((BT_CTRL_AGC_RECORRECT_EN << 0) | (BT_CTRL_CODED_AGC_RECORRECT <<1)) +#define AGC_RECORRECT_EN ((BT_CTRL_AGC_RECORRECT_EN << 0) | (BT_CTRL_CODED_AGC_RECORRECT <<1) | (BT_CTRL_AGC_RECORRECT_NEW << 2)) #define CFG_MASK_BIT_SCAN_DUPLICATE_OPTION (1<<0) diff --git a/components/bt/include/esp32c6/include/esp_bt.h b/components/bt/include/esp32c6/include/esp_bt.h index 876754df6d4..210ead42da9 100644 --- a/components/bt/include/esp32c6/include/esp_bt.h +++ b/components/bt/include/esp32c6/include/esp_bt.h @@ -155,7 +155,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type */ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -#define CONFIG_VERSION 0x20230113 +#define CONFIG_VERSION 0x20231124 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -212,10 +212,11 @@ typedef struct { uint8_t cca_drop_mode; /*!< CCA drop mode */ int8_t cca_low_tx_pwr; /*!< CCA low transmit power */ uint8_t main_xtal_freq; /*!< Main crystal frequency */ - uint8_t version_num; /*!< Controller configuration version number */ + uint32_t version_num; /*!< Controller configuration version number */ uint8_t cpu_freq_mhz; /*!< CPU frequency in megahertz (MHz) */ uint8_t ignore_wl_for_direct_adv; /*!< Ignore the whitelist for direct advertising */ uint8_t enable_pcl; /*!< Enable power control */ + uint8_t csa2_select; /*!< Select CSA#2*/ uint32_t config_magic; /*!< Magic number for configuration validation */ } esp_bt_controller_config_t; @@ -270,6 +271,7 @@ typedef struct { .cpu_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, \ .ignore_wl_for_direct_adv = 0, \ .enable_pcl = DEFAULT_BT_LE_POWER_CONTROL_ENABLED, \ + .csa2_select = DEFAULT_BT_LE_50_FEATURE_SUPPORT, \ .config_magic = CONFIG_MAGIC, \ } diff --git a/components/bt/include/esp32h2/include/esp_bt.h b/components/bt/include/esp32h2/include/esp_bt.h index 75b9231b227..a1c7aed8ee2 100644 --- a/components/bt/include/esp32h2/include/esp_bt.h +++ b/components/bt/include/esp32h2/include/esp_bt.h @@ -160,7 +160,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type */ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -#define CONFIG_VERSION 0x20230113 +#define CONFIG_VERSION 0x20231124 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -220,6 +220,7 @@ typedef struct { uint8_t cpu_freq_mhz; /*!< CPU frequency in megahertz */ uint8_t ignore_wl_for_direct_adv; /*!< Ignore the white list for directed advertising */ uint8_t enable_pcl; /*!< Enable power control */ + uint8_t csa2_select; /*!< Select CSA#2*/ uint32_t config_magic; /*!< Configuration magic value */ } esp_bt_controller_config_t; @@ -274,6 +275,7 @@ typedef struct { .cpu_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, \ .ignore_wl_for_direct_adv = 0, \ .enable_pcl = 0, \ + .csa2_select = DEFAULT_BT_LE_50_FEATURE_SUPPORT, \ .config_magic = CONFIG_MAGIC, \ } diff --git a/components/bt/porting/nimble/include/nimble/hci_common.h b/components/bt/porting/nimble/include/nimble/hci_common.h index 76c8d49a5f7..4cda1c731c5 100644 --- a/components/bt/porting/nimble/include/nimble/hci_common.h +++ b/components/bt/porting/nimble/include/nimble/hci_common.h @@ -1149,10 +1149,14 @@ struct ble_hci_vs_duplicate_exception_list_cp { uint8_t device_info[6]; } __attribute__((packed)); -#if SOC_BLE_POWER_CONTROL_SUPPORTED && MYNEWT_VAL(BLE_HCI_VS) -#define BLE_HCI_OCF_VS_PCL_SET_RSSI (MYNEWT_VAL(BLE_HCI_VS_OCF_OFFSET) + (0x0111)) +#define BLE_HCI_OCF_VS_LEGACY_ADV_CLEAR (MYNEWT_VAL(BLE_HCI_VS_OCF_OFFSET) + (0x010C)) + +#if SOC_BLE_POWER_CONTROL_SUPPORTED +#define BLE_HCI_OCF_VS_PCL_SET_RSSI (MYNEWT_VAL(BLE_HCI_VS_OCF_OFFSET) + (0x0111)) #endif +#define BLE_HCI_OCF_VS_SET_CHAN_SELECT (MYNEWT_VAL(BLE_HCI_VS_OCF_OFFSET) + (0x0112)) + /* Command Specific Definitions */ /* --- Set controller to host flow control (OGF 0x03, OCF 0x0031) --- */ #define BLE_HCI_CTLR_TO_HOST_FC_OFF (0) diff --git a/components/bt/porting/npl/freertos/src/npl_os_freertos.c b/components/bt/porting/npl/freertos/src/npl_os_freertos.c index 6e53b823ac6..ebf89d3cdd5 100644 --- a/components/bt/porting/npl/freertos/src/npl_os_freertos.c +++ b/components/bt/porting/npl/freertos/src/npl_os_freertos.c @@ -133,6 +133,9 @@ npl_freertos_eventq_init(struct ble_npl_eventq *evq) memset(eventq, 0, sizeof(*eventq)); eventq->q = xQueueCreate(ble_freertos_total_event_cnt, sizeof(struct ble_npl_eventq *)); BLE_LL_ASSERT(eventq->q); + } else { + eventq = (struct ble_npl_eventq_freertos*)evq->eventq; + xQueueReset(eventq->q); } #else if(!evq->eventq) { @@ -142,6 +145,9 @@ npl_freertos_eventq_init(struct ble_npl_eventq *evq) memset(eventq, 0, sizeof(*eventq)); eventq->q = xQueueCreate(ble_freertos_total_event_cnt, sizeof(struct ble_npl_eventq *)); BLE_LL_ASSERT(eventq->q); + } else { + eventq = (struct ble_npl_eventq_freertos*)evq->eventq; + xQueueReset(eventq->q); } #endif } @@ -720,12 +726,12 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co) } #else xTimerDelete(callout->handle, portMAX_DELAY); +#endif // BLE_NPL_USE_ESP_TIMER #if OS_MEM_ALLOC os_memblock_put(&ble_freertos_co_pool,callout); #else free((void *)callout); #endif // OS_MEM_ALLOC -#endif // BLE_NPL_USE_ESP_TIMER co->co = NULL; memset(co, 0, sizeof(struct ble_npl_callout)); } diff --git a/components/bt/sdkconfig.rename b/components/bt/sdkconfig.rename index cdaf6d30143..55beeffcfd6 100644 --- a/components/bt/sdkconfig.rename +++ b/components/bt/sdkconfig.rename @@ -284,3 +284,6 @@ CONFIG_BT_NIMBLE_ACL_BUF_SIZE CONFIG_BT_NIMBLE_TRA CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE CONFIG_BT_NIMBLE_TRANSPORT_EVT_SIZE CONFIG_BT_NIMBLE_HCI_EVT_HI_BUF_COUNT CONFIG_BT_NIMBLE_TRANSPORT_EVT_COUNT CONFIG_BT_NIMBLE_HCI_EVT_LO_BUF_COUNT CONFIG_BT_NIMBLE_TRANSPORT_EVT_DISCARD_COUNT + +CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_EN CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN +CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS diff --git a/components/bt/sdkconfig.rename.esp32c3 b/components/bt/sdkconfig.rename.esp32c3 new file mode 100644 index 00000000000..38906e4cb40 --- /dev/null +++ b/components/bt/sdkconfig.rename.esp32c3 @@ -0,0 +1,5 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_EN CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EN +CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS diff --git a/components/bt/sdkconfig.rename.esp32s3 b/components/bt/sdkconfig.rename.esp32s3 new file mode 100644 index 00000000000..38906e4cb40 --- /dev/null +++ b/components/bt/sdkconfig.rename.esp32s3 @@ -0,0 +1,5 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_EN CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EN +CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS diff --git a/components/console/CMakeLists.txt b/components/console/CMakeLists.txt index 5904ac5ada5..f0aaabb3400 100644 --- a/components/console/CMakeLists.txt +++ b/components/console/CMakeLists.txt @@ -28,4 +28,6 @@ idf_component_register(SRCS "commands.c" ${argtable_srcs} INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR} REQUIRES vfs - PRIV_REQUIRES driver) + PRIV_REQUIRES esp_driver_uart + driver # to be replaced by esp_driver_usj + ) diff --git a/components/console/commands.c b/components/console/commands.c index 5e63db87b4c..800b57fac67 100644 --- a/components/console/commands.c +++ b/components/console/commands.c @@ -32,9 +32,11 @@ typedef struct cmd_item_ { * May be NULL. */ char *hint; - esp_console_cmd_func_t func; //!< pointer to the command handler - void *argtable; //!< optional pointer to arg table - SLIST_ENTRY(cmd_item_) next; //!< next command in the list + esp_console_cmd_func_t func; //!< pointer to the command handler (without user context) + esp_console_cmd_func_with_context_t func_w_context; //!< pointer to the command handler (with user context) + void *argtable; //!< optional pointer to arg table + void *context; //!< optional pointer to user context + SLIST_ENTRY(cmd_item_) next; //!< next command in the list } cmd_item_t; /** linked list of command structures */ @@ -97,6 +99,10 @@ esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd) if (strchr(cmd->command, ' ') != NULL) { return ESP_ERR_INVALID_ARG; } + if ((cmd->func == NULL && cmd->func_w_context == NULL) + || (cmd->func != NULL && cmd->func_w_context != NULL)) { + return ESP_ERR_INVALID_ARG; + } item = (cmd_item_t *)find_command_by_name(cmd->command); if (!item) { // not registered before @@ -130,19 +136,39 @@ esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd) } item->argtable = cmd->argtable; item->func = cmd->func; - cmd_item_t *last = SLIST_FIRST(&s_cmd_list); + item->func_w_context = cmd->func_w_context; + cmd_item_t *last = NULL; + cmd_item_t *it; + SLIST_FOREACH(it, &s_cmd_list, next) { + if (strcmp(it->command, item->command) > 0) { + break; + } + last = it; + } if (last == NULL) { SLIST_INSERT_HEAD(&s_cmd_list, item, next); } else { - cmd_item_t *it; - while ((it = SLIST_NEXT(last, next)) != NULL) { - last = it; - } SLIST_INSERT_AFTER(last, item, next); } return ESP_OK; } +esp_err_t esp_console_cmd_set_context(const char *cmd, void *context) +{ + if (cmd == NULL ) { + return ESP_ERR_INVALID_ARG; + } + + cmd_item_t *it; + SLIST_FOREACH(it, &s_cmd_list, next) { + if (strcmp(cmd, it->command) == 0) { + it->context = context; + return ESP_OK; + } + } + return ESP_ERR_NOT_FOUND; +} + void esp_console_get_completion(const char *buf, linenoiseCompletions *lc) { size_t len = strlen(buf); @@ -210,7 +236,12 @@ esp_err_t esp_console_run(const char *cmdline, int *cmd_ret) free(argv); return ESP_ERR_NOT_FOUND; } - *cmd_ret = (*cmd->func)(argc, argv); + if (cmd->func) { + *cmd_ret = (*cmd->func)(argc, argv); + } + if (cmd->func_w_context) { + *cmd_ret = (*cmd->func_w_context)(cmd->context, argc, argv); + } free(argv); return ESP_OK; } diff --git a/components/console/esp_console.h b/components/console/esp_console.h index 304dc423b1a..dff737ba003 100644 --- a/components/console/esp_console.h +++ b/components/console/esp_console.h @@ -13,6 +13,7 @@ extern "C" { #include "sdkconfig.h" #include "esp_heap_caps.h" #include "esp_err.h" +#include "freertos/FreeRTOS.h" // Forward declaration. Definition in linenoise/linenoise.h. typedef struct linenoiseCompletions linenoiseCompletions; @@ -50,6 +51,7 @@ typedef struct { const char *history_save_path; //!< file path used to save history commands, set to NULL won't save to file system uint32_t task_stack_size; //!< repl task stack size uint32_t task_priority; //!< repl task priority + BaseType_t task_core_id; //!< repl task affinity, i.e. which core the task is pinned to const char *prompt; //!< prompt (NULL represents default: "esp> ") size_t max_cmdline_length; //!< maximum length of a command line. If 0, default value will be used } esp_console_repl_config_t; @@ -64,6 +66,7 @@ typedef struct { .history_save_path = NULL, \ .task_stack_size = 4096, \ .task_priority = 2, \ + .task_core_id = tskNO_AFFINITY, \ .prompt = NULL, \ .max_cmdline_length = 0, \ } @@ -156,6 +159,15 @@ esp_err_t esp_console_deinit(void); */ typedef int (*esp_console_cmd_func_t)(int argc, char **argv); +/** + * @brief Console command main function, with context + * @param context a user context given at invocation + * @param argc number of arguments + * @param argv array with argc entries, each pointing to a zero-terminated string argument + * @return console command return code, 0 indicates "success" + */ +typedef int (*esp_console_cmd_func_with_context_t)(void *context, int argc, char **argv); + /** * @brief Console command description */ @@ -179,6 +191,7 @@ typedef struct { const char *hint; /** * Pointer to a function which implements the command. + * @note: Setting both \c func and \c func_w_context is not allowed. */ esp_console_cmd_func_t func; /** @@ -188,18 +201,44 @@ typedef struct { * Only used for the duration of esp_console_cmd_register call. */ void *argtable; + /** + * Pointer to a context aware function which implements the command. + * @note: Setting both \c func and \c func_w_context is not allowed. + */ + esp_console_cmd_func_with_context_t func_w_context; } esp_console_cmd_t; /** * @brief Register console command * @param cmd pointer to the command description; can point to a temporary value + * + * @note If the member func_w_context of cmd is set instead of func, then there + * MUST be a subsequent call to \c esp_console_cmd_set_context to initialize the + * function context before it is used! + * * @return * - ESP_OK on success * - ESP_ERR_NO_MEM if out of memory * - ESP_ERR_INVALID_ARG if command description includes invalid arguments + * - ESP_ERR_INVALID_ARG if both func and func_w_context members of cmd are non-NULL + * - ESP_ERR_INVALID_ARG if both func and func_w_context members of cmd are NULL */ esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd); +/** + * @brief Register context for a command registered with \c func_w_context before + * + * \c context is only used if \c func_w_context has been set in the structure + * passed to esp_console_cmd_register() + * @param cmd pointer to the command name + * @param context pointer to user-defined per-command context data + * @return + * - ESP_OK on success + * - ESP_ERR_NOT_FOUND if command was not found + * - ESP_ERR_INVALID_ARG if invalid arguments + */ +esp_err_t esp_console_cmd_set_context(const char *cmd, void *context); + /** * @brief Run command line * @param cmdline command line (command name followed by a number of arguments) diff --git a/components/console/esp_console_repl.c b/components/console/esp_console_repl.c index 123572d62f2..00d93242d38 100644 --- a/components/console/esp_console_repl.c +++ b/components/console/esp_console_repl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,6 +18,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "driver/uart.h" +#include "driver/uart_vfs.h" #include "driver/usb_serial_jtag.h" #include "linenoise/linenoise.h" @@ -106,8 +107,8 @@ esp_err_t esp_console_new_repl_usb_cdc(const esp_console_dev_usb_cdc_config_t *d cdc_repl->repl_com.repl_core.del = esp_console_repl_usb_cdc_delete; /* spawn a single thread to run REPL */ - if (xTaskCreate(esp_console_repl_task, "console_repl", repl_config->task_stack_size, - cdc_repl, repl_config->task_priority, &cdc_repl->repl_com.task_hdl) != pdTRUE) { + if (xTaskCreatePinnedToCore(esp_console_repl_task, "console_repl", repl_config->task_stack_size, + cdc_repl, repl_config->task_priority, &cdc_repl->repl_com.task_hdl, repl_config->task_core_id) != pdTRUE) { ret = ESP_FAIL; goto _exit; } @@ -183,8 +184,8 @@ esp_err_t esp_console_new_repl_usb_serial_jtag(const esp_console_dev_usb_serial_ usb_serial_jtag_repl->repl_com.repl_core.del = esp_console_repl_usb_serial_jtag_delete; /* spawn a single thread to run REPL */ - if (xTaskCreate(esp_console_repl_task, "console_repl", repl_config->task_stack_size, - usb_serial_jtag_repl, repl_config->task_priority, &usb_serial_jtag_repl->repl_com.task_hdl) != pdTRUE) { + if (xTaskCreatePinnedToCore(esp_console_repl_task, "console_repl", repl_config->task_stack_size, + usb_serial_jtag_repl, repl_config->task_priority, &usb_serial_jtag_repl->repl_com.task_hdl, repl_config->task_core_id) != pdTRUE) { ret = ESP_FAIL; goto _exit; } @@ -224,9 +225,9 @@ esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_con fsync(fileno(stdout)); /* Minicom, screen, idf_monitor send CR when ENTER key is pressed */ - esp_vfs_dev_uart_port_set_rx_line_endings(dev_config->channel, ESP_LINE_ENDINGS_CR); + uart_vfs_dev_port_set_rx_line_endings(dev_config->channel, ESP_LINE_ENDINGS_CR); /* Move the caret to the beginning of the next line on '\n' */ - esp_vfs_dev_uart_port_set_tx_line_endings(dev_config->channel, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_tx_line_endings(dev_config->channel, ESP_LINE_ENDINGS_CRLF); /* Configure UART. Note that REF_TICK/XTAL is used so that the baud rate remains * correct while APB frequency is changing in light sleep mode. @@ -261,7 +262,7 @@ esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_con } /* Tell VFS to use UART driver */ - esp_vfs_dev_uart_use_driver(dev_config->channel); + uart_vfs_dev_use_driver(dev_config->channel); // initialize console, common part ret = esp_console_common_init(repl_config->max_cmdline_length, &uart_repl->repl_com); @@ -285,8 +286,8 @@ esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_con /* Spawn a single thread to run REPL, we need to pass `uart_repl` to it as * it also requires the uart channel. */ - if (xTaskCreate(esp_console_repl_task, "console_repl", repl_config->task_stack_size, - uart_repl, repl_config->task_priority, &uart_repl->repl_com.task_hdl) != pdTRUE) { + if (xTaskCreatePinnedToCore(esp_console_repl_task, "console_repl", repl_config->task_stack_size, + uart_repl, repl_config->task_priority, &uart_repl->repl_com.task_hdl, repl_config->task_core_id) != pdTRUE) { ret = ESP_FAIL; goto _exit; } @@ -423,7 +424,7 @@ static esp_err_t esp_console_repl_uart_delete(esp_console_repl_t *repl) } repl_com->state = CONSOLE_REPL_STATE_DEINIT; esp_console_deinit(); - esp_vfs_dev_uart_use_nonblocking(uart_repl->uart_channel); + uart_vfs_dev_use_nonblocking(uart_repl->uart_channel); uart_driver_delete(uart_repl->uart_channel); free(uart_repl); _exit: diff --git a/components/console/test_apps/console/README.md b/components/console/test_apps/console/README.md index bf47d80ec64..1e72354679e 100644 --- a/components/console/test_apps/console/README.md +++ b/components/console/test_apps/console/README.md @@ -1,2 +1,8 @@ | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | + +Note: Most of the test cases shouldn't be run manually, but [pytest](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/contribute/esp-idf-tests-with-pytest.html) should be used instead. E.g., to run all test cases on ESP32 using pytest, use: + +``` +pytest --target esp32 -m generic +``` diff --git a/components/console/test_apps/console/main/test_console.c b/components/console/test_apps/console/main/test_console.c index db7685027a0..ef63ca683f7 100644 --- a/components/console/test_apps/console/main/test_console.c +++ b/components/console/test_apps/console/main/test_console.c @@ -13,12 +13,71 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" +/* + * NOTE: Most of these unit tests DO NOT work standalone. They require pytest to control + * the application and check for correct output. + * E.g., to run the test "esp console help command - reverse registration", type: + * pytest --target esp32 -m "generic" -k test_console_help_reverse_registration + * The pytest test cases are different than the unit test cases here, they can be found + * in the pytest_*.py file in the root directory of this test project. + * For more information on pytest, please refer to + * https://docs.espressif.com/projects/esp-idf/en/latest/esp32/contribute/esp-idf-tests-with-pytest.html. + */ + +typedef struct { + const char *in; + const char *out; +} cmd_context_t; + +static int do_hello_cmd_with_context(void *context, int argc, char **argv) +{ + cmd_context_t *cmd_context = (cmd_context_t *)context; + cmd_context->out = cmd_context->in; + return 0; +} + static int do_hello_cmd(int argc, char **argv) { printf("Hello World\n"); return 0; } +static int do_not_call(void* context, int argc, char **argv) +{ + TEST_ASSERT_MESSAGE(false, "This function is a dummy and must not be called\n"); + return 0; +} + +TEST_CASE("esp console register with normal and context aware functions set fails", "[console]") +{ + esp_console_config_t console_config = ESP_CONSOLE_CONFIG_DEFAULT(); + TEST_ESP_OK(esp_console_init(&console_config)); + const esp_console_cmd_t cmd = { + .command = "valid_cmd", + .help = "Command which is valid", + .hint = NULL, + .func = do_hello_cmd, + .func_w_context = do_not_call, + }; + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_console_cmd_register(&cmd)); + TEST_ESP_OK(esp_console_deinit()); +} + +TEST_CASE("esp console register with normal and context aware function set to NULL fails", "[console]") +{ + esp_console_config_t console_config = ESP_CONSOLE_CONFIG_DEFAULT(); + TEST_ESP_OK(esp_console_init(&console_config)); + const esp_console_cmd_t cmd = { + .command = "valid_cmd", + .help = "Command which is valid", + .hint = NULL, + .func = do_hello_cmd, + .func_w_context = do_not_call, + }; + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_console_cmd_register(&cmd)); + TEST_ESP_OK(esp_console_deinit()); +} + TEST_CASE("esp console init/deinit test", "[console]") { esp_console_config_t console_config = ESP_CONSOLE_CONFIG_DEFAULT(); @@ -69,7 +128,20 @@ TEST_CASE("esp console repl test", "[console][ignore]") vTaskDelay(pdMS_TO_TICKS(2000)); } -TEST_CASE("esp console help command", "[console][ignore]") +static const esp_console_cmd_t cmd_a = { + .command = "aaa", + .help = "should appear first in help", + .hint = NULL, + .func = do_hello_cmd, +}; +static const esp_console_cmd_t cmd_z = { + .command = "zzz", + .help = "should appear last in help", + .hint = NULL, + .func = do_hello_cmd, +}; + +TEST_CASE("esp console help command - sorted registration", "[console][ignore]") { esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); @@ -77,6 +149,27 @@ TEST_CASE("esp console help command", "[console][ignore]") TEST_ESP_OK(esp_console_cmd_register(&s_quit_cmd)); TEST_ESP_OK(esp_console_register_help_command()); + TEST_ESP_OK(esp_console_cmd_register(&cmd_a)); + TEST_ESP_OK(esp_console_cmd_register(&cmd_z)); + + TEST_ESP_OK(esp_console_start_repl(s_repl)); + vTaskDelay(pdMS_TO_TICKS(5000)); +} + +/** + * The commands in the 'help'-command's output should be alphabetically sorted, + * regardless of their registration order. + */ +TEST_CASE("esp console help command - reverse registration", "[console][ignore]") +{ + esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); + TEST_ESP_OK(esp_console_new_repl_uart(&uart_config, &repl_config, &s_repl)); + + TEST_ESP_OK(esp_console_cmd_register(&cmd_z)); + TEST_ESP_OK(esp_console_cmd_register(&cmd_a)); + TEST_ESP_OK(esp_console_register_help_command()); + TEST_ESP_OK(esp_console_cmd_register(&s_quit_cmd)); TEST_ESP_OK(esp_console_start_repl(s_repl)); vTaskDelay(pdMS_TO_TICKS(5000)); @@ -102,3 +195,71 @@ TEST_CASE("esp console init/deinit test, minimal config", "[console]") TEST_ESP_OK(esp_console_cmd_register(&cmd)); TEST_ESP_OK(esp_console_deinit()); } + +TEST_CASE("esp console test set_context", "[console]") +{ + /* Test with minimal init config */ + esp_console_config_t console_config = { + .max_cmdline_args = 2, + .max_cmdline_length = 100, + }; + + TEST_ESP_OK(esp_console_init(&console_config)); + + TEST_ASSERT_EQUAL(esp_console_cmd_set_context(NULL, NULL), ESP_ERR_INVALID_ARG); + TEST_ASSERT_EQUAL(esp_console_cmd_set_context("invalid", NULL), ESP_ERR_NOT_FOUND); + + TEST_ESP_OK(esp_console_deinit()); +} + +TEST_CASE("esp console test with context", "[console]") +{ + /* Test with minimal init config */ + esp_console_config_t console_config = { + .max_cmdline_args = 2, + .max_cmdline_length = 100, + }; + + TEST_ESP_OK(esp_console_init(&console_config)); + + const esp_console_cmd_t cmds[] = { + { + .command = "hello-c1", + .help = "Print Hello World in context c1", + .hint = NULL, + .func_w_context = do_hello_cmd_with_context, + }, + { + .command = "hello-c2", + .help = "Print Hello World in context c2", + .hint = NULL, + .func_w_context = do_hello_cmd_with_context, + }, + }; + cmd_context_t contexts[] = { + { + .in = "c1", + .out = NULL, + }, + { + .in = "c2", + .out = NULL, + }, + }; + + static_assert((sizeof(contexts) / sizeof(contexts[0])) == (sizeof(cmds) / sizeof(cmds[0]))); + + for (int i=0; i < sizeof(cmds) / sizeof(cmds[0]); i++) { + TEST_ESP_OK(esp_console_cmd_register(&cmds[i])); + TEST_ESP_OK(esp_console_cmd_set_context(cmds[i].command, &contexts[i])); + } + + for (int i=0; i < sizeof(cmds) / sizeof(cmds[0]); i++) { + int ret; + TEST_ESP_OK(esp_console_run(cmds[i].command, &ret)); + TEST_ASSERT_EQUAL(ret, 0); + TEST_ASSERT_EQUAL(contexts[i].in, contexts[i].out); + } + + TEST_ESP_OK(esp_console_deinit()); +} diff --git a/components/console/test_apps/console/pytest_console.py b/components/console/test_apps/console/pytest_console.py index 0dfdd13526f..1cbaffea2ab 100644 --- a/components/console/test_apps/console/pytest_console.py +++ b/components/console/test_apps/console/pytest_console.py @@ -15,27 +15,34 @@ def do_test_quit(dut: Dut) -> None: dut.expect_exact('ByeBye', timeout=5) -def do_test_help_generic(dut: Dut) -> None: +def do_test_help_generic(dut: Dut, registration_order: str) -> None: dut.expect_exact('Press ENTER to see the list of tests') - dut.write('"esp console help command"') + dut.write('"esp console help command - {} registration"'.format(registration_order)) dut.expect_exact('esp>', timeout=5) dut.write('help') - dut.expect_exact('quit', timeout=5) - dut.expect_exact('Quit REPL environment', timeout=5) + dut.expect_exact('aaa', timeout=5) + dut.expect_exact('should appear first in help', timeout=5) dut.expect(r'help\s+\[\]', timeout=5) # Note: repl seems to do the line breaks by itself, this needs to be adjusted if repl changes its line width dut.expect_exact('Print the summary of all registered commands if no arguments are given,', timeout=5) dut.expect_exact('otherwise print summary of given command.', timeout=5) - dut.expect(r'\s+Name of command\s+esp>', timeout=5) + dut.expect(r'\s+Name of command', timeout=5) + + dut.expect_exact('quit', timeout=5) + dut.expect_exact('Quit REPL environment', timeout=5) + + dut.expect_exact('zzz', timeout=5) + dut.expect_exact('should appear last in help', timeout=5) + dut.expect_exact('esp>', timeout=5) def do_test_help_quit(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') - dut.write('"esp console help command"') + dut.write('"esp console help command - sorted registration"') dut.expect_exact('esp>', timeout=5) dut.write('help quit') @@ -43,54 +50,51 @@ def do_test_help_quit(dut: Dut) -> None: dut.expect(r'quit\s+Quit REPL environment\s+esp>', timeout=5) -@pytest.mark.generic -@pytest.mark.supported_targets -def test_console(dut: Dut) -> None: - dut.run_all_single_board_cases() - - -@pytest.mark.generic -@pytest.mark.supported_targets -def test_console_repl(dut: Dut) -> None: - do_test_quit(dut) - - -@pytest.mark.generic -@pytest.mark.supported_targets -def test_console_help_generic(dut: Dut) -> None: - do_test_help_generic(dut) - - -@pytest.mark.generic -@pytest.mark.supported_targets -def test_console_help_quit(dut: Dut) -> None: - do_test_help_quit(dut) - - -@pytest.mark.host_test -@pytest.mark.qemu -@pytest.mark.esp32 -@pytest.mark.esp32c3 -def test_console_qemu(dut: Dut) -> None: +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('target', marks=[pytest.mark.supported_targets, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console(dut: Dut, test_on: str) -> None: dut.run_all_single_board_cases() -@pytest.mark.host_test -@pytest.mark.qemu -@pytest.mark.esp32 -def test_console_repl_qemu(dut: Dut) -> None: +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('target', marks=[pytest.mark.supported_targets, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console_repl(dut: Dut, test_on: str) -> None: do_test_quit(dut) -@pytest.mark.host_test -@pytest.mark.qemu -@pytest.mark.esp32 -def test_console_help_generic_qemu(dut: Dut) -> None: - do_test_help_generic(dut) - - -@pytest.mark.host_test -@pytest.mark.qemu -@pytest.mark.esp32 -def test_console_help_quit_qemu(dut: Dut) -> None: +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('target', marks=[pytest.mark.supported_targets, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console_help_sorted_registration(dut: Dut, test_on: str) -> None: + do_test_help_generic(dut, 'sorted') + + +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('target', marks=[pytest.mark.supported_targets, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console_help_reverse_registration(dut: Dut, test_on: str) -> None: + do_test_help_generic(dut, 'reverse') + + +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('target', marks=[pytest.mark.supported_targets, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console_help_quit(dut: Dut, test_on: str) -> None: do_test_help_quit(dut) diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index e575db47742..3c7d4c2fc0a 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -5,32 +5,19 @@ if(${target} STREQUAL "linux") endif() # Always compiled source files -set(srcs - "spi/spi_bus_lock.c") +set(srcs) # Always included headers -set(includes "include" - "deprecated" - "analog_comparator/include" - "dac/include" +set(includes "deprecated" "i2c/include" - "i2s/include" "ledc/include" - "mcpwm/include" "parlio/include" - "rmt/include" - "sdio_slave/include" - "sdmmc/include" - "sigma_delta/include" - "spi/include" - "temperature_sensor/include" "touch_sensor/include" "twai/include" - "uart/include" "usb_serial_jtag/include") # Always included linker fragments -set(ldfragments "linker.lf") +set(ldfragments "") # ADC related source files (dprecated) if(CONFIG_SOC_ADC_SUPPORTED) @@ -41,22 +28,9 @@ if(CONFIG_SOC_ADC_DMA_SUPPORTED) list(APPEND srcs "deprecated/adc_dma_legacy.c") endif() -# Analog comparator related source files -if(CONFIG_SOC_ANA_CMPR_SUPPORTED) - list(APPEND srcs "analog_comparator/ana_cmpr.c") - if(CONFIG_SOC_ANA_CMPR_SUPPORT_ETM) - list(APPEND srcs "analog_comparator/ana_cmpr_etm.c") - endif() -endif() - # DAC related source files if(CONFIG_SOC_DAC_SUPPORTED) - list(APPEND srcs "dac/dac_oneshot.c" - "dac/dac_cosine.c" - "dac/dac_continuous.c" - "dac/dac_common.c" - "dac/${target}/dac_dma.c" - "deprecated/dac_common_legacy.c" + list(APPEND srcs "deprecated/dac_common_legacy.c" "deprecated/${target}/dac_legacy.c") endif() @@ -72,29 +46,12 @@ endif() # I2C related source files if(CONFIG_SOC_I2C_SUPPORTED) - list(APPEND srcs "i2c/i2c.c" - "i2c/i2c_master.c" - "i2c/i2c_common.c" - ) - if(CONFIG_SOC_I2C_SUPPORT_SLAVE) - list(APPEND srcs "i2c/i2c_slave.c") - endif() - - list(APPEND ldfragments "i2c/linker.lf") + list(APPEND srcs "i2c/i2c.c") endif() # I2S related source files if(CONFIG_SOC_I2S_SUPPORTED) - list(APPEND srcs "i2s/i2s_common.c" - "i2s/i2s_platform.c" - "i2s/i2s_std.c" - "deprecated/i2s_legacy.c") - if(CONFIG_SOC_I2S_SUPPORTS_PDM) - list(APPEND srcs "i2s/i2s_pdm.c") - endif() - if(CONFIG_SOC_I2S_SUPPORTS_TDM) - list(APPEND srcs "i2s/i2s_tdm.c") - endif() + list(APPEND srcs "deprecated/i2s_legacy.c") endif() # LEDC related source files @@ -104,21 +61,9 @@ if(CONFIG_SOC_LEDC_SUPPORTED) list(APPEND ldfragments "ledc/linker.lf") endif() -# MCPWM related source files +# MCPWM legacy driver if(CONFIG_SOC_MCPWM_SUPPORTED) - list(APPEND srcs "mcpwm/mcpwm_cap.c" - "mcpwm/mcpwm_cmpr.c" - "mcpwm/mcpwm_com.c" - "mcpwm/mcpwm_fault.c" - "mcpwm/mcpwm_gen.c" - "mcpwm/mcpwm_oper.c" - "mcpwm/mcpwm_sync.c" - "mcpwm/mcpwm_timer.c" - "deprecated/mcpwm_legacy.c") - if(CONFIG_SOC_MCPWM_SUPPORT_ETM) - list(APPEND srcs "mcpwm/mcpwm_etm.c") - endif() - list(APPEND ldfragments "mcpwm/linker.lf") + list(APPEND srcs "deprecated/mcpwm_legacy.c") endif() # PCNT legacy driver @@ -126,51 +71,19 @@ if(CONFIG_SOC_PCNT_SUPPORTED) list(APPEND srcs "deprecated/pcnt_legacy.c") endif() -# RMT related source files +# RMT legacy driver if(CONFIG_SOC_RMT_SUPPORTED) - list(APPEND srcs "rmt/rmt_common.c" - "rmt/rmt_encoder.c" - "rmt/rmt_rx.c" - "rmt/rmt_tx.c" - "deprecated/rmt_legacy.c") - list(APPEND ldfragments "rmt/linker.lf") -endif() - -# SDIO Slave related source files -if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED) - list(APPEND srcs "sdio_slave/sdio_slave.c") -endif() - -# SDMMC related source files -if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) - list(APPEND srcs "sdmmc/sdmmc_transaction.c" - "sdmmc/sdmmc_host.c") + list(APPEND srcs "deprecated/rmt_legacy.c") endif() -# Sigma-Delta Modulation related source files +# Sigma-Delta Modulation legacy driver if(CONFIG_SOC_SDM_SUPPORTED) - list(APPEND srcs "sigma_delta/sdm.c" - "deprecated/sigma_delta_legacy.c") -endif() - -# SPI related source files -if(CONFIG_SOC_GPSPI_SUPPORTED) - list(APPEND srcs "spi/gpspi/spi_common.c" - "spi/gpspi/spi_master.c" - "spi/gpspi/spi_slave.c" - "spi/sdspi/sdspi_crc.c" - "spi/sdspi/sdspi_host.c" - "spi/sdspi/sdspi_transaction.c") -endif() - -if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2) - list(APPEND srcs "spi/gpspi/spi_slave_hd.c") + list(APPEND srcs "deprecated/sigma_delta_legacy.c") endif() # Temperature Sensor related source files if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED) - list(APPEND srcs "temperature_sensor/temperature_sensor.c" - "deprecated/rtc_temperature_legacy.c") + list(APPEND srcs "deprecated/rtc_temperature_legacy.c") endif() # Touch Sensor related source files @@ -187,13 +100,6 @@ if(CONFIG_SOC_TWAI_SUPPORTED) list(APPEND ldfragments "twai/linker.lf") endif() -# UART related source files -if(CONFIG_SOC_UART_SUPPORTED) - list(APPEND srcs "uart/uart.c") - - list(APPEND ldfragments "uart/linker.lf") -endif() - # USB Serial JTAG related source files if(CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED) list(APPEND srcs "usb_serial_jtag/usb_serial_jtag.c" @@ -218,7 +124,10 @@ else() REQUIRES esp_pm esp_ringbuf freertos soc hal esp_hw_support # for backward compatibility, the driver component needs to # have a public dependency on other "esp_driver_foo" components - esp_driver_gpio esp_driver_pcnt esp_driver_gptimer + esp_driver_gpio esp_driver_pcnt esp_driver_gptimer esp_driver_spi esp_driver_mcpwm + esp_driver_ana_cmpr esp_driver_i2s esp_driver_sdmmc esp_driver_sdspi esp_driver_sdio + esp_driver_dac esp_driver_rmt esp_driver_tsens esp_driver_sdm esp_driver_i2c + esp_driver_uart LDFRAGMENTS ${ldfragments} ) endif() diff --git a/components/driver/Kconfig b/components/driver/Kconfig index 9b0729bb8d0..01d8babbd8e 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -62,224 +62,8 @@ menu "Driver Configurations" endmenu # ADC Configuration - menu "SPI Configuration" - - config SPI_MASTER_IN_IRAM - bool "Place transmitting functions of SPI master into IRAM" - default n - depends on !FREERTOS_PLACE_FUNCTIONS_INTO_FLASH - select SPI_MASTER_ISR_IN_IRAM - help - Normally only the ISR of SPI master is placed in the IRAM, so that it - can work without the flash when interrupt is triggered. - For other functions, there's some possibility that the flash cache - miss when running inside and out of SPI functions, which may increase - the interval of SPI transactions. - Enable this to put ``queue_trans``, ``get_trans_result`` and - ``transmit`` functions into the IRAM to avoid possible cache miss. - - This configuration won't be available if `CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH` is enabled. - - During unit test, this is enabled to measure the ideal case of api. - - config SPI_MASTER_ISR_IN_IRAM - bool "Place SPI master ISR function into IRAM" - default y - depends on !HEAP_PLACE_FUNCTION_INTO_FLASH - select PERIPH_CTRL_FUNC_IN_IRAM - select HAL_SPI_MASTER_FUNC_IN_IRAM - help - Place the SPI master ISR in to IRAM to avoid possible cache miss. - - Enabling this configuration is possible only when HEAP_PLACE_FUNCTION_INTO_FLASH - is disabled since the spi master uses can allocate transactions buffers into DMA - memory section using the heap component API that ipso facto has to be placed in IRAM. - - Also you can forbid the ISR being disabled during flash writing - access, by add ESP_INTR_FLAG_IRAM when initializing the driver. - - config SPI_SLAVE_IN_IRAM - bool "Place transmitting functions of SPI slave into IRAM" - default n - select SPI_SLAVE_ISR_IN_IRAM - help - Normally only the ISR of SPI slave is placed in the IRAM, so that it - can work without the flash when interrupt is triggered. - For other functions, there's some possibility that the flash cache - miss when running inside and out of SPI functions, which may increase - the interval of SPI transactions. - Enable this to put ``queue_trans``, ``get_trans_result`` and - ``transmit`` functions into the IRAM to avoid possible cache miss. - - config SPI_SLAVE_ISR_IN_IRAM - bool "Place SPI slave ISR function into IRAM" - default y - select PERIPH_CTRL_FUNC_IN_IRAM - select HAL_SPI_SLAVE_FUNC_IN_IRAM - help - Place the SPI slave ISR in to IRAM to avoid possible cache miss. - - Also you can forbid the ISR being disabled during flash writing - access, by add ESP_INTR_FLAG_IRAM when initializing the driver. - - endmenu # SPI Configuration - orsource "./twai/Kconfig.twai" - menu "Temperature sensor Configuration" - depends on SOC_TEMP_SENSOR_SUPPORTED - - config TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN - bool "Suppress legacy driver deprecated warning" - default n - help - Wether to suppress the deprecation warnings when using legacy temperature sensor driver - (driver/temp_sensor.h). If you want to continue using the legacy driver, - and don't want to see related deprecation warnings, you can enable this option. - - config TEMP_SENSOR_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - Wether to enable the debug log message for temperature sensor driver. - Note that, this option only controls the temperature sensor driver log, won't affect other drivers. - - config TEMP_SENSOR_ISR_IRAM_SAFE - depends on SOC_TEMPERATURE_SENSOR_INTR_SUPPORT - bool "Temperature sensor ISR IRAM-Safe" - default n - help - Ensure the Temperature Sensor interrupt is IRAM-Safe by allowing the interrupt handler to be - executable when the cache is disabled (e.g. SPI Flash write). - - endmenu # TEMP_SENSOR Configuration - - orsource "./uart/Kconfig.uart" - - menu "Sigma Delta Modulator Configuration" - depends on SOC_SDM_SUPPORTED - config SDM_CTRL_FUNC_IN_IRAM - bool "Place SDM control functions into IRAM" - default n - help - Place SDM control functions (like set_duty) into IRAM, - so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. - Enabling this option can improve driver performance as well. - - config SDM_SUPPRESS_DEPRECATE_WARN - bool "Suppress legacy driver deprecated warning" - default n - help - Wether to suppress the deprecation warnings when using legacy sigma delta driver. - If you want to continue using the legacy driver, and don't want to see related deprecation warnings, - you can enable this option. - - config SDM_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - Wether to enable the debug log message for SDM driver. - Note that, this option only controls the SDM driver log, won't affect other drivers. - endmenu # Sigma Delta Modulator Configuration - - menu "Analog Comparator Configuration" - depends on SOC_ANA_CMPR_SUPPORTED - config ANA_CMPR_ISR_IRAM_SAFE - bool "Analog comparator ISR IRAM-Safe" - default n - help - Ensure the Analog Comparator interrupt is IRAM-Safe by allowing the interrupt handler to be - executable when the cache is disabled (e.g. SPI Flash write). - - config ANA_CMPR_CTRL_FUNC_IN_IRAM - bool "Place Analog Comparator control functions into IRAM" - default n - help - Place Analog Comparator control functions (like ana_cmpr_set_internal_reference) into IRAM, - so that these functions can be IRAM-safe and able to be called in an IRAM interrupt context. - Enabling this option can improve driver performance as well. - - config ANA_CMPR_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - Wether to enable the debug log message for Analog Comparator driver. - Note that, this option only controls the Analog Comparator driver log, won't affect other drivers. - endmenu # Analog Comparator Configuration - - orsource "./rmt/Kconfig.rmt" - - orsource "./mcpwm/Kconfig.mcpwm" - - menu "I2S Configuration" - depends on SOC_I2S_SUPPORTED - config I2S_ISR_IRAM_SAFE - bool "I2S ISR IRAM-Safe" - default n - help - Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be - executable when the cache is disabled (e.g. SPI Flash write). - - config I2S_SUPPRESS_DEPRECATE_WARN - bool "Suppress leagcy driver deprecated warning" - default n - help - Enable this option will suppress the deprecation warnings of using APIs in legacy I2S driver. - - config I2S_ENABLE_DEBUG_LOG - bool "Enable I2S debug log" - default n - help - Wether to enable the debug log message for I2S driver. - Note that, this option only controls the I2S driver log, will not affect other drivers. - endmenu # I2S Configuration - - menu "DAC Configuration" - depends on SOC_DAC_SUPPORTED - config DAC_CTRL_FUNC_IN_IRAM - bool "Place DAC control functions into IRAM" - default n - help - Place DAC control functions (e.g. 'dac_oneshot_output_voltage') into IRAM, - so that this function can be IRAM-safe and able to be called in the other IRAM interrupt context. - Enabling this option can improve driver performance as well. - - config DAC_ISR_IRAM_SAFE - bool "DAC ISR IRAM-Safe" - default n - help - Ensure the DAC interrupt is IRAM-Safe by allowing the interrupt handler to be - executable when the cache is disabled (e.g. SPI Flash write). - - config DAC_SUPPRESS_DEPRECATE_WARN - bool "Suppress legacy driver deprecated warning" - default n - help - Wether to suppress the deprecation warnings when using legacy DAC driver (driver/dac.h). - If you want to continue using the legacy driver, and don't want to see related deprecation warnings, - you can enable this option. - - config DAC_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - Wether to enable the debug log message for DAC driver. - Note that, this option only controls the DAC driver log, won't affect other drivers. - - config DAC_DMA_AUTO_16BIT_ALIGN - bool "Align the continuous data to 16 bit automatically" - depends on SOC_DAC_DMA_16BIT_ALIGN - default y - help - Whether to left shift the continuous data to align every bytes to 16 bits in the driver. - On ESP32, although the DAC resolution is only 8 bits, - the hardware requires 16 bits data in continuous mode. - By enabling this option, the driver will left shift 8 bits for the input data automatically. - Only disable this option when you decide to do this step by yourself. - Note that the driver will allocate a new piece of memory to save the converted data. - - endmenu # DAC Configuration - menu "USB Serial/JTAG Configuration" depends on SOC_USB_SERIAL_JTAG_SUPPORTED config USJ_NO_AUTO_LS_ON_CONNECTION @@ -319,24 +103,4 @@ menu "Driver Configurations" orsource "./ledc/Kconfig.ledc" - menu "I2C Configuration" - config I2C_ISR_IRAM_SAFE - bool "I2C ISR IRAM-Safe" - default n - help - Ensure the I2C interrupt is IRAM-Safe by allowing the interrupt handler to be - executable when the cache is disabled (e.g. SPI Flash write). - note: This cannot be used in the I2C legacy driver. - - config I2C_ENABLE_DEBUG_LOG - bool "Enable I2C debug log" - default n - help - Wether to enable the debug log message for I2C driver. - Note that this option only controls the I2C driver log, will not affect other drivers. - - note: This cannot be used in the I2C legacy driver. - - endmenu # I2C Configurations - endmenu # Driver configurations diff --git a/components/driver/deprecated/adc_dma_legacy.c b/components/driver/deprecated/adc_dma_legacy.c index 170a0b85ad9..846276c17fb 100644 --- a/components/driver/deprecated/adc_dma_legacy.c +++ b/components/driver/deprecated/adc_dma_legacy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -67,6 +67,7 @@ typedef struct adc_digi_context_t { gdma_channel_handle_t rx_dma_channel; //dma rx channel handle #elif CONFIG_IDF_TARGET_ESP32S2 spi_host_device_t spi_host; //ADC uses this SPI DMA + spi_dma_ctx_t *spi_dma_ctx; //spi_dma context intr_handle_t intr_hdl; //Interrupt handler #elif CONFIG_IDF_TARGET_ESP32 i2s_port_t i2s_host; //ADC uses this I2S DMA @@ -167,7 +168,7 @@ esp_err_t adc_digi_deinitialize(void) gdma_del_channel(s_adc_digi_ctx->rx_dma_channel); #elif CONFIG_IDF_TARGET_ESP32S2 esp_intr_free(s_adc_digi_ctx->intr_hdl); - spicommon_dma_chan_free(s_adc_digi_ctx->spi_host); + spicommon_dma_chan_free(s_adc_digi_ctx->spi_dma_ctx); spicommon_periph_free(s_adc_digi_ctx->spi_host); #elif CONFIG_IDF_TARGET_ESP32 esp_intr_free(s_adc_digi_ctx->intr_hdl); @@ -274,13 +275,14 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config) uint32_t dma_chan = 0; spi_success = spicommon_periph_claim(SPI3_HOST, "adc"); - ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &dma_chan, &dma_chan); + ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &s_adc_digi_ctx->spi_dma_ctx); if (ret == ESP_OK) { s_adc_digi_ctx->spi_host = SPI3_HOST; } if (!spi_success || (s_adc_digi_ctx->spi_host != SPI3_HOST)) { goto cleanup; } + dma_chan = s_adc_digi_ctx->spi_dma_ctx->rx_dma_chan.chan_id; ret = esp_intr_alloc(spicommon_irqdma_source_for_host(s_adc_digi_ctx->spi_host), 0, adc_dma_intr_handler, (void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl); @@ -396,6 +398,8 @@ esp_err_t adc_digi_start(void) ESP_LOGE(ADC_TAG, "The driver is already started"); return ESP_ERR_INVALID_STATE; } + //reset ADC digital part to reset ADC sampling EOF counter + periph_module_reset(PERIPH_SARADC_MODULE); sar_periph_ctrl_adc_continuous_power_acquire(); //reset flags s_adc_digi_ctx->ringbuf_overflow_flag = 0; diff --git a/components/driver/deprecated/i2s_legacy.c b/components/driver/deprecated/i2s_legacy.c index bfbb850b565..172b750c0db 100644 --- a/components/driver/deprecated/i2s_legacy.c +++ b/components/driver/deprecated/i2s_legacy.c @@ -885,6 +885,7 @@ static void i2s_adc_set_slot_legacy(void) i2s_ll_rx_set_ws_width(dev, slot_cfg->slot_bit_width); i2s_ll_rx_enable_msb_right(dev, false); i2s_ll_rx_enable_right_first(dev, false); + i2s_ll_rx_select_std_slot(dev, I2S_STD_SLOT_LEFT, false); /* Should always enable fifo */ i2s_ll_rx_force_enable_fifo_mod(dev, true); } @@ -1473,15 +1474,14 @@ static esp_err_t i2s_init_legacy(i2s_port_t i2s_num, int intr_alloc_flag) if (p_i2s[i2s_num]->dir & I2S_DIR_RX) { sar_periph_ctrl_adc_continuous_power_acquire(); adc_set_i2s_data_source(ADC_I2S_DATA_SRC_ADC); - i2s_ll_enable_builtin_adc(p_i2s[i2s_num]->hal.dev, true); + i2s_ll_enable_builtin_adc_dac(p_i2s[i2s_num]->hal.dev, true); } if (p_i2s[i2s_num]->dir & I2S_DIR_TX) { - i2s_ll_enable_builtin_dac(p_i2s[i2s_num]->hal.dev, true); + i2s_ll_enable_builtin_adc_dac(p_i2s[i2s_num]->hal.dev, true); } } else { adc_set_i2s_data_source(ADC_I2S_DATA_SRC_IO_SIG); - i2s_ll_enable_builtin_adc(p_i2s[i2s_num]->hal.dev, false); - i2s_ll_enable_builtin_dac(p_i2s[i2s_num]->hal.dev, false); + i2s_ll_enable_builtin_adc_dac(p_i2s[i2s_num]->hal.dev, false); } #endif diff --git a/components/driver/linker.lf b/components/driver/linker.lf deleted file mode 100644 index 6c90eff1f4c..00000000000 --- a/components/driver/linker.lf +++ /dev/null @@ -1,12 +0,0 @@ -[mapping:driver] -archive: libdriver.a -entries: - if SDM_CTRL_FUNC_IN_IRAM = y: - sdm: sdm_channel_set_pulse_density (noflash) - if ANA_CMPR_CTRL_FUNC_IN_IRAM = y: - ana_cmpr: ana_cmpr_set_internal_reference (noflash) - ana_cmpr: ana_cmpr_set_debounce (noflash) - ana_cmpr: ana_cmpr_set_cross_type (noflash) - if DAC_CTRL_FUNC_IN_IRAM = y: - dac_oneshot: dac_oneshot_output_voltage (noflash) - dac_continuous: dac_continuous_write_asynchronously (noflash) diff --git a/components/driver/spi/sdspi/sdspi_crc.c b/components/driver/spi/sdspi/sdspi_crc.c deleted file mode 100644 index 98b65c09f44..00000000000 --- a/components/driver/spi/sdspi/sdspi_crc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdspi_crc.h" -#include "sdkconfig.h" -#include "esp_rom_crc.h" - -static const uint8_t crc7_table[256] = -{ - 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, - 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, - 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, - 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, - 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, - 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, - 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, - 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, - 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, - 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, - 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, - 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, - 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, - 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, - 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, - 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79, -}; - -// returns the CRC-7 for a message of "length" bytes -uint8_t sdspi_crc7(const uint8_t *data, size_t size) -{ - uint8_t result = 0; - for (size_t i = 0; i < size; ++i) { - result = crc7_table[(result << 1) ^ data[i]]; - } - return result; -} - -/// Return CRC16 of data, in the on-the-wire format used by SD protocol -uint16_t sdspi_crc16(const uint8_t* data, size_t size) -{ - return __builtin_bswap16(esp_rom_crc16_be(UINT16_MAX, data, size) ^ UINT16_MAX); -} diff --git a/components/driver/test_apps/.build-test-rules.yml b/components/driver/test_apps/.build-test-rules.yml index 9fb560fa289..735ddbaa996 100644 --- a/components/driver/test_apps/.build-test-rules.yml +++ b/components/driver/test_apps/.build-test-rules.yml @@ -1,49 +1,10 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps -components/driver/test_apps/analog_comparator: - disable: - - if: SOC_ANA_CMPR_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: not supported yet - -components/driver/test_apps/dac_test_apps/dac: - disable: - - if: SOC_DAC_SUPPORTED != 1 - components/driver/test_apps/dac_test_apps/legacy_dac_driver: disable: - if: SOC_DAC_SUPPORTED != 1 - -components/driver/test_apps/i2c_test_apps: - disable: - - if: SOC_I2C_SUPPORTED != 1 # TODO: IDF-8070 - -components/driver/test_apps/i2s_test_apps: - disable: - - if: SOC_I2S_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runners - -components/driver/test_apps/i2s_test_apps/i2s: - disable: - - if: SOC_I2S_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runners - -components/driver/test_apps/i2s_test_apps/i2s_multi_dev: - disable: - - if: SOC_I2S_SUPPORTED != 1 - - if: SOC_I2S_HW_VERSION_2 != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runners + depends_components: + - esp_adc components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac: disable: @@ -66,22 +27,30 @@ components/driver/test_apps/legacy_adc_driver: - if: SOC_ADC_SUPPORTED != 1 components/driver/test_apps/legacy_i2c_driver: - disable: + disable_test: - if: IDF_TARGET == "esp32p4" temporary: true - reason: not supported yet # TODO: IDF-8070 + reason: lack of runner + depends_filepatterns: + - components/driver/i2c/** components/driver/test_apps/legacy_mcpwm_driver: disable: - if: SOC_MCPWM_SUPPORTED != 1 + depends_filepatterns: + - components/driver/deprecated/**/*mcpwm* components/driver/test_apps/legacy_pcnt_driver: disable: - if: SOC_PCNT_SUPPORTED != 1 + depends_filepatterns: + - components/driver/deprecated/**/*pcnt* components/driver/test_apps/legacy_rmt_driver: disable: - if: SOC_RMT_SUPPORTED != 1 + depends_filepatterns: + - components/driver/deprecated/**/*rmt* components/driver/test_apps/legacy_rtc_temp_driver: disable: @@ -91,17 +60,15 @@ components/driver/test_apps/legacy_sigma_delta_driver: disable: - if: SOC_SDM_SUPPORTED != 1 depends_filepatterns: - - components/driver/deprecated/**/* + - components/driver/deprecated/**/*sigma* depends_components: - esp_driver_gpio components/driver/test_apps/legacy_timer_driver: disable: - if: SOC_GPTIMER_SUPPORTED != 1 - -components/driver/test_apps/mcpwm: - disable: - - if: SOC_MCPWM_SUPPORTED != 1 + depends_filepatterns: + - components/driver/deprecated/**/*timer* components/driver/test_apps/parlio: disable: @@ -111,71 +78,18 @@ components/driver/test_apps/parlio: temporary: true reason: lack of runner -components/driver/test_apps/rmt: - disable: - - if: SOC_RMT_SUPPORTED != 1 - -components/driver/test_apps/rs485: - disable: - - if: SOC_UART_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET != "esp32" - temporary: true - reason: lack of runners - -components/driver/test_apps/sdio: - disable: - - if: SOC_SDIO_SLAVE_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32c6" - temporary: true - reason: lack of runners - -components/driver/test_apps/sigma_delta: - disable: - - if: SOC_SDM_SUPPORTED != 1 - depends_filepatterns: - - components/driver/sigma_delta/**/* - depends_components: - - esp_driver_gpio - -components/driver/test_apps/spi/master: - disable: - - if: SOC_GPSPI_SUPPORTED != 1 - -components/driver/test_apps/spi/param: - disable: - - if: SOC_GPSPI_SUPPORTED != 1 - -components/driver/test_apps/spi/slave: - disable: - - if: SOC_GPSPI_SUPPORTED != 1 - -components/driver/test_apps/spi/slave_hd: - disable: - - if: SOC_GPSPI_SUPPORTED != 1 - - if: SOC_SPI_SUPPORT_SLAVE_HD_VER2 != 1 - -components/driver/test_apps/temperature_sensor: - disable: - - if: SOC_TEMP_SENSOR_SUPPORTED != 1 - components/driver/test_apps/touch_sensor_v1: disable: - - if: SOC_TOUCH_VERSION_1 != 1 + - if: SOC_TOUCH_SENSOR_VERSION != 1 components/driver/test_apps/touch_sensor_v2: disable: - - if: SOC_TOUCH_VERSION_2 != 1 + - if: SOC_TOUCH_SENSOR_VERSION != 2 components/driver/test_apps/twai: disable: - if: SOC_TWAI_SUPPORTED != 1 -components/driver/test_apps/uart: - disable: - - if: SOC_UART_SUPPORTED != 1 - components/driver/test_apps/usb_serial_jtag: disable: - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 diff --git a/components/driver/test_apps/components/test_driver_utils/CMakeLists.txt b/components/driver/test_apps/components/test_driver_utils/CMakeLists.txt index 8d35576ec53..9e70b9939b9 100644 --- a/components/driver/test_apps/components/test_driver_utils/CMakeLists.txt +++ b/components/driver/test_apps/components/test_driver_utils/CMakeLists.txt @@ -1,5 +1,5 @@ idf_component_register( - SRCS test_spi_utils.c param_test.c + SRCS test_spi_utils.c param_test.c test_dualboard_utils.c INCLUDE_DIRS include REQUIRES driver unity ) diff --git a/components/driver/test_apps/components/test_driver_utils/include/test_dualboard_utils.h b/components/driver/test_apps/components/test_driver_utils/include/test_dualboard_utils.h new file mode 100644 index 00000000000..09e37a7dd8b --- /dev/null +++ b/components/driver/test_apps/components/test_driver_utils/include/test_dualboard_utils.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include + +/** + * Fill tx_buffers used in dual-board test with random numbers + * + * dut0_buffer and dut1_buffer will be filled with random data + * + * this can be used by a fullduplex dualboard transaction + * + * @param seed Random number seed + * @param dut0_buffer TX buffer used by dut0 + * @param dut1_buffer TX buffer used by dut1 + * @param buffer_size Buffer size + */ +void test_fill_random_to_buffers_dualboard(uint32_t seed, uint8_t *dut0_buffer, uint8_t *dut1_buffer, size_t buffer_size); + + +/** + * Fill tx buffer with random numbers + * + * @param seed Random number seed + * @param buffer Buffer + * @param buffer_size Buffer size + */ +void test_fill_random_to_buffer(uint32_t seed, uint8_t *buffer, size_t buffer_size); + + +/** + * Calloc a pool, filled with random numbers + * + * @param pool_size Size of the pool + * @param flags Calloc flags, see `esp_heap_caps.h` + */ +void test_prepare_buffer_pool(size_t pool_size, uint32_t flags); + +/** + * Get a buffer from the pool + * + * @param offset A random offset + * @param size Buffer size + * @param[out] out_buffer Out buffer + */ +void test_get_buffer_from_pool(uint32_t offset, size_t size, void **out_buffer); + +/** + * Destroy the pool + */ +void test_destroy_buffer_pool(void); diff --git a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h index c27ce19dee0..214e8b513f1 100644 --- a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h +++ b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h @@ -22,6 +22,7 @@ #include "sdkconfig.h" #include "soc/spi_periph.h" #include "driver/spi_master.h" +#include "test_dualboard_utils.h" // All the tests using the header should use this definition as much as possible, // so that the working host can be changed easily in the future. @@ -292,15 +293,4 @@ void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx); //then the cs_num of the 1st and 2nd devices are 0 and 1 respectively. void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_num); -/** - * This function is used to get tx_buffer used in dual-board test - * `master_send_buf` and `slave_send_buf` will be fulfilled with same random numbers with the seed of `seed`. - * - * @param seed Random number seed - * @param master_send_buf Master TX buffer - * @param slave_send_buf Slave TX buffer - * @param send_buf_size Buffer size - */ -void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size); - #endif //_TEST_COMMON_SPI_H_ diff --git a/components/driver/test_apps/components/test_driver_utils/test_dualboard_utils.c b/components/driver/test_apps/components/test_driver_utils/test_dualboard_utils.c new file mode 100644 index 00000000000..e119173169c --- /dev/null +++ b/components/driver/test_apps/components/test_driver_utils/test_dualboard_utils.c @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "esp_log.h" +#include "esp_heap_caps.h" +#include "test_dualboard_utils.h" + +/*--------------------------------------------------------------- + Fill buffer with random numbers +---------------------------------------------------------------*/ +void test_fill_random_to_buffers_dualboard(uint32_t seed, uint8_t *dut0_buffer, uint8_t *dut1_buffer, size_t buffer_size) +{ + srand(seed); + for (int i = 0; i < buffer_size; i++) { + dut1_buffer[i] = rand() % 256; + dut0_buffer[i] = rand() % 256; + } +} + +void test_fill_random_to_buffer(uint32_t seed, uint8_t *buffer, size_t buffer_size) +{ + srand(seed); + for (int i = 0; i < buffer_size; i++) { + buffer[i] = rand() % 256; + } +} + + +/*--------------------------------------------------------------- + Create a pool with random numbers, get buffer from pool +---------------------------------------------------------------*/ +static uint8_t *s_pool; +static size_t s_pool_size; + +void test_prepare_buffer_pool(size_t pool_size, uint32_t flags) +{ + s_pool_size = pool_size; + s_pool = (uint8_t *)heap_caps_calloc(1, pool_size, flags); + TEST_ASSERT(s_pool); + test_fill_random_to_buffer(199, s_pool, pool_size); +} + +void test_get_buffer_from_pool(uint32_t offset, size_t size, void **out_buffer) +{ + //to make sure the out_buffer is within the pool + offset = ((offset % (s_pool_size - size)) + 3) & ~3; + // TEST_ASSERT(offset + size < (uint32_t)s_pool + s_pool_size) + + *out_buffer = (void *)(s_pool + offset); +} + +void test_destroy_buffer_pool(void) +{ + free(s_pool); + s_pool = NULL; + s_pool_size = 0; +} diff --git a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c index 829e7d5e650..869c48927af 100644 --- a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c +++ b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c @@ -240,12 +240,3 @@ void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, GPIO.func_in_sel_cfg[FSPIQ_IN_IDX].sig_in_sel = 1; #endif } - -void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size) -{ - srand(seed); - for (int i = 0; i < send_buf_size; i++) { - slave_send_buf[i] = rand() % 256; - master_send_buf[i] = rand() % 256; - } -} diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_adc.c b/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_adc.c index a7c29dd6c8f..9e20140149a 100644 --- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_adc.c +++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_adc.c @@ -155,14 +155,14 @@ static void example_i2s_init(void) }; //install and start i2s driver - TEST_ESP_OK( i2s_driver_install(i2s_num, &i2s_config, 0, NULL) ); + TEST_ESP_OK(i2s_driver_install(i2s_num, &i2s_config, 0, NULL)); //init ADC pad - TEST_ESP_OK( i2s_set_adc_mode(I2S_ADC_UNIT, I2S_ADC_CHANNEL) ); + TEST_ESP_OK(i2s_set_adc_mode(I2S_ADC_UNIT, I2S_ADC_CHANNEL)); } static void example_i2s_deinit(void) { - TEST_ESP_OK( i2s_driver_uninstall(EXAMPLE_I2S_NUM) ); + TEST_ESP_OK(i2s_driver_uninstall(EXAMPLE_I2S_NUM)); } /** @@ -172,9 +172,11 @@ static void example_disp_buf(uint8_t *buf, int length) { printf("\n======"); for (int i = 0; i < length; i += 2) { - uint16_t data = ((uint16_t)buf[i+1] << 8) | (uint16_t)buf[i]; + uint16_t data = ((uint16_t)buf[i + 1] << 8) | (uint16_t)buf[i]; adc_digi_output_data_t *p = (adc_digi_output_data_t *)&data; - if ((i) % 16 == 0) printf("\n"); + if ((i) % 16 == 0) { + printf("\n"); + } printf("[%d_%d] ", p->type1.channel, p->type1.data); } printf("\n======\n"); @@ -183,17 +185,17 @@ static void example_disp_buf(uint8_t *buf, int length) static esp_err_t adc_dma_data_check(uint8_t *buf, int length, int ideal_level) { for (int i = 0; i < length; i += 2) { - uint16_t data = ((uint16_t)buf[i+1] << 8) | (uint16_t)buf[i]; + uint16_t data = ((uint16_t)buf[i + 1] << 8) | (uint16_t)buf[i]; adc_digi_output_data_t *p = (adc_digi_output_data_t *)&data; if (p->type1.channel != I2S_ADC_CHANNEL) { TEST_FAIL_MESSAGE("I2S-DMA data channel error!"); } if (ideal_level == 1) { // high level 3.3v - TEST_ASSERT_EQUAL( 0xFFF, p->type1.data ); + TEST_ASSERT_EQUAL(0xFFF, p->type1.data); } else if (ideal_level == 0) { // low level 0v - TEST_ASSERT_LESS_THAN( 10, p->type1.data ); + TEST_ASSERT_LESS_THAN(10, p->type1.data); } else if (ideal_level == 2) { // middle level 1.4v - TEST_ASSERT_INT_WITHIN( 128, 1586, p->type1.data ); + TEST_ASSERT_INT_WITHIN(128, 1586, p->type1.data); } else if (ideal_level == 3) { // normal level } else { // no check } @@ -209,7 +211,7 @@ static void adc_dma_read(uint8_t *buf, int length) vTaskDelay(pdTICKS_TO_MS(100)); while (flash_wr_size < length) { //read data from I2S bus, in this case, from ADC. - TEST_ESP_OK( i2s_read(EXAMPLE_I2S_NUM, (void *) buf + flash_wr_size, length - flash_wr_size, &bytes_read, portMAX_DELAY) ); + TEST_ESP_OK(i2s_read(EXAMPLE_I2S_NUM, (void *) buf + flash_wr_size, length - flash_wr_size, &bytes_read, portMAX_DELAY)); flash_wr_size += bytes_read; example_disp_buf((uint8_t *) buf, 128); } @@ -221,7 +223,7 @@ TEST_CASE("ADC_DMA_read", "[adc dma]") char *i2s_read_buff = (char *) calloc(i2s_read_len, sizeof(char)); example_i2s_init(); - TEST_ESP_OK( i2s_adc_enable(EXAMPLE_I2S_NUM) ); + TEST_ESP_OK(i2s_adc_enable(EXAMPLE_I2S_NUM)); adc_fake_tie_low(I2S_ADC_UNIT, I2S_ADC_CHANNEL); adc_dma_read((uint8_t *)i2s_read_buff, i2s_read_len); @@ -237,7 +239,7 @@ TEST_CASE("ADC_DMA_read", "[adc dma]") adc_io_normal(I2S_ADC_UNIT, I2S_ADC_CHANNEL); - TEST_ESP_OK( i2s_adc_disable(EXAMPLE_I2S_NUM) ); + TEST_ESP_OK(i2s_adc_disable(EXAMPLE_I2S_NUM)); if (i2s_read_buff) { free(i2s_read_buff); i2s_read_buff = NULL; diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_dac.c b/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_dac.c index 88c4a47e2fd..dc102547b1b 100644 --- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_dac.c +++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac/main/test_i2s_dac.c @@ -62,15 +62,15 @@ static void example_i2s_init(void) .use_apll = 0, }; //install and start i2s driver - TEST_ESP_OK( i2s_driver_install(i2s_num, &i2s_config, 0, NULL) ); + TEST_ESP_OK(i2s_driver_install(i2s_num, &i2s_config, 0, NULL)); //init DAC pad - TEST_ESP_OK( i2s_set_dac_mode(I2S_DAC_CHANNEL_BOTH_EN) ); + TEST_ESP_OK(i2s_set_dac_mode(I2S_DAC_CHANNEL_BOTH_EN)); } static void example_i2s_deinit(void) { - TEST_ESP_OK( i2s_set_dac_mode(I2S_DAC_CHANNEL_DISABLE) ); - TEST_ESP_OK( i2s_driver_uninstall(EXAMPLE_I2S_NUM) ); + TEST_ESP_OK(i2s_set_dac_mode(I2S_DAC_CHANNEL_DISABLE)); + TEST_ESP_OK(i2s_driver_uninstall(EXAMPLE_I2S_NUM)); } /** @@ -78,7 +78,7 @@ static void example_i2s_deinit(void) */ static void example_set_file_play_mode(void) { - TEST_ESP_OK( i2s_set_clk(EXAMPLE_I2S_NUM, 16000, EXAMPLE_I2S_SAMPLE_BITS, 1) ); + TEST_ESP_OK(i2s_set_clk(EXAMPLE_I2S_NUM, 16000, EXAMPLE_I2S_SAMPLE_BITS, 1)); } /** @@ -125,7 +125,7 @@ static void example_disp_buf(uint8_t *buf, int length) */ static void example_reset_play_mode(void) { - TEST_ESP_OK( i2s_set_clk(EXAMPLE_I2S_NUM, EXAMPLE_I2S_SAMPLE_RATE, EXAMPLE_I2S_SAMPLE_BITS, EXAMPLE_I2S_CHANNEL_NUM) ); + TEST_ESP_OK(i2s_set_clk(EXAMPLE_I2S_NUM, EXAMPLE_I2S_SAMPLE_RATE, EXAMPLE_I2S_SAMPLE_BITS, EXAMPLE_I2S_CHANNEL_NUM)); } TEST_CASE("DAC_DMA_output", "[dac]") diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c index 38e30e89774..26d38344bb0 100644 --- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c +++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c @@ -223,8 +223,8 @@ static bool whether_contains_exapected_data(uint16_t *src, uint32_t src_len, uin if (src[i] == val) { if (val == start_val && i < src_len - 8) { printf("start index: %d ---> \n%d %d %d %d %d %d %d %d\n", i, - src[i], src[i+1], src[i+2], src[i+3], - src[i+4], src[i+5], src[i+6], src[i+7]); + src[i], src[i + 1], src[i + 2], src[i + 3], + src[i + 4], src[i + 5], src[i + 6], src[i + 7]); } index_step = src_step; val += val_step; @@ -299,7 +299,7 @@ TEST_CASE("I2S_legacy_mono_stereo_loopback_test", "[i2s_legacy]") uint32_t retry = 0; bool is_failed = false; for (int n = 0; n < WRITE_BUF_LEN / 2; n++) { - w_buf[n] = n%100; + w_buf[n] = n % 100; } /* rx right mono test * tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ... @@ -307,14 +307,14 @@ TEST_CASE("I2S_legacy_mono_stereo_loopback_test", "[i2s_legacy]") TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY)); for (retry = 0; retry < RETEY_TIMES; retry++) { TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY)); - #if CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 /* The data of tx/rx channels are flipped on ESP32 */ for (int n = 0; n < READ_BUF_LEN / 2; n += 2) { int16_t temp = r_buf[n]; - r_buf[n] = r_buf[n+1]; - r_buf[n+1] = temp; + r_buf[n] = r_buf[n + 1]; + r_buf[n + 1] = temp; } - #endif +#endif /* Expected: 1 3 5 7 9 ... 97 99 */ if (whether_contains_exapected_data(r_buf, READ_BUF_LEN / 2, 1, 1, 2)) { break; @@ -385,14 +385,14 @@ TEST_CASE("I2S_legacy_mono_stereo_loopback_test", "[i2s_legacy]") TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY)); for (retry = 0; retry < RETEY_TIMES; retry++) { TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY)); - #if CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 /* The data of tx/rx channels are flipped on ESP32 */ for (int n = 0; n < READ_BUF_LEN / 2; n += 2) { int16_t temp = r_buf[n]; - r_buf[n] = r_buf[n+1]; - r_buf[n+1] = temp; + r_buf[n] = r_buf[n + 1]; + r_buf[n + 1] = temp; } - #endif +#endif /* Expected: 2 4 6 8 10 ... 96 98 */ if (whether_contains_exapected_data(r_buf, READ_BUF_LEN / 2, 1, 2, 2)) { break; @@ -877,7 +877,8 @@ static void i2s_test_common_sample_rate(i2s_port_t id) const uint32_t test_freq[] = { 8000, 10000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 64000, 88200, - 96000, 128000, 144000,196000}; + 96000, 128000, 144000, 196000 + }; int real_pulse = 0; #if CONFIG_IDF_ENV_FPGA // Limit the test sample rate on FPGA platform due to the low frequency it supports. diff --git a/components/driver/test_apps/legacy_i2c_driver/README.md b/components/driver/test_apps/legacy_i2c_driver/README.md index a8b7833fa30..bf47d80ec64 100644 --- a/components/driver/test_apps/legacy_i2c_driver/README.md +++ b/components/driver/test_apps/legacy_i2c_driver/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c b/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c index ea4b03da85a..5668bea0b54 100644 --- a/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c +++ b/components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c @@ -20,6 +20,7 @@ #include "hal/gpio_hal.h" #include "hal/uart_ll.h" #include "hal/i2c_types.h" +#include "soc/uart_periph.h" #include "test_utils.h" #define DATA_LENGTH 512 /*! 512 -#define TEST_CNT 10000 - -#define TEST_SDSPI_HOST SPI2_HOST -#define TEST_SDSPI_DMACHAN 1 - -#define TEST_RESET_DATA_LEN 10 - -#ifndef MIN -#define MIN(a, b) ((a)<(b)? (a): (b)) -#endif - -typedef enum { - SDIO_1BIT = 0, - SDIO_4BIT = 1, - SDIO_SPI = 2, -} sdio_mode_t; - -typedef void (*sdio_test_func)(essl_handle_t handle); - -typedef struct { - const char test_name[16]; - sdio_mode_t sdio_mode; - uint32_t freq; - bool check_data; - bool packet_mode; -} sdio_test_config_t; - - -sdio_test_config_t test_cfg_array[] = { - //the first item will be the default config used by all tests - { - .test_name = "HS4B", - .sdio_mode = SDIO_4BIT, - .freq = SDMMC_FREQ_HIGHSPEED, - .check_data = true, - }, - { - .test_name = "HS1B", - .sdio_mode = SDIO_1BIT, - .freq = SDMMC_FREQ_HIGHSPEED, - .check_data = true, - }, - { - .test_name = "SPI", - .sdio_mode = SDIO_SPI, - .freq = SDMMC_FREQ_HIGHSPEED, - .check_data = true, - }, - //the performance test is only done when psram is not enabled -#if !CONFIG_SPIRAM && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE - { - .test_name = "HS4B (perf)", - .sdio_mode = SDIO_4BIT, - .freq = SDMMC_FREQ_HIGHSPEED, - }, - { - .test_name = "HS1B (perf)", - .sdio_mode = SDIO_1BIT, - .freq = SDMMC_FREQ_HIGHSPEED, - }, - { - .test_name = "SPI (perf)", - .sdio_mode = SDIO_SPI, - .freq = SDMMC_FREQ_HIGHSPEED, - }, -#endif -}; - -sdio_test_config_t packet_config = { - .test_name = "HS4B packet", - .sdio_mode = SDIO_4BIT, - .freq = SDMMC_FREQ_HIGHSPEED, - .check_data = true, - .packet_mode = true, -}; - -const sdio_test_config_t* default_config = &test_cfg_array[0]; - -#define TEST_SIZE (sizeof(test_cfg_array)/sizeof(sdio_test_config_t)) - - -/******************************************************************************* - * Master - ******************************************************************************/ - -static sdmmc_card_t s_card; - -typedef void (*test_func_t)(essl_handle_t handle, const sdio_test_config_t* config); - -static void init_sdmmc_host(void); -static void init_essl(essl_handle_t *out_handle, const sdio_test_config_t *conf); -static void deinit_essl(essl_handle_t handle, const sdio_test_config_t *conf); - -static void test_framework_master(test_func_t test_func, const sdio_test_config_t* config) -{ - unity_send_signal("Master ready"); - unity_wait_for_signal("Slave ready"); - ESP_LOGI(MASTER_TAG, "### Testing %s... ####", config->test_name); - essl_handle_t handle; - esp_err_t err; - init_essl(&handle, config); - - err = essl_init(handle, TIMEOUT_MAX); - TEST_ESP_OK(err); - - (*test_func)(handle, config); - - deinit_essl(handle, config); -} - -static void init_sdmmc_host(void) -{ - esp_err_t err; - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - err = sdmmc_host_init(); - TEST_ESP_OK(err); - - err = sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config); - TEST_ESP_OK(err); -} - -static void init_essl(essl_handle_t *out_handle, const sdio_test_config_t *conf) -{ - sdmmc_host_t config; - esp_err_t err; - spi_bus_config_t bus_config; - /* Probe */ - - switch (conf->sdio_mode) { - case SDIO_4BIT: - ESP_LOGI(MASTER_TAG, "Probe using SD 4-bit..."); - config = (sdmmc_host_t)SDMMC_HOST_DEFAULT(); - config.flags = SDMMC_HOST_FLAG_4BIT; - config.max_freq_khz = conf->freq; - init_sdmmc_host(); - break; - case SDIO_1BIT: - ESP_LOGI(MASTER_TAG, "Probe using SD 1-bit..."); - config = (sdmmc_host_t)SDMMC_HOST_DEFAULT(); - config.flags = SDMMC_HOST_FLAG_1BIT; - config.max_freq_khz = conf->freq; - init_sdmmc_host(); - break; - case SDIO_SPI: - bus_config = (spi_bus_config_t) { - .mosi_io_num = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD, - .miso_io_num = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0, - .sclk_io_num = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - err = spi_bus_initialize(TEST_SDSPI_HOST, &bus_config, TEST_SDSPI_DMACHAN); - TEST_ESP_OK(err); - - sdspi_device_config_t device_config = SDSPI_DEVICE_CONFIG_DEFAULT(); - device_config.host_id = TEST_SDSPI_HOST; - device_config.gpio_cs = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3; - device_config.gpio_int= SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1; - - err = gpio_install_isr_service(0); - TEST_ASSERT(err == ESP_OK || err == ESP_ERR_INVALID_STATE); - - sdspi_dev_handle_t sdspi_handle; - err = sdspi_host_init(); - TEST_ESP_OK(err); - err = sdspi_host_init_device(&device_config, &sdspi_handle); - TEST_ESP_OK(err); - - ESP_LOGI(MASTER_TAG, "Probe using SPI..."); - - config = (sdmmc_host_t)SDSPI_HOST_DEFAULT(); - config.slot = sdspi_handle; - break; - } - - sdmmc_card_t *card = &s_card; - //wait for at least 5 seconds - int retry_times = 5; - do { - if (sdmmc_card_init(&config, card) == ESP_OK) { - break; - } - ESP_LOGW(MASTER_TAG, "slave init failed, retry..."); - vTaskDelay(1000 / portTICK_PERIOD_MS); - } while (--retry_times); - TEST_ASSERT_MESSAGE(retry_times != 0, "Initializing slave failed."); - essl_sdio_config_t ser_config = { - .card = card, - .recv_buffer_size = RX_BUFFER_SIZE, - }; - err = essl_sdio_init_dev(out_handle, &ser_config); - TEST_ESP_OK(err); - - err = essl_init(*out_handle, TIMEOUT_MAX); - TEST_ESP_OK(err); -} - -static void deinit_essl(essl_handle_t handle, const sdio_test_config_t *conf) -{ - esp_err_t err; - essl_sdio_deinit_dev(handle); - if (conf->sdio_mode == SDIO_SPI) { - gpio_uninstall_isr_service(); - - err = sdspi_host_deinit(); - TEST_ESP_OK(err); - - err = spi_bus_free(TEST_SDSPI_HOST); - TEST_ESP_OK(err); - } else { - err = sdmmc_host_deinit(); - TEST_ESP_OK(err); - } -} - -static void send_finish_test(essl_handle_t handle) -{ - //the slave needs a signal to quite the test - essl_send_slave_intr(handle, BIT(7), TIMEOUT_MAX); -} - -static void test_int(essl_handle_t handle, const sdio_test_config_t* config) -{ - esp_err_t err; - err = essl_set_intr_ena(handle, INT_MASK_ALL, TIMEOUT_MAX); - TEST_ESP_OK(err); - - err = essl_wait_int(handle, 0); - TEST_ASSERT_EQUAL_HEX(ESP_ERR_TIMEOUT, err); - - //tests all 8 interrupts of the slave, in which int 7 is used to terminate the test on the slave. - for (int i = 0; i < 8; i ++) { - uint32_t int_st; - err = essl_send_slave_intr(handle, BIT(i), TIMEOUT_MAX); - TEST_ESP_OK(err); - //the slave should return interrupt with the same bit in 10 ms - err = essl_wait_int(handle, 10); - TEST_ESP_OK(err); - - err = essl_get_intr(handle, NULL, &int_st, TIMEOUT_MAX); - TEST_ESP_OK(err); - //check and clear the returned interrupt - TEST_ASSERT_EQUAL_HEX(BIT(i), int_st); - err = essl_clear_intr(handle, int_st, TIMEOUT_MAX); - TEST_ESP_OK(err); - } -} - -static void test_sdio_interrupt_master(void) -{ - test_framework_master(test_int, default_config); -} - -static void test_reg(essl_handle_t handle, const sdio_test_config_t* config) -{ - esp_err_t err; - uint8_t data[REG_ADDR_MAX]; - srand(850); - - //initialize the buffer - for (int i = 0; i < REG_ADDR_MAX; i++) { - data[i] = rand(); - err = essl_write_reg(handle, i, data[i], NULL, 10); - TEST_ESP_OK(err); - } - - for (int i = 0; i < 512; i++) { - //randomly write one - int offset = rand() % REG_ADDR_MAX; - uint8_t data_write = rand(); - data[offset] = data_write; - - err = essl_write_reg(handle, offset, data_write, NULL, 10); - TEST_ESP_OK(err); - - //randomly read another one and compare - offset = rand() % REG_ADDR_MAX; - uint8_t data_read; - err = essl_read_reg(handle, offset, &data_read, 10); - TEST_ESP_OK(err); - - TEST_ASSERT_EQUAL_HEX8(data[offset], data_read); - } - - send_finish_test(handle); -} - -static void test_sdio_reg_master(void) -{ - test_framework_master(test_reg, default_config); -} - -static uint8_t tx_buffer[TX_BUFFER_SIZE*2]; -static uint8_t rcv_buffer[RX_BUFFER_SIZE*RX_BUFFER_NUM]; - -static void init_tx_buffer(void) -{ - srand(776); - for (int i = 0; i < sizeof(tx_buffer); i++) { - tx_buffer[i] = rand(); - } -} - -static void get_master_send_data(int offset, uint8_t** out_start, int* out_len) -{ - int page_cnt = offset / TX_BUFFER_SIZE; - int offset_in_page = offset % TX_BUFFER_SIZE; - srand(page_cnt); - int page_offset = (rand() % (sizeof(tx_buffer) - (TX_BUFFER_SIZE) + 1)) & (~3); - *out_start = &tx_buffer[page_offset + offset_in_page]; - *out_len = TX_BUFFER_SIZE - offset_in_page; -} - -static void log_performance_tohost(uint32_t speed, const sdio_test_config_t* config) -{ - if (!config->check_data) { - switch (config->sdio_mode) { - case SDIO_4BIT: - TEST_PERFORMANCE_CCOMP_GREATER_THAN(SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT, "%" PRIu32, speed); - break; - case SDIO_1BIT: - TEST_PERFORMANCE_CCOMP_GREATER_THAN(SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT, "%" PRIu32, speed); - break; - case SDIO_SPI: - TEST_PERFORMANCE_CCOMP_GREATER_THAN(SDIO_THROUGHPUT_KBSEC_TOHOST_SPI, "%" PRIu32, speed); - break; - } - } -} - -static void test_tp_tohost_master(essl_handle_t handle, const sdio_test_config_t* config) -{ - esp_err_t err; - int expected_length = TEST_CNT * TX_BUFFER_SIZE; - int recv_size = 4096; - init_tx_buffer(); - //wait for the slave to get ready - vTaskDelay(20); - - int remain_length = expected_length; - int offset = 0; - - // Two counters are used. The `esp_timer_get_time()` is for the typical time, and the - // `ccomp_timer` is for performance test to reduce influence caused by cache miss. - int64_t pre_us = esp_timer_get_time(); - err = ccomp_timer_start(); - assert(err == ESP_OK); - // though the flow is the same, the check of config->check_data influences the throughput much, put it outside - if (config->check_data) { - do { - size_t rcv_len; - err = essl_get_packet(handle, rcv_buffer, recv_size, &rcv_len, TIMEOUT_MAX); - TEST_ASSERT(err == ESP_OK || err == ESP_ERR_NOT_FINISHED); - TEST_ASSERT_LESS_OR_EQUAL(remain_length, rcv_len); - - //compare until all received data are used - int compared_len = 0; - do { - //get the expected master sent data, there may be several segments, so get and compare - //several times - uint8_t* cmp_start; - int seg_len; - get_master_send_data(offset, &cmp_start, &seg_len); - - int cmp_len = MIN(rcv_len-compared_len, seg_len); - - TEST_ASSERT_EQUAL_HEX8_ARRAY(cmp_start, &rcv_buffer[compared_len], cmp_len); - - compared_len += cmp_len; - offset += cmp_len; - } while (compared_len < rcv_len); - - remain_length -= rcv_len; - } while (remain_length > 0); - } else { - do { - size_t rcv_len; - err = essl_get_packet(handle, rcv_buffer, recv_size, &rcv_len, TIMEOUT_MAX); - TEST_ASSERT(err == ESP_OK || err == ESP_ERR_NOT_FINISHED); - TEST_ASSERT_LESS_OR_EQUAL(remain_length, rcv_len); - - offset += rcv_len; - remain_length -= rcv_len; - } while (remain_length > 0); - } - int64_t c_time_ms = ccomp_timer_stop()/1000; - int64_t end_us = esp_timer_get_time(); - - uint32_t total_time_ms = (end_us - pre_us)/1000; - ESP_LOGI(MASTER_TAG, "test done, total time: %" PRIu32 " ms (%d ms compensated), bytes transferred: %d", total_time_ms, (int)c_time_ms, expected_length); - - uint32_t throughput_byte_per_ms = expected_length / c_time_ms; - ESP_LOGI(MASTER_TAG, "Throughput: compensated %.2lf MB/s, typical %.2lf MB/s", - throughput_byte_per_ms/1000., expected_length/(total_time_ms*1000.)); - log_performance_tohost(throughput_byte_per_ms, config); - - send_finish_test(handle); -} - -static void log_performance_frhost(uint32_t speed, const sdio_test_config_t* config) -{ - if (!config->check_data) { - switch (config->sdio_mode) { - case SDIO_4BIT: - TEST_PERFORMANCE_CCOMP_GREATER_THAN(SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT, "%" PRIu32, speed); - break; - case SDIO_1BIT: - TEST_PERFORMANCE_CCOMP_GREATER_THAN(SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT, "%" PRIu32, speed); - break; - case SDIO_SPI: - TEST_PERFORMANCE_CCOMP_GREATER_THAN(SDIO_THROUGHPUT_KBSEC_FRHOST_SPI, "%" PRIu32, speed); - break; - } - } -} - -static void test_tp_frhost_master(essl_handle_t handle, const sdio_test_config_t* config) -{ - esp_err_t err; - int expected_length = TEST_CNT * TX_BUFFER_SIZE; - init_tx_buffer(); - //wait for the slave to get ready - vTaskDelay(20); - - int remain_length = expected_length; - int offset = 0; - - // Two counters are used. The `esp_timer_get_time()` is for the typical time, and the - // `ccomp_timer` is for performance test to reduce influence caused by cache miss. - int64_t pre_us = esp_timer_get_time(); - err = ccomp_timer_start(); - assert(err == ESP_OK); - do { - int send_len; - uint8_t* send_start; - get_master_send_data(offset, &send_start, &send_len); - TEST_ASSERT_EQUAL(TX_BUFFER_SIZE, send_len); - - err = essl_send_packet(handle, send_start, send_len, TIMEOUT_MAX); - TEST_ASSERT(err == ESP_OK); - - remain_length -= send_len; - offset += send_len; - } while (remain_length > 0); - - int64_t c_time_ms = ccomp_timer_stop()/1000; - int64_t end_us = esp_timer_get_time(); - - uint32_t total_time_ms = (end_us - pre_us)/1000; - ESP_LOGI(MASTER_TAG, "test done, total time: %" PRIu32 " ms (%d ms compensated), bytes transferred: %d", total_time_ms, (int)c_time_ms, expected_length); - - uint32_t throughput_byte_per_ms = expected_length / c_time_ms; - ESP_LOGI(MASTER_TAG, "Throughput: compensated %.2lf MB/s, typical %.2lf MB/s", - throughput_byte_per_ms/1000., expected_length/(total_time_ms*1000.)); - log_performance_frhost(throughput_byte_per_ms, config); - - send_finish_test(handle); -} - -void test_reset_master(essl_handle_t handle, const sdio_test_config_t* config) -{ - init_tx_buffer(); - //wait for the slave to stop, reset and start again - vTaskDelay(10); - - for (int i = 0; i < 10; i++) { - WORD_ALIGNED_ATTR uint8_t buffer[TEST_RESET_DATA_LEN]; - size_t read_len; - esp_err_t err = essl_get_packet(handle, buffer, TEST_RESET_DATA_LEN, &read_len, portMAX_DELAY); - if (err == ESP_ERR_NOT_FINISHED) { - TEST_ASSERT_LESS_THAN(10, i); - err = ESP_OK; - } - TEST_ESP_OK(err); - TEST_ASSERT_EQUAL(TEST_RESET_DATA_LEN, read_len); - TEST_ASSERT_EQUAL_HEX8_ARRAY(tx_buffer + 4*i, buffer, read_len); - } - - for (int i = 0; i < 10; i++) { - esp_err_t err = essl_send_packet(handle, tx_buffer + i * 8, TEST_RESET_DATA_LEN, portMAX_DELAY); - TEST_ESP_OK(err); - } - - send_finish_test(handle); -} - -void test_sdio_reset_master(void) -{ - test_framework_master(test_reset_master, &packet_config); -} - -/******************************************************************************* - * Slave - ******************************************************************************/ - -typedef struct { - int queued_cnt; - bool s_finished; -} slave_context_t; - -typedef void (*test_func_slave_t)(slave_context_t *context, const sdio_test_config_t* config); - -static slave_context_t slave_context; - -static void event_cb(uint8_t event) -{ - ESP_EARLY_LOGI(SLAVE_TAG, "event: %d", event); - sdio_slave_send_host_int(event); - if (event == 7) slave_context.s_finished = true; -} - - -static void wait_for_finish(slave_context_t *ctx) -{ - while (!ctx->s_finished) { - vTaskDelay(10); - } - //wait for host to read the respond from slave - vTaskDelay(10); -} - -static void test_framework_slave(test_func_slave_t test_func, const sdio_test_config_t* config) -{ - unity_wait_for_signal("Master ready"); - slave_context.s_finished = false; - esp_err_t err; - sdio_slave_config_t slave_config = { - .sending_mode = (config->packet_mode? SDIO_SLAVE_SEND_PACKET: SDIO_SLAVE_SEND_STREAM), - .send_queue_size = SDIO_SLAVE_QUEUE_SIZE, - .recv_buffer_size = RX_BUFFER_SIZE, - .event_cb = event_cb, - }; - err = sdio_slave_initialize(&slave_config); - TEST_ESP_OK(err); - - err = sdio_slave_start(); - TEST_ESP_OK(err); - - unity_send_signal("Slave ready"); - - test_func(&slave_context, config); - - sdio_slave_stop(); - sdio_slave_deinit(); -} - -static void test_int_slave(slave_context_t* ctx, const sdio_test_config_t* config) -{ - wait_for_finish(ctx); -} - -static void test_sdio_interrupt_slave(void) -{ - test_framework_slave(test_int_slave, default_config); -} - -static void test_tp_tohost_slave(slave_context_t* ctx, const sdio_test_config_t* config) -{ -#define QUEUE_FULL() (ctx->queued_cnt == SDIO_SLAVE_QUEUE_SIZE) -#define QUEUE_EMPTY() (ctx->queued_cnt == 0) - - init_tx_buffer(); - esp_err_t err; - int offset = 0; - for (int i = 0; i < TEST_CNT; i++) { - do { - void* arg; - //when the queue is full, do a blocking wait for 10ms, otherwise non-blocking - err = sdio_slave_send_get_finished(&arg, QUEUE_FULL()? 1: 0); - if (err == ESP_OK) { - ctx->queued_cnt --; - continue; - } - TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, err); - } while (QUEUE_FULL()); - - uint8_t* start; - int send_len; - get_master_send_data(offset, &start, &send_len); - TEST_ASSERT_EQUAL(TX_BUFFER_SIZE, send_len); - - err = sdio_slave_send_queue(start, send_len, NULL, portMAX_DELAY); - TEST_ESP_OK(err); - - ctx->queued_cnt++; - offset += TX_BUFFER_SIZE; - } - - while (!QUEUE_EMPTY()) { - void* arg; - err = sdio_slave_send_get_finished(&arg, portMAX_DELAY); - TEST_ESP_OK(err); - ctx->queued_cnt--; - } - - wait_for_finish(ctx); -} - -static void slave_parepare_recv_buffer(void) -{ - for (int i = 0; i < RX_BUFFER_NUM; i++) { - sdio_slave_buf_handle_t buf_handle = sdio_slave_recv_register_buf(&rcv_buffer[i*RX_BUFFER_SIZE]); - esp_err_t err = sdio_slave_recv_load_buf(buf_handle); - TEST_ESP_OK(err); - } - -} - - -static void test_tp_frhost_slave(slave_context_t *ctx, const sdio_test_config_t* config) -{ - esp_err_t err; - init_tx_buffer(); - slave_parepare_recv_buffer(); - - int offset = 0; - for (int i = 0; i < TEST_CNT; i++) { - sdio_slave_buf_handle_t buf_handle; - uint8_t* buf; - size_t rcv_len; - - err = sdio_slave_recv(&buf_handle, &buf, &rcv_len, portMAX_DELAY); - TEST_ESP_OK(err); - - if (config->check_data) { - //compare until all received data are used - int compared_len = 0; - do { - //get the expected master sent data, there may be several segments, so get and compare - //several times - uint8_t* cmp_start; - int seg_len; - get_master_send_data(offset, &cmp_start, &seg_len); - - int cmp_len = MIN(rcv_len-compared_len, seg_len); - - TEST_ASSERT_EQUAL_HEX8_ARRAY(cmp_start, &buf[compared_len], cmp_len); - - compared_len += cmp_len; - offset += cmp_len; - } while (compared_len < rcv_len); - } else { - offset += rcv_len; - } - - err = sdio_slave_recv_load_buf(buf_handle); - TEST_ESP_OK(err); - } - wait_for_finish(ctx); -} - -static void slave_tx_rx_short_data(void) -{ - esp_err_t err; - for (int i = 0; i < 10; i++) { - err = sdio_slave_send_queue(tx_buffer + 4*i, TEST_RESET_DATA_LEN, (void*)i, portMAX_DELAY); - TEST_ESP_OK(err); - } - - for (int i = 0; i < 10; i++) { - uint8_t* addr; - size_t size; - sdio_slave_buf_handle_t recv_handle; - err = sdio_slave_recv(&recv_handle, &addr, &size, portMAX_DELAY); - TEST_ESP_OK(err); - TEST_ASSERT_EQUAL(TEST_RESET_DATA_LEN, size); - TEST_ASSERT_EQUAL_HEX8_ARRAY(tx_buffer+i*8, addr, size); - } - - for (int i = 0; i < 10; i++) { - void* arg; - err = sdio_slave_send_get_finished(&arg, portMAX_DELAY); - TEST_ESP_OK(err); - TEST_ASSERT_EQUAL(i, arg); - } -} - -void test_reset_slave(slave_context_t *context, const sdio_test_config_t* config) -{ - sdio_slave_stop(); - - esp_err_t err = sdio_slave_reset(); - TEST_ESP_OK(err); - - err = sdio_slave_start(); - TEST_ESP_OK(err); - - init_tx_buffer(); - - slave_parepare_recv_buffer(); - - slave_tx_rx_short_data(); - - wait_for_finish(context); -} - -void test_sdio_reset_slave(void) -{ - test_framework_slave(test_reset_slave, &packet_config); -} - - -TEST_CASE_MULTIPLE_DEVICES("sdio interrupt", "[sdio][test_env=sdio_master_slave]", test_sdio_interrupt_master, test_sdio_interrupt_slave); - -TEST_CASE_MULTIPLE_DEVICES("sdio register", "[sdio][test_env=sdio_master_slave]", test_sdio_reg_master, test_sdio_interrupt_slave); - -#if !CONFIG_FREERTOS_UNICORE -TEST_CASE_MULTIPLE_DEVICES("sdio reset", "[sdio][test_env=sdio_master_slave]", test_sdio_reset_master, test_sdio_reset_slave); -#else -//Currently there is weird issue on the runner, when tested with single core config, seems to relate to receiving -TEST_CASE_MULTIPLE_DEVICES("sdio reset", "[sdio][test_env=sdio_master_slave][ignore]", test_sdio_reset_master, test_sdio_reset_slave); -#endif - - -static void test_sdio_frhost_master(const void* pset, void* context) -{ - test_framework_master(test_tp_frhost_master, pset); -} - -static void test_sdio_frhost_slave(const void* pset, void* context) -{ - test_framework_slave(test_tp_frhost_slave, pset); -} - -static void test_sdio_tohost_master(const void* pset, void* context) -{ - test_framework_master(test_tp_tohost_master, pset); -} - -static void test_sdio_tohost_slave(const void* pset, void* context) -{ - test_framework_slave(test_tp_tohost_slave, pset); -} - - -static void null_pre(void** arg) -{ - -} - -static void null_post(void* arg) -{ - -} - -ptest_func_t frhost_master = { - .pre_test = null_pre, - .loop = test_sdio_frhost_master, - .post_test = null_post, -}; - -ptest_func_t frhost_slave = { - .pre_test = null_pre, - .loop = test_sdio_frhost_slave, - .post_test = null_post, -}; - -PARAM_GROUP_DECLARE_TYPE(IO_MODE, sdio_test_config_t, test_cfg_array); - -#if !CONFIG_FREERTOS_UNICORE -TEST_MASTER_SLAVE(SDIO_FRHOST, test_cfg_array, "[sdio][timeout=180][test_env=sdio_master_slave]", &frhost_master, &frhost_slave); -#else -//Currently there is weird issue on the runner, when tested with single core config, seems to relate to receiving -TEST_MASTER_SLAVE(SDIO_FRHOST, test_cfg_array, "[sdio][timeout=180][test_env=sdio_master_slave][ignore]", &frhost_master, &frhost_slave); -#endif - -ptest_func_t tohost_master = { - .pre_test = null_pre, - .loop = test_sdio_tohost_master, - .post_test = null_post, -}; - -ptest_func_t tohost_slave = { - .pre_test = null_pre, - .loop = test_sdio_tohost_slave, - .post_test = null_post, -}; - -TEST_MASTER_SLAVE(SDIO_TOHOST, test_cfg_array, "[sdio][timeout=180][test_env=sdio_master_slave]", &tohost_master, &tohost_slave); - -#endif //SOC_SDMMC_HOST_SUPPORTED && SOC_SDIO_SLAVE_SUPPORTED diff --git a/components/driver/test_apps/sdio/main/test_sdmmc_sdspi_init.cpp b/components/driver/test_apps/sdio/main/test_sdmmc_sdspi_init.cpp deleted file mode 100644 index f34114aaba1..00000000000 --- a/components/driver/test_apps/sdio/main/test_sdmmc_sdspi_init.cpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "soc/soc_caps.h" - -#if SOC_SDMMC_HOST_SUPPORTED -#include "driver/sdmmc_host.h" -#endif - -#include "driver/sdspi_host.h" - - -/** - * Check that C-style designated initializers are valid in C++ file. - */ -static void test_initializers() __attribute__((unused)); - -static void test_initializers() -{ -#if SOC_SDMMC_HOST_SUPPORTED - sdmmc_host_t sdmmc_host = SDMMC_HOST_DEFAULT(); - (void) sdmmc_host; - sdmmc_slot_config_t sdmmc_slot = SDMMC_SLOT_CONFIG_DEFAULT(); - (void) sdmmc_slot; -#endif - sdmmc_host_t sdspi_host = SDSPI_HOST_DEFAULT(); - (void) sdspi_host; - sdspi_device_config_t sdspi_dev = SDSPI_DEVICE_CONFIG_DEFAULT(); - (void) sdspi_dev; -} diff --git a/components/driver/test_apps/sdio/pytest_sdio.py b/components/driver/test_apps/sdio/pytest_sdio.py deleted file mode 100644 index b53618dbf64..00000000000 --- a/components/driver/test_apps/sdio/pytest_sdio.py +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: CC0-1.0 - -import pytest - - -@pytest.mark.esp32 -@pytest.mark.sdio_master_slave -@pytest.mark.parametrize('count', [2,], indirect=True) -def test_sdio_multi_dev(case_tester) -> None: # type: ignore - case_tester.run_all_multi_dev_cases(reset=True, timeout=180) diff --git a/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c b/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c index 44643ffd68f..1ef0f9f656e 100644 --- a/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c +++ b/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c @@ -57,7 +57,7 @@ void test_pxp_deinit_io(void) } #endif -#define TOUCH_READ_INVALID_VAL (SOC_TOUCH_PAD_THRESHOLD_MAX) +#define TOUCH_READ_INVALID_VAL (TOUCH_PAD_THRESHOLD_MAX) #define TOUCH_READ_ERROR_THRESH (0.1) // 10% error #define TOUCH_INTR_THRESHOLD (0.1) #define TOUCH_EXCEED_TIME_MS (1000) diff --git a/components/driver/touch_sensor/esp32/touch_sensor.c b/components/driver/touch_sensor/esp32/touch_sensor.c index 94c5571f583..042c802cc3c 100644 --- a/components/driver/touch_sensor/esp32/touch_sensor.c +++ b/components/driver/touch_sensor/esp32/touch_sensor.c @@ -13,7 +13,6 @@ #include "soc/rtc.h" #include "soc/periph_defs.h" #include "freertos/FreeRTOS.h" -#include "freertos/xtensa_api.h" #include "freertos/semphr.h" #include "esp_timer.h" #include "esp_intr_alloc.h" diff --git a/components/driver/touch_sensor/esp32s2/touch_sensor.c b/components/driver/touch_sensor/esp32s2/touch_sensor.c index f9476c7adc3..ebac4090210 100644 --- a/components/driver/touch_sensor/esp32s2/touch_sensor.c +++ b/components/driver/touch_sensor/esp32s2/touch_sensor.c @@ -11,7 +11,6 @@ #include "sys/lock.h" #include "soc/soc_pins.h" #include "freertos/FreeRTOS.h" -#include "freertos/xtensa_api.h" #include "freertos/semphr.h" #include "freertos/timers.h" #include "esp_intr_alloc.h" diff --git a/components/driver/touch_sensor/esp32s3/touch_sensor.c b/components/driver/touch_sensor/esp32s3/touch_sensor.c index 45959c62807..e1b86db319e 100644 --- a/components/driver/touch_sensor/esp32s3/touch_sensor.c +++ b/components/driver/touch_sensor/esp32s3/touch_sensor.c @@ -11,7 +11,6 @@ #include "sys/lock.h" #include "soc/soc_pins.h" #include "freertos/FreeRTOS.h" -#include "freertos/xtensa_api.h" #include "freertos/semphr.h" #include "freertos/timers.h" #include "esp_intr_alloc.h" diff --git a/components/driver/uart/linker.lf b/components/driver/uart/linker.lf deleted file mode 100644 index eb5d2d6f091..00000000000 --- a/components/driver/uart/linker.lf +++ /dev/null @@ -1,5 +0,0 @@ -[mapping:uart_hal] -archive: libhal.a -entries: - if UART_ISR_IN_IRAM = y: - uart_hal_iram (noflash) diff --git a/components/driver/usb_serial_jtag/usb_serial_jtag.c b/components/driver/usb_serial_jtag/usb_serial_jtag.c index 01df0ae39cb..85ac7b9b92f 100644 --- a/components/driver/usb_serial_jtag/usb_serial_jtag.c +++ b/components/driver/usb_serial_jtag/usb_serial_jtag.c @@ -6,6 +6,7 @@ #include #include +#include #include "esp_log.h" #include "hal/usb_serial_jtag_ll.h" #include "hal/usb_phy_ll.h" @@ -15,7 +16,20 @@ #include "esp_intr_alloc.h" #include "driver/usb_serial_jtag.h" #include "soc/periph_defs.h" +#include "soc/soc_caps.h" #include "esp_check.h" +#include "esp_private/periph_ctrl.h" + +#if !SOC_RCC_IS_INDEPENDENT +#define USJ_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define USJ_RCC_ATOMIC() +#endif + +typedef enum { + FIFO_IDLE = 0, /*!< Indicates the fifo is in idle state */ + FIFO_BUSY = 1, /*!< Indicates the fifo is in busy state */ +} fifo_status_t; // The hardware buffer max size is 64 #define USB_SER_JTAG_ENDP_SIZE (64) @@ -23,6 +37,8 @@ typedef struct{ intr_handle_t intr_handle; /*!< USB-SERIAL-JTAG interrupt handler */ + portMUX_TYPE spinlock; /*!< Spinlock for usb_serial_jtag */ + _Atomic fifo_status_t fifo_status; /*!< Record the status of fifo */ // RX parameters RingbufHandle_t rx_ring_buf; /*!< RX ring buffer handler */ @@ -59,7 +75,7 @@ static void usb_serial_jtag_isr_handler_default(void *arg) { // If the hardware fifo is available, write in it. Otherwise, do nothing. if (usb_serial_jtag_ll_txfifo_writable() == 1) { // We disable the interrupt here so that the interrupt won't be triggered if there is no data to send. - usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + size_t queued_size; uint8_t *queued_buff = NULL; bool is_stashed_data = false; @@ -83,10 +99,13 @@ static void usb_serial_jtag_isr_handler_default(void *arg) { // On ringbuffer wrap-around the size can be 0 even though the buffer returned is not NULL if (queued_size > 0) { + portENTER_CRITICAL_ISR(&p_usb_serial_jtag_obj->spinlock); + atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_BUSY); uint32_t sent_size = usb_serial_jtag_write_and_flush(queued_buff, queued_size); + portEXIT_CRITICAL_ISR(&p_usb_serial_jtag_obj->spinlock); if (sent_size < queued_size) { - // Not all bytes could be sent at once, stash the unwritten bytes in a tx buffer + // Not all bytes could be sent at once; stash the unwritten bytes in a tx buffer // stash_size will not larger than USB_SER_JTAG_ENDP_SIZE because queued_size is got from xRingbufferReceiveUpToFromISR size_t stash_size = queued_size - sent_size; memcpy(p_usb_serial_jtag_obj->tx_data_buf, &queued_buff[sent_size], stash_size); @@ -100,9 +119,17 @@ static void usb_serial_jtag_isr_handler_default(void *arg) { if (is_stashed_data == false) { vRingbufferReturnItemFromISR(p_usb_serial_jtag_obj->tx_ring_buf, queued_buff, &xTaskWoken); } - usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } else { + // The last transmit may have sent a full EP worth of data. The host will interpret + // this as a transaction that hasn't finished yet and keep the data in its internal + // buffers rather than releasing it to the program listening on the CDC serial port. + // We need to flush again in order to send a 0-byte packet that ends the transaction. + usb_serial_jtag_ll_txfifo_flush(); + // Note that since this doesn't re-enable USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY, the + // flush will not by itself cause this ISR to be called again. } } else { + atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_IDLE); usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); } } @@ -131,6 +158,7 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se p_usb_serial_jtag_obj->rx_buf_size = usb_serial_jtag_config->rx_buffer_size; p_usb_serial_jtag_obj->tx_buf_size = usb_serial_jtag_config->tx_buffer_size; p_usb_serial_jtag_obj->tx_stash_cnt = 0; + p_usb_serial_jtag_obj->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; if (p_usb_serial_jtag_obj == NULL) { ESP_LOGE(USB_SERIAL_JTAG_TAG, "memory allocate error"); err = ESP_ERR_NO_MEM; @@ -151,6 +179,12 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se goto _exit; } + // Enable USB-Serial-JTAG peripheral module clock + USJ_RCC_ATOMIC() { + usb_serial_jtag_ll_enable_bus_clock(true); + } + atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_IDLE); + // Configure PHY usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG); @@ -199,10 +233,22 @@ int usb_serial_jtag_write_bytes(const void* src, size_t size, TickType_t ticks_t ESP_RETURN_ON_FALSE(src != NULL, ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "Invalid buffer pointer."); ESP_RETURN_ON_FALSE(p_usb_serial_jtag_obj != NULL, ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "The driver hasn't been initialized"); + size_t sent_data = 0; + BaseType_t result = pdTRUE; const uint8_t *buff = (const uint8_t *)src; + if (p_usb_serial_jtag_obj->fifo_status == FIFO_IDLE) { + portENTER_CRITICAL(&p_usb_serial_jtag_obj->spinlock); + atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_BUSY); + sent_data = usb_serial_jtag_write_and_flush(src, size); + portEXIT_CRITICAL(&p_usb_serial_jtag_obj->spinlock); + } + // Blocking method, Sending data to ringbuffer, and handle the data in ISR. - BaseType_t result = xRingbufferSend(p_usb_serial_jtag_obj->tx_ring_buf, (void*) (buff), size, ticks_to_wait); - // Now trigger the ISR to read data from the ring buffer. + if (size - sent_data > 0) { + result = xRingbufferSend(p_usb_serial_jtag_obj->tx_ring_buf, (void*) (buff+sent_data), size-sent_data, ticks_to_wait); + } else { + atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_IDLE); + } usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); return (result == pdFALSE) ? 0 : size; } @@ -214,6 +260,7 @@ esp_err_t usb_serial_jtag_driver_uninstall(void) return ESP_OK; } + /* Not disable the module clock and usb_pad_enable here since the USJ stdout might still depends on it. */ //Disable tx/rx interrupt. usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT); esp_intr_free(p_usb_serial_jtag_obj->intr_handle); diff --git a/components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c b/components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c index 238069e20a2..44a9f37edab 100644 --- a/components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c +++ b/components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c @@ -68,7 +68,7 @@ static void IRAM_ATTR usb_serial_jtag_sof_tick_hook(void) } } -ESP_SYSTEM_INIT_FN(usb_serial_jtag_conn_status_init, BIT(0), 230) +ESP_SYSTEM_INIT_FN(usb_serial_jtag_conn_status_init, SECONDARY, BIT(0), 230) { #if CONFIG_USJ_NO_AUTO_LS_ON_CONNECTION ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "usb_serial_jtag", &s_usb_serial_jtag_pm_lock), diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index 80db72a608b..fa075f91ace 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -235,7 +235,7 @@ esp_err_t esp_efuse_write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint3 /** * @brief Return efuse coding scheme for blocks. * - * Note: The coding scheme is applicable only to 1, 2 and 3 blocks. For 0 block, the coding scheme is always ``NONE``. + * @note The coding scheme is applicable only to 1, 2 and 3 blocks. For 0 block, the coding scheme is always ``NONE``. * * @param[in] blk Block number of eFuse. * @return Return efuse coding scheme for blocks @@ -708,6 +708,12 @@ esp_err_t esp_efuse_set_write_protect_of_digest_revoke(unsigned num_digest); * * The burn of a key, protection bits, and a purpose happens in batch mode. * + * @note This API also enables the read protection efuse bit for certain key blocks like XTS-AES, HMAC, ECDSA etc. + * This ensures that the key is only accessible to hardware peripheral. + * + * @note For SoC's with capability `SOC_EFUSE_ECDSA_USE_HARDWARE_K` (e.g., ESP32-H2), this API writes an additional + * efuse bit for ECDSA key purpose to enforce hardware TRNG generated k mode in the peripheral. + * * @param[in] block Block to read purpose for. Must be in range EFUSE_BLK_KEY0 to EFUSE_BLK_KEY_MAX. Key block must be unused (esp_efuse_key_block_unused). * @param[in] purpose Purpose to set for this key. Purpose must be already unset. * @param[in] key Pointer to data to write. @@ -727,6 +733,12 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo * * The burn of keys, protection bits, and purposes happens in batch mode. * + * @note This API also enables the read protection efuse bit for certain key blocks like XTS-AES, HMAC, ECDSA etc. + * This ensures that the key is only accessible to hardware peripheral. + * + * @note For SoC's with capability `SOC_EFUSE_ECDSA_USE_HARDWARE_K` (e.g., ESP32-H2), this API writes an additional + * efuse bit for ECDSA key purpose to enforce hardware TRNG generated k mode in the peripheral. + * * @param[in] purposes Array of purposes (purpose[number_of_keys]). * @param[in] keys Array of keys (uint8_t keys[number_of_keys][32]). Each key is 32 bytes long. * @param[in] number_of_keys The number of keys to write (up to 6 keys). diff --git a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c index 179966e7fd0..0d48b1fd4e3 100644 --- a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c +++ b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -315,6 +315,12 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP) { ESP_EFUSE_CHK(esp_efuse_set_key_dis_read(block)); } +#if SOC_EFUSE_ECDSA_USE_HARDWARE_K + if (purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY) { + // Permanently enable the hardware TRNG supplied k mode (most secure mode) + ESP_EFUSE_CHK(esp_efuse_write_field_bit(ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K)); + } +#endif ESP_EFUSE_CHK(esp_efuse_set_key_purpose(block, purpose)); ESP_EFUSE_CHK(esp_efuse_set_keypurpose_dis_write(block)); return esp_efuse_batch_write_commit(); diff --git a/components/esp-tls/Kconfig b/components/esp-tls/Kconfig index 32e1e0db832..297a357b6df 100644 --- a/components/esp-tls/Kconfig +++ b/components/esp-tls/Kconfig @@ -21,7 +21,7 @@ menu "ESP-TLS" select ATCA_MBEDTLS_ECDSA_VERIFY help Enable use of Secure Element for ESP-TLS, this enables internal support for - ATECC608A peripheral on ESPWROOM32SE, which can be used for TLS connection. + ATECC608A peripheral, which can be used for TLS connection. config ESP_TLS_USE_DS_PERIPHERAL bool "Use Digital Signature (DS) Peripheral with ESP-TLS" diff --git a/components/esp-tls/esp_tls.c b/components/esp-tls/esp_tls.c index 76265587e97..c56bb75c658 100644 --- a/components/esp-tls/esp_tls.c +++ b/components/esp-tls/esp_tls.c @@ -24,9 +24,16 @@ #include #include #include -#include #include +#ifdef __linux__ +#include +#endif + +#ifdef __APPLE__ +#include +#endif + typedef struct in_addr ip_addr_t; typedef struct in6_addr ip6_addr_t; #define ipaddr_ntoa(ipaddr) inet_ntoa(*ipaddr) @@ -278,6 +285,7 @@ static esp_err_t esp_tls_set_socket_options(int fd, const esp_tls_cfg_t *cfg) ESP_LOGE(TAG, "Fail to setsockopt SO_KEEPALIVE"); return ESP_ERR_ESP_TLS_SOCKET_SETOPT_FAILED; } +#ifndef __APPLE__ if (setsockopt(fd, IPPROTO_TCP, TCP_KEEPIDLE, &keep_alive_idle, sizeof(keep_alive_idle)) != 0) { ESP_LOGE(TAG, "Fail to setsockopt TCP_KEEPIDLE"); return ESP_ERR_ESP_TLS_SOCKET_SETOPT_FAILED; @@ -290,11 +298,22 @@ static esp_err_t esp_tls_set_socket_options(int fd, const esp_tls_cfg_t *cfg) ESP_LOGE(TAG, "Fail to setsockopt TCP_KEEPCNT"); return ESP_ERR_ESP_TLS_SOCKET_SETOPT_FAILED; } +#else // __APPLE__ + if (setsockopt(fd, IPPROTO_TCP, TCP_KEEPALIVE, &keep_alive_idle, sizeof(keep_alive_idle)) != 0) { + ESP_LOGE(TAG, "Fail to setsockopt TCP_KEEPALIVE"); + return ESP_ERR_ESP_TLS_SOCKET_SETOPT_FAILED; + } +#endif // __APPLE__ } if (cfg->if_name) { if (cfg->if_name->ifr_name[0] != 0) { ESP_LOGD(TAG, "Bind [sock=%d] to interface %s", fd, cfg->if_name->ifr_name); +#ifndef __APPLE__ if (setsockopt(fd, SOL_SOCKET, SO_BINDTODEVICE, cfg->if_name, sizeof(struct ifreq)) != 0) { +#else + int idx = if_nametoindex(cfg->if_name->ifr_name); + if (setsockopt(fd, IPPROTO_IP, IP_BOUND_IF, &idx, sizeof(idx)) != 0) { +#endif ESP_LOGE(TAG, "Bind [sock=%d] to interface %s fail", fd, cfg->if_name->ifr_name); return ESP_ERR_ESP_TLS_SOCKET_SETOPT_FAILED; } diff --git a/components/esp-tls/esp_tls.h b/components/esp-tls/esp_tls.h index 32eccacb5d8..b4a90b8f4c5 100644 --- a/components/esp-tls/esp_tls.h +++ b/components/esp-tls/esp_tls.h @@ -170,7 +170,7 @@ typedef struct esp_tls_cfg { blocking mode after tls session is established */ bool use_secure_element; /*!< Enable this option to use secure element or - atecc608a chip ( Integrated with ESP32-WROOM-32SE ) */ + atecc608a chip */ int timeout_ms; /*!< Network timeout in milliseconds. Note: If this value is not set, by default the timeout is @@ -238,6 +238,10 @@ typedef struct esp_tls_server_session_ticket_ctx { * or a specific MBEDTLS_ERR_XXX code, which will cause the handhsake to abort */ typedef mbedtls_ssl_hs_cb_t esp_tls_handshake_callback; +#else +// When CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not defined, +// the following typedef is only kept for compatibility reasons, not to be used. +typedef void* esp_tls_handshake_callback; #endif /** @@ -299,7 +303,7 @@ typedef struct esp_tls_cfg_server { uint8_t ecdsa_key_efuse_blk; /*!< The efuse block where ECDSA key is stored */ bool use_secure_element; /*!< Enable this option to use secure element or - atecc608a chip ( Integrated with ESP32-WROOM-32SE ) */ + atecc608a chip */ #if defined(CONFIG_ESP_TLS_SERVER_SESSION_TICKETS) diff --git a/components/esp-tls/esp_tls_errors.h b/components/esp-tls/esp_tls_errors.h index d87adeb43b1..6606562671c 100644 --- a/components/esp-tls/esp_tls_errors.h +++ b/components/esp-tls/esp_tls_errors.h @@ -10,8 +10,12 @@ #include "esp_err.h" #ifdef CONFIG_ESP_TLS_USING_MBEDTLS #include "mbedtls/error.h" +#include "mbedtls/ssl.h" +#elif CONFIG_ESP_TLS_USING_WOLFSSL +#include "wolfssl/wolfcrypt/settings.h" +#include "wolfssl/ssl.h" #endif -/* For wolfSSL, errors are included through ssl.h which is included by default by esp_tls.h */ + #ifdef __cplusplus extern "C" { diff --git a/components/esp-tls/test_apps/main/app_main.c b/components/esp-tls/test_apps/main/app_main.c index 401a39d7457..d84480083fb 100644 --- a/components/esp-tls/test_apps/main/app_main.c +++ b/components/esp-tls/test_apps/main/app_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "unity.h" +#include "mbedtls/aes.h" #include "memory_checks.h" #include "soc/soc_caps.h" #if SOC_SHA_SUPPORT_PARALLEL_ENG @@ -26,13 +27,21 @@ /* setUp runs before every test */ void setUp(void) { - // Execute esp_sha operation to allocate internal SHA semaphore memory - // which is considered as leaked otherwise + // Execute esp_sha operation to allocate internal SHA semaphore (in case of ESP32) + // and initial DMA setup memory which is considered as leaked otherwise #if SOC_SHA_SUPPORTED const uint8_t input_buffer[64] = {0}; uint8_t output_buffer[64]; esp_sha(SHA_TYPE, input_buffer, sizeof(input_buffer), output_buffer); #endif // SOC_SHA_SUPPORTED + + // Execute mbedtls_aes_init operation to allocate AES interrupt + // allocation memory which is considered as leak otherwise +#if SOC_AES_SUPPORTED + mbedtls_aes_context ctx; + mbedtls_aes_init(&ctx); +#endif // SOC_AES_SUPPORTED + test_utils_record_free_mem(); TEST_ESP_OK(test_utils_set_leak_level(0, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL)); TEST_ESP_OK(test_utils_set_leak_level(0, ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_GENERAL)); diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c index d954e880eaf..71d405ccb81 100644 --- a/components/esp_adc/adc_continuous.c +++ b/components/esp_adc/adc_continuous.c @@ -196,13 +196,14 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi uint32_t dma_chan = 0; spi_success = spicommon_periph_claim(SPI3_HOST, "adc"); - ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &dma_chan, &dma_chan); + ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &adc_ctx->spi_dma_ctx); if (ret == ESP_OK) { adc_ctx->spi_host = SPI3_HOST; } if (!spi_success || (adc_ctx->spi_host != SPI3_HOST)) { goto cleanup; } + dma_chan = adc_ctx->spi_dma_ctx->rx_dma_chan.chan_id; ret = esp_intr_alloc(spicommon_irqdma_source_for_host(adc_ctx->spi_host), ESP_INTR_FLAG_IRAM, adc_dma_intr_handler, (void *)adc_ctx, &adc_ctx->dma_intr_hdl); @@ -359,6 +360,9 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle) ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised"); ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already"); + //reset ADC digital part to reset ADC sampling EOF counter + periph_module_reset(PERIPH_SARADC_MODULE); + if (handle->pm_lock) { ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(handle->pm_lock), ADC_TAG, "acquire pm_lock failed"); } @@ -491,7 +495,7 @@ esp_err_t adc_continuous_deinit(adc_continuous_handle_t handle) gdma_del_channel(handle->rx_dma_channel); #elif CONFIG_IDF_TARGET_ESP32S2 esp_intr_free(handle->dma_intr_hdl); - spicommon_dma_chan_free(handle->spi_host); + spicommon_dma_chan_free(handle->spi_dma_ctx); spicommon_periph_free(handle->spi_host); #elif CONFIG_IDF_TARGET_ESP32 esp_intr_free(handle->dma_intr_hdl); diff --git a/components/esp_adc/adc_continuous_internal.h b/components/esp_adc/adc_continuous_internal.h index e78787ba975..64d6ad2a5fe 100644 --- a/components/esp_adc/adc_continuous_internal.h +++ b/components/esp_adc/adc_continuous_internal.h @@ -19,6 +19,7 @@ #include "esp_private/gdma.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "hal/spi_types.h" +#include "esp_private/spi_common_internal.h" #elif CONFIG_IDF_TARGET_ESP32 #include "driver/i2s_types.h" #endif @@ -77,6 +78,7 @@ struct adc_continuous_ctx_t { gdma_channel_handle_t rx_dma_channel; //dma rx channel handle #elif CONFIG_IDF_TARGET_ESP32S2 spi_host_device_t spi_host; //ADC uses this SPI DMA + spi_dma_ctx_t *spi_dma_ctx; //spi_dma context #elif CONFIG_IDF_TARGET_ESP32 i2s_port_t i2s_host; //ADC uses this I2S DMA #endif diff --git a/components/esp_adc/esp32c5/include/.gitkeep b/components/esp_adc/esp32c5/include/.gitkeep new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml index ab0728836d8..9c6297a2ffd 100644 --- a/components/esp_adc/test_apps/.build-test-rules.yml +++ b/components/esp_adc/test_apps/.build-test-rules.yml @@ -7,7 +7,6 @@ components/esp_adc/test_apps/adc: depends_components: - esp_adc - esp_driver_gpio + - esp_driver_i2s # ADC continuous driver relies on I2S on ESP32 - efuse - depends_filepatterns: - - components/driver/spi/**/* # ADC continuous driver relies on SPI on ESP32S2 - - components/driver/i2s/**/* # ADC continuous driver relies on I2S on ESP32 + - esp_driver_spi # ADC continuous driver relies on SPI on ESP32S2 diff --git a/components/esp_adc/test_apps/adc/main/test_adc.c b/components/esp_adc/test_apps/adc/main/test_adc.c index f568dde6c72..d1d2789e4cc 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc.c +++ b/components/esp_adc/test_apps/adc/main/test_adc.c @@ -286,14 +286,14 @@ static void s_adc_oneshot_with_sleep(adc_unit_t unit_id, adc_channel_t channel) #define ADC2_SLEEP_TEST_CHAN ADC_CHANNEL_0 #endif -TEST_CASE("test ADC1 Single Read with Light Sleep", "[adc][manul][ignore]") +TEST_CASE("test ADC1 Single Read with Light Sleep", "[adc]") { s_adc_oneshot_with_sleep(ADC_UNIT_1, ADC1_SLEEP_TEST_CHAN); } #if (SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3 //ESP32C3 ADC2 oneshot mode is not supported anymore -TEST_CASE("test ADC2 Single Read with Light Sleep", "[adc][manul][ignore]") +TEST_CASE("test ADC2 Single Read with Light Sleep", "[adc]") { s_adc_oneshot_with_sleep(ADC_UNIT_2, ADC2_SLEEP_TEST_CHAN); } diff --git a/components/esp_adc/test_apps/adc/main/test_adc_driver.c b/components/esp_adc/test_apps/adc/main/test_adc_driver.c index 913820bd771..00a210f295c 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc_driver.c +++ b/components/esp_adc/test_apps/adc/main/test_adc_driver.c @@ -264,6 +264,57 @@ TEST_CASE("ADC continuous flush internal pool", "[adc_continuous][mannual][ignor TEST_ESP_OK(adc_continuous_deinit(handle)); } +#if !CONFIG_IDF_TARGET_ESP32C3 //TODO: DIG-270 + +#define ADC_RESTART_TEST_SIZE 4096 +#define ADC_READ_TEST_COUNT 10 + +TEST_CASE("ADC continuous test after restarting", "[adc_continuous]") +{ + adc_continuous_handle_t handle = NULL; + adc_continuous_handle_cfg_t adc_config = { + .max_store_buf_size = ADC_RESTART_TEST_SIZE, + .conv_frame_size = ADC_RESTART_TEST_SIZE, + }; + TEST_ESP_OK(adc_continuous_new_handle(&adc_config, &handle)); + + adc_continuous_config_t dig_cfg = { + .sample_freq_hz = 50 * 1000, + .conv_mode = ADC_CONV_SINGLE_UNIT_1, + .format = ADC_DRIVER_TEST_OUTPUT_TYPE, + }; + adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0}; + adc_pattern[0].atten = ADC_ATTEN_DB_12; + adc_pattern[0].channel = ADC1_TEST_CHAN0; + adc_pattern[0].unit = ADC_UNIT_1; + adc_pattern[0].bit_width = SOC_ADC_DIGI_MAX_BITWIDTH; + dig_cfg.adc_pattern = adc_pattern; + dig_cfg.pattern_num = 1; + TEST_ESP_OK(adc_continuous_config(handle, &dig_cfg)); + + uint8_t* result = malloc(ADC_RESTART_TEST_SIZE); + TEST_ASSERT(result); + + test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 0); + + for (int i = 0; i < ADC_READ_TEST_COUNT; i++) { + uint32_t ret_num = 0; + TEST_ESP_OK(adc_continuous_start(handle)); + TEST_ESP_OK(adc_continuous_read(handle, result, ADC_RESTART_TEST_SIZE, &ret_num, ADC_MAX_DELAY)); + TEST_ASSERT_EQUAL(ADC_RESTART_TEST_SIZE, ret_num); + for (int i = 0; i < ret_num; i += SOC_ADC_DIGI_RESULT_BYTES) { + adc_digi_output_data_t *p = (void*)&result[i]; + uint32_t chan_num = ADC_DRIVER_TEST_GET_CHANNEL(p); + TEST_ASSERT(chan_num < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1)); + } + TEST_ESP_OK(adc_continuous_stop(handle)); + } + + TEST_ESP_OK(adc_continuous_deinit(handle)); + free(result); +} +#endif //!CONFIG_IDF_TARGET_ESP32C3 + #if SOC_ADC_DIG_IIR_FILTER_SUPPORTED TEST_CASE("ADC filter exhausted allocation", "[adc_continuous]") { diff --git a/components/esp_app_format/CMakeLists.txt b/components/esp_app_format/CMakeLists.txt index 05d7c9ce3c8..c25ced06f29 100644 --- a/components/esp_app_format/CMakeLists.txt +++ b/components/esp_app_format/CMakeLists.txt @@ -18,7 +18,7 @@ if(NOT BOOTLOADER_BUILD) target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_app_desc") if(CONFIG_APP_PROJECT_VER_FROM_CONFIG) - # Ignore current PROJECT_VER (which was set in __project_get_revision()). + # Ignore current PROJECT_VER (which was set in project.cmake) # Gets the version from the CONFIG_APP_PROJECT_VER. idf_build_set_property(PROJECT_VER "${CONFIG_APP_PROJECT_VER}") endif() diff --git a/components/esp_coex/include/esp_coex_i154.h b/components/esp_coex/include/esp_coex_i154.h index 8bd181eeb5c..942de356139 100644 --- a/components/esp_coex/include/esp_coex_i154.h +++ b/components/esp_coex/include/esp_coex_i154.h @@ -17,6 +17,7 @@ typedef enum { void esp_coex_ieee802154_txrx_pti_set(ieee802154_coex_event_t event); void esp_coex_ieee802154_ack_pti_set(ieee802154_coex_event_t event); +void esp_coex_ieee802154_coex_break_notify(void); #endif #endif diff --git a/components/esp_coex/include/private/esp_coexist_adapter.h b/components/esp_coex/include/private/esp_coexist_adapter.h index fde83d1111d..539fd3ec632 100644 --- a/components/esp_coex/include/private/esp_coexist_adapter.h +++ b/components/esp_coex/include/private/esp_coexist_adapter.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -51,6 +51,12 @@ typedef struct { extern coex_adapter_funcs_t g_coex_adapter_funcs; +typedef struct { + uint8_t major; + uint8_t minor; + uint8_t patch; +} coex_version_t; + #ifdef __cplusplus } #endif diff --git a/components/esp_coex/include/private/esp_coexist_internal.h b/components/esp_coex/include/private/esp_coexist_internal.h index 15fe35cc1ba..7aee0c05333 100644 --- a/components/esp_coex/include/private/esp_coexist_internal.h +++ b/components/esp_coex/include/private/esp_coexist_internal.h @@ -75,6 +75,14 @@ void coex_disable(void); */ const char *coex_version_get(void); +/** + * @brief Get software coexist version value + * extern function for internal use. + * @param ptr_version : points to version structure + * @return : ESP_OK - success, other - failed + */ +esp_err_t coex_version_get_value(coex_version_t* ptr_version); + /** * @brief Coexist performance preference set from libbt.a * extern function for internal use. diff --git a/components/esp_coex/lib b/components/esp_coex/lib index 68cbbdb45cd..667353cc7a0 160000 --- a/components/esp_coex/lib +++ b/components/esp_coex/lib @@ -1 +1 @@ -Subproject commit 68cbbdb45cdc8c88ffbfc2587a4e7af020695e56 +Subproject commit 667353cc7a0520924135ce50b798f495cd308e47 diff --git a/components/esp_coex/linker.lf b/components/esp_coex/linker.lf index 89f1fd620db..10d99add7eb 100644 --- a/components/esp_coex/linker.lf +++ b/components/esp_coex/linker.lf @@ -1,5 +1,23 @@ +[sections:coex_iram] +entries: + .coexiram+ + +[sections:coex_sleep_iram] +entries: + .coexsleepiram+ + +[scheme:coex_iram_config] +entries: + if ESP_WIFI_IRAM_OPT = y: + coex_iram -> iram0_text + else: + coex_iram -> flash_text + if ESP_WIFI_SLP_IRAM_OPT = y: + coex_sleep_iram -> iram0_text + else: + coex_sleep_iram -> flash_text + [mapping:coexist] archive: libcoexist.a entries: - if ESP_WIFI_SLP_IRAM_OPT = y: - * (wifi_slp_iram) + * (coex_iram_config) diff --git a/components/esp_common/include/esp_err.h b/components/esp_common/include/esp_err.h index 30789475a5b..039dc5552a0 100644 --- a/components/esp_common/include/esp_err.h +++ b/components/esp_common/include/esp_err.h @@ -79,7 +79,6 @@ const char *esp_err_to_name_r(esp_err_t code, char *buf, size_t buflen); /** @cond */ void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression) __attribute__((__noreturn__)); -/** @cond */ void _esp_error_check_failed_without_abort(esp_err_t rc, const char *file, int line, const char *function, const char *expression); #ifndef __ASSERT_FUNC diff --git a/components/esp_common/src/esp_err_to_name.c b/components/esp_common/src/esp_err_to_name.c index 7aca0e17e4d..b99fbd6d3e3 100644 --- a/components/esp_common/src/esp_err_to_name.c +++ b/components/esp_common/src/esp_err_to_name.c @@ -416,6 +416,9 @@ static const esp_err_msg_t esp_err_msg_table[] = { # endif # ifdef ESP_ERR_WIFI_DISCARD ERR_TBL_IT(ESP_ERR_WIFI_DISCARD), /* 12315 0x301b Discard frame */ +# endif +# ifdef ESP_ERR_WIFI_ROC_IN_PROGRESS + ERR_TBL_IT(ESP_ERR_WIFI_ROC_IN_PROGRESS), /* 12316 0x301c ROC op is in progress */ # endif // components/wpa_supplicant/esp_supplicant/include/esp_wps.h # ifdef ESP_ERR_WIFI_REGISTRAR @@ -454,6 +457,9 @@ static const esp_err_msg_t esp_err_msg_table[] = { # endif # ifdef ESP_ERR_ESPNOW_IF ERR_TBL_IT(ESP_ERR_ESPNOW_IF), /* 12396 0x306c Interface error */ +# endif +# ifdef ESP_ERR_ESPNOW_CHAN + ERR_TBL_IT(ESP_ERR_ESPNOW_CHAN), /* 12397 0x306d Channel error */ # endif // components/wpa_supplicant/esp_supplicant/include/esp_dpp.h # ifdef ESP_ERR_DPP_FAILURE @@ -464,6 +470,9 @@ static const esp_err_msg_t esp_err_msg_table[] = { # endif # ifdef ESP_ERR_DPP_INVALID_ATTR ERR_TBL_IT(ESP_ERR_DPP_INVALID_ATTR), /* 12441 0x3099 Encountered invalid DPP Attribute */ +# endif +# ifdef ESP_ERR_DPP_AUTH_TIMEOUT + ERR_TBL_IT(ESP_ERR_DPP_AUTH_TIMEOUT), /* 12442 0x309a DPP Auth response was not recieved in time */ # endif // components/esp_common/include/esp_err.h # ifdef ESP_ERR_MESH_BASE diff --git a/components/esp_driver_ana_cmpr/CMakeLists.txt b/components/esp_driver_ana_cmpr/CMakeLists.txt new file mode 100644 index 00000000000..5fd665a33d7 --- /dev/null +++ b/components/esp_driver_ana_cmpr/CMakeLists.txt @@ -0,0 +1,15 @@ +set(srcs) + +# Analog comparator related source files +if(CONFIG_SOC_ANA_CMPR_SUPPORTED) + list(APPEND srcs "ana_cmpr.c") + if(CONFIG_SOC_ANA_CMPR_SUPPORT_ETM) + list(APPEND srcs "ana_cmpr_etm.c") + endif() +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS "include" + PRIV_REQUIRES esp_pm esp_driver_gpio + LDFRAGMENTS "linker.lf" + ) diff --git a/components/esp_driver_ana_cmpr/Kconfig b/components/esp_driver_ana_cmpr/Kconfig new file mode 100644 index 00000000000..98a8c96e557 --- /dev/null +++ b/components/esp_driver_ana_cmpr/Kconfig @@ -0,0 +1,24 @@ +menu "ESP-Driver:Analog Comparator Configurations" + depends on SOC_ANA_CMPR_SUPPORTED + config ANA_CMPR_ISR_IRAM_SAFE + bool "Analog comparator ISR IRAM-Safe" + default n + help + Ensure the Analog Comparator interrupt is IRAM-Safe by allowing the interrupt handler to be + executable when the cache is disabled (e.g. SPI Flash write). + + config ANA_CMPR_CTRL_FUNC_IN_IRAM + bool "Place Analog Comparator control functions into IRAM" + default n + help + Place Analog Comparator control functions (like ana_cmpr_set_internal_reference) into IRAM, + so that these functions can be IRAM-safe and able to be called in an IRAM interrupt context. + Enabling this option can improve driver performance as well. + + config ANA_CMPR_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for Analog Comparator driver. + Note that, this option only controls the Analog Comparator driver log, won't affect other drivers. +endmenu # Analog Comparator Configuration diff --git a/components/driver/analog_comparator/ana_cmpr.c b/components/esp_driver_ana_cmpr/ana_cmpr.c similarity index 97% rename from components/driver/analog_comparator/ana_cmpr.c rename to components/esp_driver_ana_cmpr/ana_cmpr.c index f417c2a02a3..2f887286ac3 100644 --- a/components/driver/analog_comparator/ana_cmpr.c +++ b/components/esp_driver_ana_cmpr/ana_cmpr.c @@ -63,7 +63,7 @@ static const char *TAG = "ana_cmpr"; /* Global static object of the Analog Comparator unit */ static ana_cmpr_handle_t s_ana_cmpr[SOC_ANA_CMPR_NUM] = { - [0 ... (SOC_ANA_CMPR_NUM - 1)] = NULL, + [0 ...(SOC_ANA_CMPR_NUM - 1)] = NULL, }; /* Global spin lock */ @@ -149,9 +149,9 @@ esp_err_t ana_cmpr_new_unit(const ana_cmpr_config_t *config, ana_cmpr_handle_t * /* Analog clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well */ ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &s_ana_cmpr[unit]->src_clk_freq_hz), - err, TAG, "get source clock frequency failed"); + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, + &s_ana_cmpr[unit]->src_clk_freq_hz), + err, TAG, "get source clock frequency failed"); ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(config->clk_src)), err, TAG, "potential clock source conflicts from other IOMUX peripherals"); @@ -298,7 +298,7 @@ esp_err_t ana_cmpr_register_event_callbacks(ana_cmpr_handle_t cmpr, const ana_cm intr_flags |= ESP_INTR_FLAG_SHARED; #endif // SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(ana_cmpr_periph[cmpr->unit].intr_src, intr_flags, (uint32_t)analog_cmpr_ll_get_intr_status_reg(cmpr->dev), - cmpr->intr_mask, s_ana_cmpr_default_intr_handler, cmpr, &cmpr->intr_handle), TAG, "allocate interrupt failed"); + cmpr->intr_mask, s_ana_cmpr_default_intr_handler, cmpr, &cmpr->intr_handle), TAG, "allocate interrupt failed"); } /* Save the callback group */ diff --git a/components/driver/analog_comparator/ana_cmpr_etm.c b/components/esp_driver_ana_cmpr/ana_cmpr_etm.c similarity index 100% rename from components/driver/analog_comparator/ana_cmpr_etm.c rename to components/esp_driver_ana_cmpr/ana_cmpr_etm.c diff --git a/components/driver/analog_comparator/ana_cmpr_private.h b/components/esp_driver_ana_cmpr/ana_cmpr_private.h similarity index 100% rename from components/driver/analog_comparator/ana_cmpr_private.h rename to components/esp_driver_ana_cmpr/ana_cmpr_private.h diff --git a/components/driver/analog_comparator/include/driver/ana_cmpr.h b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr.h similarity index 98% rename from components/driver/analog_comparator/include/driver/ana_cmpr.h rename to components/esp_driver_ana_cmpr/include/driver/ana_cmpr.h index d10b1e0a74f..0fbb0839275 100644 --- a/components/driver/analog_comparator/include/driver/ana_cmpr.h +++ b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr.h @@ -31,7 +31,7 @@ typedef struct { int intr_priority; /*!< The interrupt priority, range 0~7, if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3) * otherwise the larger the higher, 7 is NMI */ struct { - uint32_t io_loop_back:1; /*!< Enable this field when the other signals that output on the comparision pins are supposed to be fed back. + uint32_t io_loop_back: 1; /*!< Enable this field when the other signals that output on the comparision pins are supposed to be fed back. * Normally used for debug/test scenario */ } flags; /*!< Analog comparator driver flags */ } ana_cmpr_config_t; diff --git a/components/driver/analog_comparator/include/driver/ana_cmpr_etm.h b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_etm.h similarity index 100% rename from components/driver/analog_comparator/include/driver/ana_cmpr_etm.h rename to components/esp_driver_ana_cmpr/include/driver/ana_cmpr_etm.h diff --git a/components/driver/analog_comparator/include/driver/ana_cmpr_types.h b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h similarity index 96% rename from components/driver/analog_comparator/include/driver/ana_cmpr_types.h rename to components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h index 97850926209..19747433630 100644 --- a/components/driver/analog_comparator/include/driver/ana_cmpr_types.h +++ b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h @@ -105,7 +105,7 @@ typedef struct { * * @return Whether a high priority task has been waken up by this callback function */ -typedef bool (*ana_cmpr_cross_cb_t) (ana_cmpr_handle_t cmpr, const ana_cmpr_cross_event_data_t *edata, void *user_ctx); +typedef bool (*ana_cmpr_cross_cb_t)(ana_cmpr_handle_t cmpr, const ana_cmpr_cross_event_data_t *edata, void *user_ctx); #ifdef __cplusplus } diff --git a/components/esp_driver_ana_cmpr/linker.lf b/components/esp_driver_ana_cmpr/linker.lf new file mode 100644 index 00000000000..c48d1eaa6e4 --- /dev/null +++ b/components/esp_driver_ana_cmpr/linker.lf @@ -0,0 +1,7 @@ +[mapping:ana_cmpr_driver] +archive: libesp_driver_ana_cmpr.a +entries: + if ANA_CMPR_CTRL_FUNC_IN_IRAM = y: + ana_cmpr: ana_cmpr_set_internal_reference (noflash) + ana_cmpr: ana_cmpr_set_debounce (noflash) + ana_cmpr: ana_cmpr_set_cross_type (noflash) diff --git a/components/esp_driver_ana_cmpr/test_apps/.build-test-rules.yml b/components/esp_driver_ana_cmpr/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..cbcb9d16bc0 --- /dev/null +++ b/components/esp_driver_ana_cmpr/test_apps/.build-test-rules.yml @@ -0,0 +1,12 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_ana_cmpr/test_apps/analog_comparator: + disable: + - if: SOC_ANA_CMPR_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: not supported yet + depends_components: + - esp_driver_gpio + - esp_driver_ana_cmpr diff --git a/components/driver/test_apps/analog_comparator/CMakeLists.txt b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/CMakeLists.txt similarity index 86% rename from components/driver/test_apps/analog_comparator/CMakeLists.txt rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/CMakeLists.txt index ef4e64222d4..c5b8c3e782a 100644 --- a/components/driver/test_apps/analog_comparator/CMakeLists.txt +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/CMakeLists.txt @@ -10,7 +10,7 @@ project(test_ana_cmpr) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_ana_cmpr/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/test_ana_cmpr.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/analog_comparator/README.md b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md similarity index 100% rename from components/driver/test_apps/analog_comparator/README.md rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md diff --git a/components/driver/test_apps/analog_comparator/main/CMakeLists.txt b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt similarity index 78% rename from components/driver/test_apps/analog_comparator/main/CMakeLists.txt rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt index bad9d9c3314..b4687d1c66e 100644 --- a/components/driver/test_apps/analog_comparator/main/CMakeLists.txt +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt @@ -8,5 +8,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS "." - PRIV_REQUIRES unity driver + PRIV_REQUIRES unity esp_driver_gpio esp_driver_ana_cmpr WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/analog_comparator/main/test_ana_cmpr.c b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr.c similarity index 100% rename from components/driver/test_apps/analog_comparator/main/test_ana_cmpr.c rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr.c diff --git a/components/driver/test_apps/analog_comparator/main/test_ana_cmpr.h b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr.h similarity index 100% rename from components/driver/test_apps/analog_comparator/main/test_ana_cmpr.h rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr.h diff --git a/components/driver/test_apps/analog_comparator/main/test_ana_cmpr_common.c b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_common.c similarity index 100% rename from components/driver/test_apps/analog_comparator/main/test_ana_cmpr_common.c rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_common.c diff --git a/components/driver/test_apps/analog_comparator/main/test_ana_cmpr_iram.c b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_iram.c similarity index 100% rename from components/driver/test_apps/analog_comparator/main/test_ana_cmpr_iram.c rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_iram.c diff --git a/components/driver/test_apps/analog_comparator/main/test_app_main.c b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/analog_comparator/main/test_app_main.c rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_app_main.c diff --git a/components/driver/test_apps/analog_comparator/pytest_ana_cmpr.py b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py similarity index 100% rename from components/driver/test_apps/analog_comparator/pytest_ana_cmpr.py rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py diff --git a/components/driver/test_apps/analog_comparator/sdkconfig.ci.iram_safe b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/analog_comparator/sdkconfig.ci.iram_safe rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/analog_comparator/sdkconfig.ci.release b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/analog_comparator/sdkconfig.ci.release rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.ci.release diff --git a/components/driver/test_apps/analog_comparator/sdkconfig.defaults b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/analog_comparator/sdkconfig.defaults rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/sdkconfig.defaults diff --git a/components/esp_driver_dac/CMakeLists.txt b/components/esp_driver_dac/CMakeLists.txt new file mode 100644 index 00000000000..4b34f22df63 --- /dev/null +++ b/components/esp_driver_dac/CMakeLists.txt @@ -0,0 +1,32 @@ +idf_build_get_property(target IDF_TARGET) + +set(srcs) +set(priv_req esp_pm esp_driver_gpio) + +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +elseif(${target} STREQUAL "esp32") + list(APPEND priv_req esp_driver_i2s) +elseif(${target} STREQUAL "esp32s2") + list(APPEND priv_req esp_driver_spi) +endif() + +if(CONFIG_SOC_DAC_SUPPORTED) + list(APPEND srcs "dac_oneshot.c" + "dac_cosine.c" + "dac_continuous.c" + "dac_common.c") + + if(${target} STREQUAL "esp32") + list(APPEND srcs "esp32/dac_dma.c") + elseif(${target} STREQUAL "esp32s2") + list(APPEND srcs "esp32s2/dac_dma.c") + endif() + +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS "./include" + PRIV_REQUIRES ${priv_req} + LDFRAGMENTS "linker.lf" + ) diff --git a/components/esp_driver_dac/Kconfig b/components/esp_driver_dac/Kconfig new file mode 100644 index 00000000000..a0c9c30c1d3 --- /dev/null +++ b/components/esp_driver_dac/Kconfig @@ -0,0 +1,45 @@ +menu "ESP-Driver:DAC Configurations" + depends on SOC_DAC_SUPPORTED + config DAC_CTRL_FUNC_IN_IRAM + bool "Place DAC control functions into IRAM" + default n + help + Place DAC control functions (e.g. 'dac_oneshot_output_voltage') into IRAM, + so that this function can be IRAM-safe and able to be called in the other IRAM interrupt context. + Enabling this option can improve driver performance as well. + + config DAC_ISR_IRAM_SAFE + bool "DAC ISR IRAM-Safe" + default n + help + Ensure the DAC interrupt is IRAM-Safe by allowing the interrupt handler to be + executable when the cache is disabled (e.g. SPI Flash write). + + config DAC_SUPPRESS_DEPRECATE_WARN + bool "Suppress legacy driver deprecated warning" + default n + help + Wether to suppress the deprecation warnings when using legacy DAC driver (driver/dac.h). + If you want to continue using the legacy driver, and don't want to see related deprecation warnings, + you can enable this option. + + config DAC_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for DAC driver. + Note that, this option only controls the DAC driver log, won't affect other drivers. + + config DAC_DMA_AUTO_16BIT_ALIGN + bool "Align the continuous data to 16 bit automatically" + depends on SOC_DAC_DMA_16BIT_ALIGN + default y + help + Whether to left shift the continuous data to align every bytes to 16 bits in the driver. + On ESP32, although the DAC resolution is only 8 bits, + the hardware requires 16 bits data in continuous mode. + By enabling this option, the driver will left shift 8 bits for the input data automatically. + Only disable this option when you decide to do this step by yourself. + Note that the driver will allocate a new piece of memory to save the converted data. + +endmenu # DAC Configuration diff --git a/components/driver/dac/dac_common.c b/components/esp_driver_dac/dac_common.c similarity index 100% rename from components/driver/dac/dac_common.c rename to components/esp_driver_dac/dac_common.c diff --git a/components/driver/dac/dac_continuous.c b/components/esp_driver_dac/dac_continuous.c similarity index 98% rename from components/driver/dac/dac_continuous.c rename to components/esp_driver_dac/dac_continuous.c index 98bee776efd..b3f8f9c25e0 100644 --- a/components/driver/dac/dac_continuous.c +++ b/components/esp_driver_dac/dac_continuous.c @@ -194,7 +194,6 @@ static void IRAM_ATTR s_dac_default_intr_handler(void *arg) } } - esp_err_t dac_continuous_new_channels(const dac_continuous_config_t *cont_cfg, dac_continuous_handle_t *ret_handle) { #if CONFIG_DAC_ENABLE_DEBUG_LOG @@ -250,7 +249,7 @@ esp_err_t dac_continuous_new_channels(const dac_continuous_config_t *cont_cfg, d err2, TAG, "Failed to initialize DAC DMA peripheral"); /* Register DMA interrupt */ ESP_GOTO_ON_ERROR(esp_intr_alloc(dac_dma_periph_get_intr_signal(), DAC_INTR_ALLOC_FLAGS, - s_dac_default_intr_handler, handle, &(handle->intr_handle)), + s_dac_default_intr_handler, handle, &(handle->intr_handle)), err1, TAG, "Failed to register DAC DMA interrupt"); /* Connect DAC module to the DMA peripheral */ DAC_RTC_ENTER_CRITICAL(); @@ -359,7 +358,7 @@ esp_err_t dac_continuous_enable(dac_continuous_handle_t handle) esp_err_t ret = ESP_OK; /* Reset the descriptor pool */ xQueueReset(handle->desc_pool); - for ( int i = 0; i < handle->cfg.desc_num; i++) { + for (int i = 0; i < handle->cfg.desc_num; i++) { ESP_GOTO_ON_FALSE(xQueueSend(handle->desc_pool, &handle->desc[i], 0) == pdTRUE, ESP_ERR_INVALID_STATE, err, TAG, "the descriptor pool is not cleared"); } @@ -475,8 +474,8 @@ static size_t s_dac_load_data_into_buf(dac_continuous_handle_t handle, uint8_t * } esp_err_t dac_continuous_write_asynchronously(dac_continuous_handle_t handle, uint8_t *dma_buf, - size_t dma_buf_len, const uint8_t *data, - size_t data_len, size_t *bytes_loaded) + size_t dma_buf_len, const uint8_t *data, + size_t data_len, size_t *bytes_loaded) { DAC_NULL_POINTER_CHECK_ISR(handle); DAC_NULL_POINTER_CHECK_ISR(dma_buf); @@ -533,7 +532,7 @@ esp_err_t dac_continuous_write_cyclically(dac_continuous_handle_t handle, uint8_ buf += load_bytes / DAC_16BIT_ALIGN_COEFF; } /* Link the tail to the head as a ring */ - STAILQ_NEXT(handle->desc[i-1], qe) = handle->desc[0]; + STAILQ_NEXT(handle->desc[i - 1], qe) = handle->desc[0]; dac_dma_periph_dma_trans_start((uint32_t)handle->desc[0]); atomic_store(&handle->is_running, true); @@ -607,8 +606,8 @@ esp_err_t dac_continuous_write(dac_continuous_handle_t handle, uint8_t *buf, siz /* Wait for the previous DMA stop */ while (atomic_load(&handle->is_running)) {} for (int i = 0; - i < handle->cfg.desc_num && buf_size > 0; - i++, buf += w_size, buf_size -= w_size) { + i < handle->cfg.desc_num && buf_size > 0; + i++, buf += w_size, buf_size -= w_size) { ESP_GOTO_ON_ERROR(s_dac_wait_to_load_dma_data(handle, buf, buf_size, &w_size, timeout_tick), err, TAG, "Load data failed"); } dac_dma_periph_dma_trans_start((uint32_t)(STAILQ_FIRST(&handle->head))); diff --git a/components/driver/dac/dac_cosine.c b/components/esp_driver_dac/dac_cosine.c similarity index 97% rename from components/driver/dac/dac_cosine.c rename to components/esp_driver_dac/dac_cosine.c index b2214656680..445cc7455be 100644 --- a/components/driver/dac/dac_cosine.c +++ b/components/esp_driver_dac/dac_cosine.c @@ -113,7 +113,7 @@ esp_err_t dac_cosine_start(dac_cosine_handle_t handle) periph_rtc_dig_clk8m_enable(); /* Enabled DAC channel */ ESP_RETURN_ON_ERROR(dac_priv_enable_channel(handle->cfg.chan_id), TAG, - "enable dac channel %d failed", handle->cfg.chan_id); + "enable dac channel %d failed", handle->cfg.chan_id); /* Enabled the cosine wave generator if no channel using it before */ DAC_RTC_ENTER_CRITICAL(); if (s_cwg_refer_cnt == 0) { @@ -136,7 +136,7 @@ esp_err_t dac_cosine_stop(dac_cosine_handle_t handle) /* Enabled DAC channel */ ESP_RETURN_ON_ERROR(dac_priv_disable_channel(handle->cfg.chan_id), TAG, - "disable dac channel %d failed", handle->cfg.chan_id); + "disable dac channel %d failed", handle->cfg.chan_id); DAC_RTC_ENTER_CRITICAL(); /* Disconnect the DAC channel from the cosine wave generator */ dac_ll_cw_enable_channel(handle->cfg.chan_id, false); diff --git a/components/driver/dac/dac_oneshot.c b/components/esp_driver_dac/dac_oneshot.c similarity index 99% rename from components/driver/dac/dac_oneshot.c rename to components/esp_driver_dac/dac_oneshot.c index b698f9cd735..5e75ea11462 100644 --- a/components/driver/dac/dac_oneshot.c +++ b/components/esp_driver_dac/dac_oneshot.c @@ -19,7 +19,7 @@ #include "esp_pm.h" #endif - struct dac_oneshot_s { +struct dac_oneshot_s { dac_oneshot_config_t cfg; /*!< Oneshot mode configurations */ }; diff --git a/components/driver/dac/dac_priv_common.h b/components/esp_driver_dac/dac_priv_common.h similarity index 100% rename from components/driver/dac/dac_priv_common.h rename to components/esp_driver_dac/dac_priv_common.h diff --git a/components/driver/dac/dac_priv_dma.h b/components/esp_driver_dac/dac_priv_dma.h similarity index 99% rename from components/driver/dac/dac_priv_dma.h rename to components/esp_driver_dac/dac_priv_dma.h index a5491f39f0f..deae4f55d01 100644 --- a/components/driver/dac/dac_priv_dma.h +++ b/components/esp_driver_dac/dac_priv_dma.h @@ -9,7 +9,6 @@ #include "esp_err.h" #include "esp_intr_alloc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/driver/dac/esp32/dac_dma.c b/components/esp_driver_dac/esp32/dac_dma.c similarity index 98% rename from components/driver/dac/esp32/dac_dma.c rename to components/esp_driver_dac/esp32/dac_dma.c index f1e648f16dd..84cd0b4ad77 100644 --- a/components/driver/dac/esp32/dac_dma.c +++ b/components/esp_driver_dac/esp32/dac_dma.c @@ -125,7 +125,7 @@ esp_err_t dac_dma_periph_init(uint32_t freq_hz, bool is_alternate, bool is_apll) } ESP_GOTO_ON_ERROR(s_dac_dma_periph_set_clock(freq_hz, is_apll), err, TAG, "Failed to set clock of DMA peripheral"); - i2s_ll_enable_builtin_dac(s_ddp->periph_dev, true); + i2s_ll_enable_builtin_adc_dac(s_ddp->periph_dev, true); i2s_ll_tx_reset(s_ddp->periph_dev); i2s_ll_tx_set_slave_mod(s_ddp->periph_dev, false); i2s_ll_tx_set_sample_bit(s_ddp->periph_dev, DAC_DMA_PERIPH_I2S_BIT_WIDTH, DAC_DMA_PERIPH_I2S_BIT_WIDTH); @@ -178,7 +178,7 @@ static void s_dac_dma_periph_reset(void) static void s_dac_dma_periph_start(void) { - i2s_ll_enable_dma(s_ddp->periph_dev,true); + i2s_ll_enable_dma(s_ddp->periph_dev, true); i2s_ll_tx_enable_intr(s_ddp->periph_dev); i2s_ll_tx_start(s_ddp->periph_dev); i2s_ll_dma_enable_eof_on_fifo_empty(s_ddp->periph_dev, true); diff --git a/components/driver/dac/esp32s2/dac_dma.c b/components/esp_driver_dac/esp32s2/dac_dma.c similarity index 96% rename from components/driver/dac/esp32s2/dac_dma.c rename to components/esp_driver_dac/esp32s2/dac_dma.c index d13c63f39b9..6e715bc4dc3 100644 --- a/components/driver/dac/esp32s2/dac_dma.c +++ b/components/esp_driver_dac/esp32s2/dac_dma.c @@ -38,6 +38,7 @@ typedef struct { void *periph_dev; /* DMA peripheral device address */ uint32_t dma_chan; + spi_dma_ctx_t *spi_dma_ctx; /* spi_dma context */ intr_handle_t intr_handle; /* Interrupt handle */ bool use_apll; /* Whether use APLL as digital controller clock source */ } dac_dma_periph_spi_t; @@ -71,14 +72,15 @@ static uint32_t s_dac_set_apll_freq(uint32_t expt_freq) * - ESP_OK config success * - ESP_ERR_INVALID_ARG invalid frequency */ -static esp_err_t s_dac_dma_periph_set_clock(uint32_t freq_hz, bool is_apll){ +static esp_err_t s_dac_dma_periph_set_clock(uint32_t freq_hz, bool is_apll) +{ /* Step 1: Determine the digital clock source frequency */ uint32_t digi_ctrl_freq; // Digital controller clock if (is_apll) { /* Theoretical frequency range (due to the limitation of DAC, the maximum frequency may not reach): * CLK_LL_APLL_MAX_HZ: 119.24 Hz ~ 67.5 MHz * CLK_LL_APLL_MIN_HZ: 5.06 Hz ~ 2.65 MHz */ - digi_ctrl_freq = s_dac_set_apll_freq(freq_hz < 120 ? CLK_LL_APLL_MIN_HZ :CLK_LL_APLL_MAX_HZ); + digi_ctrl_freq = s_dac_set_apll_freq(freq_hz < 120 ? CLK_LL_APLL_MIN_HZ : CLK_LL_APLL_MAX_HZ); ESP_RETURN_ON_FALSE(digi_ctrl_freq, ESP_ERR_INVALID_ARG, TAG, "set APLL coefficients failed"); } else { digi_ctrl_freq = APB_CLK_FREQ; @@ -141,9 +143,10 @@ esp_err_t dac_dma_periph_init(uint32_t freq_hz, bool is_alternate, bool is_apll) /* When transmit alternately, twice frequency is needed to guarantee the convert frequency in one channel */ uint32_t trans_freq_hz = freq_hz * (is_alternate ? 2 : 1); ESP_GOTO_ON_ERROR(s_dac_dma_periph_set_clock(trans_freq_hz, is_apll), err, TAG, "Failed to set clock of DMA peripheral"); - ESP_GOTO_ON_ERROR(spicommon_dma_chan_alloc(DAC_DMA_PERIPH_SPI_HOST, SPI_DMA_CH_AUTO, &s_ddp->dma_chan, &s_ddp->dma_chan), + ESP_GOTO_ON_ERROR(spicommon_dma_chan_alloc(DAC_DMA_PERIPH_SPI_HOST, SPI_DMA_CH_AUTO, &s_ddp->spi_dma_ctx), err, TAG, "Failed to allocate dma peripheral channel"); + s_ddp->dma_chan = s_ddp->spi_dma_ctx->rx_dma_chan.chan_id; spi_ll_enable_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_OUT_TOTAL_EOF); dac_ll_digi_set_convert_mode(is_alternate); return ret; @@ -156,7 +159,7 @@ esp_err_t dac_dma_periph_deinit(void) { ESP_RETURN_ON_FALSE(s_ddp->intr_handle == NULL, ESP_ERR_INVALID_STATE, TAG, "The interrupt is not deregistered yet"); if (s_ddp->dma_chan) { - ESP_RETURN_ON_ERROR(spicommon_dma_chan_free(DAC_DMA_PERIPH_SPI_HOST), TAG, "Failed to free dma peripheral channel"); + ESP_RETURN_ON_ERROR(spicommon_dma_chan_free(s_ddp->spi_dma_ctx), TAG, "Failed to free dma peripheral channel"); } ESP_RETURN_ON_FALSE(spicommon_periph_free(DAC_DMA_PERIPH_SPI_HOST), ESP_FAIL, TAG, "Failed to release DAC DMA peripheral"); spi_ll_disable_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_OUT_TOTAL_EOF); diff --git a/components/driver/dac/include/driver/dac_continuous.h b/components/esp_driver_dac/include/driver/dac_continuous.h similarity index 99% rename from components/driver/dac/include/driver/dac_continuous.h rename to components/esp_driver_dac/include/driver/dac_continuous.h index 0cb931522d1..ad7668309f8 100644 --- a/components/driver/dac/include/driver/dac_continuous.h +++ b/components/esp_driver_dac/include/driver/dac_continuous.h @@ -59,7 +59,6 @@ typedef struct { dac_continuous_channel_mode_t chan_mode; /*!< The channel mode of continuous mode, only take effect when multiple channels enabled, depends converting the buffer alternately or simultaneously */ } dac_continuous_config_t; - /** * @brief Event structure used in DAC event queue */ @@ -96,7 +95,6 @@ typedef struct { */ } dac_event_callbacks_t; - /** * @brief Allocate new DAC channels in continuous mode * @note The DAC channels can't be registered to continuous mode separately diff --git a/components/driver/dac/include/driver/dac_cosine.h b/components/esp_driver_dac/include/driver/dac_cosine.h similarity index 100% rename from components/driver/dac/include/driver/dac_cosine.h rename to components/esp_driver_dac/include/driver/dac_cosine.h diff --git a/components/driver/dac/include/driver/dac_oneshot.h b/components/esp_driver_dac/include/driver/dac_oneshot.h similarity index 100% rename from components/driver/dac/include/driver/dac_oneshot.h rename to components/esp_driver_dac/include/driver/dac_oneshot.h diff --git a/components/driver/dac/include/driver/dac_types.h b/components/esp_driver_dac/include/driver/dac_types.h similarity index 100% rename from components/driver/dac/include/driver/dac_types.h rename to components/esp_driver_dac/include/driver/dac_types.h diff --git a/components/esp_driver_dac/linker.lf b/components/esp_driver_dac/linker.lf new file mode 100644 index 00000000000..c58fa57831d --- /dev/null +++ b/components/esp_driver_dac/linker.lf @@ -0,0 +1,6 @@ +[mapping:dac_driver] +archive: libesp_driver_dac.a +entries: + if DAC_CTRL_FUNC_IN_IRAM = y: + dac_oneshot: dac_oneshot_output_voltage (noflash) + dac_continuous: dac_continuous_write_asynchronously (noflash) diff --git a/components/esp_driver_dac/test_apps/.build-test-rules.yml b/components/esp_driver_dac/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..33c41155f13 --- /dev/null +++ b/components/esp_driver_dac/test_apps/.build-test-rules.yml @@ -0,0 +1,9 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_dac/test_apps/dac: + disable: + - if: SOC_DAC_SUPPORTED != 1 + depends_components: + - esp_driver_i2s + - esp_driver_spi + - esp_adc diff --git a/components/driver/test_apps/dac_test_apps/dac/CMakeLists.txt b/components/esp_driver_dac/test_apps/dac/CMakeLists.txt similarity index 87% rename from components/driver/test_apps/dac_test_apps/dac/CMakeLists.txt rename to components/esp_driver_dac/test_apps/dac/CMakeLists.txt index 71dad1881a2..0e63a580847 100644 --- a/components/driver/test_apps/dac_test_apps/dac/CMakeLists.txt +++ b/components/esp_driver_dac/test_apps/dac/CMakeLists.txt @@ -10,7 +10,7 @@ project(dac_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_dac/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/dac_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/dac_test_apps/dac/README.md b/components/esp_driver_dac/test_apps/dac/README.md similarity index 100% rename from components/driver/test_apps/dac_test_apps/dac/README.md rename to components/esp_driver_dac/test_apps/dac/README.md diff --git a/components/driver/test_apps/dac_test_apps/dac/main/CMakeLists.txt b/components/esp_driver_dac/test_apps/dac/main/CMakeLists.txt similarity index 67% rename from components/driver/test_apps/dac_test_apps/dac/main/CMakeLists.txt rename to components/esp_driver_dac/test_apps/dac/main/CMakeLists.txt index 369886c7ddf..5a701a9196e 100644 --- a/components/driver/test_apps/dac_test_apps/dac/main/CMakeLists.txt +++ b/components/esp_driver_dac/test_apps/dac/main/CMakeLists.txt @@ -8,5 +8,6 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity esp_driver_pcnt driver esp_adc + PRIV_REQUIRES unity esp_driver_pcnt esp_adc + esp_driver_dac esp_driver_gpio esp_driver_i2s esp_driver_spi WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/dac_test_apps/dac/main/test_app_main.c b/components/esp_driver_dac/test_apps/dac/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/dac_test_apps/dac/main/test_app_main.c rename to components/esp_driver_dac/test_apps/dac/main/test_app_main.c diff --git a/components/driver/test_apps/dac_test_apps/dac/main/test_dac.c b/components/esp_driver_dac/test_apps/dac/main/test_dac.c similarity index 98% rename from components/driver/test_apps/dac_test_apps/dac/main/test_dac.c rename to components/esp_driver_dac/test_apps/dac/main/test_dac.c index 4a0a99f83e9..79b6e080665 100644 --- a/components/driver/test_apps/dac_test_apps/dac/main/test_dac.c +++ b/components/esp_driver_dac/test_apps/dac/main/test_dac.c @@ -39,11 +39,15 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]") { /* Constant API test */ dac_oneshot_handle_t oneshot_chan0_handle; - TEST_ESP_OK(dac_oneshot_new_channel(&(dac_oneshot_config_t){.chan_id = DAC_CHAN_0}, &oneshot_chan0_handle)); + TEST_ESP_OK(dac_oneshot_new_channel(&(dac_oneshot_config_t) { + .chan_id = DAC_CHAN_0 + }, &oneshot_chan0_handle)); TEST_ESP_OK(dac_oneshot_output_voltage(oneshot_chan0_handle, 128)); TEST_ESP_OK(dac_oneshot_del_channel(oneshot_chan0_handle)); dac_oneshot_handle_t oneshot_chan1_handle; - TEST_ESP_OK(dac_oneshot_new_channel(&(dac_oneshot_config_t){.chan_id = DAC_CHAN_1}, &oneshot_chan1_handle)); + TEST_ESP_OK(dac_oneshot_new_channel(&(dac_oneshot_config_t) { + .chan_id = DAC_CHAN_1 + }, &oneshot_chan1_handle)); TEST_ESP_OK(dac_oneshot_output_voltage(oneshot_chan1_handle, 100)); TEST_ESP_OK(dac_oneshot_del_channel(oneshot_chan1_handle)); diff --git a/components/driver/test_apps/dac_test_apps/dac/main/test_dac_iram.c b/components/esp_driver_dac/test_apps/dac/main/test_dac_iram.c similarity index 96% rename from components/driver/test_apps/dac_test_apps/dac/main/test_dac_iram.c rename to components/esp_driver_dac/test_apps/dac/main/test_dac_iram.c index 7a8a1bd196c..8f59b831f01 100644 --- a/components/driver/test_apps/dac_test_apps/dac/main/test_dac_iram.c +++ b/components/esp_driver_dac/test_apps/dac/main/test_dac_iram.c @@ -53,7 +53,9 @@ static bool IRAM_ATTR test_dac_on_convert_done_cb(dac_continuous_handle_t handle TEST_CASE("DAC_IRAM_safe_test", "[dac]") { dac_oneshot_handle_t oneshot_handle; - TEST_ESP_OK(dac_oneshot_new_channel(&(dac_oneshot_config_t){.chan_id = DAC_CHAN_0}, &oneshot_handle)); + TEST_ESP_OK(dac_oneshot_new_channel(&(dac_oneshot_config_t) { + .chan_id = DAC_CHAN_0 + }, &oneshot_handle)); /* Test direct voltage setting safety */ unity_utils_run_cache_disable_stub(test_dac_direct_set_safety, oneshot_handle); diff --git a/components/driver/test_apps/dac_test_apps/dac/pytest_dac.py b/components/esp_driver_dac/test_apps/dac/pytest_dac.py similarity index 100% rename from components/driver/test_apps/dac_test_apps/dac/pytest_dac.py rename to components/esp_driver_dac/test_apps/dac/pytest_dac.py diff --git a/components/driver/test_apps/dac_test_apps/dac/sdkconfig.ci.iram_safe b/components/esp_driver_dac/test_apps/dac/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/dac_test_apps/dac/sdkconfig.ci.iram_safe rename to components/esp_driver_dac/test_apps/dac/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/dac_test_apps/dac/sdkconfig.ci.release b/components/esp_driver_dac/test_apps/dac/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/dac_test_apps/dac/sdkconfig.ci.release rename to components/esp_driver_dac/test_apps/dac/sdkconfig.ci.release diff --git a/components/driver/test_apps/dac_test_apps/dac/sdkconfig.defaults b/components/esp_driver_dac/test_apps/dac/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/dac_test_apps/dac/sdkconfig.defaults rename to components/esp_driver_dac/test_apps/dac/sdkconfig.defaults diff --git a/components/esp_driver_gpio/test_apps/.build-test-rules.yml b/components/esp_driver_gpio/test_apps/.build-test-rules.yml index 13e104d9c9a..d9694c7aef2 100644 --- a/components/esp_driver_gpio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_gpio/test_apps/.build-test-rules.yml @@ -8,3 +8,5 @@ components/esp_driver_gpio/test_apps/gpio_extensions: enable: - if: SOC_DEDICATED_GPIO_SUPPORTED == 1 - if: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER == 1 or SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0 + depends_components: + - esp_driver_gpio diff --git a/components/esp_driver_gptimer/CMakeLists.txt b/components/esp_driver_gptimer/CMakeLists.txt index 4ec99842f0f..9b0871a8f72 100644 --- a/components/esp_driver_gptimer/CMakeLists.txt +++ b/components/esp_driver_gptimer/CMakeLists.txt @@ -11,6 +11,6 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} - PRIV_REQUIRES "esp_pm" + REQUIRES "esp_pm" LDFRAGMENTS "linker.lf" ) diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt b/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt index 7e2ef128f47..2768a1f04e1 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt @@ -8,5 +8,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver + PRIV_REQUIRES unity esp_driver_gptimer WHOLE_ARCHIVE) diff --git a/components/esp_driver_i2c/CMakeLists.txt b/components/esp_driver_i2c/CMakeLists.txt new file mode 100644 index 00000000000..db7bdc88588 --- /dev/null +++ b/components/esp_driver_i2c/CMakeLists.txt @@ -0,0 +1,20 @@ +set(srcs) +set(include "include") + +# I2C related source files +if(CONFIG_SOC_I2C_SUPPORTED) + list(APPEND srcs + "i2c_master.c" + "i2c_common.c" + ) + if(CONFIG_SOC_I2C_SUPPORT_SLAVE) + list(APPEND srcs "i2c_slave.c") + endif() + +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${include} + PRIV_REQUIRES esp_driver_gpio esp_pm esp_ringbuf + LDFRAGMENTS "linker.lf" + ) diff --git a/components/esp_driver_i2c/Kconfig b/components/esp_driver_i2c/Kconfig new file mode 100644 index 00000000000..db3b45814b2 --- /dev/null +++ b/components/esp_driver_i2c/Kconfig @@ -0,0 +1,20 @@ +menu "ESP-Driver:I2C Configurations" + depends on SOC_I2C_SUPPORTED + config I2C_ISR_IRAM_SAFE + bool "I2C ISR IRAM-Safe" + default n + help + Ensure the I2C interrupt is IRAM-Safe by allowing the interrupt handler to be + executable when the cache is disabled (e.g. SPI Flash write). + note: This cannot be used in the I2C legacy driver. + + config I2C_ENABLE_DEBUG_LOG + bool "Enable I2C debug log" + default n + help + Wether to enable the debug log message for I2C driver. + Note that this option only controls the I2C driver log, will not affect other drivers. + + note: This cannot be used in the I2C legacy driver. + +endmenu # I2C Configurations diff --git a/components/driver/i2c/i2c_common.c b/components/esp_driver_i2c/i2c_common.c similarity index 99% rename from components/driver/i2c/i2c_common.c rename to components/esp_driver_i2c/i2c_common.c index 831bef2bdc6..9a7e7101d64 100644 --- a/components/driver/i2c/i2c_common.c +++ b/components/esp_driver_i2c/i2c_common.c @@ -218,7 +218,6 @@ esp_err_t i2c_select_periph_clock(i2c_bus_handle_t handle, i2c_clock_source_t cl } #endif // CONFIG_PM_ENABLE - ESP_LOGD(TAG, "bus clock source frequency: %"PRIu32"hz", periph_src_clk_hz); return ret; } @@ -243,7 +242,6 @@ esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle) esp_rom_gpio_connect_out_signal(handle->sda_num, i2c_periph_signal[port_id].sda_out_sig, 0, 0); esp_rom_gpio_connect_in_signal(handle->sda_num, i2c_periph_signal[port_id].sda_in_sig, 0); - // SCL pin configurations gpio_config_t scl_conf = { .intr_type = GPIO_INTR_DISABLE, diff --git a/components/driver/i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c similarity index 98% rename from components/driver/i2c/i2c_master.c rename to components/esp_driver_i2c/i2c_master.c index 35203d519cc..91e44952d57 100644 --- a/components/driver/i2c/i2c_master.c +++ b/components/esp_driver_i2c/i2c_master.c @@ -444,7 +444,7 @@ static void s_i2c_send_command_async(i2c_master_bus_handle_t i2c_master, BaseTyp i2c_master->sent_all = true; return; } - while(i2c_ll_is_bus_busy(hal->dev)){} + while (i2c_ll_is_bus_busy(hal->dev)) {} while (i2c_master->i2c_trans.cmd_count && !needs_start) { i2c_master->in_progress = true; @@ -514,13 +514,12 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf return ret; } - ///////////////////////////////I2C DRIVERS////////////////////////////////////////////////////////////// IRAM_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_master) { i2c_hal_context_t *hal = &i2c_master->base->hal; - while(i2c_ll_is_bus_busy(hal->dev)){} + while (i2c_ll_is_bus_busy(hal->dev)) {} if (i2c_master->status == I2C_STATUS_READ) { i2c_operation_t *i2c_operation = &i2c_master->i2c_trans.ops[i2c_master->trans_idx]; portENTER_CRITICAL_ISR(&i2c_master->base->spinlock); @@ -656,7 +655,7 @@ static esp_err_t i2c_master_bus_destroy(i2c_master_bus_handle_t bus_handle) { ESP_RETURN_ON_FALSE(bus_handle, ESP_ERR_INVALID_ARG, TAG, "no memory for i2c master bus"); i2c_master_bus_handle_t i2c_master = bus_handle; - if(i2c_release_bus_handle(i2c_master->base) == ESP_OK) { + if (i2c_release_bus_handle(i2c_master->base) == ESP_OK) { if (i2c_master) { if (i2c_master->bus_lock_mux) { vSemaphoreDeleteWithCaps(i2c_master->bus_lock_mux); @@ -717,7 +716,7 @@ static esp_err_t s_i2c_asynchronous_transaction(i2c_master_dev_handle_t i2c_dev, i2c_dev->master_bus->queue_trans = false; ESP_RETURN_ON_ERROR(s_i2c_transaction_start(i2c_dev, timeout_ms), TAG, "I2C transaction failed"); } else { - i2c_dev->master_bus->i2c_anyc_ops[i2c_dev->master_bus->index]=(i2c_operation_t(*))heap_caps_calloc(1, sizeof(i2c_operation_t) * 6, I2C_MEM_ALLOC_CAPS); + i2c_dev->master_bus->i2c_anyc_ops[i2c_dev->master_bus->index] = (i2c_operation_t(*))heap_caps_calloc(1, sizeof(i2c_operation_t) * 6, I2C_MEM_ALLOC_CAPS); memcpy(i2c_dev->master_bus->i2c_anyc_ops[i2c_dev->master_bus->index], i2c_ops, sizeof(i2c_operation_t) * ops_dim); i2c_transaction_t i2c_queue_pre; if (i2c_dev->master_bus->num_trans_inflight < i2c_dev->master_bus->queue_size) { @@ -874,7 +873,9 @@ esp_err_t i2c_master_bus_add_device(i2c_master_bus_handle_t bus_handle, const i2 { esp_err_t ret = ESP_OK; ESP_RETURN_ON_FALSE((bus_handle != NULL), ESP_ERR_INVALID_ARG, TAG, "this bus is not initialized, please call `i2c_new_master_bus`"); - if(bus_handle->base->bus_mode != I2C_BUS_MODE_MASTER) { + ESP_RETURN_ON_FALSE(dev_config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(dev_config->scl_speed_hz > 0, ESP_ERR_INVALID_ARG, TAG, "invalid scl frequency"); + if (bus_handle->base->bus_mode != I2C_BUS_MODE_MASTER) { ESP_LOGE(TAG, "This is not master bus!"); return ESP_ERR_INVALID_ARG; } @@ -943,7 +944,6 @@ esp_err_t i2c_master_bus_reset(i2c_master_bus_handle_t bus_handle) return ESP_OK; } - esp_err_t i2c_master_transmit(i2c_master_dev_handle_t i2c_dev, const uint8_t *write_buffer, size_t write_size, int xfer_timeout_ms) { ESP_RETURN_ON_FALSE(i2c_dev != NULL, ESP_ERR_INVALID_ARG, TAG, "i2c handle not initialized"); @@ -957,7 +957,7 @@ esp_err_t i2c_master_transmit(i2c_master_dev_handle_t i2c_dev, const uint8_t *wr }; ESP_RETURN_ON_ERROR(s_i2c_synchronous_transaction(i2c_dev, i2c_ops, DIM(i2c_ops), xfer_timeout_ms), TAG, "I2C transaction failed"); } else { - i2c_dev->master_bus->anyc_write_buffer[i2c_dev->master_bus->index] = (uint8_t*)heap_caps_calloc(1, sizeof(uint8_t)*write_size, I2C_MEM_ALLOC_CAPS); + i2c_dev->master_bus->anyc_write_buffer[i2c_dev->master_bus->index] = (uint8_t*)heap_caps_calloc(1, sizeof(uint8_t) * write_size, I2C_MEM_ALLOC_CAPS); memcpy(i2c_dev->master_bus->anyc_write_buffer[i2c_dev->master_bus->index], write_buffer, write_size); i2c_operation_t i2c_ops[] = { {.hw_cmd = I2C_TRANS_START_COMMAND}, @@ -986,7 +986,7 @@ esp_err_t i2c_master_transmit_receive(i2c_master_dev_handle_t i2c_dev, const uin }; ESP_RETURN_ON_ERROR(s_i2c_synchronous_transaction(i2c_dev, i2c_ops, DIM(i2c_ops), xfer_timeout_ms), TAG, "I2C transaction failed"); } else { - i2c_dev->master_bus->anyc_write_buffer[i2c_dev->master_bus->index] = (uint8_t*)heap_caps_calloc(1, sizeof(uint8_t)*write_size, I2C_MEM_ALLOC_CAPS); + i2c_dev->master_bus->anyc_write_buffer[i2c_dev->master_bus->index] = (uint8_t*)heap_caps_calloc(1, sizeof(uint8_t) * write_size, I2C_MEM_ALLOC_CAPS); memcpy(i2c_dev->master_bus->anyc_write_buffer[i2c_dev->master_bus->index], write_buffer, write_size); i2c_operation_t i2c_ops[] = { diff --git a/components/driver/i2c/i2c_private.h b/components/esp_driver_i2c/i2c_private.h similarity index 100% rename from components/driver/i2c/i2c_private.h rename to components/esp_driver_i2c/i2c_private.h diff --git a/components/driver/i2c/i2c_slave.c b/components/esp_driver_i2c/i2c_slave.c similarity index 100% rename from components/driver/i2c/i2c_slave.c rename to components/esp_driver_i2c/i2c_slave.c diff --git a/components/driver/i2c/include/driver/i2c_master.h b/components/esp_driver_i2c/include/driver/i2c_master.h similarity index 99% rename from components/driver/i2c/include/driver/i2c_master.h rename to components/esp_driver_i2c/include/driver/i2c_master.h index fb78ef47b8d..228f64fcc95 100644 --- a/components/driver/i2c/include/driver/i2c_master.h +++ b/components/esp_driver_i2c/include/driver/i2c_master.h @@ -27,7 +27,7 @@ typedef struct { int intr_priority; /*!< I2C interrupt priority, if set to 0, driver will select the default priority (1,2,3). */ size_t trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background, only valid in asynchronous transaction. (Typically max_device_num * per_transaction)*/ struct { - uint32_t enable_internal_pullup:1; /*!< Enable internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. Recommend proper external pull-up if possible */ + uint32_t enable_internal_pullup: 1; /*!< Enable internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. Recommend proper external pull-up if possible */ } flags; /*!< I2C master config flags */ } i2c_master_bus_config_t; diff --git a/components/driver/i2c/include/driver/i2c_slave.h b/components/esp_driver_i2c/include/driver/i2c_slave.h similarity index 96% rename from components/driver/i2c/include/driver/i2c_slave.h rename to components/esp_driver_i2c/include/driver/i2c_slave.h index e705aa3b022..897b9899ed0 100644 --- a/components/driver/i2c/include/driver/i2c_slave.h +++ b/components/esp_driver_i2c/include/driver/i2c_slave.h @@ -29,16 +29,16 @@ typedef struct { int intr_priority; /*!< I2C interrupt priority, if set to 0, driver will select the default priority (1,2,3). */ struct { #if SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE - uint32_t stretch_en:1; /*!< Enable slave stretch */ + uint32_t stretch_en: 1; /*!< Enable slave stretch */ #endif #if SOC_I2C_SLAVE_SUPPORT_BROADCAST - uint32_t broadcast_en:1; /*!< I2C slave enable broadcast */ + uint32_t broadcast_en: 1; /*!< I2C slave enable broadcast */ #endif #if SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS - uint32_t access_ram_en:1; /*!< Can get access to I2C RAM directly */ + uint32_t access_ram_en: 1; /*!< Can get access to I2C RAM directly */ #endif #if SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH - uint32_t slave_unmatch_en:1; /*!< Can trigger unmatch interrupt when slave address does not match what master sends*/ + uint32_t slave_unmatch_en: 1; /*!< Can trigger unmatch interrupt when slave address does not match what master sends*/ #endif } flags; /*!< I2C slave config flags */ } i2c_slave_config_t; diff --git a/components/driver/i2c/include/driver/i2c_types.h b/components/esp_driver_i2c/include/driver/i2c_types.h similarity index 97% rename from components/driver/i2c/include/driver/i2c_types.h rename to components/esp_driver_i2c/include/driver/i2c_types.h index 8e31bbfe598..346b50dcd03 100644 --- a/components/driver/i2c/include/driver/i2c_types.h +++ b/components/esp_driver_i2c/include/driver/i2c_types.h @@ -34,7 +34,6 @@ typedef enum { I2C_STATUS_TIMEOUT, /*!< I2C bus status error, and operation timeout */ } i2c_master_status_t; - typedef enum { I2C_EVENT_ALIVE, /*!< i2c bus in alive status.*/ I2C_EVENT_DONE, /*!< i2c bus transaction done */ @@ -86,7 +85,7 @@ typedef struct { * * @param[in] i2c_slave Handle for I2C slave. * @param[out] evt_data I2C capture event data, fed by driver - * @param[in] user_ctx User data, set in `i2c_slave_register_event_callbacks()` + * @param[in] arg User data, set in `i2c_slave_register_event_callbacks()` * * @return Whether a high priority task has been waken up by this function */ diff --git a/components/driver/i2c/linker.lf b/components/esp_driver_i2c/linker.lf similarity index 62% rename from components/driver/i2c/linker.lf rename to components/esp_driver_i2c/linker.lf index c16bd8c206d..7a3bcd47e52 100644 --- a/components/driver/i2c/linker.lf +++ b/components/esp_driver_i2c/linker.lf @@ -1,8 +1,14 @@ [mapping:i2c_driver] -archive: libdriver.a +archive: libesp_driver_i2c.a entries: if I2C_ISR_IRAM_SAFE = y: i2c_master: s_i2c_send_command_async (noflash) i2c_master: s_i2c_write_command (noflash) i2c_master: s_i2c_read_command (noflash) i2c_master: s_i2c_start_end_command (noflash) + +[mapping:i2c_hal] +archive: libhal.a +entries: + if I2C_ISR_IRAM_SAFE = y: + i2c_hal: i2c_hal_master_trans_start (noflash) diff --git a/components/esp_driver_i2c/test_apps/.build-test-rules.yml b/components/esp_driver_i2c/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..074e8796e9f --- /dev/null +++ b/components/esp_driver_i2c/test_apps/.build-test-rules.yml @@ -0,0 +1,11 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_i2c/test_apps/i2c_test_apps: + disable: + - if: SOC_I2C_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: lack of runners + depends_components: + - esp_driver_i2c diff --git a/components/driver/test_apps/i2c_test_apps/CMakeLists.txt b/components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt similarity index 88% rename from components/driver/test_apps/i2c_test_apps/CMakeLists.txt rename to components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt index ff8c38b0c54..3ebe26f85d7 100644 --- a/components/driver/test_apps/i2c_test_apps/CMakeLists.txt +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt @@ -14,7 +14,7 @@ project(i2c_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i2c/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/i2c_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/i2c_test_apps/README.md b/components/esp_driver_i2c/test_apps/i2c_test_apps/README.md similarity index 100% rename from components/driver/test_apps/i2c_test_apps/README.md rename to components/esp_driver_i2c/test_apps/i2c_test_apps/README.md diff --git a/components/driver/test_apps/i2c_test_apps/main/CMakeLists.txt b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/i2c_test_apps/main/CMakeLists.txt rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt diff --git a/components/driver/test_apps/i2c_test_apps/main/test_app_main.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/i2c_test_apps/main/test_app_main.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_app_main.c diff --git a/components/driver/test_apps/i2c_test_apps/main/test_board.h b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_board.h similarity index 100% rename from components/driver/test_apps/i2c_test_apps/main/test_board.h rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_board.h diff --git a/components/driver/test_apps/i2c_test_apps/main/test_i2c_10bit.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_10bit.c similarity index 99% rename from components/driver/test_apps/i2c_test_apps/main/test_i2c_10bit.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_10bit.c index 399a2671c9d..ec76603e99e 100644 --- a/components/driver/test_apps/i2c_test_apps/main/test_i2c_10bit.c +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_10bit.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ - #include #include #include "sdkconfig.h" @@ -119,7 +118,6 @@ static void i2c_slave_read_test_10bit(void) TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test 10 bit", "[i2c][test_env=generic_multi_device][timeout=150]", i2c_master_write_test_10bit, i2c_slave_read_test_10bit); - static void master_read_slave_test_10bit(void) { uint8_t data_rd[DATA_LENGTH] = {0}; @@ -153,7 +151,7 @@ static void master_read_slave_test_10bit(void) vTaskDelay(100 / portTICK_PERIOD_MS); for (int i = 0; i < DATA_LENGTH; i++) { printf("%d\n", data_rd[i]); - TEST_ASSERT(data_rd[i]==i); + TEST_ASSERT(data_rd[i] == i); } unity_send_signal("ready to delete 10bit"); @@ -192,5 +190,4 @@ static void slave_write_buffer_test_10bit(void) TEST_ESP_OK(i2c_del_slave_device(slave_handle)); } - TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test 10 bit", "[i2c][test_env=generic_multi_device][timeout=150]", master_read_slave_test_10bit, slave_write_buffer_test_10bit); diff --git a/components/driver/test_apps/i2c_test_apps/main/test_i2c_broadcast.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_broadcast.c similarity index 99% rename from components/driver/test_apps/i2c_test_apps/main/test_i2c_broadcast.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_broadcast.c index e6cf562289c..6a90afcf889 100644 --- a/components/driver/test_apps/i2c_test_apps/main/test_i2c_broadcast.c +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_broadcast.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ - #include #include #include "sdkconfig.h" diff --git a/components/driver/test_apps/i2c_test_apps/main/test_i2c_common.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c similarity index 97% rename from components/driver/test_apps/i2c_test_apps/main/test_i2c_common.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c index ee307c32a3d..cc238cc0a6e 100644 --- a/components/driver/test_apps/i2c_test_apps/main/test_i2c_common.c +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c @@ -101,21 +101,21 @@ TEST_CASE("I2C device add & remove check", "[i2c]") TEST_ESP_OK(i2c_new_master_bus(&i2c_mst_config_1, &bus_handle)); i2c_device_config_t dev_cfg_1 = { - .scl_speed_hz = 100*1000, + .scl_speed_hz = 100 * 1000, .device_address = 0x10, }; i2c_master_dev_handle_t dev_1; i2c_master_bus_add_device(bus_handle, &dev_cfg_1, &dev_1); i2c_device_config_t dev_cfg_2 = { - .scl_speed_hz = 100*1000, + .scl_speed_hz = 100 * 1000, .device_address = 0x20, }; i2c_master_dev_handle_t dev_2; i2c_master_bus_add_device(bus_handle, &dev_cfg_2, &dev_2); i2c_device_config_t dev_cfg_3 = { - .scl_speed_hz = 100*1000, + .scl_speed_hz = 100 * 1000, .device_address = 0x30, }; i2c_master_dev_handle_t dev_3; diff --git a/components/driver/test_apps/i2c_test_apps/main/test_i2c_iram.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_iram.c similarity index 100% rename from components/driver/test_apps/i2c_test_apps/main/test_i2c_iram.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_iram.c diff --git a/components/driver/test_apps/i2c_test_apps/main/test_i2c_multi.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_multi.c similarity index 99% rename from components/driver/test_apps/i2c_test_apps/main/test_i2c_multi.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_multi.c index eaf026f0c8d..e15b5472d2f 100644 --- a/components/driver/test_apps/i2c_test_apps/main/test_i2c_multi.c +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_multi.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ - #include #include #include "sdkconfig.h" @@ -32,7 +31,7 @@ void disp_buf(uint8_t *buf, int len) int i; for (i = 0; i < len; i++) { printf("%02x ", buf[i]); - if (( i + 1 ) % 16 == 0) { + if ((i + 1) % 16 == 0) { printf("\n"); } } @@ -132,7 +131,6 @@ static void i2c_slave_read_test(void) TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test", "[i2c][test_env=generic_multi_device][timeout=150]", i2c_master_write_test, i2c_slave_read_test); - static void master_read_slave_test(void) { uint8_t data_rd[DATA_LENGTH] = {0}; @@ -166,7 +164,7 @@ static void master_read_slave_test(void) vTaskDelay(100 / portTICK_PERIOD_MS); for (int i = 0; i < DATA_LENGTH; i++) { printf("%d\n", data_rd[i]); - TEST_ASSERT(data_rd[i]==i); + TEST_ASSERT(data_rd[i] == i); } unity_send_signal("ready to delete master read test"); @@ -205,7 +203,6 @@ static void slave_write_buffer_test(void) TEST_ESP_OK(i2c_del_slave_device(slave_handle)); } - TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=generic_multi_device][timeout=150]", master_read_slave_test, slave_write_buffer_test); static void i2c_master_write_read_test(void) @@ -313,7 +310,6 @@ static void i2c_slave_read_write_test(void) TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=generic_multi_device][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test); - static void i2c_master_repeat_write(void) { uint8_t data_wr[DATA_LENGTH] = {0}; diff --git a/components/driver/test_apps/i2c_test_apps/main/test_i2c_ram.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_ram.c similarity index 99% rename from components/driver/test_apps/i2c_test_apps/main/test_i2c_ram.c rename to components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_ram.c index 165d3afb3b0..084b60cffa1 100644 --- a/components/driver/test_apps/i2c_test_apps/main/test_i2c_ram.c +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_ram.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ - #include #include #include "sdkconfig.h" @@ -98,7 +97,6 @@ static void i2c_slave_read_from_ram_test(void) i2c_slave_dev_handle_t slave_handle; TEST_ESP_OK(i2c_new_slave_device(&i2c_slv_config, &slave_handle)); - unity_send_signal("i2c slave init finish"); unity_wait_for_signal("master write"); @@ -115,7 +113,6 @@ static void i2c_slave_read_from_ram_test(void) TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test - slave directly read from ram", "[i2c][test_env=generic_multi_device][timeout=150]", i2c_master_write_to_ram_test, i2c_slave_read_from_ram_test); - static void master_read_slave_from_ram_test(void) { uint8_t data_rd[DATA_LENGTH_RAM] = {0}; @@ -151,7 +148,7 @@ static void master_read_slave_from_ram_test(void) vTaskDelay(100 / portTICK_PERIOD_MS); for (int i = 0; i < DATA_LENGTH_RAM; i++) { printf("%d\n", data_rd[i]); - TEST_ASSERT(data_rd[i]==i); + TEST_ASSERT(data_rd[i] == i); } unity_send_signal("ready to delete ram test"); @@ -191,7 +188,6 @@ static void slave_write_buffer_to_ram_test(void) TEST_ESP_OK(i2c_del_slave_device(slave_handle)); } - TEST_CASE_MULTIPLE_DEVICES("I2C master read slave ram test", "[i2c][test_env=generic_multi_device][timeout=150]", master_read_slave_from_ram_test, slave_write_buffer_to_ram_test); TEST_CASE("I2C slave init as ram but read by fifo", "[i2c]") diff --git a/components/driver/test_apps/i2c_test_apps/pytest_i2c.py b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py similarity index 100% rename from components/driver/test_apps/i2c_test_apps/pytest_i2c.py rename to components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py diff --git a/components/driver/test_apps/i2c_test_apps/sdkconfig.ci.defaults b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.defaults similarity index 100% rename from components/driver/test_apps/i2c_test_apps/sdkconfig.ci.defaults rename to components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.defaults diff --git a/components/driver/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe rename to components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/i2c_test_apps/sdkconfig.ci.release b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/i2c_test_apps/sdkconfig.ci.release rename to components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release diff --git a/components/driver/test_apps/i2c_test_apps/sdkconfig.defaults b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/i2c_test_apps/sdkconfig.defaults rename to components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.defaults diff --git a/components/esp_driver_i2s/CMakeLists.txt b/components/esp_driver_i2s/CMakeLists.txt new file mode 100644 index 00000000000..e68980e63f3 --- /dev/null +++ b/components/esp_driver_i2s/CMakeLists.txt @@ -0,0 +1,26 @@ +idf_build_get_property(target IDF_TARGET) + +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() + +set(srcs) +set(include "include") + +# I2S related source files +if(CONFIG_SOC_I2S_SUPPORTED) + list(APPEND srcs "i2s_common.c" + "i2s_platform.c" + "i2s_std.c") + if(CONFIG_SOC_I2S_SUPPORTS_PDM) + list(APPEND srcs "i2s_pdm.c") + endif() + if(CONFIG_SOC_I2S_SUPPORTS_TDM) + list(APPEND srcs "i2s_tdm.c") + endif() +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${include} + PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm + ) diff --git a/components/esp_driver_i2s/Kconfig b/components/esp_driver_i2s/Kconfig new file mode 100644 index 00000000000..09a2014e488 --- /dev/null +++ b/components/esp_driver_i2s/Kconfig @@ -0,0 +1,22 @@ +menu "ESP-Driver:I2S Configurations" + depends on SOC_I2S_SUPPORTED + config I2S_ISR_IRAM_SAFE + bool "I2S ISR IRAM-Safe" + default n + help + Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be + executable when the cache is disabled (e.g. SPI Flash write). + + config I2S_SUPPRESS_DEPRECATE_WARN + bool "Suppress legacy driver deprecated warning" + default n + help + Enable this option will suppress the deprecation warnings of using APIs in legacy I2S driver. + + config I2S_ENABLE_DEBUG_LOG + bool "Enable I2S debug log" + default n + help + Wether to enable the debug log message for I2S driver. + Note that, this option only controls the I2S driver log, will not affect other drivers. +endmenu # I2S Configuration diff --git a/components/driver/i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c similarity index 98% rename from components/driver/i2s/i2s_common.c rename to components/esp_driver_i2s/i2s_common.c index 41b58a035a5..4e1c51519f4 100644 --- a/components/driver/i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -32,7 +32,6 @@ #if SOC_I2S_SUPPORTS_ADC_DAC #include "hal/adc_ll.h" -#include "driver/adc_i2s_legacy.h" #endif #if SOC_I2S_SUPPORTS_APLL #include "hal/clk_tree_ll.h" @@ -70,7 +69,8 @@ static const char *TAG = "i2s_common"; __attribute__((always_inline)) -inline void *i2s_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size) { +inline void *i2s_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size) +{ void *ptr = NULL; esp_dma_calloc(num, size, caps, &ptr, actual_size); return ptr; @@ -205,7 +205,7 @@ static i2s_controller_t *i2s_acquire_controller_obj(int id) portEXIT_CRITICAL(&g_i2s.spinlock); #if SOC_I2S_SUPPORTS_ADC_DAC if (id == I2S_NUM_0) { - adc_ll_digi_set_data_source(ADC_I2S_DATA_SRC_IO_SIG); + adc_ll_digi_set_data_source(0); } #endif } else { @@ -703,12 +703,12 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag) /* Initialize I2S module interrupt */ if (handle->dir == I2S_DIR_TX) { esp_intr_alloc_intrstatus(i2s_periph_signal[port_id].irq, intr_flag, - (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_TX_EVENT_MASK, - i2s_dma_tx_callback, handle, &handle->dma.dma_chan); + (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_TX_EVENT_MASK, + i2s_dma_tx_callback, handle, &handle->dma.dma_chan); } else { esp_intr_alloc_intrstatus(i2s_periph_signal[port_id].irq, intr_flag, - (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_RX_EVENT_MASK, - i2s_dma_rx_callback, handle, &handle->dma.dma_chan); + (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_RX_EVENT_MASK, + i2s_dma_rx_callback, handle, &handle->dma.dma_chan); } /* Start DMA */ i2s_ll_enable_dma(handle->controller->hal.dev, true); @@ -957,7 +957,7 @@ esp_err_t i2s_channel_get_info(i2s_chan_handle_t handle, i2s_chan_info_t *chan_i for (int i = 0; i < SOC_I2S_NUM; i++) { if (g_i2s.controller[i] != NULL) { if (g_i2s.controller[i]->tx_chan == handle || - g_i2s.controller[i]->rx_chan == handle) { + g_i2s.controller[i]->rx_chan == handle) { goto found; } } @@ -984,7 +984,6 @@ esp_err_t i2s_channel_get_info(i2s_chan_handle_t handle, i2s_chan_info_t *chan_i return ESP_OK; } - esp_err_t i2s_channel_enable(i2s_chan_handle_t handle) { I2S_NULL_POINTER_CHECK(TAG, handle); @@ -1064,7 +1063,7 @@ esp_err_t i2s_channel_preload_data(i2s_chan_handle_t tx_handle, const void *src, /* Loop until no bytes in source buff remain or the descriptors are full */ while (remain_bytes) { size_t bytes_can_load = remain_bytes > (tx_handle->dma.buf_size - tx_handle->dma.rw_pos) ? - (tx_handle->dma.buf_size - tx_handle->dma.rw_pos) : remain_bytes; + (tx_handle->dma.buf_size - tx_handle->dma.rw_pos) : remain_bytes; /* When all the descriptors has loaded data, no more bytes can be loaded, break directly */ if (bytes_can_load == 0) { break; @@ -1085,7 +1084,7 @@ esp_err_t i2s_channel_preload_data(i2s_chan_handle_t tx_handle, const void *src, * will remain at the end of the last dma buffer */ if (STAILQ_NEXT((lldesc_t *)tx_handle->dma.curr_desc, qe) != tx_handle->dma.desc[0]) { tx_handle->dma.curr_desc = STAILQ_NEXT((lldesc_t *)tx_handle->dma.curr_desc, qe); - tx_handle->dma.curr_ptr = (void *)(((lldesc_t *)tx_handle->dma.curr_desc)->buf); + tx_handle->dma.curr_ptr = (void *)(((lldesc_t *)tx_handle->dma.curr_desc)->buf); tx_handle->dma.rw_pos = 0; } else { break; diff --git a/components/driver/i2s/i2s_pdm.c b/components/esp_driver_i2s/i2s_pdm.c similarity index 99% rename from components/driver/i2s/i2s_pdm.c rename to components/esp_driver_i2s/i2s_pdm.c index 856cf43a1fc..e545ad08f80 100644 --- a/components/driver/i2s/i2s_pdm.c +++ b/components/esp_driver_i2s/i2s_pdm.c @@ -320,7 +320,6 @@ esp_err_t i2s_channel_reconfig_pdm_tx_gpio(i2s_chan_handle_t handle, const i2s_p #endif - /*--------------------------------------------------------------- PDM RX ---------------------------------------------------------------*/ diff --git a/components/driver/i2s/i2s_platform.c b/components/esp_driver_i2s/i2s_platform.c similarity index 93% rename from components/driver/i2s/i2s_platform.c rename to components/esp_driver_i2s/i2s_platform.c index 39d9e87cc29..07a49c1de33 100644 --- a/components/driver/i2s/i2s_platform.c +++ b/components/esp_driver_i2s/i2s_platform.c @@ -15,8 +15,8 @@ static const char *TAG = "i2s_platform"; */ i2s_platform_t g_i2s = { .spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED, - .controller[0 ... (SOC_I2S_NUM - 1)] = NULL, // groups will be lazy installed - .comp_name[0 ... (SOC_I2S_NUM - 1)] = NULL, + .controller[0 ...(SOC_I2S_NUM - 1)] = NULL, // groups will be lazy installed + .comp_name[0 ...(SOC_I2S_NUM - 1)] = NULL, }; /*--------------------------------------------------------------------------- @@ -74,5 +74,5 @@ size_t i2s_platform_get_dma_buffer_offset(void) { /* Force to transfer address '0' into 'i2s_chan_handle_t' type, * then find the corresponding field , the address of this field is the offset of this type */ - return (size_t)&(((i2s_chan_handle_t)0)->dma.bufs); + return (size_t) & (((i2s_chan_handle_t)0)->dma.bufs); } diff --git a/components/driver/i2s/i2s_private.h b/components/esp_driver_i2s/i2s_private.h similarity index 98% rename from components/driver/i2s/i2s_private.h rename to components/esp_driver_i2s/i2s_private.h index 0777091c85b..9a5877be0f4 100644 --- a/components/driver/i2s/i2s_private.h +++ b/components/esp_driver_i2s/i2s_private.h @@ -147,8 +147,8 @@ struct i2s_channel_obj_t { QueueHandle_t msg_queue; /*!< Message queue handler, used for transporting data between interrupt and read/write task */ i2s_event_callbacks_internal_t callbacks; /*!< Callback functions */ void *user_data; /*!< User data for callback functions */ - void (*start)(i2s_chan_handle_t); /*!< start tx/rx channel */ - void (*stop)(i2s_chan_handle_t); /*!< stop tx/rx channel */ + void (*start)(i2s_chan_handle_t); /*!< start tx/rx channel */ + void (*stop)(i2s_chan_handle_t); /*!< stop tx/rx channel */ }; /** diff --git a/components/driver/i2s/i2s_std.c b/components/esp_driver_i2s/i2s_std.c similarity index 99% rename from components/driver/i2s/i2s_std.c rename to components/esp_driver_i2s/i2s_std.c index 715ca04399a..73354e0c0fd 100644 --- a/components/driver/i2s/i2s_std.c +++ b/components/esp_driver_i2s/i2s_std.c @@ -147,8 +147,7 @@ static esp_err_t i2s_std_set_gpio(i2s_chan_handle_t handle, const i2s_std_gpio_c i2s_std_config_t *std_cfg = (i2s_std_config_t *)(handle->mode_info); /* Loopback if dout = din */ - if (gpio_cfg->dout != -1 && - gpio_cfg->dout == gpio_cfg->din) { + if (gpio_cfg->dout != -1 && gpio_cfg->dout == gpio_cfg->din) { i2s_gpio_loopback_set(gpio_cfg->dout, i2s_periph_signal[id].data_out_sig, i2s_periph_signal[id].data_in_sig); } else if (handle->dir == I2S_DIR_TX) { /* Set data output GPIO */ diff --git a/components/driver/i2s/i2s_tdm.c b/components/esp_driver_i2s/i2s_tdm.c similarity index 99% rename from components/driver/i2s/i2s_tdm.c rename to components/esp_driver_i2s/i2s_tdm.c index caed5c51a4f..f9c8cc25ef0 100644 --- a/components/driver/i2s/i2s_tdm.c +++ b/components/esp_driver_i2s/i2s_tdm.c @@ -152,7 +152,7 @@ static esp_err_t i2s_tdm_set_gpio(i2s_chan_handle_t handle, const i2s_tdm_gpio_c i2s_tdm_config_t *tdm_cfg = (i2s_tdm_config_t *)(handle->mode_info); /* Loopback if dout = din */ if (gpio_cfg->dout != -1 && - gpio_cfg->dout == gpio_cfg->din) { + gpio_cfg->dout == gpio_cfg->din) { i2s_gpio_loopback_set(gpio_cfg->dout, i2s_periph_signal[id].data_out_sig, i2s_periph_signal[id].data_in_sig); } else if (handle->dir == I2S_DIR_TX) { /* Set data output GPIO */ @@ -198,7 +198,6 @@ static esp_err_t i2s_tdm_set_gpio(i2s_chan_handle_t handle, const i2s_tdm_gpio_c return ESP_OK; } - esp_err_t i2s_channel_init_tdm_mode(i2s_chan_handle_t handle, const i2s_tdm_config_t *tdm_cfg) { #if CONFIG_I2S_ENABLE_DEBUG_LOG diff --git a/components/driver/i2s/include/driver/i2s_common.h b/components/esp_driver_i2s/include/driver/i2s_common.h similarity index 100% rename from components/driver/i2s/include/driver/i2s_common.h rename to components/esp_driver_i2s/include/driver/i2s_common.h diff --git a/components/driver/i2s/include/driver/i2s_pdm.h b/components/esp_driver_i2s/include/driver/i2s_pdm.h similarity index 99% rename from components/driver/i2s/include/driver/i2s_pdm.h rename to components/esp_driver_i2s/include/driver/i2s_pdm.h index 26efd8c06f2..e790dfb940a 100644 --- a/components/driver/i2s/include/driver/i2s_pdm.h +++ b/components/esp_driver_i2s/include/driver/i2s_pdm.h @@ -66,8 +66,6 @@ extern "C" { .bclk_div = 8, \ } - - /** * @brief I2S slot configuration for PDM RX mode */ @@ -190,10 +188,8 @@ esp_err_t i2s_channel_reconfig_pdm_rx_slot(i2s_chan_handle_t handle, const i2s_p */ esp_err_t i2s_channel_reconfig_pdm_rx_gpio(i2s_chan_handle_t handle, const i2s_pdm_rx_gpio_config_t *gpio_cfg); - #endif // SOC_I2S_SUPPORTS_PDM_RX - #if SOC_I2S_SUPPORTS_PDM_TX #if SOC_I2S_HW_VERSION_2 /** diff --git a/components/driver/i2s/include/driver/i2s_std.h b/components/esp_driver_i2s/include/driver/i2s_std.h similarity index 100% rename from components/driver/i2s/include/driver/i2s_std.h rename to components/esp_driver_i2s/include/driver/i2s_std.h diff --git a/components/driver/i2s/include/driver/i2s_tdm.h b/components/esp_driver_i2s/include/driver/i2s_tdm.h similarity index 99% rename from components/driver/i2s/include/driver/i2s_tdm.h rename to components/esp_driver_i2s/include/driver/i2s_tdm.h index b71f3be79de..a7a911b61dc 100644 --- a/components/driver/i2s/include/driver/i2s_tdm.h +++ b/components/esp_driver_i2s/include/driver/i2s_tdm.h @@ -113,7 +113,6 @@ extern "C" { I2S_TDM_PHILIPS_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo, mask) // Alias /** @endcond */ - /** * @brief I2S default TDM clock configuration * @note Please set the mclk_multiple to I2S_MCLK_MULTIPLE_384 while the data width in slot configuration is set to 24 bits @@ -258,7 +257,6 @@ esp_err_t i2s_channel_reconfig_tdm_slot(i2s_chan_handle_t handle, const i2s_tdm_ */ esp_err_t i2s_channel_reconfig_tdm_gpio(i2s_chan_handle_t handle, const i2s_tdm_gpio_config_t *gpio_cfg); - #ifdef __cplusplus } #endif diff --git a/components/driver/i2s/include/driver/i2s_types.h b/components/esp_driver_i2s/include/driver/i2s_types.h similarity index 100% rename from components/driver/i2s/include/driver/i2s_types.h rename to components/esp_driver_i2s/include/driver/i2s_types.h diff --git a/components/driver/include/esp_private/i2s_platform.h b/components/esp_driver_i2s/include/esp_private/i2s_platform.h similarity index 100% rename from components/driver/include/esp_private/i2s_platform.h rename to components/esp_driver_i2s/include/esp_private/i2s_platform.h diff --git a/components/driver/include/esp_private/i2s_sync.h b/components/esp_driver_i2s/include/esp_private/i2s_sync.h similarity index 100% rename from components/driver/include/esp_private/i2s_sync.h rename to components/esp_driver_i2s/include/esp_private/i2s_sync.h diff --git a/components/esp_driver_i2s/test_apps/.build-test-rules.yml b/components/esp_driver_i2s/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..855a23e9104 --- /dev/null +++ b/components/esp_driver_i2s/test_apps/.build-test-rules.yml @@ -0,0 +1,25 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_i2s/test_apps/i2s: + disable: + - if: SOC_I2S_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: lack of runners + depends_components: + - esp_driver_i2s + - esp_driver_gpio + - esp_driver_pcnt + +components/esp_driver_i2s/test_apps/i2s_multi_dev: + disable: + - if: SOC_I2S_SUPPORTED != 1 + - if: SOC_I2S_HW_VERSION_2 != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: lack of runners + depends_components: + - esp_driver_i2s + - esp_driver_gpio diff --git a/components/driver/test_apps/i2s_test_apps/i2s/CMakeLists.txt b/components/esp_driver_i2s/test_apps/i2s/CMakeLists.txt similarity index 87% rename from components/driver/test_apps/i2s_test_apps/i2s/CMakeLists.txt rename to components/esp_driver_i2s/test_apps/i2s/CMakeLists.txt index b65a90e79a6..13fa5a9dc0e 100644 --- a/components/driver/test_apps/i2s_test_apps/i2s/CMakeLists.txt +++ b/components/esp_driver_i2s/test_apps/i2s/CMakeLists.txt @@ -10,7 +10,7 @@ project(i2s_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i2s/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/i2s_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/i2s_test_apps/i2s/README.md b/components/esp_driver_i2s/test_apps/i2s/README.md similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/README.md rename to components/esp_driver_i2s/test_apps/i2s/README.md diff --git a/components/driver/test_apps/i2s_test_apps/i2s/main/CMakeLists.txt b/components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/main/CMakeLists.txt rename to components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt diff --git a/components/driver/test_apps/i2s_test_apps/i2s/main/test_app_main.c b/components/esp_driver_i2s/test_apps/i2s/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/main/test_app_main.c rename to components/esp_driver_i2s/test_apps/i2s/main/test_app_main.c diff --git a/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c similarity index 98% rename from components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c rename to components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c index 0cbe69b6ff6..eff30d9f1c6 100644 --- a/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c +++ b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c @@ -145,7 +145,7 @@ static void i2s_read_write_test(i2s_chan_handle_t tx_chan, i2s_chan_handle_t rx_ // test the read data right or not for (int i = 0, j = 0; i < (I2S_RECV_BUF_LEN - I2S_SEND_BUF_LEN); i++) { if (recv_buf[i] == 1) { - for (j = 1; (j < I2S_SEND_BUF_LEN) && (recv_buf[i+j] == j + 1); j++) {} + for (j = 1; (j < I2S_SEND_BUF_LEN) && (recv_buf[i + j] == j + 1); j++) {} if (j == I2S_SEND_BUF_LEN) { is_success = true; goto finish; @@ -217,7 +217,8 @@ TEST_CASE("I2S_basic_channel_allocation_reconfig_deleting_test", "[i2s]") static volatile bool task_run_flag; -static void i2s_read_task(void *args) { +static void i2s_read_task(void *args) +{ i2s_chan_handle_t rx_handle = (i2s_chan_handle_t)args; uint8_t *recv_buf = (uint8_t *)calloc(1, 2000); TEST_ASSERT(recv_buf); @@ -236,7 +237,8 @@ static void i2s_read_task(void *args) { vTaskDelete(NULL); } -static void i2s_write_task(void *args) { +static void i2s_write_task(void *args) +{ i2s_chan_handle_t tx_handle = (i2s_chan_handle_t)args; uint8_t *send_buf = (uint8_t *)calloc(1, 2000); TEST_ASSERT(send_buf); @@ -255,7 +257,8 @@ static void i2s_write_task(void *args) { vTaskDelete(NULL); } -static void i2s_reconfig_task(void *args) { +static void i2s_reconfig_task(void *args) +{ i2s_chan_handle_t tx_handle = (i2s_chan_handle_t)args; i2s_chan_info_t chan_info; TEST_ESP_OK(i2s_channel_get_info(tx_handle, &chan_info)); @@ -374,8 +377,8 @@ static bool whether_contains_exapected_data(uint16_t *src, uint32_t src_len, uin if (src[i] == val) { if (val == start_val && i < src_len - 8) { printf("start index: %d ---> \n%d %d %d %d %d %d %d %d\n", i, - src[i], src[i+1], src[i+2], src[i+3], - src[i+4], src[i+5], src[i+6], src[i+7]); + src[i], src[i + 1], src[i + 2], src[i + 3], + src[i + 4], src[i + 5], src[i + 6], src[i + 7]); } index_step = src_step; val += val_step; @@ -443,7 +446,7 @@ TEST_CASE("I2S_mono_stereo_loopback_test", "[i2s]") size_t r_bytes = 0; uint32_t retry = 0; for (int n = 0; n < WRITE_BUF_LEN / 2; n++) { - w_buf[n] = n%100; + w_buf[n] = n % 100; } /* rx right mono test @@ -456,8 +459,8 @@ TEST_CASE("I2S_mono_stereo_loopback_test", "[i2s]") /* The data of tx/rx channels are flipped on ESP32 */ for (int n = 0; n < READ_BUF_LEN / 2; n += 2) { int16_t temp = r_buf[n]; - r_buf[n] = r_buf[n+1]; - r_buf[n+1] = temp; + r_buf[n] = r_buf[n + 1]; + r_buf[n + 1] = temp; } #endif /* Expected: 1 3 5 7 9 ... 97 99 */ @@ -488,8 +491,8 @@ TEST_CASE("I2S_mono_stereo_loopback_test", "[i2s]") /* The data of tx/rx channels are flipped on ESP32 */ for (int n = 0; n < READ_BUF_LEN / 2; n += 2) { int16_t temp = r_buf[n]; - r_buf[n] = r_buf[n+1]; - r_buf[n+1] = temp; + r_buf[n] = r_buf[n + 1]; + r_buf[n + 1] = temp; } #endif /* Expected: 2 4 6 8 10 ... 96 98 */ @@ -750,7 +753,8 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c const uint32_t test_freq[] = { 8000, 10000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 64000, 88200, - 96000, 128000,144000,196000}; + 96000, 128000, 144000, 196000 + }; int real_pulse = 0; int case_cnt = sizeof(test_freq) / sizeof(uint32_t); #if SOC_I2S_SUPPORTS_PLL_F96M @@ -853,7 +857,7 @@ TEST_CASE("I2S_package_lost_test", "[i2s]") * interrupt_interval = dma_frame_num / sample_rate = 3.549 ms * 2. dma_desc_num > polling_cycle / interrupt_interval = cell(2.818) = 3 * 3. recv_buffer_size > dma_desc_num * dma_buffer_size = 3 * 4092 = 12276 bytes */ - #define TEST_RECV_BUF_LEN 12276 +#define TEST_RECV_BUF_LEN 12276 i2s_chan_handle_t rx_handle; i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_AUTO, I2S_ROLE_MASTER); diff --git a/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s_iram.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s_iram.c similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s_iram.c rename to components/esp_driver_i2s/test_apps/i2s/main/test_i2s_iram.c diff --git a/components/driver/test_apps/i2s_test_apps/i2s/pytest_i2s.py b/components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/pytest_i2s.py rename to components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py diff --git a/components/driver/test_apps/i2s_test_apps/i2s/sdkconfig.ci.iram_safe b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/sdkconfig.ci.iram_safe rename to components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/i2s_test_apps/i2s/sdkconfig.ci.release b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/sdkconfig.ci.release rename to components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.release diff --git a/components/driver/test_apps/i2s_test_apps/i2s/sdkconfig.defaults b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s/sdkconfig.defaults rename to components/esp_driver_i2s/test_apps/i2s/sdkconfig.defaults diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/CMakeLists.txt b/components/esp_driver_i2s/test_apps/i2s_multi_dev/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/CMakeLists.txt rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/CMakeLists.txt diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/README.md b/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/README.md rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/CMakeLists.txt b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/CMakeLists.txt rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/main/CMakeLists.txt diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/test_app_main.c b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/test_app_main.c rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_app_main.c diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c similarity index 94% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c index 4a26b391b5e..18a7092511a 100644 --- a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c @@ -28,7 +28,7 @@ static const char *TAG = "i2s_multi_dev_test"; #define TEST_I2S_FRAME_TIMEOUT_SEC (10.0f) // Timeout seconds of waiting for a correct frame #define TEST_I2S_NUM (I2S_NUM_0) // ESP32-C3 has only I2S0 -#define TEST_I2S_MCK_IO (GPIO_NUM_0) +#define TEST_I2S_MCK_IO (GPIO_NUM_1) #define TEST_I2S_BCK_IO (GPIO_NUM_4) #define TEST_I2S_WS_IO (GPIO_NUM_5) #if CONFIG_IDF_TARGET_ESP32H2 @@ -208,8 +208,7 @@ static void test_i2s_tdm_slave_48k_32bits_4slots(void) } TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_32bits_4slots", "[I2S_TDM]", - test_i2s_tdm_master_48k_32bits_4slots, test_i2s_tdm_slave_48k_32bits_4slots); - + test_i2s_tdm_master_48k_32bits_4slots, test_i2s_tdm_slave_48k_32bits_4slots); static void test_i2s_tdm_master_48k_16bits_4slots(void) { @@ -222,8 +221,7 @@ static void test_i2s_tdm_slave_48k_16bits_4slots(void) } TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_16bits_4slots", "[I2S_TDM]", - test_i2s_tdm_master_48k_16bits_4slots, test_i2s_tdm_slave_48k_16bits_4slots); - + test_i2s_tdm_master_48k_16bits_4slots, test_i2s_tdm_slave_48k_16bits_4slots); static void test_i2s_tdm_master_48k_8bits_4slots(void) { @@ -236,7 +234,7 @@ static void test_i2s_tdm_slave_48k_8bits_4slots(void) } TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_8bits_4slots", "[I2S_TDM]", - test_i2s_tdm_master_48k_8bits_4slots, test_i2s_tdm_slave_48k_8bits_4slots); + test_i2s_tdm_master_48k_8bits_4slots, test_i2s_tdm_slave_48k_8bits_4slots); /* The I2S source clock can only reach 96Mhz on ESP32H2, which can't satisfy the following configurations in slave mode */ @@ -250,12 +248,11 @@ static void test_i2s_tdm_master_48k_16bits_8slots(void) static void test_i2s_tdm_slave_48k_16bits_8slots(void) { test_i2s_tdm_slave(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3 | - I2S_TDM_SLOT4 | I2S_TDM_SLOT5 | I2S_TDM_SLOT6 | I2S_TDM_SLOT7); + I2S_TDM_SLOT4 | I2S_TDM_SLOT5 | I2S_TDM_SLOT6 | I2S_TDM_SLOT7); } TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_16bits_8slots", "[I2S_TDM]", - test_i2s_tdm_master_48k_16bits_8slots, test_i2s_tdm_slave_48k_16bits_8slots); - + test_i2s_tdm_master_48k_16bits_8slots, test_i2s_tdm_slave_48k_16bits_8slots); static void test_i2s_tdm_master_96k_16bits_4slots(void) { @@ -268,7 +265,7 @@ static void test_i2s_tdm_slave_96k_16bits_4slots(void) } TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_96k_16bits_4slots", "[I2S_TDM]", - test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_4slots); + test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_4slots); #endif // !CONFIG_IDF_TARGET_ESP32H2 static void test_i2s_external_clk_src(bool is_master, bool is_external) @@ -344,7 +341,7 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external) // Check the data for (int i = 0; i < TEST_I2S_ARRAY_LENGTH; i++) { if (recv_buff[i] == 0x12 && recv_buff[i + 1] == 0x34 && - recv_buff[i + 2] == 0x56 && recv_buff[i + 3] == 0x78) { + recv_buff[i + 2] == 0x56 && recv_buff[i + 3] == 0x78) { is_success = true; break; } @@ -378,7 +375,7 @@ static void test_i2s_slave_clock_in(void) } TEST_CASE_MULTIPLE_DEVICES("I2S_external_clock_master_output_slave_input", "[I2S]", - test_i2s_master_clock_out, test_i2s_slave_clock_in); + test_i2s_master_clock_out, test_i2s_slave_clock_in); static void test_i2s_master_clock_in(void) { @@ -391,4 +388,4 @@ static void test_i2s_slave_clock_out(void) } TEST_CASE_MULTIPLE_DEVICES("I2S_external_clock_master_input_slave_output", "[I2S]", - test_i2s_master_clock_in, test_i2s_slave_clock_out); + test_i2s_master_clock_in, test_i2s_slave_clock_out); diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py diff --git a/components/driver/test_apps/i2s_test_apps/i2s_multi_dev/sdkconfig.defaults b/components/esp_driver_i2s/test_apps/i2s_multi_dev/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/i2s_test_apps/i2s_multi_dev/sdkconfig.defaults rename to components/esp_driver_i2s/test_apps/i2s_multi_dev/sdkconfig.defaults diff --git a/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h b/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h new file mode 100644 index 00000000000..d6616c40fb7 --- /dev/null +++ b/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SAMPLE_RATE (48000) +#define SAMPLE_BITS (16) + +#if CONFIG_IDF_TARGET_ESP32 +#define MASTER_MCK_IO 0 +#define MASTER_BCK_IO 4 +#define MASTER_WS_IO 5 +#define SLAVE_BCK_IO 21 +#define SLAVE_WS_IO 22 +#define DATA_IN_IO 19 +#define DATA_OUT_IO 18 +#elif CONFIG_IDF_TARGET_ESP32S2 +#define MASTER_MCK_IO 0 +#define MASTER_BCK_IO 4 +#define MASTER_WS_IO 5 +#define SLAVE_BCK_IO 14 +#define SLAVE_WS_IO 15 +#define DATA_IN_IO 19 +#define DATA_OUT_IO 18 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define MASTER_MCK_IO 0 +#define MASTER_BCK_IO 4 +#define MASTER_WS_IO 5 +#define SLAVE_BCK_IO 14 +#define SLAVE_WS_IO 15 +#define DATA_IN_IO 19 +#define DATA_OUT_IO 18 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define MASTER_MCK_IO 0 +#define MASTER_BCK_IO 4 +#define MASTER_WS_IO 5 +#define SLAVE_BCK_IO 14 +#define SLAVE_WS_IO 15 +#define DATA_IN_IO 19 +#define DATA_OUT_IO 18 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define MASTER_MCK_IO 34 +#define MASTER_BCK_IO 35 +#define MASTER_WS_IO 48 +#define SLAVE_BCK_IO 10 +#define SLAVE_WS_IO 11 +#define DATA_IN_IO 12 +#define DATA_OUT_IO 49 +#else +#define MASTER_MCK_IO 0 +#define MASTER_BCK_IO 4 +#define MASTER_WS_IO 5 +#define SLAVE_BCK_IO 2 +#define SLAVE_WS_IO 3 +#define DATA_IN_IO 6 +#define DATA_OUT_IO 7 +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_mcpwm/CMakeLists.txt b/components/esp_driver_mcpwm/CMakeLists.txt new file mode 100644 index 00000000000..15483918a48 --- /dev/null +++ b/components/esp_driver_mcpwm/CMakeLists.txt @@ -0,0 +1,21 @@ +set(srcs) +set(public_include "include") +if(CONFIG_SOC_MCPWM_SUPPORTED) + list(APPEND srcs "src/mcpwm_cap.c" + "src/mcpwm_cmpr.c" + "src/mcpwm_com.c" + "src/mcpwm_fault.c" + "src/mcpwm_gen.c" + "src/mcpwm_oper.c" + "src/mcpwm_sync.c" + "src/mcpwm_timer.c") + if(CONFIG_SOC_MCPWM_SUPPORT_ETM) + list(APPEND srcs "src/mcpwm_etm.c") + endif() +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES "esp_pm" "esp_driver_gpio" + LDFRAGMENTS "linker.lf" + ) diff --git a/components/driver/mcpwm/Kconfig.mcpwm b/components/esp_driver_mcpwm/Kconfig similarity index 96% rename from components/driver/mcpwm/Kconfig.mcpwm rename to components/esp_driver_mcpwm/Kconfig index b1a7fd8c810..0b5bb37bdd9 100644 --- a/components/driver/mcpwm/Kconfig.mcpwm +++ b/components/esp_driver_mcpwm/Kconfig @@ -1,4 +1,4 @@ -menu "MCPWM Configuration" +menu "ESP-Driver:MCPWM Configurations" depends on SOC_MCPWM_SUPPORTED config MCPWM_ISR_IRAM_SAFE bool "Place MCPWM ISR function into IRAM" @@ -30,4 +30,4 @@ menu "MCPWM Configuration" help Wether to enable the debug log message for MCPWM driver. Note that, this option only controls the MCPWM driver log, won't affect other drivers. -endmenu # MCPWM Configuration +endmenu diff --git a/components/driver/mcpwm/include/driver/mcpwm_cap.h b/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h similarity index 99% rename from components/driver/mcpwm/include/driver/mcpwm_cap.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_cap.h index 4fa50c657fb..0d94f009211 100644 --- a/components/driver/mcpwm/include/driver/mcpwm_cap.h +++ b/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h @@ -136,7 +136,9 @@ typedef struct { int intr_priority; /*!< MCPWM capture interrupt priority, if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3) */ uint32_t prescale; /*!< Prescale of input signal, effective frequency = cap_input_clk/prescale */ - struct { + + /// Extra configuration flags for capture channel + struct extra_flags { uint32_t pos_edge: 1; /*!< Whether to capture on positive edge */ uint32_t neg_edge: 1; /*!< Whether to capture on negative edge */ uint32_t pull_up: 1; /*!< Whether to pull up internally */ diff --git a/components/driver/mcpwm/include/driver/mcpwm_cmpr.h b/components/esp_driver_mcpwm/include/driver/mcpwm_cmpr.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_cmpr.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_cmpr.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_etm.h b/components/esp_driver_mcpwm/include/driver/mcpwm_etm.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_etm.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_etm.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_fault.h b/components/esp_driver_mcpwm/include/driver/mcpwm_fault.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_fault.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_fault.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_gen.h b/components/esp_driver_mcpwm/include/driver/mcpwm_gen.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_gen.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_gen.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_oper.h b/components/esp_driver_mcpwm/include/driver/mcpwm_oper.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_oper.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_oper.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_prelude.h b/components/esp_driver_mcpwm/include/driver/mcpwm_prelude.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_prelude.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_prelude.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_sync.h b/components/esp_driver_mcpwm/include/driver/mcpwm_sync.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_sync.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_sync.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_timer.h b/components/esp_driver_mcpwm/include/driver/mcpwm_timer.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_timer.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_timer.h diff --git a/components/driver/mcpwm/include/driver/mcpwm_types.h b/components/esp_driver_mcpwm/include/driver/mcpwm_types.h similarity index 100% rename from components/driver/mcpwm/include/driver/mcpwm_types.h rename to components/esp_driver_mcpwm/include/driver/mcpwm_types.h diff --git a/components/driver/include/esp_private/mcpwm.h b/components/esp_driver_mcpwm/include/esp_private/mcpwm.h similarity index 100% rename from components/driver/include/esp_private/mcpwm.h rename to components/esp_driver_mcpwm/include/esp_private/mcpwm.h diff --git a/components/driver/mcpwm/linker.lf b/components/esp_driver_mcpwm/linker.lf similarity index 85% rename from components/driver/mcpwm/linker.lf rename to components/esp_driver_mcpwm/linker.lf index ccc448ea74f..7729fa00f11 100644 --- a/components/driver/mcpwm/linker.lf +++ b/components/esp_driver_mcpwm/linker.lf @@ -1,5 +1,5 @@ [mapping:mcpwm_driver] -archive: libdriver.a +archive: libesp_driver_mcpwm.a entries: if MCPWM_CTRL_FUNC_IN_IRAM = y: mcpwm_cmpr: mcpwm_comparator_set_compare_value (noflash) diff --git a/components/driver/mcpwm/mcpwm_cap.c b/components/esp_driver_mcpwm/src/mcpwm_cap.c similarity index 98% rename from components/driver/mcpwm/mcpwm_cap.c rename to components/esp_driver_mcpwm/src/mcpwm_cap.c index fda51f38c85..d369530005f 100644 --- a/components/driver/mcpwm/mcpwm_cap.c +++ b/components/esp_driver_mcpwm/src/mcpwm_cap.c @@ -392,8 +392,8 @@ esp_err_t mcpwm_capture_channel_register_event_callbacks(mcpwm_cap_channel_handl int isr_flags = MCPWM_INTR_ALLOC_FLAG; isr_flags |= mcpwm_get_intr_priority_flag(group); ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, - (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_CAPTURE(cap_chan_id), - mcpwm_capture_default_isr, cap_channel, &cap_channel->intr), TAG, "install interrupt service for cap channel failed"); + (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_CAPTURE(cap_chan_id), + mcpwm_capture_default_isr, cap_channel, &cap_channel->intr), TAG, "install interrupt service for cap channel failed"); } portENTER_CRITICAL(&group->spinlock); diff --git a/components/driver/mcpwm/mcpwm_cmpr.c b/components/esp_driver_mcpwm/src/mcpwm_cmpr.c similarity index 97% rename from components/driver/mcpwm/mcpwm_cmpr.c rename to components/esp_driver_mcpwm/src/mcpwm_cmpr.c index 1fccdc7d064..307d0b026c0 100644 --- a/components/driver/mcpwm/mcpwm_cmpr.c +++ b/components/esp_driver_mcpwm/src/mcpwm_cmpr.c @@ -255,8 +255,8 @@ esp_err_t mcpwm_comparator_register_event_callbacks(mcpwm_cmpr_handle_t cmpr, co int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ ESP_INTR_FLAG_INTRDISABLED; isr_flags |= mcpwm_get_intr_priority_flag(group); ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, - (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_CMP_EQUAL(oper_id, cmpr_id), - mcpwm_comparator_default_isr, oper_cmpr, &oper_cmpr->intr), TAG, "install interrupt service for comparator failed"); + (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_CMP_EQUAL(oper_id, cmpr_id), + mcpwm_comparator_default_isr, oper_cmpr, &oper_cmpr->intr), TAG, "install interrupt service for comparator failed"); } portENTER_CRITICAL(&group->spinlock); diff --git a/components/driver/mcpwm/mcpwm_com.c b/components/esp_driver_mcpwm/src/mcpwm_com.c similarity index 100% rename from components/driver/mcpwm/mcpwm_com.c rename to components/esp_driver_mcpwm/src/mcpwm_com.c diff --git a/components/driver/mcpwm/mcpwm_etm.c b/components/esp_driver_mcpwm/src/mcpwm_etm.c similarity index 100% rename from components/driver/mcpwm/mcpwm_etm.c rename to components/esp_driver_mcpwm/src/mcpwm_etm.c diff --git a/components/driver/mcpwm/mcpwm_fault.c b/components/esp_driver_mcpwm/src/mcpwm_fault.c similarity index 97% rename from components/driver/mcpwm/mcpwm_fault.c rename to components/esp_driver_mcpwm/src/mcpwm_fault.c index 52070ca7123..5961b1eec80 100644 --- a/components/driver/mcpwm/mcpwm_fault.c +++ b/components/esp_driver_mcpwm/src/mcpwm_fault.c @@ -255,8 +255,8 @@ esp_err_t mcpwm_fault_register_event_callbacks(mcpwm_fault_handle_t fault, const int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ESP_INTR_FLAG_INTRDISABLED; isr_flags |= mcpwm_get_intr_priority_flag(group); ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, - (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_FAULT_MASK(fault_id), - mcpwm_gpio_fault_default_isr, gpio_fault, &gpio_fault->intr), TAG, "install interrupt service for gpio fault failed"); + (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_FAULT_MASK(fault_id), + mcpwm_gpio_fault_default_isr, gpio_fault, &gpio_fault->intr), TAG, "install interrupt service for gpio fault failed"); } // different mcpwm events share the same interrupt control register diff --git a/components/driver/mcpwm/mcpwm_gen.c b/components/esp_driver_mcpwm/src/mcpwm_gen.c similarity index 94% rename from components/driver/mcpwm/mcpwm_gen.c rename to components/esp_driver_mcpwm/src/mcpwm_gen.c index 47db3f176f4..f4ae4597455 100644 --- a/components/driver/mcpwm/mcpwm_gen.c +++ b/components/esp_driver_mcpwm/src/mcpwm_gen.c @@ -167,7 +167,7 @@ esp_err_t mcpwm_generator_set_action_on_timer_event(mcpwm_gen_handle_t gen, mcpw ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TAG, "UTEP and DTEZ can't be reached under MCPWM_TIMER_COUNT_MODE_UP_DOWN mode"); } mcpwm_ll_generator_set_action_on_timer_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act.direction, ev_act.event, ev_act.action); + ev_act.direction, ev_act.event, ev_act.action); return ESP_OK; } @@ -195,7 +195,7 @@ esp_err_t mcpwm_generator_set_actions_on_timer_event(mcpwm_gen_handle_t gen, mcp ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TAG, "UTEP and DTEZ can't be reached under MCPWM_TIMER_COUNT_MODE_UP_DOWN mode"); } mcpwm_ll_generator_set_action_on_timer_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act_itor.direction, ev_act_itor.event, ev_act_itor.action); + ev_act_itor.direction, ev_act_itor.event, ev_act_itor.action); ev_act_itor = va_arg(it, mcpwm_gen_timer_event_action_t); } va_end(it); @@ -209,7 +209,7 @@ esp_err_t mcpwm_generator_set_action_on_compare_event(mcpwm_gen_handle_t gen, mc mcpwm_oper_t *oper = gen->oper; mcpwm_group_t *group = oper->group; mcpwm_ll_generator_set_action_on_compare_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act.direction, ev_act.comparator->cmpr_id, ev_act.action); + ev_act.direction, ev_act.comparator->cmpr_id, ev_act.action); return ESP_OK; } @@ -223,7 +223,7 @@ esp_err_t mcpwm_generator_set_actions_on_compare_event(mcpwm_gen_handle_t gen, m va_start(it, ev_act); while (ev_act_itor.comparator) { mcpwm_ll_generator_set_action_on_compare_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act_itor.direction, ev_act_itor.comparator->cmpr_id, ev_act_itor.action); + ev_act_itor.direction, ev_act_itor.comparator->cmpr_id, ev_act_itor.action); ev_act_itor = va_arg(it, mcpwm_gen_compare_event_action_t); } va_end(it); @@ -237,7 +237,7 @@ esp_err_t mcpwm_generator_set_action_on_brake_event(mcpwm_gen_handle_t gen, mcpw mcpwm_oper_t *oper = gen->oper; mcpwm_group_t *group = oper->group; mcpwm_ll_generator_set_action_on_brake_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act.direction, ev_act.brake_mode, ev_act.action); + ev_act.direction, ev_act.brake_mode, ev_act.action); return ESP_OK; } @@ -251,7 +251,7 @@ esp_err_t mcpwm_generator_set_actions_on_brake_event(mcpwm_gen_handle_t gen, mcp va_start(it, ev_act); while (ev_act_itor.brake_mode != MCPWM_OPER_BRAKE_MODE_INVALID) { mcpwm_ll_generator_set_action_on_brake_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act_itor.direction, ev_act_itor.brake_mode, ev_act_itor.action); + ev_act_itor.direction, ev_act_itor.brake_mode, ev_act_itor.action); ev_act_itor = va_arg(it, mcpwm_gen_brake_event_action_t); } va_end(it); @@ -280,7 +280,7 @@ esp_err_t mcpwm_generator_set_action_on_fault_event(mcpwm_gen_handle_t gen, mcpw mcpwm_gpio_fault_t *gpio_fault = __containerof(fault, mcpwm_gpio_fault_t, base); mcpwm_ll_operator_set_trigger_from_gpio_fault(group->hal.dev, oper->oper_id, trigger_id, gpio_fault->fault_id); mcpwm_ll_generator_set_action_on_trigger_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act.direction, trigger_id, ev_act.action); + ev_act.direction, trigger_id, ev_act.action); return ESP_OK; } @@ -297,7 +297,8 @@ esp_err_t mcpwm_generator_set_action_on_sync_event(mcpwm_gen_handle_t gen, mcpwm if (oper->triggers[i] == MCPWM_TRIGGER_SYNC_EVENT) { trigger_sync_used = 1; break; - } else if (oper->triggers[i] == MCPWM_TRIGGER_NO_ASSIGN) { + } + if (oper->triggers[i] == MCPWM_TRIGGER_NO_ASSIGN) { trigger_id = i; oper->triggers[i] = MCPWM_TRIGGER_SYNC_EVENT; break; @@ -308,7 +309,7 @@ esp_err_t mcpwm_generator_set_action_on_sync_event(mcpwm_gen_handle_t gen, mcpwm ESP_RETURN_ON_FALSE(trigger_id >= 0, ESP_ERR_NOT_FOUND, TAG, "no free trigger in operator (%d,%d)", group->group_id, oper->oper_id); mcpwm_ll_operator_set_trigger_from_sync(group->hal.dev, oper->oper_id, trigger_id); mcpwm_ll_generator_set_action_on_trigger_event(group->hal.dev, oper->oper_id, gen->gen_id, - ev_act.direction, trigger_id, ev_act.action); + ev_act.direction, trigger_id, ev_act.action); return ESP_OK; } diff --git a/components/driver/mcpwm/mcpwm_oper.c b/components/esp_driver_mcpwm/src/mcpwm_oper.c similarity index 98% rename from components/driver/mcpwm/mcpwm_oper.c rename to components/esp_driver_mcpwm/src/mcpwm_oper.c index 27167d477e1..ce8d3a7f091 100644 --- a/components/driver/mcpwm/mcpwm_oper.c +++ b/components/esp_driver_mcpwm/src/mcpwm_oper.c @@ -258,8 +258,8 @@ esp_err_t mcpwm_operator_register_event_callbacks(mcpwm_oper_handle_t oper, cons int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ ESP_INTR_FLAG_INTRDISABLED; isr_flags |= mcpwm_get_intr_priority_flag(group); ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, - (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_OPER_MASK(oper_id), - mcpwm_operator_default_isr, oper, &oper->intr), TAG, "install interrupt service for operator failed"); + (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_OPER_MASK(oper_id), + mcpwm_operator_default_isr, oper, &oper->intr), TAG, "install interrupt service for operator failed"); } // enable/disable interrupt events diff --git a/components/driver/mcpwm/mcpwm_private.h b/components/esp_driver_mcpwm/src/mcpwm_private.h similarity index 100% rename from components/driver/mcpwm/mcpwm_private.h rename to components/esp_driver_mcpwm/src/mcpwm_private.h diff --git a/components/driver/mcpwm/mcpwm_sync.c b/components/esp_driver_mcpwm/src/mcpwm_sync.c similarity index 100% rename from components/driver/mcpwm/mcpwm_sync.c rename to components/esp_driver_mcpwm/src/mcpwm_sync.c diff --git a/components/driver/mcpwm/mcpwm_timer.c b/components/esp_driver_mcpwm/src/mcpwm_timer.c similarity index 100% rename from components/driver/mcpwm/mcpwm_timer.c rename to components/esp_driver_mcpwm/src/mcpwm_timer.c diff --git a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..cbc941233cd --- /dev/null +++ b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_mcpwm/test_apps/mcpwm: + disable: + - if: SOC_MCPWM_SUPPORTED != 1 + depends_components: + - esp_driver_mcpwm diff --git a/components/driver/test_apps/mcpwm/CMakeLists.txt b/components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt similarity index 87% rename from components/driver/test_apps/mcpwm/CMakeLists.txt rename to components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt index 9e9a606d463..9bd915a8ce1 100644 --- a/components/driver/test_apps/mcpwm/CMakeLists.txt +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt @@ -10,7 +10,7 @@ project(mcpwm_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_mcpwm/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/mcpwm_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/mcpwm/README.md b/components/esp_driver_mcpwm/test_apps/mcpwm/README.md similarity index 100% rename from components/driver/test_apps/mcpwm/README.md rename to components/esp_driver_mcpwm/test_apps/mcpwm/README.md diff --git a/components/driver/test_apps/mcpwm/main/CMakeLists.txt b/components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt similarity index 88% rename from components/driver/test_apps/mcpwm/main/CMakeLists.txt rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt index 6cf3fe2cf4c..119892a0b4d 100644 --- a/components/driver/test_apps/mcpwm/main/CMakeLists.txt +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt @@ -16,5 +16,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver + PRIV_REQUIRES unity esp_driver_mcpwm esp_driver_gpio WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/mcpwm/main/test_app_main.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_app_main.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_app_main.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cmpr.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cmpr.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_common.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_common.c similarity index 99% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_common.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_common.c index f31efcc65aa..7ec047b4543 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_common.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_common.c @@ -163,7 +163,6 @@ TEST_CASE("mcpwm_group_set_prescale_dynamically", "[mcpwm]") carrier_config.first_pulse_duration_us = 5; TEST_ESP_OK(mcpwm_operator_apply_carrier(oper, &carrier_config)); - TEST_ESP_OK(mcpwm_del_generator(generator)); TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_fault.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_fault.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c similarity index 78% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c index f4a6fef3865..1a11325503e 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c @@ -170,7 +170,7 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") TEST_ESP_OK(mcpwm_generator_set_force_level(generator, 0, false)); TEST_ASSERT_EQUAL(0, gpio_get_level(gen_gpio)); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(generator, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); // generator should output high level on tez event, the previous force level should disappear TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); vTaskDelay(pdMS_TO_TICKS(200)); @@ -181,7 +181,7 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") TEST_ESP_OK(mcpwm_generator_set_force_level(generator, 1, false)); TEST_ASSERT_EQUAL(1, gpio_get_level(gen_gpio)); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(generator, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); // generator should output low level on tez event, the previous force level should disappear TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); vTaskDelay(pdMS_TO_TICKS(200)); @@ -230,9 +230,9 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]") printf("set generator to output high on timer full\r\n"); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_KEEP), - MCPWM_GEN_TIMER_EVENT_ACTION_END())); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_KEEP), + MCPWM_GEN_TIMER_EVENT_ACTION_END())); printf("start timer\r\n"); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); vTaskDelay(pdMS_TO_TICKS(100)); @@ -242,9 +242,9 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]") printf("set generator to output low on timer full\r\n"); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_KEEP), - MCPWM_GEN_TIMER_EVENT_ACTION_END())); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_KEEP), + MCPWM_GEN_TIMER_EVENT_ACTION_END())); printf("start timer\r\n"); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); vTaskDelay(pdMS_TO_TICKS(100)); @@ -262,7 +262,7 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]") typedef void (*set_gen_actions_cb_t)(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb); static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t period, mcpwm_timer_count_mode_t count_mode, - uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, set_gen_actions_cb_t set_generator_actions) + uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, set_gen_actions_cb_t set_generator_actions) { mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -321,72 +321,72 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p static void single_edge_active_high(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); } static void single_edge_active_low(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_HIGH))); } static void pulse_placement(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_TOGGLE), - MCPWM_GEN_TIMER_EVENT_ACTION_END())); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_TOGGLE), + MCPWM_GEN_TIMER_EVENT_ACTION_END())); } static void dual_edge_active_low_asym(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpb, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpb, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_TIMER_EVENT_ACTION_END())); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_TIMER_EVENT_ACTION_END())); } static void dual_edge_active_low_sym(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpa, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpa, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpb, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpb, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); } static void dual_edge_complementary(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpa, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpa, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpb, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_DOWN, cmpb, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); } TEST_CASE("mcpwm_generator_action_on_compare_event", "[mcpwm]") @@ -425,7 +425,7 @@ TEST_CASE("mcpwm_generator_action_on_compare_event", "[mcpwm]") typedef void (*set_dead_time_cb_t)(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb); static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t period, uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, - set_gen_actions_cb_t set_generator_actions, set_dead_time_cb_t set_dead_time) + set_gen_actions_cb_t set_generator_actions, set_dead_time_cb_t set_dead_time) { mcpwm_timer_config_t timer_config = { .group_id = 0, @@ -485,9 +485,9 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per static void ahc_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); } static void ahc_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -506,9 +506,9 @@ static void ahc_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) static void alc_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); } static void alc_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -528,9 +528,9 @@ static void alc_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) static void ah_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); } static void ah_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -548,9 +548,9 @@ static void ah_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) static void al_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); } static void al_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -569,13 +569,13 @@ static void al_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) static void reda_only_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); } static void reda_only_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -594,13 +594,13 @@ static void reda_only_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t static void fedb_only_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); } static void fedb_only_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -620,13 +620,13 @@ static void fedb_only_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t static void redfedb_only_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb) { TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpa, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, cmpb, MCPWM_GEN_ACTION_LOW))); } static void redfedb_only_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb) @@ -727,9 +727,9 @@ TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]") printf("set generator actions on timer and compare events\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gen, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gen, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW))); printf("start timer\r\n"); TEST_ESP_OK(mcpwm_timer_enable(timer)); @@ -769,6 +769,15 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") const int generator_gpio = 0; const int fault_gpio_num[3] = {2, 4, 5}; printf("create timer and operator\r\n"); + mcpwm_timer_config_t timer_config = { + .group_id = 0, + .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, + .resolution_hz = 1000000, + .count_mode = MCPWM_TIMER_COUNT_MODE_UP, + .period_ticks = 1000, + }; + mcpwm_timer_handle_t timer = NULL; + TEST_ESP_OK(mcpwm_new_timer(&timer_config, &timer)); mcpwm_operator_config_t oper_config = { .group_id = 0, @@ -776,6 +785,9 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") mcpwm_oper_handle_t oper = NULL; TEST_ESP_OK(mcpwm_new_operator(&oper_config, &oper)); + printf("connect timer and operator\r\n"); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); + printf("install gpio faults trigger\r\n"); mcpwm_fault_handle_t gpio_faults[3]; mcpwm_gpio_fault_config_t gpio_trigger_config = { @@ -800,12 +812,12 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") printf("set generator to output high on trigger0 and low on trigger1\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_fault_event(gen, - MCPWM_GEN_FAULT_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_faults[0], MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_FAULT_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_faults[0], MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_fault_event(gen, - MCPWM_GEN_FAULT_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_faults[1], MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_FAULT_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_faults[1], MCPWM_GEN_ACTION_LOW))); // no free trigger TEST_ESP_ERR(ESP_ERR_NOT_FOUND, mcpwm_generator_set_action_on_fault_event(gen, - MCPWM_GEN_FAULT_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_faults[2], MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_FAULT_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_faults[2], MCPWM_GEN_ACTION_LOW))); TEST_ASSERT_EQUAL(0, gpio_get_level(generator_gpio)); gpio_set_level(fault_gpio_num[0], 1); @@ -825,6 +837,7 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]") TEST_ESP_OK(mcpwm_del_fault(gpio_faults[2])); TEST_ESP_OK(mcpwm_del_generator(gen)); TEST_ESP_OK(mcpwm_del_operator(oper)); + TEST_ESP_OK(mcpwm_del_timer(timer)); } TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]") @@ -872,13 +885,13 @@ TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]") printf("set generator to output high on soft sync trigger\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_sync_event(gen, - MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, soft_sync, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, soft_sync, MCPWM_GEN_ACTION_HIGH))); //more than 1 sync is not supported mcpwm_sync_handle_t invalid_soft_sync = NULL; TEST_ESP_OK(mcpwm_new_soft_sync_src(&soft_sync_config, &invalid_soft_sync)); TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_generator_set_action_on_sync_event(gen, - MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, invalid_soft_sync, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, invalid_soft_sync, MCPWM_GEN_ACTION_LOW))); TEST_ASSERT_EQUAL(0, gpio_get_level(generator_gpio)); mcpwm_soft_sync_activate(soft_sync); @@ -941,7 +954,7 @@ TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]") printf("set generator to output high on timer sync trigger\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_sync_event(gen, - MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, timer_sync, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, timer_sync, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_timer_enable(timer)); @@ -1011,7 +1024,7 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]") printf("set generator to output high on gpio sync trigger\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_sync_event(gen, - MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_sync, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_sync, MCPWM_GEN_ACTION_HIGH))); TEST_ASSERT_EQUAL(0, gpio_get_level(generator_gpio)); gpio_set_level(gpio_sync_config.gpio_num, 1); diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c similarity index 95% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c index cc60e467c53..0a0ae2fd88e 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c @@ -146,9 +146,9 @@ TEST_CASE("mcpwm_comparator_iram_safe", "[mcpwm]") printf("set generator actions on timer and compare events\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gen, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_compare_event(gen, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW))); printf("register compare event callback\r\n"); mcpwm_comparator_event_callbacks_t cbs = { diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c similarity index 91% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c index c201d4147cb..1c138a63bce 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c @@ -193,15 +193,15 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") printf("set generator actions on timer event\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gen_a, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gen_b, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); printf("set generator actions on brake event\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_brake_event(gen_a, - MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_CBC, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_CBC, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_brake_event(gen_b, - MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_OST, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_OST, MCPWM_GEN_ACTION_HIGH))); printf("enable and start timer\r\n"); TEST_ESP_OK(mcpwm_timer_enable(timer)); @@ -299,15 +299,15 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") printf("set generator actions on timer event\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gen_a, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); TEST_ESP_OK(mcpwm_generator_set_action_on_timer_event(gen_b, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW))); printf("set generator actions on brake event\r\n"); TEST_ESP_OK(mcpwm_generator_set_action_on_brake_event(gen_a, - MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_CBC, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_CBC, MCPWM_GEN_ACTION_HIGH))); TEST_ESP_OK(mcpwm_generator_set_action_on_brake_event(gen_b, - MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_OST, MCPWM_GEN_ACTION_HIGH))); + MCPWM_GEN_BRAKE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_OPER_BRAKE_MODE_OST, MCPWM_GEN_ACTION_HIGH))); printf("enable and start timer\r\n"); TEST_ESP_OK(mcpwm_timer_enable(timer)); diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_sync.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_sync.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_timer.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_timer.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_utils.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_utils.c similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_utils.c rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_utils.c diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_utils.h b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_utils.h similarity index 100% rename from components/driver/test_apps/mcpwm/main/test_mcpwm_utils.h rename to components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_utils.h diff --git a/components/driver/test_apps/mcpwm/pytest_mcpwm.py b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py similarity index 100% rename from components/driver/test_apps/mcpwm/pytest_mcpwm.py rename to components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py diff --git a/components/driver/test_apps/mcpwm/sdkconfig.ci.iram_safe b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/mcpwm/sdkconfig.ci.iram_safe rename to components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/mcpwm/sdkconfig.ci.release b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/mcpwm/sdkconfig.ci.release rename to components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.release diff --git a/components/driver/test_apps/mcpwm/sdkconfig.defaults b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/mcpwm/sdkconfig.defaults rename to components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.defaults diff --git a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt index 82fd9210955..67bb690c46b 100644 --- a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt +++ b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt @@ -9,6 +9,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity esp_driver_pcnt spi_flash - driver # will be replaced by esp_driver_gpio + PRIV_REQUIRES unity esp_driver_pcnt esp_driver_gpio spi_flash WHOLE_ARCHIVE) diff --git a/components/esp_driver_rmt/CMakeLists.txt b/components/esp_driver_rmt/CMakeLists.txt new file mode 100644 index 00000000000..df2b8dbf82e --- /dev/null +++ b/components/esp_driver_rmt/CMakeLists.txt @@ -0,0 +1,14 @@ +set(srcs) +set(public_include "include") +if(CONFIG_SOC_RMT_SUPPORTED) + list(APPEND srcs "src/rmt_common.c" + "src/rmt_encoder.c" + "src/rmt_rx.c" + "src/rmt_tx.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES "esp_pm" "esp_driver_gpio" + LDFRAGMENTS "linker.lf" + ) diff --git a/components/driver/rmt/Kconfig.rmt b/components/esp_driver_rmt/Kconfig similarity index 96% rename from components/driver/rmt/Kconfig.rmt rename to components/esp_driver_rmt/Kconfig index 97ea9c02b40..2a568e22d4a 100644 --- a/components/driver/rmt/Kconfig.rmt +++ b/components/esp_driver_rmt/Kconfig @@ -1,4 +1,4 @@ -menu "RMT Configuration" +menu "ESP-Driver:RMT Configurations" depends on SOC_RMT_SUPPORTED config RMT_ISR_IRAM_SAFE bool "RMT ISR IRAM-Safe" @@ -32,4 +32,4 @@ menu "RMT Configuration" help Wether to enable the debug log message for RMT driver. Note that, this option only controls the RMT driver log, won't affect other drivers. -endmenu # RMT Configuration +endmenu diff --git a/components/driver/rmt/include/driver/rmt_common.h b/components/esp_driver_rmt/include/driver/rmt_common.h similarity index 100% rename from components/driver/rmt/include/driver/rmt_common.h rename to components/esp_driver_rmt/include/driver/rmt_common.h diff --git a/components/driver/rmt/include/driver/rmt_encoder.h b/components/esp_driver_rmt/include/driver/rmt_encoder.h similarity index 100% rename from components/driver/rmt/include/driver/rmt_encoder.h rename to components/esp_driver_rmt/include/driver/rmt_encoder.h diff --git a/components/driver/rmt/include/driver/rmt_rx.h b/components/esp_driver_rmt/include/driver/rmt_rx.h similarity index 88% rename from components/driver/rmt/include/driver/rmt_rx.h rename to components/esp_driver_rmt/include/driver/rmt_rx.h index 325a755560a..243facf68f1 100644 --- a/components/driver/rmt/include/driver/rmt_rx.h +++ b/components/esp_driver_rmt/include/driver/rmt_rx.h @@ -22,7 +22,8 @@ extern "C" { * The variables used in the function should be in the SRAM as well. */ typedef struct { - rmt_rx_done_callback_t on_recv_done; /*!< Event callback, invoked when one RMT channel receiving transaction completes */ + rmt_rx_done_callback_t on_recv_done; /*!< Event callback, invoked when the RMT channel reception is finished + or partial data is received */ } rmt_rx_event_callbacks_t; /** @@ -35,13 +36,13 @@ typedef struct { size_t mem_block_symbols; /*!< Size of memory block, in number of `rmt_symbol_word_t`, must be an even. In the DMA mode, this field controls the DMA buffer size, it can be set to a large value (e.g. 1024); In the normal mode, this field controls the number of RMT memory block that will be used by the channel. */ + int intr_priority; /*!< RMT interrupt priority, + if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3) */ struct { uint32_t invert_in: 1; /*!< Whether to invert the incoming RMT channel signal */ uint32_t with_dma: 1; /*!< If set, the driver will allocate an RMT channel with DMA capability */ uint32_t io_loop_back: 1; /*!< For debug/test, the signal output from the GPIO will be fed to the input path as well */ } flags; /*!< RX channel config flags */ - int intr_priority; /*!< RMT interrupt priority, - if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3) */ } rmt_rx_channel_config_t; /** @@ -50,6 +51,12 @@ typedef struct { typedef struct { uint32_t signal_range_min_ns; /*!< A pulse whose width is smaller than this threshold will be treated as glitch and ignored */ uint32_t signal_range_max_ns; /*!< RMT will stop receiving if one symbol level has kept more than `signal_range_max_ns` */ + + /// Receive specific flags + struct extra_flags { + uint32_t en_partial_rx: 1; /*!< Set this flag if the incoming data is very long, and the driver can only receive the data piece by piece, + because the user buffer is not sufficient to save all the data. */ + } flags; /*!< Receive specific config flags */ } rmt_receive_config_t; /** diff --git a/components/driver/rmt/include/driver/rmt_tx.h b/components/esp_driver_rmt/include/driver/rmt_tx.h similarity index 100% rename from components/driver/rmt/include/driver/rmt_tx.h rename to components/esp_driver_rmt/include/driver/rmt_tx.h diff --git a/components/driver/rmt/include/driver/rmt_types.h b/components/esp_driver_rmt/include/driver/rmt_types.h similarity index 93% rename from components/driver/rmt/include/driver/rmt_types.h rename to components/esp_driver_rmt/include/driver/rmt_types.h index 63032d4d994..e795cfda8de 100644 --- a/components/driver/rmt/include/driver/rmt_types.h +++ b/components/esp_driver_rmt/include/driver/rmt_types.h @@ -56,6 +56,9 @@ typedef bool (*rmt_tx_done_callback_t)(rmt_channel_handle_t tx_chan, const rmt_t typedef struct { rmt_symbol_word_t *received_symbols; /*!< Point to the received RMT symbols */ size_t num_symbols; /*!< The number of received RMT symbols */ + struct { + uint32_t is_last: 1; /*!< Indicating if the current received data are the last part of the transaction */ + } flags; /*!< Extra flags */ } rmt_rx_done_event_data_t; /** diff --git a/components/driver/include/esp_private/rmt.h b/components/esp_driver_rmt/include/esp_private/rmt.h similarity index 100% rename from components/driver/include/esp_private/rmt.h rename to components/esp_driver_rmt/include/esp_private/rmt.h diff --git a/components/driver/rmt/linker.lf b/components/esp_driver_rmt/linker.lf similarity index 86% rename from components/driver/rmt/linker.lf rename to components/esp_driver_rmt/linker.lf index 508fc84c218..fc6694041e0 100644 --- a/components/driver/rmt/linker.lf +++ b/components/esp_driver_rmt/linker.lf @@ -1,5 +1,5 @@ [mapping:rmt_driver] -archive: libdriver.a +archive: libesp_driver_rmt.a entries: if RMT_RECV_FUNC_IN_IRAM = y: rmt_rx: rmt_receive (noflash) diff --git a/components/driver/rmt/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c similarity index 100% rename from components/driver/rmt/rmt_common.c rename to components/esp_driver_rmt/src/rmt_common.c diff --git a/components/driver/rmt/rmt_encoder.c b/components/esp_driver_rmt/src/rmt_encoder.c similarity index 98% rename from components/driver/rmt/rmt_encoder.c rename to components/esp_driver_rmt/src/rmt_encoder.c index d1275173047..a5183586617 100644 --- a/components/driver/rmt/rmt_encoder.c +++ b/components/esp_driver_rmt/src/rmt_encoder.c @@ -48,7 +48,7 @@ static esp_err_t rmt_bytes_encoder_reset(rmt_encoder_t *encoder) } static size_t IRAM_ATTR rmt_encode_bytes(rmt_encoder_t *encoder, rmt_channel_handle_t channel, - const void *primary_data, size_t data_size, rmt_encode_state_t *ret_state) + const void *primary_data, size_t data_size, rmt_encode_state_t *ret_state) { rmt_bytes_encoder_t *bytes_encoder = __containerof(encoder, rmt_bytes_encoder_t, base); rmt_tx_channel_t *tx_chan = __containerof(channel, rmt_tx_channel_t, base); diff --git a/components/driver/rmt/rmt_private.h b/components/esp_driver_rmt/src/rmt_private.h similarity index 97% rename from components/driver/rmt/rmt_private.h rename to components/esp_driver_rmt/src/rmt_private.h index ac9e38e4ea5..6fa1b6388dc 100644 --- a/components/driver/rmt/rmt_private.h +++ b/components/esp_driver_rmt/src/rmt_private.h @@ -176,6 +176,10 @@ typedef struct { size_t buffer_size; // size of the buffer, in bytes size_t received_symbol_num; // track the number of received symbols size_t copy_dest_off; // tracking offset in the copy destination + int dma_desc_index; // tracking the DMA descriptor used by ping-pong + struct { + uint32_t en_partial_rx: 1; // packet is too long, we need to notify the user to process the data piece by piece, in a ping-pong approach + } flags; } rmt_rx_trans_desc_t; struct rmt_rx_channel_t { diff --git a/components/driver/rmt/rmt_rx.c b/components/esp_driver_rmt/src/rmt_rx.c similarity index 77% rename from components/driver/rmt/rmt_rx.c rename to components/esp_driver_rmt/src/rmt_rx.c index a0c259345db..b27ac639b4b 100644 --- a/components/driver/rmt/rmt_rx.c +++ b/components/esp_driver_rmt/src/rmt_rx.c @@ -28,7 +28,8 @@ #include "rmt_private.h" #include "rom/cache.h" -#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) static const char *TAG = "rmt"; @@ -39,36 +40,20 @@ static esp_err_t rmt_rx_disable(rmt_channel_handle_t channel); static void rmt_rx_default_isr(void *args); #if SOC_RMT_SUPPORT_DMA -static bool rmt_dma_rx_eof_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); +static bool rmt_dma_rx_one_block_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); -static void rmt_rx_mount_dma_buffer(rmt_dma_descriptor_t *desc_array, rmt_dma_descriptor_t *desc_array_nc, size_t array_size, const void *buffer, size_t buffer_size) +static void rmt_rx_mount_dma_buffer(rmt_rx_channel_t *rx_chan, const void *buffer, size_t buffer_size, size_t per_block_size, size_t last_block_size) { - size_t prepared_length = 0; uint8_t *data = (uint8_t *)buffer; - int dma_node_i = 0; - rmt_dma_descriptor_t *desc = NULL; - while (buffer_size > RMT_DMA_DESC_BUF_MAX_SIZE) { - desc = &desc_array_nc[dma_node_i]; - desc->dw0.suc_eof = 0; - desc->dw0.size = RMT_DMA_DESC_BUF_MAX_SIZE; - desc->dw0.length = 0; - desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc->buffer = &data[prepared_length]; - desc->next = &desc_array[dma_node_i + 1]; // note, we must use the cache address for the "next" pointer - prepared_length += RMT_DMA_DESC_BUF_MAX_SIZE; - buffer_size -= RMT_DMA_DESC_BUF_MAX_SIZE; - dma_node_i++; - } - if (buffer_size) { - desc = &desc_array_nc[dma_node_i]; - desc->dw0.suc_eof = 0; - desc->dw0.size = buffer_size; - desc->dw0.length = 0; - desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc->buffer = &data[prepared_length]; - prepared_length += buffer_size; - } - desc->next = NULL; // one-off DMA chain + for (int i = 0; i < rx_chan->num_dma_nodes; i++) { + rmt_dma_descriptor_t *desc_nc = &rx_chan->dma_nodes_nc[i]; + desc_nc->buffer = data + i * per_block_size; + desc_nc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + desc_nc->dw0.suc_eof = 0; + desc_nc->dw0.length = 0; + desc_nc->dw0.size = per_block_size; + } + rx_chan->dma_nodes_nc[rx_chan->num_dma_nodes - 1].dw0.size = last_block_size; } static esp_err_t rmt_rx_init_dma_link(rmt_rx_channel_t *rx_channel, const rmt_rx_channel_config_t *config) @@ -77,8 +62,16 @@ static esp_err_t rmt_rx_init_dma_link(rmt_rx_channel_t *rx_channel, const rmt_rx .direction = GDMA_CHANNEL_DIRECTION_RX, }; ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &rx_channel->base.dma_chan), TAG, "allocate RX DMA channel failed"); + + // circular DMA descriptor + for (int i = 0; i < rx_channel->num_dma_nodes; i++) { + rx_channel->dma_nodes_nc[i].next = &rx_channel->dma_nodes[i + 1]; + } + rx_channel->dma_nodes_nc[rx_channel->num_dma_nodes - 1].next = &rx_channel->dma_nodes[0]; + + // register event callbacks gdma_rx_event_callbacks_t cbs = { - .on_recv_eof = rmt_dma_rx_eof_cb, + .on_recv_done = rmt_dma_rx_one_block_cb, }; gdma_register_rx_event_callbacks(rx_channel->base.dma_chan, &cbs, rx_channel); return ESP_OK; @@ -204,6 +197,7 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_ if (config->flags.with_dma) { mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA; num_dma_nodes = config->mem_block_symbols * sizeof(rmt_symbol_word_t) / RMT_DMA_DESC_BUF_MAX_SIZE + 1; + num_dma_nodes = MAX(2, num_dma_nodes); // at least 2 DMA nodes for ping-pong // DMA descriptors must be placed in internal SRAM rx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps); ESP_GOTO_ON_FALSE(rx_channel->dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for rx channel DMA nodes"); @@ -347,6 +341,8 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ ESP_RETURN_ON_FALSE_ISR(channel && buffer && buffer_size && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE_ISR(channel->direction == RMT_CHANNEL_DIRECTION_RX, ESP_ERR_INVALID_ARG, TAG, "invalid channel direction"); rmt_rx_channel_t *rx_chan = __containerof(channel, rmt_rx_channel_t, base); + size_t per_dma_block_size = 0; + size_t last_dma_block_size = 0; if (channel->dma_chan) { ESP_RETURN_ON_FALSE_ISR(esp_ptr_internal(buffer), ESP_ERR_INVALID_ARG, TAG, "buffer must locate in internal RAM for DMA use"); @@ -356,11 +352,14 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buffer & data_cache_line_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer must be aligned to cache line size"); ESP_RETURN_ON_FALSE_ISR((buffer_size & data_cache_line_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer size must be aligned to cache line size"); #endif - } - if (channel->dma_chan) { ESP_RETURN_ON_FALSE_ISR(buffer_size <= rx_chan->num_dma_nodes * RMT_DMA_DESC_BUF_MAX_SIZE, ESP_ERR_INVALID_ARG, TAG, "buffer size exceeds DMA capacity"); + per_dma_block_size = buffer_size / rx_chan->num_dma_nodes; + per_dma_block_size = ALIGN_DOWN(per_dma_block_size, sizeof(rmt_symbol_word_t)); + last_dma_block_size = buffer_size - per_dma_block_size * (rx_chan->num_dma_nodes - 1); + ESP_RETURN_ON_FALSE_ISR(last_dma_block_size <= RMT_DMA_DESC_BUF_MAX_SIZE, ESP_ERR_INVALID_ARG, TAG, "buffer size exceeds DMA capacity"); } + rmt_group_t *group = channel->group; rmt_hal_context_t *hal = &group->hal; int channel_id = channel->channel_id; @@ -377,14 +376,17 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ // fill in the transaction descriptor rmt_rx_trans_desc_t *t = &rx_chan->trans_desc; + memset(t, 0, sizeof(rmt_rx_trans_desc_t)); t->buffer = buffer; t->buffer_size = buffer_size; t->received_symbol_num = 0; t->copy_dest_off = 0; + t->dma_desc_index = 0; + t->flags.en_partial_rx = config->flags.en_partial_rx; if (channel->dma_chan) { #if SOC_RMT_SUPPORT_DMA - rmt_rx_mount_dma_buffer(rx_chan->dma_nodes, rx_chan->dma_nodes_nc, rx_chan->num_dma_nodes, buffer, buffer_size); + rmt_rx_mount_dma_buffer(rx_chan, buffer, buffer_size, per_dma_block_size, last_dma_block_size); gdma_reset(channel->dma_chan); gdma_start(channel->dma_chan, (intptr_t)rx_chan->dma_nodes); // note, we must use the cached descriptor address to start the DMA #endif @@ -531,16 +533,6 @@ static esp_err_t rmt_rx_disable(rmt_channel_handle_t channel) return ESP_OK; } -static size_t IRAM_ATTR rmt_copy_symbols(rmt_symbol_word_t *symbol_stream, size_t symbol_num, void *buffer, size_t offset, size_t buffer_size) -{ - size_t mem_want = symbol_num * sizeof(rmt_symbol_word_t); - size_t mem_have = buffer_size - offset; - size_t copy_size = MIN(mem_want, mem_have); - // do memory copy - memcpy(buffer + offset, symbol_stream, copy_size); - return copy_size; -} - static bool IRAM_ATTR rmt_isr_handle_rx_done(rmt_rx_channel_t *rx_chan) { rmt_channel_t *channel = &rx_chan->base; @@ -548,21 +540,55 @@ static bool IRAM_ATTR rmt_isr_handle_rx_done(rmt_rx_channel_t *rx_chan) rmt_hal_context_t *hal = &group->hal; uint32_t channel_id = channel->channel_id; rmt_rx_trans_desc_t *trans_desc = &rx_chan->trans_desc; + rmt_rx_done_callback_t cb = rx_chan->on_recv_done; bool need_yield = false; rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_RX_DONE(channel_id)); - portENTER_CRITICAL_ISR(&channel->spinlock); // disable the RX engine, it will be enabled again when next time user calls `rmt_receive()` rmt_ll_rx_enable(hal->regs, channel_id, false); + portEXIT_CRITICAL_ISR(&channel->spinlock); + uint32_t offset = rmt_ll_rx_get_memory_writer_offset(hal->regs, channel_id); // sanity check assert(offset >= rx_chan->mem_off); + size_t mem_want = (offset - rx_chan->mem_off) * sizeof(rmt_symbol_word_t); + size_t mem_have = trans_desc->buffer_size - trans_desc->copy_dest_off; + size_t copy_size = mem_want; + if (mem_want > mem_have) { + if (trans_desc->flags.en_partial_rx) { // check partial receive is enabled or not + // notify the user to process the received symbols if the buffer is going to be full + if (trans_desc->received_symbol_num) { + if (cb) { + rmt_rx_done_event_data_t edata = { + .received_symbols = trans_desc->buffer, + .num_symbols = trans_desc->received_symbol_num, + .flags.is_last = false, + }; + if (cb(channel, &edata, rx_chan->user_data)) { + need_yield = true; + } + } + trans_desc->copy_dest_off = 0; + trans_desc->received_symbol_num = 0; + mem_have = trans_desc->buffer_size; + + // even user process the partial received data, the remain buffer may still be insufficient + if (mem_want > mem_have) { + ESP_DRAM_LOGE(TAG, "user buffer too small, received symbols truncated"); + copy_size = mem_have; + } + } + } else { + ESP_DRAM_LOGE(TAG, "user buffer too small, received symbols truncated"); + copy_size = mem_have; + } + } + + portENTER_CRITICAL_ISR(&channel->spinlock); rmt_ll_rx_set_mem_owner(hal->regs, channel_id, RMT_LL_MEM_OWNER_SW); - // copy the symbols to user space - size_t stream_symbols = offset - rx_chan->mem_off; - size_t copy_size = rmt_copy_symbols(channel->hw_mem_base + rx_chan->mem_off, stream_symbols, - trans_desc->buffer, trans_desc->copy_dest_off, trans_desc->buffer_size); + // copy the symbols to the user buffer + memcpy((uint8_t *)trans_desc->buffer + trans_desc->copy_dest_off, channel->hw_mem_base + rx_chan->mem_off, copy_size); rmt_ll_rx_set_mem_owner(hal->regs, channel_id, RMT_LL_MEM_OWNER_HW); portEXIT_CRITICAL_ISR(&channel->spinlock); @@ -579,22 +605,19 @@ static bool IRAM_ATTR rmt_isr_handle_rx_done(rmt_rx_channel_t *rx_chan) } #endif // !SOC_RMT_SUPPORT_RX_PINGPONG - // check whether all symbols are copied - if (copy_size != stream_symbols * sizeof(rmt_symbol_word_t)) { - ESP_DRAM_LOGE(TAG, "user buffer too small, received symbols truncated"); - } trans_desc->copy_dest_off += copy_size; trans_desc->received_symbol_num += copy_size / sizeof(rmt_symbol_word_t); // switch back to the enable state, then user can call `rmt_receive` to start a new receive atomic_store(&channel->fsm, RMT_FSM_ENABLE); - // notify the user with receive RMT symbols - if (rx_chan->on_recv_done) { + // notify the user that all RMT symbols are received done + if (cb) { rmt_rx_done_event_data_t edata = { .received_symbols = trans_desc->buffer, .num_symbols = trans_desc->received_symbol_num, + .flags.is_last = true, }; - if (rx_chan->on_recv_done(channel, &edata, rx_chan->user_data)) { + if (cb(channel, &edata, rx_chan->user_data)) { need_yield = true; } } @@ -604,6 +627,7 @@ static bool IRAM_ATTR rmt_isr_handle_rx_done(rmt_rx_channel_t *rx_chan) #if SOC_RMT_SUPPORT_RX_PINGPONG static bool IRAM_ATTR rmt_isr_handle_rx_threshold(rmt_rx_channel_t *rx_chan) { + bool need_yield = false; rmt_channel_t *channel = &rx_chan->base; rmt_group_t *group = channel->group; rmt_hal_context_t *hal = &group->hal; @@ -612,24 +636,54 @@ static bool IRAM_ATTR rmt_isr_handle_rx_threshold(rmt_rx_channel_t *rx_chan) rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_RX_THRES(channel_id)); + size_t mem_want = rx_chan->ping_pong_symbols * sizeof(rmt_symbol_word_t); + size_t mem_have = trans_desc->buffer_size - trans_desc->copy_dest_off; + size_t copy_size = mem_want; + if (mem_want > mem_have) { + if (trans_desc->flags.en_partial_rx) { + // notify the user to process the received symbols if the buffer is going to be full + if (trans_desc->received_symbol_num) { + rmt_rx_done_callback_t cb = rx_chan->on_recv_done; + if (cb) { + rmt_rx_done_event_data_t edata = { + .received_symbols = trans_desc->buffer, + .num_symbols = trans_desc->received_symbol_num, + .flags.is_last = false, + }; + if (cb(channel, &edata, rx_chan->user_data)) { + need_yield = true; + } + } + trans_desc->copy_dest_off = 0; + trans_desc->received_symbol_num = 0; + mem_have = trans_desc->buffer_size; + + // even user process the partial received data, the remain buffer size still insufficient + if (mem_want > mem_have) { + ESP_DRAM_LOGE(TAG, "user buffer too small, received symbols truncated"); + copy_size = mem_have; + } + } + } else { + ESP_DRAM_LOGE(TAG, "user buffer too small, received symbols truncated"); + copy_size = mem_have; + } + } + portENTER_CRITICAL_ISR(&channel->spinlock); rmt_ll_rx_set_mem_owner(hal->regs, channel_id, RMT_LL_MEM_OWNER_SW); - // copy the symbols to user space - size_t copy_size = rmt_copy_symbols(channel->hw_mem_base + rx_chan->mem_off, rx_chan->ping_pong_symbols, - trans_desc->buffer, trans_desc->copy_dest_off, trans_desc->buffer_size); + // copy the symbols to the user buffer + memcpy((uint8_t *)trans_desc->buffer + trans_desc->copy_dest_off, channel->hw_mem_base + rx_chan->mem_off, copy_size); rmt_ll_rx_set_mem_owner(hal->regs, channel_id, RMT_LL_MEM_OWNER_HW); portEXIT_CRITICAL_ISR(&channel->spinlock); - // check whether all symbols are copied - if (copy_size != rx_chan->ping_pong_symbols * sizeof(rmt_symbol_word_t)) { - ESP_DRAM_LOGE(TAG, "received symbols truncated"); - } trans_desc->copy_dest_off += copy_size; trans_desc->received_symbol_num += copy_size / sizeof(rmt_symbol_word_t); + // update the hw memory offset, where stores the next RMT symbols to copy rx_chan->mem_off = rx_chan->ping_pong_symbols - rx_chan->mem_off; - return false; + return need_yield; } #endif // SOC_RMT_SUPPORT_RX_PINGPONG @@ -666,18 +720,29 @@ static void IRAM_ATTR rmt_rx_default_isr(void *args) } #if SOC_RMT_SUPPORT_DMA -static size_t IRAM_ATTR rmt_rx_get_received_symbol_num_from_dma(rmt_dma_descriptor_t *desc_nc) +static size_t IRAM_ATTR rmt_rx_count_symbols_until_eof(rmt_rx_channel_t *rx_chan, int start_index) { size_t received_bytes = 0; - while (desc_nc) { - received_bytes += desc_nc->dw0.length; - desc_nc = (rmt_dma_descriptor_t *)RMT_GET_NON_CACHE_ADDR(desc_nc->next); + for (int i = 0; i < rx_chan->num_dma_nodes; i++) { + received_bytes += rx_chan->dma_nodes_nc[start_index].dw0.length; + if (rx_chan->dma_nodes_nc[start_index].dw0.suc_eof) { + break; + } + start_index++; + start_index %= rx_chan->num_dma_nodes; } received_bytes = ALIGN_UP(received_bytes, sizeof(rmt_symbol_word_t)); return received_bytes / sizeof(rmt_symbol_word_t); } -static bool IRAM_ATTR rmt_dma_rx_eof_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +static size_t IRAM_ATTR rmt_rx_count_symbols_for_single_block(rmt_rx_channel_t *rx_chan, int desc_index) +{ + size_t received_bytes = rx_chan->dma_nodes_nc[desc_index].dw0.length; + received_bytes = ALIGN_UP(received_bytes, sizeof(rmt_symbol_word_t)); + return received_bytes / sizeof(rmt_symbol_word_t); +} + +static bool IRAM_ATTR rmt_dma_rx_one_block_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { bool need_yield = false; rmt_rx_channel_t *rx_chan = (rmt_rx_channel_t *)user_data; @@ -687,11 +752,6 @@ static bool IRAM_ATTR rmt_dma_rx_eof_cb(gdma_channel_handle_t dma_chan, gdma_eve rmt_rx_trans_desc_t *trans_desc = &rx_chan->trans_desc; uint32_t channel_id = channel->channel_id; - portENTER_CRITICAL_ISR(&channel->spinlock); - // disable the RX engine, it will be enabled again in the next `rmt_receive()` - rmt_ll_rx_enable(hal->regs, channel_id, false); - portEXIT_CRITICAL_ISR(&channel->spinlock); - #if CONFIG_IDF_TARGET_ESP32P4 int invalidate_map = CACHE_MAP_L1_DCACHE; if (esp_ptr_external_ram((const void *)trans_desc->buffer)) { @@ -700,19 +760,48 @@ static bool IRAM_ATTR rmt_dma_rx_eof_cb(gdma_channel_handle_t dma_chan, gdma_eve Cache_Invalidate_Addr(invalidate_map, (uint32_t)trans_desc->buffer, trans_desc->buffer_size); #endif - // switch back to the enable state, then user can call `rmt_receive` to start a new receive - atomic_store(&channel->fsm, RMT_FSM_ENABLE); + if (event_data->flags.normal_eof) { + // if the DMA received an EOF, it means the RMT peripheral has received an "end marker" + portENTER_CRITICAL_ISR(&channel->spinlock); + // disable the RX engine, it will be enabled again in the next `rmt_receive()` + rmt_ll_rx_enable(hal->regs, channel_id, false); + portEXIT_CRITICAL_ISR(&channel->spinlock); - if (rx_chan->on_recv_done) { - rmt_rx_done_event_data_t edata = { - .received_symbols = trans_desc->buffer, - .num_symbols = rmt_rx_get_received_symbol_num_from_dma(rx_chan->dma_nodes_nc), - }; - if (rx_chan->on_recv_done(channel, &edata, rx_chan->user_data)) { - need_yield = true; + // switch back to the enable state, then user can call `rmt_receive` to start a new receive + atomic_store(&channel->fsm, RMT_FSM_ENABLE); + + if (rx_chan->on_recv_done) { + int recycle_start_index = trans_desc->dma_desc_index; + rmt_rx_done_event_data_t edata = { + .received_symbols = rx_chan->dma_nodes_nc[recycle_start_index].buffer, + .num_symbols = rmt_rx_count_symbols_until_eof(rx_chan, recycle_start_index), + .flags.is_last = true, + }; + if (rx_chan->on_recv_done(channel, &edata, rx_chan->user_data)) { + need_yield = true; + } + } + } else { + // it's a partial receive done event + if (trans_desc->flags.en_partial_rx) { + if (rx_chan->on_recv_done) { + size_t dma_desc_index = trans_desc->dma_desc_index; + rmt_rx_done_event_data_t edata = { + .received_symbols = rx_chan->dma_nodes_nc[dma_desc_index].buffer, + .num_symbols = rmt_rx_count_symbols_for_single_block(rx_chan, dma_desc_index), + .flags.is_last = false, + }; + if (rx_chan->on_recv_done(channel, &edata, rx_chan->user_data)) { + need_yield = true; + } + + dma_desc_index++; + trans_desc->dma_desc_index = dma_desc_index % rx_chan->num_dma_nodes; + } } } return need_yield; } + #endif // SOC_RMT_SUPPORT_DMA diff --git a/components/driver/rmt/rmt_tx.c b/components/esp_driver_rmt/src/rmt_tx.c similarity index 99% rename from components/driver/rmt/rmt_tx.c rename to components/esp_driver_rmt/src/rmt_tx.c index 3cb25a395f5..b4d3a246920 100644 --- a/components/driver/rmt/rmt_tx.c +++ b/components/esp_driver_rmt/src/rmt_tx.c @@ -65,6 +65,11 @@ static esp_err_t rmt_tx_init_dma_link(rmt_tx_channel_t *tx_channel, const rmt_tx .direction = GDMA_CHANNEL_DIRECTION_TX, }; ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &tx_channel->base.dma_chan), TAG, "allocate TX DMA channel failed"); + gdma_strategy_config_t gdma_strategy_conf = { + .auto_update_desc = true, + .owner_check = true, + }; + gdma_apply_strategy(tx_channel->base.dma_chan, &gdma_strategy_conf); gdma_tx_event_callbacks_t cbs = { .on_trans_eof = rmt_dma_tx_eof_cb, }; diff --git a/components/esp_driver_rmt/test_apps/.build-test-rules.yml b/components/esp_driver_rmt/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..2a97c6cdec1 --- /dev/null +++ b/components/esp_driver_rmt/test_apps/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_rmt/test_apps/rmt: + disable: + - if: SOC_RMT_SUPPORTED != 1 + depends_components: + - esp_driver_rmt diff --git a/components/driver/test_apps/rmt/CMakeLists.txt b/components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt similarity index 87% rename from components/driver/test_apps/rmt/CMakeLists.txt rename to components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt index 4ad5bb66269..6c44dbcf33d 100644 --- a/components/driver/test_apps/rmt/CMakeLists.txt +++ b/components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt @@ -10,7 +10,7 @@ project(rmt_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_rmt/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/rmt_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/rmt/README.md b/components/esp_driver_rmt/test_apps/rmt/README.md similarity index 100% rename from components/driver/test_apps/rmt/README.md rename to components/esp_driver_rmt/test_apps/rmt/README.md diff --git a/components/driver/test_apps/rmt/main/CMakeLists.txt b/components/esp_driver_rmt/test_apps/rmt/main/CMakeLists.txt similarity index 76% rename from components/driver/test_apps/rmt/main/CMakeLists.txt rename to components/esp_driver_rmt/test_apps/rmt/main/CMakeLists.txt index 018443a52a2..ba76bdbf9f0 100644 --- a/components/driver/test_apps/rmt/main/CMakeLists.txt +++ b/components/esp_driver_rmt/test_apps/rmt/main/CMakeLists.txt @@ -9,5 +9,5 @@ if(CONFIG_RMT_ISR_IRAM_SAFE) endif() idf_component_register(SRCS "${srcs}" - PRIV_REQUIRES unity driver esp_timer esp_psram + PRIV_REQUIRES unity esp_driver_rmt esp_driver_gpio esp_timer esp_psram WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/rmt/main/test_app_main.c b/components/esp_driver_rmt/test_apps/rmt/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/rmt/main/test_app_main.c rename to components/esp_driver_rmt/test_apps/rmt/main/test_app_main.c diff --git a/components/driver/test_apps/rmt/main/test_board.h b/components/esp_driver_rmt/test_apps/rmt/main/test_board.h similarity index 100% rename from components/driver/test_apps/rmt/main/test_board.h rename to components/esp_driver_rmt/test_apps/rmt/main/test_board.h diff --git a/components/driver/test_apps/rmt/main/test_rmt_common.c b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_common.c similarity index 100% rename from components/driver/test_apps/rmt/main/test_rmt_common.c rename to components/esp_driver_rmt/test_apps/rmt/main/test_rmt_common.c diff --git a/components/driver/test_apps/rmt/main/test_rmt_iram.c b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c similarity index 96% rename from components/driver/test_apps/rmt/main/test_rmt_iram.c rename to components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c index 32eac623299..985ea2a7a33 100644 --- a/components/driver/test_apps/rmt/main/test_rmt_iram.c +++ b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c @@ -108,13 +108,13 @@ typedef struct { size_t received_symbol_num; rmt_receive_config_t rx_config; rmt_symbol_word_t remote_codes[128]; -} test_nec_rx_user_data_t; +} test_rx_user_data_t; IRAM_ATTR static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx_done_event_data_t *edata, void *user_data) { BaseType_t high_task_wakeup = pdFALSE; - test_nec_rx_user_data_t *test_user_data = (test_nec_rx_user_data_t *)user_data; + test_rx_user_data_t *test_user_data = (test_rx_user_data_t *)user_data; test_user_data->received_symbol_num += edata->num_symbols; // should receive one RMT symbol at a time if (edata->num_symbols == 1) { @@ -142,13 +142,13 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c TEST_ESP_OK(rmt_new_rx_channel(&rx_channel_cfg, &rx_channel)); // initialize the GPIO level to low - TEST_ESP_OK(gpio_set_level(0, 0)); + TEST_ESP_OK(gpio_set_level(TEST_RMT_GPIO_NUM_A, 0)); printf("register rx event callbacks\r\n"); rmt_rx_event_callbacks_t cbs = { .on_recv_done = test_rmt_rx_done_callback, }; - test_nec_rx_user_data_t test_user_data = { + test_rx_user_data_t test_user_data = { .task_to_notify = xTaskGetCurrentTaskHandle(), .received_symbol_num = 0, .rx_config = { @@ -165,7 +165,7 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c TEST_ESP_OK(rmt_receive(rx_channel, test_user_data.remote_codes, sizeof(test_user_data.remote_codes), &test_user_data.rx_config)); // disable the flash cache, and simulate input signal by GPIO - unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, 0); + unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, TEST_RMT_GPIO_NUM_A); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); TEST_ASSERT_EQUAL(TEST_RMT_SYMBOLS, test_user_data.received_symbol_num); diff --git a/components/driver/test_apps/rmt/main/test_rmt_rx.c b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_rx.c similarity index 66% rename from components/driver/test_apps/rmt/main/test_rmt_rx.c rename to components/esp_driver_rmt/test_apps/rmt/main/test_rmt_rx.c index 22958a3c719..9ba314983ba 100644 --- a/components/driver/test_apps/rmt/main/test_rmt_rx.c +++ b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_rx.c @@ -11,6 +11,7 @@ #include "unity.h" #include "driver/rmt_tx.h" #include "driver/rmt_rx.h" +#include "driver/gpio.h" #include "soc/soc_caps.h" #include "test_util_rmt_encoders.h" #include "test_board.h" @@ -45,7 +46,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt { uint32_t const test_rx_buffer_symbols = 128; rmt_symbol_word_t *remote_codes = heap_caps_aligned_calloc(64, test_rx_buffer_symbols, sizeof(rmt_symbol_word_t), - MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); TEST_ASSERT_NOT_NULL(remote_codes); rmt_rx_channel_config_t rx_channel_cfg = { @@ -201,3 +202,108 @@ TEST_CASE("rmt rx nec with carrier", "[rmt]") test_rmt_rx_nec_carrier(128, true, RMT_CLK_SRC_DEFAULT); #endif } + +#if SOC_RMT_SUPPORT_RX_PINGPONG +#define TEST_RMT_SYMBOLS 10000 // a very long frame, contains 10000 symbols + +static void pwm_bit_bang(int gpio_num) +{ + for (int i = 0; i < TEST_RMT_SYMBOLS; i++) { + gpio_set_level(gpio_num, 1); + esp_rom_delay_us(50); + gpio_set_level(gpio_num, 0); + esp_rom_delay_us(50); + } +} + +typedef struct { + TaskHandle_t task_to_notify; + size_t received_symbol_num; +} test_rx_user_data_t; + +TEST_RMT_CALLBACK_ATTR +static bool test_rmt_partial_receive_done(rmt_channel_handle_t channel, const rmt_rx_done_event_data_t *edata, void *user_data) +{ + BaseType_t high_task_wakeup = pdFALSE; + test_rx_user_data_t *test_user_data = (test_rx_user_data_t *)user_data; + test_user_data->received_symbol_num += edata->num_symbols; + // when receive done, notify the task to check the received data + if (edata->flags.is_last) { + vTaskNotifyGiveFromISR(test_user_data->task_to_notify, &high_task_wakeup); + } + return high_task_wakeup == pdTRUE; +} + +static void test_rmt_partial_receive(size_t mem_block_symbols, bool with_dma, rmt_clock_source_t clk_src) +{ + uint32_t const test_rx_buffer_symbols = 128; // the user buffer is small, it can't hold all the received symbols + rmt_symbol_word_t *receive_user_buf = heap_caps_aligned_calloc(64, test_rx_buffer_symbols, sizeof(rmt_symbol_word_t), + MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(receive_user_buf); + + rmt_rx_channel_config_t rx_channel_cfg = { + .clk_src = clk_src, + .resolution_hz = 1000000, // 1MHz, 1 tick = 1us + .mem_block_symbols = mem_block_symbols, + .gpio_num = TEST_RMT_GPIO_NUM_A, + .flags.with_dma = with_dma, + .flags.io_loop_back = true, // the GPIO will act like a loopback + }; + printf("install rx channel\r\n"); + rmt_channel_handle_t rx_channel = NULL; + TEST_ESP_OK(rmt_new_rx_channel(&rx_channel_cfg, &rx_channel)); + + // initialize the GPIO level to low + TEST_ESP_OK(gpio_set_level(TEST_RMT_GPIO_NUM_A, 0)); + + printf("register rx event callbacks\r\n"); + rmt_rx_event_callbacks_t cbs = { + .on_recv_done = test_rmt_partial_receive_done, + }; + test_rx_user_data_t test_user_data = { + .task_to_notify = xTaskGetCurrentTaskHandle(), + .received_symbol_num = 0, + }; + TEST_ESP_OK(rmt_rx_register_event_callbacks(rx_channel, &cbs, &test_user_data)); + + printf("enable rx channel\r\n"); + TEST_ESP_OK(rmt_enable(rx_channel)); + + rmt_receive_config_t rx_config = { + .signal_range_min_ns = 1250, + .signal_range_max_ns = 12000000, + .flags.en_partial_rx = true, // enable partial receive + }; + // ready to receive + TEST_ESP_OK(rmt_receive(rx_channel, receive_user_buf, test_rx_buffer_symbols * sizeof(rmt_symbol_word_t), &rx_config)); + + // simulate input signal by GPIO + pwm_bit_bang(TEST_RMT_GPIO_NUM_A); + + TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(2000))); + printf("received %zu symbols\r\n", test_user_data.received_symbol_num); + TEST_ASSERT_EQUAL(TEST_RMT_SYMBOLS, test_user_data.received_symbol_num); + // verify the received data + for (int i = 0; i < 10; i++) { + printf("{%d:%d},{%d:%d}\r\n", receive_user_buf[i].level0, receive_user_buf[i].duration0, receive_user_buf[i].level1, receive_user_buf[i].duration1); + TEST_ASSERT_EQUAL(1, receive_user_buf[i].level0); + TEST_ASSERT_INT_WITHIN(20, 50, receive_user_buf[i].duration0); + TEST_ASSERT_EQUAL(0, receive_user_buf[i].level1); + TEST_ASSERT_INT_WITHIN(20, 50, receive_user_buf[i].duration1); + } + + printf("disable rx channels\r\n"); + TEST_ESP_OK(rmt_disable(rx_channel)); + printf("delete channels and encoder\r\n"); + TEST_ESP_OK(rmt_del_channel(rx_channel)); + free(receive_user_buf); +} + +TEST_CASE("rmt rx long frame partially", "[rmt]") +{ + test_rmt_partial_receive(SOC_RMT_MEM_WORDS_PER_CHANNEL, false, RMT_CLK_SRC_DEFAULT); +#if SOC_RMT_SUPPORT_DMA + test_rmt_partial_receive(256, true, RMT_CLK_SRC_DEFAULT); +#endif +} +#endif // SOC_RMT_SUPPORT_RX_PINGPONG diff --git a/components/driver/test_apps/rmt/main/test_rmt_tx.c b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_tx.c similarity index 100% rename from components/driver/test_apps/rmt/main/test_rmt_tx.c rename to components/esp_driver_rmt/test_apps/rmt/main/test_rmt_tx.c diff --git a/components/driver/test_apps/rmt/main/test_util_rmt_encoders.c b/components/esp_driver_rmt/test_apps/rmt/main/test_util_rmt_encoders.c similarity index 100% rename from components/driver/test_apps/rmt/main/test_util_rmt_encoders.c rename to components/esp_driver_rmt/test_apps/rmt/main/test_util_rmt_encoders.c diff --git a/components/driver/test_apps/rmt/main/test_util_rmt_encoders.h b/components/esp_driver_rmt/test_apps/rmt/main/test_util_rmt_encoders.h similarity index 100% rename from components/driver/test_apps/rmt/main/test_util_rmt_encoders.h rename to components/esp_driver_rmt/test_apps/rmt/main/test_util_rmt_encoders.h diff --git a/components/driver/test_apps/rmt/pytest_rmt.py b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py similarity index 100% rename from components/driver/test_apps/rmt/pytest_rmt.py rename to components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py diff --git a/components/driver/test_apps/rmt/sdkconfig.ci.iram_safe b/components/esp_driver_rmt/test_apps/rmt/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/rmt/sdkconfig.ci.iram_safe rename to components/esp_driver_rmt/test_apps/rmt/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/rmt/sdkconfig.ci.release b/components/esp_driver_rmt/test_apps/rmt/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/rmt/sdkconfig.ci.release rename to components/esp_driver_rmt/test_apps/rmt/sdkconfig.ci.release diff --git a/components/driver/test_apps/rmt/sdkconfig.defaults b/components/esp_driver_rmt/test_apps/rmt/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/rmt/sdkconfig.defaults rename to components/esp_driver_rmt/test_apps/rmt/sdkconfig.defaults diff --git a/components/driver/test_apps/rmt/sdkconfig.defaults.esp32s3 b/components/esp_driver_rmt/test_apps/rmt/sdkconfig.defaults.esp32s3 similarity index 100% rename from components/driver/test_apps/rmt/sdkconfig.defaults.esp32s3 rename to components/esp_driver_rmt/test_apps/rmt/sdkconfig.defaults.esp32s3 diff --git a/components/esp_driver_sdio/CMakeLists.txt b/components/esp_driver_sdio/CMakeLists.txt new file mode 100644 index 00000000000..a90762b19c4 --- /dev/null +++ b/components/esp_driver_sdio/CMakeLists.txt @@ -0,0 +1,13 @@ +set(srcs) + +set(public_include "include") + +# SDIO Slave related source files +if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED) + list(APPEND srcs "src/sdio_slave.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES esp_driver_gpio esp_ringbuf + ) diff --git a/components/driver/sdio_slave/include/driver/sdio_slave.h b/components/esp_driver_sdio/include/driver/sdio_slave.h similarity index 94% rename from components/driver/sdio_slave/include/driver/sdio_slave.h rename to components/esp_driver_sdio/include/driver/sdio_slave.h index 6d05406bb76..16225507cec 100644 --- a/components/driver/sdio_slave/include/driver/sdio_slave.h +++ b/components/esp_driver_sdio/include/driver/sdio_slave.h @@ -18,18 +18,17 @@ extern "C" { typedef void(*sdio_event_cb_t)(uint8_t event); - /// Configuration of SDIO slave typedef struct { sdio_slave_timing_t timing; ///< timing of sdio_slave. see `sdio_slave_timing_t`. sdio_slave_sending_mode_t sending_mode; ///< mode of sdio_slave. `SDIO_SLAVE_MODE_STREAM` if the data needs to be sent as much as possible; `SDIO_SLAVE_MODE_PACKET` if the data should be sent in packets. int send_queue_size; ///< max buffers that can be queued before sending. size_t recv_buffer_size; - ///< If buffer_size is too small, it costs more CPU time to handle larger number of buffers. - ///< If buffer_size is too large, the space larger than the transaction length is left blank but still counts a buffer, and the buffers are easily run out. - ///< Should be set according to length of data really transferred. - ///< All data that do not fully fill a buffer is still counted as one buffer. E.g. 10 bytes data costs 2 buffers if the size is 8 bytes per buffer. - ///< Buffer size of the slave pre-defined between host and slave before communication. All receive buffer given to the driver should be larger than this. + ///< If buffer_size is too small, it costs more CPU time to handle larger number of buffers. + ///< If buffer_size is too large, the space larger than the transaction length is left blank but still counts a buffer, and the buffers are easily run out. + ///< Should be set according to length of data really transferred. + ///< All data that do not fully fill a buffer is still counted as one buffer. E.g. 10 bytes data costs 2 buffers if the size is 8 bytes per buffer. + ///< Buffer size of the slave pre-defined between host and slave before communication. All receive buffer given to the driver should be larger than this. sdio_event_cb_t event_cb; ///< when the host interrupts slave, this callback will be called with interrupt number (0-7). uint32_t flags; ///< Features to be enabled for the slave, combinations of ``SDIO_SLAVE_FLAG_*``. #define SDIO_SLAVE_FLAG_DAT2_DISABLED BIT(0) /**< It is required by the SD specification that all 4 data @@ -282,7 +281,6 @@ void sdio_slave_clear_host_int(sdio_slave_hostint_t mask); */ esp_err_t sdio_slave_wait_int(int pos, TickType_t wait); - #ifdef __cplusplus } #endif diff --git a/components/driver/sdio_slave/README.md b/components/esp_driver_sdio/src/README.md similarity index 100% rename from components/driver/sdio_slave/README.md rename to components/esp_driver_sdio/src/README.md diff --git a/components/driver/sdio_slave/sdio_slave.c b/components/esp_driver_sdio/src/sdio_slave.c similarity index 99% rename from components/driver/sdio_slave/sdio_slave.c rename to components/esp_driver_sdio/src/sdio_slave.c index 589984e3ae9..c683547047d 100644 --- a/components/driver/sdio_slave/sdio_slave.c +++ b/components/esp_driver_sdio/src/sdio_slave.c @@ -75,8 +75,6 @@ The driver of FIFOs works as below: driver also fix the STAILQ_NEXT pointer of the last descriptor so that the descriptors are now in a ring again. */ - - #include #include "driver/sdio_slave.h" #include "soc/sdio_slave_periph.h" @@ -92,7 +90,6 @@ The driver of FIFOs works as below: #include "hal/sdio_slave_hal.h" #include "hal/gpio_hal.h" - #define SDIO_SLAVE_CHECK(res, str, ret_val) do { if(!(res)){\ SDIO_SLAVE_LOGE("%s", str);\ return ret_val;\ @@ -103,7 +100,6 @@ static const char TAG[] = "sdio_slave"; #define SDIO_SLAVE_LOGE(s, ...) ESP_LOGE(TAG, "%s(%d): "s, __FUNCTION__,__LINE__,##__VA_ARGS__) #define SDIO_SLAVE_LOGW(s, ...) ESP_LOGW(TAG, "%s: "s, __FUNCTION__,##__VA_ARGS__) - // sdio_slave_buf_handle_t is of type recv_desc_t*; typedef struct recv_desc_s { union { @@ -122,7 +118,6 @@ typedef struct recv_desc_s { }; } recv_desc_t; - typedef TAILQ_HEAD(recv_tailq_head_s, recv_desc_s) recv_tailq_t; typedef struct { diff --git a/components/esp_driver_sdio/test_apps/.build-test-rules.yml b/components/esp_driver_sdio/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..df1d2c4828f --- /dev/null +++ b/components/esp_driver_sdio/test_apps/.build-test-rules.yml @@ -0,0 +1,17 @@ +components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc: + enable: + - if: IDF_TARGET == "esp32" + temporary: false + reason: always use ESP32 SDMMC as host + depends_components: + - sdmmc + - esp_driver_sdmmc + - esp_driver_sdio + +components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio: + disable: + - if: SOC_SDIO_SLAVE_SUPPORTED != 1 + depends_components: + - sdmmc + - esp_driver_sdmmc + - esp_driver_sdio diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/README.md b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/README.md new file mode 100644 index 00000000000..fbbb3434827 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/README.md @@ -0,0 +1,7 @@ +# SDIO Cross Chips Test Apps + +This folder contains SDIO related tests. This folder contains two sub-folders: +- host_sdmmc: this fodler contains the ESP32 SDMMC test app which works as the host to test the SDIO Slave peripheral +- sdio: this fodler contains the ESP SDIO Slave test apps + +Tests in this folder are all dual-board tests. diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/CMakeLists.txt b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/CMakeLists.txt new file mode 100644 index 00000000000..5c2d9f84cb5 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/CMakeLists.txt @@ -0,0 +1,13 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + +set(EXTRA_COMPONENT_DIRS + "$ENV{IDF_PATH}/tools/unit-test-app/components" + "$ENV{IDF_PATH}/components/driver/test_apps/components" +) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(host_sdmmc) diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md new file mode 100644 index 00000000000..abb7f3c223c --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md @@ -0,0 +1,6 @@ +| Supported Targets | ESP32 | +| ----------------- | ----- | + +# SDIO Cross Chips Test Apps: SDMMC Host App + +This test app is using ESP32 SDMMC as the host to test the SDIO Slave peripherals among ESP chips. diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/CMakeLists.txt b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/CMakeLists.txt new file mode 100644 index 00000000000..28932ca2ce5 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/CMakeLists.txt @@ -0,0 +1,6 @@ +set(srcs "test_app_main.c" + "test_sdio_sdhost.c") + +idf_component_register(SRCS ${srcs} + PRIV_REQUIRES unity test_driver_utils driver esp_serial_slave_link sdmmc test_utils esp_timer + WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/sdio/main/idf_component.yml b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/idf_component.yml similarity index 100% rename from components/driver/test_apps/sdio/main/idf_component.yml rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/idf_component.yml diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_app_main.c b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_app_main.c new file mode 100644 index 00000000000..f32ce071b38 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_app_main.c @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "unity.h" +#include "unity_test_utils.h" +#include "esp_heap_caps.h" + +// Some resources are lazy allocated, the threadhold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (700) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + unity_utils_check_leak(before_free_8bit, after_free_8bit, "8BIT", TEST_MEMORY_LEAK_THRESHOLD); + unity_utils_check_leak(before_free_32bit, after_free_32bit, "32BIT", TEST_MEMORY_LEAK_THRESHOLD); +} + +void app_main(void) +{ + /* _____ ____ ________ _____ ____ __ _____ _________ + / ___// __ \/ _/ __ \ / ___// __ \/ |/ / |/ / ____/ + \__ \/ / / // // / / / \__ \/ / / / /|_/ / /|_/ / / + ___/ / /_/ // // /_/ / ___/ / /_/ / / / / / / / /___ + /____/_____/___/\____/ /____/_____/_/ /_/_/ /_/\____/ + + */ + + printf(" _____ ____ ________ _____ ____ __ _____ _________\n"); + printf(" / ___// __ \\/ _/ __ \\ / ___// __ \\/ |/ / |/ / ____/\n"); + printf(" \\__ \\/ / / // // / / / \\__ \\/ / / / /|_/ / /|_/ / / \n"); + printf(" ___/ / /_/ // // /_/ / ___/ / /_/ / / / / / / / /___ \n"); + printf("/____/_____/___/\\____/ /____/_____/_/ /_/_/ /_/\\____/ \n"); + printf(" \n"); + + unity_run_menu(); +} diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c new file mode 100644 index 00000000000..23ef53a52c4 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c @@ -0,0 +1,351 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * This file uses ESP32 SDMMC peripheral to test SDIO Slave peripheral SD modes + */ + +#include "unity.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_timer.h" +#include "ccomp_timer.h" + +#include "sdmmc_cmd.h" +#include "driver/sdmmc_host.h" +#include "esp_serial_slave_link/essl_sdio.h" +#include "soc/soc_caps.h" + +#include "test_utils.h" +#include "idf_performance.h" +#include "test_dualboard_utils.h" +#include "../../sdio_common_test.h" + +static const char *TAG = "test_sdio_sdhost"; + +#define TEST_HEX_LOG_LEVEL ESP_LOG_DEBUG +#define TEST_INT_MASK_ALL 0xff +#define TEST_REG_ADDR_MAX 60 +#define TEST_TIMEOUT_MAX UINT32_MAX + +typedef struct { + uint32_t host_flags; + uint32_t max_freq_khz; + bool check_data; +} test_sdio_param_t; + +/*--------------------------------------------------------------- + Host Init Settings +---------------------------------------------------------------*/ +static sdmmc_card_t s_card; + +static void s_master_init(test_sdio_param_t *host_param, essl_handle_t *out_handle) +{ + sdmmc_host_t host_config = (sdmmc_host_t)SDMMC_HOST_DEFAULT(); + host_config.flags = host_param->host_flags; + if (host_config.flags == SDMMC_HOST_FLAG_4BIT) { + ESP_LOGI(TAG, "Probe using SD 4-bit..."); + } else if (host_config.flags == SDMMC_HOST_FLAG_1BIT) { + ESP_LOGI(TAG, "Probe using SD 1-bit..."); + } + host_config.max_freq_khz = host_param->max_freq_khz; + ESP_LOGI(TAG, "Host max_freq_khz: %d", host_config.max_freq_khz); + + //init sdmmc host + TEST_ESP_OK(sdmmc_host_init()); + sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); + TEST_ESP_OK(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config)); + + //host init slave + sdmmc_card_t *card = &s_card; + //wait for at least 5 seconds + int retry_times = 5; + do { + if (sdmmc_card_init(&host_config, card) == ESP_OK) { + break; + } + ESP_LOGW(TAG, "slave init failed, retry..."); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } while (--retry_times); + TEST_ASSERT_MESSAGE(retry_times != 0, "Initializing slave failed."); + + //init essl sdmmc host + essl_sdio_config_t essl_sdio_config = { + .card = card, + .recv_buffer_size = TEST_RX_BUFFER_SIZE, + }; + TEST_ESP_OK(essl_sdio_init_dev(out_handle, &essl_sdio_config)); + + TEST_ESP_OK(essl_init(*out_handle, TEST_TIMEOUT_MAX)); +} + +//trigger event 7 to indicate Slave to stop the test +static void s_send_finish_test(essl_handle_t handle) +{ + //the slave needs a signal to quite the test + essl_send_slave_intr(handle, BIT(7), TEST_TIMEOUT_MAX); +} + +/*--------------------------------------------------------------- + Function Tests +---------------------------------------------------------------*/ + +/*--------------------------------------------------------------- + SDMMC_SDIO: test interrupt +---------------------------------------------------------------*/ +TEST_CASE("SDIO_SDMMC: test interrupt", "[sdio]") +{ + esp_err_t ret = ESP_FAIL; + essl_handle_t handle = NULL; + test_sdio_param_t test_param = { + .host_flags = SDMMC_HOST_FLAG_4BIT, + .max_freq_khz = SDMMC_FREQ_HIGHSPEED, + }; + //essl init and sdmmc init + s_master_init(&test_param, &handle); + + TEST_ESP_OK(essl_set_intr_ena(handle, TEST_INT_MASK_ALL, TEST_TIMEOUT_MAX)); + ret = essl_wait_int(handle, 0); + TEST_ASSERT_EQUAL_HEX(ESP_ERR_TIMEOUT, ret); + + //tests all 8 interrupts of the slave, in which int 7 is used to terminate the test on the slave. + for (int i = 0; i < 8; i ++) { + esp_rom_printf("to essl_send_slave_intr\n"); + TEST_ESP_OK(essl_send_slave_intr(handle, BIT(i), TEST_TIMEOUT_MAX)); + //the slave should return interrupt with the same bit in 10 ms + TEST_ESP_OK(essl_wait_int(handle, 10)); + + uint32_t int_st; + TEST_ESP_OK(essl_get_intr(handle, NULL, &int_st, TEST_TIMEOUT_MAX)); + + //check and clear the returned interrupt + TEST_ASSERT_EQUAL_HEX(BIT(i), int_st); + TEST_ESP_OK(essl_clear_intr(handle, int_st, TEST_TIMEOUT_MAX)); + } + + sdmmc_host_deinit(); +} + +/*--------------------------------------------------------------- + SDMMC_SDIO: test register +---------------------------------------------------------------*/ +TEST_CASE("SDIO_SDMMC: test register", "[sdio]") +{ + essl_handle_t handle = NULL; + test_sdio_param_t test_param = { + .host_flags = SDMMC_HOST_FLAG_4BIT, + .max_freq_khz = SDMMC_FREQ_HIGHSPEED, + }; + //essl init and sdmmc init + s_master_init(&test_param, &handle); + + uint32_t init_val = 30; + srand(850); + //initialize the registers + for (int i = 0; i < TEST_REG_ADDR_MAX; i++) { + TEST_ESP_OK(essl_write_reg(handle, i, init_val, NULL, 10)); + } + + for (int i = 0; i < TEST_REG_ADDR_MAX; i++) { + uint8_t data_write = rand() % 0xFF; + TEST_ESP_OK(essl_write_reg(handle, i, data_write, NULL, 10)); + + uint8_t data_read = 0; + TEST_ESP_OK(essl_read_reg(handle, i, &data_read, 10)); + + TEST_ASSERT_EQUAL_HEX8(data_write, data_read); + } + + s_send_finish_test(handle); + sdmmc_host_deinit(); +} + +/*--------------------------------------------------------------- + SDMMC_SDIO: test reset +---------------------------------------------------------------*/ +TEST_CASE("SDIO_SDMMC: test reset", "[sdio]") +{ + essl_handle_t handle = NULL; + test_sdio_param_t test_param = { + .host_flags = SDMMC_HOST_FLAG_4BIT, + .max_freq_khz = SDMMC_FREQ_HIGHSPEED, + }; + //essl init and sdmmc init + s_master_init(&test_param, &handle); + + //wait for the slave to stop, reset and start again + vTaskDelay(10); + + //rx + WORD_ALIGNED_ATTR uint8_t slave_tx_buffer[TEST_RESET_DATA_LEN] = {}; + WORD_ALIGNED_ATTR uint8_t host_rx_buffer[TEST_RESET_DATA_LEN] = {}; + size_t read_len = 0; + for (int i = 0; i < TEST_RESET_BUF_NUMS; i++) { + test_fill_random_to_buffer(i, slave_tx_buffer, TEST_RESET_DATA_LEN); + esp_err_t ret = essl_get_packet(handle, host_rx_buffer, TEST_RESET_DATA_LEN, &read_len, portMAX_DELAY); + if (ret == ESP_ERR_NOT_FINISHED) { + printf("not finished\n"); + ret = ESP_OK; + } + TEST_ESP_OK(ret); + TEST_ASSERT_EQUAL(TEST_RESET_DATA_LEN, read_len); + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_tx_buffer, host_rx_buffer, read_len); + } + + //tx + WORD_ALIGNED_ATTR uint8_t host_tx_buffer[TEST_RESET_BUF_NUMS][TEST_RESET_DATA_LEN] = {}; + for (int i = 0; i < TEST_RESET_BUF_NUMS; i++) { + test_fill_random_to_buffer(i, host_tx_buffer[i], TEST_RESET_DATA_LEN); + TEST_ESP_OK(essl_send_packet(handle, host_tx_buffer[i], TEST_RESET_DATA_LEN, TEST_TIMEOUT_MAX)); + } + + s_send_finish_test(handle); + sdmmc_host_deinit(); +} + +/*--------------------------------------------------------------- + Transaction Tests +---------------------------------------------------------------*/ +test_sdio_param_t test_param_lists[TEST_TARNS_PARAM_NUMS] = { + { + .host_flags = SDMMC_HOST_FLAG_4BIT, + .max_freq_khz = SDMMC_FREQ_HIGHSPEED, + }, + { + .host_flags = SDMMC_HOST_FLAG_1BIT, + .max_freq_khz = SDMMC_FREQ_HIGHSPEED, + }, +}; + +/*--------------------------------------------------------------- + SDMMC_SDIO: test from host +---------------------------------------------------------------*/ +static void test_from_host(bool check_data) +{ + test_prepare_buffer_pool(TEST_RX_BUFFER_SIZE * 4, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + + for (int i = 0; i < TEST_TARNS_PARAM_NUMS; i++) { + ESP_LOGI(TAG, "host mode: %s", (test_param_lists[i].host_flags == SDMMC_HOST_FLAG_4BIT) ? "4BIT Mode" : "1BIT Mode"); + ESP_LOGI(TAG, "host speed: %"PRIu32" kHz", test_param_lists[i].max_freq_khz); + + essl_handle_t handle = NULL; + s_master_init(&test_param_lists[i], &handle); + + // Two counters are used. The `esp_timer_get_time()` is for the typical time, and the + // `ccomp_timer` is for performance test to reduce influence caused by cache miss. + int64_t pre_us = esp_timer_get_time(); + TEST_ESP_OK(ccomp_timer_start()); + uint32_t expected_length = TEST_TRANS_NUMS * TEST_RX_BUFFER_SIZE; + + void *tx_buf_ptr = NULL; + for (int j = 0; j < TEST_TRANS_NUMS; j++) { + ESP_LOGD(TAG, "j: %d", j); + + test_get_buffer_from_pool(j, TEST_RX_BUFFER_SIZE, &tx_buf_ptr); + ESP_LOG_BUFFER_HEX_LEVEL(TAG, tx_buf_ptr, TEST_RX_BUFFER_SIZE, TEST_HEX_LOG_LEVEL); + TEST_ESP_OK(essl_send_packet(handle, tx_buf_ptr, TEST_RX_BUFFER_SIZE, TEST_TIMEOUT_MAX)); + } + + int64_t c_time_ms = ccomp_timer_stop() / 1000; + int64_t end_us = esp_timer_get_time(); + + uint32_t total_time_ms = (end_us - pre_us) / 1000; + ESP_LOGI(TAG, "test done, total time: %" PRIu32 " ms (%d ms compensated), bytes transferred: %"PRIu32, total_time_ms, (int)c_time_ms, expected_length); + + uint32_t throughput_byte_per_ms = expected_length / c_time_ms; + ESP_LOGI(TAG, "Throughput: compensated %"PRIu32"KB/s (%.2lf MB/s), typical %.2lf MB/s", + throughput_byte_per_ms, throughput_byte_per_ms / 1000., expected_length / (total_time_ms * 1000.)); + + esp_rom_delay_us(50 * 1000); + s_send_finish_test(handle); + sdmmc_host_deinit(); + } + + test_destroy_buffer_pool(); +} + +TEST_CASE("SDIO_SDMMC: test from host", "[sdio]") +{ + test_from_host(true); +} + +TEST_CASE("SDIO_SDMMC: test from host (Performance)", "[sdio_speed]") +{ + test_from_host(false); +} + +static void test_to_host(bool check_data) +{ + //prepare buffer + test_prepare_buffer_pool(TEST_RX_BUFFER_SIZE * 21, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + int recv_size = 4096; + uint8_t *host_rx_buffer = (uint8_t *)heap_caps_calloc(1, recv_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + + for (int i = 0; i < TEST_TARNS_PARAM_NUMS; i++) { + ESP_LOGI(TAG, "host mode: %s", (test_param_lists[i].host_flags == SDMMC_HOST_FLAG_4BIT) ? "4BIT Mode" : "1BIT Mode"); + ESP_LOGI(TAG, "host speed: %"PRIu32" kHz", test_param_lists[i].max_freq_khz); + + essl_handle_t handle = NULL; + s_master_init(&test_param_lists[i], &handle); + + esp_err_t ret; + int offset = 0; + void *tx_buf_ptr = NULL; + uint32_t expected_length = TEST_TRANS_NUMS * TEST_RX_BUFFER_SIZE; + int remain_length = expected_length; + + // Two counters are used. The `esp_timer_get_time()` is for the typical time, and the + // `ccomp_timer` is for performance test to reduce influence caused by cache miss. + int64_t pre_us = esp_timer_get_time(); + TEST_ESP_OK(ccomp_timer_start()); + do { + size_t rcv_len; + ret = essl_get_packet(handle, host_rx_buffer, recv_size, &rcv_len, TEST_TIMEOUT_MAX); + TEST_ASSERT(ret == ESP_OK || ret == ESP_ERR_NOT_FINISHED); + TEST_ASSERT_LESS_OR_EQUAL(remain_length, rcv_len); + + if (check_data) { + size_t compared_len = 0; + do { + test_get_buffer_from_pool(offset, TEST_RX_BUFFER_SIZE, &tx_buf_ptr); + TEST_ASSERT_EQUAL_HEX8_ARRAY(tx_buf_ptr, &host_rx_buffer[compared_len], TEST_RX_BUFFER_SIZE); + compared_len += TEST_RX_BUFFER_SIZE; + offset += TEST_RX_BUFFER_SIZE; + } while (compared_len < rcv_len); + } + + remain_length -= rcv_len; + } while (remain_length > 0); + + int64_t c_time_ms = ccomp_timer_stop() / 1000; + int64_t end_us = esp_timer_get_time(); + + uint32_t total_time_ms = (end_us - pre_us) / 1000; + ESP_LOGI(TAG, "test done, total time: %" PRIu32 " ms (%d ms compensated), bytes transferred: %"PRIu32, total_time_ms, (int)c_time_ms, expected_length); + + uint32_t throughput_byte_per_ms = expected_length / c_time_ms; + ESP_LOGI(TAG, "Throughput: compensated %"PRIu32"KB/s %.2lf MB/s, typical %.2lf MB/s", + throughput_byte_per_ms, throughput_byte_per_ms / 1000., expected_length / (total_time_ms * 1000.)); + + esp_rom_delay_us(50 * 1000); + s_send_finish_test(handle); + sdmmc_host_deinit(); + } + + free(host_rx_buffer); + test_destroy_buffer_pool(); +} + +TEST_CASE("SDIO_SDMMC: test to host", "[sdio]") +{ + test_to_host(true); +} + +TEST_CASE("SDIO_SDMMC: test to host (Performance)", "[sdio_speed]") +{ + test_to_host(false); +} diff --git a/components/driver/test_apps/spi/master/sdkconfig.ci.defaults b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/sdkconfig.ci.default similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.ci.defaults rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/sdkconfig.ci.default diff --git a/components/driver/test_apps/rs485/sdkconfig.defaults b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/rs485/sdkconfig.defaults rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/sdkconfig.defaults diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py new file mode 100644 index 00000000000..e0e6f3ebf73 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py @@ -0,0 +1,133 @@ +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import os.path +from typing import Tuple + +import pytest +from pytest_embedded_idf import IdfDut + + +# Normal tests +def test_sdio_flow(dut:Tuple[IdfDut, IdfDut]) -> None: + dut[1].expect('Press ENTER to see the list of tests') + dut[1].write('[sdio]') + dut[1].expect('test_sdio: slave ready') + + dut[0].expect('Press ENTER to see the list of tests') + dut[0].write('[sdio]') + + dut[1].expect_unity_test_output() + dut[0].expect_unity_test_output() + + +@pytest.mark.esp32c6 +@pytest.mark.sdio_multidev_32_c6 +@pytest.mark.parametrize('count', [2,], indirect=True) +@pytest.mark.parametrize('app_path, target', [ + pytest.param( + f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', + 'esp32|esp32c6'), +], indirect=True) +def test_sdio_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None: + test_sdio_flow(dut) + + +@pytest.mark.esp32 +@pytest.mark.sdio_master_slave +@pytest.mark.parametrize('count', [2,], indirect=True) +@pytest.mark.parametrize('app_path, target', [ + pytest.param( + f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', + 'esp32|esp32'), +], indirect=True) +def test_sdio_esp32_esp32(dut:Tuple[IdfDut, IdfDut]) -> None: + test_sdio_flow(dut) + + +# From host speed tests +def test_sdio_speed_frhost_flow(dut:Tuple[IdfDut, IdfDut], expected_4b_speed:int, expected_1b_speed:int) -> None: + dut[1].expect('Press ENTER to see the list of tests') + dut[1].write('"SDIO_Slave: test from host (Performance)"') + dut[1].expect('test_sdio: slave ready') + + dut[0].expect('Press ENTER to see the list of tests') + dut[0].write('"SDIO_SDMMC: test from host (Performance)"') + + dut[0].expect('Probe using SD 4-bit') + res = dut[0].expect(r'Throughput: compensated (\d+)') + frhost_speed_4bit = res.group(1).decode('utf8') + assert (int(frhost_speed_4bit) > expected_4b_speed) + + dut[0].expect('Probe using SD 1-bit') + res = dut[0].expect(r'Throughput: compensated (\d+)') + frhost_speed_1bit = res.group(1).decode('utf8') + assert (int(frhost_speed_1bit) > expected_1b_speed) + + +@pytest.mark.esp32c6 +@pytest.mark.sdio_multidev_32_c6 +@pytest.mark.parametrize('count', [2,], indirect=True) +@pytest.mark.parametrize('app_path, target', [ + pytest.param( + f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', + 'esp32|esp32c6'), +], indirect=True) +def test_sdio_speed_frhost_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None: + test_sdio_speed_frhost_flow(dut, 10000, 4000) + + +@pytest.mark.esp32 +@pytest.mark.sdio_master_slave +@pytest.mark.parametrize('count', [2,], indirect=True) +@pytest.mark.parametrize('app_path, target', [ + pytest.param( + f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', + 'esp32|esp32'), +], indirect=True) +def test_sdio_speed_frhost_esp32_esp32(dut:Tuple[IdfDut, IdfDut]) -> None: + test_sdio_speed_frhost_flow(dut, 12200, 4000) + + +# To host speed tests +def test_sdio_speed_tohost_flow(dut:Tuple[IdfDut, IdfDut], expected_4b_speed:int, expected_1b_speed:int) -> None: + dut[1].expect('Press ENTER to see the list of tests') + dut[1].write('"SDIO_Slave: test to host (Performance)"') + dut[1].expect('test_sdio: slave ready') + + dut[0].expect('Press ENTER to see the list of tests') + dut[0].write('"SDIO_SDMMC: test to host (Performance)"') + + dut[0].expect('Probe using SD 4-bit') + res = dut[0].expect(r'Throughput: compensated (\d+)') + tohost_speed_4bit = res.group(1).decode('utf8') + assert (int(tohost_speed_4bit) > expected_4b_speed) + + dut[0].expect('Probe using SD 1-bit') + res = dut[0].expect(r'Throughput: compensated (\d+)') + tohost_speed_1bit = res.group(1).decode('utf8') + assert (int(tohost_speed_1bit) > expected_1b_speed) + + +@pytest.mark.esp32c6 +@pytest.mark.sdio_multidev_32_c6 +@pytest.mark.parametrize('count', [2,], indirect=True) +@pytest.mark.parametrize('app_path, target', [ + pytest.param( + f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', + 'esp32|esp32c6'), +], indirect=True) +def test_sdio_speed_tohost_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None: + test_sdio_speed_tohost_flow(dut, 9000, 4000) + + +@pytest.mark.esp32 +@pytest.mark.sdio_master_slave +@pytest.mark.parametrize('count', [2,], indirect=True) +@pytest.mark.parametrize('app_path, target', [ + pytest.param( + f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', + 'esp32|esp32'), +], indirect=True) +def test_sdio_speed_tohost_esp32_esp32(dut:Tuple[IdfDut, IdfDut]) -> None: + test_sdio_speed_tohost_flow(dut, 12200, 4000) diff --git a/components/driver/test_apps/sdio/CMakeLists.txt b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt similarity index 95% rename from components/driver/test_apps/sdio/CMakeLists.txt rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt index 33e36e53351..40ea327d0b5 100644 --- a/components/driver/test_apps/sdio/CMakeLists.txt +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt @@ -10,4 +10,4 @@ set(EXTRA_COMPONENT_DIRS ) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(sdio_test) +project(sdio) diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/README.md b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/README.md new file mode 100644 index 00000000000..d222ec2f7dd --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/README.md @@ -0,0 +1,6 @@ +| Supported Targets | ESP32 | ESP32-C6 | +| ----------------- | ----- | -------- | + +# SDIO Cross Chips Test Apps: SDIO Slave App + +This test app is to test ESP SDIO Slave peripheral. diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt new file mode 100644 index 00000000000..94e0034a58b --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt @@ -0,0 +1,6 @@ +set(srcs "test_app_main.c" + "test_sdio_slave.c") + +idf_component_register(SRCS ${srcs} + PRIV_REQUIRES test_driver_utils driver + WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/sdio/main/test_app_main.c b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_app_main.c similarity index 50% rename from components/driver/test_apps/sdio/main/test_app_main.c rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_app_main.c index adf43817e8a..de8b75a1353 100644 --- a/components/driver/test_apps/sdio/main/test_app_main.c +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_app_main.c @@ -1,15 +1,15 @@ /* * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ #include "unity.h" #include "unity_test_utils.h" #include "esp_heap_caps.h" - -#define TEST_MEMORY_LEAK_THRESHOLD (200) +// Some resources are lazy allocated, the threadhold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (300) static size_t before_free_8bit; static size_t before_free_32bit; @@ -22,27 +22,28 @@ void setUp(void) void tearDown(void) { - esp_reent_cleanup(); //clean up some of the newlib's lazy allocations size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); - printf("\n"); unity_utils_check_leak(before_free_8bit, after_free_8bit, "8BIT", TEST_MEMORY_LEAK_THRESHOLD); unity_utils_check_leak(before_free_32bit, after_free_32bit, "32BIT", TEST_MEMORY_LEAK_THRESHOLD); } void app_main(void) { - // _____ _ _ _ - // |_ _|__ ___| |_ ___ __| (_) ___ - // | |/ _ \/ __| __| / __|/ _` | |/ _ `. - // | | __/\__ \ |_ \__ \ (_| | | (_) | - // |_|\___||___/\__| |___/\__,_|_|\___/ - - printf(" _____ _ _ _ \n"); - printf(" |_ _|__ ___| |_ ___ __| (_) ___ \n"); - printf(" | |/ _ \\/ __| __| / __|/ _` | |/ _ \\ \n"); - printf(" | | __/\\__ \\ |_ \\__ \\ (_| | | (_) |\n"); - printf(" |_|\\___||___/\\__| |___/\\__,_|_|\\___/ \n"); + /* + _____ ____ ________ _____ __ + / ___// __ \/ _/ __ \ / ___// /___ __ _____ + \__ \/ / / // // / / / \__ \/ / __ `/ | / / _ \ + ___/ / /_/ // // /_/ / ___/ / / /_/ /| |/ / __/ + /____/_____/___/\____/ /____/_/\__,_/ |___/\___/ + + */ + + printf(" _____ ____ ________ _____ __ \n"); + printf(" / ___// __ \\/ _/ __ \\ / ___// /___ __ _____ \n"); + printf(" \\__ \\/ / / // // / / / \\__ \\/ / __ `/ | / / _ \\\n"); + printf(" ___/ / /_/ // // /_/ / ___/ / / /_/ /| |/ / __/\n"); + printf("/____/_____/___/\\____/ /____/_/\\__,_/ |___/\\___/\n"); unity_run_menu(); } diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c new file mode 100644 index 00000000000..ca3e6816d2e --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c @@ -0,0 +1,293 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * This file uses ESP32 SDMMC peripheral to test SDIO Slave peripheral SD modes + */ + +#include "unity.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "driver/sdio_slave.h" +#include "soc/soc_caps.h" +#include "soc/sdio_slave_pins.h" + +#include "test_dualboard_utils.h" +#include "../../sdio_common_test.h" + +#define TEST_HEX_LOG_LEVEL ESP_LOG_DEBUG +#define TEST_SDIO_SLAVE_QUEUE_SIZE 20 + +static const char *TAG = "test_sdio"; + +/*--------------------------------------------------------------- + Slave Init Settings +---------------------------------------------------------------*/ +typedef struct { + int queued_cnt; + bool s_finished; +} s_test_slv_ctx_t; + +static s_test_slv_ctx_t s_test_slv_ctx; + +//callback to event 7, indicating test finish in these tests +static void s_event_cb(uint8_t event) +{ + ESP_EARLY_LOGI(TAG, "event: %d", event); + sdio_slave_send_host_int(event); + if (event == 7) { + s_test_slv_ctx.s_finished = true; + } +} + +static void wait_for_finish(s_test_slv_ctx_t *ctx) +{ + while (!ctx->s_finished) { + vTaskDelay(10); + } + //wait for host to read the respond from slave + vTaskDelay(10); +} + +static void s_slave_init(sdio_slave_sending_mode_t mode) +{ + s_test_slv_ctx.s_finished = false; + s_test_slv_ctx.queued_cnt = 0; + + sdio_slave_config_t slave_config = { + .sending_mode = mode, + .send_queue_size = TEST_SDIO_SLAVE_QUEUE_SIZE, + .recv_buffer_size = TEST_RX_BUFFER_SIZE, + .event_cb = s_event_cb, + }; + TEST_ESP_OK(sdio_slave_initialize(&slave_config)); +} + +/*--------------------------------------------------------------- + Function Tests +---------------------------------------------------------------*/ + +/*--------------------------------------------------------------- + SDMMC_SDIO: test interrupt +---------------------------------------------------------------*/ +TEST_CASE("SDIO_Slave: test interrupt", "[sdio]") +{ + s_slave_init(SDIO_SLAVE_SEND_STREAM); + TEST_ESP_OK(sdio_slave_start()); + ESP_LOGI(TAG, "slave ready"); + + wait_for_finish(&s_test_slv_ctx); + + sdio_slave_stop(); + sdio_slave_deinit(); +} + +/*--------------------------------------------------------------- + SDMMC_SDIO: test register +---------------------------------------------------------------*/ +TEST_CASE("SDIO_Slave: test register", "[sdio]") +{ + s_slave_init(SDIO_SLAVE_SEND_STREAM); + TEST_ESP_OK(sdio_slave_start()); + ESP_LOGI(TAG, "slave ready"); + + wait_for_finish(&s_test_slv_ctx); + + sdio_slave_stop(); + sdio_slave_deinit(); +} + +/*--------------------------------------------------------------- + SDMMC_SDIO: test reset +---------------------------------------------------------------*/ +TEST_CASE("SDIO_Slave: test reset", "[sdio]") +{ + s_slave_init(SDIO_SLAVE_SEND_PACKET); + TEST_ESP_OK(sdio_slave_start()); + ESP_LOGI(TAG, "slave ready"); + + sdio_slave_stop(); + TEST_ESP_OK(sdio_slave_reset()); + TEST_ESP_OK(sdio_slave_start()); + + //tx + WORD_ALIGNED_ATTR uint8_t slave_tx_buffer[TEST_RESET_BUF_NUMS][TEST_RESET_DATA_LEN] = {}; + for (int i = 0; i < TEST_RESET_BUF_NUMS; i++) { + test_fill_random_to_buffer(i, slave_tx_buffer[i], TEST_RESET_DATA_LEN); + TEST_ESP_OK(sdio_slave_send_queue(slave_tx_buffer[i], TEST_RESET_DATA_LEN, (void *)i, portMAX_DELAY)); + } + + //rx + sdio_slave_buf_handle_t buf_handle[TEST_RESET_BUF_NUMS] = {}; + WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[TEST_RESET_BUF_NUMS][TEST_RESET_DATA_LEN] = {}; + + for (int i = 0; i < TEST_RESET_BUF_NUMS; i++) { + buf_handle[i] = sdio_slave_recv_register_buf(slave_rx_buffer[i]); + TEST_ASSERT(buf_handle[i]); + TEST_ESP_OK(sdio_slave_recv_load_buf(buf_handle[i])); + } + + for (int i = 0; i < TEST_RESET_BUF_NUMS; i++) { + void* arg; + TEST_ESP_OK(sdio_slave_send_get_finished(&arg, portMAX_DELAY)); + TEST_ASSERT_EQUAL(i, arg); + } + + WORD_ALIGNED_ATTR uint8_t host_tx_buffer[TEST_RESET_DATA_LEN] = {}; + for (int i = 0; i < TEST_RESET_BUF_NUMS; i++) { + test_fill_random_to_buffer(i, host_tx_buffer, TEST_RESET_DATA_LEN); + uint8_t* addr; + size_t size; + sdio_slave_buf_handle_t recv_handle; + TEST_ESP_OK(sdio_slave_recv(&recv_handle, &addr, &size, portMAX_DELAY)); + TEST_ASSERT_EQUAL(TEST_RESET_DATA_LEN, size); + TEST_ASSERT_EQUAL_HEX8_ARRAY(host_tx_buffer, addr, size); + } + + wait_for_finish(&s_test_slv_ctx); + + sdio_slave_stop(); + sdio_slave_deinit(); +} + +/*--------------------------------------------------------------- + Transaction Tests +---------------------------------------------------------------*/ +#define TEST_SLAVE_TRANS_BUF_NUMS 10 + +/*--------------------------------------------------------------- + From Host Tests +---------------------------------------------------------------*/ +static void test_from_host(bool check_data) +{ + //prepare buffer + test_prepare_buffer_pool(TEST_RX_BUFFER_SIZE * 4, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + uint8_t *slave_rx_buffer[TEST_SLAVE_TRANS_BUF_NUMS] = {}; + for (int i = 0; i < TEST_SLAVE_TRANS_BUF_NUMS; i++) { + slave_rx_buffer[i] = (uint8_t *)heap_caps_calloc(1, TEST_RX_BUFFER_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + TEST_ASSERT(slave_rx_buffer[i]); + } + + for (int i = 0; i < TEST_TARNS_PARAM_NUMS; i++) { + //slave init + s_slave_init(SDIO_SLAVE_SEND_STREAM); + TEST_ESP_OK(sdio_slave_start()); + ESP_LOGI(TAG, "slave ready"); + + //slave load rx buffer + sdio_slave_buf_handle_t buf_handle[TEST_SLAVE_TRANS_BUF_NUMS] = {}; + for (int j = 0; j < TEST_SLAVE_TRANS_BUF_NUMS; j++) { + buf_handle[j] = sdio_slave_recv_register_buf(slave_rx_buffer[j]); + TEST_ASSERT(buf_handle[j]); + TEST_ESP_OK(sdio_slave_recv_load_buf(buf_handle[j])); + } + + void *tx_buf_ptr = NULL; + for (int j = 0; j < TEST_TRANS_NUMS; j++) { + ESP_LOGD(TAG, "j: %d", j); + + sdio_slave_buf_handle_t used_buf_handle = NULL; + uint8_t* buf = NULL; + size_t rcv_len = 0; + + TEST_ESP_OK(sdio_slave_recv(&used_buf_handle, &buf, &rcv_len, portMAX_DELAY)); + ESP_LOGD(TAG, "rcv_len: 0d%d", rcv_len); + ESP_LOG_BUFFER_HEX_LEVEL(TAG, buf, TEST_RX_BUFFER_SIZE, TEST_HEX_LOG_LEVEL); + + if (check_data) { + test_get_buffer_from_pool(j, TEST_RX_BUFFER_SIZE, &tx_buf_ptr); + ESP_LOG_BUFFER_HEX_LEVEL("Expect data", tx_buf_ptr, TEST_RX_BUFFER_SIZE, TEST_HEX_LOG_LEVEL); + TEST_ASSERT_EQUAL_HEX8_ARRAY(tx_buf_ptr, buf, rcv_len); + } + + TEST_ESP_OK(sdio_slave_recv_load_buf(used_buf_handle)); + } + + wait_for_finish(&s_test_slv_ctx); + sdio_slave_stop(); + sdio_slave_deinit(); + } + + for (int i = 0; i < TEST_SLAVE_TRANS_BUF_NUMS; i++) { + free(slave_rx_buffer[i]); + } + test_destroy_buffer_pool(); +} + +TEST_CASE("SDIO_Slave: test from host", "[sdio]") +{ + test_from_host(true); +} + +TEST_CASE("SDIO_Slave: test from host (Performance)", "[sdio_speed]") +{ + test_from_host(false); +} + +/*--------------------------------------------------------------- + To Host Tests +---------------------------------------------------------------*/ +#define QUEUE_FULL() (s_test_slv_ctx.queued_cnt == TEST_SDIO_SLAVE_QUEUE_SIZE) +#define QUEUE_EMPTY() (s_test_slv_ctx.queued_cnt == 0) + +static void test_to_host(void) +{ + //prepare buffer + test_prepare_buffer_pool(TEST_RX_BUFFER_SIZE * 21, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + + for (int i = 0; i < TEST_TARNS_PARAM_NUMS; i++) { + //slave init + s_slave_init(SDIO_SLAVE_SEND_STREAM); + TEST_ESP_OK(sdio_slave_start()); + ESP_LOGI(TAG, "slave ready"); + + esp_err_t err = ESP_OK; + int offset = 0; + void *tx_buf_ptr = NULL; + for (int j = 0; j < TEST_TRANS_NUMS; j++) { + do { + void* arg; + //when the queue is full, do a blocking wait for 10ms, otherwise non-blocking + err = sdio_slave_send_get_finished(&arg, QUEUE_FULL() ? 1 : 0); + if (err == ESP_OK) { + s_test_slv_ctx.queued_cnt --; + continue; + } + TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, err); + } while (QUEUE_FULL()); + + test_get_buffer_from_pool(offset, TEST_RX_BUFFER_SIZE, &tx_buf_ptr); + TEST_ESP_OK(sdio_slave_send_queue((uint8_t *)tx_buf_ptr, TEST_RX_BUFFER_SIZE, NULL, portMAX_DELAY)); + + s_test_slv_ctx.queued_cnt++; + offset += TEST_RX_BUFFER_SIZE; + } + + while (!QUEUE_EMPTY()) { + void* arg; + TEST_ESP_OK(sdio_slave_send_get_finished(&arg, portMAX_DELAY)); + s_test_slv_ctx.queued_cnt--; + } + + wait_for_finish(&s_test_slv_ctx); + sdio_slave_stop(); + sdio_slave_deinit(); + } + + test_destroy_buffer_pool(); +} + +TEST_CASE("SDIO_Slave: test to host", "[sdio]") +{ + test_to_host(); +} + +TEST_CASE("SDIO_Slave: test to host (Performance)", "[sdio_speed]") +{ + test_to_host(); +} diff --git a/components/driver/test_apps/spi/slave/sdkconfig.ci.defaults b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.ci.default similarity index 100% rename from components/driver/test_apps/spi/slave/sdkconfig.ci.defaults rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.ci.default diff --git a/components/driver/test_apps/sdio/sdkconfig.defaults b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/sdio/sdkconfig.defaults rename to components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.defaults diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio_common_test.h b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio_common_test.h new file mode 100644 index 00000000000..2f857f42464 --- /dev/null +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio_common_test.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define TEST_RX_BUFFER_SIZE 2048 + +/*--------------------------------------------------------------- + Function Tests +---------------------------------------------------------------*/ +/*--------------------------------------------------------------- + SDMMC_SDIO: test reset +---------------------------------------------------------------*/ +#define TEST_RESET_DATA_LEN 12 +#define TEST_RESET_BUF_NUMS 10 + +/*--------------------------------------------------------------- + Transaction Tests +---------------------------------------------------------------*/ +#define TEST_TARNS_PARAM_NUMS 2 +/*--------------------------------------------------------------- + SDMMC_SDIO: test from host +---------------------------------------------------------------*/ +#define TEST_TRANS_NUMS 10000 + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_sdm/CMakeLists.txt b/components/esp_driver_sdm/CMakeLists.txt new file mode 100644 index 00000000000..b7d5031dc83 --- /dev/null +++ b/components/esp_driver_sdm/CMakeLists.txt @@ -0,0 +1,11 @@ +set(srcs) +set(public_include "include") +if(CONFIG_SOC_SDM_SUPPORTED) + list(APPEND srcs "src/sdm.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES "esp_pm" "esp_driver_gpio" + LDFRAGMENTS "linker.lf" + ) diff --git a/components/esp_driver_sdm/Kconfig b/components/esp_driver_sdm/Kconfig new file mode 100644 index 00000000000..b572c4ab9fa --- /dev/null +++ b/components/esp_driver_sdm/Kconfig @@ -0,0 +1,25 @@ +menu "ESP-Driver:Sigma Delta Modulator Configurations" + depends on SOC_SDM_SUPPORTED + config SDM_CTRL_FUNC_IN_IRAM + bool "Place SDM control functions into IRAM" + default n + help + Place SDM control functions (like set_duty) into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + Enabling this option can improve driver performance as well. + + config SDM_SUPPRESS_DEPRECATE_WARN + bool "Suppress legacy driver deprecated warning" + default n + help + Wether to suppress the deprecation warnings when using legacy sigma delta driver. + If you want to continue using the legacy driver, and don't want to see related deprecation warnings, + you can enable this option. + + config SDM_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for SDM driver. + Note that, this option only controls the SDM driver log, won't affect other drivers. +endmenu # Sigma Delta Modulator Configurations diff --git a/components/driver/sigma_delta/include/driver/sdm.h b/components/esp_driver_sdm/include/driver/sdm.h similarity index 100% rename from components/driver/sigma_delta/include/driver/sdm.h rename to components/esp_driver_sdm/include/driver/sdm.h diff --git a/components/esp_driver_sdm/linker.lf b/components/esp_driver_sdm/linker.lf new file mode 100644 index 00000000000..37812f1e53c --- /dev/null +++ b/components/esp_driver_sdm/linker.lf @@ -0,0 +1,5 @@ +[mapping:sdm_driver] +archive: libesp_driver_sdm.a +entries: + if SDM_CTRL_FUNC_IN_IRAM = y: + sdm: sdm_channel_set_pulse_density (noflash) diff --git a/components/driver/sigma_delta/sdm.c b/components/esp_driver_sdm/src/sdm.c similarity index 98% rename from components/driver/sigma_delta/sdm.c rename to components/esp_driver_sdm/src/sdm.c index 2ad46375bbc..2856604f460 100644 --- a/components/driver/sigma_delta/sdm.c +++ b/components/esp_driver_sdm/src/sdm.c @@ -210,7 +210,7 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_ ESP_GOTO_ON_FALSE(group->clk_src == 0 || group->clk_src == config->clk_src, ESP_ERR_INVALID_ARG, err, TAG, "clock source conflict"); uint32_t src_clk_hz = 0; ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), err, TAG, "get source clock frequency failed"); + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), err, TAG, "get source clock frequency failed"); #if CONFIG_PM_ENABLE esp_pm_lock_type_t pm_type = ESP_PM_NO_LIGHT_SLEEP; diff --git a/components/esp_driver_sdm/test_apps/.build-test-rules.yml b/components/esp_driver_sdm/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..77a14a95759 --- /dev/null +++ b/components/esp_driver_sdm/test_apps/.build-test-rules.yml @@ -0,0 +1,8 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_sdm/test_apps/sigma_delta: + disable: + - if: SOC_SDM_SUPPORTED != 1 + depends_components: + - esp_driver_gpio + - esp_driver_sdm diff --git a/components/driver/test_apps/sigma_delta/CMakeLists.txt b/components/esp_driver_sdm/test_apps/sigma_delta/CMakeLists.txt similarity index 87% rename from components/driver/test_apps/sigma_delta/CMakeLists.txt rename to components/esp_driver_sdm/test_apps/sigma_delta/CMakeLists.txt index 2150ef0e3a7..7ad2bd49baf 100644 --- a/components/driver/test_apps/sigma_delta/CMakeLists.txt +++ b/components/esp_driver_sdm/test_apps/sigma_delta/CMakeLists.txt @@ -10,7 +10,7 @@ project(sigma_delta_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_sdm/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/sigma_delta_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/sigma_delta/README.md b/components/esp_driver_sdm/test_apps/sigma_delta/README.md similarity index 66% rename from components/driver/test_apps/sigma_delta/README.md rename to components/esp_driver_sdm/test_apps/sigma_delta/README.md index 19f1d19a549..a79fcf4c5ea 100644 --- a/components/driver/test_apps/sigma_delta/README.md +++ b/components/esp_driver_sdm/test_apps/sigma_delta/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/sigma_delta/main/CMakeLists.txt b/components/esp_driver_sdm/test_apps/sigma_delta/main/CMakeLists.txt similarity index 84% rename from components/driver/test_apps/sigma_delta/main/CMakeLists.txt rename to components/esp_driver_sdm/test_apps/sigma_delta/main/CMakeLists.txt index 29c6893034e..54847204313 100644 --- a/components/driver/test_apps/sigma_delta/main/CMakeLists.txt +++ b/components/esp_driver_sdm/test_apps/sigma_delta/main/CMakeLists.txt @@ -7,5 +7,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver + PRIV_REQUIRES unity esp_driver_sdm WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/sigma_delta/main/test_app_main.c b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/sigma_delta/main/test_app_main.c rename to components/esp_driver_sdm/test_apps/sigma_delta/main/test_app_main.c diff --git a/components/driver/test_apps/sigma_delta/main/test_sdm.c b/components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.c similarity index 100% rename from components/driver/test_apps/sigma_delta/main/test_sdm.c rename to components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.c diff --git a/components/driver/test_apps/sigma_delta/pytest_sigma_delta.py b/components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py similarity index 100% rename from components/driver/test_apps/sigma_delta/pytest_sigma_delta.py rename to components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py diff --git a/components/driver/test_apps/sigma_delta/sdkconfig.ci.iram_safe b/components/esp_driver_sdm/test_apps/sigma_delta/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/sigma_delta/sdkconfig.ci.iram_safe rename to components/esp_driver_sdm/test_apps/sigma_delta/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/rs485/sdkconfig.ci.release b/components/esp_driver_sdm/test_apps/sigma_delta/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/rs485/sdkconfig.ci.release rename to components/esp_driver_sdm/test_apps/sigma_delta/sdkconfig.ci.release diff --git a/components/driver/test_apps/sigma_delta/sdkconfig.defaults b/components/esp_driver_sdm/test_apps/sigma_delta/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/sigma_delta/sdkconfig.defaults rename to components/esp_driver_sdm/test_apps/sigma_delta/sdkconfig.defaults diff --git a/components/esp_driver_sdmmc/CMakeLists.txt b/components/esp_driver_sdmmc/CMakeLists.txt new file mode 100644 index 00000000000..afca5125308 --- /dev/null +++ b/components/esp_driver_sdmmc/CMakeLists.txt @@ -0,0 +1,15 @@ +set(srcs) + +set(public_include "include") + +# SDMMC related source files +if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) + list(APPEND srcs "src/sdmmc_transaction.c" + "src/sdmmc_host.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + REQUIRES sdmmc esp_driver_gpio + PRIV_REQUIRES esp_timer esp_pm esp_mm + ) diff --git a/components/esp_driver_sdmmc/README.md b/components/esp_driver_sdmmc/README.md new file mode 100644 index 00000000000..2bdde243479 --- /dev/null +++ b/components/esp_driver_sdmmc/README.md @@ -0,0 +1,19 @@ +# SDMMC Host Driver + +SD Host side related components are: +- `sdmmc` +- `esp_driver_sdmmc` (current component) +- `esp_driver_sdspi` + +For relationship and dependency among these components, see [SD Host Side Related Component Architecture](../sdmmc/README.md). + +`esp_driver_sdmmc` components holds SDMMC Host driver for ESP SDMMC peripheral, this driver provides APIs to help you: +- do SD transactions (under SD mode) via ESP SDMMC peripheral. +- tune ESP SDMMC hardware configurations, such as clock frequency, bus width, etc. +- ... + +You can +- use this driver to implement `sdmmc` protocol interfaces +- directly use `esp_driver_sdmmc` APIs + +to communicate with SD slave devices under SD mode. diff --git a/components/driver/sdmmc/include/driver/sdmmc_default_configs.h b/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h similarity index 99% rename from components/driver/sdmmc/include/driver/sdmmc_default_configs.h rename to components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h index 4ffef8fe84d..52a7ae22204 100644 --- a/components/driver/sdmmc/include/driver/sdmmc_default_configs.h +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h @@ -50,8 +50,6 @@ extern "C" { #define SDMMC_SLOT_NO_WP GPIO_NUM_NC ///< indicates that write protect line is not used #define SDMMC_SLOT_WIDTH_DEFAULT 0 ///< use the maximum possible width for the slot - - #if SOC_SDMMC_USE_IOMUX && !SOC_SDMMC_USE_GPIO_MATRIX /** * Macro defining default configuration of SDMMC host slot diff --git a/components/esp_netif/linux/stubs/include/machine/endian.h b/components/esp_driver_sdmmc/include/driver/sdmmc_defs.h similarity index 81% rename from components/esp_netif/linux/stubs/include/machine/endian.h rename to components/esp_driver_sdmmc/include/driver/sdmmc_defs.h index 120152bdabb..5e2f32b5024 100644 --- a/components/esp_netif/linux/stubs/include/machine/endian.h +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_defs.h @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #pragma once -#include_next +#include "sd_protocol_defs.h" diff --git a/components/driver/sdmmc/include/driver/sdmmc_host.h b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h similarity index 95% rename from components/driver/sdmmc/include/driver/sdmmc_host.h rename to components/esp_driver_sdmmc/include/driver/sdmmc_host.h index c9804e543b1..3a4de21bcae 100644 --- a/components/driver/sdmmc/include/driver/sdmmc_host.h +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h @@ -12,7 +12,7 @@ #include #include #include "esp_err.h" -#include "sdmmc_types.h" +#include "driver/sdmmc_types.h" #include "driver/sdmmc_default_configs.h" #include "driver/gpio.h" @@ -47,15 +47,15 @@ typedef struct { uint8_t width; ///< Bus width used by the slot (might be less than the max width supported) uint32_t flags; ///< Features used by this slot #define SDMMC_SLOT_FLAG_INTERNAL_PULLUP BIT(0) - /**< Enable internal pullups on enabled pins. The internal pullups - are insufficient however, please make sure external pullups are - connected on the bus. This is for debug / example purpose only. - */ + /**< Enable internal pullups on enabled pins. The internal pullups + are insufficient however, please make sure external pullups are + connected on the bus. This is for debug / example purpose only. + */ #define SDMMC_SLOT_FLAG_WP_ACTIVE_HIGH BIT(1) - /**< GPIO write protect polarity. - * 0 means "active low", i.e. card is protected when the GPIO is low; - * 1 means "active high", i.e. card is protected when GPIO is high. - */ + /**< GPIO write protect polarity. + * 0 means "active low", i.e. card is protected when the GPIO is low; + * 1 means "active high", i.e. card is protected when GPIO is high. + */ } sdmmc_slot_config_t; /** diff --git a/components/fatfs/host_test/main/main.cpp b/components/esp_driver_sdmmc/include/driver/sdmmc_types.h similarity index 71% rename from components/fatfs/host_test/main/main.cpp rename to components/esp_driver_sdmmc/include/driver/sdmmc_types.h index cd66dc30832..cc832d8a2b8 100644 --- a/components/fatfs/host_test/main/main.cpp +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_types.h @@ -3,5 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#define CATCH_CONFIG_MAIN -#include "catch.hpp" + +#pragma once + +#include "sd_protocol_types.h" diff --git a/components/driver/sdmmc/sdmmc_host.c b/components/esp_driver_sdmmc/src/sdmmc_host.c similarity index 96% rename from components/driver/sdmmc/sdmmc_host.c rename to components/esp_driver_sdmmc/src/sdmmc_host.c index f6f1e3e47c2..cbfe397aa88 100644 --- a/components/driver/sdmmc/sdmmc_host.c +++ b/components/esp_driver_sdmmc/src/sdmmc_host.c @@ -45,7 +45,6 @@ #define SDMMC_CLK_SRC_ATOMIC() #endif - static const char *TAG = "sdmmc_periph"; /** @@ -70,7 +69,6 @@ typedef struct host_ctx_t { static host_ctx_t s_host_ctx; - static void sdmmc_isr(void *arg); static void sdmmc_host_dma_init(void); static esp_err_t sdmmc_host_pullup_en_internal(int slot, int width); @@ -209,10 +207,10 @@ void sdmmc_host_get_clk_dividers(uint32_t freq_khz, int *host_div, int *card_div * effective frequency range: 400 kHz - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme) */ *host_div = (clk_src_freq_hz) / (freq_khz * 1000); - if (*host_div > 15 ) { + if (*host_div > 15) { *host_div = 2; *card_div = (clk_src_freq_hz / 2) / (2 * freq_khz * 1000); - if ( ((clk_src_freq_hz / 2) % (2 * freq_khz * 1000)) > 0 ) { + if (((clk_src_freq_hz / 2) % (2 * freq_khz * 1000)) > 0) { (*card_div)++; } } else if ((clk_src_freq_hz % (freq_khz * 1000)) > 0) { @@ -315,22 +313,22 @@ esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase) int delay_phase_num = 0; sdmmc_ll_delay_phase_t phase = SDMMC_LL_DELAY_PHASE_0; switch (delay_phase) { - case SDMMC_DELAY_PHASE_1: - phase = SDMMC_LL_DELAY_PHASE_1; - delay_phase_num = 1; - break; - case SDMMC_DELAY_PHASE_2: - phase = SDMMC_LL_DELAY_PHASE_2; - delay_phase_num = 2; - break; - case SDMMC_DELAY_PHASE_3: - phase = SDMMC_LL_DELAY_PHASE_3; - delay_phase_num = 3; - break; - default: - phase = SDMMC_LL_DELAY_PHASE_0; - delay_phase_num = 0; - break; + case SDMMC_DELAY_PHASE_1: + phase = SDMMC_LL_DELAY_PHASE_1; + delay_phase_num = 1; + break; + case SDMMC_DELAY_PHASE_2: + phase = SDMMC_LL_DELAY_PHASE_2; + delay_phase_num = 2; + break; + case SDMMC_DELAY_PHASE_3: + phase = SDMMC_LL_DELAY_PHASE_3; + delay_phase_num = 3; + break; + default: + phase = SDMMC_LL_DELAY_PHASE_0; + delay_phase_num = 0; + break; } SDMMC_CLK_SRC_ATOMIC() { sdmmc_ll_set_din_delay(s_host_ctx.hal.dev, phase); @@ -433,13 +431,13 @@ esp_err_t sdmmc_host_init(void) } // Enable interrupts SDMMC.intmask.val = - SDMMC_INTMASK_CD | - SDMMC_INTMASK_CMD_DONE | - SDMMC_INTMASK_DATA_OVER | - SDMMC_INTMASK_RCRC | SDMMC_INTMASK_DCRC | - SDMMC_INTMASK_RTO | SDMMC_INTMASK_DTO | SDMMC_INTMASK_HTO | - SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE | - SDMMC_INTMASK_RESP_ERR | SDMMC_INTMASK_HLE; //sdio is enabled only when use. + SDMMC_INTMASK_CD | + SDMMC_INTMASK_CMD_DONE | + SDMMC_INTMASK_DATA_OVER | + SDMMC_INTMASK_RCRC | SDMMC_INTMASK_DCRC | + SDMMC_INTMASK_RTO | SDMMC_INTMASK_DTO | SDMMC_INTMASK_HTO | + SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE | + SDMMC_INTMASK_RESP_ERR | SDMMC_INTMASK_HLE; //sdio is enabled only when use. SDMMC.ctrl.int_enable = 1; // Disable generation of Busy Clear Interrupt @@ -479,7 +477,7 @@ static void configure_pin_iomux(uint8_t gpio_num) static void configure_pin_gpio_matrix(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char *name) { - assert (gpio_num != (uint8_t) GPIO_NUM_NC); + assert(gpio_num != (uint8_t) GPIO_NUM_NC); ESP_LOGD(TAG, "using GPIO%d as %s pin", gpio_num, name); gpio_reset_pin(gpio_num); gpio_set_direction(gpio_num, mode); @@ -651,7 +649,7 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config) // As hardware expects an active-high signal, // if WP signal is active low, then invert it in GPIO matrix, // else keep it in its default state - esp_rom_gpio_connect_in_signal(matrix_in_wp, slot_info->write_protect, (gpio_wp_polarity? false : true)); + esp_rom_gpio_connect_in_signal(matrix_in_wp, slot_info->write_protect, (gpio_wp_polarity ? false : true)); // By default, set probing frequency (400kHz) and 1-bit bus esp_err_t ret = sdmmc_host_set_card_clk(slot, 400); @@ -733,7 +731,7 @@ esp_err_t sdmmc_host_set_bus_width(int slot, size_t width) size_t sdmmc_host_get_slot_width(int slot) { - assert( slot == 0 || slot == 1 ); + assert(slot == 0 || slot == 1); return s_host_ctx.slot_ctx[slot].slot_width; } diff --git a/components/driver/sdmmc/sdmmc_private.h b/components/esp_driver_sdmmc/src/sdmmc_private.h similarity index 100% rename from components/driver/sdmmc/sdmmc_private.h rename to components/esp_driver_sdmmc/src/sdmmc_private.h diff --git a/components/driver/sdmmc/sdmmc_transaction.c b/components/esp_driver_sdmmc/src/sdmmc_transaction.c similarity index 81% rename from components/driver/sdmmc/sdmmc_transaction.c rename to components/esp_driver_sdmmc/src/sdmmc_transaction.c index 1af3b864579..0ab95106174 100644 --- a/components/driver/sdmmc/sdmmc_transaction.c +++ b/components/esp_driver_sdmmc/src/sdmmc_transaction.c @@ -18,13 +18,11 @@ #include "driver/sdmmc_types.h" #include "driver/sdmmc_defs.h" #include "driver/sdmmc_host.h" -#include "esp_timer.h" #include "esp_cache.h" #include "esp_private/esp_cache_private.h" #include "sdmmc_private.h" #include "soc/soc_caps.h" - /* Number of DMA descriptors used for transfer. * Increasing this value above 4 doesn't improve performance for the usual case * of SD memory cards (most data transfers are multiples of 512 bytes). @@ -56,18 +54,18 @@ typedef struct { } sdmmc_transfer_state_t; const uint32_t SDMMC_DATA_ERR_MASK = - SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC | - SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE | - SDMMC_INTMASK_EBE; + SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC | + SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE | + SDMMC_INTMASK_EBE; const uint32_t SDMMC_DMA_DONE_MASK = - SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI | - SDMMC_IDMAC_INTMASK_NI; + SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI | + SDMMC_IDMAC_INTMASK_NI; const uint32_t SDMMC_CMD_ERR_MASK = - SDMMC_INTMASK_RTO | - SDMMC_INTMASK_RCRC | - SDMMC_INTMASK_RESP_ERR; + SDMMC_INTMASK_RTO | + SDMMC_INTMASK_RCRC | + SDMMC_INTMASK_RESP_ERR; SDMMC_ALIGN_ATTR static sdmmc_desc_t s_dma_desc[SDMMC_DMA_DESC_CNT]; static sdmmc_transfer_state_t s_cur_transfer = { 0 }; @@ -80,9 +78,9 @@ static esp_pm_lock_handle_t s_pm_lock; static esp_err_t handle_idle_state_events(void); static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd); static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state, - sdmmc_event_t* unhandled_events); + sdmmc_event_t* unhandled_events); static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd, - sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events); + sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events); static void process_command_response(uint32_t status, sdmmc_command_t* cmd); static void fill_dma_descriptors(size_t num_desc); static size_t get_free_descriptors_count(void); @@ -139,7 +137,7 @@ esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo) // Length should be either <4 or >=4 and =0 (mod 4). if (cmdinfo->datalen >= 4 && cmdinfo->datalen % 4 != 0) { ESP_LOGD(TAG, "%s: invalid size: total=%d", - __func__, cmdinfo->datalen); + __func__, cmdinfo->datalen); ret = ESP_ERR_INVALID_SIZE; goto out; } @@ -247,7 +245,7 @@ static void fill_dma_descriptors(size_t num_desc) assert(!desc->owned_by_idmac); size_t size_to_fill = (s_cur_transfer.size_remaining < SDMMC_DMA_MAX_BUF_LEN) ? - s_cur_transfer.size_remaining : SDMMC_DMA_MAX_BUF_LEN; + s_cur_transfer.size_remaining : SDMMC_DMA_MAX_BUF_LEN; bool last = size_to_fill == s_cur_transfer.size_remaining; desc->last_descriptor = last; desc->second_address_chained = 1; @@ -261,8 +259,8 @@ static void fill_dma_descriptors(size_t num_desc) s_cur_transfer.ptr += size_to_fill; s_cur_transfer.next_desc = (s_cur_transfer.next_desc + 1) % SDMMC_DMA_DESC_CNT; ESP_LOGV(TAG, "fill %d desc=%d rem=%d next=%d last=%d sz=%d", - num_desc, next, s_cur_transfer.size_remaining, - s_cur_transfer.next_desc, desc->last_descriptor, desc->buffer1_size); + num_desc, next, s_cur_transfer.size_remaining, + s_cur_transfer.next_desc, desc->last_descriptor, desc->buffer1_size); #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M); assert(ret == ESP_OK); @@ -284,16 +282,15 @@ static esp_err_t handle_idle_state_events(void) } if (evt.sdmmc_status != 0 || evt.dma_status != 0) { ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08"PRIx32" %08"PRIx32, - evt.sdmmc_status, evt.dma_status); + evt.sdmmc_status, evt.dma_status); } } return ESP_OK; } - static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state, - sdmmc_event_t* unhandled_events) + sdmmc_event_t* unhandled_events) { sdmmc_event_t event; esp_err_t err = sdmmc_host_wait_for_event(cmd->timeout_ms / portTICK_PERIOD_MS, &event); @@ -305,8 +302,8 @@ static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state, return err; } ESP_LOGV(TAG, "sdmmc_handle_event: event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32, - event.sdmmc_status, event.dma_status, - unhandled_events->sdmmc_status, unhandled_events->dma_status); + event.sdmmc_status, event.dma_status, + unhandled_events->sdmmc_status, unhandled_events->dma_status); event.sdmmc_status |= unhandled_events->sdmmc_status; event.dma_status |= unhandled_events->dma_status; process_events(event, cmd, state, unhandled_events); @@ -357,8 +354,8 @@ static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd) res.send_auto_stop = cmd_needs_auto_stop(cmd) ? 1 : 0; } ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d, auto_stop=%d", __func__, - res.cmd_index, res.response_expect, res.check_response_crc, - res.send_auto_stop); + res.cmd_index, res.response_expect, res.check_response_crc, + res.send_auto_stop); return res; } @@ -402,7 +399,7 @@ static void process_data_status(uint32_t status, sdmmc_command_t* cmd) } else if (status & SDMMC_INTMASK_DCRC) { cmd->error = ESP_ERR_INVALID_CRC; } else if ((status & SDMMC_INTMASK_EBE) && - (cmd->flags & SCF_CMD_READ) == 0) { + (cmd->flags & SCF_CMD_READ) == 0) { cmd->error = ESP_ERR_TIMEOUT; } else { cmd->error = ESP_FAIL; @@ -418,14 +415,15 @@ static void process_data_status(uint32_t status, sdmmc_command_t* cmd) } -static inline bool mask_check_and_clear(uint32_t* state, uint32_t mask) { +static inline bool mask_check_and_clear(uint32_t* state, uint32_t mask) +{ bool ret = ((*state) & mask) != 0; *state &= ~mask; return ret; } static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd, - sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events) + sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events) { const char* const s_state_names[] __attribute__((unused)) = { "IDLE", @@ -435,68 +433,67 @@ static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd, }; sdmmc_event_t orig_evt = evt; ESP_LOGV(TAG, "%s: state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, s_state_names[*pstate], - evt.sdmmc_status, evt.dma_status); + evt.sdmmc_status, evt.dma_status); sdmmc_req_state_t next_state = *pstate; sdmmc_req_state_t state = (sdmmc_req_state_t) -1; while (next_state != state) { state = next_state; switch (state) { - case SDMMC_IDLE: - break; - - case SDMMC_SENDING_CMD: - if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) { - process_command_response(orig_evt.sdmmc_status, cmd); - // In addition to the error interrupt, CMD_DONE will also be - // reported. It may occur immediately (in the same sdmmc_event_t) or - // be delayed until the next interrupt. - } - if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) { - process_command_response(orig_evt.sdmmc_status, cmd); - if (cmd->error != ESP_OK) { - next_state = SDMMC_IDLE; - break; - } - - if (cmd->data == NULL) { - next_state = SDMMC_IDLE; - } else { - next_state = SDMMC_SENDING_DATA; - } - } - break; - + case SDMMC_IDLE: + break; - case SDMMC_SENDING_DATA: - if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_DATA_ERR_MASK)) { - process_data_status(orig_evt.sdmmc_status, cmd); - sdmmc_host_dma_stop(); - } - if (mask_check_and_clear(&evt.dma_status, SDMMC_DMA_DONE_MASK)) { - s_cur_transfer.desc_remaining--; - if (s_cur_transfer.size_remaining) { - int desc_to_fill = get_free_descriptors_count(); - fill_dma_descriptors(desc_to_fill); - sdmmc_host_dma_resume(); - } - if (s_cur_transfer.desc_remaining == 0) { - next_state = SDMMC_BUSY; - } - } - if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) { - // On start bit error, DATA_DONE interrupt will not be generated + case SDMMC_SENDING_CMD: + if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) { + process_command_response(orig_evt.sdmmc_status, cmd); + // In addition to the error interrupt, CMD_DONE will also be + // reported. It may occur immediately (in the same sdmmc_event_t) or + // be delayed until the next interrupt. + } + if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) { + process_command_response(orig_evt.sdmmc_status, cmd); + if (cmd->error != ESP_OK) { next_state = SDMMC_IDLE; break; } - break; - case SDMMC_BUSY: - if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) { - break; + if (cmd->data == NULL) { + next_state = SDMMC_IDLE; + } else { + next_state = SDMMC_SENDING_DATA; } + } + break; + + case SDMMC_SENDING_DATA: + if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_DATA_ERR_MASK)) { process_data_status(orig_evt.sdmmc_status, cmd); + sdmmc_host_dma_stop(); + } + if (mask_check_and_clear(&evt.dma_status, SDMMC_DMA_DONE_MASK)) { + s_cur_transfer.desc_remaining--; + if (s_cur_transfer.size_remaining) { + int desc_to_fill = get_free_descriptors_count(); + fill_dma_descriptors(desc_to_fill); + sdmmc_host_dma_resume(); + } + if (s_cur_transfer.desc_remaining == 0) { + next_state = SDMMC_BUSY; + } + } + if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) { + // On start bit error, DATA_DONE interrupt will not be generated next_state = SDMMC_IDLE; break; + } + break; + + case SDMMC_BUSY: + if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) { + break; + } + process_data_status(orig_evt.sdmmc_status, cmd); + next_state = SDMMC_IDLE; + break; } ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]); } diff --git a/components/esp_driver_sdmmc/test_apps/.build-test-rules.yml b/components/esp_driver_sdmmc/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..7a4947815c7 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/.build-test-rules.yml @@ -0,0 +1,6 @@ +components/esp_driver_sdmmc/test_apps/sdmmc: + disable: + - if: SOC_SDMMC_HOST_SUPPORTED != 1 + depends_components: + - sdmmc + - esp_driver_sdmmc diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/CMakeLists.txt b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/CMakeLists.txt new file mode 100644 index 00000000000..649cb95a546 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/CMakeLists.txt @@ -0,0 +1,9 @@ +set(srcs "sdmmc_test_cd_wp_common.c" "sdmmc_test_rw_common.c" "sdmmc_test_erase_common_sd.c") + +set(public_include "include") + +idf_component_register( + SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES sdmmc unity test_utils +) diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_common.h b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_cd_wp_common.h similarity index 97% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_common.h rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_cd_wp_common.h index 0b8e248f3a2..f1f61a7657e 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_common.h +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_cd_wp_common.h @@ -5,7 +5,7 @@ */ #pragma once -#include "driver/sdmmc_types.h" +#include "sd_protocol_types.h" #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_erase_common_sd.h b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_erase_common_sd.h new file mode 100644 index 00000000000..572c9e1f893 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_erase_common_sd.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "driver/sdmmc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Test erase blocks performance of the card + * + * This function writes a buffer to the card, then erase all the buffers. + * The time taken for each operation is measured, and the throughput is calculated. + * The process is repeated for different buffer ranges. + * In this test, data is always written and then erase from the card + * + * This test function works both with SDMMC and SDSPI hosts. + * + * @param card Pointer to the card object, must be initialized before calling this function. + */ +void sdmmc_test_sd_erase_blocks(sdmmc_card_t* card); + +#ifdef __cplusplus +}; +#endif diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_common.h b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_rw_common.h similarity index 98% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_common.h rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_rw_common.h index 3ca55aeb12b..3398c79f02d 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_common.h +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/include/sdmmc_test_rw_common.h @@ -5,7 +5,7 @@ */ #pragma once -#include "driver/sdmmc_types.h" +#include "sd_protocol_types.h" #ifdef __cplusplus extern "C" { diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_common.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_cd_wp_common.c similarity index 99% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_common.c rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_cd_wp_common.c index 73ff1b5f888..3eb9ab984ae 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_common.c +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_cd_wp_common.c @@ -11,7 +11,6 @@ #include "sdmmc_cmd.h" #include "sdmmc_test_cd_wp_common.h" - void sdmmc_test_cd_input(int gpio_cd_num, const sdmmc_host_t* config) { sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_erase_common_sd.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_erase_common_sd.c new file mode 100644 index 00000000000..77ff8cc53ee --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_erase_common_sd.c @@ -0,0 +1,205 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "sdmmc_cmd.h" + +#define PATTERN_SEED 0x12345678 +#define FLAG_ERASE_TEST_ADJACENT (1 << 0) +#define FLAG_VERIFY_ERASE_STATE (1 << 1) + +#ifdef CONFIG_SOC_SDMMC_HOST_SUPPORTED +extern bool get_sanitize_flag(void); +#endif + +static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) +{ + srand(seed); + for (size_t i = 0; i < count; ++i) { + uint32_t val; + memcpy(&val, src + i * sizeof(uint32_t), sizeof(val)); + TEST_ASSERT_EQUAL_HEX32(rand(), val); + } +} + +static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) +{ + srand(seed); + for (size_t i = 0; i < count; ++i) { + uint32_t val = rand(); + memcpy(dst + i * sizeof(uint32_t), &val, sizeof(val)); + } +} + +static void ensure_sector_written(sdmmc_card_t* card, size_t sector, + uint8_t *pattern_buf, uint8_t *temp_buf) +{ + size_t block_size = card->csd.sector_size; + TEST_ESP_OK(sdmmc_write_sectors(card, pattern_buf, sector, 1)); + memset((void *)temp_buf, 0x00, block_size); + TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); + check_buffer(PATTERN_SEED, temp_buf, block_size / sizeof(uint32_t)); +} + +static void ensure_sector_intact(sdmmc_card_t* card, size_t sector, + uint8_t *pattern_buf, uint8_t *temp_buf) +{ + size_t block_size = card->csd.sector_size; + memset((void *)temp_buf, 0x00, block_size); + TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); + check_buffer(PATTERN_SEED, temp_buf, block_size / sizeof(uint32_t)); +} + +static int32_t ensure_sector_erase(sdmmc_card_t* card, size_t sector, + uint8_t *pattern_buf, uint8_t *temp_buf) +{ + size_t block_size = card->csd.sector_size; + memset((void *)temp_buf, 0, block_size); + TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); + return memcmp(pattern_buf, temp_buf, block_size); +} + +static void do_single_erase_test(sdmmc_card_t* card, size_t start_block, + size_t block_count, uint8_t flags, sdmmc_erase_arg_t arg) +{ + size_t block_size = card->csd.sector_size; + uint8_t *temp_buf = NULL; + uint8_t *pattern_buf = NULL; + size_t end_block = (start_block + block_count - 1); + + /* + * To ensure erase is successful/valid + * selected blocks after erase should have erase state data pattern + * data of blocks adjacent to selected region should remain intact + */ + TEST_ESP_OK((start_block + block_count) > card->csd.capacity); + + pattern_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(pattern_buf); + temp_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(temp_buf); + + // create pattern buffer + fill_buffer(PATTERN_SEED, pattern_buf, block_size / sizeof(uint32_t)); + + // check if it's not the first block of device & write/read/verify pattern + if ((flags & FLAG_ERASE_TEST_ADJACENT) && start_block) { + ensure_sector_written(card, (start_block - 1), pattern_buf, temp_buf); + } + + ensure_sector_written(card, start_block, pattern_buf, temp_buf); + + // check if it's not the last block of device & write/read/verify pattern + if ((flags & FLAG_ERASE_TEST_ADJACENT) && (end_block < (card->csd.capacity - 1))) { + ensure_sector_written(card, (end_block + 1), pattern_buf, temp_buf); + } + + // when block count is 1, start and end block is same, hence skip + if (block_count != 1) { + ensure_sector_written(card, end_block, pattern_buf, temp_buf); + } + + // fill pattern to (start_block + end_block)/2 in the erase range + if (block_count > 2) { + ensure_sector_written(card, (start_block + end_block) / 2, pattern_buf, temp_buf); + } + + float total_size = (block_count / 1024.0f) * block_size; + printf(" %10d | %10d | %8.1f ", start_block, block_count, total_size); + fflush(stdout); + + // erase the blocks + struct timeval t_start_er; + gettimeofday(&t_start_er, NULL); + TEST_ESP_OK(sdmmc_erase_sectors(card, start_block, block_count, arg)); +#ifdef CONFIG_SOC_SDMMC_HOST_SUPPORTED + if (get_sanitize_flag()) { + TEST_ESP_OK(sdmmc_mmc_sanitize(card, block_count * 500)); + } +#endif + struct timeval t_stop_wr; + gettimeofday(&t_stop_wr, NULL); + float time_er = 1e3f * (t_stop_wr.tv_sec - t_start_er.tv_sec) + 1e-3f * (t_stop_wr.tv_usec - t_start_er.tv_usec); + printf(" | %8.2f\n", time_er); + + // ensure adjacent blocks are not affected + // block before start_block + if ((flags & FLAG_ERASE_TEST_ADJACENT) && start_block) { + ensure_sector_intact(card, (start_block - 1), pattern_buf, temp_buf); + } + + // block after end_block + if ((flags & FLAG_ERASE_TEST_ADJACENT) && (end_block < (card->csd.capacity - 1))) { + ensure_sector_intact(card, (end_block + 1), pattern_buf, temp_buf); + } + + uint8_t erase_mem_byte = 0xFF; + // ensure all the blocks are erased and are up to after erase state. + if (!card->is_mmc) { + erase_mem_byte = card->scr.erase_mem_state ? 0xFF : 0x00; + } else { + erase_mem_byte = card->ext_csd.erase_mem_state ? 0xFF : 0x00; + } + + memset((void *)pattern_buf, erase_mem_byte, block_size); + + // as it is block by block comparison, a time taking process. Really long + // when you do erase and verify on complete device. + if (flags & FLAG_VERIFY_ERASE_STATE) { + for (size_t i = 0; i < block_count; i++) { + if (ensure_sector_erase(card, (start_block + i), pattern_buf, temp_buf)) { + printf("Error: Sector %d erase\n", (start_block + i)); + break; + } + } + } + + free(temp_buf); + free(pattern_buf); +} + +void sdmmc_test_sd_erase_blocks(sdmmc_card_t* card) +{ + printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); + printf(" sector | count | size(kB) | er_time(ms) \n"); + /* + * bit-0: verify adjacent blocks of given range + * bit-1: verify erase state of blocks in range + */ + uint8_t flags = 0; + sdmmc_erase_arg_t arg = SDMMC_ERASE_ARG; + + //check for adjacent blocks and erase state of blocks + flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT | (uint8_t)FLAG_VERIFY_ERASE_STATE; + do_single_erase_test(card, 1, 16, flags, arg); + do_single_erase_test(card, 1, 13, flags, arg); + do_single_erase_test(card, 16, 32, flags, arg); + do_single_erase_test(card, 48, 64, flags, arg); + do_single_erase_test(card, 128, 128, flags, arg); + do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); + do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); + // single sector erase is failing on different make cards + do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 1, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 4, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 8, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 16, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 32, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 64, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 128, flags, arg); +#ifdef SDMMC_FULL_ERASE_TEST + /* + * check for adjacent blocks, do not check erase state of blocks as it is + * time taking process to verify all the blocks. + */ + flags &= ~(uint8_t)FLAG_VERIFY_ERASE_STATE; //comment this line to verify after-erase state + // erase complete card + do_single_erase_test(card, 0, card->csd.capacity, flags, arg); +#endif //SDMMC_FULL_ERASE_TEST +} diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_common.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_rw_common.c similarity index 88% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_common.c rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_rw_common.c index 8bed8e394f0..625f9d0786d 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_common.c +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/common_test_flows/sdmmc_test_rw_common.c @@ -12,14 +12,15 @@ #include "sdkconfig.h" #include "soc/soc_caps.h" #include "unity.h" -#include "driver/sdmmc_defs.h" +#include "sd_protocol_defs.h" #include "sdmmc_cmd.h" #include "sdmmc_test_rw_common.h" static void do_single_rw_perf_test(sdmmc_card_t* card, size_t start_block, size_t block_count, size_t alignment, FILE* performance_log); -static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) { +static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) +{ srand(seed); for (size_t i = 0; i < count; ++i) { uint32_t val = rand(); @@ -29,7 +30,8 @@ static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) { // Check if the buffer pointed to by 'dst' contains 'count' 32-bit // ints generated from 'rand' with the starting value of 'seed' -static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) { +static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) +{ srand(seed); for (size_t i = 0; i < count; ++i) { uint32_t val; @@ -77,7 +79,7 @@ static void do_single_rw_perf_test(sdmmc_card_t* card, size_t start_block, stdout = performance_log; static const char wr_speed_str[] = "SDMMC_WR_SPEED"; static const char rd_speed_str[] = "SDMMC_RD_SPEED"; - int aligned = ((alignment % 4) == 0)? 1: 0; + int aligned = ((alignment % 4) == 0) ? 1 : 0; IDF_LOG_PERFORMANCE(wr_speed_str, "%d, blk_n: %d, aligned: %d", (int)(total_size * 1000 / time_wr), block_count, aligned); IDF_LOG_PERFORMANCE(rd_speed_str, "%d, blk_n: %d, aligned: %d", @@ -142,15 +144,15 @@ void sdmmc_test_rw_with_offset(sdmmc_card_t* card) do_single_rw_perf_test(card, card->csd.capacity - 64, 32, 4, NULL); do_single_rw_perf_test(card, card->csd.capacity - 64, 64, 4, NULL); do_single_rw_perf_test(card, card->csd.capacity - 8, 1, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 1, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 4, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 8, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 16, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 32, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 64, 4, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 128, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 1, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 4, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 8, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 16, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 32, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 64, 4, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 128, 4, NULL); /* unaligned */ - do_single_rw_perf_test(card, card->csd.capacity/2, 1, 1, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 8, 1, NULL); - do_single_rw_perf_test(card, card->csd.capacity/2, 128, 1, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 1, 1, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 8, 1, NULL); + do_single_rw_perf_test(card, card->csd.capacity / 2, 128, 1, NULL); } diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/CMakeLists.txt b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/CMakeLists.txt similarity index 58% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/CMakeLists.txt rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/CMakeLists.txt index 6d7fd32bbf2..8bed4b6fec1 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/CMakeLists.txt +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/CMakeLists.txt @@ -1,3 +1,3 @@ idf_component_register(SRCS sdmmc_test_board.c sdmmc_test_board_defs.c INCLUDE_DIRS include - PRIV_REQUIRES sdmmc driver) + REQUIRES esp_driver_sdmmc esp_driver_sdspi esp_driver_gpio) diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/Kconfig.projbuild b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/Kconfig.projbuild similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/Kconfig.projbuild rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/Kconfig.projbuild diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/README.md b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/README.md new file mode 100644 index 00000000000..192e7e6e476 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/README.md @@ -0,0 +1,8 @@ +# SDMMC Test Boards + +This component is a test utility component for test board info: +- SDMMC test boards (e.g. ESP32_WROVER_KIT, ESP32S3_USB_OTG, etc.) +- eMMC test boards +- SDMMC with SD breakout adapter board +- SDSPI with SD breakout adapter board +- ... diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/include/sdmmc_test_board.h b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h similarity index 99% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/include/sdmmc_test_board.h rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h index f7b8e227416..1417f36d82d 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/include/sdmmc_test_board.h +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h @@ -56,7 +56,6 @@ typedef struct { void (*card_power_set)(bool); /*< function to turn card power on or off */ } sdmmc_test_board_info_t; - /** * @brief Get information about the test board * @return Pointer to the board information structure @@ -92,7 +91,6 @@ void sdmmc_test_board_get_config_sdmmc(int slot_index, sdmmc_host_t *out_host_co void sdmmc_test_board_get_config_sdspi(int slot_index, sdmmc_host_t *out_host_config, spi_bus_config_t *out_spi_bus_config, sdspi_device_config_t *out_dev_config); - /** * @brief Set card power on or off * For boards with card power control circuit, this function allows powering the card up or down. diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/sdmmc_test_board.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c similarity index 99% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/sdmmc_test_board.c rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c index 0b9e20aed2b..01b85ffdcf1 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/sdmmc_test_board.c +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c @@ -8,7 +8,6 @@ #include "sdkconfig.h" #include "soc/soc_caps.h" - const sdmmc_test_board_slot_info_t* sdmmc_test_board_get_slot_info(int slot_index) { assert(slot_index >= 0 && slot_index < SDMMC_TEST_BOARD_MAX_SLOTS); diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/sdmmc_test_board_defs.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c similarity index 99% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/sdmmc_test_board_defs.c rename to components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c index bb76aed3d03..2610e1a78bc 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_test_board/sdmmc_test_board_defs.c +++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c @@ -385,7 +385,6 @@ static const sdmmc_test_board_info_t s_board_info = { #endif // CONFIG_SDMMC_BOARD_* - const sdmmc_test_board_info_t* sdmmc_test_board_get_info(void) { return &s_board_info; diff --git a/components/sdmmc/test_apps/sdmmc_console/CMakeLists.txt b/components/esp_driver_sdmmc/test_apps/sdmmc/CMakeLists.txt similarity index 65% rename from components/sdmmc/test_apps/sdmmc_console/CMakeLists.txt rename to components/esp_driver_sdmmc/test_apps/sdmmc/CMakeLists.txt index cde7ad6b49b..937ae28ab76 100644 --- a/components/sdmmc/test_apps/sdmmc_console/CMakeLists.txt +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/CMakeLists.txt @@ -1,7 +1,7 @@ cmake_minimum_required(VERSION 3.16) -list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/examples/system/console/advanced/components") list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/components/esp_driver_sdmmc/test_apps/sd_test_utils/components") set(COMPONENTS main) include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/README.md b/components/esp_driver_sdmmc/test_apps/sdmmc/README.md new file mode 100644 index 00000000000..7fb40f3f87b --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt new file mode 100644 index 00000000000..599b9ffba34 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt @@ -0,0 +1,24 @@ +set(srcs) + + +if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) + list(APPEND srcs "sdmmc_test_begin_end_sd.c" + "sdmmc_test_cd_wp_sd.c" + "sdmmc_test_probe_sd.c" + "sdmmc_test_rw_sd.c" + "sdmmc_test_erase_sd.c" + "sdmmc_test_trim_sd.c" + "sdmmc_test_discard_sd.c" + "sdmmc_test_sanitize_sd.c") +endif() + +set(priv_requires "sdmmc" + "esp_driver_sdmmc" + "sdmmc_test_boards" + "common_test_flows" + "unity" +) + +idf_component_register(SRCS ${srcs} + PRIV_REQUIRES ${priv_requires} + WHOLE_ARCHIVE TRUE) diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c similarity index 89% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end_sd.c rename to components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c index f67be4ead6d..a5aaa269943 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end_sd.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c @@ -11,9 +11,9 @@ #include "unity.h" #include "sdmmc_test_board.h" #include "driver/sdmmc_host.h" -#include "driver/sdmmc_defs.h" +#include "sd_protocol_defs.h" #include "sdmmc_cmd.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_sd.h" #include "hal/gpio_hal.h" void sdmmc_test_sd_skip_if_board_incompatible(int slot, int width, int freq_khz, int ddr) @@ -33,7 +33,8 @@ void sdmmc_test_sd_skip_if_board_incompatible(int slot, int width, int freq_khz, TEST_IGNORE_MESSAGE("Board doesn't support required bus width"); } } -void sdmmc_test_sd_begin(int slot, int width, int freq_khz, int ddr, sdmmc_card_t *out_card) { +void sdmmc_test_sd_begin(int slot, int width, int freq_khz, int ddr, sdmmc_card_t *out_card) +{ sdmmc_host_t config = SDMMC_HOST_DEFAULT(); sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); @@ -87,18 +88,18 @@ void sdmmc_test_sd_end(sdmmc_card_t *card) int slot = card->host.slot; const sdmmc_test_board_slot_info_t *slot_info = sdmmc_test_board_get_slot_info(slot); const int pins[] = { - slot_info->clk, - slot_info->cmd_mosi, - slot_info->d0_miso, - slot_info->d1, - slot_info->d2, - slot_info->d3_cs, - slot_info->d4, - slot_info->d5, - slot_info->d6, - slot_info->d7, - slot_info->cd, - slot_info->wp, + slot_info->clk, + slot_info->cmd_mosi, + slot_info->d0_miso, + slot_info->d1, + slot_info->d2, + slot_info->d3_cs, + slot_info->d4, + slot_info->d5, + slot_info->d6, + slot_info->d7, + slot_info->cd, + slot_info->wp, }; const int num_pins = sizeof(pins) / sizeof(pins[0]); // Silence logging in gpio_reset_pin, which logs at INFO level diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end.h b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.h similarity index 71% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end.h rename to components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.h index da5126b6c3c..11207811855 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end.h +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.h @@ -5,7 +5,7 @@ */ #pragma once -#include "driver/sdmmc_types.h" +#include "sd_protocol_types.h" #ifdef __cplusplus extern "C" { @@ -19,7 +19,6 @@ extern "C" { /* Helper functions to initialize/deinintalize the host (SDMMC/SDSPI) inside the test */ - #if SOC_SDMMC_HOST_SUPPORTED /** * @brief Skip the test if the board is incompatible with the given slot, width, frequency and DDR mode @@ -49,25 +48,6 @@ void sdmmc_test_sd_begin(int slot, int width, int freq_khz, int ddr, sdmmc_card_ void sdmmc_test_sd_end(sdmmc_card_t *card); #endif -/** - * @brief Skip the test if the board is incompatible with the given slot and frequency, for SPI mode. - * @see sdmmc_test_sd_skip_if_board_incompatible - */ -void sdmmc_test_spi_skip_if_board_incompatible(int slot, int freq_khz); - -/** - * @brief Helper function to initialize the SDMMC host and slot for the test using the given settings, for SPI mode - * @see sdmmc_test_sd_begin - */ -void sdmmc_test_spi_begin(int slot, int freq_khz, sdmmc_card_t *out_card); - -/** - * @brief Helper function to deinitialize the SDMMC host and slot after the test, for SPI mode - * @see sdmmc_test_sd_end - */ -void sdmmc_test_spi_end(int slot, sdmmc_card_t *card); - - #ifdef __cplusplus }; #endif diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_cd_wp_sd.c similarity index 95% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_sd.c rename to components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_cd_wp_sd.c index 6ba204cb67e..2db5ffe9218 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_sd.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_cd_wp_sd.c @@ -10,6 +10,8 @@ #include "sdmmc_test_cd_wp_common.h" #include "sdmmc_test_board.h" +//TODO: IDF-8734 +#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3 TEST_CASE("CD input works in SD mode", "[sdmmc]") { sdmmc_host_t config = SDMMC_HOST_DEFAULT(); @@ -43,3 +45,4 @@ TEST_CASE("WP input works in SD mode", "[sdmmc]") TEST_ESP_OK(sdmmc_host_deinit()); sdmmc_test_board_card_power_set(false); } +#endif diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_discard_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_discard_sd.c new file mode 100644 index 00000000000..b0211b73d91 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_discard_sd.c @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "driver/sdmmc_defs.h" +#include "sdmmc_cmd.h" +#include "sdmmc_test_begin_end_sd.h" +#include "sdmmc_test_erase_common_sd.h" + +static void test_discard_blocks(sdmmc_card_t* card, int slot) +{ + /* MMC discard applies to write blocks */ + sdmmc_erase_arg_t arg = SDMMC_DISCARD_ARG; + if (slot == SLOT_0) { + uint32_t prev_ext_csd = card->ext_csd.rev; + // overwrite discard_support as not-supported for -ve test + card->ext_csd.rev = 0; + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, 0, 32, arg)); + // restore discard_support + card->ext_csd.rev = prev_ext_csd; + } else { + uint32_t prev_discard_support = card->ssr.discard_support; + // overwrite discard_support as not-supported for -ve test + card->ssr.discard_support = 0; + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, 0, 32, arg)); + // restore discard_support + card->ssr.discard_support = prev_discard_support; + } + + if (sdmmc_can_discard(card) != ESP_OK) { + printf("Card/device do not support discard\n"); + return; + } + sdmmc_test_sd_erase_blocks(card); +} + +static void do_one_mmc_discard_test(int slot, int width, int freq_khz, int ddr) +{ + sdmmc_card_t card; + sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr); + sdmmc_test_sd_begin(slot, width, freq_khz, ddr, &card); + sdmmc_card_print_info(stdout, &card); + test_discard_blocks(&card, slot); + sdmmc_test_sd_end(&card); +} + +TEST_CASE("sdmmc discard, slot 0, 4-bit", "[sdmmc]") +{ + do_one_mmc_discard_test(SLOT_0, 4, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} + +TEST_CASE("sdmmc discard, slot 0, 8-bit", "[sdmmc]") +{ + do_one_mmc_discard_test(SLOT_0, 8, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} + +TEST_CASE("sdmmc discard, slot 1, 4-bit", "[sdmmc]") +{ + do_one_mmc_discard_test(SLOT_1, 4, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_erase_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_erase_sd.c new file mode 100644 index 00000000000..9212c61a8ce --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_erase_sd.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "sdmmc_cmd.h" +#include "sdmmc_test_begin_end_sd.h" +#include "sdmmc_test_erase_common_sd.h" + +static void do_one_sdmmc_erase_test(int slot, int width, int freq_khz, int ddr) +{ + sdmmc_card_t card; + sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr); + sdmmc_test_sd_begin(slot, width, freq_khz, ddr, &card); + sdmmc_card_print_info(stdout, &card); + sdmmc_test_sd_erase_blocks(&card); + sdmmc_test_sd_end(&card); +} + +TEST_CASE("sdmmc erase, slot 1, 1-bit", "[sdmmc]") +{ + do_one_sdmmc_erase_test(SLOT_1, 1, SDMMC_FREQ_PROBING, NO_DDR); + do_one_sdmmc_erase_test(SLOT_1, 1, SDMMC_FREQ_DEFAULT, NO_DDR); + do_one_sdmmc_erase_test(SLOT_1, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} + +TEST_CASE("sdmmc erase, slot 1, 4-bit", "[sdmmc]") +{ + do_one_sdmmc_erase_test(SLOT_1, 4, SDMMC_FREQ_PROBING, NO_DDR); + do_one_sdmmc_erase_test(SLOT_1, 4, SDMMC_FREQ_DEFAULT, NO_DDR); + do_one_sdmmc_erase_test(SLOT_1, 4, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_probe_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_probe_sd.c similarity index 93% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_probe_sd.c rename to components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_probe_sd.c index 2984b8401dc..ce4ab53fc42 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_probe_sd.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_probe_sd.c @@ -6,7 +6,9 @@ #include #include "unity.h" #include "sdmmc_cmd.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_sd.h" + +#define SDMMC_FREQ_CUSTOM_10M 10000 static void do_one_sdmmc_probe_test(int slot, int width, int freq_khz, int ddr) { @@ -58,6 +60,7 @@ TEST_CASE("sdmmc probe, slot 1, 4-bit", "[sdmmc]") do_one_sdmmc_probe_test(SLOT_1, 4, SDMMC_FREQ_PROBING, NO_DDR); do_one_sdmmc_probe_test(SLOT_1, 4, SDMMC_FREQ_DEFAULT, NO_DDR); do_one_sdmmc_probe_test(SLOT_1, 4, SDMMC_FREQ_HIGHSPEED, NO_DDR); + do_one_sdmmc_probe_test(SLOT_1, 4, SDMMC_FREQ_CUSTOM_10M, NO_DDR); } TEST_CASE("sdmmc probe, slot 1, 4-bit DDR", "[sdmmc]") diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_rw_sd.c similarity index 98% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_sd.c rename to components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_rw_sd.c index 9ed0c245eff..b8740ff533e 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_sd.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_rw_sd.c @@ -7,7 +7,7 @@ #include #include "unity.h" #include "sdmmc_cmd.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_sd.h" #include "sdmmc_test_rw_common.h" /* ========== Read/write performance tests, SD ========== */ diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_sanitize_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_sanitize_sd.c new file mode 100644 index 00000000000..4fc434fbb5e --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_sanitize_sd.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "driver/sdmmc_defs.h" +#include "sdmmc_cmd.h" +#include "sdmmc_test_begin_end_sd.h" +#include "sdmmc_test_erase_common_sd.h" + +static bool do_sanitize_flag; + +bool get_sanitize_flag(void) +{ + return do_sanitize_flag; +} + +static void test_mmc_sanitize_blocks(sdmmc_card_t* card) +{ + /* MMC trim applies to write blocks */ + if (sdmmc_mmc_can_sanitize(card) != ESP_OK) { + printf("Card/device do not support sanitize\n"); + return; + } + do_sanitize_flag = true; + sdmmc_test_sd_erase_blocks(card); + do_sanitize_flag = false; +} + +static void do_one_mmc_sanitize_test(int slot, int width, int freq_khz, int ddr) +{ + sdmmc_card_t card; + sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr); + sdmmc_test_sd_begin(slot, width, freq_khz, ddr, &card); + sdmmc_card_print_info(stdout, &card); + test_mmc_sanitize_blocks(&card); + sdmmc_test_sd_end(&card); +} + +TEST_CASE("sdmmc sanitize, slot 0, 4-bit", "[sdmmc]") +{ + do_one_mmc_sanitize_test(SLOT_0, 4, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} + +TEST_CASE("sdmmc sanitize, slot 0, 8-bit", "[sdmmc]") +{ + do_one_mmc_sanitize_test(SLOT_0, 8, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_trim_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_trim_sd.c new file mode 100644 index 00000000000..8f277b80669 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_trim_sd.c @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "driver/sdmmc_defs.h" +#include "sdmmc_cmd.h" +#include "sdmmc_test_begin_end_sd.h" +#include "sdmmc_test_erase_common_sd.h" + +static void test_mmc_trim_blocks(sdmmc_card_t* card) +{ + /* MMC trim applies to write blocks */ + sdmmc_erase_arg_t arg = SDMMC_ERASE_ARG; + uint8_t prev_sec_feature = card->ext_csd.sec_feature; + // overwrite sec_feature + card->ext_csd.sec_feature &= ~(EXT_CSD_SEC_GB_CL_EN); + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, 0, 32, arg)); + // restore sec_feature + card->ext_csd.sec_feature = prev_sec_feature; + if (sdmmc_can_trim(card) != ESP_OK) { + printf("Card/device do not support trim\n"); + return; + } + sdmmc_test_sd_erase_blocks(card); +} + +static void do_one_mmc_trim_test(int slot, int width, int freq_khz, int ddr) +{ + sdmmc_card_t card; + sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr); + sdmmc_test_sd_begin(slot, width, freq_khz, ddr, &card); + sdmmc_card_print_info(stdout, &card); + test_mmc_trim_blocks(&card); + sdmmc_test_sd_end(&card); +} + +TEST_CASE("sdmmc trim, slot 0, 4-bit", "[sdmmc]") +{ + do_one_mmc_trim_test(SLOT_0, 4, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} + +TEST_CASE("sdmmc trim, slot 0, 8-bit", "[sdmmc]") +{ + do_one_mmc_trim_test(SLOT_0, 8, SDMMC_FREQ_HIGHSPEED, NO_DDR); +} diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/main/CMakeLists.txt b/components/esp_driver_sdmmc/test_apps/sdmmc/main/CMakeLists.txt new file mode 100644 index 00000000000..03cd59aaedb --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/main/CMakeLists.txt @@ -0,0 +1,13 @@ +set(srcs "test_app_main.c") + +set(priv_requires + # tests reside in this component, also available for `sdmmc_console` + sdmmc_tests + # general + unity +) + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS "." + PRIV_REQUIRES ${priv_requires} + WHOLE_ARCHIVE TRUE) diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c b/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c new file mode 100644 index 00000000000..e6e17ee73ee --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + */ + +#include "unity.h" +#include "unity_test_utils.h" +#include "esp_heap_caps.h" +#include "sdkconfig.h" + +#define TEST_MEMORY_LEAK_THRESHOLD (300) + +void setUp(void) +{ + unity_utils_record_free_mem(); +} + +void tearDown(void) +{ + unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD); +} + +void app_main(void) +{ + /* + _____ _ ______________ ______ ________ + |_ _| | | / ___| _ \ \/ || \/ / __ \ + | | ___ ___| |_ \ `--.| | | | . . || . . | / \/ + | |/ _ \/ __| __| `--. \ | | | |\/| || |\/| | | + | | __/\__ \ |_ /\__/ / |/ /| | | || | | | \__/\ + \_/\___||___/\__| \____/|___/ \_| |_/\_| |_/\____/ + */ + + printf(" _____ _ ______________ ______ ________\n"); + printf("|_ _| | | / ___| _ \\ \\/ || \\/ / __ \\ \n"); + printf(" | | ___ ___| |_ \\ `--.| | | | . . || . . | / \\/\n"); + printf(" | |/ _ \\/ __| __| `--. \\ | | | |\\/| || |\\/| | |\n"); + printf(" | | __/\\__ \\ |_ /\\__/ / |/ /| | | || | | | \\__/\\\n"); + printf(" \\_/\\___||___/\\__| \\____/|___/ \\_| |_/\\_| |_/\\____/\n"); + + unity_run_menu(); +} diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/pytest_sdmmc.py b/components/esp_driver_sdmmc/test_apps/sdmmc/pytest_sdmmc.py new file mode 100644 index 00000000000..6d4e712930a --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/pytest_sdmmc.py @@ -0,0 +1,12 @@ +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded_idf import IdfDut + + +@pytest.mark.esp32 +@pytest.mark.esp32s3 +@pytest.mark.sdcard +def test_sdmmc(dut: IdfDut) -> None: + dut.run_all_single_board_cases() diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/sdkconfig.defaults b/components/esp_driver_sdmmc/test_apps/sdmmc/sdkconfig.defaults new file mode 100644 index 00000000000..fa8ac618b94 --- /dev/null +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT_EN=n diff --git a/components/esp_driver_sdspi/CMakeLists.txt b/components/esp_driver_sdspi/CMakeLists.txt new file mode 100644 index 00000000000..41809a1e0d4 --- /dev/null +++ b/components/esp_driver_sdspi/CMakeLists.txt @@ -0,0 +1,15 @@ +set(srcs) + +set(public_include "include") + +if(CONFIG_SOC_GPSPI_SUPPORTED) + list(APPEND srcs "src/sdspi_crc.c" + "src/sdspi_host.c" + "src/sdspi_transaction.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + REQUIRES sdmmc esp_driver_spi esp_driver_gpio + PRIV_REQUIRES esp_timer + ) diff --git a/components/esp_driver_sdspi/README.md b/components/esp_driver_sdspi/README.md new file mode 100644 index 00000000000..fb85c7efd16 --- /dev/null +++ b/components/esp_driver_sdspi/README.md @@ -0,0 +1,19 @@ +# SDSPI Host Driver + +SD Host side related components are: +- `sdmmc` +- `esp_driver_sdmmc` +- `esp_driver_sdspi` (current component) + +For relationship and dependency among these components, see [SD Host Side Related Component Architecture](../sdmmc/README.md). + +`esp_driver_sdspi` components is a driver based on ESP GPSPI master driver to help you: +- do SD transactions (under SDSPI mode) via ESP GPSPI peripheral. +- tune ESP GPSPI hardware configurations, such as clock frequency, bus width, etc. +- ... + +You can +- use this driver to implement `sdmmc` protocol interfaces +- directly use `esp_driver_sdspi` APIs + +to communicate with SD slave devices under SDSPI mode. diff --git a/components/driver/spi/include/driver/sdspi_host.h b/components/esp_driver_sdspi/include/driver/sdspi_host.h similarity index 94% rename from components/driver/spi/include/driver/sdspi_host.h rename to components/esp_driver_sdspi/include/driver/sdspi_host.h index 04c0258e0d8..a8a793e17e3 100644 --- a/components/driver/spi/include/driver/sdspi_host.h +++ b/components/esp_driver_sdspi/include/driver/sdspi_host.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include #include "esp_err.h" -#include "driver/sdmmc_types.h" +#include "sd_protocol_types.h" #include "driver/gpio.h" #include "driver/spi_master.h" @@ -65,9 +65,9 @@ typedef struct { gpio_num_t gpio_cd; ///< GPIO number of card detect signal gpio_num_t gpio_wp; ///< GPIO number of write protect signal gpio_num_t gpio_int; ///< GPIO number of interrupt line (input) for SDIO card. - bool gpio_wp_polarity; ///< GPIO write protect polarity - /// 0 means "active low", i.e. card is protected when the GPIO is low; - /// 1 means "active high", i.e. card is protected when GPIO is high. + bool gpio_wp_polarity; /*!< GPIO write protect polarity + 0 means "active low", i.e. card is protected when the GPIO is low; + 1 means "active high", i.e. card is protected when GPIO is high. */ } sdspi_device_config_t; #define SDSPI_SLOT_NO_CS GPIO_NUM_NC ///< indicates that card select line is not used diff --git a/components/esp_driver_sdspi/src/sdspi_crc.c b/components/esp_driver_sdspi/src/sdspi_crc.c new file mode 100644 index 00000000000..b4309077d0a --- /dev/null +++ b/components/esp_driver_sdspi/src/sdspi_crc.c @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdspi_crc.h" +#include "sdkconfig.h" +#include "esp_rom_crc.h" + +static const uint8_t crc7_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, + 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, + 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, + 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, + 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, + 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, + 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, + 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79, +}; + +// returns the CRC-7 for a message of "length" bytes +uint8_t sdspi_crc7(const uint8_t *data, size_t size) +{ + uint8_t result = 0; + for (size_t i = 0; i < size; ++i) { + result = crc7_table[(result << 1) ^ data[i]]; + } + return result; +} + +/// Return CRC16 of data, in the on-the-wire format used by SD protocol +uint16_t sdspi_crc16(const uint8_t* data, size_t size) +{ + return __builtin_bswap16(esp_rom_crc16_be(UINT16_MAX, data, size) ^ UINT16_MAX); +} diff --git a/components/driver/spi/sdspi/sdspi_crc.h b/components/esp_driver_sdspi/src/sdspi_crc.h similarity index 99% rename from components/driver/spi/sdspi/sdspi_crc.h rename to components/esp_driver_sdspi/src/sdspi_crc.h index d130764db15..b4a95108a30 100644 --- a/components/driver/spi/sdspi/sdspi_crc.h +++ b/components/esp_driver_sdspi/src/sdspi_crc.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Return CRC7 of data, in the format used by SD protocol * @param data array of data used to compute CRC @@ -29,7 +28,6 @@ uint8_t sdspi_crc7(const uint8_t *data, size_t size); */ uint16_t sdspi_crc16(const uint8_t* data, size_t size); - #ifdef __cplusplus } #endif diff --git a/components/driver/spi/sdspi/sdspi_host.c b/components/esp_driver_sdspi/src/sdspi_host.c similarity index 95% rename from components/driver/spi/sdspi/sdspi_host.c rename to components/esp_driver_sdspi/src/sdspi_host.c index 9fb87753a29..7877c3133f6 100644 --- a/components/driver/spi/sdspi/sdspi_host.c +++ b/components/esp_driver_sdspi/src/sdspi_host.c @@ -13,7 +13,7 @@ #include "esp_log.h" #include "esp_heap_caps.h" #include "driver/gpio.h" -#include "driver/sdmmc_defs.h" +#include "sd_protocol_defs.h" #include "driver/sdspi_host.h" #include "sdspi_private.h" #include "sdspi_crc.h" @@ -22,7 +22,6 @@ #include "freertos/semphr.h" #include "soc/soc_memory_layout.h" - /// Max number of transactions in flight (used in start_command_write_blocks) #define SDSPI_TRANSACTION_COUNT 4 #define SDSPI_MOSI_IDLE_VAL 0xff //!< Data value which causes MOSI to stay high @@ -67,13 +66,12 @@ static const char *TAG = "sdspi_host"; static const bool use_polling = true; static const bool no_use_polling = true; - /// Functions to send out different kinds of commands static esp_err_t start_command_read_blocks(slot_info_t *slot, sdspi_hw_cmd_t *cmd, - uint8_t *data, uint32_t rx_length, bool need_stop_command); + uint8_t *data, uint32_t rx_length, bool need_stop_command); static esp_err_t start_command_write_blocks(slot_info_t *slot, sdspi_hw_cmd_t *cmd, - const uint8_t *data, uint32_t tx_length, bool multi_block, bool stop_trans); + const uint8_t *data, uint32_t tx_length, bool multi_block, bool stop_trans); static esp_err_t start_command_default(slot_info_t *slot, int flags, sdspi_hw_cmd_t *cmd); @@ -189,7 +187,7 @@ static void go_idle_clockout(slot_info_t *slot) uint8_t data[12]; memset(data, 0xff, sizeof(data)); spi_transaction_t t = { - .length = 10*8, + .length = 10 * 8, .tx_buffer = data, .rx_buffer = data, }; @@ -276,17 +274,19 @@ esp_err_t sdspi_host_remove_device(sdspi_dev_handle_t handle) return ESP_ERR_INVALID_ARG; } - deinit_slot(slot); + deinit_slot(slot); return ESP_OK; } //only the slots locally stored can be deinit in this function. esp_err_t sdspi_host_deinit(void) { - for (size_t i = 0; i < sizeof(s_slots)/sizeof(s_slots[0]); ++i) { + for (size_t i = 0; i < sizeof(s_slots) / sizeof(s_slots[0]); ++i) { slot_info_t* slot = remove_slot_info(i); //slot isn't used, skip - if (slot == NULL) continue; + if (slot == NULL) { + continue; + } deinit_slot(slot); } @@ -514,8 +514,8 @@ static esp_err_t start_command_default(slot_info_t *slot, int flags, sdspi_hw_cm { size_t cmd_size = SDSPI_CMD_R1_SIZE; if ((flags & SDSPI_CMD_FLAG_RSP_R1) || - (flags & SDSPI_CMD_FLAG_NORSP) || - (flags & SDSPI_CMD_FLAG_RSP_R1B )) { + (flags & SDSPI_CMD_FLAG_NORSP) || + (flags & SDSPI_CMD_FLAG_RSP_R1B)) { cmd_size = SDSPI_CMD_R1_SIZE; } else if (flags & SDSPI_CMD_FLAG_RSP_R2) { cmd_size = SDSPI_CMD_R2_SIZE; @@ -529,7 +529,7 @@ static esp_err_t start_command_default(slot_info_t *slot, int flags, sdspi_hw_cm cmd_size = SDSPI_CMD_R7_SIZE; } //add extra clocks to avoid polling - cmd_size += (SDSPI_NCR_MAX_SIZE-SDSPI_NCR_MIN_SIZE); + cmd_size += (SDSPI_NCR_MAX_SIZE - SDSPI_NCR_MIN_SIZE); spi_transaction_t t = { .flags = 0, .length = cmd_size * 8, @@ -553,7 +553,9 @@ static esp_err_t start_command_default(slot_info_t *slot, int flags, sdspi_hw_cm // we have sent and received bytes with enough length. // now shift the response to match the offset of sdspi_hw_cmd_t ret = shift_cmd_response(cmd, cmd_size); - if (ret != ESP_OK) return ESP_ERR_TIMEOUT; + if (ret != ESP_OK) { + return ESP_ERR_TIMEOUT; + } if (flags & SDSPI_CMD_FLAG_RSP_R1B) { ret = poll_busy(slot, cmd->timeout_ms, no_use_polling); @@ -594,7 +596,7 @@ static esp_err_t poll_busy(slot_info_t *slot, int timeout_ms, bool polling) return ESP_OK; } } - } while(esp_timer_get_time() < t_end); + } while (esp_timer_get_time() < t_end); ESP_LOGD(TAG, "%s: timeout", __func__); return ESP_ERR_TIMEOUT; } @@ -629,7 +631,7 @@ static esp_err_t poll_data_token(slot_info_t *slot, uint8_t *extra_ptr, size_t * } if (rd_data != 0xff && rd_data != 0) { ESP_LOGD(TAG, "%s: received 0x%02x while waiting for data", - __func__, rd_data); + __func__, rd_data); return ESP_ERR_INVALID_RESPONSE; } } @@ -648,10 +650,14 @@ static esp_err_t shift_cmd_response(sdspi_hw_cmd_t* cmd, int sent_bytes) { uint8_t* pr1 = &cmd->r1; int ncr_cnt = 1; - while(true) { - if ((*pr1 & SD_SPI_R1_NO_RESPONSE) == 0) break; + while (true) { + if ((*pr1 & SD_SPI_R1_NO_RESPONSE) == 0) { + break; + } pr1++; - if (++ncr_cnt > 8) return ESP_ERR_NOT_FOUND; + if (++ncr_cnt > 8) { + return ESP_ERR_NOT_FOUND; + } } int copy_bytes = sent_bytes - SDSPI_CMD_SIZE - ncr_cnt; @@ -662,7 +668,6 @@ static esp_err_t shift_cmd_response(sdspi_hw_cmd_t* cmd, int sent_bytes) return ESP_OK; } - /** * Receiving one or more blocks of data happens as follows: * 1. send command + receive r1 response (SDSPI_CMD_R1_SIZE bytes total) @@ -705,7 +710,7 @@ static esp_err_t shift_cmd_response(sdspi_hw_cmd_t* cmd, int sent_bytes) * expense of one extra temporary buffer. */ static esp_err_t start_command_read_blocks(slot_info_t *slot, sdspi_hw_cmd_t *cmd, - uint8_t *data, uint32_t rx_length, bool need_stop_command) + uint8_t *data, uint32_t rx_length, bool need_stop_command) { spi_transaction_t t_command = { .length = (SDSPI_CMD_R1_SIZE + SDSPI_RESPONSE_MAX_DELAY) * 8, @@ -838,7 +843,7 @@ static esp_err_t start_command_read_blocks(slot_info_t *slot, sdspi_hw_cmd_t *cm * It's also different that stop transmission token is not needed in the SDIO mode. */ static esp_err_t start_command_write_blocks(slot_info_t *slot, sdspi_hw_cmd_t *cmd, - const uint8_t *data, uint32_t tx_length, bool multi_block, bool stop_trans) + const uint8_t *data, uint32_t tx_length, bool multi_block, bool stop_trans) { if (card_write_protected(slot)) { ESP_LOGW(TAG, "%s: card write protected", __func__); @@ -846,7 +851,7 @@ static esp_err_t start_command_write_blocks(slot_info_t *slot, sdspi_hw_cmd_t *c } // Send the minimum length that is sure to get the complete response // SD cards always return R1 (1bytes), SDIO returns R5 (2 bytes) - const int send_bytes = SDSPI_CMD_R5_SIZE+SDSPI_NCR_MAX_SIZE-SDSPI_NCR_MIN_SIZE; + const int send_bytes = SDSPI_CMD_R5_SIZE + SDSPI_NCR_MAX_SIZE - SDSPI_NCR_MIN_SIZE; spi_transaction_t t_command = { .length = send_bytes * 8, @@ -866,7 +871,7 @@ static esp_err_t start_command_write_blocks(slot_info_t *slot, sdspi_hw_cmd_t *c } uint8_t start_token = multi_block ? - TOKEN_BLOCK_START_WRITE_MULTI : TOKEN_BLOCK_START; + TOKEN_BLOCK_START_WRITE_MULTI : TOKEN_BLOCK_START; while (tx_length > 0) { // Write block start token @@ -909,7 +914,7 @@ static esp_err_t start_command_write_blocks(slot_info_t *slot, sdspi_hw_cmd_t *c spi_transaction_t t_crc_rsp = { .length = size_crc_response * 8, - .flags = SPI_TRANS_USE_TXDATA|SPI_TRANS_USE_RXDATA, + .flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA, }; memset(t_crc_rsp.tx_data, 0xff, 4); memcpy(t_crc_rsp.tx_data, &crc, sizeof(crc)); @@ -920,7 +925,9 @@ static esp_err_t start_command_write_blocks(slot_info_t *slot, sdspi_hw_cmd_t *c } uint8_t data_rsp = t_crc_rsp.rx_data[2]; - if (!SD_SPI_DATA_RSP_VALID(data_rsp)) return ESP_ERR_INVALID_RESPONSE; + if (!SD_SPI_DATA_RSP_VALID(data_rsp)) { + return ESP_ERR_INVALID_RESPONSE; + } switch (SD_SPI_DATA_RSP(data_rsp)) { case SD_SPI_DATA_ACCEPTED: break; @@ -976,7 +983,9 @@ esp_err_t sdspi_host_io_int_wait(sdspi_dev_handle_t handle, TickType_t timeout_t { slot_info_t* slot = get_slot_info(handle); //skip the interrupt and semaphore if the gpio is already low. - if (gpio_get_level(slot->gpio_int)==0) return ESP_OK; + if (gpio_get_level(slot->gpio_int) == 0) { + return ESP_OK; + } //clear the semaphore before wait xSemaphoreTake(slot->semphr_int, 0); diff --git a/components/driver/spi/sdspi/sdspi_private.h b/components/esp_driver_sdspi/src/sdspi_private.h similarity index 99% rename from components/driver/spi/sdspi/sdspi_private.h rename to components/esp_driver_sdspi/src/sdspi_private.h index e78756b4c2c..ab9ddc43217 100644 --- a/components/driver/spi/sdspi/sdspi_private.h +++ b/components/esp_driver_sdspi/src/sdspi_private.h @@ -34,7 +34,6 @@ /// Data rejected due to write error #define TOKEN_RSP_WRITE_ERR 0b01101 - /// Data error tokens have format 0b0000xyzw where xyzw are signle bit flags. /// MASK and VAL are used to check if a token is an error token #define TOKEN_ERR_MASK 0b11110000 @@ -49,7 +48,6 @@ /// Card is locked #define TOKEN_ERR_LOCKED BIT(0) - /// Transfer format in SPI mode. See section 7.3.1.1 of SD simplified spec. typedef struct { // These fields form the command sent from host to the card (6 bytes) diff --git a/components/driver/spi/sdspi/sdspi_transaction.c b/components/esp_driver_sdspi/src/sdspi_transaction.c similarity index 93% rename from components/driver/spi/sdspi/sdspi_transaction.c rename to components/esp_driver_sdspi/src/sdspi_transaction.c index f60b9535d08..ad139c7cc4d 100644 --- a/components/driver/spi/sdspi/sdspi_transaction.c +++ b/components/esp_driver_sdspi/src/sdspi_transaction.c @@ -8,9 +8,8 @@ #include "esp_err.h" #include "esp_log.h" #include "sys/lock.h" -#include "driver/sdmmc_types.h" -#include "driver/sdmmc_defs.h" -#include "driver/sdmmc_types.h" +#include "sd_protocol_defs.h" +#include "sd_protocol_types.h" #include "sdspi_private.h" #include "sdspi_crc.h" @@ -22,7 +21,7 @@ static bool s_app_cmd; static uint8_t sdspi_msg_crc7(sdspi_hw_cmd_t* hw_cmd) { const size_t bytes_to_crc = offsetof(sdspi_hw_cmd_t, arguments) + - sizeof(hw_cmd->arguments); /* can't take address of bit fields */ + sizeof(hw_cmd->arguments); /* can't take address of bit fields */ return sdspi_crc7((const uint8_t *)hw_cmd, bytes_to_crc); } @@ -128,7 +127,7 @@ esp_err_t sdspi_host_do_transaction(int slot, sdmmc_command_t *cmdinfo) } else if (s_app_cmd && cmdinfo->opcode == SD_APP_SD_STATUS) { flags |= SDSPI_CMD_FLAG_RSP_R2; } else if (!s_app_cmd && cmdinfo->opcode == MMC_GO_IDLE_STATE && - !(cmdinfo->flags & SCF_RSP_R1)) { + !(cmdinfo->flags & SCF_RSP_R1)) { /* used to send CMD0 without expecting a response */ flags |= SDSPI_CMD_FLAG_NORSP; } else if (!s_app_cmd && cmdinfo->opcode == SD_IO_SEND_OP_COND) { @@ -137,9 +136,13 @@ esp_err_t sdspi_host_do_transaction(int slot, sdmmc_command_t *cmdinfo) flags |= SDSPI_CMD_FLAG_RSP_R5; } else if (!s_app_cmd && cmdinfo->opcode == SD_IO_RW_EXTENDED) { flags |= SDSPI_CMD_FLAG_RSP_R5 | SDSPI_CMD_FLAG_DATA; - if (cmdinfo->arg & SD_ARG_CMD53_WRITE) flags |= SDSPI_CMD_FLAG_WRITE; + if (cmdinfo->arg & SD_ARG_CMD53_WRITE) { + flags |= SDSPI_CMD_FLAG_WRITE; + } // The CMD53 can assign block mode in the arg when the length is exactly 512 bytes - if (cmdinfo->arg & SD_ARG_CMD53_BLOCK_MODE) flags |= SDSPI_CMD_FLAG_MULTI_BLK; + if (cmdinfo->arg & SD_ARG_CMD53_BLOCK_MODE) { + flags |= SDSPI_CMD_FLAG_MULTI_BLK; + } } else if (!s_app_cmd && (cmdinfo->opcode == MMC_ERASE || cmdinfo->opcode == MMC_STOP_TRANSMISSION)) { flags |= SDSPI_CMD_FLAG_RSP_R1B; } else { @@ -148,7 +151,7 @@ esp_err_t sdspi_host_do_transaction(int slot, sdmmc_command_t *cmdinfo) // Send the command and get the response. esp_err_t ret = sdspi_host_start_command(slot, &hw_cmd, - cmdinfo->data, cmdinfo->datalen, flags); + cmdinfo->data, cmdinfo->datalen, flags); // Extract response bytes and store them into cmdinfo structure if (ret == ESP_OK) { diff --git a/components/esp_driver_sdspi/test_apps/.build-test-rules.yml b/components/esp_driver_sdspi/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..9c1df73b266 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/.build-test-rules.yml @@ -0,0 +1,10 @@ +components/esp_driver_sdspi/test_apps/sdspi: + disable: + - if: SOC_GPSPI_SUPPORTED != 1 + disable_test: + - if: SOC_GPSPI_SUPPORTED == 1 + temporary: true + reason: will add runners later # TODO: IDF-8747 + depends_components: + - sdmmc + - esp_driver_sdspi diff --git a/components/esp_driver_sdspi/test_apps/sdspi/CMakeLists.txt b/components/esp_driver_sdspi/test_apps/sdspi/CMakeLists.txt new file mode 100644 index 00000000000..2725c2f9ad1 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/CMakeLists.txt @@ -0,0 +1,10 @@ +cmake_minimum_required(VERSION 3.16) + +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/components/esp_driver_sdmmc/test_apps/sd_test_utils/components") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests") + +set(COMPONENTS main) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(sdmmc_test_console) diff --git a/components/driver/test_apps/rs485/README.md b/components/esp_driver_sdspi/test_apps/sdspi/README.md similarity index 100% rename from components/driver/test_apps/rs485/README.md rename to components/esp_driver_sdspi/test_apps/sdspi/README.md diff --git a/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/CMakeLists.txt b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/CMakeLists.txt new file mode 100644 index 00000000000..b4e403e4074 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/CMakeLists.txt @@ -0,0 +1,21 @@ +set(srcs) + +if(CONFIG_SOC_GPSPI_SUPPORTED) + list(APPEND srcs "sdmmc_test_begin_end_spi.c" + "sdmmc_test_cd_wp_spi.c" + "sdmmc_test_probe_spi.c" + "sdmmc_test_rw_spi.c" + "sdmmc_test_erase_spi.c" + "sdmmc_test_erase_common_spi.c") +endif() + +set(priv_requires "sdmmc" + "esp_driver_sdspi" + "sdmmc_test_boards" + "common_test_flows" + "unity" +) + +idf_component_register(SRCS ${srcs} + PRIV_REQUIRES ${priv_requires} + WHOLE_ARCHIVE TRUE) diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end_spi.c b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_begin_end_spi.c similarity index 97% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end_spi.c rename to components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_begin_end_spi.c index d69dc805655..2ab040bfcea 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_begin_end_spi.c +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_begin_end_spi.c @@ -11,9 +11,9 @@ #include "esp_log.h" #include "sdmmc_test_board.h" #include "driver/sdspi_host.h" -#include "driver/sdmmc_defs.h" +#include "sd_protocol_defs.h" #include "sdmmc_cmd.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_spi.h" void sdmmc_test_spi_skip_if_board_incompatible(int slot, int freq_khz) { diff --git a/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_begin_end_spi.h b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_begin_end_spi.h new file mode 100644 index 00000000000..95f20c8a2a9 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_begin_end_spi.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "sd_protocol_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defines for readability */ +#define SLOT_0 0 +#define SLOT_1 1 +#define NO_DDR 0 +#define WITH_DDR 1 + +/* Helper functions to initialize/deinintalize the host (SDMMC/SDSPI) inside the test */ + +/** + * @brief Skip the test if the board is incompatible with the given slot and frequency, for SPI mode. + * @see sdmmc_test_sd_skip_if_board_incompatible + */ +void sdmmc_test_spi_skip_if_board_incompatible(int slot, int freq_khz); + +/** + * @brief Helper function to initialize the SDMMC host and slot for the test using the given settings, for SPI mode + * @see sdmmc_test_sd_begin + */ +void sdmmc_test_spi_begin(int slot, int freq_khz, sdmmc_card_t *out_card); + +/** + * @brief Helper function to deinitialize the SDMMC host and slot after the test, for SPI mode + * @see sdmmc_test_sd_end + */ +void sdmmc_test_spi_end(int slot, sdmmc_card_t *card); + +#ifdef __cplusplus +}; +#endif diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_spi.c b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_cd_wp_spi.c similarity index 98% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_spi.c rename to components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_cd_wp_spi.c index a042ed6fac4..1787758eccf 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_cd_wp_spi.c +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_cd_wp_spi.c @@ -9,7 +9,7 @@ #include "driver/sdspi_host.h" #include "sdmmc_cmd.h" #include "sdmmc_test_board.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_spi.h" #include "sdmmc_test_cd_wp_common.h" TEST_CASE("CD input works in SPI mode", "[sdspi]") diff --git a/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_common_spi.c b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_common_spi.c new file mode 100644 index 00000000000..d7daf7a17d9 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_common_spi.c @@ -0,0 +1,198 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "sdmmc_cmd.h" +#include "sdmmc_test_begin_end_spi.h" + +#define PATTERN_SEED 0x12345678 +#define FLAG_ERASE_TEST_ADJACENT (1 << 0) +#define FLAG_VERIFY_ERASE_STATE (1 << 1) + +static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) +{ + srand(seed); + for (size_t i = 0; i < count; ++i) { + uint32_t val; + memcpy(&val, src + i * sizeof(uint32_t), sizeof(val)); + TEST_ASSERT_EQUAL_HEX32(rand(), val); + } +} + +static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) +{ + srand(seed); + for (size_t i = 0; i < count; ++i) { + uint32_t val = rand(); + memcpy(dst + i * sizeof(uint32_t), &val, sizeof(val)); + } +} + +static void ensure_sector_written(sdmmc_card_t* card, size_t sector, + uint8_t *pattern_buf, uint8_t *temp_buf) +{ + size_t block_size = card->csd.sector_size; + TEST_ESP_OK(sdmmc_write_sectors(card, pattern_buf, sector, 1)); + memset((void *)temp_buf, 0x00, block_size); + TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); + check_buffer(PATTERN_SEED, temp_buf, block_size / sizeof(uint32_t)); +} + +static void ensure_sector_intact(sdmmc_card_t* card, size_t sector, + uint8_t *pattern_buf, uint8_t *temp_buf) +{ + size_t block_size = card->csd.sector_size; + memset((void *)temp_buf, 0x00, block_size); + TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); + check_buffer(PATTERN_SEED, temp_buf, block_size / sizeof(uint32_t)); +} + +static int32_t ensure_sector_erase(sdmmc_card_t* card, size_t sector, + uint8_t *pattern_buf, uint8_t *temp_buf) +{ + size_t block_size = card->csd.sector_size; + memset((void *)temp_buf, 0, block_size); + TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); + return memcmp(pattern_buf, temp_buf, block_size); +} + +static void do_single_erase_test(sdmmc_card_t* card, size_t start_block, + size_t block_count, uint8_t flags, sdmmc_erase_arg_t arg) +{ + size_t block_size = card->csd.sector_size; + uint8_t *temp_buf = NULL; + uint8_t *pattern_buf = NULL; + size_t end_block = (start_block + block_count - 1); + + /* + * To ensure erase is successful/valid + * selected blocks after erase should have erase state data pattern + * data of blocks adjacent to selected region should remain intact + */ + TEST_ESP_OK((start_block + block_count) > card->csd.capacity); + + pattern_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(pattern_buf); + temp_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(temp_buf); + + // create pattern buffer + fill_buffer(PATTERN_SEED, pattern_buf, block_size / sizeof(uint32_t)); + + // check if it's not the first block of device & write/read/verify pattern + if ((flags & FLAG_ERASE_TEST_ADJACENT) && start_block) { + ensure_sector_written(card, (start_block - 1), pattern_buf, temp_buf); + } + + ensure_sector_written(card, start_block, pattern_buf, temp_buf); + + // check if it's not the last block of device & write/read/verify pattern + if ((flags & FLAG_ERASE_TEST_ADJACENT) && (end_block < (card->csd.capacity - 1))) { + ensure_sector_written(card, (end_block + 1), pattern_buf, temp_buf); + } + + // when block count is 1, start and end block is same, hence skip + if (block_count != 1) { + ensure_sector_written(card, end_block, pattern_buf, temp_buf); + } + + // fill pattern to (start_block + end_block)/2 in the erase range + if (block_count > 2) { + ensure_sector_written(card, (start_block + end_block) / 2, pattern_buf, temp_buf); + } + + float total_size = (block_count / 1024.0f) * block_size; + printf(" %10d | %10d | %8.1f ", start_block, block_count, total_size); + fflush(stdout); + + // erase the blocks + struct timeval t_start_er; + gettimeofday(&t_start_er, NULL); + TEST_ESP_OK(sdmmc_erase_sectors(card, start_block, block_count, arg)); + + struct timeval t_stop_wr; + gettimeofday(&t_stop_wr, NULL); + float time_er = 1e3f * (t_stop_wr.tv_sec - t_start_er.tv_sec) + 1e-3f * (t_stop_wr.tv_usec - t_start_er.tv_usec); + printf(" | %8.2f\n", time_er); + + // ensure adjacent blocks are not affected + // block before start_block + if ((flags & FLAG_ERASE_TEST_ADJACENT) && start_block) { + ensure_sector_intact(card, (start_block - 1), pattern_buf, temp_buf); + } + + // block after end_block + if ((flags & FLAG_ERASE_TEST_ADJACENT) && (end_block < (card->csd.capacity - 1))) { + ensure_sector_intact(card, (end_block + 1), pattern_buf, temp_buf); + } + + uint8_t erase_mem_byte = 0xFF; + // ensure all the blocks are erased and are up to after erase state. + if (!card->is_mmc) { + erase_mem_byte = card->scr.erase_mem_state ? 0xFF : 0x00; + } else { + erase_mem_byte = card->ext_csd.erase_mem_state ? 0xFF : 0x00; + } + + memset((void *)pattern_buf, erase_mem_byte, block_size); + + // as it is block by block comparison, a time taking process. Really long + // when you do erase and verify on complete device. + if (flags & FLAG_VERIFY_ERASE_STATE) { + for (size_t i = 0; i < block_count; i++) { + if (ensure_sector_erase(card, (start_block + i), pattern_buf, temp_buf)) { + printf("Error: Sector %d erase\n", (start_block + i)); + break; + } + } + } + + free(temp_buf); + free(pattern_buf); +} + +void sdmmc_test_sd_erase_blocks(sdmmc_card_t* card) +{ + printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); + printf(" sector | count | size(kB) | er_time(ms) \n"); + /* + * bit-0: verify adjacent blocks of given range + * bit-1: verify erase state of blocks in range + */ + uint8_t flags = 0; + sdmmc_erase_arg_t arg = SDMMC_ERASE_ARG; + + //check for adjacent blocks and erase state of blocks + flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT | (uint8_t)FLAG_VERIFY_ERASE_STATE; + do_single_erase_test(card, 1, 16, flags, arg); + do_single_erase_test(card, 1, 13, flags, arg); + do_single_erase_test(card, 16, 32, flags, arg); + do_single_erase_test(card, 48, 64, flags, arg); + do_single_erase_test(card, 128, 128, flags, arg); + do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); + do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); + // single sector erase is failing on different make cards + do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 1, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 4, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 8, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 16, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 32, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 64, flags, arg); + do_single_erase_test(card, card->csd.capacity / 2, 128, flags, arg); +#ifdef SDMMC_FULL_ERASE_TEST + /* + * check for adjacent blocks, do not check erase state of blocks as it is + * time taking process to verify all the blocks. + */ + flags &= ~(uint8_t)FLAG_VERIFY_ERASE_STATE; //comment this line to verify after-erase state + // erase complete card + do_single_erase_test(card, 0, card->csd.capacity, flags, arg); +#endif //SDMMC_FULL_ERASE_TEST +} diff --git a/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_common_spi.h b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_common_spi.h new file mode 100644 index 00000000000..572c9e1f893 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_common_spi.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "driver/sdmmc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Test erase blocks performance of the card + * + * This function writes a buffer to the card, then erase all the buffers. + * The time taken for each operation is measured, and the throughput is calculated. + * The process is repeated for different buffer ranges. + * In this test, data is always written and then erase from the card + * + * This test function works both with SDMMC and SDSPI hosts. + * + * @param card Pointer to the card object, must be initialized before calling this function. + */ +void sdmmc_test_sd_erase_blocks(sdmmc_card_t* card); + +#ifdef __cplusplus +}; +#endif diff --git a/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_spi.c b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_spi.c new file mode 100644 index 00000000000..5f1e3c10f37 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_erase_spi.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "unity.h" +#include "sdmmc_cmd.h" +#include "sdmmc_test_begin_end_spi.h" +#include "sdmmc_test_erase_common_spi.h" + +static void do_one_sdspi_erase(int slot, int freq_khz) +{ + sdmmc_card_t card; + sdmmc_test_spi_skip_if_board_incompatible(slot, freq_khz); + sdmmc_test_spi_begin(slot, freq_khz, &card); + sdmmc_card_print_info(stdout, &card); + sdmmc_test_sd_erase_blocks(&card); + sdmmc_test_spi_end(slot, &card); +} + +TEST_CASE("sdspi erase, slot 1", "[sdspi]") +{ + do_one_sdspi_erase(SLOT_1, SDMMC_FREQ_PROBING); + do_one_sdspi_erase(SLOT_1, SDMMC_FREQ_DEFAULT); +} diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_probe_spi.c b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_probe_spi.c similarity index 69% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_probe_spi.c rename to components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_probe_spi.c index d50725f16da..42da8c1e93b 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_probe_spi.c +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_probe_spi.c @@ -6,7 +6,9 @@ #include #include "unity.h" #include "sdmmc_cmd.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_spi.h" + +#define SDMMC_FREQ_CUSTOM_10M 10000 static void do_one_sdspi_probe(int slot, int freq_khz) { @@ -30,13 +32,21 @@ TEST_CASE("sdspi probe, slot 0, HS", "[sdspi]") do_one_sdspi_probe(SLOT_0, SDMMC_FREQ_HIGHSPEED); } +#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3 +//TODO: IDF-8750. Leaks too much memory, needs check TEST_CASE("sdspi probe, slot 1", "[sdspi]") { do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_PROBING); do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_DEFAULT); + do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_CUSTOM_10M); } +#endif +#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3 +//TODO: IDF-8749 +//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749 TEST_CASE("sdspi probe, slot 1, HS", "[sdspi]") { - do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_HIGHSPEED); + do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_DEFAULT); } +#endif diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_spi.c b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_rw_spi.c similarity index 81% rename from components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_spi.c rename to components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_rw_spi.c index 3d96bb7179e..a45e5f0c13b 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/sdmmc_test_rw_spi.c +++ b/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_rw_spi.c @@ -6,7 +6,7 @@ #include #include "unity.h" #include "sdmmc_cmd.h" -#include "sdmmc_test_begin_end.h" +#include "sdmmc_test_begin_end_spi.h" #include "sdmmc_test_rw_common.h" /* ========== Read/write performance tests, SPI ========== */ @@ -26,10 +26,14 @@ TEST_CASE("sdspi read/write performance, slot 0", "[sdspi]") do_one_sdspi_perf_test(SLOT_0, SDMMC_FREQ_HIGHSPEED); } +#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3 +//TODO: IDF-8749 +//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749 TEST_CASE("sdspi read/write performance, slot 1", "[sdspi]") { - do_one_sdspi_perf_test(SLOT_1, SDMMC_FREQ_HIGHSPEED); + do_one_sdspi_perf_test(SLOT_1, SDMMC_FREQ_DEFAULT); } +#endif /* ========== Read/write tests with offset, SPI ========== */ @@ -48,10 +52,14 @@ TEST_CASE("sdspi read/write performance with offset, slot 0", "[sdspi]") do_one_sdspi_rw_test_with_offset(SLOT_0, SDMMC_FREQ_HIGHSPEED); } +#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3 +//TODO: IDF-8749 +//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749 TEST_CASE("sdspi read/write performance with offset, slot 1", "[sdspi]") { - do_one_sdspi_rw_test_with_offset(SLOT_1, SDMMC_FREQ_HIGHSPEED); + do_one_sdspi_rw_test_with_offset(SLOT_1, SDMMC_FREQ_DEFAULT); } +#endif /* ========== Read/write tests with unaligned source/destination buffer, SPI ========== */ diff --git a/components/esp_driver_sdspi/test_apps/sdspi/main/CMakeLists.txt b/components/esp_driver_sdspi/test_apps/sdspi/main/CMakeLists.txt new file mode 100644 index 00000000000..797caf73e9f --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/main/CMakeLists.txt @@ -0,0 +1,13 @@ +set(srcs "test_app_main.c") + +set(priv_requires + # tests reside in this component, also available for `sdmmc_console` + sdspi_tests + # general + unity +) + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS "." + PRIV_REQUIRES ${priv_requires} + WHOLE_ARCHIVE TRUE) diff --git a/components/esp_driver_sdspi/test_apps/sdspi/main/test_app_main.c b/components/esp_driver_sdspi/test_apps/sdspi/main/test_app_main.c new file mode 100644 index 00000000000..274579059d1 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/main/test_app_main.c @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + */ + +#include "unity.h" +#include "unity_test_utils.h" +#include "esp_heap_caps.h" +#include "sdkconfig.h" + +#define TEST_MEMORY_LEAK_THRESHOLD (400) + +void setUp(void) +{ + unity_utils_record_free_mem(); +} + +void tearDown(void) +{ + unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD); +} + +void app_main(void) +{ + /* + _____ _ ___________ ___________ _____ + |_ _| | | / ___| _ \/ ___| ___ \_ _| + | | ___ ___| |_ \ `--.| | | |\ `--.| |_/ / | | + | |/ _ \/ __| __| `--. \ | | | `--. \ __/ | | + | | __/\__ \ |_ /\__/ / |/ / /\__/ / | _| |_ + \_/\___||___/\__| \____/|___/ \____/\_| \___/ + */ + + printf(" _____ _ ___________ ___________ _____\n"); + printf("|_ _| | | / ___| _ \\/ ___| ___ \\_ _|\n"); + printf(" | | ___ ___| |_ \\ `--.| | | |\\ `--.| |_/ / | |\n"); + printf(" | |/ _ \\/ __| __| `--. \\ | | | `--. \\ __/ | |\n"); + printf(" | | __/\\__ \\ |_ /\\__/ / |/ / /\\__/ / | _| |_\n"); + printf(" \\_/\\___||___/\\__| \\____/|___/ \\____/\\_| \\___/\n"); + + unity_run_menu(); +} diff --git a/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py b/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py new file mode 100644 index 00000000000..f2d30a8c2d2 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py @@ -0,0 +1,8 @@ +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +from pytest_embedded_idf import IdfDut + + +def test_sdspi(dut: IdfDut) -> None: + dut.run_all_single_board_cases() diff --git a/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults b/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults new file mode 100644 index 00000000000..fa8ac618b94 --- /dev/null +++ b/components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT_EN=n diff --git a/components/esp_driver_spi/CMakeLists.txt b/components/esp_driver_spi/CMakeLists.txt new file mode 100644 index 00000000000..a2c123ab761 --- /dev/null +++ b/components/esp_driver_spi/CMakeLists.txt @@ -0,0 +1,27 @@ +idf_build_get_property(target IDF_TARGET) + +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() + +set(srcs "") + +set(public_include "include") + +if(CONFIG_SOC_GPSPI_SUPPORTED) + list(APPEND srcs "src/gpspi/spi_common.c" + "src/gpspi/spi_master.c" + "src/gpspi/spi_slave.c" + "src/gpspi/spi_dma.c") +endif() + +if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2) + list(APPEND srcs "src/gpspi/spi_slave_hd.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + REQUIRES esp_pm + PRIV_REQUIRES esp_timer esp_mm esp_driver_gpio esp_ringbuf + LDFRAGMENTS "linker.lf" + ) diff --git a/components/esp_driver_spi/Kconfig b/components/esp_driver_spi/Kconfig new file mode 100644 index 00000000000..6ef7191211d --- /dev/null +++ b/components/esp_driver_spi/Kconfig @@ -0,0 +1,63 @@ +menu "ESP-Driver:SPI Configurations" + depends on SOC_GPSPI_SUPPORTED + config SPI_MASTER_IN_IRAM + bool "Place transmitting functions of SPI master into IRAM" + default n + depends on !FREERTOS_PLACE_FUNCTIONS_INTO_FLASH + select SPI_MASTER_ISR_IN_IRAM + select ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM + help + Normally only the ISR of SPI master is placed in the IRAM, so that it + can work without the flash when interrupt is triggered. + For other functions, there's some possibility that the flash cache + miss when running inside and out of SPI functions, which may increase + the interval of SPI transactions. + Enable this to put ``queue_trans``, ``get_trans_result`` and + ``transmit`` functions into the IRAM to avoid possible cache miss. + + This configuration won't be available if `CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH` is enabled. + + During unit test, this is enabled to measure the ideal case of api. + + config SPI_MASTER_ISR_IN_IRAM + bool "Place SPI master ISR function into IRAM" + default y + depends on !HEAP_PLACE_FUNCTION_INTO_FLASH + select PERIPH_CTRL_FUNC_IN_IRAM + select HAL_SPI_MASTER_FUNC_IN_IRAM + select ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM + help + Place the SPI master ISR in to IRAM to avoid possible cache miss. + + Enabling this configuration is possible only when HEAP_PLACE_FUNCTION_INTO_FLASH + is disabled since the spi master uses can allocate transactions buffers into DMA + memory section using the heap component API that ipso facto has to be placed in IRAM. + + Also you can forbid the ISR being disabled during flash writing + access, by add ESP_INTR_FLAG_IRAM when initializing the driver. + + config SPI_SLAVE_IN_IRAM + bool "Place transmitting functions of SPI slave into IRAM" + default n + select SPI_SLAVE_ISR_IN_IRAM + help + Normally only the ISR of SPI slave is placed in the IRAM, so that it + can work without the flash when interrupt is triggered. + For other functions, there's some possibility that the flash cache + miss when running inside and out of SPI functions, which may increase + the interval of SPI transactions. + Enable this to put ``queue_trans``, ``get_trans_result`` and + ``transmit`` functions into the IRAM to avoid possible cache miss. + + config SPI_SLAVE_ISR_IN_IRAM + bool "Place SPI slave ISR function into IRAM" + default y + select PERIPH_CTRL_FUNC_IN_IRAM + select HAL_SPI_SLAVE_FUNC_IN_IRAM + help + Place the SPI slave ISR in to IRAM to avoid possible cache miss. + + Also you can forbid the ISR being disabled during flash writing + access, by add ESP_INTR_FLAG_IRAM when initializing the driver. + +endmenu # SPI Configuration diff --git a/components/driver/spi/include/driver/spi_common.h b/components/esp_driver_spi/include/driver/spi_common.h similarity index 87% rename from components/driver/spi/include/driver/spi_common.h rename to components/esp_driver_spi/include/driver/spi_common.h index dfb5809ea1d..23f5299ea09 100644 --- a/components/driver/spi/include/driver/spi_common.h +++ b/components/esp_driver_spi/include/driver/spi_common.h @@ -69,12 +69,12 @@ extern "C" * @brief SPI DMA channels */ typedef enum { - SPI_DMA_DISABLED = 0, ///< Do not enable DMA for SPI + SPI_DMA_DISABLED = 0, ///< Do not enable DMA for SPI #if CONFIG_IDF_TARGET_ESP32 - SPI_DMA_CH1 = 1, ///< Enable DMA, select DMA Channel 1 - SPI_DMA_CH2 = 2, ///< Enable DMA, select DMA Channel 2 + SPI_DMA_CH1 = 1, ///< Enable DMA, select DMA Channel 1 + SPI_DMA_CH2 = 2, ///< Enable DMA, select DMA Channel 2 #endif - SPI_DMA_CH_AUTO = 3, ///< Enable DMA, channel is automatically selected by driver + SPI_DMA_CH_AUTO = 3, ///< Enable DMA, channel is automatically selected by driver } spi_common_dma_t; #if __cplusplus @@ -95,21 +95,21 @@ typedef spi_common_dma_t spi_dma_chan_t; */ typedef struct { union { - int mosi_io_num; ///< GPIO pin for Master Out Slave In (=spi_d) signal, or -1 if not used. - int data0_io_num; ///< GPIO pin for spi data0 signal in quad/octal mode, or -1 if not used. + int mosi_io_num; ///< GPIO pin for Master Out Slave In (=spi_d) signal, or -1 if not used. + int data0_io_num; ///< GPIO pin for spi data0 signal in quad/octal mode, or -1 if not used. }; union { - int miso_io_num; ///< GPIO pin for Master In Slave Out (=spi_q) signal, or -1 if not used. - int data1_io_num; ///< GPIO pin for spi data1 signal in quad/octal mode, or -1 if not used. + int miso_io_num; ///< GPIO pin for Master In Slave Out (=spi_q) signal, or -1 if not used. + int data1_io_num; ///< GPIO pin for spi data1 signal in quad/octal mode, or -1 if not used. }; int sclk_io_num; ///< GPIO pin for SPI Clock signal, or -1 if not used. union { - int quadwp_io_num; ///< GPIO pin for WP (Write Protect) signal, or -1 if not used. - int data2_io_num; ///< GPIO pin for spi data2 signal in quad/octal mode, or -1 if not used. + int quadwp_io_num; ///< GPIO pin for WP (Write Protect) signal, or -1 if not used. + int data2_io_num; ///< GPIO pin for spi data2 signal in quad/octal mode, or -1 if not used. }; union { - int quadhd_io_num; ///< GPIO pin for HD (Hold) signal, or -1 if not used. - int data3_io_num; ///< GPIO pin for spi data3 signal in quad/octal mode, or -1 if not used. + int quadhd_io_num; ///< GPIO pin for HD (Hold) signal, or -1 if not used. + int data3_io_num; ///< GPIO pin for spi data3 signal in quad/octal mode, or -1 if not used. }; int data4_io_num; ///< GPIO pin for spi data4 signal in octal mode, or -1 if not used. int data5_io_num; ///< GPIO pin for spi data5 signal in octal mode, or -1 if not used. @@ -125,7 +125,6 @@ typedef struct { */ } spi_bus_config_t; - /** * @brief Initialize a SPI bus * diff --git a/components/driver/spi/include/driver/spi_master.h b/components/esp_driver_spi/include/driver/spi_master.h similarity index 99% rename from components/driver/spi/include/driver/spi_master.h rename to components/esp_driver_spi/include/driver/spi_master.h index 305d6beadd8..0fb098954ce 100644 --- a/components/driver/spi/include/driver/spi_master.h +++ b/components/esp_driver_spi/include/driver/spi_master.h @@ -102,7 +102,6 @@ typedef struct { */ } spi_device_interface_config_t; - #define SPI_TRANS_MODE_DIO (1<<0) ///< Transmit/receive data in 2-bit mode #define SPI_TRANS_MODE_QIO (1<<1) ///< Transmit/receive data in 4-bit mode #define SPI_TRANS_USE_RXDATA (1<<2) ///< Receive into rx_data member of spi_transaction_t instead into memory at rx_buffer. @@ -158,7 +157,6 @@ typedef struct { uint8_t dummy_bits; ///< The dummy length in this transaction, in bits. } spi_transaction_ext_t ; - typedef struct spi_device_t *spi_device_handle_t; ///< Handle for a device on a SPI bus /** * @brief Allocate a device on a SPI bus @@ -183,7 +181,6 @@ typedef struct spi_device_t *spi_device_handle_t; ///< Handle for a device on a */ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interface_config_t *dev_config, spi_device_handle_t *handle); - /** * @brief Remove a device from the SPI bus * @@ -195,7 +192,6 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa */ esp_err_t spi_bus_remove_device(spi_device_handle_t handle); - /** * @brief Queue a SPI transaction for interrupt transaction execution. Get the result by ``spi_device_get_trans_result``. * @@ -217,7 +213,6 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle); */ esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait); - /** * @brief Get the result of a SPI transaction queued earlier by ``spi_device_queue_trans``. * @@ -240,7 +235,6 @@ esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t * */ esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait); - /** * @brief Send a SPI transaction, wait for it to complete, and return the result * @@ -259,7 +253,6 @@ esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transactio */ esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc); - /** * @brief Immediately start a polling transaction. * @@ -283,7 +276,6 @@ esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *tra */ esp_err_t spi_device_polling_start(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait); - /** * @brief Poll until the polling transaction ends. * @@ -301,7 +293,6 @@ esp_err_t spi_device_polling_start(spi_device_handle_t handle, spi_transaction_t */ esp_err_t spi_device_polling_end(spi_device_handle_t handle, TickType_t ticks_to_wait); - /** * @brief Send a polling transaction, wait for it to complete, and return the result * @@ -323,7 +314,6 @@ esp_err_t spi_device_polling_end(spi_device_handle_t handle, TickType_t ticks_to */ esp_err_t spi_device_polling_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc); - /** * @brief Occupy the SPI bus for a device to do continuous transactions. * diff --git a/components/driver/spi/include/driver/spi_slave.h b/components/esp_driver_spi/include/driver/spi_slave.h similarity index 98% rename from components/driver/spi/include/driver/spi_slave.h rename to components/esp_driver_spi/include/driver/spi_slave.h index cc07d094f71..beef8866aae 100644 --- a/components/driver/spi/include/driver/spi_slave.h +++ b/components/esp_driver_spi/include/driver/spi_slave.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #ifndef _DRIVER_SPI_SLAVE_H_ #define _DRIVER_SPI_SLAVE_H_ @@ -13,13 +12,11 @@ #include "freertos/semphr.h" #include "driver/spi_common.h" - #ifdef __cplusplus extern "C" { #endif - #define SPI_SLAVE_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first #define SPI_SLAVE_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first #define SPI_SLAVE_BIT_LSBFIRST (SPI_SLAVE_TXBIT_LSBFIRST|SPI_SLAVE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first @@ -65,7 +62,6 @@ typedef struct { */ } spi_slave_interface_config_t; - #define SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO (1<<0) ///< Automatically re-malloc dma buffer if user buffer doesn't meet hardware alignment or dma_capable, this process may loss some memory and performance /** @@ -123,10 +119,11 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b */ esp_err_t spi_slave_free(spi_host_device_t host); - /** * @brief Queue a SPI transaction for execution * + * @note On esp32, if trans length not WORD aligned, the rx buffer last word memory will still overwritten by DMA HW + * * Queues a SPI transaction to be executed by this slave device. (The transaction queue size was specified when the slave * device was initialised via spi_slave_initialize.) This function may block if the queue is full (depending on the * ticks_to_wait parameter). No SPI operation is directly initiated by this function, the next queued transaction @@ -148,7 +145,6 @@ esp_err_t spi_slave_free(spi_host_device_t host); */ esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait); - /** * @brief Get the result of a SPI transaction queued earlier * @@ -171,7 +167,6 @@ esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transact */ esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait); - /** * @brief Do a SPI transaction * @@ -191,7 +186,6 @@ esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transacti */ esp_err_t spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait); - #ifdef __cplusplus } #endif diff --git a/components/driver/spi/include/driver/spi_slave_hd.h b/components/esp_driver_spi/include/driver/spi_slave_hd.h similarity index 99% rename from components/driver/spi/include/driver/spi_slave_hd.h rename to components/esp_driver_spi/include/driver/spi_slave_hd.h index fbd8caca4a7..a8ba436958c 100644 --- a/components/driver/spi/include/driver/spi_slave_hd.h +++ b/components/esp_driver_spi/include/driver/spi_slave_hd.h @@ -62,7 +62,6 @@ typedef struct { void* arg; ///< Argument indicating this SPI Slave HD peripheral instance } spi_slave_hd_callback_config_t; - //flags for ``spi_slave_hd_slot_config_t`` to use #define SPI_SLAVE_HD_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first #define SPI_SLAVE_HD_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first diff --git a/components/esp_driver_spi/include/esp_private/spi_common_internal.h b/components/esp_driver_spi/include/esp_private/spi_common_internal.h new file mode 100644 index 00000000000..4652347593d --- /dev/null +++ b/components/esp_driver_spi/include/esp_private/spi_common_internal.h @@ -0,0 +1,299 @@ +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Internal header, don't use it in the user code + +#pragma once + +#include +#include "driver/spi_common.h" +#include "freertos/FreeRTOS.h" +#include "hal/spi_types.h" +#include "hal/dma_types.h" +#include "esp_private/spi_dma.h" +#include "esp_pm.h" +#include "esp_private/spi_share_hw_ctrl.h" +#if SOC_GDMA_SUPPORTED +#include "esp_private/gdma.h" +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef CONFIG_SPI_MASTER_ISR_IN_IRAM +#define SPI_MASTER_ISR_ATTR IRAM_ATTR +#else +#define SPI_MASTER_ISR_ATTR +#endif + +#ifdef CONFIG_SPI_MASTER_IN_IRAM +#define SPI_MASTER_ATTR IRAM_ATTR +#else +#define SPI_MASTER_ATTR +#endif + +//NOTE!! If both A and B are not defined, '#if (A==B)' is true, because GCC use 0 stand for undefined symbol +#if SOC_GPSPI_SUPPORTED && defined(SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI) +#define DMA_DESC_MEM_ALIGN_SIZE 8 +typedef dma_descriptor_align8_t spi_dma_desc_t; +#else +#define DMA_DESC_MEM_ALIGN_SIZE 4 +typedef dma_descriptor_align4_t spi_dma_desc_t; +#endif + +/// Attributes of an SPI bus +typedef struct { + spi_bus_config_t bus_cfg; ///< Config used to initialize the bus + uint32_t flags; ///< Flags (attributes) of the bus + int max_transfer_sz; ///< Maximum length of bytes available to send + bool dma_enabled; ///< To enable DMA or not + uint16_t internal_mem_align_size; ///< Buffer align byte requirement for internal memory + spi_bus_lock_handle_t lock; +#ifdef CONFIG_PM_ENABLE + esp_pm_lock_handle_t pm_lock; ///< Power management lock +#endif +} spi_bus_attr_t; + +typedef struct { +#if SOC_GDMA_SUPPORTED + gdma_channel_handle_t tx_dma_chan; ///< GDMA tx channel + gdma_channel_handle_t rx_dma_chan; ///< GDMA rx channel +#else + spi_dma_chan_handle_t tx_dma_chan; ///< TX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan are same + spi_dma_chan_handle_t rx_dma_chan; ///< RX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan are same +#endif + int dma_desc_num; ///< DMA descriptor number of dmadesc_tx or dmadesc_rx. + spi_dma_desc_t *dmadesc_tx; ///< DMA descriptor array for TX + spi_dma_desc_t *dmadesc_rx; ///< DMA descriptor array for RX +} spi_dma_ctx_t; + +/// Destructor called when a bus is deinitialized. +typedef esp_err_t (*spi_destroy_func_t)(void*); + +/** + * @brief Alloc DMA channel for SPI + * + * @param host_id SPI host ID + * @param dma_chan DMA channel to be used + * @param out_dma_ctx Actual DMA channel context (if you choose to assign a specific DMA channel, this will be the channel you assigned before) + * + * @return + * - ESP_OK: On success + * - ESP_ERR_NO_MEM: No enough memory + * - ESP_ERR_NOT_FOUND: There is no available DMA channel + */ +esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, spi_dma_ctx_t **out_dma_ctx); + +/** + * @brief Alloc DMA descriptors for SPI + * + * @param dma_ctx DMA context returned by `spicommon_dma_chan_alloc` + * @param[in] cfg_max_sz Expected maximum transfer size, in bytes. + * @param[out] actual_max_sz Actual max transfer size one transaction can be, in bytes. + * + * @return + * - ESP_OK: On success + * - ESP_ERR_NO_MEM: No enough memory + */ +esp_err_t spicommon_dma_desc_alloc(spi_dma_ctx_t *dma_ctx, int cfg_max_sz, int *actual_max_sz); + +/** + * @brief Free DMA for SPI + * + * @param dma_ctx spi_dma_ctx_t struct pointer + * + * @return + * - ESP_OK: On success + */ +esp_err_t spicommon_dma_chan_free(spi_dma_ctx_t *dma_ctx); + +/** + * @brief Connect a SPI peripheral to GPIO pins + * + * This routine is used to connect a SPI peripheral to the IO-pads and DMA channel given in + * the arguments. Depending on the IO-pads requested, the routing is done either using the + * IO_mux or using the GPIO matrix. + * + * @param host SPI peripheral to be routed + * @param bus_config Pointer to a spi_bus_config struct detailing the GPIO pins + * @param flags Combination of SPICOMMON_BUSFLAG_* flags, set to ensure the pins set are capable with some functions: + * - ``SPICOMMON_BUSFLAG_MASTER``: Initialize I/O in master mode + * - ``SPICOMMON_BUSFLAG_SLAVE``: Initialize I/O in slave mode + * - ``SPICOMMON_BUSFLAG_IOMUX_PINS``: Pins set should match the iomux pins of the controller. + * - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: + * Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capability according to the mode. + * - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so that DIO mode is capable. + * - ``SPICOMMON_BUSFLAG_WPHD`` Make sure WP and HD are set to valid output GPIOs. + * - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``. + * - ``SPICOMMON_BUSFLAG_IO4_IO7``: Make sure spi data4 ~ spi data7 are set to valid output GPIOs. + * - ``SPICOMMON_BUSFLAG_OCTAL``: Combination of ``SPICOMMON_BUSFLAG_QUAL`` and ``SPICOMMON_BUSFLAG_IO4_IO7``. + * @param[out] flags_o A SPICOMMON_BUSFLAG_* flag combination of bus abilities will be written to this address. + * Leave to NULL if not needed. + * - ``SPICOMMON_BUSFLAG_IOMUX_PINS``: The bus is connected to iomux pins. + * - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: The bus has + * CLK/MISO/MOSI connected. + * - ``SPICOMMON_BUSFLAG_DUAL``: The bus is capable with DIO mode. + * - ``SPICOMMON_BUSFLAG_WPHD`` The bus has WP and HD connected. + * - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``. + * - ``SPICOMMON_BUSFLAG_IO4_IO7``: The bus has spi data4 ~ spi data7 connected. + * - ``SPICOMMON_BUSFLAG_OCTAL``: Combination of ``SPICOMMON_BUSFLAG_QUAL`` and ``SPICOMMON_BUSFLAG_IO4_IO7``. + * @return + * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_OK on success + */ +esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, uint32_t flags, uint32_t *flags_o); + +/** + * @brief Free the IO used by a SPI peripheral + * + * @param bus_cfg Bus config struct which defines which pins to be used. + * + * @return + * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_OK on success + */ +esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg); + +/** + * @brief Initialize a Chip Select pin for a specific SPI peripheral + * + * @param host SPI peripheral + * @param cs_io_num GPIO pin to route + * @param cs_num CS id to route + * @param force_gpio_matrix If true, CS will always be routed through the GPIO matrix. If false, + * if the GPIO number allows it, the routing will happen through the IO_mux. + */ +void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix); + +/** + * @brief Free a chip select line + * + * @param cs_gpio_num CS gpio num to free + */ +void spicommon_cs_free_io(int cs_gpio_num); + +/** + * @brief Check whether all pins used by a host are through IOMUX. + * + * @param host SPI peripheral + * + * @return false if any pins are through the GPIO matrix, otherwise true. + */ +bool spicommon_bus_using_iomux(spi_host_device_t host); + +/** + * @brief Get the IRQ source for a specific SPI host + * + * @param host The SPI host + * + * @return The hosts IRQ source + */ +int spicommon_irqsource_for_host(spi_host_device_t host); + +/** + * @brief Get the IRQ source for a specific SPI DMA + * + * @param host The SPI host + * + * @return The hosts IRQ source + */ +int spicommon_irqdma_source_for_host(spi_host_device_t host); + +/** + * Callback, to be called when a DMA engine reset is completed +*/ +typedef void(*dmaworkaround_cb_t)(void *arg); + +#if CONFIG_IDF_TARGET_ESP32 +//This workaround is only for esp32 +/** + * @brief Request a reset for a certain DMA channel + * + * @note In some (well-defined) cases in the ESP32 (at least rev v.0 and v.1), a SPI DMA channel will get confused. This can be remedied + * by resetting the SPI DMA hardware in case this happens. Unfortunately, the reset knob used for thsi will reset _both_ DMA channels, and + * as such can only done safely when both DMA channels are idle. These functions coordinate this. + * + * Essentially, when a reset is needed, a driver can request this using spicommon_dmaworkaround_req_reset. This is supposed to be called + * with an user-supplied function as an argument. If both DMA channels are idle, this call will reset the DMA subsystem and return true. + * If the other DMA channel is still busy, it will return false; as soon as the other DMA channel is done, however, it will reset the + * DMA subsystem and call the callback. The callback is then supposed to be used to continue the SPI drivers activity. + * + * @param dmachan DMA channel associated with the SPI host that needs a reset + * @param cb Callback to call in case DMA channel cannot be reset immediately + * @param arg Argument to the callback + * + * @return True when a DMA reset could be executed immediately. False when it could not; in this + * case the callback will be called with the specified argument when the logic can execute + * a reset, after that reset. + */ +bool spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg); + +/** + * @brief Check if a DMA reset is requested but has not completed yet + * + * @return True when a DMA reset is requested but hasn't completed yet. False otherwise. + */ +bool spicommon_dmaworkaround_reset_in_progress(void); + +/** + * @brief Mark a DMA channel as idle. + * + * A call to this function tells the workaround logic that this channel will + * not be affected by a global SPI DMA reset. + */ +void spicommon_dmaworkaround_idle(int dmachan); + +/** + * @brief Mark a DMA channel as active. + * + * A call to this function tells the workaround logic that this channel will + * be affected by a global SPI DMA reset, and a reset like that should not be attempted. + */ +void spicommon_dmaworkaround_transfer_active(int dmachan); +#endif //#if CONFIG_IDF_TARGET_ESP32 + +/******************************************************************************* + * Bus attributes + ******************************************************************************/ +/** + * @brief Set bus lock for the main bus, called by startup code. + * + * @param lock The lock to be used by the main SPI bus. + */ +void spi_bus_main_set_lock(spi_bus_lock_handle_t lock); + +/** + * @brief Get the attributes of a specified SPI bus. + * + * @param host_id The specified host to get attribute + * @return (Const) Pointer to the attributes + */ +const spi_bus_attr_t* spi_bus_get_attr(spi_host_device_t host_id); + +/** + * @brief Get the dma context of a specified SPI bus. + * + * @param host_id The specified host to get attribute + * @return (Const) Pointer to the dma context + */ +const spi_dma_ctx_t* spi_bus_get_dma_ctx(spi_host_device_t host_id); + +/** + * @brief Register a function to a initialized bus to make it called when deinitializing the bus. + * + * @param host_id The SPI bus to register the destructor. + * @param f Destructor to register + * @param arg The argument to call the destructor + * @return Always ESP_OK. + */ +esp_err_t spi_bus_register_destroy_func(spi_host_device_t host_id, + spi_destroy_func_t f, void *arg); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_spi/include/esp_private/spi_dma.h b/components/esp_driver_spi/include/esp_private/spi_dma.h new file mode 100644 index 00000000000..39ff2c3c8fa --- /dev/null +++ b/components/esp_driver_spi/include/esp_private/spi_dma.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include "stdbool.h" +#include "hal/spi_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_GDMA_SUPPORTED +/** + * @brief Enumeration of SPI_DMA channel direction + */ +typedef enum { + DMA_CHANNEL_DIRECTION_TX, /*!< DMA channel direction: TX */ + DMA_CHANNEL_DIRECTION_RX, /*!< DMA channel direction: RX */ +} spi_dma_chan_dir_t; + +typedef struct { + spi_host_device_t host_id; + spi_dma_chan_dir_t dir; + int chan_id; +} spi_dma_chan_handle_t; + +/** + * Enable/Disable data/desc burst for spi_dma channel + * + * @param chan_handle Context of the spi_dma channel. + * @param data_burst enable or disable data burst + * @param desc_burst enable or disable desc burst + */ +void spi_dma_enable_burst(spi_dma_chan_handle_t chan_handle, bool data_burst, bool desc_burst); + +/** + * Reset dma channel for spi_dma + * + * @param chan_handle Context of the spi_dma channel. + */ +void spi_dma_reset(spi_dma_chan_handle_t chan_handle); + +/** + * Start dma channel for spi_dma + * + * @param chan_handle Context of the spi_dma channel. + * @param addr Addr of linked dma descriptor to mount + */ +void spi_dma_start(spi_dma_chan_handle_t chan_handle, void *addr); + +#endif //!SOC_GDMA_SUPPORTED + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/include/esp_private/spi_slave_internal.h b/components/esp_driver_spi/include/esp_private/spi_slave_internal.h similarity index 99% rename from components/driver/include/esp_private/spi_slave_internal.h rename to components/esp_driver_spi/include/esp_private/spi_slave_internal.h index 01de22fee62..75cec46b50b 100644 --- a/components/driver/include/esp_private/spi_slave_internal.h +++ b/components/esp_driver_spi/include/esp_private/spi_slave_internal.h @@ -22,7 +22,6 @@ extern "C" { #endif - /** * @brief Reset the trans Queue of slave driver * @note @@ -40,7 +39,6 @@ extern "C" { */ esp_err_t spi_slave_queue_reset(spi_host_device_t host); - /** * @brief Reset the trans Queue from within ISR of slave driver * @note @@ -55,7 +53,6 @@ esp_err_t spi_slave_queue_reset(spi_host_device_t host); */ esp_err_t spi_slave_queue_reset_isr(spi_host_device_t host); - /** * @brief Queue a SPI transaction in ISR * @note @@ -76,7 +73,6 @@ esp_err_t spi_slave_queue_reset_isr(spi_host_device_t host); */ esp_err_t spi_slave_queue_trans_isr(spi_host_device_t host, const spi_slave_transaction_t *trans_desc); - #ifdef __cplusplus } #endif diff --git a/components/esp_driver_spi/linker.lf b/components/esp_driver_spi/linker.lf new file mode 100644 index 00000000000..fe92562a6bb --- /dev/null +++ b/components/esp_driver_spi/linker.lf @@ -0,0 +1,7 @@ +[mapping:gpspi_driver] +archive: libesp_driver_spi.a +entries: + if SOC_GDMA_SUPPORTED = n: + if SPI_MASTER_ISR_IN_IRAM = y || SPI_SLAVE_ISR_IN_IRAM = y: + spi_dma: spi_dma_reset (noflash) + spi_dma: spi_dma_start (noflash) diff --git a/components/driver/spi/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c similarity index 72% rename from components/driver/spi/gpspi/spi_common.c rename to components/esp_driver_spi/src/gpspi/spi_common.c index a475ed4c147..981cd19ab5b 100644 --- a/components/driver/spi/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -4,13 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include "sdkconfig.h" #include "stdatomic.h" #include "esp_types.h" #include "esp_attr.h" #include "esp_check.h" +#include "esp_cache.h" #include "esp_rom_gpio.h" #include "esp_heap_caps.h" #include "soc/spi_periph.h" @@ -18,6 +18,8 @@ #include "driver/spi_master.h" #include "esp_private/periph_ctrl.h" #include "esp_private/spi_common_internal.h" +#include "esp_private/spi_share_hw_ctrl.h" +#include "esp_private/esp_cache_private.h" #include "hal/spi_hal.h" #include "hal/gpio_hal.h" #if CONFIG_IDF_TARGET_ESP32 @@ -25,14 +27,6 @@ #endif #if SOC_GDMA_SUPPORTED #include "esp_private/gdma.h" -#include "hal/cache_hal.h" -#include "hal/cache_ll.h" -#endif - -#if !SOC_RCC_IS_INDEPENDENT -#define SPI_COMMON_RCC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC() -#else -#define SPI_COMMON_RCC_CLOCK_ATOMIC() #endif static const char *SPI_TAG = "spi"; @@ -48,47 +42,50 @@ static const char *SPI_TAG = "spi"; #define SPI_MAIN_BUS_DEFAULT() { \ .host_id = 0, \ .bus_attr = { \ - .tx_dma_chan = 0, \ - .rx_dma_chan = 0, \ .max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE, \ - .dma_desc_num= 0, \ }, \ } #define FUNC_GPIO PIN_FUNC_GPIO - typedef struct { int host_id; spi_destroy_func_t destroy_func; void* destroy_arg; spi_bus_attr_t bus_attr; + spi_dma_ctx_t *dma_ctx; #if SOC_GDMA_SUPPORTED gdma_channel_handle_t tx_channel; gdma_channel_handle_t rx_channel; #endif } spicommon_bus_context_t; -//Periph 1 is 'claimed' by SPI flash code. -static atomic_bool spi_periph_claimed[SOC_SPI_PERIPH_NUM] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false), -#if (SOC_SPI_PERIPH_NUM >= 3) -ATOMIC_VAR_INIT(false), -#endif -#if (SOC_SPI_PERIPH_NUM >= 4) -ATOMIC_VAR_INIT(false), -#endif -}; - -static const char* spi_claiming_func[3] = {NULL, NULL, NULL}; static spicommon_bus_context_t s_mainbus = SPI_MAIN_BUS_DEFAULT(); static spicommon_bus_context_t* bus_ctx[SOC_SPI_PERIPH_NUM] = {&s_mainbus}; -#if !SOC_GDMA_SUPPORTED +#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS +/* The lock for the share SPI1 bus is registered here in a constructor due to need to access the context + This way we are able to decouple the SPI-flash driver from the spi-master driver */ +static __attribute__((constructor)) void spi_bus_lock_init_main_bus(void) +{ + /* Initialize bus context about the main SPI bus lock, called during chip startup. */ + spi_bus_main_set_lock(g_main_spi_bus_lock); +} +#endif + +#if SOC_GDMA_SUPPORTED +//NOTE!! If both A and B are not defined, '#if (A==B)' is true, because GCC use 0 stand for undefined symbol +#if defined(SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI) +#define SPI_GDMA_NEW_CHANNEL gdma_new_axi_channel +#elif defined(SOC_GDMA_BUS_AHB) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AHB) +#define SPI_GDMA_NEW_CHANNEL gdma_new_ahb_channel +#endif + +#else //Each bit stands for 1 dma channel, BIT(0) should be used for SPI1 static uint8_t spi_dma_chan_enabled = 0; static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED; -#endif //#if !SOC_GDMA_SUPPORTED - +#endif //!SOC_GDMA_SUPPORTED static inline bool is_valid_host(spi_host_device_t host) { @@ -99,42 +96,6 @@ static inline bool is_valid_host(spi_host_device_t host) #endif } -//----------------------------------------------------------alloc spi periph-------------------------------------------------------// -//Returns true if this peripheral is successfully claimed, false if otherwise. -bool spicommon_periph_claim(spi_host_device_t host, const char* source) -{ - bool false_var = false; - bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &false_var, true); - if (ret) { - spi_claiming_func[host] = source; - SPI_COMMON_RCC_CLOCK_ATOMIC() { - spi_ll_enable_bus_clock(host, true); - spi_ll_reset_register(host); - } - } else { - ESP_EARLY_LOGE(SPI_TAG, "SPI%d already claimed by %s.", host+1, spi_claiming_func[host]); - } - return ret; -} - -bool spicommon_periph_in_use(spi_host_device_t host) -{ - return atomic_load(&spi_periph_claimed[host]); -} - -//Returns true if this peripheral is successfully freed, false if otherwise. -bool spicommon_periph_free(spi_host_device_t host) -{ - bool true_var = true; - bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &true_var, false); - if (ret) { - SPI_COMMON_RCC_CLOCK_ATOMIC() { - spi_ll_enable_bus_clock(host, false); - } - } - return ret; -} - int spicommon_irqsource_for_host(spi_host_device_t host) { return spi_periph_signal[host].irq; @@ -202,7 +163,7 @@ static void connect_spi_and_dma(spi_host_device_t host, int dma_chan) #endif } -static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_chan, spi_dma_ctx_t *dma_ctx) { assert(is_valid_host(host_id)); #if CONFIG_IDF_TARGET_ESP32 @@ -217,7 +178,7 @@ static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_ch if (dma_chan == SPI_DMA_CH_AUTO) { #if CONFIG_IDF_TARGET_ESP32 - for (int i = 1; i < SOC_SPI_DMA_CHAN_NUM+1; i++) { + for (int i = 1; i < SOC_SPI_DMA_CHAN_NUM + 1; i++) { success = claim_dma_chan(i, &actual_dma_chan); if (success) { break; @@ -232,60 +193,66 @@ static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_ch } //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same - *out_actual_tx_dma_chan = actual_dma_chan; - *out_actual_rx_dma_chan = actual_dma_chan; + dma_ctx->tx_dma_chan.chan_id = actual_dma_chan; + dma_ctx->rx_dma_chan.chan_id = actual_dma_chan; + dma_ctx->tx_dma_chan.host_id = host_id; + dma_ctx->rx_dma_chan.host_id = host_id; + dma_ctx->tx_dma_chan.dir = DMA_CHANNEL_DIRECTION_TX; + dma_ctx->rx_dma_chan.dir = DMA_CHANNEL_DIRECTION_RX; if (!success) { SPI_CHECK(false, "no available dma channel", ESP_ERR_NOT_FOUND); } + connect_spi_and_dma(host_id, actual_dma_chan); - connect_spi_and_dma(host_id, *out_actual_tx_dma_chan); - + spi_dma_enable_burst(dma_ctx->tx_dma_chan, true, true); + spi_dma_enable_burst(dma_ctx->rx_dma_chan, true, true); return ret; } #else //SOC_GDMA_SUPPORTED -static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_chan, spi_dma_ctx_t *dma_ctx) { assert(is_valid_host(host_id)); assert(dma_chan == SPI_DMA_CH_AUTO); - esp_err_t ret = ESP_OK; - spicommon_bus_context_t *ctx = bus_ctx[host_id]; if (dma_chan == SPI_DMA_CH_AUTO) { gdma_channel_alloc_config_t tx_alloc_config = { .flags.reserve_sibling = 1, .direction = GDMA_CHANNEL_DIRECTION_TX, }; - ESP_RETURN_ON_ERROR(SPI_GDMA_NEW_CHANNEL(&tx_alloc_config, &ctx->tx_channel), SPI_TAG, "alloc gdma tx failed"); + ESP_RETURN_ON_ERROR(SPI_GDMA_NEW_CHANNEL(&tx_alloc_config, &dma_ctx->tx_dma_chan), SPI_TAG, "alloc gdma tx failed"); gdma_channel_alloc_config_t rx_alloc_config = { .direction = GDMA_CHANNEL_DIRECTION_RX, - .sibling_chan = ctx->tx_channel, + .sibling_chan = dma_ctx->tx_dma_chan, }; - ESP_RETURN_ON_ERROR(SPI_GDMA_NEW_CHANNEL(&rx_alloc_config, &ctx->rx_channel), SPI_TAG, "alloc gdma rx failed"); + ESP_RETURN_ON_ERROR(SPI_GDMA_NEW_CHANNEL(&rx_alloc_config, &dma_ctx->rx_dma_chan), SPI_TAG, "alloc gdma rx failed"); if (host_id == SPI2_HOST) { - gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); - gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); + gdma_connect(dma_ctx->tx_dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); + gdma_connect(dma_ctx->rx_dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); } #if (SOC_SPI_PERIPH_NUM >= 3) else if (host_id == SPI3_HOST) { - gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); - gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); + gdma_connect(dma_ctx->tx_dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); + gdma_connect(dma_ctx->rx_dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); } #endif - gdma_get_channel_id(ctx->tx_channel, (int *)out_actual_tx_dma_chan); - gdma_get_channel_id(ctx->rx_channel, (int *)out_actual_rx_dma_chan); + gdma_transfer_ability_t ability = { + .psram_trans_align = 0, // fall back to use the same size of the psram data cache line size + .sram_trans_align = 4, + }; + ESP_RETURN_ON_ERROR(gdma_set_transfer_ability(dma_ctx->tx_dma_chan, &ability), SPI_TAG, "set gdma tx transfer ability failed"); + ESP_RETURN_ON_ERROR(gdma_set_transfer_ability(dma_ctx->rx_dma_chan, &ability), SPI_TAG, "set gdma rx transfer ability failed"); } - return ret; } #endif //#if !SOC_GDMA_SUPPORTED -esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, spi_dma_ctx_t **out_dma_ctx) { assert(is_valid_host(host_id)); #if CONFIG_IDF_TARGET_ESP32 @@ -295,103 +262,88 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma #endif esp_err_t ret = ESP_OK; - uint32_t actual_tx_dma_chan = 0; - uint32_t actual_rx_dma_chan = 0; - spicommon_bus_context_t *ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t)); - if (!ctx) { + spi_dma_ctx_t *dma_ctx = (spi_dma_ctx_t *)calloc(1, sizeof(spi_dma_ctx_t)); + if (!dma_ctx) { ret = ESP_ERR_NO_MEM; goto cleanup; } - bus_ctx[host_id] = ctx; - ctx->host_id = host_id; - ret = alloc_dma_chan(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + ret = alloc_dma_chan(host_id, dma_chan, dma_ctx); if (ret != ESP_OK) { goto cleanup; } - ctx->bus_attr.tx_dma_chan = actual_tx_dma_chan; - ctx->bus_attr.rx_dma_chan = actual_rx_dma_chan; - *out_actual_tx_dma_chan = actual_tx_dma_chan; - *out_actual_rx_dma_chan = actual_rx_dma_chan; - + *out_dma_ctx = dma_ctx; return ret; cleanup: - free(ctx); - ctx = NULL; + free(dma_ctx); return ret; } -#if SOC_GDMA_SUPPORTED -esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction) +esp_err_t spicommon_dma_desc_alloc(spi_dma_ctx_t *dma_ctx, int cfg_max_sz, int *actual_max_sz) { - assert(is_valid_host(host_id)); - ESP_RETURN_ON_FALSE((gdma_direction == GDMA_CHANNEL_DIRECTION_TX) || \ - (gdma_direction == GDMA_CHANNEL_DIRECTION_RX), \ - ESP_ERR_INVALID_ARG, SPI_TAG, "GDMA Direction not supported!"); - - - if (gdma_direction == GDMA_CHANNEL_DIRECTION_TX) { - *gdma_handle = bus_ctx[host_id]->tx_channel; + int dma_desc_ct = (cfg_max_sz + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; + if (dma_desc_ct == 0) { + dma_desc_ct = 1; //default to 4k when max is not given } - if (gdma_direction == GDMA_CHANNEL_DIRECTION_RX) { - *gdma_handle = bus_ctx[host_id]->rx_channel; + + dma_ctx->dmadesc_tx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); + dma_ctx->dmadesc_rx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); + if (dma_ctx->dmadesc_tx == NULL || dma_ctx->dmadesc_rx == NULL) { + if (dma_ctx->dmadesc_tx) { + free(dma_ctx->dmadesc_tx); + dma_ctx->dmadesc_tx = NULL; + } + if (dma_ctx->dmadesc_rx) { + free(dma_ctx->dmadesc_rx); + dma_ctx->dmadesc_rx = NULL; + } + return ESP_ERR_NO_MEM; } + dma_ctx->dma_desc_num = dma_desc_ct; + *actual_max_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; return ESP_OK; } -#endif // SOC_GDMA_SUPPORTED - //----------------------------------------------------------free dma periph-------------------------------------------------------// -static esp_err_t dma_chan_free(spi_host_device_t host_id) +esp_err_t spicommon_dma_chan_free(spi_dma_ctx_t *dma_ctx) { - assert(is_valid_host(host_id)); + assert(dma_ctx); - spicommon_bus_context_t *ctx = bus_ctx[host_id]; #if !SOC_GDMA_SUPPORTED //On ESP32S2, each SPI controller has its own DMA channel - int dma_chan = ctx->bus_attr.tx_dma_chan; + int dma_chan = dma_ctx->tx_dma_chan.chan_id; assert(spi_dma_chan_enabled & BIT(dma_chan)); portENTER_CRITICAL(&spi_dma_spinlock); spi_dma_chan_enabled &= ~BIT(dma_chan); #if SPI_LL_DMA_SHARED - PERIPH_RCC_RELEASE_ATOMIC(get_dma_periph(dma_chan), ref_count) { - if (ref_count == 0) { - spi_dma_ll_enable_bus_clock(host_id, false); - } + PERIPH_RCC_RELEASE_ATOMIC(get_dma_periph(dma_chan), ref_count) { + if (ref_count == 0) { + spi_dma_ll_enable_bus_clock(dma_ctx->tx_dma_chan.host_id, false); } + } #else - SPI_COMMON_RCC_CLOCK_ATOMIC() { - spi_dma_ll_enable_bus_clock(host_id, false); - } + SPI_COMMON_RCC_CLOCK_ATOMIC() { + spi_dma_ll_enable_bus_clock(dma_ctx->tx_dma_chan.host_id, false); + } #endif portEXIT_CRITICAL(&spi_dma_spinlock); #else //SOC_GDMA_SUPPORTED - if (ctx->rx_channel) { - gdma_disconnect(ctx->rx_channel); - gdma_del_channel(ctx->rx_channel); + if (dma_ctx->rx_dma_chan) { + gdma_disconnect(dma_ctx->rx_dma_chan); + gdma_del_channel(dma_ctx->rx_dma_chan); } - if (ctx->tx_channel) { - gdma_disconnect(ctx->tx_channel); - gdma_del_channel(ctx->tx_channel); + if (dma_ctx->tx_dma_chan) { + gdma_disconnect(dma_ctx->tx_dma_chan); + gdma_del_channel(dma_ctx->tx_dma_chan); } #endif + free(dma_ctx); return ESP_OK; } -esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id) -{ - assert(is_valid_host(host_id)); - - esp_err_t ret = dma_chan_free(host_id); - free(bus_ctx[host_id]); - bus_ctx[host_id] = NULL; - - return ret; -} - //----------------------------------------------------------IO general-------------------------------------------------------// #if SOC_SPI_SUPPORT_OCT static bool check_iomux_pins_oct(spi_host_device_t host, const spi_bus_config_t* bus_config) @@ -400,10 +352,12 @@ static bool check_iomux_pins_oct(spi_host_device_t host, const spi_bus_config_t* return false; } int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num, - bus_config->sclk_io_num, bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num}; + bus_config->sclk_io_num, bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num + }; int io_mux_nums[] = {SPI2_IOMUX_PIN_NUM_MOSI_OCT, SPI2_IOMUX_PIN_NUM_MISO_OCT, SPI2_IOMUX_PIN_NUM_WP_OCT, SPI2_IOMUX_PIN_NUM_HD_OCT, - SPI2_IOMUX_PIN_NUM_CLK_OCT, SPI2_IOMUX_PIN_NUM_IO4_OCT, SPI2_IOMUX_PIN_NUM_IO5_OCT, SPI2_IOMUX_PIN_NUM_IO6_OCT, SPI2_IOMUX_PIN_NUM_IO7_OCT}; - for (size_t i = 0; i < sizeof(io_nums)/sizeof(io_nums[0]); i++) { + SPI2_IOMUX_PIN_NUM_CLK_OCT, SPI2_IOMUX_PIN_NUM_IO4_OCT, SPI2_IOMUX_PIN_NUM_IO5_OCT, SPI2_IOMUX_PIN_NUM_IO6_OCT, SPI2_IOMUX_PIN_NUM_IO7_OCT + }; + for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) { if (io_nums[i] >= 0 && io_nums[i] != io_mux_nums[i]) { return false; } @@ -414,24 +368,24 @@ static bool check_iomux_pins_oct(spi_host_device_t host, const spi_bus_config_t* static bool check_iomux_pins_quad(spi_host_device_t host, const spi_bus_config_t* bus_config) { - if (bus_config->sclk_io_num>=0 && - bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) { + if (bus_config->sclk_io_num >= 0 && + bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) { return false; } - if (bus_config->quadwp_io_num>=0 && - bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) { + if (bus_config->quadwp_io_num >= 0 && + bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) { return false; } - if (bus_config->quadhd_io_num>=0 && - bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) { + if (bus_config->quadhd_io_num >= 0 && + bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) { return false; } if (bus_config->mosi_io_num >= 0 && - bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) { + bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) { return false; } - if (bus_config->miso_io_num>=0 && - bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) { + if (bus_config->miso_io_num >= 0 && + bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) { return false; } return true; @@ -454,11 +408,13 @@ static void bus_iomux_pins_set_oct(spi_host_device_t host, const spi_bus_config_ { assert(host == SPI2_HOST); int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num, - bus_config->sclk_io_num, bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num}; + bus_config->sclk_io_num, bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num + }; int io_signals[] = {spi_periph_signal[host].spid_in, spi_periph_signal[host].spiq_in, spi_periph_signal[host].spiwp_in, - spi_periph_signal[host].spihd_in,spi_periph_signal[host].spiclk_in, spi_periph_signal[host].spid4_out, - spi_periph_signal[host].spid5_out, spi_periph_signal[host].spid6_out, spi_periph_signal[host].spid7_out}; - for (size_t i = 0; i < sizeof(io_nums)/sizeof(io_nums[0]); i++) { + spi_periph_signal[host].spihd_in, spi_periph_signal[host].spiclk_in, spi_periph_signal[host].spid4_out, + spi_periph_signal[host].spid5_out, spi_periph_signal[host].spid6_out, spi_periph_signal[host].spid7_out + }; + for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) { if (io_nums[i] > 0) { gpio_iomux_in(io_nums[i], io_signals[i]); // In Octal mode use function channel 2 @@ -526,15 +482,15 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf bool miso_need_output; bool mosi_need_output; bool sclk_need_output; - if ((flags&SPICOMMON_BUSFLAG_MASTER) != 0) { + if ((flags & SPICOMMON_BUSFLAG_MASTER) != 0) { //initial for master - miso_need_output = ((flags&SPICOMMON_BUSFLAG_DUAL) != 0) ? true : false; + miso_need_output = ((flags & SPICOMMON_BUSFLAG_DUAL) != 0) ? true : false; mosi_need_output = true; sclk_need_output = true; } else { //initial for slave miso_need_output = true; - mosi_need_output = ((flags&SPICOMMON_BUSFLAG_DUAL) != 0) ? true : false; + mosi_need_output = ((flags & SPICOMMON_BUSFLAG_DUAL) != 0) ? true : false; sclk_need_output = false; } @@ -542,14 +498,14 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf const bool hd_need_output = true; //check pin capabilities - if (bus_config->sclk_io_num>=0) { + if (bus_config->sclk_io_num >= 0) { temp_flag |= SPICOMMON_BUSFLAG_SCLK; SPI_CHECK_PIN(bus_config->sclk_io_num, "sclk", sclk_need_output); } - if (bus_config->quadwp_io_num>=0) { + if (bus_config->quadwp_io_num >= 0) { SPI_CHECK_PIN(bus_config->quadwp_io_num, "wp", wp_need_output); } - if (bus_config->quadhd_io_num>=0) { + if (bus_config->quadhd_io_num >= 0) { SPI_CHECK_PIN(bus_config->quadhd_io_num, "hd", hd_need_output); } #if SOC_SPI_SUPPORT_OCT @@ -576,7 +532,9 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #endif //SOC_SPI_SUPPORT_OCT //set flags for QUAD mode according to the existence of wp and hd - if (bus_config->quadhd_io_num >= 0 && bus_config->quadwp_io_num >= 0) temp_flag |= SPICOMMON_BUSFLAG_WPHD; + if (bus_config->quadhd_io_num >= 0 && bus_config->quadwp_io_num >= 0) { + temp_flag |= SPICOMMON_BUSFLAG_WPHD; + } if (bus_config->mosi_io_num >= 0) { temp_flag |= SPICOMMON_BUSFLAG_MOSI; SPI_CHECK_PIN(bus_config->mosi_io_num, "mosi", mosi_need_output); @@ -586,8 +544,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf SPI_CHECK_PIN(bus_config->miso_io_num, "miso", miso_need_output); } //set flags for DUAL mode according to output-capability of MOSI and MISO pins. - if ( (bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) && - (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num)) ) { + if ((bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) && + (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num))) { temp_flag |= SPICOMMON_BUSFLAG_DUAL; } @@ -603,7 +561,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf missing_flag &= ~SPICOMMON_BUSFLAG_MASTER;//don't check this flag if (missing_flag != 0) { - //check pins existence + //check pins existence if (missing_flag & SPICOMMON_BUSFLAG_SCLK) { ESP_LOGE(SPI_TAG, "sclk pin required."); } @@ -633,13 +591,13 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf if (use_iomux) { //All SPI iomux pin selections resolve to 1, so we put that here instead of trying to figure //out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway. - ESP_LOGD(SPI_TAG, "SPI%d use iomux pins.", host+1); + ESP_LOGD(SPI_TAG, "SPI%d use iomux pins.", host + 1); bus_iomux_pins_set(host, bus_config); } else { //Use GPIO matrix - ESP_LOGD(SPI_TAG, "SPI%d use gpio matrix.", host+1); + ESP_LOGD(SPI_TAG, "SPI%d use gpio matrix.", host + 1); if (bus_config->mosi_io_num >= 0) { - if (mosi_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) { + if (mosi_need_output || (temp_flag & SPICOMMON_BUSFLAG_DUAL)) { gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT_OUTPUT); esp_rom_gpio_connect_out_signal(bus_config->mosi_io_num, spi_periph_signal[host].spid_out, false, false); } else { @@ -652,7 +610,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO); } if (bus_config->miso_io_num >= 0) { - if (miso_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) { + if (miso_need_output || (temp_flag & SPICOMMON_BUSFLAG_DUAL)) { gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT_OUTPUT); esp_rom_gpio_connect_out_signal(bus_config->miso_io_num, spi_periph_signal[host].spiq_out, false, false); } else { @@ -699,9 +657,10 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf if ((flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL) { int io_nums[] = {bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num}; uint8_t io_signals[4][2] = {{spi_periph_signal[host].spid4_out, spi_periph_signal[host].spid4_in}, - {spi_periph_signal[host].spid5_out, spi_periph_signal[host].spid5_in}, - {spi_periph_signal[host].spid6_out, spi_periph_signal[host].spid6_in}, - {spi_periph_signal[host].spid7_out, spi_periph_signal[host].spid7_in}}; + {spi_periph_signal[host].spid5_out, spi_periph_signal[host].spid5_in}, + {spi_periph_signal[host].spid6_out, spi_periph_signal[host].spid6_in}, + {spi_periph_signal[host].spid7_out, spi_periph_signal[host].spid7_in} + }; for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) { if (io_nums[i] >= 0) { gpio_set_direction(io_nums[i], GPIO_MODE_INPUT_OUTPUT); @@ -717,7 +676,9 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #endif //SOC_SPI_SUPPORT_OCT } - if (flags_o) *flags_o = temp_flag; + if (flags_o) { + *flags_o = temp_flag; + } return ESP_OK; } @@ -730,7 +691,7 @@ esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg) bus_cfg->quadwp_io_num, bus_cfg->quadhd_io_num, }; - for (int i = 0; i < sizeof(pin_array)/sizeof(int); i ++) { + for (int i = 0; i < sizeof(pin_array) / sizeof(int); i ++) { const int io = pin_array[i]; if (GPIO_IS_VALID_GPIO(io)) { gpio_reset_pin(io); @@ -753,7 +714,9 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, } else { gpio_set_direction(cs_io_num, GPIO_MODE_INPUT); } - if (cs_num == 0) esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false); + if (cs_num == 0) { + esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false); + } PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]); gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO); } @@ -776,7 +739,6 @@ bool spicommon_bus_using_iomux(spi_host_device_t host) return true; } - void spi_bus_main_set_lock(spi_bus_lock_handle_t lock) { bus_ctx[0]->bus_attr.lock = lock; @@ -793,21 +755,19 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * esp_err_t err = ESP_OK; spicommon_bus_context_t *ctx = NULL; spi_bus_attr_t *bus_attr = NULL; - uint32_t actual_tx_dma_chan = 0; - uint32_t actual_rx_dma_chan = 0; SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_ctx[host_id] == NULL, "SPI bus already initialized.", ESP_ERR_INVALID_STATE); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif CONFIG_IDF_TARGET_ESP32S2 - SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif - SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); + SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM - SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM)==0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_MASTER_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG); + SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_MASTER_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG); #endif bool spi_chan_claimed = spicommon_periph_claim(host_id, "spi master"); @@ -827,33 +787,22 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * if (dma_chan != SPI_DMA_DISABLED) { bus_attr->dma_enabled = 1; - err = alloc_dma_chan(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + err = spicommon_dma_chan_alloc(host_id, dma_chan, &ctx->dma_ctx); if (err != ESP_OK) { goto cleanup; } - bus_attr->tx_dma_chan = actual_tx_dma_chan; - bus_attr->rx_dma_chan = actual_rx_dma_chan; - - int dma_desc_ct = (bus_config->max_transfer_sz + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; - if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given - - bus_attr->max_transfer_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; - bus_attr->dmadesc_tx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); - bus_attr->dmadesc_rx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); - if (bus_attr->dmadesc_tx == NULL || bus_attr->dmadesc_rx == NULL) { - err = ESP_ERR_NO_MEM; + err = spicommon_dma_desc_alloc(ctx->dma_ctx, bus_config->max_transfer_sz, &bus_attr->max_transfer_sz); + if (err != ESP_OK) { goto cleanup; } - bus_attr->dma_desc_num = dma_desc_ct; #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - bus_attr->internal_mem_align_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); + esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, (size_t *)&bus_attr->internal_mem_align_size); #else bus_attr->internal_mem_align_size = 4; #endif } else { bus_attr->dma_enabled = 0; bus_attr->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE; - bus_attr->dma_desc_num = 0; } spi_bus_lock_config_t lock_config = { @@ -867,7 +816,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * #ifdef CONFIG_PM_ENABLE err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_master", - &bus_attr->pm_lock); + &bus_attr->pm_lock); if (err != ESP_OK) { goto cleanup; } @@ -888,12 +837,11 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * if (bus_attr->lock) { spi_bus_deinit_lock(bus_attr->lock); } - free(bus_attr->dmadesc_tx); - free(bus_attr->dmadesc_rx); - bus_attr->dmadesc_tx = NULL; - bus_attr->dmadesc_rx = NULL; - if (bus_attr->dma_enabled) { - dma_chan_free(host_id); + if (ctx->dma_ctx) { + free(ctx->dma_ctx->dmadesc_tx); + free(ctx->dma_ctx->dmadesc_rx); + spicommon_dma_chan_free(ctx->dma_ctx); + ctx->dma_ctx = NULL; } } spicommon_periph_free(host_id); @@ -904,11 +852,22 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * const spi_bus_attr_t* spi_bus_get_attr(spi_host_device_t host_id) { - if (bus_ctx[host_id] == NULL) return NULL; + if (bus_ctx[host_id] == NULL) { + return NULL; + } return &bus_ctx[host_id]->bus_attr; } +const spi_dma_ctx_t* spi_bus_get_dma_ctx(spi_host_device_t host_id) +{ + if (bus_ctx[host_id] == NULL) { + return NULL; + } + + return bus_ctx[host_id]->dma_ctx; +} + esp_err_t spi_bus_free(spi_host_device_t host_id) { if (bus_ctx[host_id] == NULL) { @@ -922,19 +881,17 @@ esp_err_t spi_bus_free(spi_host_device_t host_id) if (ctx->destroy_func) { err = ctx->destroy_func(ctx->destroy_arg); } - spicommon_bus_free_io_cfg(&bus_attr->bus_cfg); #ifdef CONFIG_PM_ENABLE esp_pm_lock_delete(bus_attr->pm_lock); #endif spi_bus_deinit_lock(bus_attr->lock); - free(bus_attr->dmadesc_rx); - free(bus_attr->dmadesc_tx); - bus_attr->dmadesc_tx = NULL; - bus_attr->dmadesc_rx = NULL; - if (bus_attr->dma_enabled > 0) { - dma_chan_free(host_id); + if (ctx->dma_ctx) { + free(ctx->dma_ctx->dmadesc_tx); + free(ctx->dma_ctx->dmadesc_rx); + spicommon_dma_chan_free(ctx->dma_ctx); + ctx->dma_ctx = NULL; } spicommon_periph_free(host_id); free(ctx); @@ -950,7 +907,6 @@ esp_err_t spi_bus_register_destroy_func(spi_host_device_t host_id, return ESP_OK; } - /* Code for workaround for DMA issue in ESP32 v0/v1 silicon */ @@ -967,7 +923,7 @@ bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t int otherchan = (dmachan == 1) ? 2 : 1; bool ret; portENTER_CRITICAL_ISR(&dmaworkaround_mux); - if (dmaworkaround_channels_busy[otherchan-1]) { + if (dmaworkaround_channels_busy[otherchan - 1]) { //Other channel is busy. Call back when it's done. dmaworkaround_cb = cb; dmaworkaround_cb_arg = arg; @@ -975,7 +931,7 @@ bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t ret = false; } else { //Reset DMA - periph_module_reset( PERIPH_SPI_DMA_MODULE ); + periph_module_reset(PERIPH_SPI_DMA_MODULE); ret = true; } portEXIT_CRITICAL_ISR(&dmaworkaround_mux); @@ -990,10 +946,10 @@ bool IRAM_ATTR spicommon_dmaworkaround_reset_in_progress(void) void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan) { portENTER_CRITICAL_ISR(&dmaworkaround_mux); - dmaworkaround_channels_busy[dmachan-1] = 0; + dmaworkaround_channels_busy[dmachan - 1] = 0; if (dmaworkaround_waiting_for_chan == dmachan) { //Reset DMA - periph_module_reset( PERIPH_SPI_DMA_MODULE ); + periph_module_reset(PERIPH_SPI_DMA_MODULE); dmaworkaround_waiting_for_chan = 0; //Call callback dmaworkaround_cb(dmaworkaround_cb_arg); @@ -1005,7 +961,7 @@ void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan) void IRAM_ATTR spicommon_dmaworkaround_transfer_active(int dmachan) { portENTER_CRITICAL_ISR(&dmaworkaround_mux); - dmaworkaround_channels_busy[dmachan-1] = 1; + dmaworkaround_channels_busy[dmachan - 1] = 1; portEXIT_CRITICAL_ISR(&dmaworkaround_mux); } #endif //#if CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_driver_spi/src/gpspi/spi_dma.c b/components/esp_driver_spi/src/gpspi/spi_dma.c new file mode 100644 index 00000000000..4d258602e6f --- /dev/null +++ b/components/esp_driver_spi/src/gpspi/spi_dma.c @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_private/spi_dma.h" +#include "hal/spi_ll.h" + +#if !SOC_GDMA_SUPPORTED +void spi_dma_enable_burst(spi_dma_chan_handle_t chan_handle, bool data_burst, bool desc_burst) +{ + spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); + + if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { + spi_dma_ll_tx_enable_burst_data(spi_dma, chan_handle.chan_id, data_burst); + spi_dma_ll_tx_enable_burst_desc(spi_dma, chan_handle.chan_id, desc_burst); + } else { + spi_dma_ll_rx_enable_burst_data(spi_dma, chan_handle.chan_id, data_burst); + spi_dma_ll_rx_enable_burst_desc(spi_dma, chan_handle.chan_id, desc_burst); + } +} + +/************************************* IRAM CONTEXT **************************************/ + +void spi_dma_reset(spi_dma_chan_handle_t chan_handle) +{ + spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); + + if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { + spi_dma_ll_tx_reset(spi_dma, chan_handle.chan_id); + } else { + spi_dma_ll_rx_reset(spi_dma, chan_handle.chan_id); + } +} + +void spi_dma_start(spi_dma_chan_handle_t chan_handle, void *addr) +{ + spi_dma_dev_t *spi_dma = SPI_LL_GET_HW(chan_handle.host_id); + + if (chan_handle.dir == DMA_CHANNEL_DIRECTION_TX) { + spi_dma_ll_tx_start(spi_dma, chan_handle.chan_id, (lldesc_t *)addr); + } else { + spi_dma_ll_rx_start(spi_dma, chan_handle.chan_id, (lldesc_t *)addr); + } +} +#endif diff --git a/components/driver/spi/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c similarity index 89% rename from components/driver/spi/gpspi/spi_master.c rename to components/esp_driver_spi/src/gpspi/spi_master.c index a0692ddfb09..5ae4d1a803d 100644 --- a/components/driver/spi/gpspi/spi_master.c +++ b/components/esp_driver_spi/src/gpspi/spi_master.c @@ -137,7 +137,7 @@ typedef struct spi_device_t spi_device_t; typedef struct { spi_transaction_t *trans; const uint32_t *buffer_to_send; //equals to tx_data, if SPI_TRANS_USE_RXDATA is applied; otherwise if original buffer wasn't in DMA-capable memory, this gets the address of a temporary buffer that is; - //otherwise sets to the original buffer or NULL if no buffer is assigned. + //otherwise sets to the original buffer or NULL if no buffer is assigned. uint32_t *buffer_to_rcv; // similar to buffer_to_send } spi_trans_priv_t; @@ -149,6 +149,7 @@ typedef struct { spi_trans_priv_t cur_trans_buf; int cur_cs; //current device doing transaction const spi_bus_attr_t* bus_attr; + const spi_dma_ctx_t *dma_ctx; /** * the bus is permanently controlled by a device until `spi_bus_release_bus`` is called. Otherwise @@ -221,6 +222,7 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id) esp_err_t err = ESP_OK; const spi_bus_attr_t* bus_attr = spi_bus_get_attr(host_id); + const spi_dma_ctx_t *dma_ctx = spi_bus_get_dma_ctx(host_id); SPI_CHECK(bus_attr != NULL, "host_id not initialized", ESP_ERR_INVALID_STATE); SPI_CHECK(bus_attr->lock != NULL, "SPI Master cannot attach to bus. (Check CONFIG_SPI_FLASH_SHARE_SPI1_BUS)", ESP_ERR_INVALID_ARG); // spihost contains atomic variables, which should not be put in PSRAM @@ -236,6 +238,7 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id) .polling = false, .device_acquiring_lock = NULL, .bus_attr = bus_attr, + .dma_ctx = dma_ctx, }; // interrupts are not allowed on SPI1 bus @@ -259,17 +262,24 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id) } //assign the SPI, RX DMA and TX DMA peripheral registers beginning address - spi_hal_config_t hal_config = { + spi_hal_config_t hal_config = { .dma_enabled = bus_attr->dma_enabled, }; + if (bus_attr->dma_enabled && dma_ctx) { + hal_config.dmadesc_tx = dma_ctx->dmadesc_tx; + hal_config.dmadesc_rx = dma_ctx->dmadesc_rx; + hal_config.dmadesc_n = dma_ctx->dma_desc_num; +#if SOC_GDMA_SUPPORTED + //temporary used for gdma_ll alias in hal layer + gdma_get_channel_id(dma_ctx->tx_dma_chan, (int *)&hal_config.tx_dma_chan); + gdma_get_channel_id(dma_ctx->rx_dma_chan, (int *)&hal_config.rx_dma_chan); +#else //On ESP32-S2 and earlier chips, DMA registers are part of SPI registers. Pass the registers of SPI peripheral to control it. - .dma_in = SPI_LL_GET_HW(host_id), - .dma_out = SPI_LL_GET_HW(host_id), - .dma_enabled = bus_attr->dma_enabled, - .dmadesc_tx = bus_attr->dmadesc_tx, - .dmadesc_rx = bus_attr->dmadesc_rx, - .tx_dma_chan = bus_attr->tx_dma_chan, - .rx_dma_chan = bus_attr->rx_dma_chan, - .dmadesc_n = bus_attr->dma_desc_num, - }; + hal_config.dma_in = SPI_LL_GET_HW(host_id); + hal_config.dma_out = SPI_LL_GET_HW(host_id); + hal_config.tx_dma_chan = dma_ctx->tx_dma_chan.chan_id; + hal_config.rx_dma_chan = dma_ctx->rx_dma_chan.chan_id; +#endif + } + SPI_MASTER_PERI_CLOCK_ATOMIC() { spi_ll_enable_clock(host_id, true); } @@ -305,7 +315,7 @@ static esp_err_t spi_master_deinit_driver(void* arg) SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG); int x; - for (x=0; xdevice[x] == NULL, "not all CSses freed", ESP_ERR_INVALID_STATE); } @@ -326,8 +336,12 @@ void spi_get_timing(bool gpio_is_used, int input_delay_ns, int eff_clk, int* dum int timing_miso_delay; spi_hal_cal_timing(APB_CLK_FREQ, eff_clk, gpio_is_used, input_delay_ns, &timing_dummy, &timing_miso_delay); - if (dummy_o) *dummy_o = timing_dummy; - if (cycles_remain_o) *cycles_remain_o = timing_miso_delay; + if (dummy_o) { + *dummy_o = timing_dummy; + } + if (cycles_remain_o) { + *cycles_remain_o = timing_miso_delay; + } #else //TODO: IDF-6578 ESP_LOGW(SPI_TAG, "This func temporary not supported for current target!"); @@ -382,7 +396,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa //The hardware looks like it would support this, but actually setting cs_ena_pretrans when transferring in full //duplex mode does absolutely nothing on the ESP32. SPI_CHECK(dev_config->cs_ena_pretrans <= 1 || (dev_config->address_bits == 0 && dev_config->command_bits == 0) || - (dev_config->flags & SPI_DEVICE_HALFDUPLEX), "In full-duplex mode, only support cs pretrans delay = 1 and without address_bits and command_bits", ESP_ERR_INVALID_ARG); + (dev_config->flags & SPI_DEVICE_HALFDUPLEX), "In full-duplex mode, only support cs pretrans delay = 1 and without address_bits and command_bits", ESP_ERR_INVALID_ARG); #endif //Check post_cb status when `SPI_DEVICE_NO_RETURN_RESULT` flag is set. @@ -428,7 +442,9 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa //Allocate memory for device dev = malloc(sizeof(spi_device_t)); - if (dev == NULL) goto nomem; + if (dev == NULL) { + goto nomem; + } memset(dev, 0, sizeof(spi_device_t)); dev->id = freecs; @@ -461,7 +477,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa //save a pointer to device in spi_host_t host->device[freecs] = dev; //save a pointer to host in spi_device_t - dev->host= host; + dev->host = host; //initialise the device specific configuration spi_hal_dev_config_t *hal_dev = &(dev->hal_dev); @@ -486,14 +502,18 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa hal_dev->positive_cs = dev_config->flags & SPI_DEVICE_POSITIVE_CS ? 1 : 0; *handle = dev; - ESP_LOGD(SPI_TAG, "SPI%d: New device added to CS%d, effective clock: %dkHz", host_id+1, freecs, freq/1000); + ESP_LOGD(SPI_TAG, "SPI%d: New device added to CS%d, effective clock: %dkHz", host_id + 1, freecs, freq / 1000); return ESP_OK; nomem: if (dev) { - if (dev->trans_queue) vQueueDelete(dev->trans_queue); - if (dev->ret_queue) vQueueDelete(dev->ret_queue); + if (dev->trans_queue) { + vQueueDelete(dev->trans_queue); + } + if (dev->ret_queue) { + vQueueDelete(dev->ret_queue); + } spi_bus_lock_unregister_dev(dev->dev_lock); } free(dev); @@ -502,13 +522,13 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa esp_err_t spi_bus_remove_device(spi_device_handle_t handle) { - SPI_CHECK(handle!=NULL, "invalid handle", ESP_ERR_INVALID_ARG); + SPI_CHECK(handle != NULL, "invalid handle", ESP_ERR_INVALID_ARG); //These checks aren't exhaustive; another thread could sneak in a transaction inbetween. These are only here to //catch design errors and aren't meant to be triggered during normal operation. - SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); + SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue) == 0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); SPI_CHECK(handle->host->cur_cs == DEV_NUM_MAX || handle->host->device[handle->host->cur_cs] != handle, "Have unfinished transactions", ESP_ERR_INVALID_STATE); if (handle->ret_queue) { - SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); + SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue) == 0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); } #if SOC_SPI_SUPPORT_CLK_RC_FAST @@ -519,11 +539,17 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) //return int spics_io_num = handle->cfg.spics_io_num; - if (spics_io_num >= 0) spicommon_cs_free_io(spics_io_num); + if (spics_io_num >= 0) { + spicommon_cs_free_io(spics_io_num); + } //Kill queues - if (handle->trans_queue) vQueueDelete(handle->trans_queue); - if (handle->ret_queue) vQueueDelete(handle->ret_queue); + if (handle->trans_queue) { + vQueueDelete(handle->trans_queue); + } + if (handle->ret_queue) { + vQueueDelete(handle->ret_queue); + } spi_bus_lock_unregister_dev(handle->dev_lock); assert(handle->host->device[handle->id] == handle); @@ -534,7 +560,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz) { - if ((spi_device_t*)handle == NULL || freq_khz == NULL) { + if ((spi_device_t *)handle == NULL || freq_khz == NULL) { return ESP_ERR_INVALID_ARG; } @@ -568,7 +594,9 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev) static SPI_MASTER_ISR_ATTR spi_device_t *get_acquiring_dev(spi_host_t *host) { spi_bus_lock_dev_handle_t dev_lock = spi_bus_lock_get_acquiring_dev(host->bus_attr->lock); - if (!dev_lock) return NULL; + if (!dev_lock) { + return NULL; + } return host->device[spi_bus_lock_get_dev_id(dev_lock)]; } @@ -615,15 +643,15 @@ static void SPI_MASTER_ISR_ATTR spi_new_trans(spi_device_t *dev, spi_trans_priv_ spi_hal_trans_config_t hal_trans = {}; hal_trans.tx_bitlen = trans->length; hal_trans.rx_bitlen = trans->rxlength; - hal_trans.rcv_buffer = (uint8_t*)host->cur_trans_buf.buffer_to_rcv; - hal_trans.send_buffer = (uint8_t*)host->cur_trans_buf.buffer_to_send; + hal_trans.rcv_buffer = (uint8_t*)trans_buf->buffer_to_rcv; + hal_trans.send_buffer = (uint8_t*)trans_buf->buffer_to_send; hal_trans.cmd = trans->cmd; hal_trans.addr = trans->addr; hal_trans.cs_keep_active = (trans->flags & SPI_TRANS_CS_KEEP_ACTIVE) ? 1 : 0; //Set up OIO/QIO/DIO if needed hal_trans.line_mode.data_lines = (trans->flags & SPI_TRANS_MODE_DIO) ? 2 : - (trans->flags & SPI_TRANS_MODE_QIO) ? 4 : 1; + (trans->flags & SPI_TRANS_MODE_QIO) ? 4 : 1; #if SOC_SPI_SUPPORT_OCT if (trans->flags & SPI_TRANS_MODE_OCT) { hal_trans.line_mode.data_lines = 8; @@ -652,7 +680,9 @@ static void SPI_MASTER_ISR_ATTR spi_new_trans(spi_device_t *dev, spi_trans_priv_ spi_hal_prepare_data(hal, hal_dev, &hal_trans); //Call pre-transmission callback, if any - if (dev->cfg.pre_cb) dev->cfg.pre_cb(trans); + if (dev->cfg.pre_cb) { + dev->cfg.pre_cb(trans); + } //Kick off transfer spi_hal_user_start(hal); } @@ -666,7 +696,9 @@ static void SPI_MASTER_ISR_ATTR spi_post_trans(spi_host_t *host) spi_hal_fetch_result(&host->hal); //Call post-transaction callback, if any spi_device_t* dev = host->device[host->cur_cs]; - if (dev->cfg.post_cb) dev->cfg.post_cb(cur_trans); + if (dev->cfg.post_cb) { + dev->cfg.post_cb(cur_trans); + } host->cur_cs = DEV_NUM_MAX; } @@ -677,6 +709,10 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) BaseType_t do_yield = pdFALSE; spi_host_t *host = (spi_host_t *)arg; const spi_bus_attr_t* bus_attr = host->bus_attr; +#if CONFIG_IDF_TARGET_ESP32 + //only for esp32 dma workaround usage + const spi_dma_ctx_t *dma_ctx = host->dma_ctx; +#endif assert(spi_hal_usr_is_done(&host->hal)); @@ -698,7 +734,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) if (bus_attr->dma_enabled) { #if CONFIG_IDF_TARGET_ESP32 //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same - spicommon_dmaworkaround_idle(bus_attr->tx_dma_chan); + spicommon_dmaworkaround_idle(dma_ctx->tx_dma_chan.chan_id); #endif //#if CONFIG_IDF_TARGET_ESP32 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE //invalidate here to let user access rx data in post_cb if possible @@ -734,7 +770,6 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) spi_bus_lock_handle_t lock = host->bus_attr->lock; BaseType_t trans_found = pdFALSE; - // There should be remaining requests BUS_LOCK_DEBUG_EXECUTE_CHECK(spi_bus_lock_bg_req_exist(lock)); @@ -772,7 +807,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) if (bus_attr->dma_enabled && (cur_trans_buf->buffer_to_rcv || cur_trans_buf->buffer_to_send)) { //mark channel as active, so that the DMA will not be reset by the slave //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same - spicommon_dmaworkaround_transfer_active(bus_attr->tx_dma_chan); + spicommon_dmaworkaround_transfer_active(dma_ctx->tx_dma_chan.chan_id); } #endif //#if CONFIG_IDF_TARGET_ESP32 spi_new_trans(device_to_send, cur_trans_buf); @@ -781,26 +816,28 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) // or resume acquiring device task (if quit due to bus acquiring). } while (!spi_bus_lock_bg_exit(lock, trans_found, &do_yield)); - if (do_yield) portYIELD_FROM_ISR(); + if (do_yield) { + portYIELD_FROM_ISR(); + } } static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handle, spi_transaction_t *trans_desc) { - SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG); + SPI_CHECK(handle != NULL, "invalid dev handle", ESP_ERR_INVALID_ARG); spi_host_t *host = handle->host; const spi_bus_attr_t* bus_attr = host->bus_attr; bool tx_enabled = (trans_desc->flags & SPI_TRANS_USE_TXDATA) || (trans_desc->tx_buffer); bool rx_enabled = (trans_desc->flags & SPI_TRANS_USE_RXDATA) || (trans_desc->rx_buffer); spi_transaction_ext_t *t_ext = (spi_transaction_ext_t *)trans_desc; - bool dummy_enabled = (((trans_desc->flags & SPI_TRANS_VARIABLE_DUMMY)? t_ext->dummy_bits: handle->cfg.dummy_bits) != 0); + bool dummy_enabled = (((trans_desc->flags & SPI_TRANS_VARIABLE_DUMMY) ? t_ext->dummy_bits : handle->cfg.dummy_bits) != 0); bool extra_dummy_enabled = handle->hal_dev.timing_conf.timing_dummy; bool is_half_duplex = ((handle->cfg.flags & SPI_DEVICE_HALFDUPLEX) != 0); //check transmission length - SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_RXDATA)==0 || trans_desc->rxlength <= 32, "SPI_TRANS_USE_RXDATA only available for rxdata transfer <= 32 bits", ESP_ERR_INVALID_ARG); - SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_TXDATA)==0 || trans_desc->length <= 32, "SPI_TRANS_USE_TXDATA only available for txdata transfer <= 32 bits", ESP_ERR_INVALID_ARG); - SPI_CHECK(trans_desc->length <= bus_attr->max_transfer_sz*8, "txdata transfer > host maximum", ESP_ERR_INVALID_ARG); - SPI_CHECK(trans_desc->rxlength <= bus_attr->max_transfer_sz*8, "rxdata transfer > host maximum", ESP_ERR_INVALID_ARG); + SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_RXDATA) == 0 || trans_desc->rxlength <= 32, "SPI_TRANS_USE_RXDATA only available for rxdata transfer <= 32 bits", ESP_ERR_INVALID_ARG); + SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_TXDATA) == 0 || trans_desc->length <= 32, "SPI_TRANS_USE_TXDATA only available for txdata transfer <= 32 bits", ESP_ERR_INVALID_ARG); + SPI_CHECK(trans_desc->length <= bus_attr->max_transfer_sz * 8, "txdata transfer > host maximum", ESP_ERR_INVALID_ARG); + SPI_CHECK(trans_desc->rxlength <= bus_attr->max_transfer_sz * 8, "rxdata transfer > host maximum", ESP_ERR_INVALID_ARG); SPI_CHECK(is_half_duplex || trans_desc->rxlength <= trans_desc->length, "rx length > tx length in full duplex mode", ESP_ERR_INVALID_ARG); //check working mode #if SOC_SPI_SUPPORT_OCT @@ -808,10 +845,10 @@ static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handl SPI_CHECK(!((trans_desc->flags & SPI_TRANS_MODE_OCT) && (handle->cfg.flags & SPI_DEVICE_3WIRE)), "Incompatible when setting to both Octal mode and 3-wire-mode", ESP_ERR_INVALID_ARG); SPI_CHECK(!((trans_desc->flags & SPI_TRANS_MODE_OCT) && !is_half_duplex), "Incompatible when setting to both Octal mode and half duplex mode", ESP_ERR_INVALID_ARG); #endif - SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && (handle->cfg.flags & SPI_DEVICE_3WIRE)), "Incompatible when setting to both multi-line mode and 3-wire-mode", ESP_ERR_INVALID_ARG); - SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && !is_half_duplex), "Incompatible when setting to both multi-line mode and half duplex mode", ESP_ERR_INVALID_ARG); + SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_QIO)) && (handle->cfg.flags & SPI_DEVICE_3WIRE)), "Incompatible when setting to both multi-line mode and 3-wire-mode", ESP_ERR_INVALID_ARG); + SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_QIO)) && !is_half_duplex), "Incompatible when setting to both multi-line mode and half duplex mode", ESP_ERR_INVALID_ARG); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK(!is_half_duplex || !bus_attr->dma_enabled || !rx_enabled || !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_INVALID_ARG ); + SPI_CHECK(!is_half_duplex || !bus_attr->dma_enabled || !rx_enabled || !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_INVALID_ARG); #endif #if !SOC_SPI_HD_BOTH_INOUT_SUPPORTED //On these chips, HW doesn't support using both TX and RX phases when in halfduplex mode @@ -825,8 +862,8 @@ static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handl SPI_CHECK(!is_half_duplex || trans_desc->rxlength != 0 || !rx_enabled, "trans rx_buffer should be NULL and SPI_TRANS_USE_RXDATA should be cleared to skip MISO phase.", ESP_ERR_INVALID_ARG); //In Full duplex mode, default rxlength to be the same as length, if not filled in. // set rxlength to length is ok, even when rx buffer=NULL - if (trans_desc->rxlength==0 && !is_half_duplex) { - trans_desc->rxlength=trans_desc->length; + if (trans_desc->rxlength == 0 && !is_half_duplex) { + trans_desc->rxlength = trans_desc->length; } //Dummy phase is not available when both data out and in are enabled, regardless of FD or HD mode. SPI_CHECK(!tx_enabled || !rx_enabled || !dummy_enabled || !extra_dummy_enabled, "Dummy phase is not available when both data out and in are enabled", ESP_ERR_INVALID_ARG); @@ -846,7 +883,7 @@ static SPI_MASTER_ISR_ATTR void uninstall_priv_desc(spi_trans_priv_t* trans_buf) { spi_transaction_t *trans_desc = trans_buf->trans; if ((void *)trans_buf->buffer_to_send != &trans_desc->tx_data[0] && - trans_buf->buffer_to_send != trans_desc->tx_buffer) { + trans_buf->buffer_to_send != trans_desc->tx_buffer) { free((void *)trans_buf->buffer_to_send); //force free, ignore const } // copy data from temporary DMA-capable buffer back to IRAM buffer and free the temporary one. @@ -868,7 +905,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans // rx memory assign uint32_t* rcv_ptr; - if ( trans_desc->flags & SPI_TRANS_USE_RXDATA ) { + if (trans_desc->flags & SPI_TRANS_USE_RXDATA) { rcv_ptr = (uint32_t *)&trans_desc->rx_data[0]; } else { //if not use RXDATA neither rx_buffer, buffer_to_rcv assigned to NULL @@ -877,7 +914,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans // tx memory assign const uint32_t *send_ptr; - if ( trans_desc->flags & SPI_TRANS_USE_TXDATA ) { + if (trans_desc->flags & SPI_TRANS_USE_TXDATA) { send_ptr = (uint32_t *)&trans_desc->tx_data[0]; } else { //if not use TXDATA neither tx_buffer, tx data assigned to NULL @@ -895,17 +932,17 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans #endif if (send_ptr && bus_attr->dma_enabled) { - if ((!esp_ptr_dma_capable(send_ptr) || tx_unaligned )) { + if ((!esp_ptr_dma_capable(send_ptr) || tx_unaligned)) { ESP_RETURN_ON_FALSE(!(trans_desc->flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but TX buffer addr&len not align to %d, or not dma_capable", alignment); //if txbuf in the desc not DMA-capable, or not bytes aligned to alignment, malloc a new one - ESP_EARLY_LOGD(SPI_TAG, "Allocate TX buffer for DMA" ); + ESP_EARLY_LOGD(SPI_TAG, "Allocate TX buffer for DMA"); tx_byte_len = (tx_byte_len + alignment - 1) & (~(alignment - 1)); // up align alignment uint32_t *temp = heap_caps_aligned_alloc(alignment, tx_byte_len, MALLOC_CAP_DMA); if (temp == NULL) { goto clean_up; } - memcpy( temp, send_ptr, (trans_desc->length + 7) / 8 ); + memcpy(temp, send_ptr, (trans_desc->length + 7) / 8); send_ptr = temp; } #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE @@ -914,10 +951,10 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans #endif } - if (rcv_ptr && bus_attr->dma_enabled && (!esp_ptr_dma_capable(rcv_ptr) || rx_unaligned )) { + if (rcv_ptr && bus_attr->dma_enabled && (!esp_ptr_dma_capable(rcv_ptr) || rx_unaligned)) { ESP_RETURN_ON_FALSE(!(trans_desc->flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but RX buffer addr&len not align to %d, or not dma_capable", alignment); //if rxbuf in the desc not DMA-capable, or not aligned to alignment, malloc a new one - ESP_EARLY_LOGD(SPI_TAG, "Allocate RX buffer for DMA" ); + ESP_EARLY_LOGD(SPI_TAG, "Allocate RX buffer for DMA"); rx_byte_len = (rx_byte_len + alignment - 1) & (~(alignment - 1)); // up align alignment rcv_ptr = heap_caps_aligned_alloc(alignment, rx_byte_len, MALLOC_CAP_DMA); if (rcv_ptr == NULL) { @@ -936,11 +973,13 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait) { esp_err_t ret = check_trans_valid(handle, trans_desc); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } spi_host_t *host = handle->host; - SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE ); + SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE); /* Even when using interrupt transfer, the CS can only be kept activated if the bus has been * acquired with `spi_device_acquire_bus()` first. */ @@ -950,7 +989,9 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi spi_trans_priv_t trans_buf = { .trans = trans_desc, }; ret = setup_priv_desc(host, &trans_buf); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } #ifdef CONFIG_PM_ENABLE // though clock source is selectable, read/write reg and mem of spi peripherial still use APB @@ -985,14 +1026,14 @@ esp_err_t SPI_MASTER_ATTR spi_device_get_trans_result(spi_device_handle_t handle { BaseType_t r; spi_trans_priv_t trans_buf; - SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG); + SPI_CHECK(handle != NULL, "invalid dev handle", ESP_ERR_INVALID_ARG); bool use_dma = handle->host->bus_attr->dma_enabled; //if SPI_DEVICE_NO_RETURN_RESULT is set, ret_queue will always be empty SPI_CHECK(!(handle->cfg.flags & SPI_DEVICE_NO_RETURN_RESULT), "API not Supported!", ESP_ERR_NOT_SUPPORTED); //use the interrupt, block until return - r=xQueueReceive(handle->ret_queue, (void*)&trans_buf, ticks_to_wait); + r = xQueueReceive(handle->ret_queue, (void*)&trans_buf, ticks_to_wait); if (!r) { // The memory occupied by rx and tx DMA buffer destroyed only when receiving from the queue (transaction finished). // If timeout, wait and retry. @@ -1015,10 +1056,14 @@ esp_err_t SPI_MASTER_ATTR spi_device_transmit(spi_device_handle_t handle, spi_tr spi_transaction_t *ret_trans; //ToDo: check if any spi transfers in flight ret = spi_device_queue_trans(handle, trans_desc, portMAX_DELAY); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } ret = spi_device_get_trans_result(handle, &ret_trans, portMAX_DELAY); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } assert(ret_trans == trans_desc); return ESP_OK; @@ -1027,8 +1072,8 @@ esp_err_t SPI_MASTER_ATTR spi_device_transmit(spi_device_handle_t handle, spi_tr esp_err_t SPI_MASTER_ISR_ATTR spi_device_acquire_bus(spi_device_t *device, TickType_t wait) { spi_host_t *const host = device->host; - SPI_CHECK(wait==portMAX_DELAY, "acquire finite time not supported now.", ESP_ERR_INVALID_ARG); - SPI_CHECK(!spi_bus_device_is_polling(device), "Cannot acquire bus when a polling transaction is in progress.", ESP_ERR_INVALID_STATE ); + SPI_CHECK(wait == portMAX_DELAY, "acquire finite time not supported now.", ESP_ERR_INVALID_ARG); + SPI_CHECK(!spi_bus_device_is_polling(device), "Cannot acquire bus when a polling transaction is in progress.", ESP_ERR_INVALID_STATE); esp_err_t ret = spi_bus_lock_acquire_start(device->dev_lock, wait); if (ret != ESP_OK) { @@ -1050,7 +1095,7 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_acquire_bus(spi_device_t *device, TickT #if CONFIG_IDF_TARGET_ESP32 if (host->bus_attr->dma_enabled) { //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same - spicommon_dmaworkaround_transfer_active(host->bus_attr->tx_dma_chan); + spicommon_dmaworkaround_transfer_active(host->dma_ctx->tx_dma_chan.chan_id); } #endif //#if CONFIG_IDF_TARGET_ESP32 @@ -1062,7 +1107,7 @@ void SPI_MASTER_ISR_ATTR spi_device_release_bus(spi_device_t *dev) { spi_host_t *host = dev->host; - if (spi_bus_device_is_polling(dev)){ + if (spi_bus_device_is_polling(dev)) { ESP_EARLY_LOGE(SPI_TAG, "Cannot release bus when a polling transaction is in progress."); assert(0); } @@ -1070,7 +1115,7 @@ void SPI_MASTER_ISR_ATTR spi_device_release_bus(spi_device_t *dev) #if CONFIG_IDF_TARGET_ESP32 if (host->bus_attr->dma_enabled) { //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same - spicommon_dmaworkaround_idle(host->bus_attr->tx_dma_chan); + spicommon_dmaworkaround_idle(host->dma_ctx->tx_dma_chan.chan_id); } //Tell common code DMA workaround that our DMA channel is idle. If needed, the code will do a DMA reset. #endif //#if CONFIG_IDF_TARGET_ESP32 @@ -1093,13 +1138,17 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_start(spi_device_handle_t handl esp_err_t ret; SPI_CHECK(ticks_to_wait == portMAX_DELAY, "currently timeout is not available for polling transactions", ESP_ERR_INVALID_ARG); ret = check_trans_valid(handle, trans_desc); - if (ret!=ESP_OK) return ret; - SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot send polling transaction while the previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE ); + if (ret != ESP_OK) { + return ret; + } + SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot send polling transaction while the previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE); spi_host_t *host = handle->host; spi_trans_priv_t priv_polling_trans = { .trans = trans_desc, }; ret = setup_priv_desc(host, &priv_polling_trans); - if (ret!=ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } /* If device_acquiring_lock is set to handle, it means that the user has already * acquired the bus thanks to the function `spi_device_acquire_bus()`. @@ -1182,7 +1231,9 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_transmit(spi_device_handle_t ha { esp_err_t ret; ret = spi_device_polling_start(handle, trans_desc, portMAX_DELAY); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } return spi_device_polling_end(handle, portMAX_DELAY); } diff --git a/components/driver/spi/gpspi/spi_slave.c b/components/esp_driver_spi/src/gpspi/spi_slave.c similarity index 77% rename from components/driver/spi/gpspi/spi_slave.c rename to components/esp_driver_spi/src/gpspi/spi_slave.c index f71a0443e49..73c9eab3c94 100644 --- a/components/driver/spi/gpspi/spi_slave.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave.c @@ -31,12 +31,12 @@ #include "esp_private/spi_slave_internal.h" #include "esp_private/spi_common_internal.h" #include "esp_private/esp_cache_private.h" +#include "esp_private/spi_share_hw_ctrl.h" static const char *SPI_TAG = "spi_slave"; #define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, SPI_TAG, str) - #ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM #define SPI_SLAVE_ISR_ATTR IRAM_ATTR #else @@ -59,6 +59,7 @@ typedef struct { typedef struct { int id; spi_bus_config_t bus_config; + spi_dma_ctx_t *dma_ctx; spi_slave_interface_config_t cfg; intr_handle_t intr; spi_slave_hal_context_t hal; @@ -72,8 +73,6 @@ typedef struct { bool cs_iomux; uint8_t cs_in_signal; uint16_t internal_mem_align_size; - uint32_t tx_dma_chan; - uint32_t rx_dma_chan; #ifdef CONFIG_PM_ENABLE esp_pm_lock_handle_t pm_lock; #endif @@ -98,7 +97,7 @@ static inline bool is_valid_host(spi_host_device_t host) static inline bool SPI_SLAVE_ISR_ATTR bus_is_iomux(spi_slave_t *host) { - return host->flags&SPICOMMON_BUSFLAG_IOMUX_PINS; + return host->flags & SPICOMMON_BUSFLAG_IOMUX_PINS; } static void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host) @@ -133,30 +132,28 @@ static void ipc_isr_reg_to_core(void *args) esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, spi_dma_chan_t dma_chan) { bool spi_chan_claimed; - uint32_t actual_tx_dma_chan = 0; - uint32_t actual_rx_dma_chan = 0; esp_err_t ret = ESP_OK; esp_err_t err; SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif CONFIG_IDF_TARGET_ESP32S2 - SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif - SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); + SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM - SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM)==0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG); + SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG); #endif SPI_CHECK(slave_config->spics_io_num < 0 || GPIO_IS_VALID_GPIO(slave_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG); //Check post_trans_cb status when `SPI_SLAVE_NO_RETURN_RESULT` flag is set. - if(slave_config->flags & SPI_SLAVE_NO_RETURN_RESULT) { + if (slave_config->flags & SPI_SLAVE_NO_RETURN_RESULT) { SPI_CHECK(slave_config->post_trans_cb != NULL, "use feature flag 'SPI_SLAVE_NO_RETURN_RESULT' but no post_trans_cb function sets", ESP_ERR_INVALID_ARG); } - spi_chan_claimed=spicommon_periph_claim(host, "spi slave"); + spi_chan_claimed = spicommon_periph_claim(host, "spi slave"); SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE); spihost[host] = malloc(sizeof(spi_slave_t)); @@ -172,17 +169,27 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b spihost[host]->dma_enabled = (dma_chan != SPI_DMA_DISABLED); if (spihost[host]->dma_enabled) { - ret = spicommon_dma_chan_alloc(host, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + ret = spicommon_dma_chan_alloc(host, dma_chan, &spihost[host]->dma_ctx); if (ret != ESP_OK) { goto cleanup; } - spihost[host]->tx_dma_chan = actual_tx_dma_chan; - spihost[host]->rx_dma_chan = actual_rx_dma_chan; + ret = spicommon_dma_desc_alloc(spihost[host]->dma_ctx, bus_config->max_transfer_sz, &spihost[host]->max_transfer_sz); + if (ret != ESP_OK) { + goto cleanup; + } + + hal->dmadesc_tx = spihost[host]->dma_ctx->dmadesc_tx; + hal->dmadesc_rx = spihost[host]->dma_ctx->dmadesc_rx; + hal->dmadesc_n = spihost[host]->dma_ctx->dma_desc_num; +#if SOC_GDMA_SUPPORTED + //temporary used for gdma_ll alias in hal layer + gdma_get_channel_id(spihost[host]->dma_ctx->tx_dma_chan, (int *)&hal->tx_dma_chan); + gdma_get_channel_id(spihost[host]->dma_ctx->rx_dma_chan, (int *)&hal->rx_dma_chan); +#else + hal->tx_dma_chan = spihost[host]->dma_ctx->tx_dma_chan.chan_id; + hal->rx_dma_chan = spihost[host]->dma_ctx->rx_dma_chan.chan_id; +#endif - //See how many dma descriptors we need and allocate them - int dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN; - if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given - spihost[host]->max_transfer_sz = dma_desc_ct * SPI_MAX_DMA_LEN; #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE size_t alignment; esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &alignment); @@ -190,21 +197,13 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b #else spihost[host]->internal_mem_align_size = 4; #endif - - hal->dmadesc_tx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); - hal->dmadesc_rx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); - if (!hal->dmadesc_tx || !hal->dmadesc_rx) { - ret = ESP_ERR_NO_MEM; - goto cleanup; - } - hal->dmadesc_n = dma_desc_ct; } else { //We're limited to non-DMA transfers: the SPI work registers can hold 64 bytes at most. spihost[host]->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE; } - err = spicommon_bus_initialize_io(host, bus_config, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags); - if (err!=ESP_OK) { + err = spicommon_bus_initialize_io(host, bus_config, SPICOMMON_BUSFLAG_SLAVE | bus_config->flags, &spihost[host]->flags); + if (err != ESP_OK) { ret = err; goto cleanup; } @@ -216,11 +215,13 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b } // The slave DMA suffers from unexpected transactions. Forbid reading if DMA is enabled by disabling the CS line. - if (spihost[host]->dma_enabled) freeze_cs(spihost[host]); + if (spihost[host]->dma_enabled) { + freeze_cs(spihost[host]); + } #ifdef CONFIG_PM_ENABLE err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_slave", - &spihost[host]->pm_lock); + &spihost[host]->pm_lock); if (err != ESP_OK) { ret = err; goto cleanup; @@ -235,7 +236,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b ret = ESP_ERR_NO_MEM; goto cleanup; } - if(!(slave_config->flags & SPI_SLAVE_NO_RETURN_RESULT)) { + if (!(slave_config->flags & SPI_SLAVE_NO_RETURN_RESULT)) { spihost[host]->ret_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_trans_priv_t)); if (!spihost[host]->ret_queue) { ret = ESP_ERR_NO_MEM; @@ -274,16 +275,17 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b hal->tx_lsbfirst = (slave_config->flags & SPI_SLAVE_TXBIT_LSBFIRST) ? 1 : 0; hal->mode = slave_config->mode; hal->use_dma = spihost[host]->dma_enabled; - hal->tx_dma_chan = actual_tx_dma_chan; - hal->rx_dma_chan = actual_rx_dma_chan; - spi_slave_hal_setup_device(hal); return ESP_OK; cleanup: if (spihost[host]) { - if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue); - if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue); + if (spihost[host]->trans_queue) { + vQueueDelete(spihost[host]->trans_queue); + } + if (spihost[host]->ret_queue) { + vQueueDelete(spihost[host]->ret_queue); + } #ifdef CONFIG_PM_ENABLE if (spihost[host]->pm_lock) { esp_pm_lock_release(spihost[host]->pm_lock); @@ -293,9 +295,9 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b } spi_slave_hal_deinit(&spihost[host]->hal); if (spihost[host]->dma_enabled) { - spicommon_dma_chan_free(host); - free(spihost[host]->hal.dmadesc_tx); - free(spihost[host]->hal.dmadesc_rx); + free(spihost[host]->dma_ctx->dmadesc_tx); + free(spihost[host]->dma_ctx->dmadesc_rx); + spicommon_dma_chan_free(spihost[host]->dma_ctx); } free(spihost[host]); @@ -309,12 +311,16 @@ esp_err_t spi_slave_free(spi_host_device_t host) { SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG); - if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue); - if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue); + if (spihost[host]->trans_queue) { + vQueueDelete(spihost[host]->trans_queue); + } + if (spihost[host]->ret_queue) { + vQueueDelete(spihost[host]->ret_queue); + } if (spihost[host]->dma_enabled) { - spicommon_dma_chan_free(host); - free(spihost[host]->hal.dmadesc_tx); - free(spihost[host]->hal.dmadesc_rx); + free(spihost[host]->dma_ctx->dmadesc_tx); + free(spihost[host]->dma_ctx->dmadesc_rx); + spicommon_dma_chan_free(spihost[host]->dma_ctx); } spicommon_bus_free_io_cfg(&spihost[host]->bus_config); esp_intr_free(spihost[host]->intr); @@ -357,10 +363,10 @@ static esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_setup_priv_trans(spi_host_device_t uint32_t buffer_byte_len = (trans->length + 7) / 8; if (spihost[host]->dma_enabled && trans->tx_buffer) { - if ((!esp_ptr_dma_capable( trans->tx_buffer ) || ((((uint32_t)trans->tx_buffer) | buffer_byte_len) & (alignment - 1)))) { + if ((!esp_ptr_dma_capable(trans->tx_buffer) || ((((uint32_t)trans->tx_buffer) | buffer_byte_len) & (alignment - 1)))) { ESP_RETURN_ON_FALSE_ISR(trans->flags & SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, SPI_TAG, "TX buffer addr&len not align to %d, or not dma_capable", alignment); //if txbuf in the desc not DMA-capable, or not align to "alignment", malloc a new one - ESP_EARLY_LOGD(SPI_TAG, "Allocate TX buffer for DMA" ); + ESP_EARLY_LOGD(SPI_TAG, "Allocate TX buffer for DMA"); buffer_byte_len = (buffer_byte_len + alignment - 1) & (~(alignment - 1)); // up align to "alignment" uint32_t *temp = heap_caps_aligned_alloc(alignment, buffer_byte_len, MALLOC_CAP_DMA); if (temp == NULL) { @@ -376,11 +382,11 @@ static esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_setup_priv_trans(spi_host_device_t if (spihost[host]->dma_enabled && trans->rx_buffer && (!esp_ptr_dma_capable(trans->rx_buffer) || ((((uint32_t)trans->rx_buffer) | (trans->length + 7) / 8) & (alignment - 1)))) { ESP_RETURN_ON_FALSE_ISR(trans->flags & SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, SPI_TAG, "RX buffer addr&len not align to %d, or not dma_capable", alignment); //if rxbuf in the desc not DMA-capable, or not align to "alignment", malloc a new one - ESP_EARLY_LOGD(SPI_TAG, "Allocate RX buffer for DMA" ); + ESP_EARLY_LOGD(SPI_TAG, "Allocate RX buffer for DMA"); buffer_byte_len = (buffer_byte_len + alignment - 1) & (~(alignment - 1)); // up align to "alignment" priv_trans->rx_buffer = heap_caps_aligned_alloc(alignment, buffer_byte_len, MALLOC_CAP_DMA); if (priv_trans->rx_buffer == NULL) { - free (priv_trans->tx_buffer); + free(priv_trans->tx_buffer); return ESP_ERR_NO_MEM; } } @@ -393,12 +399,18 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi BaseType_t r; SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG); - SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer), - "txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG); - SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->rx_buffer==NULL || - (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) && - (trans_desc->length%4==0)), - "rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG); + SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->tx_buffer == NULL || esp_ptr_dma_capable(trans_desc->tx_buffer), + "txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG); + + // We don't check length WORD alignment for rx when using DMA, seems break DMA requirement, + // however peripheral can also stop DMA from over writing memory even if it not aligned (except esp32). + // ATTENTION!: On esp32, peripheral can NOT stop DMA, if length not WORD aligned, + // remain bytes in last word domain will overwritten by DMA HW, which may cause unexpected issues! + // But driver already used for long time, to avoid breaking changes, we still don't add alignment limit. + SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->rx_buffer == NULL || + (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) && + (trans_desc->length % 8 == 0)), + "rxdata not in DMA-capable memory or not BYTE aligned", ESP_ERR_INVALID_ARG); SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG); @@ -406,7 +418,9 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi SPI_CHECK(ESP_OK == spi_slave_setup_priv_trans(host, &priv_trans), "slave setup priv_trans failed", ESP_ERR_NO_MEM); r = xQueueSend(spihost[host]->trans_queue, (void *)&priv_trans, ticks_to_wait); - if (!r) return ESP_ERR_TIMEOUT; + if (!r) { + return ESP_ERR_TIMEOUT; + } esp_intr_enable(spihost[host]->intr); return ESP_OK; } @@ -415,6 +429,7 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi * @note * This API is used to reset SPI Slave transaction queue. After calling this function: * - The SPI Slave transaction queue will be reset. + * - The transaction which already mount on hardware will NOT be reset, and can be overwritten by next `trans_queue` * * Therefore, this API shouldn't be called when the corresponding SPI Master is doing an SPI transaction. * @@ -434,7 +449,7 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_reset(spi_host_device_t host) spi_ll_set_int_stat(spihost[host]->hal.hw); spi_slave_trans_priv_t trans; - while( uxQueueMessagesWaiting(spihost[host]->trans_queue)) { + while (uxQueueMessagesWaiting(spihost[host]->trans_queue)) { xQueueReceive(spihost[host]->trans_queue, &trans, 0); spi_slave_uninstall_priv_trans(host, &trans); } @@ -452,20 +467,20 @@ esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_queue_trans_isr(spi_host_device_t host, c ESP_RETURN_ON_FALSE_ISR(trans_desc->length <= spihost[host]->max_transfer_sz * 8, ESP_ERR_INVALID_ARG, SPI_TAG, "data transfer > host maximum"); if (spihost[host]->dma_enabled) { uint16_t alignment = spihost[host]->internal_mem_align_size; + (void) alignment; + +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + // For those targets length and addr alignment is still required from Cache side uint32_t buffer_byte_len = (trans_desc->length + 7) / 8; + bool tx_aligned = (trans_desc->tx_buffer == NULL) || (esp_ptr_dma_capable(trans_desc->tx_buffer) && ((((uint32_t)trans_desc->tx_buffer | buffer_byte_len) & (alignment - 1)) == 0)); + bool rx_aligned = (trans_desc->rx_buffer == NULL) || (esp_ptr_dma_capable(trans_desc->rx_buffer) && ((((uint32_t)trans_desc->rx_buffer | buffer_byte_len) & (alignment - 1)) == 0)); +#else + bool tx_aligned = (trans_desc->tx_buffer == NULL) || esp_ptr_dma_capable(trans_desc->tx_buffer); + bool rx_aligned = (trans_desc->rx_buffer == NULL) || (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) && (trans_desc->length % 8 == 0)); +#endif - ESP_RETURN_ON_FALSE_ISR(\ - (trans_desc->tx_buffer && \ - esp_ptr_dma_capable(trans_desc->tx_buffer) && \ - ((((uint32_t)trans_desc->tx_buffer) | buffer_byte_len) & (alignment - 1)) == 0), \ - ESP_ERR_INVALID_ARG, SPI_TAG, "txdata addr & len not align to %d bytes or not dma_capable", alignment\ - ); - ESP_RETURN_ON_FALSE_ISR(\ - (trans_desc->rx_buffer && \ - esp_ptr_dma_capable(trans_desc->rx_buffer) && \ - ((((uint32_t)trans_desc->rx_buffer) | buffer_byte_len) & (alignment - 1)) == 0), \ - ESP_ERR_INVALID_ARG, SPI_TAG, "rxdata addr & len not align to %d bytes or not dma_capable", alignment\ - ); + ESP_RETURN_ON_FALSE_ISR(tx_aligned, ESP_ERR_INVALID_ARG, SPI_TAG, "txdata addr & len not align to %d bytes or not dma_capable", alignment); + ESP_RETURN_ON_FALSE_ISR(rx_aligned, ESP_ERR_INVALID_ARG, SPI_TAG, "rxdata addr & len not align to %d bytes or not dma_capable", alignment); } spi_slave_trans_priv_t priv_trans = { @@ -490,7 +505,7 @@ esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_queue_reset_isr(spi_host_device_t host) spi_slave_trans_priv_t trans; BaseType_t do_yield = pdFALSE; - while( pdFALSE == xQueueIsQueueEmptyFromISR(spihost[host]->trans_queue)) { + while (pdFALSE == xQueueIsQueueEmptyFromISR(spihost[host]->trans_queue)) { xQueueReceiveFromISR(spihost[host]->trans_queue, &trans, &do_yield); spi_slave_uninstall_priv_trans(host, &trans); } @@ -512,23 +527,28 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_ spi_slave_trans_priv_t priv_trans; r = xQueueReceive(spihost[host]->ret_queue, (void *)&priv_trans, ticks_to_wait); - if (!r) return ESP_ERR_TIMEOUT; + if (!r) { + return ESP_ERR_TIMEOUT; + } spi_slave_uninstall_priv_trans(host, &priv_trans); *trans_desc = priv_trans.trans; return ESP_OK; } - esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait) { esp_err_t ret; spi_slave_transaction_t *ret_trans; //ToDo: check if any spi transfers in flight ret = spi_slave_queue_trans(host, trans_desc, ticks_to_wait); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } ret = spi_slave_get_trans_result(host, &ret_trans, ticks_to_wait); - if (ret != ESP_OK) return ret; + if (ret != ESP_OK) { + return ret; + } assert(ret_trans == trans_desc); return ESP_OK; } @@ -556,7 +576,9 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) bool use_dma = host->dma_enabled; if (host->cur_trans.trans) { // When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready. - if (use_dma) freeze_cs(host); + if (use_dma) { + freeze_cs(host); + } spi_slave_hal_store_result(hal); host->cur_trans.trans->trans_len = spi_slave_hal_get_rcv_bitlen(hal); @@ -565,7 +587,7 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) //This workaround is only for esp32 if (spi_slave_hal_dma_need_reset(hal)) { //On ESP32, actual_tx_dma_chan and actual_rx_dma_chan are always same - spicommon_dmaworkaround_req_reset(host->tx_dma_chan, spi_slave_restart_after_dmareset, host); + spicommon_dmaworkaround_req_reset(host->dma_ctx->tx_dma_chan.chan_id, spi_slave_restart_after_dmareset, host); } #endif //#if CONFIG_IDF_TARGET_ESP32 @@ -579,9 +601,11 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) assert(ret == ESP_OK); } #endif - if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans.trans); + if (host->cfg.post_trans_cb) { + host->cfg.post_trans_cb(host->cur_trans.trans); + } - if(!(host->cfg.flags & SPI_SLAVE_NO_RETURN_RESULT)) { + if (!(host->cfg.flags & SPI_SLAVE_NO_RETURN_RESULT)) { xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield); } host->cur_trans.trans = NULL; @@ -591,11 +615,13 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) //This workaround is only for esp32 if (use_dma) { //On ESP32, actual_tx_dma_chan and actual_rx_dma_chan are always same - spicommon_dmaworkaround_idle(host->tx_dma_chan); + spicommon_dmaworkaround_idle(host->dma_ctx->tx_dma_chan.chan_id); if (spicommon_dmaworkaround_reset_in_progress()) { //We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr. esp_intr_disable(host->intr); - if (do_yield) portYIELD_FROM_ISR(); + if (do_yield) { + portYIELD_FROM_ISR(); + } return; } } @@ -624,7 +650,7 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) if (use_dma) { //This workaround is only for esp32 //On ESP32, actual_tx_dma_chan and actual_rx_dma_chan are always same - spicommon_dmaworkaround_transfer_active(host->tx_dma_chan); + spicommon_dmaworkaround_transfer_active(host->dma_ctx->tx_dma_chan.chan_id); } #endif //#if CONFIG_IDF_TARGET_ESP32 @@ -637,7 +663,11 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) //Kick off transfer spi_slave_hal_user_start(hal); - if (host->cfg.post_setup_cb) host->cfg.post_setup_cb(priv_trans.trans); + if (host->cfg.post_setup_cb) { + host->cfg.post_setup_cb(priv_trans.trans); + } + } + if (do_yield) { + portYIELD_FROM_ISR(); } - if (do_yield) portYIELD_FROM_ISR(); } diff --git a/components/driver/spi/gpspi/spi_slave_hd.c b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c similarity index 88% rename from components/driver/spi/gpspi/spi_slave_hd.c rename to components/esp_driver_spi/src/gpspi/spi_slave_hd.c index 8612748a1de..2138db26c0c 100644 --- a/components/driver/spi/gpspi/spi_slave_hd.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c @@ -13,6 +13,7 @@ #include "freertos/ringbuf.h" #include "driver/gpio.h" #include "esp_private/spi_common_internal.h" +#include "esp_private/spi_share_hw_ctrl.h" #include "esp_private/esp_cache_private.h" #include "driver/spi_slave_hd.h" #include "hal/spi_slave_hd_hal.h" @@ -35,15 +36,12 @@ typedef struct { typedef struct { bool dma_enabled; + spi_dma_ctx_t *dma_ctx; uint16_t internal_mem_align_size; int max_transfer_sz; uint32_t flags; portMUX_TYPE int_spinlock; intr_handle_t intr; -#if SOC_GDMA_SUPPORTED - gdma_channel_handle_t gdma_handle_tx; //varible for storge gdma handle - gdma_channel_handle_t gdma_handle_rx; -#endif intr_handle_t intr_dma; spi_slave_hd_callback_config_t callback; spi_slave_hd_hal_context_t hal; @@ -73,13 +71,10 @@ static bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_ev static void spi_slave_hd_intr_append(void *arg); static void spi_slave_hd_intr_segment(void *arg); -esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, - const spi_slave_hd_slot_config_t *config) +esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, const spi_slave_hd_slot_config_t *config) { bool spi_chan_claimed; bool append_mode = (config->flags & SPI_SLAVE_HD_APPEND_MODE); - uint32_t actual_tx_dma_chan = 0; - uint32_t actual_rx_dma_chan = 0; esp_err_t ret = ESP_OK; SPIHD_CHECK(VALID_HOST(host_id), "invalid host", ESP_ERR_INVALID_ARG); @@ -103,34 +98,28 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b host->append_mode = append_mode; if (host->dma_enabled) { - ret = spicommon_dma_chan_alloc(host_id, config->dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + ret = spicommon_dma_chan_alloc(host_id, config->dma_chan, &host->dma_ctx); if (ret != ESP_OK) { goto cleanup; } - - //Malloc for all the DMA descriptors - int dma_desc_ct = (bus_config->max_transfer_sz + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; - if (dma_desc_ct == 0) { - dma_desc_ct = 1; //default to 4k when max is not given + ret = spicommon_dma_desc_alloc(host->dma_ctx, bus_config->max_transfer_sz, &host->max_transfer_sz); + if (ret != ESP_OK) { + goto cleanup; } - host->hal.dma_desc_num = dma_desc_ct; - spi_dma_desc_t *orig_dmadesc_tx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); - spi_dma_desc_t *orig_dmadesc_rx = heap_caps_aligned_alloc(DMA_DESC_MEM_ALIGN_SIZE, sizeof(spi_dma_desc_t) * dma_desc_ct, MALLOC_CAP_DMA); - host->hal.dmadesc_tx = heap_caps_malloc(sizeof(spi_slave_hd_hal_desc_append_t) * dma_desc_ct, MALLOC_CAP_DEFAULT); - host->hal.dmadesc_rx = heap_caps_malloc(sizeof(spi_slave_hd_hal_desc_append_t) * dma_desc_ct, MALLOC_CAP_DEFAULT); - if (!(host->hal.dmadesc_tx && host->hal.dmadesc_rx && orig_dmadesc_tx && orig_dmadesc_rx)) { + host->hal.dma_desc_num = host->dma_ctx->dma_desc_num; + host->hal.dmadesc_tx = heap_caps_malloc(sizeof(spi_slave_hd_hal_desc_append_t) * host->hal.dma_desc_num, MALLOC_CAP_DEFAULT); + host->hal.dmadesc_rx = heap_caps_malloc(sizeof(spi_slave_hd_hal_desc_append_t) * host->hal.dma_desc_num, MALLOC_CAP_DEFAULT); + if (!(host->hal.dmadesc_tx && host->hal.dmadesc_rx)) { ret = ESP_ERR_NO_MEM; goto cleanup; } //Pair each desc to each possible trans - for (int i = 0; i < dma_desc_ct; i ++) { - host->hal.dmadesc_tx[i].desc = &orig_dmadesc_tx[i]; - host->hal.dmadesc_rx[i].desc = &orig_dmadesc_rx[i]; + for (int i = 0; i < host->hal.dma_desc_num; i ++) { + host->hal.dmadesc_tx[i].desc = &host->dma_ctx->dmadesc_tx[i]; + host->hal.dmadesc_rx[i].desc = &host->dma_ctx->dmadesc_rx[i]; } - //Get the actual SPI bus transaction size in bytes. - host->max_transfer_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE size_t alignment; esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &alignment); @@ -155,14 +144,21 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b .dma_in = SPI_LL_GET_HW(host_id), .dma_out = SPI_LL_GET_HW(host_id), .dma_enabled = host->dma_enabled, - .tx_dma_chan = actual_tx_dma_chan, - .rx_dma_chan = actual_rx_dma_chan, .append_mode = append_mode, .mode = config->mode, .tx_lsbfirst = (config->flags & SPI_SLAVE_HD_RXBIT_LSBFIRST), .rx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST), }; +#if SOC_GDMA_SUPPORTED + //temporary used for gdma_ll alias in hal layer + gdma_get_channel_id(host->dma_ctx->tx_dma_chan, (int *)&hal_config.tx_dma_chan); + gdma_get_channel_id(host->dma_ctx->rx_dma_chan, (int *)&hal_config.rx_dma_chan); +#else + hal_config.tx_dma_chan = host->dma_ctx->tx_dma_chan.chan_id; + hal_config.rx_dma_chan = host->dma_ctx->rx_dma_chan.chan_id; +#endif + //Init the hal according to the hal_config set above spi_slave_hd_hal_init(&host->hal, &hal_config); @@ -198,12 +194,12 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b if (!host->append_mode) { //Seg mode ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_segment, - (void *)host, &host->intr); + (void *)host, &host->intr); if (ret != ESP_OK) { goto cleanup; } ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_segment, - (void *)host, &host->intr_dma); + (void *)host, &host->intr_dma); if (ret != ESP_OK) { goto cleanup; } @@ -212,20 +208,19 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b //On ESP32S2, `cmd7` and `cmd8` interrupts registered as spi rx & tx interrupt are from SPI DMA interrupt source. //although the `cmd7` and `cmd8` interrupt on spi are registered independently here ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_append, - (void *)host, &host->intr); + (void *)host, &host->intr); if (ret != ESP_OK) { goto cleanup; } #if SOC_GDMA_SUPPORTED // config gmda and ISR callback for gdma supported chip - spicommon_gdma_get_handle(host_id, &host->gdma_handle_tx, GDMA_CHANNEL_DIRECTION_TX); gdma_tx_event_callbacks_t tx_cbs = { .on_trans_eof = spi_gdma_tx_channel_callback }; - gdma_register_tx_event_callbacks(host->gdma_handle_tx, &tx_cbs, host); + gdma_register_tx_event_callbacks(host->dma_ctx->tx_dma_chan, &tx_cbs, host); #else ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_append, - (void *)host, &host->intr_dma); + (void *)host, &host->intr_dma); if (ret != ESP_OK) { goto cleanup; } @@ -234,10 +229,18 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b //Init callbacks memcpy((uint8_t *)&host->callback, (uint8_t *)&config->cb_config, sizeof(spi_slave_hd_callback_config_t)); spi_event_t event = 0; - if (host->callback.cb_buffer_tx != NULL) event |= SPI_EV_BUF_TX; - if (host->callback.cb_buffer_rx != NULL) event |= SPI_EV_BUF_RX; - if (host->callback.cb_cmd9 != NULL) event |= SPI_EV_CMD9; - if (host->callback.cb_cmdA != NULL) event |= SPI_EV_CMDA; + if (host->callback.cb_buffer_tx != NULL) { + event |= SPI_EV_BUF_TX; + } + if (host->callback.cb_buffer_rx != NULL) { + event |= SPI_EV_BUF_RX; + } + if (host->callback.cb_cmd9 != NULL) { + event |= SPI_EV_CMD9; + } + if (host->callback.cb_cmdA != NULL) { + event |= SPI_EV_CMDA; + } spi_slave_hd_hal_enable_event_intr(&host->hal, event); return ESP_OK; @@ -251,14 +254,28 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id) { spi_slave_hd_slot_t *host = spihost[host_id]; - if (host == NULL) return ESP_ERR_INVALID_ARG; - - if (host->tx_trans_queue) vQueueDelete(host->tx_trans_queue); - if (host->tx_ret_queue) vQueueDelete(host->tx_ret_queue); - if (host->rx_trans_queue) vQueueDelete(host->rx_trans_queue); - if (host->rx_ret_queue) vQueueDelete(host->rx_ret_queue); - if (host->tx_cnting_sem) vSemaphoreDelete(host->tx_cnting_sem); - if (host->rx_cnting_sem) vSemaphoreDelete(host->rx_cnting_sem); + if (host == NULL) { + return ESP_ERR_INVALID_ARG; + } + + if (host->tx_trans_queue) { + vQueueDelete(host->tx_trans_queue); + } + if (host->tx_ret_queue) { + vQueueDelete(host->tx_ret_queue); + } + if (host->rx_trans_queue) { + vQueueDelete(host->rx_trans_queue); + } + if (host->rx_ret_queue) { + vQueueDelete(host->rx_ret_queue); + } + if (host->tx_cnting_sem) { + vSemaphoreDelete(host->tx_cnting_sem); + } + if (host->rx_cnting_sem) { + vSemaphoreDelete(host->rx_cnting_sem); + } esp_intr_free(host->intr); esp_intr_free(host->intr_dma); #ifdef CONFIG_PM_ENABLE @@ -270,11 +287,11 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id) spicommon_periph_free(host_id); if (host->dma_enabled) { - free(host->hal.dmadesc_tx->desc); - free(host->hal.dmadesc_rx->desc); + free(host->dma_ctx->dmadesc_tx); + free(host->dma_ctx->dmadesc_rx); free(host->hal.dmadesc_tx); free(host->hal.dmadesc_rx); - spicommon_dma_chan_free(host_id); + spicommon_dma_chan_free(host->dma_ctx); } free(host); spihost[host_id] = NULL; @@ -418,7 +435,9 @@ static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg) } portEXIT_CRITICAL_ISR(&host->int_spinlock); - if (awoken == pdTRUE) portYIELD_FROM_ISR(); + if (awoken == pdTRUE) { + portYIELD_FROM_ISR(); + } } static IRAM_ATTR void spi_slave_hd_append_tx_isr(void *arg) @@ -456,7 +475,9 @@ static IRAM_ATTR void spi_slave_hd_append_tx_isr(void *arg) assert(ret == pdTRUE); } } - if (awoken==pdTRUE) portYIELD_FROM_ISR(); + if (awoken == pdTRUE) { + portYIELD_FROM_ISR(); + } } static IRAM_ATTR void spi_slave_hd_append_rx_isr(void *arg) @@ -467,7 +488,6 @@ static IRAM_ATTR void spi_slave_hd_append_rx_isr(void *arg) BaseType_t awoken = pdFALSE; BaseType_t ret __attribute__((unused)); - spi_slave_hd_trans_priv_t ret_priv_trans; size_t trans_len; while (1) { @@ -502,7 +522,9 @@ static IRAM_ATTR void spi_slave_hd_append_rx_isr(void *arg) assert(ret == pdTRUE); } } - if (awoken==pdTRUE) portYIELD_FROM_ISR(); + if (awoken == pdTRUE) { + portYIELD_FROM_ISR(); + } } #if SOC_GDMA_SUPPORTED @@ -569,7 +591,7 @@ static esp_err_t s_spi_slave_hd_setup_priv_trans(spi_host_device_t host, spi_sla if (((uint32_t)orig_trans->data) | (byte_len & (alignment - 1))) { ESP_RETURN_ON_FALSE(orig_trans->flags & SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, TAG, "data buffer addr&len not align to %d, or not dma_capable", alignment); byte_len = (byte_len + alignment - 1) & (~(alignment - 1)); // up align to alignment - ESP_LOGD(TAG, "Re-allocate %s buffer of len %ld for DMA", (chan == SPI_SLAVE_CHAN_TX)?"TX":"RX", byte_len); + ESP_LOGD(TAG, "Re-allocate %s buffer of len %ld for DMA", (chan == SPI_SLAVE_CHAN_TX) ? "TX" : "RX", byte_len); priv_trans->aligned_buffer = heap_caps_aligned_alloc(64, byte_len, MALLOC_CAP_DMA); if (priv_trans->aligned_buffer == NULL) { return ESP_ERR_NO_MEM; @@ -615,7 +637,7 @@ esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t c SPIHD_CHECK(chan == SPI_SLAVE_CHAN_TX || chan == SPI_SLAVE_CHAN_RX, "Invalid channel", ESP_ERR_INVALID_ARG); spi_slave_hd_trans_priv_t hd_priv_trans = {.trans = trans}; - SPIHD_CHECK( ESP_OK == s_spi_slave_hd_setup_priv_trans(host_id, &hd_priv_trans, chan), "No mem to allocate new cache buffer", ESP_ERR_NO_MEM); + SPIHD_CHECK(ESP_OK == s_spi_slave_hd_setup_priv_trans(host_id, &hd_priv_trans, chan), "No mem to allocate new cache buffer", ESP_ERR_NO_MEM); if (chan == SPI_SLAVE_CHAN_TX) { BaseType_t ret = xQueueSend(host->tx_trans_queue, &hd_priv_trans, timeout); @@ -669,7 +691,7 @@ esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t SPIHD_CHECK(chan == SPI_SLAVE_CHAN_TX || chan == SPI_SLAVE_CHAN_RX, "Invalid channel", ESP_ERR_INVALID_ARG); spi_slave_hd_trans_priv_t hd_priv_trans = {.trans = trans}; - SPIHD_CHECK( ESP_OK == s_spi_slave_hd_setup_priv_trans(host_id, &hd_priv_trans, chan), "No mem to allocate new cache buffer", ESP_ERR_NO_MEM); + SPIHD_CHECK(ESP_OK == s_spi_slave_hd_setup_priv_trans(host_id, &hd_priv_trans, chan), "No mem to allocate new cache buffer", ESP_ERR_NO_MEM); if (chan == SPI_SLAVE_CHAN_TX) { BaseType_t ret = xSemaphoreTake(host->tx_cnting_sem, timeout); diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..f863d7c16b9 --- /dev/null +++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml @@ -0,0 +1,26 @@ +.spi_depends_default: &spi_depends_default + depends_components: + - esp_mm # for cache + - esp_driver_spi + - esp_driver_gpio + +components/esp_driver_spi/test_apps/spi/master: + disable: + - if: SOC_GPSPI_SUPPORTED != 1 + <<: *spi_depends_default + +components/esp_driver_spi/test_apps/spi/param: + disable: + - if: SOC_GPSPI_SUPPORTED != 1 + <<: *spi_depends_default + +components/esp_driver_spi/test_apps/spi/slave: + disable: + - if: SOC_GPSPI_SUPPORTED != 1 + <<: *spi_depends_default + +components/esp_driver_spi/test_apps/spi/slave_hd: + disable: + - if: SOC_GPSPI_SUPPORTED != 1 + - if: SOC_SPI_SUPPORT_SLAVE_HD_VER2 != 1 + <<: *spi_depends_default diff --git a/components/driver/test_apps/spi/master/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/master/CMakeLists.txt similarity index 89% rename from components/driver/test_apps/spi/master/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/master/CMakeLists.txt index 0ba91789647..72e52621b38 100644 --- a/components/driver/test_apps/spi/master/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/spi/master/CMakeLists.txt @@ -15,7 +15,7 @@ project(spi_master_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_spi/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/spi_master_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/spi/master/README.md b/components/esp_driver_spi/test_apps/spi/master/README.md similarity index 100% rename from components/driver/test_apps/spi/master/README.md rename to components/esp_driver_spi/test_apps/spi/master/README.md diff --git a/components/driver/test_apps/spi/master/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/master/main/CMakeLists.txt similarity index 80% rename from components/driver/test_apps/spi/master/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/master/main/CMakeLists.txt index 3d7c23c1aef..f8d95ad31e2 100644 --- a/components/driver/test_apps/spi/master/main/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/spi/master/main/CMakeLists.txt @@ -11,6 +11,6 @@ set(srcs # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS ${srcs} - PRIV_REQUIRES test_utils driver test_driver_utils spi_flash + PRIV_REQUIRES test_utils esp_driver_spi test_driver_utils spi_flash WHOLE_ARCHIVE ) diff --git a/components/driver/test_apps/spi/master/main/test_app_main.c b/components/esp_driver_spi/test_apps/spi/master/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/spi/master/main/test_app_main.c rename to components/esp_driver_spi/test_apps/spi/master/main/test_app_main.c diff --git a/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c b/components/esp_driver_spi/test_apps/spi/master/main/test_spi_bus_lock.c similarity index 84% rename from components/driver/test_apps/spi/master/main/test_spi_bus_lock.c rename to components/esp_driver_spi/test_apps/spi/master/main/test_spi_bus_lock.c index 3a513cc7e4f..4b7276b6f04 100644 --- a/components/driver/test_apps/spi/master/main/test_spi_bus_lock.c +++ b/components/esp_driver_spi/test_apps/spi/master/main/test_spi_bus_lock.c @@ -13,7 +13,6 @@ #include "spi_flash_mmap.h" #include "unity.h" - #if CONFIG_IDF_TARGET_ESP32 // The VSPI pins on UT_T1_ESP_FLASH are connected to a external flash #define TEST_BUS_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO @@ -50,21 +49,21 @@ const static char TAG[] = "test_spi"; void spi_task1(void* arg) { //task1 send 50 polling transactions, acquire the bus and send another 50 - int count=0; + int count = 0; spi_transaction_t t = { .flags = SPI_TRANS_USE_TXDATA, .tx_data = { 0x80, 0x12, 0x34, 0x56 }, - .length = 4*8, + .length = 4 * 8, }; spi_device_handle_t handle = ((task_context_t*)arg)->handle; - for( int j = 0; j < 50; j ++ ) { - TEST_ESP_OK(spi_device_polling_transmit( handle, &t )); - ESP_LOGI(TAG, "task1:%d", count++ ); + for (int j = 0; j < 50; j ++) { + TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); + ESP_LOGI(TAG, "task1:%d", count++); } - TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY )); - for( int j = 0; j < 50; j ++ ) { - TEST_ESP_OK(spi_device_polling_transmit( handle, &t )); - ESP_LOGI(TAG, "task1:%d", count++ ); + TEST_ESP_OK(spi_device_acquire_bus(handle, portMAX_DELAY)); + for (int j = 0; j < 50; j ++) { + TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); + ESP_LOGI(TAG, "task1:%d", count++); } spi_device_release_bus(handle); ESP_LOGI(TAG, "task1 terminates"); @@ -74,29 +73,29 @@ void spi_task1(void* arg) void spi_task2(void* arg) { - int count=0; + int count = 0; //task2 acquire the bus, send 50 polling transactions and then 50 non-polling spi_transaction_t t = { .flags = SPI_TRANS_USE_TXDATA, .tx_data = { 0x80, 0x12, 0x34, 0x56 }, - .length = 4*8, + .length = 4 * 8, }; spi_transaction_t *ret_t; spi_device_handle_t handle = ((task_context_t*)arg)->handle; - TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY )); + TEST_ESP_OK(spi_device_acquire_bus(handle, portMAX_DELAY)); for (int i = 0; i < 50; i ++) { TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); - ESP_LOGI( TAG, "task2: %d", count++ ); + ESP_LOGI(TAG, "task2: %d", count++); } - for( int j = 0; j < 50; j ++ ) { + for (int j = 0; j < 50; j ++) { TEST_ESP_OK(spi_device_queue_trans(handle, &t, portMAX_DELAY)); } - for( int j = 0; j < 50; j ++ ) { + for (int j = 0; j < 50; j ++) { TEST_ESP_OK(spi_device_get_trans_result(handle, &ret_t, portMAX_DELAY)); assert(ret_t == &t); - ESP_LOGI( TAG, "task2: %d", count++ ); + ESP_LOGI(TAG, "task2: %d", count++); } spi_device_release_bus(handle); vTaskDelay(1); @@ -108,24 +107,24 @@ void spi_task2(void* arg) void spi_task3(void* arg) { //task3 send 30 polling transactions, acquire the bus, send 20 polling transactions and then 50 non-polling - int count=0; + int count = 0; spi_transaction_t t = { .flags = SPI_TRANS_USE_TXDATA, .tx_data = { 0x80, 0x12, 0x34, 0x56 }, - .length = 4*8, + .length = 4 * 8, }; spi_transaction_t *ret_t; spi_device_handle_t handle = ((task_context_t*)arg)->handle; for (int i = 0; i < 30; i ++) { TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); - ESP_LOGI( TAG, "task3: %d", count++ ); + ESP_LOGI(TAG, "task3: %d", count++); } - TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY )); + TEST_ESP_OK(spi_device_acquire_bus(handle, portMAX_DELAY)); for (int i = 0; i < 20; i ++) { TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); - ESP_LOGI( TAG, "task3: %d", count++ ); + ESP_LOGI(TAG, "task3: %d", count++); } for (int j = 0; j < 50; j++) { @@ -147,11 +146,11 @@ static void write_large_buffer(esp_flash_t *chip, const esp_partition_t *part, c { printf("Erasing chip %p, %d bytes\n", chip, length); - TEST_ESP_OK(esp_flash_erase_region(chip, part->address, (length + SPI_FLASH_SEC_SIZE) & ~(SPI_FLASH_SEC_SIZE - 1)) ); + TEST_ESP_OK(esp_flash_erase_region(chip, part->address, (length + SPI_FLASH_SEC_SIZE) & ~(SPI_FLASH_SEC_SIZE - 1))); printf("Writing chip %p, %d bytes from source %p\n", chip, length, source); // note writing to unaligned address - TEST_ESP_OK(esp_flash_write(chip, source, part->address + 1, length) ); + TEST_ESP_OK(esp_flash_write(chip, source, part->address + 1, length)); printf("Write done.\n"); } @@ -161,18 +160,18 @@ static void read_and_check(esp_flash_t *chip, const esp_partition_t *part, const printf("Checking chip %p, %d bytes\n", chip, length); uint8_t *buf = malloc(length); TEST_ASSERT_NOT_NULL(buf); - TEST_ESP_OK(esp_flash_read(chip, buf, part->address + 1, length) ); + TEST_ESP_OK(esp_flash_read(chip, buf, part->address + 1, length)); TEST_ASSERT_EQUAL_HEX8_ARRAY(source, buf, length); free(buf); // check nothing was written at beginning or end uint8_t ends[8]; - TEST_ESP_OK(esp_flash_read(chip, ends, part->address, sizeof(ends)) ); + TEST_ESP_OK(esp_flash_read(chip, ends, part->address, sizeof(ends))); TEST_ASSERT_EQUAL_HEX8(0xFF, ends[0]); TEST_ASSERT_EQUAL_HEX8(source[0], ends[1]); - TEST_ESP_OK(esp_flash_read(chip, ends, part->address + length, sizeof(ends)) ); + TEST_ESP_OK(esp_flash_read(chip, ends, part->address + length, sizeof(ends))); TEST_ASSERT_EQUAL_HEX8(source[length - 1], ends[0]); TEST_ASSERT_EQUAL_HEX8(0xFF, ends[1]); @@ -210,18 +209,18 @@ void spi_task4(void* arg) static void test_bus_lock(bool test_flash) { - task_context_t context1={}; - task_context_t context2={}; - task_context_t context3={}; - task_context_t context4={}; + task_context_t context1 = {}; + task_context_t context2 = {}; + task_context_t context3 = {}; + task_context_t context4 = {}; TaskHandle_t task1, task2, task3, task4; esp_err_t ret; - spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); + spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); buscfg.miso_io_num = TEST_BUS_PIN_NUM_MISO; buscfg.mosi_io_num = TEST_BUS_PIN_NUM_MOSI; buscfg.sclk_io_num = TEST_BUS_PIN_NUM_CLK; - spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); + spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.queue_size = 100; //Initialize the SPI bus and 3 devices @@ -258,18 +257,20 @@ static void test_bus_lock(bool test_flash) } ESP_LOGI(TAG, "Start testing..."); - xTaskCreate( spi_task1, "task1", 4096, &context1, 0, &task1 ); - xTaskCreate( spi_task2, "task2", 4096, &context2, 0, &task2 ); - xTaskCreate( spi_task3, "task3", 4096, &context3, 0, &task3 ); + xTaskCreate(spi_task1, "task1", 4096, &context1, 0, &task1); + xTaskCreate(spi_task2, "task2", 4096, &context2, 0, &task2); + xTaskCreate(spi_task3, "task3", 4096, &context3, 0, &task3); if (test_flash) { - xTaskCreate( spi_task4, "task4", 2048, &context4, 0, &task4 ); + xTaskCreate(spi_task4, "task4", 2048, &context4, 0, &task4); } else { context4.finished = true; } - for(;;){ + for (;;) { vTaskDelay(10); - if (context1.finished && context2.finished && context3.finished && context4.finished) break; + if (context1.finished && context2.finished && context3.finished && context4.finished) { + break; + } } TEST_ESP_OK(spi_bus_remove_device(context1.handle)); @@ -278,19 +279,18 @@ static void test_bus_lock(bool test_flash) if (test_flash) { TEST_ESP_OK(spi_bus_remove_flash_device(chip)); } - TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST) ); + TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST)); } #if CONFIG_IDF_TARGET_ESP32 // no need this case in other target, only esp32 need buslock to split MSPI and GPSPI2 action -TEST_CASE("spi bus lock, with flash","[spi][test_env=external_flash]") +TEST_CASE("spi bus lock, with flash", "[spi][test_env=external_flash]") { test_bus_lock(true); } #endif //CONFIG_IDF_TARGET_ESP32 - -TEST_CASE("spi bus lock","[spi]") +TEST_CASE("spi bus lock", "[spi]") { test_bus_lock(false); } @@ -327,7 +327,7 @@ TEST_CASE("spi master can be used on SPI1", "[spi]") { spi_device_interface_config_t dev_cfg = { .mode = 1, - .clock_speed_hz = 1*1000*1000, + .clock_speed_hz = 1 * 1000 * 1000, .spics_io_num = -1, .queue_size = 1, }; diff --git a/components/driver/test_apps/spi/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/spi/master/main/test_spi_master.c similarity index 95% rename from components/driver/test_apps/spi/master/main/test_spi_master.c rename to components/esp_driver_spi/test_apps/spi/master/main/test_spi_master.c index d017af51752..1375978d3ae 100644 --- a/components/driver/test_apps/spi/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/spi/master/main/test_spi_master.c @@ -7,7 +7,6 @@ Tests for the spi_master device driver */ - #include "sdkconfig.h" #include "driver/spi_master.h" #include "driver/spi_slave.h" @@ -24,7 +23,6 @@ #include "test_utils.h" #include "test_spi_utils.h" - const static char TAG[] = "test_spi"; // There is no input-only pin except on esp32 and esp32s2 @@ -75,8 +73,7 @@ static void check_spi_pre_n_for(spi_clock_source_t clock_source, int clk, int pr * {freq, pre, n} */ #define TEST_CLK_TIMES 8 -struct test_clk_param_group_t -{ +struct test_clk_param_group_t { uint32_t clk_param_80m[TEST_CLK_TIMES][3]; uint32_t clk_param_48m[TEST_CLK_TIMES][3]; uint32_t clk_param_40m[TEST_CLK_TIMES][3]; @@ -92,7 +89,6 @@ struct test_clk_param_group_t {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 2, 35}, {333333, 1, 21}, {800000, 1, 9}, {900000, 1, 8}, {1100000, 1, 6}, {4000000, 1, 2,}, {7000000, 1, 1} }, }; - TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") { spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); @@ -148,12 +144,12 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") #if SOC_SPI_SUPPORT_CLK_XTAL esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz); printf("\nTest clock source XTAL = %ld\n", clock_source_hz); - if((40 * 1000 * 1000) == clock_source_hz){ + if ((40 * 1000 * 1000) == clock_source_hz) { for (int i = 0; i < TEST_CLK_TIMES; i++) { check_spi_pre_n_for(SPI_CLK_SRC_XTAL, test_clk_param.clk_param_40m[i][0], test_clk_param.clk_param_40m[i][1], test_clk_param.clk_param_40m[i][2]); } } - if((32 * 1000 * 1000) == clock_source_hz){ + if ((32 * 1000 * 1000) == clock_source_hz) { for (int i = 0; i < TEST_CLK_TIMES; i++) { check_spi_pre_n_for(SPI_CLK_SRC_XTAL, test_clk_param.clk_param_32m[i][0], test_clk_param.clk_param_32m[i][1], test_clk_param.clk_param_32m[i][2]); } @@ -164,12 +160,12 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") #if SOC_SPI_SUPPORT_CLK_RC_FAST esp_clk_tree_src_get_freq_hz(SPI_CLK_SRC_RC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz); printf("\nTest clock source RC_FAST = %ld\n", clock_source_hz); - if((17500000) == clock_source_hz){ + if ((17500000) == clock_source_hz) { for (int i = 0; i < TEST_CLK_TIMES; i++) { check_spi_pre_n_for(SPI_CLK_SRC_RC_FAST, test_clk_param.clk_param_17m[i][0], test_clk_param.clk_param_17m[i][1], test_clk_param.clk_param_17m[i][2]); } } - if((7000000) == clock_source_hz){ + if ((7000000) == clock_source_hz) { for (int i = 0; i < TEST_CLK_TIMES; i++) { check_spi_pre_n_for(SPI_CLK_SRC_RC_FAST, test_clk_param.clk_param_7m[i][0], test_clk_param.clk_param_7m[i][1], test_clk_param.clk_param_7m[i][2]); } @@ -317,7 +313,6 @@ TEST_CASE("SPI Master test", "[spi]") TEST_ASSERT(success); } - TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") { esp_err_t ret; @@ -355,7 +350,6 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") printf("Sending to dev 2\n"); success &= spi_test(handle2, 5000); - ret = spi_bus_remove_device(handle2); TEST_ASSERT(ret == ESP_OK); master_free_device_bus(handle1); @@ -440,9 +434,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); ESP_LOGI(TAG, "test 4 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL; @@ -451,9 +445,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); ESP_LOGI(TAG, "test 6 output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_GPIO_PINS; @@ -463,9 +457,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); ESP_LOGI(TAG, "test 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; @@ -475,9 +469,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); #if TEST_SOC_HAS_INPUT_ONLY_PINS //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored. ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin..."); @@ -487,7 +481,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS; @@ -496,7 +490,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS; @@ -506,7 +500,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS; @@ -515,7 +509,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected }; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); + TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o); //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored. #endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS @@ -673,7 +667,6 @@ TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)" TEST_ESP_OK(spi_bus_free(host)); } - DRAM_ATTR static uint32_t data_dram[80] = {0}; //force to place in code area. static const uint8_t data_drom[320 + 3] = { @@ -789,36 +782,36 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); - for ( int i = 0; i < 8; i ++ ) { - memset( rx_buf, 0x66, sizeof(rx_buf)); + for (int i = 0; i < 8; i ++) { + memset(rx_buf, 0x66, sizeof(rx_buf)); spi_transaction_t t = {}; t.length = 8 * (i + 1); t.rxlength = 0; t.tx_buffer = tx_buf + 2 * i; t.rx_buffer = rx_buf + i; - if ( i == 1 ) { + if (i == 1) { //test set no start t.rx_buffer = NULL; - } else if ( i == 2 ) { + } else if (i == 2) { //test rx length != tx_length t.rxlength = t.length - 8; } - spi_device_transmit( spi, &t ); + spi_device_transmit(spi, &t); - for ( int i = 0; i < 16; i ++ ) { + for (int i = 0; i < 16; i ++) { printf("%02X ", rx_buf[i]); } printf("\n"); - if ( i == 1 ) { + if (i == 1) { // no rx, skip check - } else if ( i == 2 ) { + } else if (i == 2) { //test rx length = tx length-1 - TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length / 8 - 1 ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length / 8 - 1); } else { //normal check - TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length / 8 ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length / 8); } } @@ -826,7 +819,6 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK); } - #if (TEST_SPI_PERIPH_NUM >= 2) //These will only be enabled on chips with 2 or more SPI peripherals @@ -881,7 +873,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) #ifdef CONFIG_IDF_TARGET_ESP32 addr_bits = 56 - 8 * i; #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - //ESP32S2 only supportes up to 32 bits address + //ESP32S2 only supportes up to 32 bits address addr_bits = 28 - 4 * i; #endif int round_up = (cmd_bits + addr_bits + 7) / 8 * 8; @@ -897,7 +889,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) .address_bits = addr_bits, }; - ESP_LOGI( MASTER_TAG, "===== test%d =====", i ); + ESP_LOGI(MASTER_TAG, "===== test%d =====", i); ESP_LOGI(MASTER_TAG, "cmd_bits: %d, addr_bits: %d", cmd_bits, addr_bits); TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t *)&trans)); //wait for both master and slave end @@ -964,10 +956,10 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) TEST_CASE("SPI master variable cmd & addr test", "[spi]") { spi_slave_task_context_t slave_context = {}; - esp_err_t err = init_slave_context( &slave_context, TEST_SLAVE_HOST ); - TEST_ASSERT( err == ESP_OK ); + esp_err_t err = init_slave_context(&slave_context, TEST_SLAVE_HOST); + TEST_ASSERT(err == ESP_OK); TaskHandle_t handle_slave; - xTaskCreate( spitest_slave_task, "spi_slave", 4096, &slave_context, 0, &handle_slave); + xTaskCreate(spitest_slave_task, "spi_slave", 4096, &slave_context, 0, &handle_slave); //initial slave, mode 0, no dma int dma_chan = 0; @@ -976,12 +968,12 @@ TEST_CASE("SPI master variable cmd & addr test", "[spi]") spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slvcfg.mode = slave_mode; //Initialize SPI slave interface - TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, dma_chan) ); + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, dma_chan)); test_cmd_addr(&slave_context, false); test_cmd_addr(&slave_context, true); - vTaskDelete( handle_slave ); + vTaskDelete(handle_slave); handle_slave = 0; deinit_slave_context(&slave_context); @@ -1225,12 +1217,12 @@ static void fd_master(void) //Master FD DMA, RX without TX Test for (int i = 0; i < TEST_NUM; i++) { // 1. Master FD DMA, only receive, with NULL tx_buffer - get_tx_buffer(FD_SEED1+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED1 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); memset(mst_recv_buf, 0x0, FD_TEST_BUF_SIZE); master_only_rx_trans(spi, mst_recv_buf, slv_send_buf, FD_TEST_BUF_SIZE); //2. Master FD DMA with TX and RX - get_tx_buffer(FD_SEED2+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED2 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); memset(mst_recv_buf, 0x0, FD_TEST_BUF_SIZE); master_both_trans(spi, mst_send_buf, mst_recv_buf, slv_send_buf, FD_TEST_BUF_SIZE); } @@ -1238,11 +1230,11 @@ static void fd_master(void) //Master FD DMA, TX without RX Test for (int i = 0; i < TEST_NUM; i++) { // 1. Master FD DMA, only send, with NULL rx_buffer - get_tx_buffer(FD_SEED3+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED3 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); master_only_tx_trans(spi, mst_send_buf, FD_TEST_BUF_SIZE); //2. Master FD DMA with TX and RX - get_tx_buffer(FD_SEED4+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED4 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); memset(mst_recv_buf, 0x0, FD_TEST_BUF_SIZE); master_both_trans(spi, mst_send_buf, mst_recv_buf, slv_send_buf, FD_TEST_BUF_SIZE); } @@ -1307,23 +1299,23 @@ static void fd_slave(void) for (int i = 0; i < TEST_NUM; i++) { //1. Slave TX without RX (rx_buffer == NULL) - get_tx_buffer(FD_SEED1+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED1 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); slave_only_tx_trans(slv_send_buf, FD_TEST_BUF_SIZE); //2. Slave both TX and RX - get_tx_buffer(FD_SEED2+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED2 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); memset(slv_recv_buf, 0x0, FD_TEST_BUF_SIZE); slave_both_trans(slv_send_buf, slv_recv_buf, mst_send_buf, FD_TEST_BUF_SIZE); } for (int i = 0; i < TEST_NUM; i++) { // 1. Slave RX without TX (tx_buffer == NULL) - get_tx_buffer(FD_SEED3+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED3 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); memset(slv_recv_buf, 0x0, FD_TEST_BUF_SIZE); slave_only_rx_trans(slv_recv_buf, mst_send_buf, FD_TEST_BUF_SIZE); //2. Slave both TX and RX - get_tx_buffer(FD_SEED4+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(FD_SEED4 + i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE); memset(slv_recv_buf, 0x0, FD_TEST_BUF_SIZE); slave_both_trans(slv_send_buf, slv_recv_buf, mst_send_buf, FD_TEST_BUF_SIZE); } @@ -1337,7 +1329,6 @@ static void fd_slave(void) TEST_CASE_MULTIPLE_DEVICES("SPI Master: FD, DMA, Master Single Direction Test", "[spi_ms][test_env=generic_multi_device]", fd_master, fd_slave); #endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32) //TODO: IDF-3494 - //NOTE: Explained in IDF-1445 | MR !14996 #if !(CONFIG_SPIRAM) || (CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL >= 16384) /******************************************************************************** @@ -1539,7 +1530,7 @@ void test_add_device_master(void) TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i])); memset(master_recvbuf, 0, sizeof(master_recvbuf)); - get_tx_buffer(21, master_sendbuf, master_expect, TEST_TRANS_LEN); + test_fill_random_to_buffers_dualboard(21, master_sendbuf, master_expect, TEST_TRANS_LEN); unity_send_signal("Master ready"); unity_wait_for_signal("Slave ready"); @@ -1582,7 +1573,7 @@ void test_add_device_slave(void) for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { memset(slave_recvbuf, 0, sizeof(slave_recvbuf)); - get_tx_buffer(21, slave_expect, slave_sendbuf, TEST_TRANS_LEN); + test_fill_random_to_buffers_dualboard(21, slave_expect, slave_sendbuf, TEST_TRANS_LEN); unity_wait_for_signal("Master ready"); unity_send_signal("Slave ready"); @@ -1600,15 +1591,15 @@ void test_add_device_slave(void) TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test multiple devices", "[spi_ms]", test_add_device_master, test_add_device_slave); - #if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE) #define TEST_ISR_CNT 100 -static void test_master_isr_core_post_trans_cbk(spi_transaction_t *curr_trans){ +static void test_master_isr_core_post_trans_cbk(spi_transaction_t *curr_trans) +{ *((int *)curr_trans->user) += esp_cpu_get_core_id(); } -TEST_CASE("test_master_isr_pin_to_core","[spi]") +TEST_CASE("test_master_isr_pin_to_core", "[spi]") { spi_device_handle_t dev0; uint32_t master_send; @@ -1640,7 +1631,6 @@ TEST_CASE("test_master_isr_pin_to_core","[spi]") // by default the esp_intr_alloc is called on ESP_MAIN_TASK_AFFINITY_CPU0 now TEST_ASSERT_EQUAL_UINT32(0, master_expect); - //-------------------------------------CPU1--------------------------------------- buscfg.isr_cpu_id = ESP_INTR_CPU_AFFINITY_1; @@ -1681,7 +1671,7 @@ static IRAM_ATTR void test_master_iram(void) uint8_t *master_send = heap_caps_malloc(TEST_MASTER_IRAM_TRANS_LEN, MALLOC_CAP_DMA); uint8_t *master_recv = heap_caps_calloc(1, TEST_MASTER_IRAM_TRANS_LEN, MALLOC_CAP_DMA); uint8_t *master_exp = heap_caps_malloc(TEST_MASTER_IRAM_TRANS_LEN, MALLOC_CAP_DEFAULT); - get_tx_buffer(211, master_send, master_exp, TEST_MASTER_IRAM_TRANS_LEN); + test_fill_random_to_buffers_dualboard(211, master_send, master_exp, TEST_MASTER_IRAM_TRANS_LEN); spi_transaction_t trans_cfg = { .tx_buffer = master_send, .rx_buffer = master_recv, @@ -1696,7 +1686,7 @@ static IRAM_ATTR void test_master_iram(void) spi_flash_disable_interrupts_caches_and_other_cpu(); flag_trans_done = false; spi_device_queue_trans(dev_handle, &trans_cfg, portMAX_DELAY); - while(!flag_trans_done) { + while (!flag_trans_done) { // waitting for transaction done and return from ISR } spi_device_get_trans_result(dev_handle, &ret_trans, portMAX_DELAY); @@ -1708,7 +1698,7 @@ static IRAM_ATTR void test_master_iram(void) // Test polling trans api once ------------------------------- unity_wait_for_signal("Slave ready"); - get_tx_buffer(119, master_send, master_exp, TEST_MASTER_IRAM_TRANS_LEN); + test_fill_random_to_buffers_dualboard(119, master_send, master_exp, TEST_MASTER_IRAM_TRANS_LEN); spi_flash_disable_interrupts_caches_and_other_cpu(); spi_device_polling_transmit(dev_handle, &trans_cfg); @@ -1739,7 +1729,7 @@ static void test_iram_slave_normal(void) slave_trans.length = TEST_MASTER_IRAM_TRANS_LEN * 8; slave_trans.tx_buffer = slave_sendbuf; slave_trans.rx_buffer = slave_recvbuf; - get_tx_buffer(211, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); + test_fill_random_to_buffers_dualboard(211, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); unity_wait_for_signal("Master ready"); unity_send_signal("Slave ready"); @@ -1749,7 +1739,7 @@ static void test_iram_slave_normal(void) spitest_cmp_or_dump(slave_expect, slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN); unity_send_signal("Slave ready"); - get_tx_buffer(119, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); + test_fill_random_to_buffers_dualboard(119, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY); ESP_LOG_BUFFER_HEX("slave tx", slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN); ESP_LOG_BUFFER_HEX("slave rx", slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN); diff --git a/components/driver/test_apps/spi/master/main/test_spi_sio.c b/components/esp_driver_spi/test_apps/spi/master/main/test_spi_sio.c similarity index 99% rename from components/driver/test_apps/spi/master/main/test_spi_sio.c rename to components/esp_driver_spi/test_apps/spi/master/main/test_spi_sio.c index 49de3304454..de593a0ddf7 100644 --- a/components/driver/test_apps/spi/master/main/test_spi_sio.c +++ b/components/esp_driver_spi/test_apps/spi/master/main/test_spi_sio.c @@ -49,7 +49,6 @@ static void inner_connect(spi_bus_config_t bus) //Slave MOSI(spid_in) input to `mosi_num` spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in); - //Master MOSI input(spid_in) to `miso_num`, due to SIO mode, we use Master's `spid_in` to receive data spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in); //Slave MISO output(spiq_out) @@ -76,11 +75,9 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]") spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED)); - same_pin_func_sel(bus_cfg, dev_cfg, 0); inner_connect(bus_cfg); - WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320]; WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320]; @@ -114,7 +111,6 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]") ESP_LOG_BUFFER_HEXDUMP("slave rx", slv_trans.rx_buffer, tlen, ESP_LOG_INFO); TEST_ASSERT_EQUAL_HEX8_ARRAY(mst_trans.tx_buffer, slv_trans.rx_buffer, tlen); - ESP_LOGI("spi", "=========== TEST(%d) Master RX, Slave TX ==========", i); //Slave TX memset(&slv_trans, 0x0, sizeof(spi_slave_transaction_t)); diff --git a/components/driver/test_apps/spi/master/partition_table_esp32_flash.csv b/components/esp_driver_spi/test_apps/spi/master/partition_table_esp32_flash.csv similarity index 100% rename from components/driver/test_apps/spi/master/partition_table_esp32_flash.csv rename to components/esp_driver_spi/test_apps/spi/master/partition_table_esp32_flash.csv diff --git a/components/driver/test_apps/spi/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/spi/master/pytest_spi_master.py similarity index 100% rename from components/driver/test_apps/spi/master/pytest_spi_master.py rename to components/esp_driver_spi/test_apps/spi/master/pytest_spi_master.py diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.defaults b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.defaults new file mode 100644 index 00000000000..250a29bc45b --- /dev/null +++ b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.defaults @@ -0,0 +1,2 @@ +# don't delete. +# used for CI to compile a default config when 'sdkconfig.ci.xxxx' is exist diff --git a/components/driver/test_apps/spi/master/sdkconfig.ci.freertos_compliance b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_compliance similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.ci.freertos_compliance rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_compliance diff --git a/components/driver/test_apps/spi/master/sdkconfig.ci.freertos_flash b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_flash similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.ci.freertos_flash rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_flash diff --git a/components/driver/test_apps/spi/master/sdkconfig.ci.iram_safe b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.ci.iram_safe rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/spi/master/sdkconfig.ci.release b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.ci.release rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.release diff --git a/components/driver/test_apps/spi/master/sdkconfig.defaults b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults diff --git a/components/driver/test_apps/spi/master/sdkconfig.defaults.esp32 b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32 similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.defaults.esp32 rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32 diff --git a/components/driver/test_apps/spi/master/sdkconfig.defaults.esp32s2 b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s2 similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.defaults.esp32s2 rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s2 diff --git a/components/driver/test_apps/spi/master/sdkconfig.defaults.esp32s3 b/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s3 similarity index 100% rename from components/driver/test_apps/spi/master/sdkconfig.defaults.esp32s3 rename to components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s3 diff --git a/components/driver/test_apps/spi/param/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/param/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/spi/param/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/param/CMakeLists.txt diff --git a/components/driver/test_apps/spi/param/README.md b/components/esp_driver_spi/test_apps/spi/param/README.md similarity index 100% rename from components/driver/test_apps/spi/param/README.md rename to components/esp_driver_spi/test_apps/spi/param/README.md diff --git a/components/driver/test_apps/spi/param/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/param/main/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/spi/param/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/param/main/CMakeLists.txt diff --git a/components/driver/test_apps/spi/param/main/test_app_main.c b/components/esp_driver_spi/test_apps/spi/param/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/spi/param/main/test_app_main.c rename to components/esp_driver_spi/test_apps/spi/param/main/test_app_main.c diff --git a/components/driver/test_apps/spi/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/spi/param/main/test_spi_param.c similarity index 96% rename from components/driver/test_apps/spi/param/main/test_spi_param.c rename to components/esp_driver_spi/test_apps/spi/param/main/test_spi_param.c index 3ffee20b242..5c8f44332d5 100644 --- a/components/driver/test_apps/spi/param/main/test_spi_param.c +++ b/components/esp_driver_spi/test_apps/spi/param/main/test_spi_param.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -50,7 +50,7 @@ static void local_test_init(void **arg) spitest_context_t *context = (spitest_context_t *)*arg; TEST_ASSERT(context != NULL); context->slave_context = (spi_slave_task_context_t) {}; - esp_err_t err = init_slave_context( &context->slave_context, TEST_SLAVE_HOST); + esp_err_t err = init_slave_context(&context->slave_context, TEST_SLAVE_HOST); TEST_ASSERT(err == ESP_OK); xTaskCreate(spitest_slave_task, "spi_slave", 4096, &context->slave_context, 0, &context->handle_slave); @@ -213,16 +213,16 @@ static void local_test_loop(const void *arg1, void *arg2) bool failed = false; //check master data - if (check_master_data && memcmp(slave_trans.tx_buffer, t->rx_buffer, (len + 7) / 8) != 0 ) { + if (check_master_data && memcmp(slave_trans.tx_buffer, t->rx_buffer, (len + 7) / 8) != 0) { failed = true; } //check slave data and length //currently the rcv_len can be in range of [t->length-1, t->length+3] - if ( rcv_len < len - 1 || rcv_len > len + 4) { + if (rcv_len < len - 1 || rcv_len > len + 4) { failed = true; } - if (check_slave_data && memcmp(t->tx_buffer, slave_trans.rx_buffer, (len + 7) / 8) != 0 ) { + if (check_slave_data && memcmp(t->tx_buffer, slave_trans.rx_buffer, (len + 7) / 8) != 0) { failed = true; } @@ -378,7 +378,6 @@ static int test_freq_mode_local[] = { #define SLAVE_EXTRA_DELAY_DMA 0 #endif - static spitest_param_set_t mode_pgroup[] = { { .pset_name = "Mode 0", @@ -795,7 +794,7 @@ static void test_master_loop(const void *arg1, void *arg2) const int *timing_speed_array = test_cfg->freq_list; ESP_LOGI(MASTER_TAG, "****************** %s ***************", test_cfg->pset_name); - for (int i = 0; ; i++ ) { + for (int i = 0; ; i++) { const int freq = timing_speed_array[i]; if (freq == 0) { break; @@ -809,21 +808,21 @@ static void test_master_loop(const void *arg1, void *arg2) unity_wait_for_signal("Slave ready"); - for ( int j = 0; j < test_cfg->test_size; j ++ ) { + for (int j = 0; j < test_cfg->test_size; j ++) { //wait for both master and slave end - ESP_LOGI( MASTER_TAG, "=> test%d", j ); + ESP_LOGI(MASTER_TAG, "=> test%d", j); //send master tx data vTaskDelay(20); spi_transaction_t *t = &context->master_trans[j]; - TEST_ESP_OK (spi_device_transmit(spi, t) ); + TEST_ESP_OK(spi_device_transmit(spi, t)); int len = get_trans_len(test_cfg->dup, t); if (TEST_LOG_DBUG) { spitest_master_print_data(t, len); } size_t rcv_len; - slave_rxdata_t *rcv_data = xRingbufferReceive( context->slave_context.data_received, &rcv_len, portMAX_DELAY ); + slave_rxdata_t *rcv_data = xRingbufferReceive(context->slave_context.data_received, &rcv_len, portMAX_DELAY); if (TEST_LOG_DBUG) { spitest_slave_print_data(rcv_data, false); } @@ -840,7 +839,7 @@ static void test_master_loop(const void *arg1, void *arg2) check_len, check_slave_data)); } //clean - vRingbufferReturnItem( context->slave_context.data_received, rcv_data ); + vRingbufferReturnItem(context->slave_context.data_received, rcv_data); } master_free_device_bus(spi); } @@ -854,17 +853,17 @@ static void test_slave_init(void **arg) spitest_context_t *context = (spitest_context_t *)*arg; TEST_ASSERT(context != NULL); context->slave_context = (spi_slave_task_context_t) {}; - esp_err_t err = init_slave_context( &context->slave_context, TEST_SPI_HOST); - TEST_ASSERT( err == ESP_OK ); + esp_err_t err = init_slave_context(&context->slave_context, TEST_SPI_HOST); + TEST_ASSERT(err == ESP_OK); unity_wait_for_signal("Master ready"); - xTaskCreate( spitest_slave_task, "spi_slave", 4096, &context->slave_context, 0, &context->handle_slave); + xTaskCreate(spitest_slave_task, "spi_slave", 4096, &context->slave_context, 0, &context->handle_slave); } static void test_slave_deinit(void *arg) { spitest_context_t *context = (spitest_context_t *)arg; - vTaskDelete( context->handle_slave ); + vTaskDelete(context->handle_slave); context->handle_slave = 0; deinit_slave_context(&context->slave_context); @@ -905,7 +904,7 @@ static void test_slave_loop(const void *arg1, void *arg2) spitest_init_transactions(pset, context); const int *timing_speed_array = pset->freq_list; - for (int i = 0; ; i++ ) { + for (int i = 0; ; i++) { const int freq = timing_speed_array[i]; if (freq == 0) { break; @@ -920,16 +919,16 @@ static void test_slave_loop(const void *arg1, void *arg2) //prepare slave tx data for (int i = 0; i < pset->test_size; i ++) { - xQueueSend( context->slave_context.data_to_send, &context->slave_trans[i], portMAX_DELAY ); + xQueueSend(context->slave_context.data_to_send, &context->slave_trans[i], portMAX_DELAY); //memcpy(context->master_trans[i].rx_buffer, context->slave_trans[i].start, (context->master_trans[i].length+7)/8); } vTaskDelay(50 / portTICK_PERIOD_MS); unity_send_signal("Slave ready"); - for ( int i = 0; i < pset->test_size; i ++ ) { + for (int i = 0; i < pset->test_size; i ++) { //wait for both master and slave end - ESP_LOGI( MASTER_TAG, "===== test%d =====", i ); + ESP_LOGI(MASTER_TAG, "===== test%d =====", i); //send master tx data vTaskDelay(20); @@ -940,7 +939,7 @@ static void test_slave_loop(const void *arg1, void *arg2) } size_t rcv_len; - slave_rxdata_t *rcv_data = xRingbufferReceive( context->slave_context.data_received, &rcv_len, portMAX_DELAY ); + slave_rxdata_t *rcv_data = xRingbufferReceive(context->slave_context.data_received, &rcv_len, portMAX_DELAY); if (TEST_LOG_DBUG) { spitest_slave_print_data(rcv_data, true); } @@ -951,7 +950,7 @@ static void test_slave_loop(const void *arg1, void *arg2) const bool check_len = true; TEST_ESP_OK(spitest_check_data(len, t, rcv_data, check_master_data, check_len, check_slave_data)); //clean - vRingbufferReturnItem( context->slave_context.data_received, rcv_data ); + vRingbufferReturnItem(context->slave_context.data_received, rcv_data); } TEST_ASSERT(spi_slave_free(TEST_SPI_HOST) == ESP_OK); } @@ -1269,7 +1268,6 @@ TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "") #endif // #if (TEST_SPI_PERIPH_NUM >= 2) - #define TEST_STEP_LEN 96 #define TEST_STEP 2 static int s_spi_bus_freq[] = { @@ -1316,7 +1314,7 @@ static void test_master_fd_dma(void) unity_send_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(master_recive, 0x00, TEST_STEP_LEN); - get_tx_buffer(119 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN); + test_fill_random_to_buffers_dualboard(119 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN); uint32_t test_trans_len = TEST_STEP_LEN; spi_transaction_t trans_cfg = { @@ -1367,7 +1365,7 @@ static void test_slave_fd_dma(void) unity_wait_for_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(slave_recive, 0x00, TEST_STEP_LEN); - get_tx_buffer(119 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN); + test_fill_random_to_buffers_dualboard(119 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN); uint32_t test_trans_len = TEST_STEP_LEN; spi_slave_transaction_t trans_cfg = { @@ -1395,7 +1393,6 @@ static void test_slave_fd_dma(void) TEST_CASE_MULTIPLE_DEVICES("TEST_SPI_Freq_FD_DMA", "[spi_ms][timeout=30]", test_master_fd_dma, test_slave_fd_dma); - //------------------------------------------- Full Duplex no DMA Freq test -------------------------------------- static void test_master_fd_no_dma(void) { @@ -1432,7 +1429,7 @@ static void test_master_fd_no_dma(void) unity_send_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(master_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE); - get_tx_buffer(211 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE); + test_fill_random_to_buffers_dualboard(211 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE); uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE; spi_transaction_t trans_cfg = { @@ -1484,7 +1481,7 @@ static void test_slave_fd_no_dma(void) unity_wait_for_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(slave_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE); - get_tx_buffer(211 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE); + test_fill_random_to_buffers_dualboard(211 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE); uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE; spi_slave_transaction_t trans_cfg = { @@ -1511,7 +1508,6 @@ static void test_slave_fd_no_dma(void) TEST_CASE_MULTIPLE_DEVICES("TEST_SPI_Freq_FD_no_DMA", "[spi_ms][timeout=30]", test_master_fd_no_dma, test_slave_fd_no_dma); - #if SOC_SPI_SUPPORT_SLAVE_HD_VER2 //------------------------------------------- Half Duplex with DMA Freq test -------------------------------------- static void test_master_hd_dma(void) @@ -1540,7 +1536,7 @@ static void test_master_hd_dma(void) unity_send_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(master_recive, 0x00, TEST_STEP_LEN); - get_tx_buffer(985 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN); + test_fill_random_to_buffers_dualboard(985 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN); uint32_t test_trans_len = TEST_STEP_LEN; unity_wait_for_signal("Slave ready"); @@ -1584,7 +1580,7 @@ static void test_slave_hd_dma(void) unity_wait_for_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(slave_recive, 0x00, TEST_STEP_LEN); - get_tx_buffer(985 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN); + test_fill_random_to_buffers_dualboard(985 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN); uint32_t test_trans_len = TEST_STEP_LEN; spi_slave_hd_data_t *ret_trans, slave_trans = { @@ -1614,7 +1610,6 @@ static void test_slave_hd_dma(void) TEST_CASE_MULTIPLE_DEVICES("TEST_SPI_Freq_HD_DMA", "[spi_ms][timeout=30]", test_master_hd_dma, test_slave_hd_dma); - //------------------------------------------- Half Duplex no DMA Freq test -------------------------------------- static void test_master_hd_no_dma(void) { @@ -1642,7 +1637,7 @@ static void test_master_hd_no_dma(void) unity_send_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(master_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE); - get_tx_buffer(911 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE); + test_fill_random_to_buffers_dualboard(911 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE); uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE; unity_wait_for_signal("Slave ready"); @@ -1686,7 +1681,7 @@ static void test_slave_hd_no_dma(void) unity_wait_for_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(slave_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE); - get_tx_buffer(911 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE); + test_fill_random_to_buffers_dualboard(911 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE); uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE; spi_slave_hd_data_t *ret_trans, slave_trans = { @@ -1717,7 +1712,6 @@ static void test_slave_hd_no_dma(void) TEST_CASE_MULTIPLE_DEVICES("TEST_SPI_Freq_HD_no_DMA", "[spi_ms][timeout=30]", test_master_hd_no_dma, test_slave_hd_no_dma); #endif // SOC_SPI_SUPPORT_SLAVE_HD_VER2 - #if CONFIG_IDF_TARGET_ESP32 // item num should same as `s_spi_bus_freq` static int s_master_input_delay[] = {12.5, 12.5 * 2, 12.5 * 2, 12.5 * 5, 12.5 * 5}; @@ -1762,7 +1756,7 @@ static void test_master_sio_dma(void) unity_send_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(master_recive, 0x00, TEST_STEP_LEN); - get_tx_buffer(110 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN); + test_fill_random_to_buffers_dualboard(110 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN); spi_transaction_t trans = {}; if (sio_master_in) { // master input only @@ -1824,7 +1818,7 @@ static void test_slave_sio_dma(void) unity_wait_for_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(slave_recive, 0x00, TEST_STEP_LEN); - get_tx_buffer(110 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN); + test_fill_random_to_buffers_dualboard(110 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN); spi_slave_transaction_t trans = { .length = TEST_STEP_LEN * 8, .tx_buffer = slave_send, @@ -1853,7 +1847,6 @@ static void test_slave_sio_dma(void) TEST_CASE_MULTIPLE_DEVICES("TEST_SPI_Freq_SIO_DMA", "[spi_ms][timeout=30]", test_master_sio_dma, test_slave_sio_dma); - //------------------------------------------- SIO no DMA Freq test -------------------------------------- static void test_master_sio_no_dma(void) { @@ -1895,7 +1888,7 @@ static void test_master_sio_no_dma(void) unity_send_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(master_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE); - get_tx_buffer(122 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE); + test_fill_random_to_buffers_dualboard(122 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE); spi_transaction_t trans = {}; if (sio_master_in) { // master input only @@ -1958,7 +1951,7 @@ static void test_slave_sio_no_dma(void) unity_wait_for_signal("Master ready"); for (int i = 0; i < TEST_STEP; i++) { memset(slave_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE); - get_tx_buffer(122 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE); + test_fill_random_to_buffers_dualboard(122 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE); spi_slave_transaction_t trans = { .length = SOC_SPI_MAXIMUM_BUFFER_SIZE * 8, .tx_buffer = slave_send, diff --git a/components/driver/test_apps/spi/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/spi/param/pytest_spi_param.py similarity index 100% rename from components/driver/test_apps/spi/param/pytest_spi_param.py rename to components/esp_driver_spi/test_apps/spi/param/pytest_spi_param.py diff --git a/components/driver/test_apps/spi/param/sdkconfig.defaults b/components/esp_driver_spi/test_apps/spi/param/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/spi/param/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/spi/param/sdkconfig.defaults diff --git a/components/driver/test_apps/spi/slave/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/slave/CMakeLists.txt similarity index 89% rename from components/driver/test_apps/spi/slave/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/slave/CMakeLists.txt index a7531fe7f28..7cc8d06266b 100644 --- a/components/driver/test_apps/spi/slave/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/spi/slave/CMakeLists.txt @@ -15,7 +15,7 @@ project(spi_slave_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_spi/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/spi_slave_test.elf find-refs --from-sections=.iram0.text diff --git a/components/driver/test_apps/spi/slave/README.md b/components/esp_driver_spi/test_apps/spi/slave/README.md similarity index 100% rename from components/driver/test_apps/spi/slave/README.md rename to components/esp_driver_spi/test_apps/spi/slave/README.md diff --git a/components/driver/test_apps/spi/slave/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/slave/main/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/spi/slave/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/slave/main/CMakeLists.txt diff --git a/components/driver/test_apps/spi/slave/main/test_app_main.c b/components/esp_driver_spi/test_apps/spi/slave/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/spi/slave/main/test_app_main.c rename to components/esp_driver_spi/test_apps/spi/slave/main/test_app_main.c diff --git a/components/driver/test_apps/spi/slave/main/test_spi_slave.c b/components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave.c similarity index 89% rename from components/driver/test_apps/spi/slave/main/test_spi_slave.c rename to components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave.c index 5650233f392..c324358b4b6 100644 --- a/components/driver/test_apps/spi/slave/main/test_spi_slave.c +++ b/components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave.c @@ -36,13 +36,13 @@ static WORD_ALIGNED_ATTR uint8_t slave_rxbuf[320]; static const uint8_t master_send[] = { 0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43 }; static const uint8_t slave_send[] = { 0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0 }; -static inline void int_connect( uint32_t gpio, uint32_t sigo, uint32_t sigi ) +static inline void int_connect(uint32_t gpio, uint32_t sigo, uint32_t sigi) { - esp_rom_gpio_connect_out_signal( gpio, sigo, false, false ); - esp_rom_gpio_connect_in_signal( gpio, sigi, false ); + esp_rom_gpio_connect_out_signal(gpio, sigo, false, false); + esp_rom_gpio_connect_in_signal(gpio, sigi, false); } -static void master_init( spi_device_handle_t *spi) +static void master_init(spi_device_handle_t *spi) { esp_err_t ret; spi_bus_config_t buscfg = { @@ -101,15 +101,15 @@ static void custom_setup(void) memset(slave_rxbuf, 0, sizeof(slave_rxbuf)); //Initialize SPI Master - master_init( &spi ); + master_init(&spi); //Initialize SPI Slave slave_init(); //Do internal connections - int_connect( PIN_NUM_MOSI, spi_periph_signal[TEST_SPI_HOST].spid_out, spi_periph_signal[TEST_SLAVE_HOST].spiq_in ); - int_connect( PIN_NUM_MISO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out, spi_periph_signal[TEST_SPI_HOST].spid_in ); - int_connect( PIN_NUM_CS, spi_periph_signal[TEST_SPI_HOST].spics_out[0], spi_periph_signal[TEST_SLAVE_HOST].spics_in ); - int_connect( PIN_NUM_CLK, spi_periph_signal[TEST_SPI_HOST].spiclk_out, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in ); + int_connect(PIN_NUM_MOSI, spi_periph_signal[TEST_SPI_HOST].spid_out, spi_periph_signal[TEST_SLAVE_HOST].spiq_in); + int_connect(PIN_NUM_MISO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out, spi_periph_signal[TEST_SPI_HOST].spid_in); + int_connect(PIN_NUM_CS, spi_periph_signal[TEST_SPI_HOST].spics_out[0], spi_periph_signal[TEST_SLAVE_HOST].spics_in); + int_connect(PIN_NUM_CLK, spi_periph_signal[TEST_SPI_HOST].spiclk_out, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in); } static void custom_teardown(void) @@ -125,7 +125,7 @@ TEST_CASE("test fullduplex slave with only RX direction", "[spi]") memcpy(master_txbuf, master_send, sizeof(master_send)); - for ( int i = 0; i < 4; i ++ ) { + for (int i = 0; i < 4; i ++) { //slave send spi_slave_transaction_t slave_t; spi_slave_transaction_t *out; @@ -136,29 +136,29 @@ TEST_CASE("test fullduplex slave with only RX direction", "[spi]") slave_t.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; // Colorize RX buffer with known pattern - memset( slave_rxbuf, 0x66, sizeof(slave_rxbuf)); + memset(slave_rxbuf, 0x66, sizeof(slave_rxbuf)); TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY)); //send spi_transaction_t t = {}; t.length = 32 * (i + 1); - if ( t.length != 0 ) { + if (t.length != 0) { t.tx_buffer = master_txbuf; t.rx_buffer = NULL; } - spi_device_transmit( spi, (spi_transaction_t *)&t ); + spi_device_transmit(spi, (spi_transaction_t *)&t); //wait for end TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &out, portMAX_DELAY)); //show result ESP_LOGI(SLAVE_TAG, "trans_len: %d", slave_t.trans_len); - ESP_LOG_BUFFER_HEX( "master tx", t.tx_buffer, t.length / 8 ); - ESP_LOG_BUFFER_HEX( "slave rx", slave_t.rx_buffer, (slave_t.trans_len + 7) / 8); + ESP_LOG_BUFFER_HEX("master tx", t.tx_buffer, t.length / 8); + ESP_LOG_BUFFER_HEX("slave rx", slave_t.rx_buffer, (slave_t.trans_len + 7) / 8); - TEST_ASSERT_EQUAL_HEX8_ARRAY( t.tx_buffer, slave_t.rx_buffer, t.length / 8 ); - TEST_ASSERT_EQUAL( t.length, slave_t.trans_len ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, slave_t.rx_buffer, t.length / 8); + TEST_ASSERT_EQUAL(t.length, slave_t.trans_len); } custom_teardown(); @@ -172,7 +172,7 @@ TEST_CASE("test fullduplex slave with only TX direction", "[spi]") memcpy(slave_txbuf, slave_send, sizeof(slave_send)); - for ( int i = 0; i < 4; i ++ ) { + for (int i = 0; i < 4; i ++) { //slave send spi_slave_transaction_t slave_t; spi_slave_transaction_t *out; @@ -183,29 +183,29 @@ TEST_CASE("test fullduplex slave with only TX direction", "[spi]") slave_t.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; // Colorize RX buffer with known pattern - memset( master_rxbuf, 0x66, sizeof(master_rxbuf)); + memset(master_rxbuf, 0x66, sizeof(master_rxbuf)); TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY)); //send spi_transaction_t t = {}; t.length = 32 * (i + 1); - if ( t.length != 0 ) { + if (t.length != 0) { t.tx_buffer = NULL; t.rx_buffer = master_rxbuf; } - spi_device_transmit( spi, (spi_transaction_t *)&t ); + spi_device_transmit(spi, (spi_transaction_t *)&t); //wait for end TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &out, portMAX_DELAY)); //show result ESP_LOGI(SLAVE_TAG, "trans_len: %d", slave_t.trans_len); - ESP_LOG_BUFFER_HEX( "master rx", t.rx_buffer, t.length / 8 ); - ESP_LOG_BUFFER_HEX( "slave tx", slave_t.tx_buffer, (slave_t.trans_len + 7) / 8); + ESP_LOG_BUFFER_HEX("master rx", t.rx_buffer, t.length / 8); + ESP_LOG_BUFFER_HEX("slave tx", slave_t.tx_buffer, (slave_t.trans_len + 7) / 8); - TEST_ASSERT_EQUAL_HEX8_ARRAY( slave_t.tx_buffer, t.rx_buffer, t.length / 8 ); - TEST_ASSERT_EQUAL( t.length, slave_t.trans_len ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t.tx_buffer, t.rx_buffer, t.length / 8); + TEST_ASSERT_EQUAL(t.length, slave_t.trans_len); } custom_teardown(); @@ -220,7 +220,7 @@ TEST_CASE("test slave send unaligned", "[spi]") memcpy(master_txbuf, master_send, sizeof(master_send)); memcpy(slave_txbuf, slave_send, sizeof(slave_send)); - for ( int i = 0; i < 4; i ++ ) { + for (int i = 0; i < 4; i ++) { //slave send spi_slave_transaction_t slave_t; spi_slave_transaction_t *out; @@ -231,33 +231,33 @@ TEST_CASE("test slave send unaligned", "[spi]") slave_t.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; // Colorize RX buffers with known pattern - memset( master_rxbuf, 0x66, sizeof(master_rxbuf)); - memset( slave_rxbuf, 0x66, sizeof(slave_rxbuf)); + memset(master_rxbuf, 0x66, sizeof(master_rxbuf)); + memset(slave_rxbuf, 0x66, sizeof(slave_rxbuf)); TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY)); //send spi_transaction_t t = {}; t.length = 32 * (i + 1); - if ( t.length != 0 ) { + if (t.length != 0) { t.tx_buffer = master_txbuf + i; t.rx_buffer = master_rxbuf + i; } - spi_device_transmit( spi, (spi_transaction_t *)&t ); + spi_device_transmit(spi, (spi_transaction_t *)&t); //wait for end TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &out, portMAX_DELAY)); //show result ESP_LOGI(SLAVE_TAG, "trans_len: %d", slave_t.trans_len); - ESP_LOG_BUFFER_HEX( "master tx", t.tx_buffer, t.length / 8 ); - ESP_LOG_BUFFER_HEX( "master rx", t.rx_buffer, t.length / 8 ); - ESP_LOG_BUFFER_HEX( "slave tx", slave_t.tx_buffer, (slave_t.trans_len + 7) / 8); - ESP_LOG_BUFFER_HEX( "slave rx", slave_t.rx_buffer, (slave_t.trans_len + 7) / 8); - - TEST_ASSERT_EQUAL_HEX8_ARRAY( t.tx_buffer, slave_t.rx_buffer, t.length / 8 ); - TEST_ASSERT_EQUAL_HEX8_ARRAY( slave_t.tx_buffer, t.rx_buffer, t.length / 8 ); - TEST_ASSERT_EQUAL( t.length, slave_t.trans_len ); + ESP_LOG_BUFFER_HEX("master tx", t.tx_buffer, t.length / 8); + ESP_LOG_BUFFER_HEX("master rx", t.rx_buffer, t.length / 8); + ESP_LOG_BUFFER_HEX("slave tx", slave_t.tx_buffer, (slave_t.trans_len + 7) / 8); + ESP_LOG_BUFFER_HEX("slave rx", slave_t.rx_buffer, (slave_t.trans_len + 7) / 8); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, slave_t.rx_buffer, t.length / 8); + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t.tx_buffer, t.rx_buffer, t.length / 8); + TEST_ASSERT_EQUAL(t.length, slave_t.trans_len); } custom_teardown(); @@ -409,7 +409,7 @@ static void test_slave_iram_master_normal(void) uint8_t *master_send = heap_caps_malloc(TEST_BUFFER_SZ, MALLOC_CAP_DMA); uint8_t *master_recv = heap_caps_calloc(1, TEST_BUFFER_SZ, MALLOC_CAP_DMA); uint8_t *master_exp = heap_caps_malloc(TEST_BUFFER_SZ, MALLOC_CAP_DEFAULT); - get_tx_buffer(1001, master_send, master_exp, TEST_BUFFER_SZ); + test_fill_random_to_buffers_dualboard(1001, master_send, master_exp, TEST_BUFFER_SZ); spi_transaction_t trans_cfg = { .tx_buffer = master_send, .rx_buffer = master_recv, @@ -490,7 +490,7 @@ static IRAM_ATTR void test_slave_isr_iram(void) uint8_t *slave_iram_send = heap_caps_aligned_alloc(64, TEST_BUFFER_SZ, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *slave_iram_recv = heap_caps_aligned_alloc(64, TEST_BUFFER_SZ, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *slave_iram_exp = heap_caps_malloc(TEST_BUFFER_SZ, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL); - get_tx_buffer(1001, slave_iram_exp, slave_iram_send, TEST_BUFFER_SZ); + test_fill_random_to_buffers_dualboard(1001, slave_iram_exp, slave_iram_send, TEST_BUFFER_SZ); spi_slave_transaction_t trans_cfg[TEST_IRAM_TRANS_NUM] = {0}; unity_wait_for_signal("Master ready"); @@ -570,7 +570,7 @@ static IRAM_ATTR void spi_slave_trans_in_isr(void) uint8_t *slave_isr_send = heap_caps_aligned_alloc(64, TEST_BUFFER_SZ, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *slave_isr_recv = heap_caps_aligned_alloc(64, TEST_BUFFER_SZ, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *slave_isr_exp = heap_caps_malloc(TEST_BUFFER_SZ, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL); - get_tx_buffer(1001, slave_isr_exp, slave_isr_send, TEST_BUFFER_SZ); + test_fill_random_to_buffers_dualboard(1001, slave_isr_exp, slave_isr_send, TEST_BUFFER_SZ); spi_slave_transaction_t trans_cfg = { .tx_buffer = slave_isr_send, .rx_buffer = slave_isr_recv, @@ -652,10 +652,10 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void) uint8_t *slave_isr_send = heap_caps_aligned_alloc(64, TEST_BUFFER_SZ, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *slave_isr_recv = heap_caps_aligned_alloc(64, TEST_BUFFER_SZ, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); - uint8_t *dummy_data = heap_caps_aligned_alloc(64, 64*2, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + uint8_t *dummy_data = heap_caps_aligned_alloc(64, 64 * 2, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *slave_isr_exp = heap_caps_malloc(TEST_BUFFER_SZ, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL); - get_tx_buffer(1001, slave_isr_exp, slave_isr_send, TEST_BUFFER_SZ); - get_tx_buffer(1001, dummy_data, dummy_data + 64, 64); + test_fill_random_to_buffers_dualboard(1001, slave_isr_exp, slave_isr_send, TEST_BUFFER_SZ); + test_fill_random_to_buffers_dualboard(1001, dummy_data, dummy_data + 64, 64); spi_slave_transaction_t trans_cfg = { .tx_buffer = slave_isr_send, .rx_buffer = slave_isr_recv, @@ -664,6 +664,8 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void) }; unity_wait_for_signal("Master ready"); + queue_reset_isr_trans_cnt = 0; + test_queue_reset_isr_fail = 0; for (uint8_t i = 0; i < 2; i++) { dummy_trans[i].tx_buffer = dummy_data + i * 64; dummy_trans[i].rx_buffer = dummy_data + i * 64; @@ -672,12 +674,12 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void) } // start a trans by normal API first to trigger spi isr spi_slave_queue_trans(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY); - // spi_flash_disable_interrupts_caches_and_other_cpu(); + spi_flash_disable_interrupts_caches_and_other_cpu(); esp_rom_printf(DRAM_STR("Send signal: [Slave ready]!\n")); while (queue_reset_isr_trans_cnt <= TEST_IRAM_TRANS_NUM) { esp_rom_delay_us(10); } - // spi_flash_enable_interrupts_caches_and_other_cpu(); + spi_flash_enable_interrupts_caches_and_other_cpu(); if (test_queue_reset_isr_fail) { TEST_FAIL(); } diff --git a/components/driver/test_apps/spi/slave/main/test_spi_slave_queue.c b/components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave_queue.c similarity index 97% rename from components/driver/test_apps/spi/slave/main/test_spi_slave_queue.c rename to components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave_queue.c index 1550fca913e..52967059eef 100644 --- a/components/driver/test_apps/spi/slave/main/test_spi_slave_queue.c +++ b/components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave_queue.c @@ -49,7 +49,7 @@ static void test_master(void) mst_tx_buf[i] = heap_caps_calloc(TEST_BUF_SIZE, 1, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); mst_rx_buf[i] = heap_caps_calloc(TEST_BUF_SIZE, 1, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); slv_tx_buf[i] = heap_caps_calloc(TEST_BUF_SIZE, 1, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); - get_tx_buffer(test_seed, mst_tx_buf[i], slv_tx_buf[i], TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(test_seed, mst_tx_buf[i], slv_tx_buf[i], TEST_BUF_SIZE); } //Trans0 @@ -133,7 +133,7 @@ static void test_slave(void) slv_tx_buf[i] = heap_caps_calloc(TEST_BUF_SIZE, 1, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); slv_rx_buf[i] = heap_caps_calloc(TEST_BUF_SIZE, 1, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); mst_tx_buf[i] = heap_caps_calloc(TEST_BUF_SIZE, 1, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); - get_tx_buffer(test_seed, mst_tx_buf[i], slv_tx_buf[i], TEST_BUF_SIZE); + test_fill_random_to_buffers_dualboard(test_seed, mst_tx_buf[i], slv_tx_buf[i], TEST_BUF_SIZE); } spi_slave_transaction_t trans[TEST_TIMES] = {}; diff --git a/components/driver/test_apps/spi/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/spi/slave/pytest_spi_slave.py similarity index 100% rename from components/driver/test_apps/spi/slave/pytest_spi_slave.py rename to components/esp_driver_spi/test_apps/spi/slave/pytest_spi_slave.py diff --git a/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.defaults b/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.defaults new file mode 100644 index 00000000000..250a29bc45b --- /dev/null +++ b/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.defaults @@ -0,0 +1,2 @@ +# don't delete. +# used for CI to compile a default config when 'sdkconfig.ci.xxxx' is exist diff --git a/components/driver/test_apps/spi/slave/sdkconfig.ci.iram_safe b/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/spi/slave/sdkconfig.ci.iram_safe rename to components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/spi/slave/sdkconfig.defaults b/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/spi/slave/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/spi/slave/sdkconfig.defaults diff --git a/components/driver/test_apps/spi/slave_hd/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/slave_hd/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/spi/slave_hd/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/slave_hd/CMakeLists.txt diff --git a/components/driver/test_apps/spi/slave_hd/README.md b/components/esp_driver_spi/test_apps/spi/slave_hd/README.md similarity index 100% rename from components/driver/test_apps/spi/slave_hd/README.md rename to components/esp_driver_spi/test_apps/spi/slave_hd/README.md diff --git a/components/driver/test_apps/spi/slave_hd/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/spi/slave_hd/main/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/spi/slave_hd/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/spi/slave_hd/main/CMakeLists.txt diff --git a/components/driver/test_apps/spi/slave_hd/main/test_app_main.c b/components/esp_driver_spi/test_apps/spi/slave_hd/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/spi/slave_hd/main/test_app_main.c rename to components/esp_driver_spi/test_apps/spi/slave_hd/main/test_app_main.c diff --git a/components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c b/components/esp_driver_spi/test_apps/spi/slave_hd/main/test_spi_slave_hd.c similarity index 88% rename from components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c rename to components/esp_driver_spi/test_apps/spi/slave_hd/main/test_spi_slave_hd.c index eb547e0debf..00622e78b86 100644 --- a/components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c +++ b/components/esp_driver_spi/test_apps/spi/slave_hd/main/test_spi_slave_hd.c @@ -12,6 +12,7 @@ #include "test_spi_utils.h" #include "soc/spi_periph.h" #include "esp_serial_slave_link/essl_spi.h" +#include "test_dualboard_utils.h" #if SOC_SPI_SUPPORT_SLAVE_HD_VER2 #include "driver/spi_slave_hd.h" @@ -48,16 +49,16 @@ static uint32_t get_hd_flags(void) ESP_LOGI("io mode", "%d", flag_id); switch (flag_id) { - case 1: - return SPI_TRANS_MODE_DIO; - case 2: - return SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_DIOQIO_ADDR; - case 3: - return SPI_TRANS_MODE_QIO; - case 4: - return SPI_TRANS_MODE_QIO | SPI_TRANS_MODE_DIOQIO_ADDR; - default: - return 0; + case 1: + return SPI_TRANS_MODE_DIO; + case 2: + return SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_DIOQIO_ADDR; + case 3: + return SPI_TRANS_MODE_QIO; + case 4: + return SPI_TRANS_MODE_QIO | SPI_TRANS_MODE_DIOQIO_ADDR; + default: + return 0; } } @@ -79,7 +80,7 @@ void config_single_board_test_pin(void) static void init_master_hd(spi_device_handle_t* spi, const spitest_param_set_t* config, int freq) { spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); - bus_cfg.max_transfer_sz = TEST_DMA_MAX_SIZE*30; + bus_cfg.max_transfer_sz = TEST_DMA_MAX_SIZE * 30; bus_cfg.quadhd_io_num = PIN_NUM_HD; bus_cfg.quadwp_io_num = PIN_NUM_WP; #if defined(TEST_MASTER_GPIO_MATRIX) && CONFIG_IDF_TARGET_ESP32S2 @@ -101,7 +102,7 @@ static void init_master_hd(spi_device_handle_t* spi, const spitest_param_set_t* static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callback_config_t* callback) { spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); - bus_cfg.max_transfer_sz = TEST_DMA_MAX_SIZE*30; + bus_cfg.max_transfer_sz = TEST_DMA_MAX_SIZE * 30; bus_cfg.quadwp_io_num = -1; bus_cfg.quadhd_io_num = -1; #ifdef TEST_SLAVE_GPIO_MATRIX @@ -116,18 +117,18 @@ static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callbac if (callback) { slave_hd_cfg.cb_config = *callback; } else { - slave_hd_cfg.cb_config = (spi_slave_hd_callback_config_t){}; + slave_hd_cfg.cb_config = (spi_slave_hd_callback_config_t) {}; } TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg)); } static void test_hd_init(void** arg) { - TEST_ASSERT(*arg==NULL); + TEST_ASSERT(*arg == NULL); *arg = heap_caps_malloc(sizeof(testhd_context_t), MALLOC_CAP_DMA); - assert(((int)arg%4)==0); + assert(((int)arg % 4) == 0); testhd_context_t* context = (testhd_context_t*)*arg; - TEST_ASSERT(context!=NULL); + TEST_ASSERT(context != NULL); context->ev_rdbuf = xSemaphoreCreateBinary(); context->ev_wrbuf = xSemaphoreCreateBinary(); @@ -143,7 +144,7 @@ static void test_hd_deinit(void* arg) esp_err_t wait_wrbuf_sig(testhd_context_t* context, TickType_t wait) { BaseType_t r = xSemaphoreTake(context->ev_wrbuf, wait); - if (r==pdTRUE) { + if (r == pdTRUE) { return ESP_OK; } else { return ESP_ERR_TIMEOUT; @@ -153,7 +154,7 @@ esp_err_t wait_wrbuf_sig(testhd_context_t* context, TickType_t wait) esp_err_t wait_rdbuf_sig(testhd_context_t* context, TickType_t wait) { BaseType_t r = xSemaphoreTake(context->ev_rdbuf, wait); - if (r==pdTRUE) { + if (r == pdTRUE) { return ESP_OK; } else { return ESP_ERR_TIMEOUT; @@ -211,14 +212,19 @@ static void test_hd_start(spi_device_handle_t *spi, int freq, const spitest_para check_no_rx(ctx); check_no_tx(ctx); - srand(9322); - for (int i = 0; i < TEST_DMA_MAX_SIZE; i++) ctx->slave_rddma_buf[i] = rand(); - for (int i = 0; i < TEST_DMA_MAX_SIZE; i++) ctx->master_wrdma_buf[i] = rand(); + for (int i = 0; i < TEST_DMA_MAX_SIZE; i++) { + ctx->slave_rddma_buf[i] = rand(); + } + for (int i = 0; i < TEST_DMA_MAX_SIZE; i++) { + ctx->master_wrdma_buf[i] = rand(); + } int pos = rand() % TEST_DMA_MAX_SIZE; int len = rand() % TEST_DMA_MAX_SIZE + 1; - if (pos + len > TEST_DMA_MAX_SIZE) len = TEST_DMA_MAX_SIZE - pos; + if (pos + len > TEST_DMA_MAX_SIZE) { + len = TEST_DMA_MAX_SIZE - pos; + } ESP_LOGI("rddma_load_len", "%d", len); ctx->tx_data = (spi_slave_hd_data_t) { @@ -238,7 +244,6 @@ static void test_hd_start(spi_device_handle_t *spi, int freq, const spitest_para TEST_ESP_OK(err); } - #define REG_REGION_SIZE SOC_SPI_MAXIMUM_BUFFER_SIZE void check_no_signal(testhd_context_t* context) @@ -253,8 +258,10 @@ void check_no_signal(testhd_context_t* context) void test_wrdma(testhd_context_t* ctx, const spitest_param_set_t *cfg, spi_device_handle_t spi) { int pos = rand() % TEST_DMA_MAX_SIZE; - int len = rand() % TEST_DMA_MAX_SIZE+1; - if (pos+len > TEST_DMA_MAX_SIZE) len = TEST_DMA_MAX_SIZE - pos; + int len = rand() % TEST_DMA_MAX_SIZE + 1; + if (pos + len > TEST_DMA_MAX_SIZE) { + len = TEST_DMA_MAX_SIZE - pos; + } int test_seg_size = len;//TEST_SEG_SIZE; ESP_LOGW("test_wrdma", "len: %d, seg_size: %d", len, test_seg_size); @@ -283,7 +290,6 @@ void test_rddma(testhd_context_t* ctx, const spitest_param_set_t* cfg, spi_devic int len; int test_seg_size; - len = ctx->tx_data.len; test_seg_size = TEST_SEG_SIZE; @@ -299,8 +305,10 @@ void test_rddma(testhd_context_t* ctx, const spitest_param_set_t* cfg, spi_devic spitest_cmp_or_dump(data_expected, ctx->master_rddma_buf, len); int pos = rand() % TEST_DMA_MAX_SIZE; - len = rand() % TEST_DMA_MAX_SIZE+1; - if (pos + len > TEST_DMA_MAX_SIZE) len = TEST_DMA_MAX_SIZE - pos; + len = rand() % TEST_DMA_MAX_SIZE + 1; + if (pos + len > TEST_DMA_MAX_SIZE) { + len = TEST_DMA_MAX_SIZE - pos; + } ctx->tx_data = (spi_slave_hd_data_t) { .data = &ctx->slave_rddma_buf[pos], @@ -321,8 +329,12 @@ static void test_hd_loop(const void* arg1, void* arg2) for (int j = 0; ; j++) { spi_device_handle_t spi; const int freq = timing_speed_array[j]; - if (freq==0) break; - if (test_cfg->freq_limit && freq > test_cfg->freq_limit) break; + if (freq == 0) { + break; + } + if (test_cfg->freq_limit && freq > test_cfg->freq_limit) { + break; + } ESP_LOGI(MASTER_TAG, "======> %dk", freq / 1000); @@ -333,8 +345,8 @@ static void test_hd_loop(const void* arg1, void* arg2) uint8_t recv_buffer[REG_REGION_SIZE]; srand(123); - uint32_t mem[(REG_REGION_SIZE/4)]; - for (int i = 0; i < (REG_REGION_SIZE/4); i++) { + uint32_t mem[(REG_REGION_SIZE / 4)]; + for (int i = 0; i < (REG_REGION_SIZE / 4); i++) { mem[i] = rand(); } mem_ptr = (uint8_t*)mem; @@ -344,16 +356,18 @@ static void test_hd_loop(const void* arg1, void* arg2) spi_slave_hd_write_buffer(TEST_SLAVE_HOST, 0, (uint8_t *) mem, SOC_SPI_MAXIMUM_BUFFER_SIZE); srand(123); - for (int i = 0; i < (REG_REGION_SIZE/4); i++) { + for (int i = 0; i < (REG_REGION_SIZE / 4); i++) { TEST_ASSERT(mem[i] == rand()); } check_no_signal(context); test_rddma(context, test_cfg, spi); for (int i = 0; i < 128; i ++) { - int pos = rand()%REG_REGION_SIZE; - int len = rand()%REG_REGION_SIZE+1; - if (len+pos>REG_REGION_SIZE) len = REG_REGION_SIZE-pos; + int pos = rand() % REG_REGION_SIZE; + int len = rand() % REG_REGION_SIZE + 1; + if (len + pos > REG_REGION_SIZE) { + len = REG_REGION_SIZE - pos; + } memset(recv_buffer, 0xcc, sizeof(recv_buffer)); @@ -389,13 +403,15 @@ static void test_hd_loop(const void* arg1, void* arg2) srand(466); for (int i = 0; i < 64; i ++) { ESP_LOGI("temp_i", "^^^^^^^^^^^^^^^^ %d ^^^^^^^^^^", i); - for (int j = 0; j < (REG_REGION_SIZE/4); j++) { + for (int j = 0; j < (REG_REGION_SIZE / 4); j++) { mem[j] = rand(); } for (int k = 0; k < 2; k++) { int pos = rand() % REG_REGION_SIZE; int len = rand() % REG_REGION_SIZE + 1; - if (len + pos > REG_REGION_SIZE) len = REG_REGION_SIZE - pos; + if (len + pos > REG_REGION_SIZE) { + len = REG_REGION_SIZE - pos; + } printf("pos: %d, len: %d\n", pos, len); @@ -454,37 +470,41 @@ static int test_freq_hd[] = { #define TEST_HD_IN_CONTINUOUS_MODE true static spitest_param_set_t hd_conf[] = { - { .pset_name = "MODE0", + { + .pset_name = "MODE0", .freq_list = test_freq_hd, - .dup = FULL_DUPLEX, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 0, + .dup = FULL_DUPLEX, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 0, }, - { .pset_name = "MODE1", + { + .pset_name = "MODE1", .freq_list = test_freq_hd, - .dup = FULL_DUPLEX, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 1, + .dup = FULL_DUPLEX, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 1, }, - { .pset_name = "MODE2", + { + .pset_name = "MODE2", .freq_list = test_freq_hd, - .dup = FULL_DUPLEX, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 2, + .dup = FULL_DUPLEX, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 2, }, - { .pset_name = "MODE3", + { + .pset_name = "MODE3", .freq_list = test_freq_hd, - .dup = FULL_DUPLEX, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 3, + .dup = FULL_DUPLEX, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 3, }, }; TEST_SPI_HD(HD, hd_conf); @@ -500,7 +520,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]" { spi_device_handle_t spi; spitest_param_set_t *cfg = &hd_conf[0]; - int freq = 100*1000; // the frequency should be small enough for the slave to prepare new trans + int freq = 100 * 1000; // the frequency should be small enough for the slave to prepare new trans init_master_hd(&spi, cfg, freq); @@ -519,8 +539,8 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]" memset(slave_recv_buf, 0xcc, send_buf_size * 2); memset(master_recv_buf, 0xcc, send_buf_size * 2); - srand (939); - for (int i = 0; i< send_buf_size * 2; i++) { + srand(939); + for (int i = 0; i < send_buf_size * 2; i++) { master_send_buf[i] = rand(); slave_send_buf[i] = rand(); } @@ -630,7 +650,7 @@ static void hd_master(void) WORD_ALIGNED_ATTR uint8_t *master_recv_buf = calloc(1, send_buf_size * 2); //This buffer is used for 2-board test and should be assigned totally the same as the ``hd_slave`` does. WORD_ALIGNED_ATTR uint8_t *slave_send_buf = malloc(send_buf_size * 2); - get_tx_buffer(199, master_send_buf, slave_send_buf, send_buf_size * 2); + test_fill_random_to_buffers_dualboard(199, master_send_buf, slave_send_buf, send_buf_size * 2); //This is the same as the ``hd_slave`` sets. int trans_len[] = {5, send_buf_size}; @@ -642,7 +662,6 @@ static void hd_master(void) unity_wait_for_signal("slave ready"); essl_spi_wrdma(spi, master_send_buf + send_buf_size, send_buf_size, 5, 0); - unity_wait_for_signal("slave ready"); essl_spi_rddma(spi, master_recv_buf, send_buf_size, -1, 0); spitest_cmp_or_dump(slave_send_buf, master_recv_buf, trans_len[0]); @@ -651,7 +670,6 @@ static void hd_master(void) essl_spi_rddma(spi, master_recv_buf + send_buf_size, send_buf_size, 5, 0); spitest_cmp_or_dump(slave_send_buf + send_buf_size, master_recv_buf + send_buf_size, trans_len[1]); - free(master_recv_buf); free(master_send_buf); free(slave_send_buf); @@ -683,7 +701,7 @@ static void hd_slave(void) WORD_ALIGNED_ATTR uint8_t *slave_recv_buf = calloc(1, send_buf_size * 2); //This buffer is used for 2-board test and should be assigned totally the same as the ``hd_master`` does. WORD_ALIGNED_ATTR uint8_t *master_send_buf = malloc(send_buf_size * 2); - get_tx_buffer(199, master_send_buf, slave_send_buf, send_buf_size * 2); + test_fill_random_to_buffers_dualboard(199, master_send_buf, slave_send_buf, send_buf_size * 2); //make the first transaction shorter than the actual trans length of the master, so that the second one will be loaded while the master is still doing the first transaction. int trans_len[] = {5, send_buf_size}; @@ -750,7 +768,8 @@ TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: segment mode, master sends too long", #define BUF_SIZE 256 -static void hd_master_quad(void){ +static void hd_master_quad(void) +{ spi_bus_config_t bus_cfg = { .miso_io_num = PIN_NUM_MISO, .mosi_io_num = PIN_NUM_MOSI, @@ -775,7 +794,7 @@ static void hd_master_quad(void){ WORD_ALIGNED_ATTR uint8_t *master_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA); //This buffer is used for 2-board test and should be assigned totally the same as the ``hd_slave`` does. WORD_ALIGNED_ATTR uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); - get_tx_buffer(199, master_send_buf, slave_send_buf, BUF_SIZE); + test_fill_random_to_buffers_dualboard(199, master_send_buf, slave_send_buf, BUF_SIZE); unity_send_signal("Master ready"); unity_wait_for_signal("slave ready"); @@ -788,7 +807,7 @@ static void hd_master_quad(void){ essl_spi_rddma(spi, master_recv_buf, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); unity_wait_for_signal("slave ready"); - essl_spi_rddma(spi, master_recv_buf+ BUF_SIZE / 2, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); + essl_spi_rddma(spi, master_recv_buf + BUF_SIZE / 2, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); ESP_LOG_BUFFER_HEX("slave send", slave_send_buf, BUF_SIZE); ESP_LOG_BUFFER_HEX("master recv", master_recv_buf, BUF_SIZE); @@ -802,7 +821,8 @@ static void hd_master_quad(void){ master_free_device_bus(spi); } -static void hd_slave_quad(void){ +static void hd_slave_quad(void) +{ spi_bus_config_t bus_cfg = { .miso_io_num = PIN_NUM_MISO, @@ -829,7 +849,7 @@ static void hd_slave_quad(void){ WORD_ALIGNED_ATTR uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA); //This buffer is used for 2-board test and should be assigned totally the same as the ``hd_master`` does. WORD_ALIGNED_ATTR uint8_t *master_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); - get_tx_buffer(199, master_send_buf, slave_send_buf, BUF_SIZE); + test_fill_random_to_buffers_dualboard(199, master_send_buf, slave_send_buf, BUF_SIZE); int trans_len = BUF_SIZE / 2; spi_slave_hd_data_t slave_trans[4] = { @@ -839,7 +859,7 @@ static void hd_slave_quad(void){ .len = (trans_len + 3) & (~3), }, { - .data = slave_recv_buf+BUF_SIZE/2, + .data = slave_recv_buf + BUF_SIZE / 2, .len = (trans_len + 3) & (~3), }, //send @@ -847,8 +867,8 @@ static void hd_slave_quad(void){ .data = slave_send_buf, .len = (trans_len + 3) & (~3), }, - { - .data = slave_send_buf+BUF_SIZE/2, + { + .data = slave_send_buf + BUF_SIZE / 2, .len = (trans_len + 3) & (~3), }, }; @@ -887,15 +907,14 @@ TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test ", "[spi_ms][test_env=generic_multi #endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) - - //***************************************TEST FOR APPEND MODE******************************************// -#define TEST_APPEND_CACHE_SIZE 4 -#define TEST_TRANS_LEN TEST_DMA_MAX_SIZE +#define TEST_APPEND_NUM 4 +#define TEST_TRANS_LEN TEST_DMA_MAX_SIZE -void prepare_data(uint8_t *buff, uint32_t len, int8_t diff){ +void prepare_data(uint8_t *buff, uint32_t len, int8_t diff) +{ buff[0] = random(); - for (int line_index=1; line_index TEST_TRANS_LEN) { trans_len = TEST_TRANS_LEN; } - slave_rx_trans[cache_instans].data = heap_caps_calloc(1, TEST_TRANS_LEN, MALLOC_CAP_DMA); - TEST_ASSERT_NOT_NULL(slave_rx_trans[cache_instans].data); - slave_rx_trans[cache_instans].len = trans_len; - TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_rx_trans[cache_instans], portMAX_DELAY)); + slave_rx_trans[append_idx].data = heap_caps_aligned_calloc(4, 1, TEST_TRANS_LEN, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(slave_rx_trans[append_idx].data); + slave_rx_trans[append_idx].len = trans_len; + TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_rx_trans[append_idx], portMAX_DELAY)); } for (int trans_num = 1; trans_num <= 8; trans_num ++) { @@ -941,7 +960,7 @@ void slave_run_append(void) ESP_LOG_BUFFER_HEX_LEVEL("slave exp", slave_exp, trans_len, ESP_LOG_DEBUG); spitest_cmp_or_dump(slave_exp, ret_trans->data, trans_len); - if (trans_num <= TEST_APPEND_CACHE_SIZE) { + if (trans_num <= TEST_APPEND_NUM) { // append one more transaction int new_append_len = trans_len << 4; if (new_append_len > TEST_TRANS_LEN) { @@ -957,16 +976,16 @@ void slave_run_append(void) free(slave_exp); //------------------------------------tx direction------------------------------ - spi_slave_hd_data_t slave_tx_trans[TEST_APPEND_CACHE_SIZE] = {}; - for (uint32_t cache_instans = 0; cache_instans < TEST_APPEND_CACHE_SIZE; cache_instans ++) { - int trans_len = 16 << (cache_instans+1); + spi_slave_hd_data_t slave_tx_trans[TEST_APPEND_NUM] = {}; + for (uint32_t append_idx = 0; append_idx < TEST_APPEND_NUM; append_idx ++) { + int trans_len = 16 << (append_idx + 1); if (trans_len >= TEST_TRANS_LEN) { trans_len = TEST_TRANS_LEN; } - slave_tx_trans[cache_instans].data = slave_rx_trans[cache_instans].data; - slave_tx_trans[cache_instans].len = trans_len; - prepare_data(slave_tx_trans[cache_instans].data, trans_len, -3); - TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_tx_trans[cache_instans], portMAX_DELAY)); + slave_tx_trans[append_idx].data = slave_rx_trans[append_idx].data; + slave_tx_trans[append_idx].len = trans_len; + prepare_data(slave_tx_trans[append_idx].data, trans_len, -3); + TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_tx_trans[append_idx], portMAX_DELAY)); } //Get one result and load a new transaction @@ -976,7 +995,7 @@ void slave_run_append(void) ESP_LOGI("slave", "trasacted len: %d", ret_trans->len); ESP_LOG_BUFFER_HEX_LEVEL("slave tx", ret_trans->data, ret_trans->len, ESP_LOG_DEBUG); - if (trans_num <= TEST_APPEND_CACHE_SIZE) { + if (trans_num <= TEST_APPEND_NUM) { // append one more transaction int new_append_len = 16 << (trans_num + 4); if (new_append_len > TEST_TRANS_LEN) { @@ -989,7 +1008,9 @@ void slave_run_append(void) } } printf("================Master Rx Done==================\n"); - for (int i = 0; i < TEST_APPEND_CACHE_SIZE; i++) free(slave_tx_trans[i].data); + for (int i = 0; i < TEST_APPEND_NUM; i++) { + free(slave_tx_trans[i].data); + } spi_slave_hd_deinit(TEST_SPI_HOST); } diff --git a/components/driver/test_apps/spi/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/spi/slave_hd/pytest_spi_slave_hd.py similarity index 100% rename from components/driver/test_apps/spi/slave_hd/pytest_spi_slave_hd.py rename to components/esp_driver_spi/test_apps/spi/slave_hd/pytest_spi_slave_hd.py diff --git a/components/driver/test_apps/spi/slave_hd/sdkconfig.defaults b/components/esp_driver_spi/test_apps/spi/slave_hd/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/spi/slave_hd/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/spi/slave_hd/sdkconfig.defaults diff --git a/components/esp_driver_tsens/CMakeLists.txt b/components/esp_driver_tsens/CMakeLists.txt new file mode 100644 index 00000000000..b202242c7ff --- /dev/null +++ b/components/esp_driver_tsens/CMakeLists.txt @@ -0,0 +1,11 @@ +set(srcs) +set(priv_req efuse) +set(public_include "include") +if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED) + list(APPEND srcs "src/temperature_sensor.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES ${priv_req} + ) diff --git a/components/esp_driver_tsens/Kconfig b/components/esp_driver_tsens/Kconfig new file mode 100644 index 00000000000..541e44c8223 --- /dev/null +++ b/components/esp_driver_tsens/Kconfig @@ -0,0 +1,27 @@ +menu "ESP-Driver:Temperature Sensor Configurations" + depends on SOC_TEMP_SENSOR_SUPPORTED + + config TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN + bool "Suppress legacy driver deprecated warning" + default n + help + Wether to suppress the deprecation warnings when using legacy temperature sensor driver + (driver/temp_sensor.h). If you want to continue using the legacy driver, + and don't want to see related deprecation warnings, you can enable this option. + + config TEMP_SENSOR_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for temperature sensor driver. + Note that, this option only controls the temperature sensor driver log, won't affect other drivers. + + config TEMP_SENSOR_ISR_IRAM_SAFE + depends on SOC_TEMPERATURE_SENSOR_INTR_SUPPORT + bool "Temperature sensor ISR IRAM-Safe" + default n + help + Ensure the Temperature Sensor interrupt is IRAM-Safe by allowing the interrupt handler to be + executable when the cache is disabled (e.g. SPI Flash write). + +endmenu # TEMP_SENSOR Configuration diff --git a/components/driver/temperature_sensor/include/driver/temperature_sensor.h b/components/esp_driver_tsens/include/driver/temperature_sensor.h similarity index 93% rename from components/driver/temperature_sensor/include/driver/temperature_sensor.h rename to components/esp_driver_tsens/include/driver/temperature_sensor.h index ef05f3f0685..ef8d653b650 100644 --- a/components/driver/temperature_sensor/include/driver/temperature_sensor.h +++ b/components/esp_driver_tsens/include/driver/temperature_sensor.h @@ -97,11 +97,20 @@ esp_err_t temperature_sensor_get_celsius(temperature_sensor_handle_t tsens, floa #if SOC_TEMPERATURE_SENSOR_INTR_SUPPORT +/** + * @brief Enum for temperature sensor interrupt condition. + */ +typedef enum { + TEMPERATURE_VAL_HIGHER_THAN_HIGH_THRESHOLD = 0, /*!< temperature sensor value is higher than high threshold*/ + TEMPERATURE_VAL_LOWER_THAN_LOW_THRESHOLD = 1, /*!< temperature sensor value is lower than low threshold*/ +} temperature_val_intr_condition_t; + /** * @brief Temperature sensor event data */ typedef struct { int celsius_value; /**< Celsius value in interrupt callback. */ + temperature_val_intr_condition_t intr_condition; /*!< Can be used to judge temperature sensor interrupts in which reason*/ } temperature_sensor_threshold_event_data_t; /** diff --git a/components/driver/temperature_sensor/temperature_sensor.c b/components/esp_driver_tsens/src/temperature_sensor.c similarity index 96% rename from components/driver/temperature_sensor/temperature_sensor.c rename to components/esp_driver_tsens/src/temperature_sensor.c index 51d5e59e1d8..1e0a3a7e10a 100644 --- a/components/driver/temperature_sensor/temperature_sensor.c +++ b/components/esp_driver_tsens/src/temperature_sensor.c @@ -76,8 +76,10 @@ static void IRAM_ATTR temperature_sensor_isr(void *arg) temperature_sensor_ll_clear_intr(); bool cbs_yield = false; temperature_sensor_handle_t tsens = (temperature_sensor_handle_t) arg; + temperature_val_intr_condition_t intr_condition = (temperature_sensor_ll_get_wakeup_reason() == 1 ? TEMPERATURE_VAL_HIGHER_THAN_HIGH_THRESHOLD : TEMPERATURE_VAL_LOWER_THAN_LOW_THRESHOLD); temperature_sensor_threshold_event_data_t data = { .celsius_value = s_temperature_regval_2_celsius(tsens, temperature_sensor_ll_get_raw_value()), + .intr_condition = intr_condition, }; if (tsens->threshold_cbs) { if (tsens->threshold_cbs(tsens, &data, tsens->cb_user_arg)) { @@ -241,7 +243,7 @@ esp_err_t temperature_sensor_get_celsius(temperature_sensor_handle_t tsens, floa static uint8_t s_temperature_celsius_2_regval(temperature_sensor_handle_t tsens, int8_t celsius) { - return (uint8_t)((celsius + TEMPERATURE_SENSOR_LL_OFFSET_FACTOR + TEMPERATURE_SENSOR_LL_DAC_FACTOR * tsens->tsens_attribute->offset)/TEMPERATURE_SENSOR_LL_ADC_FACTOR); + return (uint8_t)((celsius + TEMPERATURE_SENSOR_LL_OFFSET_FACTOR + TEMPERATURE_SENSOR_LL_DAC_FACTOR * tsens->tsens_attribute->offset) / TEMPERATURE_SENSOR_LL_ADC_FACTOR); } IRAM_ATTR static int8_t s_temperature_regval_2_celsius(temperature_sensor_handle_t tsens, uint8_t regval) @@ -303,8 +305,8 @@ esp_err_t temperature_sensor_register_callbacks(temperature_sensor_handle_t tsen // lazy install interrupt service. if (!tsens->temp_sensor_isr_handle) { ret = esp_intr_alloc_intrstatus(ETS_APB_ADC_INTR_SOURCE, isr_flags, - (uint32_t)temperature_sensor_ll_get_intr_status(), - TEMPERATURE_SENSOR_LL_INTR_MASK, temperature_sensor_isr, tsens, &tsens->temp_sensor_isr_handle); + (uint32_t)temperature_sensor_ll_get_intr_status(), + TEMPERATURE_SENSOR_LL_INTR_MASK, temperature_sensor_isr, tsens, &tsens->temp_sensor_isr_handle); } if (cbs->on_threshold != NULL) { diff --git a/components/driver/temperature_sensor/temperature_sensor_private.h b/components/esp_driver_tsens/src/temperature_sensor_private.h similarity index 99% rename from components/driver/temperature_sensor/temperature_sensor_private.h rename to components/esp_driver_tsens/src/temperature_sensor_private.h index e4e97cf14af..b511505ffba 100644 --- a/components/driver/temperature_sensor/temperature_sensor_private.h +++ b/components/esp_driver_tsens/src/temperature_sensor_private.h @@ -43,7 +43,6 @@ struct temperature_sensor_obj_t { #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT }; - #ifdef __cplusplus } #endif diff --git a/components/esp_driver_tsens/test_apps/.build-test-rules.yml b/components/esp_driver_tsens/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..d54d916a4c0 --- /dev/null +++ b/components/esp_driver_tsens/test_apps/.build-test-rules.yml @@ -0,0 +1,8 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_tsens/test_apps/temperature_sensor: + disable: + - if: SOC_TEMP_SENSOR_SUPPORTED != 1 + depends_components: + - esp_driver_tsens + - esp_phy diff --git a/components/driver/test_apps/temperature_sensor/CMakeLists.txt b/components/esp_driver_tsens/test_apps/temperature_sensor/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/temperature_sensor/CMakeLists.txt rename to components/esp_driver_tsens/test_apps/temperature_sensor/CMakeLists.txt diff --git a/components/driver/test_apps/temperature_sensor/README.md b/components/esp_driver_tsens/test_apps/temperature_sensor/README.md similarity index 100% rename from components/driver/test_apps/temperature_sensor/README.md rename to components/esp_driver_tsens/test_apps/temperature_sensor/README.md diff --git a/components/driver/test_apps/temperature_sensor/main/CMakeLists.txt b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt similarity index 77% rename from components/driver/test_apps/temperature_sensor/main/CMakeLists.txt rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt index a5bd4ce9afa..e250ba0ae4b 100644 --- a/components/driver/test_apps/temperature_sensor/main/CMakeLists.txt +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt @@ -5,5 +5,5 @@ set(srcs "test_app_main.c" # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver esp_wifi test_utils nvs_flash + PRIV_REQUIRES unity esp_wifi test_utils nvs_flash esp_driver_tsens WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/temperature_sensor/main/test_app_main.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_app_main.c similarity index 100% rename from components/driver/test_apps/temperature_sensor/main/test_app_main.c rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/test_app_main.c diff --git a/components/driver/test_apps/temperature_sensor/main/test_temperature_phy.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.c similarity index 96% rename from components/driver/test_apps/temperature_sensor/main/test_temperature_phy.c rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.c index 3d215ec0035..35ab401e2b7 100644 --- a/components/driver/test_apps/temperature_sensor/main/test_temperature_phy.c +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.c @@ -40,10 +40,11 @@ struct temperature_sensor_obj_t { static void start_wifi_as_softap(void) { + uint8_t ssid_len = strlen(TEST_DEFAULT_SSID); wifi_config_t w_config = { .ap.ssid = TEST_DEFAULT_SSID, .ap.password = TEST_DEFAULT_PWD, - .ap.ssid_len = strlen(TEST_DEFAULT_SSID), + .ap.ssid_len = ssid_len, .ap.channel = TEST_DEFAULT_CHANNEL, .ap.authmode = WIFI_AUTH_WPA2_PSK, .ap.ssid_hidden = false, @@ -66,7 +67,7 @@ static void start_wifi_as_sta(void) static void stop_wifi(void) { TEST_ESP_OK(esp_wifi_stop()); - vTaskDelay(500/portTICK_PERIOD_MS); + vTaskDelay(500 / portTICK_PERIOD_MS); } static void wifi_connect(void) @@ -91,7 +92,7 @@ static void test_wifi_establish_sta(void) unity_wait_for_signal("AP start"); // make sure softap has started - vTaskDelay(1000/portTICK_PERIOD_MS); + vTaskDelay(1000 / portTICK_PERIOD_MS); wifi_connect(); unity_send_signal("connect"); unity_wait_for_signal("tsens test done"); diff --git a/components/driver/test_apps/temperature_sensor/main/test_temperature_sensor.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c similarity index 100% rename from components/driver/test_apps/temperature_sensor/main/test_temperature_sensor.c rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c diff --git a/components/driver/test_apps/temperature_sensor/pytest_temperature_sensor.py b/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py similarity index 95% rename from components/driver/test_apps/temperature_sensor/pytest_temperature_sensor.py rename to components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py index 5af7f940f43..bf7e71df17a 100644 --- a/components/driver/test_apps/temperature_sensor/pytest_temperature_sensor.py +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py @@ -2,8 +2,8 @@ # SPDX-License-Identifier: CC0-1.0 import pytest -from idf_unity_tester import CaseTester from pytest_embedded import Dut +from pytest_embedded_idf.unity_tester import CaseTester @pytest.mark.esp32s2 diff --git a/components/driver/test_apps/temperature_sensor/sdkconfig.ci.iram_safe b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/temperature_sensor/sdkconfig.ci.iram_safe rename to components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/sigma_delta/sdkconfig.ci.release b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/sigma_delta/sdkconfig.ci.release rename to components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release diff --git a/components/driver/test_apps/temperature_sensor/sdkconfig.defaults b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/temperature_sensor/sdkconfig.defaults rename to components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults diff --git a/components/esp_driver_uart/CMakeLists.txt b/components/esp_driver_uart/CMakeLists.txt new file mode 100644 index 00000000000..e6046edd67a --- /dev/null +++ b/components/esp_driver_uart/CMakeLists.txt @@ -0,0 +1,19 @@ +set(srcs) +set(public_include "include") +if(CONFIG_SOC_UART_SUPPORTED) + list(APPEND srcs "src/uart.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES esp_pm esp_driver_gpio esp_ringbuf + LDFRAGMENTS "linker.lf" + ) + +if(CONFIG_VFS_SUPPORT_IO) + target_link_libraries(${COMPONENT_LIB} PUBLIC idf::vfs) + target_sources(${COMPONENT_LIB} PRIVATE "src/uart_vfs.c") + if(CONFIG_ESP_CONSOLE_UART) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u uart_vfs_include_dev_init") + endif() +endif() diff --git a/components/driver/uart/Kconfig.uart b/components/esp_driver_uart/Kconfig similarity index 87% rename from components/driver/uart/Kconfig.uart rename to components/esp_driver_uart/Kconfig index 4272cb290fb..275084d5196 100644 --- a/components/driver/uart/Kconfig.uart +++ b/components/esp_driver_uart/Kconfig @@ -1,4 +1,4 @@ -menu "UART Configuration" +menu "ESP-Driver:UART Configurations" config UART_ISR_IN_IRAM bool "Place UART ISR function into IRAM" @@ -9,4 +9,4 @@ menu "UART Configuration" If this option is not selected, UART interrupt will be disabled for a long time and may cause data lost when doing spi flash operation. -endmenu # UART Configuration +endmenu diff --git a/components/driver/uart/include/driver/uart.h b/components/esp_driver_uart/include/driver/uart.h similarity index 98% rename from components/driver/uart/include/driver/uart.h rename to components/esp_driver_uart/include/driver/uart.h index 2ff0e566036..e6ee0565ba5 100644 --- a/components/driver/uart/include/driver/uart.h +++ b/components/esp_driver_uart/include/driver/uart.h @@ -14,10 +14,7 @@ extern "C" { #include "esp_intr_alloc.h" #include "soc/soc_caps.h" #include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" -#include "freertos/task.h" #include "freertos/queue.h" -#include "freertos/ringbuf.h" #include "hal/uart_types.h" /* @brief When calling `uart_set_pin`, instead of GPIO number, `UART_PIN_NO_CHANGE` @@ -86,7 +83,7 @@ typedef struct { uart_event_type_t type; /*!< UART event type */ size_t size; /*!< UART data size for UART_DATA event*/ bool timeout_flag; /*!< UART data read timeout flag for UART_DATA event (no new data received during configured RX TOUT)*/ - /*!< If the event is caused by FIFO-full interrupt, then there will be no event with the timeout flag before the next byte coming.*/ + /*!< If the event is caused by FIFO-full interrupt, then there will be no event with the timeout flag before the next byte coming.*/ } uart_event_t; typedef intr_handle_t uart_isr_handle_t; @@ -285,7 +282,7 @@ esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow * - ESP_OK Success * - ESP_FAIL Parameter error */ - esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_thresh_xon, uint8_t rx_thresh_xoff); +esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_thresh_xon, uint8_t rx_thresh_xoff); /** * @brief Get the UART hardware flow control configuration. diff --git a/components/driver/uart/include/driver/uart_select.h b/components/esp_driver_uart/include/driver/uart_select.h similarity index 100% rename from components/driver/uart/include/driver/uart_select.h rename to components/esp_driver_uart/include/driver/uart_select.h diff --git a/components/esp_driver_uart/include/driver/uart_vfs.h b/components/esp_driver_uart/include/driver/uart_vfs.h new file mode 100644 index 00000000000..0521603dedd --- /dev/null +++ b/components/esp_driver_uart/include/driver/uart_vfs.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_vfs_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Add /dev/uart virtual filesystem driver + * + * This function is called from startup code to enable serial output + */ +void uart_vfs_dev_register(void); + +/** + * @brief Set the line endings expected to be received on specified UART + * + * This specifies the conversion between line endings received on UART and + * newlines ('\n', LF) passed into stdin: + * + * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF + * - ESP_LINE_ENDINGS_CR: convert CR to LF + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. reading from UART + * + * @param uart_num the UART number + * @param mode line endings to send to UART + * + * @return 0 if successed, or -1 + * when an error (specified by errno) have occurred. + */ +int uart_vfs_dev_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode); + +/** + * @brief Set the line endings to sent to specified UART + * + * This specifies the conversion between newlines ('\n', LF) on stdout and line + * endings sent over UART: + * + * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF + * - ESP_LINE_ENDINGS_CR: convert LF to CR + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. writing to UART + * + * @param uart_num the UART number + * @param mode line endings to send to UART + * + * @return 0 if successed, or -1 + * when an error (specified by errno) have occurred. + */ +int uart_vfs_dev_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode); + +/** + * @brief set VFS to use simple functions for reading and writing UART + * + * Read is non-blocking, write is busy waiting until TX FIFO has enough space. + * These functions are used by default. + * + * @param uart_num UART peripheral number + */ +void uart_vfs_dev_use_nonblocking(int uart_num); + +/** + * @brief set VFS to use UART driver for reading and writing + * + * @note Application must configure UART driver before calling these functions + * With these functions, read and write are blocking and interrupt-driven. + * + * @param uart_num UART peripheral number + */ +void uart_vfs_dev_use_driver(int uart_num); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_uart/linker.lf b/components/esp_driver_uart/linker.lf new file mode 100644 index 00000000000..ff50da45039 --- /dev/null +++ b/components/esp_driver_uart/linker.lf @@ -0,0 +1,11 @@ +[mapping:uart_vfs] +archive: libesp_driver_uart.a +entries: + if VFS_SELECT_IN_RAM = y: + uart_vfs: select_notif_callback_isr (noflash) + +[mapping:uart_hal] +archive: libhal.a +entries: + if UART_ISR_IN_IRAM = y: + uart_hal_iram (noflash) diff --git a/components/driver/uart/uart.c b/components/esp_driver_uart/src/uart.c similarity index 95% rename from components/driver/uart/uart.c rename to components/esp_driver_uart/src/uart.c index 90dfae109d4..2cc2c2dccd2 100644 --- a/components/driver/uart/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -11,7 +11,6 @@ #include "esp_log.h" #include "esp_err.h" #include "esp_check.h" -#include "malloc.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" #include "freertos/semphr.h" @@ -20,15 +19,13 @@ #include "esp_private/critical_section.h" #include "hal/uart_hal.h" #include "hal/gpio_hal.h" -#include "hal/clk_tree_ll.h" #include "soc/uart_periph.h" #include "driver/uart.h" #include "driver/gpio.h" #include "driver/rtc_io.h" #include "driver/uart_select.h" #include "driver/lp_io.h" -#include "esp_private/uart_private.h" -#include "esp_private/periph_ctrl.h" +#include "esp_private/uart_share_hw_ctrl.h" #include "esp_clk_tree.h" #include "sdkconfig.h" #include "esp_rom_gpio.h" @@ -120,9 +117,6 @@ typedef struct { int rx_buffered_len; /*!< UART cached data length */ int rx_buf_size; /*!< RX ring buffer size */ bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */ - uint32_t rx_cur_remain; /*!< Data number that waiting to be read out in ring buffer item*/ - uint8_t *rx_ptr; /*!< pointer to the current data in ring buffer*/ - uint8_t *rx_head_ptr; /*!< pointer to the head of RX item*/ uint8_t *rx_data_buf; /*!< Data buffer to stash FIFO data*/ uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */ uint32_t rx_int_usr_mask; /*!< RX interrupt status. Valid at any time, regardless of RX buffer status. */ @@ -183,23 +177,9 @@ static void uart_module_enable(uart_port_t uart_num) uart_ll_enable_bus_clock(uart_num, true); } if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { - // Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output - // garbage value. -#if SOC_UART_REQUIRE_CORE_RESET - HP_UART_SRC_CLK_ATOMIC(){ - uart_hal_set_reset_core(&(uart_context[uart_num].hal), true); - } - HP_UART_BUS_CLK_ATOMIC() { - uart_ll_reset_register(uart_num); - } - HP_UART_SRC_CLK_ATOMIC(){ - uart_hal_set_reset_core(&(uart_context[uart_num].hal), false); - } -#else HP_UART_BUS_CLK_ATOMIC() { uart_ll_reset_register(uart_num); } -#endif } } #if (SOC_UART_LP_NUM >= 1) @@ -544,7 +524,7 @@ esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length) ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error"); ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_ERR_INVALID_STATE, UART_TAG, "uart driver error"); - int *pdata = (int *) malloc(queue_length * sizeof(int)); + int *pdata = (int *)heap_caps_malloc(queue_length * sizeof(int), UART_MALLOC_CAPS); if (pdata == NULL) { return ESP_ERR_NO_MEM; } @@ -637,7 +617,7 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id } /* Assign the correct funct to the GPIO. */ - assert (upin->iomux_func != -1); + assert(upin->iomux_func != -1); if (uart_num < SOC_UART_HP_NUM) { gpio_iomux_out(io_num, upin->iomux_func, false); @@ -1090,7 +1070,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) p_uart->rx_buffered_len + pat_idx); } UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); - sent = xQueueSendFromISR(p_uart->event_queue, (void * )&uart_event, &HPTaskAwoken); + sent = xQueueSendFromISR(p_uart->event_queue, (void *)&uart_event, &HPTaskAwoken); need_yield |= (HPTaskAwoken == pdTRUE); if ((p_uart->event_queue != NULL) && (sent == pdFALSE)) { #ifndef CONFIG_UART_ISR_IN_IRAM //Only log if ISR is not in IRAM @@ -1215,19 +1195,19 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) need_yield |= (HPTaskAwoken == pdTRUE); } } - #if SOC_UART_SUPPORT_WAKEUP_INT +#if SOC_UART_SUPPORT_WAKEUP_INT else if (uart_intr_status & UART_INTR_WAKEUP) { uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_WAKEUP); uart_event.type = UART_WAKEUP; } - #endif +#endif else { uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), uart_intr_status); /*simply clear all other intr status*/ uart_event.type = UART_EVENT_MAX; } if (uart_event.type != UART_EVENT_MAX && p_uart->event_queue) { - sent = xQueueSendFromISR(p_uart->event_queue, (void * )&uart_event, &HPTaskAwoken); + sent = xQueueSendFromISR(p_uart->event_queue, (void *)&uart_event, &HPTaskAwoken); need_yield |= (HPTaskAwoken == pdTRUE); if (sent == pdFALSE) { #ifndef CONFIG_UART_ISR_IN_IRAM //Only log if ISR is not in IRAM @@ -1340,7 +1320,7 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) &evt, sizeof(uart_tx_data_t), portMAX_DELAY); while (size > 0) { size_t send_size = size > max_size / 2 ? max_size / 2 : size; - xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) (src + offset), send_size, portMAX_DELAY); + xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY); size -= send_size; offset += send_size; uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT)); @@ -1414,53 +1394,35 @@ int uart_read_bytes(uart_port_t uart_num, void *buf, uint32_t length, TickType_t ESP_RETURN_ON_FALSE((buf), (-1), UART_TAG, "uart data null"); ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), (-1), UART_TAG, "uart driver error"); uint8_t *data = NULL; - size_t size; + size_t size = 0; size_t copy_len = 0; - int len_tmp; if (xSemaphoreTake(p_uart_obj[uart_num]->rx_mux, (TickType_t)ticks_to_wait) != pdTRUE) { return -1; } while (length) { - if (p_uart_obj[uart_num]->rx_cur_remain == 0) { - data = (uint8_t *) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (TickType_t) ticks_to_wait); - if (data) { - p_uart_obj[uart_num]->rx_head_ptr = data; - p_uart_obj[uart_num]->rx_ptr = data; - p_uart_obj[uart_num]->rx_cur_remain = size; + data = (uint8_t *) xRingbufferReceiveUpTo(p_uart_obj[uart_num]->rx_ring_buf, &size, (TickType_t) ticks_to_wait, length); + if (!data) { + // When using dual cores, `rx_buffer_full_flg` may read and write on different cores at same time, + // which may lose synchronization. So we also need to call `uart_check_buf_full` once when ringbuffer is empty + // to solve the possible asynchronous issues. + if (uart_check_buf_full(uart_num)) { + // This condition will never be true if `uart_read_bytes` + // and `uart_rx_intr_handler_default` are scheduled on the same core. + continue; } else { - //When using dual cores, `rx_buffer_full_flg` may read and write on different cores at same time, - //which may lose synchronization. So we also need to call `uart_check_buf_full` once when ringbuffer is empty - //to solve the possible asynchronous issues. - if (uart_check_buf_full(uart_num)) { - //This condition will never be true if `uart_read_bytes` - //and `uart_rx_intr_handler_default` are scheduled on the same core. - continue; - } else { - xSemaphoreGive(p_uart_obj[uart_num]->rx_mux); - return copy_len; - } + // Timeout while not fetched all requested length + break; } } - if (p_uart_obj[uart_num]->rx_cur_remain > length) { - len_tmp = length; - } else { - len_tmp = p_uart_obj[uart_num]->rx_cur_remain; - } - memcpy((uint8_t *)buf + copy_len, p_uart_obj[uart_num]->rx_ptr, len_tmp); + memcpy((uint8_t *)buf + copy_len, data, size); UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - p_uart_obj[uart_num]->rx_buffered_len -= len_tmp; - uart_pattern_queue_update(uart_num, len_tmp); - p_uart_obj[uart_num]->rx_ptr += len_tmp; + p_uart_obj[uart_num]->rx_buffered_len -= size; + uart_pattern_queue_update(uart_num, size); UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); - p_uart_obj[uart_num]->rx_cur_remain -= len_tmp; - copy_len += len_tmp; - length -= len_tmp; - if (p_uart_obj[uart_num]->rx_cur_remain == 0) { - vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_head_ptr); - p_uart_obj[uart_num]->rx_head_ptr = NULL; - p_uart_obj[uart_num]->rx_ptr = NULL; - uart_check_buf_full(uart_num); - } + copy_len += size; + length -= size; + vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, data); + uart_check_buf_full(uart_num); } xSemaphoreGive(p_uart_obj[uart_num]->rx_mux); @@ -1502,25 +1464,15 @@ esp_err_t uart_flush_input(uart_port_t uart_num) uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT); UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); while (true) { - if (p_uart->rx_head_ptr) { - vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr); - UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain; - uart_pattern_queue_update(uart_num, p_uart->rx_cur_remain); - UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); - p_uart->rx_ptr = NULL; - p_uart->rx_cur_remain = 0; - p_uart->rx_head_ptr = NULL; - } - data = (uint8_t*) xRingbufferReceive(p_uart->rx_ring_buf, &size, (TickType_t) 0); - if(data == NULL) { + data = (uint8_t *) xRingbufferReceive(p_uart->rx_ring_buf, &size, (TickType_t) 0); + if (data == NULL) { bool error = false; UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - if( p_uart_obj[uart_num]->rx_buffered_len != 0 ) { + if (p_uart_obj[uart_num]->rx_buffered_len != 0) { p_uart_obj[uart_num]->rx_buffered_len = 0; error = true; } - //We also need to clear the `rx_buffer_full_flg` here. + // We also need to clear the `rx_buffer_full_flg` here. p_uart_obj[uart_num]->rx_buffer_full_flg = false; UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); if (error) { @@ -1544,9 +1496,6 @@ esp_err_t uart_flush_input(uart_port_t uart_num) } } } - p_uart->rx_ptr = NULL; - p_uart->rx_cur_remain = 0; - p_uart->rx_head_ptr = NULL; uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); /* Only re-enable UART_INTR_RXFIFO_TOUT or UART_INTR_RXFIFO_FULL if they * were explicitly enabled by the user. */ @@ -1667,10 +1616,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b p_uart_obj[uart_num]->rx_buffered_len = 0; p_uart_obj[uart_num]->rx_buffer_full_flg = false; p_uart_obj[uart_num]->tx_waiting_fifo = false; - p_uart_obj[uart_num]->rx_ptr = NULL; - p_uart_obj[uart_num]->rx_cur_remain = 0; p_uart_obj[uart_num]->rx_int_usr_mask = UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT; - p_uart_obj[uart_num]->rx_head_ptr = NULL; p_uart_obj[uart_num]->tx_buf_size = tx_buffer_size; p_uart_obj[uart_num]->uart_select_notif_callback = NULL; xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem); @@ -1695,8 +1641,8 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); ret = esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags, - uart_rx_intr_handler_default, p_uart_obj[uart_num], - &p_uart_obj[uart_num]->intr_handle); + uart_rx_intr_handler_default, p_uart_obj[uart_num], + &p_uart_obj[uart_num]->intr_handle); ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART"); ret = uart_intr_config(uart_num, &uart_intr); @@ -1864,7 +1810,9 @@ esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int *out_wakeup_thresh esp_err_t uart_wait_tx_idle_polling(uart_port_t uart_num) { ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error"); - while (!uart_hal_is_tx_idle(&(uart_context[uart_num].hal))); + if (uart_ll_is_enabled(uart_num)) { + while (!uart_hal_is_tx_idle(&(uart_context[uart_num].hal))); + } return ESP_OK; } diff --git a/components/vfs/vfs_uart.c b/components/esp_driver_uart/src/uart_vfs.c similarity index 66% rename from components/vfs/vfs_uart.c rename to components/esp_driver_uart/src/uart_vfs.c index fd6fb42de91..c3e1bca87b2 100644 --- a/components/vfs/vfs_uart.c +++ b/components/esp_driver_uart/src/uart_vfs.c @@ -11,16 +11,17 @@ #include #include #include -#include "esp_vfs.h" -#include "esp_vfs_dev.h" +#include "sdkconfig.h" #include "esp_attr.h" -#include "soc/uart_periph.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" -#include "sdkconfig.h" #include "driver/uart_select.h" #include "esp_rom_uart.h" -#include "soc/soc_caps.h" #include "hal/uart_ll.h" +#include "soc/soc_caps.h" +#include "esp_private/esp_vfs_console.h" +#include "esp_vfs_dev.h" // Old headers for the aliasing functions +#include "esp_private/startup_internal.h" #define UART_NUM SOC_UART_HP_NUM @@ -43,6 +44,12 @@ # define DEFAULT_RX_MODE ESP_LINE_ENDINGS_LF #endif +#if CONFIG_VFS_SELECT_IN_RAM +#define UART_VFS_MALLOC_FLAGS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) +#else +#define UART_VFS_MALLOC_FLAGS MALLOC_CAP_DEFAULT +#endif + // UART write bytes function type typedef void (*tx_func_t)(int, int); // UART read bytes function type @@ -76,9 +83,9 @@ typedef struct { tx_func_t tx_func; // Functions used to read bytes from UART. Default to "basic" functions. rx_func_t rx_func; -} vfs_uart_context_t; +} uart_vfs_context_t; -#define VFS_CTX_DEFAULT_VAL(uart_dev) (vfs_uart_context_t) {\ +#define VFS_CTX_DEFAULT_VAL(uart_dev) (uart_vfs_context_t) {\ .uart = (uart_dev),\ .peek_char = NONE,\ .tx_mode = DEFAULT_TX_MODE,\ @@ -89,7 +96,7 @@ typedef struct { //If the context should be dynamically initialized, remove this structure //and point s_ctx to allocated data. -static vfs_uart_context_t s_context[UART_NUM] = { +static uart_vfs_context_t s_context[UART_NUM] = { VFS_CTX_DEFAULT_VAL(&UART0), VFS_CTX_DEFAULT_VAL(&UART1), #if UART_NUM > 2 @@ -97,7 +104,7 @@ static vfs_uart_context_t s_context[UART_NUM] = { #endif }; -static vfs_uart_context_t* s_ctx[UART_NUM] = { +static uart_vfs_context_t* s_ctx[UART_NUM] = { &s_context[0], &s_context[1], #if UART_NUM > 2 @@ -199,7 +206,7 @@ static int uart_rx_char_via_driver(int fd) static ssize_t uart_write(int fd, const void * data, size_t size) { - assert(fd >=0 && fd < 3); + assert(fd >= 0 && fd < 3); const char *data_c = (const char *)data; /* Even though newlib does stream locking on each individual stream, we need * a dedicated UART lock if two streams (stdout and stderr) point to the @@ -244,7 +251,7 @@ static void uart_return_char(int fd, int c) static ssize_t uart_read(int fd, void* data, size_t size) { - assert(fd >=0 && fd < 3); + assert(fd >= 0 && fd < 3); char *data_c = (char *) data; size_t received = 0; _lock_acquire_recursive(&s_ctx[fd]->read_lock); @@ -290,7 +297,7 @@ static ssize_t uart_read(int fd, void* data, size_t size) static int uart_fstat(int fd, struct stat * st) { - assert(fd >=0 && fd < 3); + assert(fd >= 0 && fd < 3); memset(st, 0, sizeof(*st)); st->st_mode = S_IFCHR; return 0; @@ -298,13 +305,13 @@ static int uart_fstat(int fd, struct stat * st) static int uart_close(int fd) { - assert(fd >=0 && fd < 3); + assert(fd >= 0 && fd < 3); return 0; } static int uart_fcntl(int fd, int cmd, int arg) { - assert(fd >=0 && fd < 3); + assert(fd >= 0 && fd < 3); int result = 0; if (cmd == F_GETFL) { result |= O_RDWR; @@ -365,7 +372,7 @@ static esp_err_t register_select(uart_select_args_t *args) portENTER_CRITICAL(&s_registered_select_lock); const int new_size = s_registered_select_num + 1; uart_select_args_t **new_selects; - if ((new_selects = realloc(s_registered_selects, new_size * sizeof(uart_select_args_t *))) == NULL) { + if ((new_selects = heap_caps_realloc(s_registered_selects, new_size * sizeof(uart_select_args_t *), UART_VFS_MALLOC_FLAGS)) == NULL) { ret = ESP_ERR_NO_MEM; } else { s_registered_selects = new_selects; @@ -391,7 +398,7 @@ static esp_err_t unregister_select(uart_select_args_t *args) // The item is removed by overwriting it with the last item. The subsequent rellocation will drop the // last item. s_registered_selects[i] = s_registered_selects[new_size]; - s_registered_selects = realloc(s_registered_selects, new_size * sizeof(uart_select_args_t *)); + s_registered_selects = heap_caps_realloc(s_registered_selects, new_size * sizeof(uart_select_args_t *), UART_VFS_MALLOC_FLAGS); // Shrinking a buffer with realloc is guaranteed to succeed. s_registered_select_num = new_size; ret = ESP_OK; @@ -410,24 +417,24 @@ static void select_notif_callback_isr(uart_port_t uart_num, uart_select_notif_t uart_select_args_t *args = s_registered_selects[i]; if (args) { switch (uart_select_notif) { - case UART_SELECT_READ_NOTIF: - if (FD_ISSET(uart_num, &args->readfds_orig)) { - FD_SET(uart_num, args->readfds); - esp_vfs_select_triggered_isr(args->select_sem, task_woken); - } - break; - case UART_SELECT_WRITE_NOTIF: - if (FD_ISSET(uart_num, &args->writefds_orig)) { - FD_SET(uart_num, args->writefds); - esp_vfs_select_triggered_isr(args->select_sem, task_woken); - } - break; - case UART_SELECT_ERROR_NOTIF: - if (FD_ISSET(uart_num, &args->errorfds_orig)) { - FD_SET(uart_num, args->errorfds); - esp_vfs_select_triggered_isr(args->select_sem, task_woken); - } - break; + case UART_SELECT_READ_NOTIF: + if (FD_ISSET(uart_num, &args->readfds_orig)) { + FD_SET(uart_num, args->readfds); + esp_vfs_select_triggered_isr(args->select_sem, task_woken); + } + break; + case UART_SELECT_WRITE_NOTIF: + if (FD_ISSET(uart_num, &args->writefds_orig)) { + FD_SET(uart_num, args->writefds); + esp_vfs_select_triggered_isr(args->select_sem, task_woken); + } + break; + case UART_SELECT_ERROR_NOTIF: + if (FD_ISSET(uart_num, &args->errorfds_orig)) { + FD_SET(uart_num, args->errorfds); + esp_vfs_select_triggered_isr(args->select_sem, task_woken); + } + break; } } } @@ -435,7 +442,7 @@ static void select_notif_callback_isr(uart_port_t uart_num, uart_select_notif_t } static esp_err_t uart_start_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, - esp_vfs_select_sem_t select_sem, void **end_select_args) + esp_vfs_select_sem_t select_sem, void **end_select_args) { const int max_fds = MIN(nfds, UART_NUM); *end_select_args = NULL; @@ -448,7 +455,7 @@ static esp_err_t uart_start_select(int nfds, fd_set *readfds, fd_set *writefds, } } - uart_select_args_t *args = malloc(sizeof(uart_select_args_t)); + uart_select_args_t *args = heap_caps_malloc(sizeof(uart_select_args_t), UART_VFS_MALLOC_FLAGS); if (args == NULL) { return ESP_ERR_NO_MEM; @@ -541,26 +548,26 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p) } switch (optional_actions) { - case TCSANOW: - // nothing to do - break; - case TCSADRAIN: - if (uart_wait_tx_done(fd, portMAX_DELAY) != ESP_OK) { - errno = EINVAL; - return -1; - } + case TCSANOW: + // nothing to do + break; + case TCSADRAIN: + if (uart_wait_tx_done(fd, portMAX_DELAY) != ESP_OK) { + errno = EINVAL; + return -1; + } - /* FALLTHRU */ + /* FALLTHRU */ - case TCSAFLUSH: - if (uart_flush_input(fd) != ESP_OK) { - errno = EINVAL; - return -1; - } - break; - default: + case TCSAFLUSH: + if (uart_flush_input(fd) != ESP_OK) { errno = EINVAL; return -1; + } + break; + default: + errno = EINVAL; + return -1; } if (p->c_iflag & IGNCR) { @@ -578,21 +585,21 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p) const tcflag_t csize_bits = p->c_cflag & CSIZE; switch (csize_bits) { - case CS5: - data_bits = UART_DATA_5_BITS; - break; - case CS6: - data_bits = UART_DATA_6_BITS; - break; - case CS7: - data_bits = UART_DATA_7_BITS; - break; - case CS8: - data_bits = UART_DATA_8_BITS; - break; - default: - errno = EINVAL; - return -1; + case CS5: + data_bits = UART_DATA_5_BITS; + break; + case CS6: + data_bits = UART_DATA_6_BITS; + break; + case CS7: + data_bits = UART_DATA_7_BITS; + break; + case CS8: + data_bits = UART_DATA_8_BITS; + break; + default: + errno = EINVAL; + return -1; } if (uart_set_word_length(fd, data_bits) != ESP_OK) { @@ -607,9 +614,9 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p) } if (uart_set_parity(fd, (p->c_cflag & PARENB) ? - ((p->c_cflag & PARODD) ? UART_PARITY_ODD : UART_PARITY_EVEN) - : - UART_PARITY_DISABLE) != ESP_OK) { + ((p->c_cflag & PARODD) ? UART_PARITY_ODD : UART_PARITY_EVEN) + : + UART_PARITY_DISABLE) != ESP_OK) { errno = EINVAL; return -1; } @@ -624,102 +631,102 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p) b = p->c_ispeed; } else { switch (p->c_ispeed) { - case B0: - b = 0; - break; - case B50: - b = 50; - break; - case B75: - b = 75; - break; - case B110: - b = 110; - break; - case B134: - b = 134; - break; - case B150: - b = 150; - break; - case B200: - b = 200; - break; - case B300: - b = 300; - break; - case B600: - b = 600; - break; - case B1200: - b = 1200; - break; - case B1800: - b = 1800; - break; - case B2400: - b = 2400; - break; - case B4800: - b = 4800; - break; - case B9600: - b = 9600; - break; - case B19200: - b = 19200; - break; - case B38400: - b = 38400; - break; - case B57600: - b = 57600; - break; - case B115200: - b = 115200; - break; - case B230400: - b = 230400; - break; - case B460800: - b = 460800; - break; - case B500000: - b = 500000; - break; - case B576000: - b = 576000; - break; - case B921600: - b = 921600; - break; - case B1000000: - b = 1000000; - break; - case B1152000: - b = 1152000; - break; - case B1500000: - b = 1500000; - break; - case B2000000: - b = 2000000; - break; - case B2500000: - b = 2500000; - break; - case B3000000: - b = 3000000; - break; - case B3500000: - b = 3500000; - break; - case B4000000: - b = 4000000; - break; - default: - errno = EINVAL; - return -1; + case B0: + b = 0; + break; + case B50: + b = 50; + break; + case B75: + b = 75; + break; + case B110: + b = 110; + break; + case B134: + b = 134; + break; + case B150: + b = 150; + break; + case B200: + b = 200; + break; + case B300: + b = 300; + break; + case B600: + b = 600; + break; + case B1200: + b = 1200; + break; + case B1800: + b = 1800; + break; + case B2400: + b = 2400; + break; + case B4800: + b = 4800; + break; + case B9600: + b = 9600; + break; + case B19200: + b = 19200; + break; + case B38400: + b = 38400; + break; + case B57600: + b = 57600; + break; + case B115200: + b = 115200; + break; + case B230400: + b = 230400; + break; + case B460800: + b = 460800; + break; + case B500000: + b = 500000; + break; + case B576000: + b = 576000; + break; + case B921600: + b = 921600; + break; + case B1000000: + b = 1000000; + break; + case B1152000: + b = 1152000; + break; + case B1500000: + b = 1500000; + break; + case B2000000: + b = 2000000; + break; + case B2500000: + b = 2500000; + break; + case B3000000: + b = 3000000; + break; + case B3500000: + b = 3500000; + break; + case B4000000: + b = 4000000; + break; + default: + errno = EINVAL; + return -1; } } @@ -764,21 +771,21 @@ static int uart_tcgetattr(int fd, struct termios *p) p->c_cflag &= (~CSIZE); switch (data_bits) { - case UART_DATA_5_BITS: - p->c_cflag |= CS5; - break; - case UART_DATA_6_BITS: - p->c_cflag |= CS6; - break; - case UART_DATA_7_BITS: - p->c_cflag |= CS7; - break; - case UART_DATA_8_BITS: - p->c_cflag |= CS8; - break; - default: - errno = ENOSYS; - return -1; + case UART_DATA_5_BITS: + p->c_cflag |= CS5; + break; + case UART_DATA_6_BITS: + p->c_cflag |= CS6; + break; + case UART_DATA_7_BITS: + p->c_cflag |= CS7; + break; + case UART_DATA_8_BITS: + p->c_cflag |= CS8; + break; + default: + errno = ENOSYS; + return -1; } } @@ -790,16 +797,16 @@ static int uart_tcgetattr(int fd, struct termios *p) } switch (stop_bits) { - case UART_STOP_BITS_1: - // nothing to do - break; - case UART_STOP_BITS_2: - p->c_cflag |= CSTOPB; - break; - default: - // UART_STOP_BITS_1_5 is unsupported by termios - errno = ENOSYS; - return -1; + case UART_STOP_BITS_1: + // nothing to do + break; + case UART_STOP_BITS_2: + p->c_cflag |= CSTOPB; + break; + default: + // UART_STOP_BITS_1_5 is unsupported by termios + errno = ENOSYS; + return -1; } } @@ -811,18 +818,18 @@ static int uart_tcgetattr(int fd, struct termios *p) } switch (parity_mode) { - case UART_PARITY_EVEN: - p->c_cflag |= PARENB; - break; - case UART_PARITY_ODD: - p->c_cflag |= (PARENB | PARODD); - break; - case UART_PARITY_DISABLE: - // nothing to do - break; - default: - errno = ENOSYS; - return -1; + case UART_PARITY_EVEN: + p->c_cflag |= PARENB; + break; + case UART_PARITY_ODD: + p->c_cflag |= (PARENB | PARODD); + break; + case UART_PARITY_DISABLE: + // nothing to do + break; + default: + errno = ENOSYS; + return -1; } } @@ -837,103 +844,103 @@ static int uart_tcgetattr(int fd, struct termios *p) speed_t sp; switch (baudrate) { - case 0: - sp = B0; - break; - case 50: - sp = B50; - break; - case 75: - sp = B75; - break; - case 110: - sp = B110; - break; - case 134: - sp = B134; - break; - case 150: - sp = B150; - break; - case 200: - sp = B200; - break; - case 300: - sp = B300; - break; - case 600: - sp = B600; - break; - case 1200: - sp = B1200; - break; - case 1800: - sp = B1800; - break; - case 2400: - sp = B2400; - break; - case 4800: - sp = B4800; - break; - case 9600: - sp = B9600; - break; - case 19200: - sp = B19200; - break; - case 38400: - sp = B38400; - break; - case 57600: - sp = B57600; - break; - case 115200: - sp = B115200; - break; - case 230400: - sp = B230400; - break; - case 460800: - sp = B460800; - break; - case 500000: - sp = B500000; - break; - case 576000: - sp = B576000; - break; - case 921600: - sp = B921600; - break; - case 1000000: - sp = B1000000; - break; - case 1152000: - sp = B1152000; - break; - case 1500000: - sp = B1500000; - break; - case 2000000: - sp = B2000000; - break; - case 2500000: - sp = B2500000; - break; - case 3000000: - sp = B3000000; - break; - case 3500000: - sp = B3500000; - break; - case 4000000: - sp = B4000000; - break; - default: - p->c_cflag |= BOTHER; - sp = baudrate; - break; + case 0: + sp = B0; + break; + case 50: + sp = B50; + break; + case 75: + sp = B75; + break; + case 110: + sp = B110; + break; + case 134: + sp = B134; + break; + case 150: + sp = B150; + break; + case 200: + sp = B200; + break; + case 300: + sp = B300; + break; + case 600: + sp = B600; + break; + case 1200: + sp = B1200; + break; + case 1800: + sp = B1800; + break; + case 2400: + sp = B2400; + break; + case 4800: + sp = B4800; + break; + case 9600: + sp = B9600; + break; + case 19200: + sp = B19200; + break; + case 38400: + sp = B38400; + break; + case 57600: + sp = B57600; + break; + case 115200: + sp = B115200; + break; + case 230400: + sp = B230400; + break; + case 460800: + sp = B460800; + break; + case 500000: + sp = B500000; + break; + case 576000: + sp = B576000; + break; + case 921600: + sp = B921600; + break; + case 1000000: + sp = B1000000; + break; + case 1152000: + sp = B1152000; + break; + case 1500000: + sp = B1500000; + break; + case 2000000: + sp = B2000000; + break; + case 2500000: + sp = B2500000; + break; + case 3000000: + sp = B3000000; + break; + case 3500000: + sp = B3500000; + break; + case 4000000: + sp = B4000000; + break; + default: + p->c_cflag |= BOTHER; + sp = baudrate; + break; } p->c_ispeed = p->c_ospeed = sp; @@ -979,7 +986,7 @@ static int uart_tcflush(int fd, int select) } #endif // CONFIG_VFS_SUPPORT_TERMIOS -static const esp_vfs_t vfs = { +static const esp_vfs_t uart_vfs = { .flags = ESP_VFS_FLAG_DEFAULT, .write = &uart_write, .open = &uart_open, @@ -1003,17 +1010,12 @@ static const esp_vfs_t vfs = { #endif // CONFIG_VFS_SUPPORT_TERMIOS }; -const esp_vfs_t* esp_vfs_uart_get_vfs(void) -{ - return &vfs; -} - -void esp_vfs_dev_uart_register(void) +void uart_vfs_dev_register(void) { - ESP_ERROR_CHECK(esp_vfs_register("/dev/uart", &vfs, NULL)); + ESP_ERROR_CHECK(esp_vfs_register("/dev/uart", &uart_vfs, NULL)); } -int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode) +int uart_vfs_dev_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode) { if (uart_num < 0 || uart_num >= UART_NUM) { errno = EBADF; @@ -1023,7 +1025,7 @@ int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t m return 0; } -int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode) +int uart_vfs_dev_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode) { if (uart_num < 0 || uart_num >= UART_NUM) { errno = EBADF; @@ -1033,21 +1035,23 @@ int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t m return 0; } -void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) +// Deprecated +void uart_vfs_dev_set_rx_line_endings(esp_line_endings_t mode) { for (int i = 0; i < UART_NUM; ++i) { s_ctx[i]->rx_mode = mode; } } -void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) +// Deprecated +void uart_vfs_dev_set_tx_line_endings(esp_line_endings_t mode) { for (int i = 0; i < UART_NUM; ++i) { s_ctx[i]->tx_mode = mode; } } -void esp_vfs_dev_uart_use_nonblocking(int uart_num) +void uart_vfs_dev_use_nonblocking(int uart_num) { _lock_acquire_recursive(&s_ctx[uart_num]->read_lock); _lock_acquire_recursive(&s_ctx[uart_num]->write_lock); @@ -1057,7 +1061,7 @@ void esp_vfs_dev_uart_use_nonblocking(int uart_num) _lock_release_recursive(&s_ctx[uart_num]->read_lock); } -void esp_vfs_dev_uart_use_driver(int uart_num) +void uart_vfs_dev_use_driver(int uart_num) { _lock_acquire_recursive(&s_ctx[uart_num]->read_lock); _lock_acquire_recursive(&s_ctx[uart_num]->write_lock); @@ -1066,3 +1070,32 @@ void esp_vfs_dev_uart_use_driver(int uart_num) _lock_release_recursive(&s_ctx[uart_num]->write_lock); _lock_release_recursive(&s_ctx[uart_num]->read_lock); } + +#if CONFIG_VFS_SUPPORT_IO && CONFIG_ESP_CONSOLE_UART +ESP_SYSTEM_INIT_FN(init_vfs_uart, CORE, BIT(0), 110) +{ + esp_vfs_set_primary_dev_vfs_def_struct(&uart_vfs); + return ESP_OK; +} +#endif + +void uart_vfs_include_dev_init(void) +{ + // Linker hook function, exists to make the linker examine this file +} + +// -------------------------- esp_vfs_dev_uart_xxx ALIAS (deprecated) ---------------------------- + +void esp_vfs_dev_uart_register(void) __attribute__((alias("uart_vfs_dev_register"))); + +void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) __attribute__((alias("uart_vfs_dev_set_rx_line_endings"))); + +void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) __attribute__((alias("uart_vfs_dev_set_tx_line_endings"))); + +int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode) __attribute__((alias("uart_vfs_dev_port_set_rx_line_endings"))); + +int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode) __attribute__((alias("uart_vfs_dev_port_set_tx_line_endings"))); + +void esp_vfs_dev_uart_use_nonblocking(int uart_num) __attribute__((alias("uart_vfs_dev_use_nonblocking"))); + +void esp_vfs_dev_uart_use_driver(int uart_num) __attribute__((alias("uart_vfs_dev_use_driver"))); diff --git a/components/esp_driver_uart/test_apps/.build-test-rules.yml b/components/esp_driver_uart/test_apps/.build-test-rules.yml new file mode 100644 index 00000000000..1e0bdf7afb9 --- /dev/null +++ b/components/esp_driver_uart/test_apps/.build-test-rules.yml @@ -0,0 +1,24 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_driver_uart/test_apps/rs485: + disable: + - if: SOC_UART_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET != "esp32" + temporary: true + reason: lack of runners + depends_components: + - esp_driver_uart + - esp_driver_gpio + +components/esp_driver_uart/test_apps/uart: + disable: + - if: SOC_UART_SUPPORTED != 1 + depends_components: + - esp_driver_uart + - esp_driver_gpio + +components/esp_driver_uart/test_apps/uart_vfs: + depends_components: + - esp_driver_uart + - vfs diff --git a/components/driver/test_apps/rs485/CMakeLists.txt b/components/esp_driver_uart/test_apps/rs485/CMakeLists.txt similarity index 100% rename from components/driver/test_apps/rs485/CMakeLists.txt rename to components/esp_driver_uart/test_apps/rs485/CMakeLists.txt diff --git a/components/driver/test_apps/uart/README.md b/components/esp_driver_uart/test_apps/rs485/README.md similarity index 100% rename from components/driver/test_apps/uart/README.md rename to components/esp_driver_uart/test_apps/rs485/README.md diff --git a/components/driver/test_apps/rs485/main/CMakeLists.txt b/components/esp_driver_uart/test_apps/rs485/main/CMakeLists.txt similarity index 82% rename from components/driver/test_apps/rs485/main/CMakeLists.txt rename to components/esp_driver_uart/test_apps/rs485/main/CMakeLists.txt index 48d86f05ec2..c4e68d5014f 100644 --- a/components/driver/test_apps/rs485/main/CMakeLists.txt +++ b/components/esp_driver_uart/test_apps/rs485/main/CMakeLists.txt @@ -2,6 +2,6 @@ # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS "test_app_main.c" "test_rs485.c" - REQUIRES driver unity test_utils + REQUIRES esp_driver_uart unity test_utils WHOLE_ARCHIVE ) diff --git a/components/driver/test_apps/rs485/main/test_app_main.c b/components/esp_driver_uart/test_apps/rs485/main/test_app_main.c similarity index 62% rename from components/driver/test_apps/rs485/main/test_app_main.c rename to components/esp_driver_uart/test_apps/rs485/main/test_app_main.c index 8d94794888d..0eb34f65b5f 100644 --- a/components/driver/test_apps/rs485/main/test_app_main.c +++ b/components/esp_driver_uart/test_apps/rs485/main/test_app_main.c @@ -5,30 +5,21 @@ */ #include "unity.h" +#include "unity_test_runner.h" #include "unity_test_utils.h" #include "esp_heap_caps.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" #define TEST_MEMORY_LEAK_THRESHOLD (200) -static size_t before_free_8bit; -static size_t before_free_32bit; - - void setUp(void) { - before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + unity_utils_record_free_mem(); } void tearDown(void) { - size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); - printf("\n"); - unity_utils_check_leak(before_free_8bit, after_free_8bit, "8BIT", TEST_MEMORY_LEAK_THRESHOLD); - unity_utils_check_leak(before_free_32bit, after_free_32bit, "32BIT", TEST_MEMORY_LEAK_THRESHOLD); + esp_reent_cleanup(); //clean up some of the newlib's lazy allocations + unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD); } void app_main(void) diff --git a/components/driver/test_apps/rs485/main/test_rs485.c b/components/esp_driver_uart/test_apps/rs485/main/test_rs485.c similarity index 96% rename from components/driver/test_apps/rs485/main/test_rs485.c rename to components/esp_driver_uart/test_apps/rs485/main/test_rs485.c index 774adc641f7..dac0945a480 100644 --- a/components/driver/test_apps/rs485/main/test_rs485.c +++ b/components/esp_driver_uart/test_apps/rs485/main/test_rs485.c @@ -111,20 +111,18 @@ static const uint8_t crc_low[] = { 0x40 }; - // Calculate buffer checksum using tables // The checksum CRC16 algorithm is specific // for Modbus standard and uses polynomial value = 0xA001 -static uint16_t get_buffer_crc16( uint8_t * frame_ptr, uint16_t length ) +static uint16_t get_buffer_crc16(uint8_t * frame_ptr, uint16_t length) { - TEST_ASSERT( frame_ptr != NULL); + TEST_ASSERT(frame_ptr != NULL); uint8_t crc_hi_byte = 0xFF; uint8_t crc_low_byte = 0xFF; int index; - while ( length-- ) - { + while (length--) { index = crc_low_byte ^ *(frame_ptr++); crc_low_byte = crc_hi_byte ^ crc_hi[index]; crc_hi_byte = crc_low[index]; @@ -135,7 +133,7 @@ static uint16_t get_buffer_crc16( uint8_t * frame_ptr, uint16_t length ) // Fill the buffer with random numbers and apply CRC16 at the end static uint16_t buffer_fill_random(uint8_t *buffer, size_t length) { - TEST_ASSERT( buffer != NULL); + TEST_ASSERT(buffer != NULL); // Packet is too short if (length < 4) { return 0; @@ -177,8 +175,8 @@ static void rs485_init(void) static esp_err_t print_packet_data(const char *str, uint8_t *buffer, uint16_t buffer_size) { - TEST_ASSERT( buffer != NULL); - TEST_ASSERT( str != NULL); + TEST_ASSERT(buffer != NULL); + TEST_ASSERT(str != NULL); // Calculate the checksum of the buffer uint16_t crc16_calc = get_buffer_crc16(buffer, (buffer_size - 2)); @@ -187,7 +185,7 @@ static esp_err_t print_packet_data(const char *str, uint8_t *buffer, uint16_t bu // Print an array of data printf("%s%s RS485 packet = [ ", str, state_str); for (int i = 0; i < buffer_size; i++) { - printf("0x%.2X ", (uint8_t)buffer[i]); + printf("0x%.2X ", (uint8_t)buffer[i]); } printf(" ]\r\n"); printf("crc_in = 0x%.4X\r\n", (uint16_t)crc16_in); @@ -205,7 +203,7 @@ static void rs485_slave(void) unity_send_signal("Slave_ready"); unity_wait_for_signal("Master_started"); ESP_LOGI(TAG, "Start recieve loop."); - for(int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) { + for (int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) { //Read slave_data from UART int len = uart_read_bytes(UART_NUM1, slave_data, BUF_SIZE, PACKET_READ_TICS); //Write slave_data back to UART @@ -247,7 +245,7 @@ static void rs485_master(void) unity_wait_for_signal("Slave_ready"); unity_send_signal("Master_started"); ESP_LOGI(TAG, "Start recieve loop."); - for(int i = 0; i < PACKETS_NUMBER; i++) { + for (int i = 0; i < PACKETS_NUMBER; i++) { // Form random buffer with CRC16 buffer_fill_random(master_buffer, BUF_SIZE); // Print created packet for debugging @@ -268,8 +266,7 @@ static void rs485_master(void) err_count++; printf("Errors: %d\r\n", err_count); } - } - else { + } else { printf("Incorrect answer from slave, length = %d.\r\n", len); err_count++; } diff --git a/components/driver/test_apps/rs485/pytest_rs485.py b/components/esp_driver_uart/test_apps/rs485/pytest_rs485.py similarity index 100% rename from components/driver/test_apps/rs485/pytest_rs485.py rename to components/esp_driver_uart/test_apps/rs485/pytest_rs485.py diff --git a/components/driver/test_apps/temperature_sensor/sdkconfig.ci.release b/components/esp_driver_uart/test_apps/rs485/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/temperature_sensor/sdkconfig.ci.release rename to components/esp_driver_uart/test_apps/rs485/sdkconfig.ci.release diff --git a/components/esp_driver_uart/test_apps/rs485/sdkconfig.defaults b/components/esp_driver_uart/test_apps/rs485/sdkconfig.defaults new file mode 100644 index 00000000000..b308cb2ddda --- /dev/null +++ b/components/esp_driver_uart/test_apps/rs485/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n diff --git a/components/driver/test_apps/uart/CMakeLists.txt b/components/esp_driver_uart/test_apps/uart/CMakeLists.txt similarity index 88% rename from components/driver/test_apps/uart/CMakeLists.txt rename to components/esp_driver_uart/test_apps/uart/CMakeLists.txt index 2e1f783b1df..a79832e8c84 100644 --- a/components/driver/test_apps/uart/CMakeLists.txt +++ b/components/esp_driver_uart/test_apps/uart/CMakeLists.txt @@ -12,7 +12,7 @@ project(uart_test) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py - --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/ + --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_uart/,${CMAKE_BINARY_DIR}/esp-idf/hal/ --elf-file ${CMAKE_BINARY_DIR}/uart_test.elf find-refs --from-sections=.iram0.text diff --git a/components/esp_driver_uart/test_apps/uart/README.md b/components/esp_driver_uart/test_apps/uart/README.md new file mode 100644 index 00000000000..bf47d80ec64 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/uart/main/CMakeLists.txt b/components/esp_driver_uart/test_apps/uart/main/CMakeLists.txt similarity index 82% rename from components/driver/test_apps/uart/main/CMakeLists.txt rename to components/esp_driver_uart/test_apps/uart/main/CMakeLists.txt index e4d03ea3f70..44ddd7a4d85 100644 --- a/components/driver/test_apps/uart/main/CMakeLists.txt +++ b/components/esp_driver_uart/test_apps/uart/main/CMakeLists.txt @@ -2,6 +2,6 @@ # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS "test_app_main.c" "test_uart.c" - REQUIRES driver unity + REQUIRES esp_driver_uart unity esp_psram WHOLE_ARCHIVE ) diff --git a/components/driver/test_apps/uart/main/test_app_main.c b/components/esp_driver_uart/test_apps/uart/main/test_app_main.c similarity index 60% rename from components/driver/test_apps/uart/main/test_app_main.c rename to components/esp_driver_uart/test_apps/uart/main/test_app_main.c index c1070bd94d4..f3494708291 100644 --- a/components/driver/test_apps/uart/main/test_app_main.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_app_main.c @@ -5,29 +5,21 @@ */ #include "unity.h" +#include "unity_test_runner.h" #include "unity_test_utils.h" #include "esp_heap_caps.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" #define TEST_MEMORY_LEAK_THRESHOLD (200) -static size_t before_free_8bit; -static size_t before_free_32bit; - void setUp(void) { - before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + unity_utils_record_free_mem(); } void tearDown(void) { - size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); - printf("\n"); - unity_utils_check_leak(before_free_8bit, after_free_8bit, "8BIT", TEST_MEMORY_LEAK_THRESHOLD); - unity_utils_check_leak(before_free_32bit, after_free_32bit, "32BIT", TEST_MEMORY_LEAK_THRESHOLD); + esp_reent_cleanup(); //clean up some of the newlib's lazy allocations + unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD); } void app_main(void) diff --git a/components/driver/test_apps/uart/main/test_uart.c b/components/esp_driver_uart/test_apps/uart/main/test_uart.c similarity index 98% rename from components/driver/test_apps/uart/main/test_uart.c rename to components/esp_driver_uart/test_apps/uart/main/test_uart.c index 688040e649d..790f6a8e6fa 100644 --- a/components/driver/test_apps/uart/main/test_uart.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_uart.c @@ -98,7 +98,7 @@ static void test_task3(void *pvParameters) TEST_CASE("test uart_wait_tx_done is not blocked when ticks_to_wait=0", "[uart]") { xTaskCreate(test_task3, "tsk3", 4096, NULL, 5, NULL); - while(!case_end); + while (!case_end); vTaskDelay(2); // wait for test_task3 to exit } @@ -231,13 +231,13 @@ static void uart_write_task(void *param) { int uart_num = (int)param; uint8_t *tx_buf = (uint8_t *)malloc(1024); - if(tx_buf == NULL) { + if (tx_buf == NULL) { TEST_FAIL_MESSAGE("tx buffer malloc fail"); } - for(int i = 1; i < 1023; i++) { + for (int i = 1; i < 1023; i++) { tx_buf[i] = (i & 0xff); } - for(int i = 0; i < 1024; i++) { + for (int i = 0; i < 1024; i++) { //d[0] and d[1023] are header tx_buf[0] = (i & 0xff); tx_buf[1023] = ((~i) & 0xff); @@ -261,7 +261,7 @@ TEST_CASE("uart read write test", "[uart]") { const int uart_num = UART_NUM1; uint8_t *rd_data = (uint8_t *)malloc(1024); - if(rd_data == NULL) { + if (rd_data == NULL) { TEST_FAIL_MESSAGE("rx buffer malloc fail"); } uart_config_t uart_config = { @@ -330,7 +330,7 @@ TEST_CASE("uart tx with ringbuffer test", "[uart]") const int uart_num = UART_NUM1; uint8_t *rd_data = (uint8_t *)malloc(1024); uint8_t *wr_data = (uint8_t *)malloc(1024); - if(rd_data == NULL || wr_data == NULL) { + if (rd_data == NULL || wr_data == NULL) { TEST_FAIL_MESSAGE("buffer malloc fail"); } uart_config_t uart_config = { @@ -344,7 +344,7 @@ TEST_CASE("uart tx with ringbuffer test", "[uart]") }; uart_wait_tx_idle_polling(uart_num); TEST_ESP_OK(uart_param_config(uart_num, &uart_config)); - TEST_ESP_OK(uart_driver_install(uart_num, 1024 * 2, 1024 *2, 20, NULL, 0)); + TEST_ESP_OK(uart_driver_install(uart_num, 1024 * 2, 1024 * 2, 20, NULL, 0)); TEST_ESP_OK(uart_set_loop_back(uart_num, true)); TEST_ESP_OK(uart_set_pin(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART1_CTS_PIN)); //Connect the RTS out_signal to the CTS pin (which is mapped to CTS in_signal) diff --git a/components/driver/test_apps/uart/pytest_uart.py b/components/esp_driver_uart/test_apps/uart/pytest_uart.py similarity index 50% rename from components/driver/test_apps/uart/pytest_uart.py rename to components/esp_driver_uart/test_apps/uart/pytest_uart.py index a93ac513e6b..dea1980c9d2 100644 --- a/components/driver/test_apps/uart/pytest_uart.py +++ b/components/esp_driver_uart/test_apps/uart/pytest_uart.py @@ -5,6 +5,7 @@ @pytest.mark.supported_targets +@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='skip due to duplication with test_uart_single_dev_psram') @pytest.mark.generic @pytest.mark.parametrize( 'config', @@ -16,3 +17,17 @@ ) def test_uart_single_dev(case_tester) -> None: # type: ignore case_tester.run_all_normal_cases(reset=True) + + +@pytest.mark.esp32s3 +@pytest.mark.octal_psram +@pytest.mark.parametrize( + 'config', + [ + 'iram_safe', + 'release', + ], + indirect=True, +) +def test_uart_single_dev_psram(case_tester) -> None: # type: ignore + case_tester.run_all_normal_cases(reset=True) diff --git a/components/driver/test_apps/uart/sdkconfig.ci.iram_safe b/components/esp_driver_uart/test_apps/uart/sdkconfig.ci.iram_safe similarity index 100% rename from components/driver/test_apps/uart/sdkconfig.ci.iram_safe rename to components/esp_driver_uart/test_apps/uart/sdkconfig.ci.iram_safe diff --git a/components/driver/test_apps/uart/sdkconfig.ci.release b/components/esp_driver_uart/test_apps/uart/sdkconfig.ci.release similarity index 100% rename from components/driver/test_apps/uart/sdkconfig.ci.release rename to components/esp_driver_uart/test_apps/uart/sdkconfig.ci.release diff --git a/components/driver/test_apps/uart/sdkconfig.defaults b/components/esp_driver_uart/test_apps/uart/sdkconfig.defaults similarity index 100% rename from components/driver/test_apps/uart/sdkconfig.defaults rename to components/esp_driver_uart/test_apps/uart/sdkconfig.defaults diff --git a/components/esp_driver_uart/test_apps/uart/sdkconfig.defaults.esp32s3 b/components/esp_driver_uart/test_apps/uart/sdkconfig.defaults.esp32s3 new file mode 100644 index 00000000000..24336a0742e --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart/sdkconfig.defaults.esp32s3 @@ -0,0 +1,4 @@ +CONFIG_SPIRAM=y +CONFIG_SPIRAM_MODE_OCT=y +CONFIG_SPIRAM_SPEED_80M=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 diff --git a/components/esp_driver_uart/test_apps/uart_vfs/CMakeLists.txt b/components/esp_driver_uart/test_apps/uart_vfs/CMakeLists.txt new file mode 100644 index 00000000000..f1ff90157f2 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/CMakeLists.txt @@ -0,0 +1,11 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.5) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +list(PREPEND SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers" "sdkconfig.defaults") + +set(COMPONENTS main) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(uart_vfs_test) diff --git a/components/esp_driver_uart/test_apps/uart_vfs/README.md b/components/esp_driver_uart/test_apps/uart_vfs/README.md new file mode 100644 index 00000000000..bf47d80ec64 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_uart/test_apps/uart_vfs/main/CMakeLists.txt b/components/esp_driver_uart/test_apps/uart_vfs/main/CMakeLists.txt new file mode 100644 index 00000000000..c24a412b288 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/main/CMakeLists.txt @@ -0,0 +1,9 @@ +set(src "test_app_main.c" + "test_vfs_uart.c" + ) + +idf_component_register(SRCS ${src} + PRIV_INCLUDE_DIRS . + PRIV_REQUIRES esp_driver_uart unity test_utils esp_psram + WHOLE_ARCHIVE + ) diff --git a/components/esp_driver_uart/test_apps/uart_vfs/main/test_app_main.c b/components/esp_driver_uart/test_apps/uart_vfs/main/test_app_main.c new file mode 100644 index 00000000000..6ee4144067a --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/main/test_app_main.c @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "unity.h" +#include "unity_test_utils.h" +#include "esp_heap_caps.h" + +// Some resources are lazy allocated, the threadhold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (400) + +void setUp(void) +{ + unity_utils_record_free_mem(); +} + +void tearDown(void) +{ + esp_reent_cleanup(); //clean up some of the newlib's lazy allocations + unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/vfs/test_apps/main/test_vfs_uart.c b/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c similarity index 91% rename from components/vfs/test_apps/main/test_vfs_uart.c rename to components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c index 18403fb560c..561d20cf522 100644 --- a/components/vfs/test_apps/main/test_vfs_uart.c +++ b/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c @@ -10,15 +10,15 @@ #include #include #include +#include #include "unity.h" #include "esp_rom_uart.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" #include "hal/uart_ll.h" -#include "esp_vfs_dev.h" -#include "esp_vfs.h" #include "esp_clk_tree.h" #include "test_utils.h" #include "sdkconfig.h" @@ -45,7 +45,7 @@ static void flush_stdin_stdout(void) esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); } -TEST_CASE("can read from stdin", "[vfs]") +TEST_CASE("can read from stdin", "[vfs_uart]") { flush_stdin_stdout(); @@ -68,11 +68,10 @@ TEST_CASE("can read from stdin", "[vfs]") free(buf); } - -TEST_CASE("CRs are removed from the stdin correctly", "[vfs]") +TEST_CASE("CRs are removed from the stdin correctly", "[vfs_uart]") { - esp_vfs_dev_uart_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); - esp_vfs_dev_uart_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); flush_stdin_stdout(); const char* send_str = "1234567890\n\r123\r\n4\n"; @@ -155,34 +154,32 @@ static void write_task_fn(void* varg) vTaskDelete(NULL); } -TEST_CASE("can write to UART while another task is reading", "[vfs]") +TEST_CASE("can write to UART while another task is reading", "[vfs_uart]") { char out_buffer[32]; size_t out_buffer_len = sizeof(out_buffer); struct read_task_arg_t read_arg = { - .out_buffer = out_buffer, - .out_buffer_len = out_buffer_len, - .done = xSemaphoreCreateBinary() + .out_buffer = out_buffer, + .out_buffer_len = out_buffer_len, + .done = xSemaphoreCreateBinary() }; struct write_task_arg_t write_arg = { - .str = "!(@*#&(!*@&#((SDasdkjhadsl\n", - .done = xSemaphoreCreateBinary() + .str = "!(@*#&(!*@&#((SDasdkjhadsl\n", + .done = xSemaphoreCreateBinary() }; flush_stdin_stdout(); - ESP_ERROR_CHECK( uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM, - 256, 0, 0, NULL, 0) ); - esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); - + ESP_ERROR_CHECK(uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM, + 256, 0, 0, NULL, 0)); + uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); xTaskCreate(&read_task_fn, "vfs_read", 4096, &read_arg, 5, NULL); vTaskDelay(10); xTaskCreate(&write_task_fn, "vfs_write", 4096, &write_arg, 6, NULL); - int res = xSemaphoreTake(write_arg.done, 100 / portTICK_PERIOD_MS); TEST_ASSERT(res); @@ -191,13 +188,14 @@ TEST_CASE("can write to UART while another task is reading", "[vfs]") TEST_ASSERT_EQUAL(0, strcmp(write_arg.str, read_arg.out_buffer)); - esp_vfs_dev_uart_use_nonblocking(CONFIG_ESP_CONSOLE_UART_NUM); + uart_vfs_dev_use_nonblocking(CONFIG_ESP_CONSOLE_UART_NUM); uart_driver_delete(CONFIG_ESP_CONSOLE_UART_NUM); vSemaphoreDelete(read_arg.done); vSemaphoreDelete(write_arg.done); + vTaskDelay(2); // wait for tasks to exit } -TEST_CASE("fcntl supported in UART VFS", "[vfs]") +TEST_CASE("fcntl supported in UART VFS", "[vfs_uart]") { int flags = fcntl(STDIN_FILENO, F_GETFL, 0); TEST_ASSERT_NOT_EQUAL(-1, flags); @@ -209,7 +207,7 @@ TEST_CASE("fcntl supported in UART VFS", "[vfs]") } #ifdef CONFIG_VFS_SUPPORT_TERMIOS -TEST_CASE("Can use termios for UART", "[vfs]") +TEST_CASE("Can use termios for UART", "[vfs_uart]") { uint32_t clk_src_hz = 0; TEST_ESP_OK(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_hz)); @@ -226,7 +224,7 @@ TEST_CASE("Can use termios for UART", "[vfs]") const int uart_fd = open("/dev/uart/1", O_RDWR); TEST_ASSERT_NOT_EQUAL_MESSAGE(uart_fd, -1, "Cannot open UART"); - esp_vfs_dev_uart_use_driver(1); + uart_vfs_dev_use_driver(1); TEST_ASSERT_EQUAL(-1, tcgetattr(uart_fd, NULL)); TEST_ASSERT_EQUAL(EINVAL, errno); @@ -343,7 +341,7 @@ TEST_CASE("Can use termios for UART", "[vfs]") memset(&tios_result, 0xFF, sizeof(struct termios)); } - esp_vfs_dev_uart_use_nonblocking(1); + uart_vfs_dev_use_nonblocking(1); close(uart_fd); uart_driver_delete(UART_NUM_1); } diff --git a/components/esp_driver_uart/test_apps/uart_vfs/partitions.csv b/components/esp_driver_uart/test_apps/uart_vfs/partitions.csv new file mode 100644 index 00000000000..b31d4e80fd2 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +factory, 0, 0, 0x10000, 1M +flash_test, data, fat, , 528K diff --git a/components/esp_driver_uart/test_apps/uart_vfs/pytest_uart_vfs.py b/components/esp_driver_uart/test_apps/uart_vfs/pytest_uart_vfs.py new file mode 100644 index 00000000000..131d8c94231 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/pytest_uart_vfs.py @@ -0,0 +1,24 @@ +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='skip due to duplication with test_uart_vfs_psram') +@pytest.mark.generic +@pytest.mark.parametrize('config', [ + 'default', 'iram', +], indirect=True) +def test_uart_vfs_default(dut: Dut) -> None: + dut.run_all_single_board_cases() + + +@pytest.mark.esp32s3 +@pytest.mark.quad_psram +@pytest.mark.parametrize('config', [ + 'default', 'iram', +], indirect=True) +def test_uart_vfs_psram(dut: Dut) -> None: + dut.run_all_single_board_cases() diff --git a/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.ci.default b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.ci.default new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.ci.iram b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.ci.iram new file mode 100644 index 00000000000..328d7f113c9 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.ci.iram @@ -0,0 +1 @@ +CONFIG_UART_ISR_IN_IRAM=y diff --git a/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.defaults b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.defaults new file mode 100644 index 00000000000..728b21c79f2 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.defaults @@ -0,0 +1,9 @@ +# Enable Unity fixture support +CONFIG_UNITY_ENABLE_FIXTURE=n +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y + +# Custom partition table for this test app +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" + +CONFIG_ESP_TASK_WDT_INIT=n diff --git a/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.defaults.esp32s3 b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.defaults.esp32s3 new file mode 100644 index 00000000000..e831880d075 --- /dev/null +++ b/components/esp_driver_uart/test_apps/uart_vfs/sdkconfig.defaults.esp32s3 @@ -0,0 +1,3 @@ +CONFIG_SPIRAM=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y diff --git a/components/esp_eth/include/esp_eth_driver.h b/components/esp_eth/include/esp_eth_driver.h index f6f358f0155..068a911dfb1 100644 --- a/components/esp_eth/include/esp_eth_driver.h +++ b/components/esp_eth/include/esp_eth_driver.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -121,6 +121,15 @@ typedef struct { esp_err_t (*write_phy_reg)(esp_eth_handle_t eth_handle, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value); } esp_eth_config_t; +/** + * @brief Data structure to Read/Write PHY register via ioctl API + * + */ +typedef struct { + uint32_t reg_addr; /*!< PHY register address */ + uint32_t *reg_value_p; /*!< Pointer to a memory where the register value is read/written */ +} esp_eth_phy_reg_rw_data_t; + /** * @brief Command list for ioctl API * @@ -139,6 +148,8 @@ typedef enum { ETH_CMD_G_DUPLEX_MODE, /*!< Get Duplex mode */ ETH_CMD_S_DUPLEX_MODE, /*!< Set Duplex mode */ ETH_CMD_S_PHY_LOOPBACK, /*!< Set PHY loopback */ + ETH_CMD_READ_PHY_REG, /*!< Read PHY register */ + ETH_CMD_WRITE_PHY_REG, /*!< Write PHY register */ ETH_CMD_CUSTOM_MAC_CMDS = 0x0FFF, // Offset for start of MAC custom commands ETH_CMD_CUSTOM_PHY_CMDS = 0x1FFF, // Offset for start of PHY custom commands diff --git a/components/esp_eth/src/esp_eth.c b/components/esp_eth/src/esp_eth.c index 90cc8a229ff..6590ae15e93 100644 --- a/components/esp_eth/src/esp_eth.c +++ b/components/esp_eth/src/esp_eth.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -466,7 +466,23 @@ esp_err_t esp_eth_ioctl(esp_eth_handle_t hdl, esp_eth_io_cmd_t cmd, void *data) case ETH_CMD_S_PHY_LOOPBACK: ESP_GOTO_ON_FALSE(data, ESP_ERR_INVALID_ARG, err, TAG, "can't set loopback to null"); ESP_GOTO_ON_ERROR(phy->loopback(phy, *(bool *)data), err, TAG, "configuration of phy loopback mode failed"); - + break; + case ETH_CMD_READ_PHY_REG: + uint32_t phy_addr; + ESP_GOTO_ON_FALSE(data, ESP_ERR_INVALID_ARG, err, TAG, "invalid register read/write info"); + esp_eth_phy_reg_rw_data_t *phy_r_data = (esp_eth_phy_reg_rw_data_t *)data; + ESP_GOTO_ON_FALSE(phy_r_data->reg_value_p, ESP_ERR_INVALID_ARG, err, TAG, "can't read registers to null"); + ESP_GOTO_ON_ERROR(phy->get_addr(phy, &phy_addr), err, TAG, "get phy address failed"); + ESP_GOTO_ON_ERROR(eth_driver->mediator.phy_reg_read(ð_driver->mediator, + phy_addr, phy_r_data->reg_addr, phy_r_data->reg_value_p), err, TAG, "failed to read PHY register"); + break; + case ETH_CMD_WRITE_PHY_REG: + ESP_GOTO_ON_FALSE(data, ESP_ERR_INVALID_ARG, err, TAG, "invalid register read/write info"); + esp_eth_phy_reg_rw_data_t *phy_w_data = (esp_eth_phy_reg_rw_data_t *)data; + ESP_GOTO_ON_FALSE(phy_w_data->reg_value_p, ESP_ERR_INVALID_ARG, err, TAG, "can't write registers from null"); + ESP_GOTO_ON_ERROR(phy->get_addr(phy, &phy_addr), err, TAG, "get phy address failed"); + ESP_GOTO_ON_ERROR(eth_driver->mediator.phy_reg_write(ð_driver->mediator, + phy_addr, phy_w_data->reg_addr, *(phy_w_data->reg_value_p)), err, TAG, "failed to write PHY register"); break; default: if (phy->custom_ioctl != NULL && cmd >= ETH_CMD_CUSTOM_PHY_CMDS) { diff --git a/components/esp_eth/src/esp_eth_phy_lan87xx.c b/components/esp_eth/src/esp_eth_phy_lan87xx.c index 621f0b74782..b63242d660e 100644 --- a/components/esp_eth/src/esp_eth_phy_lan87xx.c +++ b/components/esp_eth/src/esp_eth_phy_lan87xx.c @@ -6,6 +6,8 @@ #include #include #include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" #include "esp_log.h" #include "esp_check.h" #include "esp_eth_phy_802_3.h" @@ -317,6 +319,19 @@ static esp_err_t lan87xx_loopback(esp_eth_phy_t *phy, bool enable) return ret; } +static esp_err_t lan87xx_set_speed(esp_eth_phy_t *phy, eth_speed_t speed) +{ + esp_err_t ret = ESP_OK; + phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy); + + /* It was observed that a delay needs to be introduced after setting speed and prior driver's start. + Otherwise, the very first read of PHY registers is not valid data (0xFFFF's). */ + ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_set_speed(phy_802_3, speed), err, TAG, "set speed failed"); + vTaskDelay(pdMS_TO_TICKS(10)); +err: + return ret; +} + static esp_err_t lan87xx_init(esp_eth_phy_t *phy) { esp_err_t ret = ESP_OK; @@ -359,6 +374,7 @@ esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config) lan87xx->phy_802_3.parent.get_link = lan87xx_get_link; lan87xx->phy_802_3.parent.autonego_ctrl = lan87xx_autonego_ctrl; lan87xx->phy_802_3.parent.loopback = lan87xx_loopback; + lan87xx->phy_802_3.parent.set_speed = lan87xx_set_speed; return &lan87xx->phy_802_3.parent; err: diff --git a/components/esp_eth/test_apps/main/Kconfig.projbuild b/components/esp_eth/test_apps/main/Kconfig.projbuild index b9ac8825dbf..61b15841e72 100644 --- a/components/esp_eth/test_apps/main/Kconfig.projbuild +++ b/components/esp_eth/test_apps/main/Kconfig.projbuild @@ -30,10 +30,10 @@ menu "esp_eth TEST_APPS Configuration" config TARGET_ETH_PHY_DEVICE_IP101 bool "IP101" - config TARGET_ETH_PHY_DEVICE_LAN87XX + config TARGET_ETH_PHY_DEVICE_LAN8720 bool "LAN8720" - config TARGET_ETH_PHY_DEVICE_KSZ80XX - bool "KSZ80xx" + config TARGET_ETH_PHY_DEVICE_KSZ8041 + bool "KSZ8041" config TARGET_ETH_PHY_DEVICE_RTL8201 bool "RTL8201" config TARGET_ETH_PHY_DEVICE_DP83848 diff --git a/components/esp_eth/test_apps/main/esp_eth_test_apps.c b/components/esp_eth/test_apps/main/esp_eth_test_apps.c index 3532df46c40..91fe20fa33c 100644 --- a/components/esp_eth/test_apps/main/esp_eth_test_apps.c +++ b/components/esp_eth/test_apps/main/esp_eth_test_apps.c @@ -164,6 +164,23 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]") // set new speed TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_S_SPEED, &speed)); +// *** LAN8720 deviation *** +// Rationale: When the device is in manual 100BASE-TX or 10BASE-T modes with Auto-MDIX enabled, the PHY does not link to a +// link partner that is configured for auto-negotiation. See LAN8720 errata for more details. +#ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720 + esp_eth_phy_reg_rw_data_t reg; + uint32_t reg_val; + reg.reg_addr = 27; + reg.reg_value_p = ®_val; + TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®)); + reg_val |= 0x8000; + TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, ®)); + uint32_t reg_val_act; + reg.reg_value_p = ®_val_act; + TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®)); + TEST_ASSERT_EQUAL(reg_val, reg_val_act); +#endif + // start the driver and wait for connection establish esp_eth_start(eth_handle); bits = xEventGroupWaitBits(eth_event_group, ETH_CONNECT_BIT, true, true, pdMS_TO_TICKS(ETH_CONNECT_TIMEOUT_MS)); @@ -242,6 +259,19 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]") esp_eth_stop(eth_handle); auto_nego_en = true; esp_eth_ioctl(eth_handle, ETH_CMD_S_AUTONEGO, &auto_nego_en); + +// *** LAN8720 deviation *** +// Rationale: See above +#ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720 + reg.reg_value_p = ®_val; + TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®)); + reg_val &= ~0x8000; + TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, ®)); + reg.reg_value_p = ®_val_act; + TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®)); + TEST_ASSERT_EQUAL(reg_val, reg_val_act); +#endif + esp_eth_start(eth_handle); bits = xEventGroupWaitBits(eth_event_group, ETH_CONNECT_BIT, true, true, pdMS_TO_TICKS(ETH_CONNECT_TIMEOUT_MS)); TEST_ASSERT((bits & ETH_CONNECT_BIT) == ETH_CONNECT_BIT); @@ -273,7 +303,7 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]") static SemaphoreHandle_t loopback_test_case_data_received; static esp_err_t loopback_test_case_incoming_handler(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv) { - TEST_ASSERT(memcmp(priv, buffer, LOOPBACK_TEST_PACKET_SIZE) == 0) + TEST_ASSERT(memcmp(priv, buffer, LOOPBACK_TEST_PACKET_SIZE) == 0); xSemaphoreGive(loopback_test_case_data_received); free(buffer); return ESP_OK; @@ -328,7 +358,7 @@ TEST_CASE("ethernet io loopback", "[ethernet]") ESP_LOGI(TAG, "Test with %s Mbps %s duplex.", expected_speed == ETH_SPEED_10M ? "10" : "100", expected_duplex == ETH_DUPLEX_HALF ? "half" : "full"); // *** KSZ80XX, KSZ8851SNL and DM9051 deviation *** // Rationale: do not support loopback at 10 Mbps -#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_KSZ80XX) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DM9051) +#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_KSZ8041) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DM9051) if ((expected_speed == ETH_SPEED_10M)) { TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, esp_eth_ioctl(eth_handle, ETH_CMD_S_SPEED, &expected_speed)); continue; @@ -378,7 +408,7 @@ TEST_CASE("ethernet io loopback", "[ethernet]") // *** RTL8201, DP83848 and LAN87xx deviation *** // Rationale: do not support autonegotiation with loopback enabled. #if defined(CONFIG_TARGET_ETH_PHY_DEVICE_RTL8201) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DP83848) || \ - defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX) + defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, esp_eth_ioctl(eth_handle, ETH_CMD_S_AUTONEGO, &auto_nego_en)); goto cleanup; #endif @@ -397,7 +427,7 @@ TEST_CASE("ethernet io loopback", "[ethernet]") TEST_ASSERT((bits & ETH_STOP_BIT) == ETH_STOP_BIT); // *** W5500, LAN87xx, RTL8201 and DP83848 deviation *** // Rationale: in those cases 'goto cleanup' is used to skip part of the test code. Incasing in #if block is done to prevent unused label error -#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_W5500) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX) || \ +#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_W5500) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) || \ defined(CONFIG_TARGET_ETH_PHY_DEVICE_RTL8201) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DP83848) cleanup: #endif diff --git a/components/esp_eth/test_apps/main/esp_eth_test_common.c b/components/esp_eth/test_apps/main/esp_eth_test_common.c index 0a04d9561ed..69f5577abdd 100644 --- a/components/esp_eth/test_apps/main/esp_eth_test_common.c +++ b/components/esp_eth/test_apps/main/esp_eth_test_common.c @@ -96,9 +96,9 @@ esp_eth_phy_t *phy_init(eth_phy_config_t *phy_config) phy_config->phy_addr = ESP_ETH_PHY_ADDR_AUTO; #if CONFIG_TARGET_ETH_PHY_DEVICE_IP101 phy = esp_eth_phy_new_ip101(phy_config); -#elif CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX +#elif CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720 phy = esp_eth_phy_new_lan87xx(phy_config); -#elif CONFIG_TARGET_ETH_PHY_DEVICE_KSZ80XX +#elif CONFIG_TARGET_ETH_PHY_DEVICE_KSZ8041 phy = esp_eth_phy_new_ksz80xx(phy_config); #elif CONFIG_TARGET_ETH_PHY_DEVICE_RTL8201 phy = esp_eth_phy_new_rtl8201(phy_config); diff --git a/components/esp_eth/test_apps/sdkconfig.ci.default_ksz8041 b/components/esp_eth/test_apps/sdkconfig.ci.default_ksz8041 index ecb0066f5e4..6a6547adf78 100644 --- a/components/esp_eth/test_apps/sdkconfig.ci.default_ksz8041 +++ b/components/esp_eth/test_apps/sdkconfig.ci.default_ksz8041 @@ -6,4 +6,4 @@ CONFIG_ETH_USE_ESP32_EMAC=y CONFIG_ESP_TASK_WDT=n CONFIG_TARGET_USE_INTERNAL_ETHERNET=y -CONFIG_TARGET_ETH_PHY_DEVICE_KSZ80XX=y +CONFIG_TARGET_ETH_PHY_DEVICE_KSZ8041=y diff --git a/components/esp_eth/test_apps/sdkconfig.ci.default_lan8720 b/components/esp_eth/test_apps/sdkconfig.ci.default_lan8720 index 1539599da09..c13b8b5f2c1 100644 --- a/components/esp_eth/test_apps/sdkconfig.ci.default_lan8720 +++ b/components/esp_eth/test_apps/sdkconfig.ci.default_lan8720 @@ -6,6 +6,6 @@ CONFIG_ETH_USE_ESP32_EMAC=y CONFIG_ESP_TASK_WDT_EN=n CONFIG_TARGET_USE_INTERNAL_ETHERNET=y -CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX=y +CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720=y CONFIG_ETH_RMII_CLK_OUTPUT=y CONFIG_ETH_RMII_CLK_OUT_GPIO=17 diff --git a/components/esp_event/host_test/.build-test-rules.yml b/components/esp_event/host_test/.build-test-rules.yml new file mode 100644 index 00000000000..c4369d5869f --- /dev/null +++ b/components/esp_event/host_test/.build-test-rules.yml @@ -0,0 +1,3 @@ +components/esp_event/host_test: + enable: + - if: IDF_TARGET == "linux" diff --git a/components/esp_event/host_test/esp_event_unit_test/main/CMakeLists.txt b/components/esp_event/host_test/esp_event_unit_test/main/CMakeLists.txt index e1185696436..0ee0e7d59ca 100644 --- a/components/esp_event/host_test/esp_event_unit_test/main/CMakeLists.txt +++ b/components/esp_event/host_test/esp_event_unit_test/main/CMakeLists.txt @@ -1,3 +1,8 @@ idf_component_register(SRCS "esp_event_test.cpp" - INCLUDE_DIRS "../../" $ENV{IDF_PATH}/tools/catch - REQUIRES esp_event cmock) + INCLUDE_DIRS "../../" + REQUIRES esp_event cmock + WHOLE_ARCHIVE) + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/esp_event/host_test/esp_event_unit_test/main/esp_event_test.cpp b/components/esp_event/host_test/esp_event_unit_test/main/esp_event_test.cpp index 16c2c590c5c..524a3e5e467 100644 --- a/components/esp_event/host_test/esp_event_unit_test/main/esp_event_test.cpp +++ b/components/esp_event/host_test/esp_event_unit_test/main/esp_event_test.cpp @@ -7,12 +7,11 @@ CONDITIONS OF ANY KIND, either express or implied. */ -#define CATCH_CONFIG_MAIN #include #include "esp_event.h" -#include "catch.hpp" +#include #include "fixtures.hpp" diff --git a/components/esp_event/host_test/esp_event_unit_test/main/idf_component.yml b/components/esp_event/host_test/esp_event_unit_test/main/idf_component.yml new file mode 100644 index 00000000000..f7982136b97 --- /dev/null +++ b/components/esp_event/host_test/esp_event_unit_test/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/catch2: "^3.4.0" diff --git a/components/esp_event/host_test/fixtures.hpp b/components/esp_event/host_test/fixtures.hpp index 0ae8ef47804..24c4bfbe04f 100644 --- a/components/esp_event/host_test/fixtures.hpp +++ b/components/esp_event/host_test/fixtures.hpp @@ -9,11 +9,12 @@ #include "esp_event.h" -#include "catch.hpp" +#include extern "C" { #include "Mocktask.h" #include "Mockqueue.h" +#include "Mockidf_additions.h" } /** @@ -129,11 +130,11 @@ struct MockTask : public CMockFix { xTaskCreatePinnedToCore_ExpectAnyArgsAndReturn(pdFALSE); } else if (flags == CreateAnd::IGNORE) { xTaskCreatePinnedToCore_IgnoreAndReturn(pdTRUE); - xTaskCreatePinnedToCore_ReturnThruPtr_pvCreatedTask(&task); + xTaskCreatePinnedToCore_ReturnThruPtr_pxCreatedTask(&task); vTaskDelete_Ignore(); } else { xTaskCreatePinnedToCore_ExpectAnyArgsAndReturn(pdTRUE); - xTaskCreatePinnedToCore_ReturnThruPtr_pvCreatedTask(&task); + xTaskCreatePinnedToCore_ReturnThruPtr_pxCreatedTask(&task); vTaskDelete_Expect(task); } } diff --git a/components/esp_event/test_apps/main/test_event_target.c b/components/esp_event/test_apps/main/test_event_target.c index f949319b7f2..bd9264119f1 100644 --- a/components/esp_event/test_apps/main/test_event_target.c +++ b/components/esp_event/test_apps/main/test_event_target.c @@ -720,7 +720,7 @@ bool test_event_on_timer_alarm(gptimer_handle_t timer, const gptimer_alarm_event TEST_CASE("can post events from interrupt handler", "[event][intr]") { /* Lazy allocated resources in gptimer/intr_alloc */ - unity_utils_set_leak_level(150); + unity_utils_set_leak_level(160); TEST_ESP_OK(esp_event_loop_create_default()); diff --git a/components/esp_gdbstub/src/gdbstub.c b/components/esp_gdbstub/src/gdbstub.c index f16790f0f68..08ccd2ef130 100644 --- a/components/esp_gdbstub/src/gdbstub.c +++ b/components/esp_gdbstub/src/gdbstub.c @@ -925,14 +925,14 @@ static int get_task_cpu_id(size_t index) if (!get_task_handle(index, &handle)) { return -1; } - BaseType_t core_id = xTaskGetAffinity(handle); + BaseType_t core_id = xTaskGetCoreID(handle); return (int)core_id; } /** Get the index of the task running on the current CPU, and save the result */ static void find_paniced_task_index(void) { - TaskHandle_t cur_handle = (TaskHandle_t)xTaskGetCurrentTaskHandleForCPU(xPortGetCoreID()); + TaskHandle_t cur_handle = (TaskHandle_t)xTaskGetCurrentTaskHandleForCore(xPortGetCoreID()); TaskHandle_t handle; for (int i = 0; i < s_scratch.task_count; i++) { if (get_task_handle(i, &handle) && cur_handle == handle) { diff --git a/components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c b/components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c index 2fb05d0b3bc..e83b4352a30 100644 --- a/components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c +++ b/components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c @@ -96,13 +96,13 @@ void esp_gdbstub_init_dports(void) #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME -#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME static bool stall_started = false; #endif void esp_gdbstub_stall_other_cpus_start(void) { -#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME if (stall_started == false) { esp_ipc_isr_stall_other_cpu(); stall_started = true; @@ -112,7 +112,7 @@ void esp_gdbstub_stall_other_cpus_start(void) void esp_gdbstub_stall_other_cpus_end(void) { -#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME if (stall_started == true) { esp_ipc_isr_release_other_cpu(); stall_started = false; @@ -142,7 +142,7 @@ void esp_gdbstub_do_step(esp_gdbstub_frame_t *frame) void esp_gdbstub_trigger_cpu(void) { -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE if (0 == esp_cpu_get_core_id()) { esp_crosscore_int_send_gdb_call(1); } else { diff --git a/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c b/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c index fa452d5b8a1..b4f201101e7 100644 --- a/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c +++ b/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c @@ -132,7 +132,7 @@ void esp_gdbstub_init_dports(void) { } -#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME static bool stall_started = false; #endif @@ -141,7 +141,7 @@ static bool stall_started = false; * */ void esp_gdbstub_stall_other_cpus_start(void) { -#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME if (stall_started == false) { esp_ipc_isr_stall_other_cpu(); stall_started = true; @@ -154,7 +154,7 @@ void esp_gdbstub_stall_other_cpus_start(void) * */ void esp_gdbstub_stall_other_cpus_end(void) { -#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME +#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME if (stall_started == true) { esp_ipc_isr_release_other_cpu(); stall_started = false; @@ -193,7 +193,7 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame) * */ void esp_gdbstub_trigger_cpu(void) { -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE if (0 == esp_cpu_get_core_id()) { esp_crosscore_int_send_gdb_call(1); } else { diff --git a/components/esp_gdbstub/src/port/xtensa/include/esp_gdbstub_arch.h b/components/esp_gdbstub/src/port/xtensa/include/esp_gdbstub_arch.h index 16a38db0193..1efe761cefa 100644 --- a/components/esp_gdbstub/src/port/xtensa/include/esp_gdbstub_arch.h +++ b/components/esp_gdbstub/src/port/xtensa/include/esp_gdbstub_arch.h @@ -6,7 +6,7 @@ #pragma once #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S b/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S index 4d90e36e6d7..da9b489077c 100644 --- a/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S +++ b/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S @@ -7,7 +7,7 @@ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" .section .iram1,"ax" .global _xt_panic_gdbstub diff --git a/components/esp_hid/CMakeLists.txt b/components/esp_hid/CMakeLists.txt index a2edf17a166..d91bfd4e794 100644 --- a/components/esp_hid/CMakeLists.txt +++ b/components/esp_hid/CMakeLists.txt @@ -19,6 +19,11 @@ if(CONFIG_BT_ENABLED) "src/bt_hidh.c" "src/bt_hidd.c") endif() + if(CONFIG_BT_NIMBLE_ENABLED) + list(APPEND srcs + "src/nimble_hidd.c" + "src/nimble_hidh.c") + endif() endif() idf_component_register(SRCS "${srcs}" diff --git a/components/esp_hid/include/esp_hidh_nimble.h b/components/esp_hid/include/esp_hidh_nimble.h new file mode 100644 index 00000000000..b9f95d05a17 --- /dev/null +++ b/components/esp_hid/include/esp_hidh_nimble.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif +#include "sdkconfig.h" + +#if CONFIG_BT_NIMBLE_ENABLED +/** + * @brief Open BlueTooth HID Device using BlueDroid + * @param bda : BT Device Address + * @param transport : BT Device Protocol (Classic/HID) + * @param remote_addr_type : BLE Remote address type + * + * @return: ESP_OK on success + */ +esp_hidh_dev_t *esp_hidh_dev_open(uint8_t *bda, esp_hid_transport_t transport, uint8_t remote_addr_type); +#endif /* CONFIG_BT_NIMBLE_ENABLED */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hid/include/esp_hidh_transport.h b/components/esp_hid/include/esp_hidh_transport.h index 22138aef8ec..626005bb423 100644 --- a/components/esp_hid/include/esp_hidh_transport.h +++ b/components/esp_hid/include/esp_hidh_transport.h @@ -1,16 +1,8 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -28,6 +20,10 @@ extern "C" { #include "esp_hidh_bluedroid.h" #endif +#if CONFIG_BT_NIMBLE_ENABLED +#include "esp_hidh_nimble.h" +#endif + #ifdef __cplusplus } #endif diff --git a/components/esp_hid/private/ble_hidd.h b/components/esp_hid/private/ble_hidd.h index 087d816c035..7bcd7327327 100644 --- a/components/esp_hid/private/ble_hidd.h +++ b/components/esp_hid/private/ble_hidd.h @@ -1,16 +1,8 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -22,7 +14,7 @@ extern "C" { #endif -#if CONFIG_GATTS_ENABLE +#if CONFIG_GATTS_ENABLE || CONFIG_BT_NIMBLE_ENABLED esp_err_t esp_ble_hidd_dev_init(esp_hidd_dev_t *dev, const esp_hid_device_config_t *config, esp_event_handler_t callback); diff --git a/components/esp_hid/private/ble_hidh.h b/components/esp_hid/private/ble_hidh.h index 131f0648058..331579bd21b 100644 --- a/components/esp_hid/private/ble_hidh.h +++ b/components/esp_hid/private/ble_hidh.h @@ -1,16 +1,8 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -20,12 +12,16 @@ extern "C" { #endif -#if CONFIG_GATTC_ENABLE +#if CONFIG_GATTC_ENABLE || CONFIG_BT_NIMBLE_ENABLED esp_err_t esp_ble_hidh_init(const esp_hidh_config_t *config); esp_err_t esp_ble_hidh_deinit(void); +#if CONFIG_BT_NIMBLE_ENABLED +esp_hidh_dev_t *esp_ble_hidh_dev_open(uint8_t *bda, uint8_t address_type); +#else esp_hidh_dev_t *esp_ble_hidh_dev_open(esp_bd_addr_t bda, esp_ble_addr_type_t address_type); +#endif #endif /* CONFIG_GATTC_ENABLE */ diff --git a/components/esp_hid/private/esp_hidh_private.h b/components/esp_hid/private/esp_hidh_private.h index a6ffda9443a..f567508d613 100644 --- a/components/esp_hid/private/esp_hidh_private.h +++ b/components/esp_hid/private/esp_hidh_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,9 @@ #include "esp_event.h" #include "sys/queue.h" #include "esp_timer.h" +#if CONFIG_BT_NIMBLE_ENABLED +#include "nimble/ble.h" +#endif #ifdef __cplusplus extern "C" { @@ -52,7 +55,11 @@ struct esp_hidh_dev_s { esp_timer_handle_t trans_timer; //transactiion timer uint8_t report_type; //Get_Report tansaction report_type uint8_t report_id; //Get_Report tansaction report_id +#if CONFIG_BT_NIMBLE_ENABLED + uint8_t *protocol_mode; // protocol mode is unique for each hid service instance +#else uint8_t protocol_mode; //device protocol mode +#endif bool connected; //we have all required data to communicate bool opened; //we opened the device manually, else the device connected to us bool added; //If lower layer has added the device @@ -82,6 +89,9 @@ struct esp_hidh_dev_s { #if CONFIG_BLUEDROID_ENABLED esp_bd_addr_t bda; #endif /* CONFIG_BLUEDROID_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED + uint8_t bda[6]; +#endif union { #if CONFIG_BT_HID_HOST_ENABLED @@ -102,6 +112,15 @@ struct esp_hidh_dev_s { uint16_t battery_ccc_handle; } ble; #endif /* CONFIG_GATTC_ENABLE */ +#if CONFIG_BT_NIMBLE_ENABLED + struct { + uint8_t address_type; + int conn_id; + uint16_t appearance; + uint16_t battery_handle; + uint16_t battery_ccc_handle; + } ble; +#endif }; TAILQ_ENTRY(esp_hidh_dev_s) devices; }; @@ -115,6 +134,10 @@ esp_hidh_dev_t *esp_hidh_dev_get_by_bda(esp_bd_addr_t bda); //BT/BLE esp_hidh_dev_t *esp_hidh_dev_get_by_handle(uint8_t handle); //Classic Bluetooth Only esp_hidh_dev_t *esp_hidh_dev_get_by_conn_id(uint16_t conn_id); //BLE Only #endif /* CONFIG_BLUEDROID_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED +esp_hidh_dev_t *esp_hidh_dev_get_by_bda(uint8_t* bda); // BLE Only +esp_hidh_dev_t *esp_hidh_dev_get_by_conn_id(uint16_t conn_id); //BLE Only +#endif esp_hidh_dev_report_t *esp_hidh_dev_get_report_by_id_type_proto(esp_hidh_dev_t *dev, size_t map_index, size_t report_id, int report_type, uint8_t protocol_mode); esp_hidh_dev_report_t *esp_hidh_dev_get_report_by_id_and_type(esp_hidh_dev_t *dev, size_t map_index, size_t report_id, int report_type); diff --git a/components/esp_hid/src/esp_hid_common.c b/components/esp_hid/src/esp_hid_common.c index b549d006630..69d987fcbff 100644 --- a/components/esp_hid/src/esp_hid_common.c +++ b/components/esp_hid/src/esp_hid_common.c @@ -1,16 +1,8 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include "esp_log.h" diff --git a/components/esp_hid/src/esp_hidd.c b/components/esp_hid/src/esp_hidd.c index b3216023ccd..571f963d659 100644 --- a/components/esp_hid/src/esp_hidd.c +++ b/components/esp_hid/src/esp_hidd.c @@ -8,7 +8,7 @@ #include "esp_hidd_private.h" #include "esp_event_base.h" -#if CONFIG_GATTS_ENABLE +#if CONFIG_GATTS_ENABLE || CONFIG_BT_NIMBLE_ENABLED #include "ble_hidd.h" #endif /* CONFIG_GATTS_ENABLE */ @@ -27,7 +27,7 @@ esp_err_t esp_hidd_dev_init(const esp_hid_device_config_t *config, esp_hid_trans } switch (transport) { -#if CONFIG_GATTS_ENABLE +#if CONFIG_GATTS_ENABLE || CONFIG_BT_NIMBLE_ENABLED case ESP_HID_TRANSPORT_BLE: ret = esp_ble_hidd_dev_init(dev, config, callback); break; diff --git a/components/esp_hid/src/esp_hidh.c b/components/esp_hid/src/esp_hidh.c index 5102105d6de..c4e18e0291e 100644 --- a/components/esp_hid/src/esp_hidh.c +++ b/components/esp_hid/src/esp_hidh.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -88,7 +88,7 @@ esp_err_t esp_hidh_init(const esp_hidh_config_t *config) } #endif /* CONFIG_BT_HID_HOST_ENABLED */ -#if CONFIG_GATTC_ENABLE +#if CONFIG_GATTC_ENABLE || CONFIG_BT_NIMBLE_ENABLED if (err == ESP_OK) { err = esp_ble_hidh_init(config); } @@ -123,7 +123,7 @@ esp_err_t esp_hidh_deinit(void) } #endif /* CONFIG_BT_HID_HOST_ENABLED */ -#if CONFIG_GATTC_ENABLE +#if CONFIG_GATTC_ENABLE || CONFIG_BT_NIMBLE_ENABLED if (err == ESP_OK) { err = esp_ble_hidh_deinit(); } @@ -150,6 +150,11 @@ esp_hidh_dev_t *esp_hidh_dev_open(esp_bd_addr_t bda, esp_hid_transport_t transpo dev = esp_ble_hidh_dev_open(bda, (esp_ble_addr_type_t)remote_addr_type); } #endif /* CONFIG_GATTC_ENABLE */ +#if CONFIG_BT_NIMBLE_ENABLED + if (transport == ESP_HID_TRANSPORT_BLE) { + dev = esp_ble_hidh_dev_open(bda, remote_addr_type); + } +#endif /* CONFIG_BT_NIMBLE_ENABLED */ #if CONFIG_BT_HID_HOST_ENABLED if (transport == ESP_HID_TRANSPORT_BT) { dev = esp_bt_hidh_dev_open(bda); @@ -159,6 +164,19 @@ esp_hidh_dev_t *esp_hidh_dev_open(esp_bd_addr_t bda, esp_hid_transport_t transpo } #endif /* CONFIG_BLUEDROID_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED +esp_hidh_dev_t *esp_hidh_dev_open(uint8_t *bda, esp_hid_transport_t transport, uint8_t remote_addr_type) +{ + if (esp_hidh_dev_get_by_bda(bda) != NULL) { + ESP_LOGE(TAG, "Already Connected"); + return NULL; + } + esp_hidh_dev_t *dev = NULL; + dev = esp_ble_hidh_dev_open(bda, remote_addr_type); + return dev; +} +#endif /* CONFIG_BT_NIMBLE_ENABLED */ + esp_err_t esp_hidh_dev_close(esp_hidh_dev_t *dev) { esp_err_t ret = ESP_OK; @@ -329,6 +347,14 @@ const uint8_t *esp_hidh_dev_bda_get(esp_hidh_dev_t *dev) esp_hidh_dev_unlock(dev); } #endif /* CONFIG_BLUEDROID_ENABLED */ + +#if CONFIG_BT_NIMBLE_ENABLED + if (esp_hidh_dev_exists(dev)) { + esp_hidh_dev_lock(dev); + ret = dev->bda; + esp_hidh_dev_unlock(dev); + } +#endif /* CONFIG_BT_NIMBLE_ENABLED */ return ret; } @@ -823,3 +849,82 @@ void esp_hidh_post_process_event_handler(void *event_handler_arg, esp_event_base } } #endif /* CONFIG_BLUEDROID_ENABLED */ + +#if CONFIG_BT_NIMBLE_ENABLED +esp_hidh_dev_t *esp_hidh_dev_get_by_bda(uint8_t *bda) +{ + esp_hidh_dev_t * d = NULL; + lock_devices(); + TAILQ_FOREACH(d, &s_esp_hidh_devices, devices) { + if (memcmp(bda, d->bda, sizeof(uint8_t) * 6) == 0) { + unlock_devices(); + return d; + } + } + unlock_devices(); + return NULL; +} + +esp_hidh_dev_t *esp_hidh_dev_get_by_conn_id(uint16_t conn_id) +{ + esp_hidh_dev_t * d = NULL; + lock_devices(); + TAILQ_FOREACH(d, &s_esp_hidh_devices, devices) { + if (d->ble.conn_id == conn_id) { + unlock_devices(); + return d; + } + } + unlock_devices(); + return NULL; +} + +/** + * The deep copy data append the end of the esp_hidh_event_data_t, move the data pointer to the correct address. This is + * a workaround way, it's better to use flexible array in the interface. + */ +void esp_hidh_preprocess_event_handler(void *event_handler_arg, esp_event_base_t event_base, int32_t event_id, + void *event_data) +{ + esp_hidh_event_t event = (esp_hidh_event_t)event_id; + esp_hidh_event_data_t *param = (esp_hidh_event_data_t *)event_data; + + switch (event) { + case ESP_HIDH_INPUT_EVENT: + if (param->input.length && param->input.data) { + param->input.data = (uint8_t *)param + sizeof(esp_hidh_event_data_t); + } + break; + case ESP_HIDH_FEATURE_EVENT: + if (param->feature.length && param->feature.data) { + param->feature.data = (uint8_t *)param + sizeof(esp_hidh_event_data_t); + } + break; + default: + break; + } +} + +void esp_hidh_post_process_event_handler(void *event_handler_arg, esp_event_base_t event_base, int32_t event_id, + void *event_data) +{ + esp_hidh_event_t event = (esp_hidh_event_t)event_id; + esp_hidh_event_data_t *param = (esp_hidh_event_data_t *)event_data; + + switch (event) { + case ESP_HIDH_OPEN_EVENT: + if (param->open.status != ESP_OK) { + esp_hidh_dev_t *dev = param->open.dev; + if (dev) { + esp_hidh_dev_free_inner(dev); + } + } + break; + case ESP_HIDH_CLOSE_EVENT: + esp_hidh_dev_free_inner(param->close.dev); + break; + default: + break; + } +} +#endif /* CONFIG_BT_NIMBLE_ENABLED */ diff --git a/components/esp_hid/src/nimble_hidd.c b/components/esp_hid/src/nimble_hidd.c new file mode 100644 index 00000000000..53631d980e2 --- /dev/null +++ b/components/esp_hid/src/nimble_hidd.c @@ -0,0 +1,710 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "ble_hidd.h" +#include "esp_hidd_private.h" +#include "esp_log.h" + +#include +#include +#include +#include "nimble/nimble_opt.h" +#include "host/ble_hs.h" +#include "host/ble_gap.h" +#include "host/ble_hs_adv.h" +#include "host/ble_hs_hci.h" +#include "host/ble_att.h" +#include "services/gap/ble_svc_gap.h" +#include "services/gatt/ble_svc_gatt.h" +#include "services/bas/ble_svc_bas.h" +#include "services/hid/ble_svc_hid.h" +#include "services/dis/ble_svc_dis.h" +#include "services/sps/ble_svc_sps.h" + +#if CONFIG_BT_NIMBLE_HID_SERVICE + +static const char *TAG = "NIMBLE_HIDD"; +#define BLE_SVC_BAS_UUID16 0x180F + + +typedef struct esp_ble_hidd_dev_s esp_ble_hidd_dev_t; +// there can be only one BLE HID device +static esp_ble_hidd_dev_t *s_dev = NULL; + +typedef hidd_report_item_t hidd_le_report_item_t; + +typedef struct { + esp_hid_raw_report_map_t reports_map; + uint8_t reports_len; + hidd_le_report_item_t *reports; + uint16_t hid_svc; + uint16_t hid_control_handle; + uint16_t hid_protocol_handle; +} hidd_dev_map_t; + + + +struct esp_ble_hidd_dev_s { + esp_hidd_dev_t *dev; + esp_event_loop_handle_t event_loop_handle; + esp_hid_device_config_t config; + uint16_t appearance; + + bool connected; + uint16_t conn_id; + + uint8_t control; // 0x00 suspend, 0x01 suspend off + uint8_t protocol; // 0x00 boot, 0x01 report + + uint16_t bat_svc_handle; + uint16_t info_svc_handle; + struct ble_gatt_svc hid_incl_svc; + + uint16_t bat_level_handle; + uint8_t pnp[7]; /* something related to device info service */ + hidd_dev_map_t *devices; + uint8_t devices_len; +}; + +// HID Information characteristic value +static const uint8_t hidInfo[4] = { + 0x11, 0x01, // bcdHID (USB HID version) + 0x00, // bCountryCode + ESP_HID_FLAGS_REMOTE_WAKE | ESP_HID_FLAGS_NORMALLY_CONNECTABLE // Flags +}; + +static int create_hid_db(int device_index) +{ + int rc = 0; + struct ble_svc_hid_params hparams = {0}; + int report_mode_rpts = 0; + + /* fill hid info */ + memcpy(&hparams.hid_info, hidInfo, sizeof hparams.hid_info); + + /* fill report map */ + memcpy(&hparams.report_map, (uint8_t *)s_dev->devices[device_index].reports_map.data, s_dev->devices[device_index].reports_map.len); + hparams.report_map_len = s_dev->devices[device_index].reports_map.len; + hparams.external_rpt_ref = BLE_SVC_BAS_UUID16; + + /* fill protocol mode */ + hparams.proto_mode_present = 1; + hparams.proto_mode = s_dev->protocol; + + for (uint8_t i = 0; i < s_dev->devices[device_index].reports_len; i++) { + hidd_le_report_item_t *report = &s_dev->devices[device_index].reports[i]; + if (report->protocol_mode == ESP_HID_PROTOCOL_MODE_REPORT) { + /* only consider report mode reports, all boot mode reports will be registered by default */ + if (report->report_type == ESP_HID_REPORT_TYPE_INPUT) { + /* Input Report */ + hparams.rpts[report_mode_rpts].type = ESP_HID_REPORT_TYPE_INPUT; + } else if (report->report_type == ESP_HID_REPORT_TYPE_OUTPUT) { + /* Output Report */ + hparams.rpts[report_mode_rpts].type = ESP_HID_REPORT_TYPE_OUTPUT; + } else { + /* Feature Report */ + hparams.rpts[report_mode_rpts].type = ESP_HID_REPORT_TYPE_FEATURE; + } + hparams.rpts[report_mode_rpts].id = report->report_id; + report_mode_rpts++; + } else { + if (report->report_type == ESP_HID_REPORT_TYPE_INPUT) { + /* Boot mode reports */ + if (report->usage == ESP_HID_USAGE_KEYBOARD) { //Boot Keyboard Input + hparams.kbd_inp_present = 1; + } else { //Boot Mouse Input + hparams.mouse_inp_present = 1; + } + } else { //Boot Keyboard Output + hparams.kbd_out_present = 1; + } + } + } + hparams.rpts_len = report_mode_rpts; + /* Add service */ + rc = ble_svc_hid_add(hparams); + if(rc != 0) { + return rc; + } + return rc; +} + + +static int ble_hid_create_info_db() { + int rc; + + rc = 0; + ble_svc_dis_init(); + uint8_t pnp_val[7] = { + 0x02, //0x1=BT, 0x2=USB + s_dev->config.vendor_id & 0xFF, (s_dev->config.vendor_id >> 8) & 0xFF, //VID + s_dev->config.product_id & 0xFF, (s_dev->config.product_id >> 8) & 0xFF, //PID + s_dev->config.version & 0xFF, (s_dev->config.version >> 8) & 0xFF //VERSION + }; + memcpy(s_dev->pnp, pnp_val, 7); + ble_svc_dis_pnp_id_set((char *)s_dev->pnp); + if (s_dev->config.manufacturer_name && s_dev->config.manufacturer_name[0]) { + rc = ble_svc_dis_manufacturer_name_set(s_dev->config.manufacturer_name); + } + if (s_dev->config.serial_number && s_dev->config.serial_number[0]) { + rc = ble_svc_dis_serial_number_set(s_dev->config.serial_number); + } + return rc; +} + +static int nimble_hid_start_gatts(void) +{ + int rc = ESP_OK; + + ble_svc_gap_init(); + ble_svc_gatt_init(); + ble_svc_sps_init(0, 0); // initialize with 0 + ble_svc_bas_init(); + ble_hid_create_info_db(); + + for (uint8_t d = 0; d < s_dev->devices_len; d++) { + rc = create_hid_db(d); + if(rc != 0) { + return rc; + } + } + /* init the hid svc */ + ble_svc_hid_init(); + + return rc; +} + +static int nimble_hid_stop_gatts(esp_ble_hidd_dev_t *dev) +{ + int rc = ESP_OK; + + /* stop gatt database */ + ble_gatts_stop(); + return rc; +} + +/* Identify the reports using the report map */ +static int ble_hid_init_config(esp_ble_hidd_dev_t *dev, const esp_hid_device_config_t *config) +{ + memset((uint8_t *)(&dev->config), 0, sizeof(esp_hid_device_config_t)); + dev->config.vendor_id = config->vendor_id; + dev->config.product_id = config->product_id; + dev->config.version = config->version; + if (config->device_name != NULL) { + dev->config.device_name = strdup(config->device_name); + } + if (config->manufacturer_name != NULL) { + dev->config.manufacturer_name = strdup(config->manufacturer_name); + } + if (config->serial_number != NULL) { + dev->config.serial_number = strdup(config->serial_number); + } + dev->appearance = ESP_HID_APPEARANCE_GENERIC; + + if (config->report_maps_len) { + dev->devices = (hidd_dev_map_t *)malloc(config->report_maps_len * sizeof(hidd_dev_map_t)); + if (dev->devices == NULL) { + ESP_LOGE(TAG, "devices malloc(%d) failed", config->report_maps_len); + return ESP_FAIL; + } + memset(dev->devices, 0, config->report_maps_len * sizeof(hidd_dev_map_t)); + dev->devices_len = config->report_maps_len; + for (uint8_t d = 0; d < dev->devices_len; d++) { + + //raw report map + uint8_t *map = (uint8_t *)malloc(config->report_maps[d].len); + if (map == NULL) { + ESP_LOGE(TAG, "report map malloc(%d) failed", config->report_maps[d].len); + return ESP_FAIL; + } + memcpy(map, config->report_maps[d].data, config->report_maps[d].len); + + dev->devices[d].reports_map.data = (const uint8_t *)map; + dev->devices[d].reports_map.len = config->report_maps[d].len; + + esp_hid_report_map_t *rmap = esp_hid_parse_report_map(config->report_maps[d].data, config->report_maps[d].len); + if (rmap == NULL) { + ESP_LOGE(TAG, "hid_parse_report_map[%d](%d) failed", d, config->report_maps[d].len); + return ESP_FAIL; + } + dev->appearance = rmap->appearance; + dev->devices[d].reports_len = rmap->reports_len; + dev->devices[d].reports = (hidd_le_report_item_t *)malloc(rmap->reports_len * sizeof(hidd_le_report_item_t)); + if (dev->devices[d].reports == NULL) { + ESP_LOGE(TAG, "reports malloc(%d) failed", rmap->reports_len * sizeof(hidd_le_report_item_t)); + free(rmap); + return ESP_FAIL; + } + for (uint8_t r = 0; r < rmap->reports_len; r++) { + dev->devices[d].reports[r].map_index = d; + dev->devices[d].reports[r].report_id = rmap->reports[r].report_id; + dev->devices[d].reports[r].protocol_mode = rmap->reports[r].protocol_mode; + dev->devices[d].reports[r].report_type = rmap->reports[r].report_type; + dev->devices[d].reports[r].usage = rmap->reports[r].usage; + dev->devices[d].reports[r].value_len = rmap->reports[r].value_len; + } + free(rmap->reports); + free(rmap); + } + } + return ESP_OK; +} + +static int ble_hid_free_config(esp_ble_hidd_dev_t *dev) +{ + for (uint8_t d = 0; d < dev->devices_len; d++) { + free((void *)dev->devices[d].reports); + free((void *)dev->devices[d].reports_map.data); + } + + free((void *)dev->devices); + free((void *)dev->config.device_name); + free((void *)dev->config.manufacturer_name); + free((void *)dev->config.serial_number); + if (dev->event_loop_handle != NULL) { + esp_event_loop_delete(dev->event_loop_handle); + } + return ESP_OK; +} + +static int nimble_hidd_dev_deinit(void *devp) { + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + if (!s_dev) { + ESP_LOGE(TAG, "HID device profile already uninitialized"); + return ESP_OK; + } + + if (s_dev != dev) { + ESP_LOGE(TAG, "Wrong HID device provided"); + return ESP_FAIL; + } + s_dev = NULL; + + nimble_hid_stop_gatts(dev); + esp_event_post_to(dev->event_loop_handle, ESP_HIDD_EVENTS, ESP_HIDD_STOP_EVENT, NULL, 0, portMAX_DELAY); + ble_hid_free_config(dev); + free(dev); + return ESP_OK; +} + +static bool nimble_hidd_dev_connected(void *devp) +{ + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + return (dev != NULL && s_dev == dev && dev->connected); +} + +static int nimble_hidd_dev_battery_set(void *devp, uint8_t level) +{ + int rc; + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + if (!dev || s_dev != dev) { + return ESP_FAIL; + } + + if (!dev->connected) { + /* Return success if not yet connected */ + return ESP_OK; + } + + rc = ble_svc_bas_battery_level_set(level); + if (rc) { + ESP_LOGE(TAG, "esp_ble_gatts_send_notify failed: %d", rc); + return ESP_FAIL; + } + + return ESP_OK; +} + +/* if mode is NULL, find the first matching report */ +static hidd_le_report_item_t* find_report(uint8_t id, uint8_t type, uint8_t *mode) { + hidd_le_report_item_t *rpt; + for (uint8_t d = 0; d < s_dev->devices_len; d++) { + for (uint8_t i = 0; i < s_dev->devices[d].reports_len; i++) { + rpt = &s_dev->devices[d].reports[i]; + if(rpt->report_id == id && rpt->report_type == type && (!mode || (mode && *mode == rpt->protocol_mode))) { + return rpt; + } + } + } + return NULL; +} +static hidd_le_report_item_t* find_report_by_usage_and_type(uint8_t usage, uint8_t type, uint8_t *mode) { + hidd_le_report_item_t *rpt; + for (uint8_t d = 0; d < s_dev->devices_len; d++) { + for (uint8_t i = 0; i < s_dev->devices[d].reports_len; i++) { + rpt = &s_dev->devices[d].reports[i]; + if(rpt->usage == usage && rpt->report_type == type && (!mode || (mode && *mode == rpt->protocol_mode))) { + return rpt; + } + } + } + return NULL; +} + +static int nimble_hidd_dev_input_set(void *devp, size_t index, size_t id, uint8_t *data, size_t length) +{ + hidd_le_report_item_t *p_rpt; + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + int rc; + struct os_mbuf *om; + if (!dev || s_dev != dev) { + return ESP_FAIL; + } + + if (!dev->connected) { + ESP_LOGE(TAG, "%s Device Not Connected", __func__); + return ESP_FAIL; + } + + /* check the protocol mode */ + /* as the protocol mode is always present, its safe to read the characteristic */ + rc = ble_att_svr_read_local(s_dev->devices[index].hid_protocol_handle, &om); + if(rc != 0) { + ESP_LOGE(TAG, "Unable to fetch protocol_mode\n"); + return ESP_FAIL; + } + rc = ble_hs_mbuf_to_flat(om, &dev->protocol, sizeof(dev->protocol), NULL); + if(rc != 0) { + return ESP_FAIL; + } + /* free the mbuf */ + os_mbuf_free_chain(om); + om = NULL; + + p_rpt = find_report(id, ESP_HID_REPORT_TYPE_INPUT, &dev->protocol); + assert(p_rpt != NULL); + om = ble_hs_mbuf_from_flat((void*)data, length); + assert(om != NULL); + /* NOTE : om is freed by stack */ + rc = ble_att_svr_write_local(p_rpt->handle, om); + if (rc != 0) { + ESP_LOGE(TAG, "Write Input Report Failed: %d", rc); + return ESP_FAIL; + } + return ESP_OK; +} + +static int nimble_hidd_dev_feature_set(void *devp, size_t index, size_t id, uint8_t *data, size_t length) +{ + /* This function is a no-op for now */ + hidd_le_report_item_t *p_rpt; + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + int rc; + struct os_mbuf *om; + if (!dev || s_dev != dev) { + return ESP_FAIL; + } + + if (!dev->connected) { + ESP_LOGE(TAG, "%s Device Not Connected", __func__); + return ESP_FAIL; + } + + /* check the protocol mode */ + /* as the protocol mode is always present, its safe to read the characteristic */ + rc = ble_att_svr_read_local(s_dev->devices[index].hid_protocol_handle, &om); + if(rc != 0) { + ESP_LOGE(TAG, "Unable to fetch protocol_mode\n"); + return ESP_FAIL; + } + rc = ble_hs_mbuf_to_flat(om, &dev->protocol, sizeof(dev->protocol), NULL); + if(rc != 0) { + return ESP_FAIL; + } + /* free the mbuf */ + os_mbuf_free_chain(om); + om = NULL; + + p_rpt = find_report(id, ESP_HID_REPORT_TYPE_FEATURE, &dev->protocol); + assert(p_rpt != NULL); + om = ble_hs_mbuf_from_flat((void*)data, length); + assert(om != NULL); + /* NOTE : om is freed by stack*/ + rc = ble_att_svr_write_local(p_rpt->handle, om); + if (rc != 0) { + ESP_LOGE(TAG, "Set Feature Report Failed: %d", rc); + return ESP_FAIL; + } + return ESP_OK; +} + +static int nimble_hidd_dev_event_handler_register(void *devp, esp_event_handler_t callback, esp_hidd_event_t event) +{ + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + if (!dev || s_dev != dev) { + return ESP_FAIL; + } + return esp_event_handler_register_with(dev->event_loop_handle, ESP_HIDD_EVENTS, event, callback, dev->dev); +} + +static int esp_ble_hidd_dev_event_handler_unregister(void *devp, esp_event_handler_t callback, esp_hidd_event_t event) +{ + esp_ble_hidd_dev_t *dev = (esp_ble_hidd_dev_t *)devp; + if (!dev || s_dev != dev) { + return ESP_FAIL; + } + return esp_event_handler_unregister_with(dev->event_loop_handle, ESP_HIDD_EVENTS, event, callback); +} + +static void ble_hidd_dev_free(void) +{ + if (s_dev) { + ble_hid_free_config(s_dev); + free(s_dev); + s_dev = NULL; + } +} + +static int nimble_hid_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + struct os_mbuf *om; + uint8_t data; + int rc; + + switch (event->type) { + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + ESP_LOGD(TAG, "connection %s; status=%d", + event->connect.status == 0 ? "established" : "failed", + event->connect.status); + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + assert(rc == 0); + + /* save connection handle */ + s_dev->connected = true; + s_dev->conn_id = event->connect.conn_handle; + esp_hidd_event_data_t cb_param = { + .connect.dev = s_dev->dev, + .connect.status = event->connect.status + }; + + /* reset the protocol mode value */ + data = ESP_HID_PROTOCOL_MODE_REPORT; + om = ble_hs_mbuf_from_flat(&data, 1); + if(om == NULL) { + ESP_LOGD(TAG, "No memory to allocate mbuf"); + } + /* NOTE : om is freed by stack */ + for(int i = 0; i < s_dev->devices_len; i++) { + rc = ble_att_svr_write_local(s_dev->devices[i].hid_protocol_handle, om); + if (rc != 0) { + ESP_LOGE(TAG, "Write on Protocol Mode Failed: %d", rc); + } + } + + esp_event_post_to(s_dev->event_loop_handle, ESP_HIDD_EVENTS, ESP_HIDD_CONNECT_EVENT, + &cb_param, sizeof(esp_hidd_event_data_t), portMAX_DELAY); + return 0; + break; + case BLE_GAP_EVENT_DISCONNECT: + ESP_LOGD(TAG, "disconnect; reason=%d", event->disconnect.reason); + + if (s_dev->connected) { + s_dev->connected = false; + esp_hidd_event_data_t cb_param = {0}; + cb_param.disconnect.dev = s_dev->dev; + cb_param.disconnect.reason = event->disconnect.reason; + esp_event_post_to(s_dev->event_loop_handle, ESP_HIDD_EVENTS, ESP_HIDD_DISCONNECT_EVENT, + &cb_param, sizeof(esp_hidd_event_data_t), portMAX_DELAY); + } + return 0; + } + return 0; +} + +/** service index is used to identify the hid service instance + of the registered characteristic. + Assuming the first instance of the hid service is registered first. + Increment service index as the hid services get registered */ +static int service_index = -1; +static void nimble_gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg) +{ + char buf[BLE_UUID_STR_LEN]; + hidd_le_report_item_t *rpt = NULL; + struct os_mbuf *om; + uint16_t uuid16; + uint16_t report_info; + uint8_t report_type, report_id; + uint16_t report_handle; + uint8_t protocol_mode; + int rc; + switch (ctxt->op) { + case BLE_GATT_REGISTER_OP_SVC: + ESP_LOGD(TAG, "registered service %s with handle=%d", + ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf), + ctxt->svc.handle); + uuid16 = ble_uuid_u16(ctxt->svc.svc_def->uuid); + if(uuid16 == BLE_SVC_HID_UUID16) { + ++service_index; + s_dev->devices[service_index].hid_svc = ctxt->svc.handle; + } + + break; + + case BLE_GATT_REGISTER_OP_CHR: + ESP_LOGD(TAG, "registering characteristic %s with " + "def_handle=%d val_handle=%d\n", + ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf), + ctxt->chr.def_handle, + ctxt->chr.val_handle); + uuid16 = ble_uuid_u16(ctxt->chr.chr_def->uuid); + if(uuid16 == BLE_SVC_HID_CHR_UUID16_HID_CTRL_PT) { + /* assuming this characteristic is from the last registered hid service */ + s_dev->devices[service_index].hid_control_handle = ctxt->chr.val_handle; + } + if(uuid16 == BLE_SVC_HID_CHR_UUID16_PROTOCOL_MODE) { + /* assuming this characteristic is from the last registered hid service */ + s_dev->devices[service_index].hid_protocol_handle = ctxt->chr.val_handle; + } + if(uuid16 == BLE_SVC_HID_CHR_UUID16_BOOT_KBD_INP) { + protocol_mode = ESP_HID_PROTOCOL_MODE_BOOT; + rpt = find_report_by_usage_and_type(ESP_HID_USAGE_KEYBOARD, ESP_HID_REPORT_TYPE_INPUT, &protocol_mode); + if(rpt == NULL) { + ESP_LOGE(TAG, "Unknown boot kbd input report registration"); + return; + } + rpt->handle = ctxt->chr.val_handle; + } + if(uuid16 == BLE_SVC_HID_CHR_UUID16_BOOT_KBD_OUT) { + protocol_mode = ESP_HID_PROTOCOL_MODE_BOOT; + rpt = find_report_by_usage_and_type(ESP_HID_USAGE_KEYBOARD, ESP_HID_REPORT_TYPE_OUTPUT, &protocol_mode); + if(rpt == NULL) { + ESP_LOGE(TAG, "Unknown boot kbd output report registration"); + return; + } + rpt->handle = ctxt->chr.val_handle; + } + if(uuid16 == BLE_SVC_HID_CHR_UUID16_BOOT_MOUSE_INP) { + protocol_mode = ESP_HID_PROTOCOL_MODE_BOOT; + rpt = find_report_by_usage_and_type(ESP_HID_USAGE_MOUSE, ESP_HID_REPORT_TYPE_INPUT, &protocol_mode); + if(rpt == NULL) { + ESP_LOGE(TAG, "Unknown boot mouse input report registration"); + return; + } + rpt->handle = ctxt->chr.val_handle; + } + break; + + case BLE_GATT_REGISTER_OP_DSC: + ESP_LOGD(TAG, "registering descriptor %s with handle=%d", + ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf), + ctxt->dsc.handle); + uuid16 = ble_uuid_u16(ctxt->dsc.dsc_def->uuid); + if(uuid16 == BLE_SVC_HID_DSC_UUID16_RPT_REF) { + rc = ble_att_svr_read_local(ctxt->dsc.handle, &om); + assert(rc == 0); + + ble_hs_mbuf_to_flat(om, &report_info, sizeof report_info, NULL); + report_type = (uint8_t)((report_info & 0xFF00) >> 8); + report_id = report_info & 0x00FF; + report_handle = (*(uint16_t*)(ctxt->dsc.dsc_def->arg)); + protocol_mode = ESP_HID_PROTOCOL_MODE_REPORT; + rpt = find_report(report_id, report_type, &protocol_mode); + assert(rpt != NULL); + rpt->handle = report_handle; + /* free the mbuf */ + os_mbuf_free_chain(om); + om = NULL; + } + break; + + default: + assert(0); + break; + } +} + +static void nimble_host_synced(void) { + esp_event_post_to(s_dev->event_loop_handle, ESP_HIDD_EVENTS, ESP_HIDD_START_EVENT, NULL, 0, portMAX_DELAY); +} + +void nimble_host_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +static struct ble_gap_event_listener nimble_gap_event_listener; +esp_err_t esp_ble_hidd_dev_init(esp_hidd_dev_t *dev_p, const esp_hid_device_config_t *config, esp_event_handler_t callback) +{ + int rc; + + if (s_dev) { + ESP_LOGE(TAG, "HID device profile already initialized"); + return ESP_FAIL; + } + + s_dev = (esp_ble_hidd_dev_t *)calloc(1, sizeof(esp_ble_hidd_dev_t)); + if (s_dev == NULL) { + ESP_LOGE(TAG, "HID device could not be allocated"); + return ESP_FAIL; + } + + // Reset the hid device target environment + s_dev->control = ESP_HID_CONTROL_EXIT_SUSPEND; + s_dev->protocol = ESP_HID_PROTOCOL_MODE_REPORT; + s_dev->event_loop_handle = NULL; + s_dev->dev = dev_p; + + esp_event_loop_args_t event_task_args = { + .queue_size = 5, + .task_name = "ble_hidd_events", + .task_priority = uxTaskPriorityGet(NULL), + .task_stack_size = 2048, + .task_core_id = tskNO_AFFINITY + }; + rc = esp_event_loop_create(&event_task_args, &s_dev->event_loop_handle); + if (rc != ESP_OK) { + ESP_LOGE(TAG, "HID device event loop could not be created"); + ble_hidd_dev_free(); + return rc; + } + + rc = ble_hid_init_config(s_dev, config); + if (rc != ESP_OK) { + ble_hidd_dev_free(); + return rc; + } + + dev_p->dev = s_dev; + dev_p->connected = nimble_hidd_dev_connected; + dev_p->deinit = nimble_hidd_dev_deinit; + dev_p->battery_set = nimble_hidd_dev_battery_set; + dev_p->input_set = nimble_hidd_dev_input_set; + dev_p->feature_set = nimble_hidd_dev_feature_set; + dev_p->event_handler_register = nimble_hidd_dev_event_handler_register; + dev_p->event_handler_unregister = esp_ble_hidd_dev_event_handler_unregister; + + rc = nimble_hidd_dev_event_handler_register(s_dev, esp_hidd_process_event_data_handler, ESP_EVENT_ANY_ID); + if (rc != ESP_OK) { + ble_hidd_dev_free(); + return rc; + } + + if (callback != NULL) { + rc = nimble_hidd_dev_event_handler_register(s_dev, callback, ESP_EVENT_ANY_ID); + if (rc != ESP_OK) { + ble_hidd_dev_free(); + return rc; + } + } + + ble_hs_cfg.reset_cb = nimble_host_reset; + ble_hs_cfg.sync_cb = nimble_host_synced; + ble_hs_cfg.gatts_register_cb = nimble_gatt_svr_register_cb; + rc = nimble_hid_start_gatts(); + if(rc != ESP_OK) { + return rc; + } + ble_gap_event_listener_register(&nimble_gap_event_listener, + nimble_hid_gap_event, NULL); + + return rc; +} +#endif // CONFIG_BT_NIMBLE_HID_SERVICE diff --git a/components/esp_hid/src/nimble_hidh.c b/components/esp_hid/src/nimble_hidh.c new file mode 100644 index 00000000000..d1881159b52 --- /dev/null +++ b/components/esp_hid/src/nimble_hidh.c @@ -0,0 +1,1020 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "ble_hidh.h" +#include "esp_hidh_private.h" +#include "esp_err.h" +#include "esp_log.h" + +#include "esp_hid_common.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" + +#include +#include +#include +#include "nimble/nimble_opt.h" +#include "host/ble_hs.h" +#include "host/ble_gap.h" +#include "host/ble_hs_adv.h" +#include "host/ble_hs_hci.h" +#include "host/ble_att.h" +#include "services/gap/ble_svc_gap.h" +#include "services/gatt/ble_svc_gatt.h" +#include "services/bas/ble_svc_bas.h" +#include "services/hid/ble_svc_hid.h" +#include "services/dis/ble_svc_dis.h" + +#if CONFIG_BT_NIMBLE_HID_SERVICE + +#define ESP_BD_ADDR_STR "%02x:%02x:%02x:%02x:%02x:%02x" +#define ESP_BD_ADDR_HEX(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5] + +static const char *TAG = "NIMBLE_HIDH"; +static SemaphoreHandle_t s_ble_hidh_cb_semaphore = NULL; + +/* variables used for attribute discovery */ +static int services_discovered; +static int chrs_discovered; +static int dscs_discovered; +static int status = 0; + +static inline void WAIT_CB(void) +{ + xSemaphoreTake(s_ble_hidh_cb_semaphore, portMAX_DELAY); +} + +static inline void SEND_CB(void) +{ + xSemaphoreGive(s_ble_hidh_cb_semaphore); +} + +static esp_event_loop_handle_t event_loop_handle; +static uint8_t *s_read_data_val = NULL; +static uint16_t s_read_data_len = 0; +static int s_read_status = 0; +static esp_event_handler_t s_event_callback; + +/** + * Utility function to log an array of bytes. + */ +void +print_bytes(const uint8_t *bytes, int len) +{ + int i; + + for (i = 0; i < len; i++) { + MODLOG_DFLT(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]); + } +} + +static void +print_mbuf(const struct os_mbuf *om) +{ + int colon; + + colon = 0; + while (om != NULL) { + if (colon) { + MODLOG_DFLT(DEBUG, ":"); + } else { + colon = 1; + } + print_bytes(om->om_data, om->om_len); + om = SLIST_NEXT(om, om_next); + } +} + +static int +nimble_on_read(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + int old_offset; + MODLOG_DFLT(INFO, "Read complete; status=%d conn_handle=%d", error->status, + conn_handle); + s_read_status = error->status; + switch(s_read_status) { + case 0: + MODLOG_DFLT(DEBUG, " attr_handle=%d value=", attr->handle); + old_offset = s_read_data_len; + s_read_data_len += OS_MBUF_PKTLEN(attr->om); + s_read_data_val = realloc(s_read_data_val, s_read_data_len + 1); // 1 extra byte to store null char + ble_hs_mbuf_to_flat(attr->om, s_read_data_val + old_offset, OS_MBUF_PKTLEN(attr->om), NULL); + print_mbuf(attr->om); + return 0; + case BLE_HS_EDONE: + s_read_data_val[s_read_data_len] = 0; // to insure strings are ended with \0 */ + s_read_status = 0; + SEND_CB(); + return 0; + } + return 0; +} + +static int read_char(uint16_t conn_handle, uint16_t handle, uint8_t **out, uint16_t *out_len) +{ + s_read_data_val = NULL; + s_read_data_len = 0; + int rc; + + /* read long because the server may not support the large enough mtu */ + rc = ble_gattc_read_long(conn_handle, handle, 0, nimble_on_read, NULL); + if (rc != 0) { + ESP_LOGE(TAG, "read_char failed"); + return rc; + } + WAIT_CB(); + if (s_read_status == 0) { + *out = s_read_data_val; + *out_len = s_read_data_len; + } + return s_read_status; +} + +static int read_descr(uint16_t conn_handle, uint16_t handle, uint8_t **out, uint16_t *out_len) +{ + int rc; + + s_read_data_val = NULL; + s_read_data_len = 0; + + rc = ble_gattc_read_long(conn_handle, handle, 0, nimble_on_read, NULL); + if (rc != 0) { + ESP_LOGE(TAG, "read_descr failed"); + return rc; + } + WAIT_CB(); + if (s_read_status == 0) { + *out = s_read_data_val; + *out_len = s_read_data_len; + } + return s_read_status; +} + +static int +svc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, + const struct ble_gatt_svc *service, void *arg) +{ + int rc; + struct ble_gatt_svc *service_result; + uint16_t uuid16; + esp_hidh_dev_t *dev; + + service_result = arg; + rc = 0; + status = error->status; + switch (error->status) { + case 0: + memcpy(service_result + services_discovered, service, sizeof(struct ble_gatt_svc)); + services_discovered++; + uuid16 = ble_uuid_u16(&service->uuid.u); + dev = esp_hidh_dev_get_by_conn_id(conn_handle); + if (!dev) { + ESP_LOGE(TAG, "Service discovery received for unknown device"); + break; + } + if (uuid16 == BLE_SVC_HID_UUID16) { + dev->status = 0; + dev->config.report_maps_len++; + ESP_LOGD(TAG, "HID Service is Discovered"); + } + break; + + case BLE_HS_EDONE: + rc = 0; + status = 0; + /* release the sem now */ + SEND_CB(); + break; + + default: + rc = error->status; + break; + } + + if (rc != 0) { + /* Error; abort discovery. */ + SEND_CB(); + ESP_LOGE(TAG, "Error in service discovery %d\n", rc); + } + + return rc; +} + +static int +chr_disced(uint16_t conn_handle, const struct ble_gatt_error *error, + const struct ble_gatt_chr *chr, void *arg) +{ + struct ble_gatt_chr *chrs; + int rc; + rc = 0; + chrs = arg; + + status = error->status; + switch (error->status) { + case 0: + ESP_LOGD(TAG,"Char discovered : def handle : %04x, val_handle : %04x, properties : %02x\n, uuid : %04x", + chr->def_handle, chr->val_handle,chr->properties, ble_uuid_u16(&chr->uuid.u)); + memcpy(chrs + chrs_discovered, chr, sizeof(struct ble_gatt_chr)); + chrs_discovered++; + break; + + case BLE_HS_EDONE: + status = 0; + /* release when discovery is complete */ + SEND_CB(); + rc = 0; + break; + + default: + rc = error->status; + break; + } + + if (rc != 0) { + /* Error; abort discovery. */ + SEND_CB(); + } + + return rc; +} + +static int +desc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, + uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, + void *arg) +{ + int rc; + struct ble_gatt_dsc *dscr; + dscr = arg; + + rc = 0; + status = error->status; + switch (error->status) { + case 0: + ESP_LOGD(TAG,"DISC discovered : handle : %04x, uuid : %04x", + dsc->handle, ble_uuid_u16(&dsc->uuid.u)); + memcpy(dscr + dscs_discovered, dsc, sizeof(struct ble_gatt_dsc)); + dscs_discovered++; + break; + + case BLE_HS_EDONE: + /* All descriptors in this characteristic discovered */ + rc = 0; + status = 0; + /* release the sem as the discovery is complete */ + SEND_CB(); + break; + + default: + /* Error; abort discovery. */ + rc = error->status; + break; + } + + if (rc != 0) { + /* Error; abort discovery. */ + SEND_CB(); + } + + return rc; +} + +/* this api does the following things : +** does service, characteristic and discriptor discovery and +** fills the hid device information accordingly in dev */ +static void read_device_services(esp_hidh_dev_t *dev) +{ + uint16_t suuid, cuuid, duuid; + uint16_t chandle, dhandle; + esp_hidh_dev_report_t *report = NULL; + uint8_t *rdata = 0; + uint16_t rlen = 0; + esp_hid_report_item_t *r; + esp_hid_report_map_t *map; + + struct ble_gatt_svc service_result[10]; + uint16_t dcount = 10; + uint8_t hidindex = 0; + int rc; + + rc = ble_gattc_disc_all_svcs(dev->ble.conn_id, svc_disced, service_result); + if(rc != 0) { + ESP_LOGD(TAG, "Error discovering services : %d", rc); + assert(rc != 0); + } + WAIT_CB(); + if(status != 0) { + ESP_LOGE(TAG, "failed to find services"); + assert(status == 0); + } + dcount = services_discovered; /* fatal if services are more than 10 */ + + if (rc == ESP_OK) { + ESP_LOGD(TAG, "Found %u HID Services", dev->config.report_maps_len); + dev->config.report_maps = (esp_hid_raw_report_map_t *)malloc(dev->config.report_maps_len * sizeof(esp_hid_raw_report_map_t)); + if (dev->config.report_maps == NULL) { + ESP_LOGE(TAG, "malloc report maps failed"); + return; + } + dev->protocol_mode = (uint8_t *)malloc(dev->config.report_maps_len * sizeof(uint8_t)); + if (dev->protocol_mode == NULL) { + ESP_LOGE(TAG, "malloc protocol_mode failed"); + return; + } + + /* read characteristic value may fail, so we should init report maps */ + memset(dev->config.report_maps, 0, dev->config.report_maps_len * sizeof(esp_hid_raw_report_map_t)); + + for (uint16_t s = 0; s < dcount; s++) { + suuid = ble_uuid_u16(&service_result[s].uuid.u); + ESP_LOGD(TAG, "Service discovered : start_handle : %d, end handle : %d, uuid: 0x%04x", + service_result[s].start_handle, service_result[s].end_handle, suuid); + + if (suuid != BLE_SVC_BAS_UUID16 + && suuid != BLE_SVC_DIS_UUID16 + && suuid != BLE_SVC_HID_UUID16 + && suuid != 0x1800) {//device name? + continue; + } + + struct ble_gatt_chr char_result[20]; + uint16_t ccount = 20; + rc = ble_gattc_disc_all_chrs(dev->ble.conn_id, service_result[s].start_handle, + service_result[s].end_handle, chr_disced, char_result); + WAIT_CB(); + if(status != 0) { + ESP_LOGE(TAG, "failed to find chars for service : %d",s); + assert(status == 0); + } + ccount = chrs_discovered; + if (rc == ESP_OK) { + for (uint16_t c = 0; c < ccount; c++) { + cuuid = ble_uuid_u16(&char_result[c].uuid.u); + chandle = char_result[c].val_handle; + ESP_LOGD(TAG, " CHAR:(%d), handle: %d, perm: 0x%02x, uuid: 0x%04x", + c + 1, chandle, char_result[c].properties, cuuid); + + if (suuid == BLE_SVC_GAP_UUID16) { + if (dev->config.device_name == NULL && cuuid == BLE_SVC_GAP_CHR_UUID16_DEVICE_NAME + && (char_result[c].properties & BLE_GATT_CHR_PROP_READ) != 0) { + if (read_char(dev->ble.conn_id, chandle,&rdata, &rlen) == 0 && rlen) { + dev->config.device_name = (const char *)rdata; + } + } else { + continue; + } + } else if (suuid == BLE_SVC_BAS_UUID16) { + if (cuuid == BLE_SVC_BAS_CHR_UUID16_BATTERY_LEVEL && + (char_result[c].properties & BLE_GATT_CHR_PROP_READ) != 0) { + dev->ble.battery_handle = chandle; + } else { + continue; + } + } else if (suuid == BLE_SVC_DIS_UUID16) { + if (char_result[c].properties & BLE_GATT_CHR_PROP_READ) { + if (cuuid == BLE_SVC_DIS_CHR_UUID16_PNP_ID) { + if (read_char(dev->ble.conn_id, chandle, &rdata, &rlen) == 0 && rlen == 7) { + dev->config.vendor_id = *((uint16_t *)&rdata[1]); + dev->config.product_id = *((uint16_t *)&rdata[3]); + dev->config.version = *((uint16_t *)&rdata[5]); + } + free(rdata); + } else if (cuuid == BLE_SVC_DIS_CHR_UUID16_MANUFACTURER_NAME) { + if (read_char(dev->ble.conn_id, chandle, &rdata, &rlen) == 0 && rlen) { + dev->config.manufacturer_name = (const char *)rdata; + } + } else if (cuuid == BLE_SVC_DIS_CHR_UUID16_SERIAL_NUMBER) { + if (read_char(dev->ble.conn_id, chandle, &rdata, &rlen) == 0 && rlen) { + dev->config.serial_number = (const char *)rdata; + } + } + } + continue; + } else { + if(cuuid == BLE_SVC_HID_CHR_UUID16_PROTOCOL_MODE) { + if (char_result[c].properties & BLE_GATT_CHR_PROP_READ) { + if (read_char(dev->ble.conn_id, chandle, &rdata, &rlen) == 0 && rlen) { + dev->protocol_mode[hidindex] = *((uint8_t *)rdata); + } + } + continue; + } + if (cuuid == BLE_SVC_HID_CHR_UUID16_REPORT_MAP) { + if (char_result[c].properties & BLE_GATT_CHR_PROP_READ) { + if (read_char(dev->ble.conn_id, chandle, &rdata, &rlen) == 0 && rlen) { + dev->config.report_maps[hidindex].data = (const uint8_t *)rdata; + dev->config.report_maps[hidindex].len = rlen; + } + } + continue; + } else if (cuuid == BLE_SVC_HID_CHR_UUID16_BOOT_KBD_INP || cuuid == BLE_SVC_HID_CHR_UUID16_BOOT_KBD_OUT + || cuuid == BLE_SVC_HID_CHR_UUID16_BOOT_MOUSE_INP || cuuid == BLE_SVC_HID_CHR_UUID16_RPT) { + report = (esp_hidh_dev_report_t *)malloc(sizeof(esp_hidh_dev_report_t)); + if (report == NULL) { + ESP_LOGE(TAG, "malloc esp_hidh_dev_report_t failed"); + return; + } + report->next = NULL; + report->permissions = char_result[c].properties; + report->handle = chandle; + report->ccc_handle = 0; + report->report_id = 0; + report->map_index = hidindex; + if (cuuid == BLE_SVC_HID_CHR_UUID16_BOOT_KBD_INP) { + report->protocol_mode = ESP_HID_PROTOCOL_MODE_BOOT; + report->report_type = ESP_HID_REPORT_TYPE_INPUT; + report->usage = ESP_HID_USAGE_KEYBOARD; + report->value_len = 8; + } else if (cuuid == BLE_SVC_HID_CHR_UUID16_BOOT_KBD_OUT) { + report->protocol_mode = ESP_HID_PROTOCOL_MODE_BOOT; + report->report_type = ESP_HID_REPORT_TYPE_OUTPUT; + report->usage = ESP_HID_USAGE_KEYBOARD; + report->value_len = 8; + } else if (cuuid == BLE_SVC_HID_CHR_UUID16_BOOT_MOUSE_INP) { + report->protocol_mode = ESP_HID_PROTOCOL_MODE_BOOT; + report->report_type = ESP_HID_REPORT_TYPE_INPUT; + report->usage = ESP_HID_USAGE_MOUSE; + report->value_len = 8; + } else { + report->protocol_mode = ESP_HID_PROTOCOL_MODE_REPORT; + report->report_type = 0; + report->usage = ESP_HID_USAGE_GENERIC; + report->value_len = 0; + } + } else { + continue; + } + } + struct ble_gatt_dsc descr_result[20]; + uint16_t dcount = 20; + uint16_t chr_end_handle; + if(c + 1 < ccount) { + chr_end_handle = char_result[c + 1].def_handle; + } + else { + chr_end_handle = service_result[s].end_handle; + } + rc = ble_gattc_disc_all_dscs(dev->ble.conn_id, char_result[c].val_handle, + chr_end_handle, desc_disced, descr_result); + WAIT_CB(); + if(status != 0) { + ESP_LOGE(TAG, "failed to find discriptors for characteristic : %d",c); + assert(status == 0); + } + dcount = dscs_discovered; + if (rc == ESP_OK) { + for (uint16_t d = 0; d < dcount; d++) { + duuid = ble_uuid_u16(&descr_result[d].uuid.u); + dhandle = descr_result[d].handle; + ESP_LOGD(TAG, " DESCR:(%d), handle: %d, uuid: 0x%04x", d + 1, dhandle, duuid); + + if (suuid == BLE_SVC_BAS_UUID16) { + if (duuid == BLE_GATT_DSC_CLT_CFG_UUID16 && + (char_result[c].properties & BLE_GATT_CHR_PROP_NOTIFY) != 0) { + dev->ble.battery_ccc_handle = dhandle; + } + } else if (suuid == BLE_SVC_HID_UUID16 && report != NULL) { + if (duuid == BLE_GATT_DSC_CLT_CFG_UUID16 && (report->permissions & BLE_GATT_CHR_PROP_NOTIFY) != 0) { + report->ccc_handle = dhandle; + } else if (duuid == BLE_SVC_HID_DSC_UUID16_RPT_REF) { + if (read_descr(dev->ble.conn_id, dhandle, &rdata, &rlen) == 0 && rlen) { + report->report_id = rdata[0]; + report->report_type = rdata[1]; + free(rdata); + } + } + } + } + } + if (suuid == BLE_SVC_HID_UUID16 && report != NULL) { + report->next = dev->reports; + dev->reports = report; + dev->reports_len++; + } + dscs_discovered = 0; + } + if (suuid == BLE_SVC_HID_UUID16) { + hidindex++; + } + } + chrs_discovered = 0; // reset the chars array for the next service + } + + for (uint8_t d = 0; d < dev->config.report_maps_len; d++) { + if (dev->reports_len && dev->config.report_maps[d].len) { + map = esp_hid_parse_report_map(dev->config.report_maps[d].data, dev->config.report_maps[d].len); + if (map) { + if (dev->ble.appearance == 0) { + dev->ble.appearance = map->appearance; + } + report = dev->reports; + + while (report) { + if (report->map_index == d) { + for (uint8_t i = 0; i < map->reports_len; i++) { + r = &map->reports[i]; + if (report->protocol_mode == ESP_HID_PROTOCOL_MODE_BOOT + && report->protocol_mode == r->protocol_mode + && report->report_type == r->report_type + && report->usage == r->usage) { + report->report_id = r->report_id; + report->value_len = r->value_len; + } else if (report->protocol_mode == r->protocol_mode + && report->report_type == r->report_type + && report->report_id == r->report_id) { + report->usage = r->usage; + report->value_len = r->value_len; + } + } + } + report = report->next; + } + free(map->reports); + free(map); + map = NULL; + } + } + } + } +} + +static int +on_subscribe(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + uint16_t conn_id; + conn_id =*((uint16_t*) arg); + + assert(conn_id == conn_handle); + + MODLOG_DFLT(INFO, "Subscribe complete; status=%d conn_handle=%d " + "attr_handle=%d\n", + error->status, conn_handle, attr->handle); + SEND_CB(); + + return 0; +} + +static void register_for_notify(uint16_t conn_handle, uint16_t handle) +{ + uint8_t value[2]; + int rc; + value[0] = 1; + value[1] = 0; + rc = ble_gattc_write_flat(conn_handle, handle, value, sizeof value, on_subscribe,(void *)&conn_handle); + if (rc != 0) { + ESP_LOGE(TAG, "Error: Failed to subscribe to characteristic; " + "rc=%d\n", rc); + } + WAIT_CB(); +} + +static int +on_write(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + uint16_t conn_id; + conn_id =*((uint16_t*) arg); + + assert(conn_id == conn_handle); + + MODLOG_DFLT(DEBUG, "write complete; status=%d conn_handle=%d " + "attr_handle=%d\n", + error->status, conn_handle, attr->handle); + SEND_CB(); + + return 0; +} +static void write_char_descr(uint16_t conn_id, uint16_t handle, uint16_t value_len, uint8_t *value) +{ + ble_gattc_write_flat(conn_id, handle, value, value_len, on_write, &conn_id); + WAIT_CB(); +} + +static void attach_report_listeners(esp_hidh_dev_t *dev) +{ + if (dev == NULL) { + return; + } + uint16_t ccc_data = 1; + esp_hidh_dev_report_t *report = dev->reports; + + //subscribe to battery notifications + if (dev->ble.battery_handle) { + register_for_notify(dev->ble.conn_id, dev->ble.battery_handle); + if (dev->ble.battery_ccc_handle) { + //Write CCC descr to enable notifications + write_char_descr(dev->ble.conn_id, dev->ble.battery_ccc_handle, 2, (uint8_t *)&ccc_data); + } + } + + while (report) { + /* subscribe to notifications */ + if ((report->permissions & BLE_GATT_CHR_PROP_NOTIFY) != 0 && report->protocol_mode == ESP_HID_PROTOCOL_MODE_REPORT) { + register_for_notify(dev->ble.conn_id, report->handle); + if (report->ccc_handle) { + /* Write CCC descr to enable notifications */ + write_char_descr(dev->ble.conn_id, report->ccc_handle, 2, (uint8_t *)&ccc_data); + } + } + report = report->next; + } +} + +static int +esp_hidh_gattc_event_handler(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + int rc; + esp_hidh_dev_t *dev = NULL; + esp_hidh_dev_report_t *report = NULL; + + switch (event->type) { + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + if (event->connect.status == 0) { + /* Connection successfully established. */ + MODLOG_DFLT(INFO, "Connection established "); + + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + assert(rc == 0); + dev = esp_hidh_dev_get_by_bda(desc.peer_ota_addr.val); + if(!dev) { + ESP_LOGE(TAG, "Connect received for unknown device"); + } + dev->status = -1; // set to not found and clear if HID service is found + dev->ble.conn_id = event->connect.conn_handle; + + /* Try to set the mtu to the max value */ + rc = ble_att_set_preferred_mtu(BLE_ATT_MTU_MAX); + if(rc != 0) { + ESP_LOGE(TAG, "att preferred mtu set failed"); + } + rc = ble_gattc_exchange_mtu(event->connect.conn_handle, NULL, NULL); + if (rc != 0) { + ESP_LOGE(TAG, "Failed to negotiate MTU; rc = %d", rc); + } + SEND_CB(); + } else { + MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", + event->connect.status); + dev->status = event->connect.status; // ESP_GATT_CONN_FAIL_ESTABLISH; + dev->ble.conn_id = -1; + SEND_CB(); // return from connection + } + return 0; + + case BLE_GAP_EVENT_DISCONNECT: + /* Connection terminated. */ + MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason); + dev = esp_hidh_dev_get_by_conn_id(event->disconnect.conn.conn_handle); + if (!dev) { + ESP_LOGE(TAG, "CLOSE received for unknown device"); + break; + } + if (!dev->connected) { + dev->status = event->disconnect.reason; + dev->ble.conn_id = -1; + } else { + dev->connected = false; + dev->status = event->disconnect.reason; + // free the device in the wrapper event handler + dev->in_use = false; + if (event_loop_handle) { + esp_hidh_event_data_t p = {0}; + p.close.dev = dev; + p.close.reason = event->disconnect.reason; + p.close.status = ESP_OK; + esp_event_post_to(event_loop_handle, ESP_HIDH_EVENTS, ESP_HIDH_CLOSE_EVENT, &p, sizeof(esp_hidh_event_data_t), portMAX_DELAY); + } else { + esp_hidh_dev_free_inner(dev); + } + } + + return 0; + + case BLE_GAP_EVENT_NOTIFY_RX: + /* Peer sent us a notification or indication. */ + MODLOG_DFLT(DEBUG, "received %s; conn_handle=%d attr_handle=%d " + "attr_len=%d\n", + event->notify_rx.indication ? + "indication" : + "notification", + event->notify_rx.conn_handle, + event->notify_rx.attr_handle, + OS_MBUF_PKTLEN(event->notify_rx.om)); + + /* Attribute data is contained in event->notify_rx.om. Use + * `os_mbuf_copydata` to copy the data received in notification mbuf */ + + dev = esp_hidh_dev_get_by_conn_id(event->notify_rx.conn_handle); + if (!dev) { + ESP_LOGE(TAG, "NOTIFY received for unknown device"); + break; + } + if (event_loop_handle) { + esp_hidh_event_data_t p = {0}; + if (event->notify_rx.attr_handle == dev->ble.battery_handle) { + p.battery.dev = dev; + ble_hs_mbuf_to_flat(event->notify_rx.om, &p.battery.level, sizeof(p.battery.level), NULL); + esp_event_post_to(event_loop_handle, ESP_HIDH_EVENTS, ESP_HIDH_BATTERY_EVENT, + &p, sizeof(esp_hidh_event_data_t), portMAX_DELAY); + } else { + report = esp_hidh_dev_get_report_by_handle(dev, event->notify_rx.attr_handle); + if (report) { + esp_hidh_event_data_t *p_param = NULL; + size_t event_data_size = sizeof(esp_hidh_event_data_t); + + if(report->protocol_mode != dev->protocol_mode[report->map_index]) { + /* only pass the notifications in the current protocol mode */ + ESP_LOGD(TAG, "Wrong protocol mode, dropping notification"); + return 0; + } + if (OS_MBUF_PKTLEN(event->notify_rx.om)) { + event_data_size += OS_MBUF_PKTLEN(event->notify_rx.om); + } + + if ((p_param = (esp_hidh_event_data_t *)malloc(event_data_size)) == NULL) { + ESP_LOGE(TAG, "%s malloc event data failed!", __func__); + break; + } + memset(p_param, 0, event_data_size); + if (OS_MBUF_PKTLEN(event->notify_rx.om) && event->notify_rx.om) { + ble_hs_mbuf_to_flat(event->notify_rx.om, ((uint8_t *)p_param) + sizeof(esp_hidh_event_data_t), + OS_MBUF_PKTLEN(event->notify_rx.om), NULL); + } + + if (report->report_type == ESP_HID_REPORT_TYPE_FEATURE) { + p_param->feature.dev = dev; + p_param->feature.map_index = report->map_index; + p_param->feature.report_id = report->report_id; + p_param->feature.usage = report->usage; + p_param->feature.length = OS_MBUF_PKTLEN(event->notify_rx.om); + p_param->feature.data = ((uint8_t *)p_param) + sizeof(esp_hidh_event_data_t); + esp_event_post_to(event_loop_handle, ESP_HIDH_EVENTS, ESP_HIDH_FEATURE_EVENT, p_param, event_data_size, portMAX_DELAY); + } else { + p_param->input.dev = dev; + p_param->input.map_index = report->map_index; + p_param->input.report_id = report->report_id; + p_param->input.usage = report->usage; + p_param->input.length = OS_MBUF_PKTLEN(event->notify_rx.om); + p_param->input.data = ((uint8_t *)p_param) + sizeof(esp_hidh_event_data_t); + esp_event_post_to(event_loop_handle, ESP_HIDH_EVENTS, ESP_HIDH_INPUT_EVENT, p_param, event_data_size, portMAX_DELAY); + } + + if (p_param) { + free(p_param); + p_param = NULL; + } + } + } + } + break; + return 0; + + case BLE_GAP_EVENT_MTU: + MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n", + event->mtu.conn_handle, + event->mtu.channel_id, + event->mtu.value); + return 0; + default: + return 0; + } + return 0; +} + +/* + * Public Functions + * */ + +static esp_err_t esp_ble_hidh_dev_close(esp_hidh_dev_t *dev) +{ + return ble_gap_terminate(dev->ble.conn_id, BLE_ERR_REM_USER_CONN_TERM); +} + +static esp_err_t esp_ble_hidh_dev_report_write(esp_hidh_dev_t *dev, size_t map_index, size_t report_id, int report_type, uint8_t *value, size_t value_len) +{ + int rc; + esp_hidh_dev_report_t *report = esp_hidh_dev_get_report_by_id_and_type(dev, map_index, report_id, report_type); + if (!report) { + ESP_LOGE(TAG, "%s report %d not found", esp_hid_report_type_str(report_type), report_id); + return ESP_FAIL; + } + if (value_len > report->value_len) { + ESP_LOGE(TAG, "%s report %d takes maximum %d bytes. you have provided %d", esp_hid_report_type_str(report_type), report_id, report->value_len, value_len); + return ESP_FAIL; + } + rc = ble_gattc_write_flat(dev->ble.conn_id, report->handle, value, value_len, on_write, &dev->ble.conn_id); + WAIT_CB();// this is not blocking in bluedroid code + return rc; +} + +static esp_err_t esp_ble_hidh_dev_report_read(esp_hidh_dev_t *dev, size_t map_index, size_t report_id, int report_type, size_t max_length, uint8_t *value, size_t *value_len) +{ + esp_hidh_dev_report_t *report = esp_hidh_dev_get_report_by_id_and_type(dev, map_index, report_id, report_type); + if (!report) { + ESP_LOGE(TAG, "%s report %d not found", esp_hid_report_type_str(report_type), report_id); + return ESP_FAIL; + } + uint16_t len = max_length; + uint8_t *v = NULL; + int s = read_char(dev->ble.conn_id, report->handle, &v, &len); + if (s == 0) { + if (len > max_length) { + len = max_length; + } + *value_len = len; + memcpy(value, v, len); + return ESP_OK; + } + ESP_LOGE(TAG, "%s report %d read failed: 0x%x", esp_hid_report_type_str(report_type), report_id, s); + return ESP_FAIL; +} + +static void esp_ble_hidh_dev_dump(esp_hidh_dev_t *dev, FILE *fp) +{ + fprintf(fp, "BDA:" ESP_BD_ADDR_STR ", Appearance: 0x%04x, Connection ID: %d\n", ESP_BD_ADDR_HEX(dev->bda), + dev->ble.appearance, dev->ble.conn_id); + fprintf(fp, "Name: %s, Manufacturer: %s, Serial Number: %s\n", dev->config.device_name ? dev->config.device_name : "", + dev->config.manufacturer_name ? dev->config.manufacturer_name : "", + dev->config.serial_number ? dev->config.serial_number : ""); + fprintf(fp, "PID: 0x%04x, VID: 0x%04x, VERSION: 0x%04x\n", dev->config.product_id, dev->config.vendor_id, dev->config.version); + fprintf(fp, "Battery: Handle: %u, CCC Handle: %u\n", dev->ble.battery_handle, dev->ble.battery_ccc_handle); + fprintf(fp, "Report Maps: %d\n", dev->config.report_maps_len); + for (uint8_t d = 0; d < dev->config.report_maps_len; d++) { + fprintf(fp, " Report Map Length: %d\n", dev->config.report_maps[d].len); + esp_hidh_dev_report_t *report = dev->reports; + while (report) { + if (report->map_index == d) { + fprintf(fp, " %8s %7s %6s, ID: %2u, Length: %3u, Permissions: 0x%02x, Handle: %3u, CCC Handle: %3u\n", + esp_hid_usage_str(report->usage), esp_hid_report_type_str(report->report_type), + esp_hid_protocol_mode_str(report->protocol_mode), report->report_id, report->value_len, + report->permissions, report->handle, report->ccc_handle); + } + report = report->next; + } + } + +} + +static void esp_ble_hidh_event_handler_wrapper(void *event_handler_arg, esp_event_base_t event_base, int32_t event_id, + void *event_data) +{ + esp_hidh_preprocess_event_handler(event_handler_arg, event_base, event_id, event_data); + + if (s_event_callback) { + s_event_callback(event_handler_arg, event_base, event_id, event_data); + } + + esp_hidh_post_process_event_handler(event_handler_arg, event_base, event_id, event_data); +} + +static void nimble_host_synced(void) { +/* + no need to perform anything here +*/ +} + +static void nimble_host_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +esp_err_t esp_ble_hidh_init(const esp_hidh_config_t *config) +{ + esp_err_t ret; + if (config == NULL) { + ESP_LOGE(TAG, "Config is NULL"); + return ESP_FAIL; + } + if (s_ble_hidh_cb_semaphore != NULL) { + ESP_LOGE(TAG, "Already initialised"); + return ESP_FAIL; + } + s_ble_hidh_cb_semaphore = xSemaphoreCreateBinary(); + if (s_ble_hidh_cb_semaphore == NULL) { + ESP_LOGE(TAG, "xSemaphoreCreateMutex failed!"); + return ESP_FAIL; + } + esp_event_loop_args_t event_task_args = { + .queue_size = 5, + .task_name = "esp_ble_hidh_events", + .task_priority = uxTaskPriorityGet(NULL), + .task_stack_size = config->event_stack_size > 0 ? config->event_stack_size : 2048, + .task_core_id = tskNO_AFFINITY + }; + + do { + ret = esp_event_loop_create(&event_task_args, &event_loop_handle); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "%s esp_event_loop_create failed!", __func__); + break; + } + + s_event_callback = config->callback; + ret = esp_event_handler_register_with(event_loop_handle, ESP_HIDH_EVENTS, ESP_EVENT_ANY_ID, + esp_ble_hidh_event_handler_wrapper, config->callback_arg); + } while (0); + + if (ret != ESP_OK) { + if (event_loop_handle) { + esp_event_loop_delete(event_loop_handle); + } + + if (s_ble_hidh_cb_semaphore) { + vSemaphoreDelete(s_ble_hidh_cb_semaphore); + s_ble_hidh_cb_semaphore = NULL; + } + } + + ble_hs_cfg.reset_cb = nimble_host_reset; + ble_hs_cfg.sync_cb = nimble_host_synced; + return ret; +} + +esp_err_t esp_ble_hidh_deinit(void) +{ + if (s_ble_hidh_cb_semaphore == NULL) { + ESP_LOGE(TAG, "Already deinitialised"); + return ESP_FAIL; + } + + if (event_loop_handle) { + esp_event_loop_delete(event_loop_handle); + } + vSemaphoreDelete(s_ble_hidh_cb_semaphore); + s_ble_hidh_cb_semaphore = NULL; + s_event_callback = NULL; + + return 0; +} + +esp_hidh_dev_t *esp_ble_hidh_dev_open(uint8_t *bda, uint8_t address_type) +{ + esp_err_t ret; + ble_addr_t addr; + uint8_t own_addr_type; + + own_addr_type = 0; // set to public for now + esp_hidh_dev_t *dev = esp_hidh_dev_malloc(); + if (dev == NULL) { + ESP_LOGE(TAG, "malloc esp_hidh_dev_t failed"); + return NULL; + } + + dev->in_use = true; + dev->transport = ESP_HID_TRANSPORT_BLE; + memcpy(dev->bda, bda, sizeof(dev->bda)); + dev->ble.address_type = address_type; + dev->ble.appearance = ESP_HID_APPEARANCE_GENERIC; + + memcpy(addr.val, bda, sizeof(addr.val)); + addr.type = address_type; + + ret = ble_gap_connect(own_addr_type, &addr, 30000, NULL, esp_hidh_gattc_event_handler, NULL); + if (ret) { + esp_hidh_dev_free_inner(dev); + ESP_LOGE(TAG, "esp_ble_gattc_open failed: %d", ret); + return NULL; + } + WAIT_CB(); + if (dev->ble.conn_id < 0) { + ret = dev->status; + ESP_LOGE(TAG, "dev open failed! status: 0x%x", dev->status); + esp_hidh_dev_free_inner(dev); + return NULL; + } + + dev->close = esp_ble_hidh_dev_close; + dev->report_write = esp_ble_hidh_dev_report_write; + dev->report_read = esp_ble_hidh_dev_report_read; + dev->dump = esp_ble_hidh_dev_dump; + + /* perform service discovery and fill the report maps */ + read_device_services(dev); + + if (event_loop_handle) { + esp_hidh_event_data_t p = {0}; + p.open.status = ESP_OK; + p.open.dev = dev; + esp_event_post_to(event_loop_handle, ESP_HIDH_EVENTS, ESP_HIDH_OPEN_EVENT, &p, sizeof(esp_hidh_event_data_t), portMAX_DELAY); + } + + attach_report_listeners(dev); + return dev; +} +#endif // CONFIG_BT_NIMBLE_HID_SERVICE diff --git a/components/esp_http_client/Kconfig b/components/esp_http_client/Kconfig index b7ea8ed68cd..355b591c8f7 100644 --- a/components/esp_http_client/Kconfig +++ b/components/esp_http_client/Kconfig @@ -21,4 +21,12 @@ menu "ESP HTTP client" This option will enable HTTP Digest Authentication. It is enabled by default, but use of this configuration is not recommended as the password can be derived from the exchange, so it introduces a vulnerability when not using TLS + + config ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT + bool "Enable custom transport" + default n + help + This option will enable injection of a custom tcp_transport handle, so the http operation + will be performed on top of the user defined transport abstraction (if configured) + endmenu diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c index 8f91ef3b05e..1b120532c54 100644 --- a/components/esp_http_client/esp_http_client.c +++ b/components/esp_http_client/esp_http_client.c @@ -88,6 +88,13 @@ typedef enum { HTTP_STATE_RES_COMPLETE_DATA, HTTP_STATE_CLOSE } esp_http_state_t; + +typedef enum { + SESSION_TICKET_UNUSED = 0, + SESSION_TICKET_NOT_SAVED, + SESSION_TICKET_SAVED, +} session_ticket_state_t; + /** * HTTP client class */ @@ -127,6 +134,9 @@ struct esp_http_client { esp_transport_keep_alive_t keep_alive_cfg; struct ifreq *if_name; unsigned cache_data_in_fetch_hdr: 1; +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + session_ticket_state_t session_ticket_state; +#endif }; typedef struct esp_http_client esp_http_client_t; @@ -194,7 +204,7 @@ static void http_dispatch_event_to_event_loop(int32_t event_id, const void* even { esp_err_t err = esp_event_post(ESP_HTTP_CLIENT_EVENT, event_id, event_data, event_data_size, portMAX_DELAY); if (err != ESP_OK) { - ESP_LOGE(TAG, "Failed to post https_ota event: %"PRId32", error: %s", event_id, esp_err_to_name(err)); + ESP_LOGE(TAG, "Failed to post http_client event: %"PRId32", error: %s", event_id, esp_err_to_name(err)); } } @@ -569,6 +579,7 @@ static esp_err_t _clear_auth_data(esp_http_client_handle_t client) free(client->auth_data->qop); free(client->auth_data->nonce); free(client->auth_data->opaque); + free(client->auth_data->uri); memset(client->auth_data, 0, sizeof(esp_http_auth_data_t)); return ESP_OK; } @@ -600,7 +611,12 @@ static esp_err_t esp_http_client_prepare(esp_http_client_handle_t client) auth_response = http_auth_basic(client->connection_info.username, client->connection_info.password); #ifdef CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH } else if (client->connection_info.auth_type == HTTP_AUTH_TYPE_DIGEST && client->auth_data) { - client->auth_data->uri = client->connection_info.path; + client->auth_data->uri = NULL; + http_utils_assign_string(&client->auth_data->uri,client->connection_info.path,-1); + if (client->connection_info.query){ + http_utils_append_string(&client->auth_data->uri,"?",-1); + http_utils_append_string(&client->auth_data->uri,client->connection_info.query,-1); + } client->auth_data->cnonce = ((uint64_t)esp_random() << 32) + esp_random(); auth_response = http_auth_digest(client->connection_info.username, client->connection_info.password, client->auth_data); client->auth_data->nc ++; @@ -742,6 +758,18 @@ esp_http_client_handle_t esp_http_client_init(const esp_http_client_config_t *co } #endif +#if CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + if (config->save_client_session) { + client->session_ticket_state = SESSION_TICKET_NOT_SAVED; + } +#endif + +#if CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT + if (config->transport) { + client->transport = config->transport; + } +#endif + if (config->client_key_pem) { if (!config->client_key_len) { esp_transport_ssl_set_client_key_data(ssl, config->client_key_pem, strlen(config->client_key_pem)); @@ -1116,7 +1144,12 @@ static int esp_http_client_get_data(esp_http_client_handle_t client) int rlen = esp_transport_read(client->transport, res_buffer->data, client->buffer_size_rx, client->timeout_ms); if (rlen >= 0) { - http_parser_execute(client->parser, client->parser_settings, res_buffer->data, rlen); + // When tls error is ESP_TLS_ERR_SSL_WANT_READ (-0x6900), esp_trasnport_read returns ERR_TCP_TRANSPORT_CONNECTION_TIMEOUT (0x0). + // We should not execute http_parser_execute() on this condition as it sets the internal state machine in an + // invalid state. + if (!(client->is_async && rlen == 0)) { + http_parser_execute(client->parser, client->parser_settings, res_buffer->data, rlen); + } } return rlen; } @@ -1382,8 +1415,21 @@ static esp_err_t esp_http_client_connect(esp_http_client_handle_t client) } if (client->state < HTTP_STATE_CONNECTED) { - ESP_LOGD(TAG, "Begin connect to: %s://%s:%d", client->connection_info.scheme, client->connection_info.host, client->connection_info.port); - client->transport = esp_transport_list_get_transport(client->transport_list, client->connection_info.scheme); +#ifdef CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT + // If the custom transport is enabled and defined, we skip the selection of appropriate transport from the list + // based on the scheme, since we already have the transport + if (!client->transport) +#endif + { + ESP_LOGD(TAG, "Begin connect to: %s://%s:%d", client->connection_info.scheme, client->connection_info.host, client->connection_info.port); + client->transport = esp_transport_list_get_transport(client->transport_list, client->connection_info.scheme); + } + +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + if (client->session_ticket_state == SESSION_TICKET_SAVED) { + esp_transport_ssl_session_ticket_operation(client->transport, ESP_TRANSPORT_SESSION_TICKET_USE); + } +#endif if (client->transport == NULL) { ESP_LOGE(TAG, "No transport found"); #ifndef CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS @@ -1415,6 +1461,13 @@ static esp_err_t esp_http_client_connect(esp_http_client_handle_t client) client->state = HTTP_STATE_CONNECTED; http_dispatch_event(client, HTTP_EVENT_ON_CONNECTED, NULL, 0); http_dispatch_event_to_event_loop(HTTP_EVENT_ON_CONNECTED, &client, sizeof(esp_http_client_handle_t)); +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + if (client->session_ticket_state != SESSION_TICKET_UNUSED) { + esp_transport_ssl_session_ticket_operation(client->transport, ESP_TRANSPORT_SESSION_TICKET_SAVE); + client->session_ticket_state = SESSION_TICKET_SAVED; + } +#endif + } return ESP_OK; } @@ -1707,6 +1760,9 @@ void esp_http_client_add_auth(esp_http_client_handle_t client) client->auth_data->nc = 1; client->auth_data->realm = http_utils_get_string_between(auth_header, "realm=\"", "\""); client->auth_data->algorithm = http_utils_get_string_between(auth_header, "algorithm=", ","); + if (client->auth_data->algorithm == NULL) { + client->auth_data->algorithm = http_utils_get_string_after(auth_header, "algorithm="); + } if (client->auth_data->algorithm == NULL) { client->auth_data->algorithm = strdup("MD5"); } diff --git a/components/esp_http_client/include/esp_http_client.h b/components/esp_http_client/include/esp_http_client.h index 06bee3dda82..1c50a1fa5ae 100644 --- a/components/esp_http_client/include/esp_http_client.h +++ b/components/esp_http_client/include/esp_http_client.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,11 @@ ESP_EVENT_DECLARE_BASE(ESP_HTTP_CLIENT_EVENT); typedef struct esp_http_client *esp_http_client_handle_t; typedef struct esp_http_client_event *esp_http_client_event_handle_t; +#if CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT +// Forward declares transport handle item to keep the dependency private (even if ENABLE_CUSTOM_TRANSPORT=y) +struct esp_transport_item_t; +#endif + /** * @brief HTTP Client events id */ @@ -178,6 +183,12 @@ typedef struct { #if CONFIG_ESP_TLS_USE_DS_PERIPHERAL void *ds_data; /*!< Pointer for digital signature peripheral context, see ESP-TLS Documentation for more details */ #endif +#if CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + bool save_client_session; +#endif +#if CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT + struct esp_transport_item_t *transport; +#endif } esp_http_client_config_t; /** diff --git a/components/esp_http_client/lib/http_auth.c b/components/esp_http_client/lib/http_auth.c index 6b8e0924026..a478660b200 100644 --- a/components/esp_http_client/lib/http_auth.c +++ b/components/esp_http_client/lib/http_auth.c @@ -12,6 +12,7 @@ #include "sys/socket.h" #include "esp_rom_md5.h" #include "esp_tls_crypto.h" +#include "mbedtls/sha256.h" #include "esp_log.h" #include "esp_check.h" @@ -20,6 +21,8 @@ #include "http_auth.h" #define MD5_MAX_LEN (33) +#define SHA256_LEN (32) +#define SHA256_HEX_LEN (65) #define HTTP_AUTH_BUF_LEN (1024) static const char *TAG = "HTTP_AUTH"; @@ -59,6 +62,54 @@ static int md5_printf(char *md, const char *fmt, ...) return MD5_MAX_LEN; } +/** + * @brief This function hash a formatted string with SHA256 and format the result as ascii characters + * + * @param sha The buffer will hold the ascii result + * @param[in] fmt The format + * + * @return Length of the result + */ +static int sha256_sprintf(char *sha, const char *fmt, ...) +{ + + unsigned char *buf; + unsigned char digest[SHA256_LEN]; + int len, i; + va_list ap; + va_start(ap, fmt); + len = vasprintf((char **)&buf, fmt, ap); + if (buf == NULL) { + va_end(ap); + return ESP_FAIL; + } + + int ret = 0; + mbedtls_sha256_context sha256; + mbedtls_sha256_init(&sha256); + if (mbedtls_sha256_starts(&sha256, 0) != 0) { + goto exit; + } + if (mbedtls_sha256_update(&sha256, buf, len) != 0) { + goto exit; + } + if (mbedtls_sha256_finish(&sha256, digest) != 0) { + goto exit; + } + + for (i = 0; i < 32; ++i) { + sprintf(&sha[i * 2], "%02x", (unsigned int)digest[i]); + } + sha[SHA256_HEX_LEN - 1] = '\0'; + ret = SHA256_HEX_LEN; + +exit: + free(buf); + mbedtls_sha256_free(&sha256); + va_end(ap); + return ret; +} + char *http_auth_digest(const char *username, const char *password, esp_http_auth_data_t *auth_data) { char *ha1, *ha2 = NULL; @@ -68,57 +119,67 @@ char *http_auth_digest(const char *username, const char *password, esp_http_auth esp_err_t ret = ESP_OK; if (username == NULL || - password == NULL || - auth_data->nonce == NULL || - auth_data->uri == NULL || - auth_data->realm == NULL) { + password == NULL || + auth_data->nonce == NULL || + auth_data->uri == NULL || + auth_data->realm == NULL) { return NULL; } - ha1 = calloc(1, MD5_MAX_LEN); + int digest_size = MD5_MAX_LEN; + int (*digest_func)(char *digest, const char *fmt, ...) = md5_printf; + if (!memcmp(auth_data->algorithm, "SHA256", strlen("SHA256")) || + !memcmp(auth_data->algorithm, "SHA-256", strlen("SHA-256"))) { + digest_size = SHA256_HEX_LEN; + digest_func = sha256_sprintf; + } + + ha1 = calloc(1, digest_size); ESP_GOTO_ON_FALSE(ha1, ESP_FAIL, _digest_exit, TAG, "Memory exhausted"); - ha2 = calloc(1, MD5_MAX_LEN); + ha2 = calloc(1, digest_size); ESP_GOTO_ON_FALSE(ha2, ESP_FAIL, _digest_exit, TAG, "Memory exhausted"); - digest = calloc(1, MD5_MAX_LEN); + digest = calloc(1, digest_size); ESP_GOTO_ON_FALSE(digest, ESP_FAIL, _digest_exit, TAG, "Memory exhausted"); - if (md5_printf(ha1, "%s:%s:%s", username, auth_data->realm, password) <= 0) { + if (digest_func(ha1, "%s:%s:%s", username, auth_data->realm, password) <= 0) { goto _digest_exit; } ESP_LOGD(TAG, "%s %s %s %s", "Digest", username, auth_data->realm, password); - if (strcasecmp(auth_data->algorithm, "md5-sess") == 0) { - if (md5_printf(ha1, "%s:%s:%016llx", ha1, auth_data->nonce, auth_data->cnonce) <= 0) { + if ((strcasecmp(auth_data->algorithm, "md5-sess") == 0) || + (strcasecmp(auth_data->algorithm, "SHA256") == 0) || + (strcasecmp(auth_data->algorithm, "md5-sess") == 0)) { + if (digest_func(ha1, "%s:%s:%016llx", ha1, auth_data->nonce, auth_data->cnonce) <= 0) { goto _digest_exit; } } - if (md5_printf(ha2, "%s:%s", auth_data->method, auth_data->uri) <= 0) { + if (digest_func(ha2, "%s:%s", auth_data->method, auth_data->uri) <= 0) { goto _digest_exit; } //support qop = auth if (auth_data->qop && strcasecmp(auth_data->qop, "auth-int") == 0) { - if (md5_printf(ha2, "%s:%s", ha2, "entity") <= 0) { + if (digest_func(ha2, "%s:%s", ha2, "entity") <= 0) { goto _digest_exit; } } if (auth_data->qop) { - // response=MD5(HA1:nonce:nonceCount:cnonce:qop:HA2) - if (md5_printf(digest, "%s:%s:%08x:%016llx:%s:%s", ha1, auth_data->nonce, auth_data->nc, auth_data->cnonce, auth_data->qop, ha2) <= 0) { + // response=digest_func(HA1:nonce:nonceCount:cnonce:qop:HA2) + if (digest_func(digest, "%s:%s:%08x:%016llx:%s:%s", ha1, auth_data->nonce, auth_data->nc, auth_data->cnonce, auth_data->qop, ha2) <= 0) { goto _digest_exit; } } else { - // response=MD5(HA1:nonce:HA2) - if (md5_printf(digest, "%s:%s:%s", ha1, auth_data->nonce, ha2) <= 0) { + // response=digest_func(HA1:nonce:HA2) + if (digest_func(digest, "%s:%s:%s", ha1, auth_data->nonce, ha2) <= 0) { goto _digest_exit; } } - int rc = asprintf(&auth_str, "Digest username=\"%s\", realm=\"%s\", nonce=\"%s\", uri=\"%s\", algorithm=\"MD5\", " - "response=\"%s\", qop=%s, nc=%08x, cnonce=%016"PRIx64, - username, auth_data->realm, auth_data->nonce, auth_data->uri, digest, auth_data->qop, auth_data->nc, auth_data->cnonce); + int rc = asprintf(&auth_str, "Digest username=\"%s\", realm=\"%s\", nonce=\"%s\", uri=\"%s\", algorithm=%s, " + "response=\"%s\", qop=%s, nc=%08x, cnonce=\"%016"PRIx64"\"", + username, auth_data->realm, auth_data->nonce, auth_data->uri, auth_data->algorithm, digest, auth_data->qop, auth_data->nc, auth_data->cnonce); if (rc < 0) { ESP_LOGE(TAG, "asprintf() returned: %d", rc); ret = ESP_FAIL; diff --git a/components/esp_http_client/lib/http_utils.c b/components/esp_http_client/lib/http_utils.c index 495b949a6ef..a47796c187c 100644 --- a/components/esp_http_client/lib/http_utils.c +++ b/components/esp_http_client/lib/http_utils.c @@ -123,6 +123,23 @@ char *http_utils_get_string_between(const char *str, const char *begin, const ch return NULL; } +char *http_utils_get_string_after(const char *str, const char *begin) +{ + char *found = strcasestr(str, begin); + char *ret = NULL; + if (found) { + found += strlen(begin); + char *found_end = (char *)str + strlen(str); + if (found_end) { + ret = calloc(1, found_end - found + 1); + mem_check(ret); + memcpy(ret, found, found_end - found); + return ret; + } + } + return NULL; +} + int http_utils_str_starts_with(const char *str, const char *start) { int i; diff --git a/components/esp_http_client/lib/include/http_utils.h b/components/esp_http_client/lib/include/http_utils.h index 5d09a5c6ac0..e3758e3f3d0 100644 --- a/components/esp_http_client/lib/include/http_utils.h +++ b/components/esp_http_client/lib/include/http_utils.h @@ -55,6 +55,17 @@ void http_utils_trim_whitespace(char **str); */ char *http_utils_get_string_between(const char *str, const char *begin, const char *end); +/** + * @brief Returns a string that contains the part after the search string till the end of the source string. + * It will allocate a new memory space for this string, so you need to free it when no longer used + * + * @param[in] str The source string + * @param[in] begin The search string + * + * @return The string between begin and the end of str + */ +char *http_utils_get_string_after(const char *str, const char *begin); + /** * @brief Join 2 strings to one * It will allocate a new memory space for this string, so you need to free it when no longer use diff --git a/components/esp_http_server/include/esp_http_server.h b/components/esp_http_server/include/esp_http_server.h index 6e4d8771b28..6b0e789bd40 100644 --- a/components/esp_http_server/include/esp_http_server.h +++ b/components/esp_http_server/include/esp_http_server.h @@ -54,6 +54,7 @@ initializer that should be kept in sync .task_priority = tskIDLE_PRIORITY+5, \ .stack_size = 4096, \ .core_id = tskNO_AFFINITY, \ + .task_caps = (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT), \ .server_port = 80, \ .ctrl_port = ESP_HTTPD_DEF_CTRL_PORT, \ .max_open_sockets = 7, \ @@ -168,6 +169,7 @@ typedef struct httpd_config { unsigned task_priority; /*!< Priority of FreeRTOS task which runs the server */ size_t stack_size; /*!< The maximum stack size allowed for the server task */ BaseType_t core_id; /*!< The core the HTTP server task will run on */ + uint32_t task_caps; /*!< The memory capabilities to use when allocating the HTTP server task's stack */ /** * TCP Port number for receiving and transmitting HTTP traffic @@ -1291,6 +1293,30 @@ esp_err_t httpd_resp_set_hdr(httpd_req_t *r, const char *field, const char *valu */ esp_err_t httpd_resp_send_err(httpd_req_t *req, httpd_err_code_t error, const char *msg); +/** + * @brief For sending out custom error code in response to HTTP request. + * + * @note + * - This API is supposed to be called only from the context of + * a URI handler where httpd_req_t* request pointer is valid. + * - Once this API is called, all request headers are purged, so + * request headers need be copied into separate buffers if + * they are required later. + * - If you wish to send additional data in the body of the + * response, please use the lower-level functions directly. + * + * @param[in] req Pointer to the HTTP request for which the response needs to be sent + * @param[in] status Error status to send + * @param[in] msg Error message string + * + * @return + * - ESP_OK : On successfully sending the response packet + * - ESP_ERR_INVALID_ARG : Null arguments + * - ESP_ERR_HTTPD_RESP_SEND : Error in raw send + * - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer + */ +esp_err_t httpd_resp_send_custom_err(httpd_req_t *req, const char *status, const char *msg); + /** * @brief Helper function for HTTP 404 * diff --git a/components/esp_http_server/src/httpd_main.c b/components/esp_http_server/src/httpd_main.c index db1500039e9..7b5e9560617 100644 --- a/components/esp_http_server/src/httpd_main.c +++ b/components/esp_http_server/src/httpd_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -101,6 +101,7 @@ static esp_err_t httpd_accept_conn(struct httpd_data *hd, int listen_fd) ESP_LOGE(TAG, LOG_FMT("error in setsockopt SO_KEEPALIVE (%d)"), errno); goto exit; } +#ifndef __APPLE__ if (setsockopt(new_fd, IPPROTO_TCP, TCP_KEEPIDLE, &keep_alive_idle, sizeof(keep_alive_idle)) < 0) { ESP_LOGE(TAG, LOG_FMT("error in setsockopt TCP_KEEPIDLE (%d)"), errno); goto exit; @@ -113,6 +114,12 @@ static esp_err_t httpd_accept_conn(struct httpd_data *hd, int listen_fd) ESP_LOGE(TAG, LOG_FMT("error in setsockopt TCP_KEEPCNT (%d)"), errno); goto exit; } +#else // __APPLE__ + if (setsockopt(new_fd, IPPROTO_TCP, TCP_KEEPALIVE, &keep_alive_idle, sizeof(keep_alive_idle)) < 0) { + ESP_LOGE(TAG, LOG_FMT("error in setsockopt TCP_KEEPALIVE (%d)"), errno); + goto exit; + } +#endif // __APPLE__ } if (ESP_OK != httpd_sess_new(hd, new_fd)) { ESP_LOGE(TAG, LOG_FMT("session creation failed")); @@ -519,7 +526,8 @@ esp_err_t httpd_start(httpd_handle_t *handle, const httpd_config_t *config) hd->config.stack_size, hd->config.task_priority, httpd_thread, hd, - hd->config.core_id) != ESP_OK) { + hd->config.core_id, + hd->config.task_caps) != ESP_OK) { /* Failed to launch task */ httpd_delete(hd); return ESP_ERR_HTTPD_TASK; diff --git a/components/esp_http_server/src/httpd_txrx.c b/components/esp_http_server/src/httpd_txrx.c index a3c24a10f6f..3630bb2833b 100644 --- a/components/esp_http_server/src/httpd_txrx.c +++ b/components/esp_http_server/src/httpd_txrx.c @@ -483,6 +483,45 @@ esp_err_t httpd_resp_send_err(httpd_req_t *req, httpd_err_code_t error, const ch return ret; } +esp_err_t httpd_resp_send_custom_err(httpd_req_t *req, const char *status, const char *msg) +{ + ESP_LOGW(TAG, LOG_FMT("%s - %s"), status, msg); + + /* Set error code in HTTP response */ + httpd_resp_set_status(req, status); + httpd_resp_set_type(req, HTTPD_TYPE_TEXT); + +#ifdef CONFIG_HTTPD_ERR_RESP_NO_DELAY + /* Use TCP_NODELAY option to force socket to send data in buffer + * This ensures that the error message is sent before the socket + * is closed */ + struct httpd_req_aux *ra = req->aux; + int nodelay = 1; + if (setsockopt(ra->sd->fd, IPPROTO_TCP, TCP_NODELAY, &nodelay, sizeof(nodelay)) < 0) { + /* If failed to turn on TCP_NODELAY, throw warning and continue */ + ESP_LOGW(TAG, LOG_FMT("error calling setsockopt : %d"), errno); + nodelay = 0; + } +#endif + + /* Send HTTP error message */ + esp_err_t ret = httpd_resp_send(req, msg, HTTPD_RESP_USE_STRLEN); + +#ifdef CONFIG_HTTPD_ERR_RESP_NO_DELAY + /* If TCP_NODELAY was set successfully above, time to disable it */ + if (nodelay == 1) { + nodelay = 0; + if (setsockopt(ra->sd->fd, IPPROTO_TCP, TCP_NODELAY, &nodelay, sizeof(nodelay)) < 0) { + /* If failed to turn off TCP_NODELAY, throw error and + * return failure to signal for socket closure */ + ESP_LOGE(TAG, LOG_FMT("error calling setsockopt : %d"), errno); + return ESP_ERR_INVALID_STATE; + } + } +#endif + return ret; +} + esp_err_t httpd_register_err_handler(httpd_handle_t handle, httpd_err_code_t error, httpd_err_handler_func_t err_handler_fn) diff --git a/components/esp_http_server/src/port/esp32/osal.h b/components/esp_http_server/src/port/esp32/osal.h index 48e3fc412af..092aadbb3fc 100644 --- a/components/esp_http_server/src/port/esp32/osal.h +++ b/components/esp_http_server/src/port/esp32/osal.h @@ -25,9 +25,9 @@ typedef TaskHandle_t othread_t; static inline int httpd_os_thread_create(othread_t *thread, const char *name, uint16_t stacksize, int prio, void (*thread_routine)(void *arg), void *arg, - BaseType_t core_id) + BaseType_t core_id, uint32_t caps) { - int ret = xTaskCreatePinnedToCore(thread_routine, name, stacksize, arg, prio, thread, core_id); + int ret = xTaskCreatePinnedToCoreWithCaps(thread_routine, name, stacksize, arg, prio, thread, core_id, caps); if (ret == pdPASS) { return OS_SUCCESS; } @@ -37,7 +37,7 @@ static inline int httpd_os_thread_create(othread_t *thread, /* Only self delete is supported */ static inline void httpd_os_thread_delete(void) { - vTaskDelete(xTaskGetCurrentTaskHandle()); + vTaskDeleteWithCaps(xTaskGetCurrentTaskHandle()); } static inline void httpd_os_thread_sleep(int msecs) diff --git a/components/esp_http_server/src/port/linux/osal.h b/components/esp_http_server/src/port/linux/osal.h index dd2df6aaee1..f2d50dfad02 100644 --- a/components/esp_http_server/src/port/linux/osal.h +++ b/components/esp_http_server/src/port/linux/osal.h @@ -21,7 +21,7 @@ typedef TaskHandle_t othread_t; static inline int httpd_os_thread_create(othread_t *thread, const char *name, uint16_t stacksize, int prio, void (*thread_routine)(void *arg), void *arg, - BaseType_t core_id) + BaseType_t core_id, uint32_t caps) { pthread_attr_t thread_attr; pthread_attr_init(&thread_attr); diff --git a/components/esp_http_server/test_apps/main/test_http_server.c b/components/esp_http_server/test_apps/main/test_http_server.c index 0acb8c9ed40..586539d1e06 100644 --- a/components/esp_http_server/test_apps/main/test_http_server.c +++ b/components/esp_http_server/test_apps/main/test_http_server.c @@ -92,7 +92,7 @@ httpd_handle_t test_httpd_start(uint16_t id) config.max_uri_handlers = HTTPD_TEST_MAX_URI_HANDLERS; config.server_port += id; config.ctrl_port += id; - TEST_ASSERT(httpd_start(&hd, &config) == ESP_OK) + TEST_ASSERT(httpd_start(&hd, &config) == ESP_OK); return hd; } diff --git a/components/esp_https_ota/src/esp_https_ota.c b/components/esp_https_ota/src/esp_https_ota.c index df1e928f7ac..2449a659cde 100644 --- a/components/esp_https_ota/src/esp_https_ota.c +++ b/components/esp_https_ota/src/esp_https_ota.c @@ -665,7 +665,7 @@ esp_err_t esp_https_ota_finish(esp_https_ota_handle_t https_ota_handle) } if ((err == ESP_OK) && (handle->state == ESP_HTTPS_OTA_SUCCESS)) { - esp_err_t err = esp_ota_set_boot_partition(handle->update_partition); + err = esp_ota_set_boot_partition(handle->update_partition); if (err != ESP_OK) { ESP_LOGE(TAG, "esp_ota_set_boot_partition failed! err=0x%x", err); } else { diff --git a/components/esp_https_server/include/esp_https_server.h b/components/esp_https_server/include/esp_https_server.h index 0a598f602ec..1de884127ef 100644 --- a/components/esp_https_server/include/esp_https_server.h +++ b/components/esp_https_server/include/esp_https_server.h @@ -103,31 +103,76 @@ struct httpd_ssl_config { /** User callback for esp_https_server */ esp_https_server_user_cb *user_cb; - void *ssl_userdata; /*!< user data to add to the ssl context */ -#if CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK - esp_tls_handshake_callback cert_select_cb; /*!< Certificate selection callback to use */ -#endif + /** User data to add to the ssl context */ + void *ssl_userdata; + + /** Certificate selection callback to use. + * The callback is only applicable when CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is enabled in menuconfig */ + esp_tls_handshake_callback cert_select_cb; - const char** alpn_protos; /*!< Application protocols the server supports in order of prefernece. Used for negotiating during the TLS handshake, first one the client supports is selected. The data structure must live as long as the https server itself! */ + /** Application protocols the server supports in order of prefernece. + * Used for negotiating during the TLS handshake, first one the client supports is selected. + * The data structure must live as long as the https server itself */ + const char** alpn_protos; }; typedef struct httpd_ssl_config httpd_ssl_config_t; -/* Macro kept for compatibility reasons */ -#define HTTPD_SSL_CONFIG_DEFAULT httpd_ssl_config_default /** - * Returns the httpd config struct with default initialisation - * - * @return - * httpd_ssl_config_t HTTPD ssl config struct - * with default initialisation + * Default config struct init * Notes: * - port is set when starting the server, according to 'transport_mode' * - one socket uses ~ 40kB RAM with SSL, we reduce the default socket count to 4 * - SSL sockets are usually long-lived, closing LRU prevents pool exhaustion DOS * - Stack size may need adjustments depending on the user application */ -httpd_ssl_config_t httpd_ssl_config_default(void); +#define HTTPD_SSL_CONFIG_DEFAULT() { \ + .httpd = { \ + .task_priority = tskIDLE_PRIORITY+5, \ + .stack_size = 10240, \ + .core_id = tskNO_AFFINITY, \ + .task_caps = (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT), \ + .server_port = 0, \ + .ctrl_port = ESP_HTTPD_DEF_CTRL_PORT+1, \ + .max_open_sockets = 4, \ + .max_uri_handlers = 8, \ + .max_resp_headers = 8, \ + .backlog_conn = 5, \ + .lru_purge_enable = true, \ + .recv_wait_timeout = 5, \ + .send_wait_timeout = 5, \ + .global_user_ctx = NULL, \ + .global_user_ctx_free_fn = NULL, \ + .global_transport_ctx = NULL, \ + .global_transport_ctx_free_fn = NULL, \ + .enable_so_linger = false, \ + .linger_timeout = 0, \ + .keep_alive_enable = false, \ + .keep_alive_idle = 0, \ + .keep_alive_interval = 0, \ + .keep_alive_count = 0, \ + .open_fn = NULL, \ + .close_fn = NULL, \ + .uri_match_fn = NULL \ + }, \ + .servercert = NULL, \ + .servercert_len = 0, \ + .cacert_pem = NULL, \ + .cacert_len = 0, \ + .prvtkey_pem = NULL, \ + .prvtkey_len = 0, \ + .use_ecdsa_peripheral = false, \ + .ecdsa_key_efuse_blk = 0, \ + .transport_mode = HTTPD_SSL_TRANSPORT_SECURE, \ + .port_secure = 443, \ + .port_insecure = 80, \ + .session_tickets = false, \ + .use_secure_element = false, \ + .user_cb = NULL, \ + .ssl_userdata = NULL, \ + .cert_select_cb = NULL, \ + .alpn_protos = NULL, \ +} /** * Create a SSL capable HTTP server (secure mode may be disabled in config) diff --git a/components/esp_https_server/src/https_server.c b/components/esp_https_server/src/https_server.c index 42a29c3b746..c224b7c0e1c 100644 --- a/components/esp_https_server/src/https_server.c +++ b/components/esp_https_server/src/https_server.c @@ -48,60 +48,6 @@ static void httpd_ssl_close(void *ctx) ESP_LOGD(TAG, "Secure socket closed"); } -httpd_ssl_config_t httpd_ssl_config_default(void) -{ - httpd_ssl_config_t config = { - .httpd = { - .task_priority = tskIDLE_PRIORITY + 5, - .stack_size = 10240, - .core_id = tskNO_AFFINITY, - .server_port = 0, - .ctrl_port = ESP_HTTPD_DEF_CTRL_PORT + 1, - .max_open_sockets = 4, - .max_uri_handlers = 8, - .max_resp_headers = 8, - .backlog_conn = 5, - .lru_purge_enable = true, - .recv_wait_timeout = 5, - .send_wait_timeout = 5, - .global_user_ctx = NULL, - .global_user_ctx_free_fn = NULL, - .global_transport_ctx = NULL, - .global_transport_ctx_free_fn = NULL, - .enable_so_linger = false, - .linger_timeout = 0, - .keep_alive_enable = false, - .keep_alive_idle = 0, - .keep_alive_interval = 0, - .keep_alive_count = 0, - .open_fn = NULL, - .close_fn = NULL, - .uri_match_fn = NULL, - }, - .servercert = NULL, - .servercert_len = 0, - .cacert_pem = NULL, - .cacert_len = 0, - .prvtkey_pem = NULL, - .prvtkey_len = 0, - .use_ecdsa_peripheral = false, - .ecdsa_key_efuse_blk = 0, - .transport_mode = HTTPD_SSL_TRANSPORT_SECURE, - .port_secure = 443, - .port_insecure = 80, - .session_tickets = false, - .use_secure_element = false, - .user_cb = NULL, - .ssl_userdata = NULL, -#if CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK - .cert_select_cb = NULL, -#endif - .alpn_protos = NULL, - }; - - return config; -} - /** * SSL socket pending-check function * diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index f996e17e520..0c460cc4616 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -27,6 +27,7 @@ if(NOT BOOTLOADER_BUILD) "revision.c" "rtc_module.c" "sleep_modes.c" + "sleep_console.c" "sleep_gpio.c" "sleep_event.c" "sleep_modem.c" @@ -36,7 +37,9 @@ if(NOT BOOTLOADER_BUILD) "port/${target}/io_mux.c" "port/${target}/esp_clk_tree.c" "port/esp_clk_tree_common.c" - "dma/esp_dma_utils.c") + "dma/esp_dma_utils.c" + "spi_share_hw_ctrl.c" + "spi_bus_lock.c") if(CONFIG_SOC_ADC_SUPPORTED) list(APPEND srcs "adc_share_hw_ctrl.c") @@ -51,8 +54,7 @@ if(NOT BOOTLOADER_BUILD) endif() # [refactor-todo] - list(APPEND priv_requires driver # for UART (by sleep_modes) - esp_driver_gpio # for GPIO and RTC (by sleep_gpio and sleep_modes) + list(APPEND priv_requires esp_driver_gpio # for GPIO and RTC (by sleep_gpio and sleep_modes) esp_timer esp_pm) @@ -66,6 +68,10 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "dma/gdma.c") endif() + if(CONFIG_SOC_MULTI_USAGE_LDO_SUPPORTED) + list(APPEND srcs "ldo/esp_ldo.c") + endif() + if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED) list(APPEND srcs "dma/esp_async_memcpy.c") if(CONFIG_SOC_GDMA_SUPPORTED) @@ -80,6 +86,10 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "dma/gdma_etm.c") endif() + if(CONFIG_SOC_DW_GDMA_SUPPORTED) + list(APPEND srcs "dma/dw_gdma.c") + endif() + if(CONFIG_SOC_SYSTIMER_SUPPORTED) list(APPEND srcs "port/${target}/systimer.c") endif() diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 063f57cefa5..ec164459133 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -50,6 +50,13 @@ menu "Hardware Settings" If you have an invalid MAC CRC (ESP_ERR_INVALID_CRC) problem and you still want to use this chip, you can enable this option to bypass such an error. This applies to both MAC_FACTORY and CUSTOM_MAC efuses. + + config ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC + bool "Enable using custom mac as base mac" + default n + help + When this configuration is enabled, the user can invoke `esp_read_mac` to obtain the desired type of + MAC using a custom MAC as the base MAC. endmenu menu "Sleep Config" @@ -134,24 +141,34 @@ menu "Hardware Settings" This option provides a software workaround for this issue. Configure to isolate all GPIO pins in sleep state. - config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY - int "Extra delay in deep sleep wake stub (in us)" - depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 - default 2000 + config ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY + int "Extra delay (in us) after flash powerdown sleep wakeup to wait flash ready" + default 2000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 + default 0 range 0 5000 help - When the chip exits deep sleep, the CPU and the flash chip are powered on - at the same time. CPU will run deep sleep stub first, and then - proceed to load code from flash. Some flash chips need sufficient - time to pass between power on and first read operation. By default, - without any extra delay, this time is approximately 900us, although + When the chip exits sleep, the CPU and the flash chip are powered on at the same time. + CPU will run rom code (deepsleep) or ram code (lightsleep) first, and then load or execute + code from flash. + + Some flash chips need sufficient time to pass between power on and first read operation. + By default, without any extra delay, this time is approximately 900us, although some flash chip types need more than that. - By default extra delay is set to 2000us. When optimizing startup time + (!!! Please adjust this value according to the Data Sheet of SPI Flash used in your project.) + In Flash Data Sheet, the parameters that define the Flash ready timing after power-up (minimum + time from Vcc(min) to CS activeare) usually named tVSL in ELECTRICAL CHARACTERISTICS chapter, + and the configuration value here should be: + ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY = tVSL - 900 + + For esp32 and esp32s3, the default extra delay is set to 2000us. When optimizing startup time for applications which require it, this value may be reduced. - If you are seeing "flash read err, 1000" message printed to the - console after deep sleep reset, try increasing this value. + If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset + on esp32, or triggered RTC_WDT/LP_WDT after lightsleep wakeup, try increasing this value. + (For esp32, the delay will be executed in both deep sleep and light sleep wake up flow. + For chips after esp32, the delay will be executed only in light sleep flow, the delay + controlled by the EFUSE_FLASH_TPUW in ROM will be executed in deepsleep wake up flow.) config ESP_SLEEP_CACHE_SAFE_ASSERTION bool "Check the cache safety of the sleep wakeup code in sleep process" @@ -225,31 +242,7 @@ menu "Hardware Settings" Note that, this option only controls the ETM related driver log, won't affect other drivers. endmenu # ETM Configuration - menu "GDMA Configuration" - depends on SOC_GDMA_SUPPORTED - config GDMA_CTRL_FUNC_IN_IRAM - bool "Place GDMA control functions into IRAM" - default n - help - Place GDMA control functions (like start/stop/append/reset) into IRAM, - so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. - Enabling this option can improve driver performance as well. - - config GDMA_ISR_IRAM_SAFE - bool "GDMA ISR IRAM-Safe" - default n - help - This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash - cache misses, and also be able to run whilst the cache is disabled. - (e.g. SPI Flash write). - - config GDMA_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - Wether to enable the debug log message for GDMA driver. - Note that, this option only controls the GDMA driver log, won't affect other drivers. - endmenu # GDMA Configuration + rsource "./dma/Kconfig.dma" menu "Main XTAL Config" choice XTAL_FREQ_SEL @@ -341,4 +334,21 @@ menu "Hardware Settings" clock support isn't done yet. So with this option, we use xtal on FPGA as the clock source. + # Invisible bringup bypass options for esp_hw_support component + config ESP_BRINGUP_BYPASS_RANDOM_SETTING + bool + default y if !SOC_RNG_SUPPORTED + default n + help + This option is only used for new chip bringup, when + RNG isn't done yet. So with this option, we use 0x5A + to fill the random buffers + + config ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM + bool + default n + + config ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM + bool + default n endmenu diff --git a/components/esp_hw_support/README.md b/components/esp_hw_support/README.md index 20892026c4f..5a952175897 100644 --- a/components/esp_hw_support/README.md +++ b/components/esp_hw_support/README.md @@ -75,3 +75,13 @@ classDiagram class gptimer_etm_task_t { } ``` + +## DMA Service + +With the increasing demand, the hardware design of DMA is changing along the way. At first, each peripheral has a dedicated DMA controller. Later, a centralized DMA controller is introduced, which is called `GDMA` in the software. + +There may be multiple GDMA instances on a chip, some is attached to the AHB bus and some is attached to the AXI bus. But their functionalities are almost the same. + +Some high-performance peripherals, such as MIPI, require DMA to provide more functions, such as hardware handshake mechanism, address growth mode, out-of-order transmission and so on. Therefore, a new DMA controller, called `DW_GDMA` was born. The prefix *DW* is taken from *DesignWare*. + +Please note that the specific DMA controller to be used for peripherals is determined by the specific chip. It is possible that, on chip A, SPI works with AHB GDMA, while on chip B, SPI works with AXI GDMA. diff --git a/components/esp_hw_support/cpu.c b/components/esp_hw_support/cpu.c index 74b521ff766..7fefa9d432d 100644 --- a/components/esp_hw_support/cpu.c +++ b/components/esp_hw_support/cpu.c @@ -387,11 +387,19 @@ esp_err_t esp_cpu_set_watchpoint(int wp_num, const void *wp_addr, size_t size, e { /* Todo: - - Check that wp_num is in range - Check if the wp_num is already in use */ - // Check if size is 2^n, where n is in [0...6] - if (size < 1 || size > 64 || (size & (size - 1)) != 0) { + if (wp_num < 0 || wp_num >= SOC_CPU_WATCHPOINTS_NUM) { + return ESP_ERR_INVALID_ARG; + } + + // Check that the watched region's start address is naturally aligned to the size of the region + if ((uint32_t)wp_addr % size) { + return ESP_ERR_INVALID_ARG; + } + + // Check if size is 2^n, and size is in the range of [1 ... SOC_CPU_WATCHPOINT_MAX_REGION_SIZE] + if (size < 1 || size > SOC_CPU_WATCHPOINT_MAX_REGION_SIZE || (size & (size - 1)) != 0) { return ESP_ERR_INVALID_ARG; } bool on_read = (trigger == ESP_CPU_WATCHPOINT_LOAD || trigger == ESP_CPU_WATCHPOINT_ACCESS); diff --git a/components/esp_hw_support/dma/Kconfig.dma b/components/esp_hw_support/dma/Kconfig.dma new file mode 100644 index 00000000000..6ba2246ef35 --- /dev/null +++ b/components/esp_hw_support/dma/Kconfig.dma @@ -0,0 +1,57 @@ +menu "GDMA Configurations" + depends on SOC_GDMA_SUPPORTED + config GDMA_CTRL_FUNC_IN_IRAM + bool "Place GDMA control functions in IRAM" + default n + help + Place GDMA control functions (like start/stop/append/reset) into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + + config GDMA_ISR_IRAM_SAFE + bool "GDMA ISR IRAM-Safe" + default n + help + This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash + cache misses, and also be able to run whilst the cache is disabled. + (e.g. SPI Flash write). + + config GDMA_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for GDMA driver. + Note that, this option only controls the GDMA driver log, won't affect other drivers. +endmenu # GDMA Configurations + +menu "DW_GDMA Configurations" + depends on SOC_DW_GDMA_SUPPORTED + + config DW_GDMA_CTRL_FUNC_IN_IRAM + bool + default n + help + Place DW_GDMA control functions (e.g. dw_gdma_channel_continue) into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + + config DW_GDMA_SETTER_FUNC_IN_IRAM + bool + default n + help + Place DW_GDMA setter functions (e.g. dw_gdma_channel_set_block_markers) into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + + config DW_GDMA_ISR_IRAM_SAFE + bool + default n + help + This will ensure the DW_GDMA interrupt handler is IRAM-Safe, allow to avoid flash + cache misses, and also be able to run whilst the cache is disabled. + (e.g. SPI Flash write). + + config DW_GDMA_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for DW_GDMA driver. + Note that, this option only controls the DW_GDMA driver log, won't affect other drivers. +endmenu # DW_GDMA Configurations diff --git a/components/esp_hw_support/dma/async_memcpy_gdma.c b/components/esp_hw_support/dma/async_memcpy_gdma.c index d460ca23d0f..eacb73b29d1 100644 --- a/components/esp_hw_support/dma/async_memcpy_gdma.c +++ b/components/esp_hw_support/dma/async_memcpy_gdma.c @@ -19,22 +19,24 @@ #include "esp_memory_utils.h" #include "esp_async_memcpy.h" #include "esp_async_memcpy_priv.h" +#include "esp_cache.h" #include "hal/dma_types.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" -#include "rom/cache.h" static const char *TAG = "async_mcp.gdma"; -#define MCP_NEEDS_INVALIDATE_DST_CACHE CONFIG_IDF_TARGET_ESP32P4 -#define MCP_NEEDS_WRITE_BACK_SRC_CACHE CONFIG_IDF_TARGET_ESP32P4 -#define MCP_NEEDS_WRITE_BACK_DESC_CACHE CONFIG_IDF_TARGET_ESP32P4 +#ifdef CACHE_LL_L2MEM_NON_CACHE_ADDR +#define MCP_GET_NON_CACHE_ADDR(addr) ((addr) ? CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) : 0) +#else +#define MCP_GET_NON_CACHE_ADDR(addr) (addr) +#endif #if SOC_AXI_GDMA_SUPPORTED -#define MCP_DMA_DESC_ALIGN 64 +#define MCP_DMA_DESC_ALIGN 8 typedef dma_descriptor_align8_t mcp_dma_descriptor_t; #elif SOC_AHB_GDMA_SUPPORTED -#define MCP_DMA_DESC_ALIGN 32 +#define MCP_DMA_DESC_ALIGN 4 typedef dma_descriptor_align4_t mcp_dma_descriptor_t; #else #error "Unsupported GDMA type" @@ -47,10 +49,12 @@ typedef dma_descriptor_align4_t mcp_dma_descriptor_t; typedef struct async_memcpy_transaction_t { mcp_dma_descriptor_t eof_node; // this is the DMA node which act as the EOF descriptor (RX path only) mcp_dma_descriptor_t *tx_desc_link; // descriptor link list, the length of the link is determined by the copy buffer size + mcp_dma_descriptor_t *tx_desc_nc; // non-cacheable version of tx_desc_link mcp_dma_descriptor_t *rx_desc_link; // descriptor link list, the length of the link is determined by the copy buffer size + mcp_dma_descriptor_t *rx_desc_nc; // non-cacheable version of rx_desc_link intptr_t tx_start_desc_addr; // TX start descriptor address intptr_t rx_start_desc_addr; // RX start descriptor address - intptr_t memcpy_dst_addr; // memcpy destination address + void *memcpy_dst_addr; // memcpy destination address size_t memcpy_size; // memcpy size async_memcpy_isr_cb_t cb; // user callback void *cb_args; // user callback args @@ -102,7 +106,8 @@ static esp_err_t mcp_gdma_destroy(async_memcpy_gdma_context_t *mcp_gdma) } static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_config_t *config, async_memcpy_handle_t *mcp, - esp_err_t (*new_channel)(const gdma_channel_alloc_config_t *, gdma_channel_handle_t *), int gdma_bus_id) + esp_err_t (*new_channel)(const gdma_channel_alloc_config_t *, gdma_channel_handle_t *), + int gdma_bus_id) { esp_err_t ret = ESP_OK; async_memcpy_gdma_context_t *mcp_gdma = NULL; @@ -113,7 +118,7 @@ static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_confi uint32_t trans_queue_len = config->backlog ? config->backlog : DEFAULT_TRANSACTION_QUEUE_LENGTH; // allocate memory for transaction pool mcp_gdma->transaction_pool = heap_caps_aligned_calloc(MCP_DMA_DESC_ALIGN, trans_queue_len, sizeof(async_memcpy_transaction_t), - MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); ESP_GOTO_ON_FALSE(mcp_gdma->transaction_pool, ESP_ERR_NO_MEM, err, TAG, "no mem for transaction pool"); // create TX channel and RX channel, they should reside in the same DMA pair @@ -134,8 +139,8 @@ static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_confi uint32_t free_m2m_id_mask = 0; gdma_get_free_m2m_trig_id_mask(mcp_gdma->tx_channel, &free_m2m_id_mask); m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask); - gdma_connect(mcp_gdma->rx_channel, m2m_trigger); - gdma_connect(mcp_gdma->tx_channel, m2m_trigger); + ESP_GOTO_ON_ERROR(gdma_connect(mcp_gdma->rx_channel, m2m_trigger), err, TAG, "GDMA rx connect failed"); + ESP_GOTO_ON_ERROR(gdma_connect(mcp_gdma->tx_channel, m2m_trigger), err, TAG, "GDMA tx connect failed"); gdma_transfer_ability_t transfer_ability = { .sram_trans_align = config->sram_trans_align, @@ -164,11 +169,7 @@ static esp_err_t esp_async_memcpy_install_gdma_template(const async_memcpy_confi mcp_gdma->gdma_bus_id = gdma_bus_id; uint32_t psram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); - uint32_t sram_cache_line_size = 0; -#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); -#endif - + uint32_t sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); // if the psram_trans_align is configured to zero, we should fall back to use the data cache line size size_t psram_trans_align = MAX(psram_cache_line_size, config->psram_trans_align); size_t sram_trans_align = MAX(sram_cache_line_size, config->sram_trans_align); @@ -197,10 +198,6 @@ esp_err_t esp_async_memcpy_install_gdma_ahb(const async_memcpy_config_t *config, { return esp_async_memcpy_install_gdma_template(config, mcp, gdma_new_ahb_channel, SOC_GDMA_BUS_AHB); } - -/// default installation falls back to use the AHB GDMA -esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_handle_t *asmcp) -__attribute__((alias("esp_async_memcpy_install_gdma_ahb"))); #endif // SOC_AHB_GDMA_SUPPORTED #if SOC_AXI_GDMA_SUPPORTED @@ -210,6 +207,16 @@ esp_err_t esp_async_memcpy_install_gdma_axi(const async_memcpy_config_t *config, } #endif // SOC_AXI_GDMA_SUPPORTED +#if SOC_AHB_GDMA_SUPPORTED +/// default installation falls back to use the AHB GDMA +esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_handle_t *asmcp) +__attribute__((alias("esp_async_memcpy_install_gdma_ahb"))); +#elif SOC_AXI_GDMA_SUPPORTED +/// default installation falls back to use the AXI GDMA +esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_handle_t *asmcp) +__attribute__((alias("esp_async_memcpy_install_gdma_axi"))); +#endif + static esp_err_t mcp_gdma_del(async_memcpy_context_t *ctx) { async_memcpy_gdma_context_t *mcp_gdma = __containerof(ctx, async_memcpy_gdma_context_t, parent); @@ -220,64 +227,59 @@ static esp_err_t mcp_gdma_del(async_memcpy_context_t *ctx) return mcp_gdma_destroy(mcp_gdma); } -static void mount_tx_buffer_to_dma(mcp_dma_descriptor_t *desc_array, int num_desc, +static void mount_tx_buffer_to_dma(async_memcpy_transaction_t *trans, int num_desc, uint8_t *buf, size_t buf_sz, size_t max_single_dma_buffer) { + mcp_dma_descriptor_t *desc_array = trans->tx_desc_link; + mcp_dma_descriptor_t *desc_nc = trans->tx_desc_nc; uint32_t prepared_length = 0; size_t len = buf_sz; for (int i = 0; i < num_desc - 1; i++) { - desc_array[i].buffer = &buf[prepared_length]; - desc_array[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc_array[i].dw0.suc_eof = 0; - desc_array[i].dw0.size = max_single_dma_buffer; - desc_array[i].dw0.length = max_single_dma_buffer; - desc_array[i].next = &desc_array[i + 1]; + desc_nc[i].buffer = &buf[prepared_length]; + desc_nc[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + desc_nc[i].dw0.suc_eof = 0; + desc_nc[i].dw0.size = max_single_dma_buffer; + desc_nc[i].dw0.length = max_single_dma_buffer; + desc_nc[i].next = &desc_array[i + 1]; prepared_length += max_single_dma_buffer; len -= max_single_dma_buffer; } // take special care to the EOF descriptor - desc_array[num_desc - 1].buffer = &buf[prepared_length]; - desc_array[num_desc - 1].next = NULL; - desc_array[num_desc - 1].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc_array[num_desc - 1].dw0.suc_eof = 1; - desc_array[num_desc - 1].dw0.size = len; - desc_array[num_desc - 1].dw0.length = len; - -#if MCP_NEEDS_WRITE_BACK_DESC_CACHE - Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)desc_array, sizeof(mcp_dma_descriptor_t) * num_desc); -#endif + desc_nc[num_desc - 1].buffer = &buf[prepared_length]; + desc_nc[num_desc - 1].next = NULL; + desc_nc[num_desc - 1].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + desc_nc[num_desc - 1].dw0.suc_eof = 1; + desc_nc[num_desc - 1].dw0.size = len; + desc_nc[num_desc - 1].dw0.length = len; } -static void mount_rx_buffer_to_dma(mcp_dma_descriptor_t *desc_array, int num_desc, mcp_dma_descriptor_t *eof_desc, +static void mount_rx_buffer_to_dma(async_memcpy_transaction_t *trans, int num_desc, uint8_t *buf, size_t buf_sz, size_t max_single_dma_buffer) { + mcp_dma_descriptor_t *desc_array = trans->rx_desc_link; + mcp_dma_descriptor_t *desc_nc = trans->rx_desc_nc; + mcp_dma_descriptor_t *eof_desc = &trans->eof_node; + mcp_dma_descriptor_t *eof_nc = (mcp_dma_descriptor_t *)MCP_GET_NON_CACHE_ADDR(eof_desc); uint32_t prepared_length = 0; size_t len = buf_sz; if (desc_array) { assert(num_desc > 0); for (int i = 0; i < num_desc; i++) { - desc_array[i].buffer = &buf[prepared_length]; - desc_array[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - desc_array[i].dw0.size = max_single_dma_buffer; - desc_array[i].dw0.length = max_single_dma_buffer; - desc_array[i].next = &desc_array[i + 1]; + desc_nc[i].buffer = &buf[prepared_length]; + desc_nc[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + desc_nc[i].dw0.size = max_single_dma_buffer; + desc_nc[i].dw0.length = max_single_dma_buffer; + desc_nc[i].next = &desc_array[i + 1]; prepared_length += max_single_dma_buffer; len -= max_single_dma_buffer; } - desc_array[num_desc - 1].next = eof_desc; + desc_nc[num_desc - 1].next = eof_desc; } - eof_desc->buffer = &buf[prepared_length]; - eof_desc->next = NULL; - eof_desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; - eof_desc->dw0.size = len; - eof_desc->dw0.length = len; - -#if MCP_NEEDS_WRITE_BACK_DESC_CACHE - if (desc_array) { - Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)desc_array, sizeof(mcp_dma_descriptor_t) * num_desc); - } - Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)eof_desc, sizeof(mcp_dma_descriptor_t)); -#endif + eof_nc->buffer = &buf[prepared_length]; + eof_nc->next = NULL; + eof_nc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + eof_nc->dw0.size = len; + eof_nc->dw0.length = len; } /// @brief help function to get one transaction from the ready queue @@ -326,24 +328,34 @@ static async_memcpy_transaction_t *try_pop_trans_from_idle_queue(async_memcpy_gd return trans; } -static bool check_buffer_aligned(async_memcpy_gdma_context_t *mcp_gdma, void *src, void *dst, size_t n) +static bool check_buffer_alignment(async_memcpy_gdma_context_t *mcp_gdma, void *src, void *dst, size_t n) { bool valid = true; - uint32_t align_mask = 0; + uint32_t psram_align_mask = 0; + uint32_t sram_align_mask = 0; + if (mcp_gdma->psram_trans_align) { + psram_align_mask = mcp_gdma->psram_trans_align - 1; + } + if (mcp_gdma->sram_trans_align) { + sram_align_mask = mcp_gdma->sram_trans_align - 1; + } if (esp_ptr_external_ram(dst)) { - if (mcp_gdma->psram_trans_align) { - align_mask = mcp_gdma->psram_trans_align - 1; - } + valid = valid && (((uint32_t)dst & psram_align_mask) == 0); + valid = valid && ((n & psram_align_mask) == 0); } else { - if (mcp_gdma->sram_trans_align) { - align_mask = mcp_gdma->sram_trans_align - 1; - } + valid = valid && (((uint32_t)dst & sram_align_mask) == 0); + valid = valid && ((n & sram_align_mask) == 0); + } + + if (esp_ptr_external_ram(src)) { + valid = valid && (((uint32_t)src & psram_align_mask) == 0); + valid = valid && ((n & psram_align_mask) == 0); + } else { + valid = valid && (((uint32_t)src & sram_align_mask) == 0); + valid = valid && ((n & sram_align_mask) == 0); } - // destination address must be cache line aligned - valid = valid && (((uint32_t)dst & align_mask) == 0); - valid = valid && ((n & align_mask) == 0); return valid; } @@ -359,11 +371,11 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s #endif // SOC_AHB_GDMA_SUPPORTED && !SOC_AHB_GDMA_SUPPORT_PSRAM #if SOC_AXI_GDMA_SUPPORTED && !SOC_AXI_GDMA_SUPPORT_PSRAM if (mcp_gdma->gdma_bus_id == SOC_GDMA_BUS_AXI) { - ESP_RETURN_ON_FALSE(esp_ptr_internal(src) && esp_ptr_internal(dst), ESP_ERR_INVALID_ARG, TAG, "AXI_DMA can only access SRAM"); + ESP_RETURN_ON_FALSE(esp_ptr_internal(src) && esp_ptr_internal(dst), ESP_ERR_INVALID_ARG, TAG, "AXI DMA can only access SRAM"); } #endif // SOC_AXI_GDMA_SUPPORTED && !SOC_AXI_GDMA_SUPPORT_PSRAM // alignment check - ESP_RETURN_ON_FALSE(check_buffer_aligned(mcp_gdma, src, dst, n), ESP_ERR_INVALID_ARG, TAG, "buffer not aligned: %p -> %p, sz=%zu", src, dst, n); + ESP_RETURN_ON_FALSE(check_buffer_alignment(mcp_gdma, src, dst, n), ESP_ERR_INVALID_ARG, TAG, "buffer not aligned: %p -> %p, sz=%zu", src, dst, n); async_memcpy_transaction_t *trans = NULL; // pick one transaction node from idle queue @@ -376,37 +388,44 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s uint32_t num_desc_per_path = (n + max_single_dma_buffer - 1) / max_single_dma_buffer; // allocate DMA descriptors, descriptors need a strict alignment trans->tx_desc_link = heap_caps_aligned_calloc(MCP_DMA_DESC_ALIGN, num_desc_per_path, sizeof(mcp_dma_descriptor_t), - MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); ESP_GOTO_ON_FALSE(trans->tx_desc_link, ESP_ERR_NO_MEM, err, TAG, "no mem for DMA descriptors"); + trans->tx_desc_nc = (mcp_dma_descriptor_t *)MCP_GET_NON_CACHE_ADDR(trans->tx_desc_link); // don't have to allocate the EOF descriptor, we will use trans->eof_node as the RX EOF descriptor if (num_desc_per_path > 1) { trans->rx_desc_link = heap_caps_aligned_calloc(MCP_DMA_DESC_ALIGN, num_desc_per_path - 1, sizeof(mcp_dma_descriptor_t), - MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); ESP_GOTO_ON_FALSE(trans->rx_desc_link, ESP_ERR_NO_MEM, err, TAG, "no mem for DMA descriptors"); + trans->rx_desc_nc = (mcp_dma_descriptor_t *)MCP_GET_NON_CACHE_ADDR(trans->rx_desc_link); } else { // small copy buffer, use the trans->eof_node is sufficient trans->rx_desc_link = NULL; + trans->rx_desc_nc = NULL; } // (preload) mount src data to the TX descriptor - mount_tx_buffer_to_dma(trans->tx_desc_link, num_desc_per_path, src, n, max_single_dma_buffer); + mount_tx_buffer_to_dma(trans, num_desc_per_path, src, n, max_single_dma_buffer); // (preload) mount dst data to the RX descriptor - mount_rx_buffer_to_dma(trans->rx_desc_link, num_desc_per_path - 1, &trans->eof_node, dst, n, max_single_dma_buffer); + mount_rx_buffer_to_dma(trans, num_desc_per_path - 1, dst, n, max_single_dma_buffer); // if the data is in the cache, write back, then DMA can see the latest data -#if MCP_NEEDS_WRITE_BACK_SRC_CACHE - int write_back_map = CACHE_MAP_L1_DCACHE; + bool need_write_back = false; if (esp_ptr_external_ram(src)) { - write_back_map |= CACHE_MAP_L2_CACHE; - } - Cache_WriteBack_Addr(write_back_map, (uint32_t)src, n); + need_write_back = true; + } else if (esp_ptr_internal(src)) { +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + need_write_back = true; #endif + } + if (need_write_back) { + esp_cache_msync(src, n, ESP_CACHE_MSYNC_FLAG_DIR_C2M); + } // save other transaction context trans->cb = cb_isr; trans->cb_args = cb_args; trans->memcpy_size = n; - trans->memcpy_dst_addr = (intptr_t)dst; + trans->memcpy_dst_addr = dst; // save the destination buffer address, because we may need to do data cache invalidate later trans->tx_start_desc_addr = (intptr_t)trans->tx_desc_link; trans->rx_start_desc_addr = trans->rx_desc_link ? (intptr_t)trans->rx_desc_link : (intptr_t)&trans->eof_node; @@ -449,14 +468,19 @@ static bool mcp_gdma_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_ // switch driver state from RUN to IDLE async_memcpy_fsm_t expected_fsm = MCP_FSM_RUN; if (atomic_compare_exchange_strong(&mcp_gdma->fsm, &expected_fsm, MCP_FSM_IDLE_WAIT)) { + void *dst = trans->memcpy_dst_addr; // if the data is in the cache, invalidate, then CPU can see the latest data -#if MCP_NEEDS_INVALIDATE_DST_CACHE - int invalidate_map = CACHE_MAP_L1_DCACHE; - if (esp_ptr_external_ram((const void *)trans->memcpy_dst_addr)) { - invalidate_map |= CACHE_MAP_L2_CACHE; - } - Cache_Invalidate_Addr(invalidate_map, (uint32_t)trans->memcpy_dst_addr, trans->memcpy_size); + bool need_invalidate = false; + if (esp_ptr_external_ram(dst)) { + need_invalidate = true; + } else if (esp_ptr_internal(dst)) { +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + need_invalidate = true; #endif + } + if (need_invalidate) { + esp_cache_msync(dst, trans->memcpy_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C); + } // invoked callback registered by user async_memcpy_isr_cb_t cb = trans->cb; diff --git a/components/esp_hw_support/dma/dw_gdma.c b/components/esp_hw_support/dma/dw_gdma.c new file mode 100644 index 00000000000..5d7755bd7de --- /dev/null +++ b/components/esp_hw_support/dma/dw_gdma.c @@ -0,0 +1,672 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "sdkconfig.h" +#if CONFIG_DW_GDMA_ENABLE_DEBUG_LOG +// The local log level must be defined before including esp_log.h +// Set the maximum log level for this source file +#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG +#endif +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "soc/soc_caps.h" +#include "soc/interrupts.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_intr_alloc.h" +#include "esp_memory_utils.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/dw_gdma.h" +#include "hal/dw_gdma_hal.h" +#include "hal/dw_gdma_ll.h" +#include "hal/cache_hal.h" +#include "hal/cache_ll.h" + +static const char *TAG = "dw-gdma"; + +#if !SOC_RCC_IS_INDEPENDENT +// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section +#define DW_GDMA_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define DW_GDMA_RCC_ATOMIC() +#endif + +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE +#define DW_GDMA_GET_NON_CACHE_ADDR(addr) ((addr) ? CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) : 0) +#else +#define DW_GDMA_GET_NON_CACHE_ADDR(addr) (addr) +#endif + +#if CONFIG_DW_GDMA_ISR_IRAM_SAFE || CONFIG_DW_GDMA_CTRL_FUNC_IN_IRAM || DW_GDMA_SETTER_FUNC_IN_IRAM +#define DW_GDMA_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) +#else +#define DW_GDMA_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT +#endif + +#if CONFIG_DW_GDMA_ISR_IRAM_SAFE +#define DW_GDMA_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM) +#else +#define DW_GDMA_INTR_ALLOC_FLAGS 0 +#endif + +#define DW_GDMA_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED + +typedef struct dw_gdma_group_t dw_gdma_group_t; +typedef struct dw_gdma_channel_t dw_gdma_channel_t; + +typedef struct dw_gdma_link_list_t { + uint32_t num_items; // number of items in the link list + dw_gdma_link_list_item_t *items; // pointer to the link list items + dw_gdma_link_list_item_t *items_nc; // pointer to the link list items, non-cached +} dw_gdma_link_list_t; + +typedef struct { + _lock_t mutex; // platform level mutex lock + dw_gdma_group_t *groups[DW_GDMA_LL_GROUPS]; // array of DMA group instances + int group_ref_counts[DW_GDMA_LL_GROUPS]; // reference count used to protect group install/uninstall +} dw_gdma_platform_t; + +struct dw_gdma_group_t { + int group_id; // Group ID, index from 0 + dw_gdma_hal_context_t hal; // HAL instance is at group level + int intr_priority; // all channels in the same group should share the same interrupt priority + portMUX_TYPE spinlock; // group level spinlock, protect group level stuffs, e.g. hal object, pair handle slots and reference count of each pair + dw_gdma_channel_t *channels[DW_GDMA_LL_CHANNELS_PER_GROUP]; // handles of DMA channels +}; + +struct dw_gdma_channel_t { + int chan_id; // channel ID, index from 0 + intr_handle_t intr; // per-channel interrupt handle + portMUX_TYPE spinlock; // channel level spinlock + dw_gdma_group_t *group; // pointer to the group which the channel belongs to + void *user_data; // user registered DMA event data + dw_gdma_event_callbacks_t cbs; // Event callbacks + dw_gdma_block_transfer_type_t src_transfer_type; // transfer type for source + dw_gdma_block_transfer_type_t dst_transfer_type; // transfer type for destination +}; + +// dw_gdma driver platform +static dw_gdma_platform_t s_platform; + +static dw_gdma_group_t *dw_gdma_acquire_group_handle(int group_id) +{ + bool new_group = false; + dw_gdma_group_t *group = NULL; + + // prevent install dw_gdma group concurrently + _lock_acquire(&s_platform.mutex); + if (!s_platform.groups[group_id]) { + // The group is handle is not created yet + group = heap_caps_calloc(1, sizeof(dw_gdma_group_t), DW_GDMA_MEM_ALLOC_CAPS); + if (group) { + new_group = true; + s_platform.groups[group_id] = group; + // enable APB to access DMA registers + DW_GDMA_RCC_ATOMIC() { + dw_gdma_ll_enable_bus_clock(group_id, true); + dw_gdma_ll_reset_register(group_id); + } + // initialize the HAL context + dw_gdma_hal_config_t hal_config = {}; + dw_gdma_hal_init(&group->hal, &hal_config); + } + } else { + // the group is installed, we just retrieve it and increase the reference count + group = s_platform.groups[group_id]; + } + if (group) { + // someone acquired the group handle means we have a new object that refer to this group + s_platform.group_ref_counts[group_id]++; + } + _lock_release(&s_platform.mutex); + + if (new_group) { + portMUX_INITIALIZE(&group->spinlock); + group->group_id = group_id; + group->intr_priority = -1; // interrupt priority not assigned yet + ESP_LOGD(TAG, "new group (%d) at %p", group_id, group); + } + + return group; +} + +static void dw_gdma_release_group_handle(dw_gdma_group_t *group) +{ + int group_id = group->group_id; + bool del_group = false; + + _lock_acquire(&s_platform.mutex); + s_platform.group_ref_counts[group_id]--; + if (s_platform.group_ref_counts[group_id] == 0) { + del_group = true; + // the group now is not used by any channel, unregister it from the platform + s_platform.groups[group_id] = NULL; + // deinitialize the HAL context + dw_gdma_hal_deinit(&group->hal); + DW_GDMA_RCC_ATOMIC() { + dw_gdma_ll_enable_bus_clock(group_id, false); + } + } + _lock_release(&s_platform.mutex); + + if (del_group) { + free(group); + ESP_LOGD(TAG, "delete group (%d)", group_id); + } +} + +static esp_err_t channel_register_to_group(dw_gdma_channel_t *chan) +{ + dw_gdma_group_t *group = NULL; + int chan_id = -1; + for (int i = 0; i < DW_GDMA_LL_GROUPS; i++) { + group = dw_gdma_acquire_group_handle(i); + ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group(%d)", i); + // loop to search free channel in the group + portENTER_CRITICAL(&group->spinlock); + for (int j = 0; j < DW_GDMA_LL_CHANNELS_PER_GROUP; j++) { + if (group->channels[j] == NULL) { + group->channels[j] = chan; + chan_id = j; + break; + } + } + portEXIT_CRITICAL(&group->spinlock); + if (chan_id < 0) { + dw_gdma_release_group_handle(group); + } else { + chan->group = group; + chan->chan_id = chan_id; + break; + } + } + ESP_RETURN_ON_FALSE(chan_id >= 0, ESP_ERR_NOT_FOUND, TAG, "no free channels"); + return ESP_OK; +} + +static void channel_unregister_from_group(dw_gdma_channel_t *chan) +{ + dw_gdma_group_t *group = chan->group; + int chan_id = chan->chan_id; + portENTER_CRITICAL(&group->spinlock); + group->channels[chan_id] = NULL; + portEXIT_CRITICAL(&group->spinlock); + // channel has a reference on group, release it now + dw_gdma_release_group_handle(group); +} + +static esp_err_t channel_destroy(dw_gdma_channel_t *chan) +{ + if (chan->group) { + channel_unregister_from_group(chan); + } + free(chan); + return ESP_OK; +} + +esp_err_t dw_gdma_new_channel(const dw_gdma_channel_alloc_config_t *config, dw_gdma_channel_handle_t *ret_chan) +{ +#if CONFIG_DW_GDMA_ENABLE_DEBUG_LOG + esp_log_level_set(TAG, ESP_LOG_DEBUG); +#endif + esp_err_t ret = ESP_OK; + dw_gdma_channel_t *chan = NULL; + ESP_RETURN_ON_FALSE(config && ret_chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(config->src.num_outstanding_requests >= 1 && config->src.num_outstanding_requests <= DW_GDMA_LL_MAX_OUTSTANDING_REQUESTS, + ESP_ERR_INVALID_ARG, TAG, "invalid num_outstanding_requests"); + ESP_RETURN_ON_FALSE(config->dst.num_outstanding_requests >= 1 && config->dst.num_outstanding_requests <= DW_GDMA_LL_MAX_OUTSTANDING_REQUESTS, + ESP_ERR_INVALID_ARG, TAG, "invalid num_outstanding_request"); + ESP_RETURN_ON_FALSE(config->chan_priority >= 0 && config->chan_priority < DW_GDMA_LL_CHANNELS_PER_GROUP, + ESP_ERR_INVALID_ARG, TAG, "invalid channel priority"); + if (config->intr_priority) { + ESP_RETURN_ON_FALSE(1 << (config->intr_priority) & DW_GDMA_ALLOW_INTR_PRIORITY_MASK, ESP_ERR_INVALID_ARG, + TAG, "invalid interrupt priority:%d", config->intr_priority); + } + + chan = heap_caps_calloc(1, sizeof(dw_gdma_channel_t), DW_GDMA_MEM_ALLOC_CAPS); + ESP_RETURN_ON_FALSE(chan, ESP_ERR_NO_MEM, TAG, "no mem for channel"); + // register channel to the group + ESP_GOTO_ON_ERROR(channel_register_to_group(chan), err, TAG, "register to group failed"); + dw_gdma_group_t *group = chan->group; + dw_gdma_hal_context_t *hal = &group->hal; + int group_id = group->group_id; + int chan_id = chan->chan_id; + + // all channels in the same group should use the same interrupt priority + bool intr_priority_conflict = false; + portENTER_CRITICAL(&group->spinlock); + if (group->intr_priority == -1) { + group->intr_priority = config->intr_priority; + } else if (config->intr_priority != 0) { + intr_priority_conflict = (group->intr_priority != config->intr_priority); + } + portEXIT_CRITICAL(&group->spinlock); + ESP_GOTO_ON_FALSE(!intr_priority_conflict, ESP_ERR_INVALID_STATE, err, TAG, "intr_priority conflict, already is %d but attempt to %d", group->intr_priority, config->intr_priority); + + // basic initialization + portMUX_INITIALIZE(&chan->spinlock); + chan->src_transfer_type = config->src.block_transfer_type; + chan->dst_transfer_type = config->dst.block_transfer_type; + // set transfer flow type + dw_gdma_ll_channel_set_trans_flow(hal->dev, chan_id, config->src.role, config->dst.role, config->flow_controller); + // set the transfer type for source and destination + dw_gdma_ll_channel_set_src_multi_block_type(hal->dev, chan_id, config->src.block_transfer_type); + dw_gdma_ll_channel_set_dst_multi_block_type(hal->dev, chan_id, config->dst.block_transfer_type); + // set handshake interface + dw_gdma_ll_channel_set_src_handshake_interface(hal->dev, chan_id, config->src.handshake_type); + dw_gdma_ll_channel_set_dst_handshake_interface(hal->dev, chan_id, config->dst.handshake_type); + // set handshake peripheral + if (config->src.role != DW_GDMA_ROLE_MEM) { + dw_gdma_ll_channel_set_src_handshake_periph(hal->dev, chan_id, config->src.role); + } + if (config->dst.role != DW_GDMA_ROLE_MEM) { + dw_gdma_ll_channel_set_dst_handshake_periph(hal->dev, chan_id, config->dst.role); + } + // set channel priority + dw_gdma_ll_channel_set_priority(hal->dev, chan_id, config->chan_priority); + // set the outstanding request number + dw_gdma_ll_channel_set_src_outstanding_limit(hal->dev, chan_id, config->src.num_outstanding_requests); + dw_gdma_ll_channel_set_dst_outstanding_limit(hal->dev, chan_id, config->dst.num_outstanding_requests); + // set the status fetch address + dw_gdma_ll_channel_set_src_periph_status_addr(hal->dev, chan_id, config->src.status_fetch_addr); + dw_gdma_ll_channel_set_dst_periph_status_addr(hal->dev, chan_id, config->dst.status_fetch_addr); + + // enable all channel events (notes, they can't trigger an interrupt until `dw_gdma_ll_channel_enable_intr_propagation` is called) + dw_gdma_ll_channel_enable_intr_generation(hal->dev, chan_id, UINT32_MAX, true); + + ESP_LOGD(TAG, "new channel (%d,%d) at %p", group_id, chan_id, chan); + *ret_chan = chan; + return ESP_OK; +err: + if (chan) { + channel_destroy(chan); + } + return ret; +} + +esp_err_t dw_gdma_del_channel(dw_gdma_channel_handle_t chan) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_group_t *group = chan->group; + int group_id = group->group_id; + int chan_id = chan->chan_id; + ESP_LOGD(TAG, "del channel (%d,%d)", group_id, chan_id); + // recycle memory resource + ESP_RETURN_ON_ERROR(channel_destroy(chan), TAG, "destroy channel failed"); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_enable_ctrl(dw_gdma_channel_handle_t chan, bool en_or_dis) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + // the atomic is ensured by the hardware, so no lock is needed here + dw_gdma_ll_channel_enable(hal->dev, chan_id, en_or_dis); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_suspend_ctrl(dw_gdma_channel_handle_t chan, bool enter_or_exit) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + // the atomic is ensured by the hardware, so no lock is needed here + dw_gdma_ll_channel_suspend(hal->dev, chan_id, enter_or_exit); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_abort(dw_gdma_channel_handle_t chan) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + // the atomic is ensured by the hardware, so no lock is needed here + dw_gdma_ll_channel_abort(hal->dev, chan_id); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_lock(dw_gdma_channel_handle_t chan, dw_gdma_lock_level_t level) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + + // the lock control bit is located in a cfg register, with other configuration bits + portENTER_CRITICAL(&chan->spinlock); + dw_gdma_ll_channel_lock(hal->dev, chan_id, level); + portEXIT_CRITICAL(&chan->spinlock); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_unlock(dw_gdma_channel_handle_t chan) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + + // the lock control bit is located in a cfg register, with other configuration bits + portENTER_CRITICAL(&chan->spinlock); + dw_gdma_ll_channel_unlock(hal->dev, chan_id); + portEXIT_CRITICAL(&chan->spinlock); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_continue(dw_gdma_channel_handle_t chan) +{ + ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + // the atomic is ensured by the hardware, so no lock is needed here + dw_gdma_ll_channel_resume_multi_block_transfer(hal->dev, chan_id); + return ESP_OK; +} + +esp_err_t dw_gdma_new_link_list(const dw_gdma_link_list_config_t *config, dw_gdma_link_list_handle_t *ret_list) +{ + esp_err_t ret = ESP_OK; + ESP_RETURN_ON_FALSE(ret_list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_link_list_item_t *items = NULL; + dw_gdma_link_list_t *list = NULL; + uint32_t num_items = config->num_items; + list = heap_caps_calloc(1, sizeof(dw_gdma_link_list_t), DW_GDMA_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(list, ESP_ERR_NO_MEM, err, TAG, "no mem for link list"); + // the link list item has a strict alignment requirement, so we allocate it separately + items = heap_caps_aligned_calloc(DW_GDMA_LL_LINK_LIST_ALIGNMENT, num_items, + sizeof(dw_gdma_link_list_item_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); + ESP_RETURN_ON_FALSE(items, ESP_ERR_NO_MEM, TAG, "no mem for link list items"); + list->num_items = num_items; + list->items = items; + list->items_nc = (dw_gdma_link_list_item_t *)DW_GDMA_GET_NON_CACHE_ADDR(items); + + // set up the link list + for (size_t i = 0; i < num_items; i++) { + dw_gdma_ll_lli_set_next_item_addr(list->items_nc + i, (uint32_t)(list->items + i + 1)); + // set master port for the link list + dw_gdma_ll_lli_set_link_list_master_port(list->items_nc + i, DW_GDMA_LL_MASTER_PORT_MEMORY); + } + switch (config->link_type) { + case DW_GDMA_LINKED_LIST_TYPE_CIRCULAR: + dw_gdma_ll_lli_set_next_item_addr(list->items_nc + num_items - 1, (uint32_t)(list->items)); + break; + case DW_GDMA_LINKED_LIST_TYPE_SINGLY: + dw_gdma_ll_lli_set_next_item_addr(list->items_nc + num_items - 1, 0); + break; + } + + ESP_LOGD(TAG, "new link list @%p, items @%p", list, items); + *ret_list = list; + return ESP_OK; +err: + if (list) { + free(list); + } + if (items) { + free(items); + } + return ret; +} + +esp_err_t dw_gdma_del_link_list(dw_gdma_link_list_handle_t list) +{ + ESP_RETURN_ON_FALSE(list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_LOGD(TAG, "del link list at %p", list); + free(list->items); + free(list); + return ESP_OK; +} + +esp_err_t dw_gdma_channel_use_link_list(dw_gdma_channel_handle_t chan, dw_gdma_link_list_handle_t list) +{ + ESP_RETURN_ON_FALSE(chan && list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(chan->src_transfer_type == DW_GDMA_BLOCK_TRANSFER_LIST || + chan->dst_transfer_type == DW_GDMA_BLOCK_TRANSFER_LIST, + ESP_ERR_INVALID_STATE, TAG, "invalid transfer type"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + + // set master port for the link list + dw_gdma_ll_channel_set_link_list_master_port(hal->dev, chan_id, DW_GDMA_LL_MASTER_PORT_MEMORY); + // set the link list head address + dw_gdma_ll_channel_set_link_list_head_addr(hal->dev, chan_id, (uint32_t)(list->items)); + return ESP_OK; +} + +dw_gdma_lli_handle_t dw_gdma_link_list_get_item(dw_gdma_link_list_handle_t list, int item_index) +{ + ESP_RETURN_ON_FALSE_ISR(list, NULL, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, NULL, TAG, "invalid item index"); + dw_gdma_link_list_item_t *lli = list->items_nc + item_index; + return lli; +} + +esp_err_t dw_gdma_channel_config_transfer(dw_gdma_channel_handle_t chan, const dw_gdma_block_transfer_config_t *config) +{ + ESP_RETURN_ON_FALSE(chan && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(chan->src_transfer_type != DW_GDMA_BLOCK_TRANSFER_LIST && + chan->dst_transfer_type != DW_GDMA_BLOCK_TRANSFER_LIST, + ESP_ERR_INVALID_STATE, TAG, "invalid transfer type"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + + // set memory address + dw_gdma_ll_channel_set_src_addr(hal->dev, chan_id, config->src.addr); + dw_gdma_ll_channel_set_dst_addr(hal->dev, chan_id, config->dst.addr); + // transfer size + dw_gdma_ll_channel_set_trans_block_size(hal->dev, chan_id, config->size); + // [Ctrl0] register + // set master port for the source and destination target + dw_gdma_ll_channel_set_src_master_port(hal->dev, chan_id, config->src.addr); + dw_gdma_ll_channel_set_dst_master_port(hal->dev, chan_id, config->dst.addr); + // transfer width + dw_gdma_ll_channel_set_src_trans_width(hal->dev, chan_id, config->src.width); + dw_gdma_ll_channel_set_dst_trans_width(hal->dev, chan_id, config->dst.width); + // set burst items + dw_gdma_ll_channel_set_src_burst_items(hal->dev, chan_id, config->src.burst_items); + dw_gdma_ll_channel_set_dst_burst_items(hal->dev, chan_id, config->dst.burst_items); + // set burst mode + dw_gdma_ll_channel_set_src_burst_mode(hal->dev, chan_id, config->src.burst_mode); + dw_gdma_ll_channel_set_dst_burst_mode(hal->dev, chan_id, config->dst.burst_mode); + // [Ctrl1] register + // set burst length + dw_gdma_ll_channel_set_src_burst_len(hal->dev, chan_id, config->src.burst_len); + dw_gdma_ll_channel_set_dst_burst_len(hal->dev, chan_id, config->dst.burst_len); + // whether to enable the peripheral status write back + dw_gdma_ll_channel_enable_src_periph_status_write_back(hal->dev, chan_id, config->src.flags.en_status_write_back); + dw_gdma_ll_channel_enable_dst_periph_status_write_back(hal->dev, chan_id, config->dst.flags.en_status_write_back); + + return ESP_OK; +} + +esp_err_t dw_gdma_channel_set_block_markers(dw_gdma_channel_handle_t chan, dw_gdma_block_markers_t markers) +{ + ESP_RETURN_ON_FALSE_ISR(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE_ISR(chan->src_transfer_type != DW_GDMA_BLOCK_TRANSFER_LIST && + chan->dst_transfer_type != DW_GDMA_BLOCK_TRANSFER_LIST, + ESP_ERR_INVALID_STATE, TAG, "invalid transfer type"); + dw_gdma_hal_context_t *hal = &chan->group->hal; + int chan_id = chan->chan_id; + + // [Ctrl1] register + // set the block markers + dw_gdma_ll_channel_set_block_markers(hal->dev, chan_id, markers.en_trans_done_intr, markers.is_last, markers.is_valid); + + return ESP_OK; +} + +esp_err_t dw_gdma_lli_config_transfer(dw_gdma_lli_handle_t lli, dw_gdma_block_transfer_config_t *config) +{ + ESP_RETURN_ON_FALSE(lli && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + + // set memory address + dw_gdma_ll_lli_set_src_addr(lli, config->src.addr); + dw_gdma_ll_lli_set_dst_addr(lli, config->dst.addr); + // transfer size + dw_gdma_ll_lli_set_trans_block_size(lli, config->size); + // [Ctrl0] register + // set master port for the source and destination target + dw_gdma_ll_lli_set_src_master_port(lli, config->src.addr); + dw_gdma_ll_lli_set_dst_master_port(lli, config->dst.addr); + // transfer width + dw_gdma_ll_lli_set_src_trans_width(lli, config->src.width); + dw_gdma_ll_lli_set_dst_trans_width(lli, config->dst.width); + // set burst items + dw_gdma_ll_lli_set_src_burst_items(lli, config->src.burst_items); + dw_gdma_ll_lli_set_dst_burst_items(lli, config->dst.burst_items); + // set burst mode + dw_gdma_ll_lli_set_src_burst_mode(lli, config->src.burst_mode); + dw_gdma_ll_lli_set_dst_burst_mode(lli, config->dst.burst_mode); + // [Ctrl1] register + // set burst length + dw_gdma_ll_lli_set_src_burst_len(lli, config->src.burst_len); + dw_gdma_ll_lli_set_dst_burst_len(lli, config->dst.burst_len); + // whether to enable the peripheral status write back + dw_gdma_ll_lli_enable_src_periph_status_write_back(lli, config->src.flags.en_status_write_back); + dw_gdma_ll_lli_enable_dst_periph_status_write_back(lli, config->dst.flags.en_status_write_back); + + return ESP_OK; +} + +esp_err_t dw_gdma_lli_set_block_markers(dw_gdma_lli_handle_t lli, dw_gdma_block_markers_t markers) +{ + ESP_RETURN_ON_FALSE_ISR(lli, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + + // [Ctrl1] register + // set the block markers + dw_gdma_ll_lli_set_block_markers(lli, markers.en_trans_done_intr, markers.is_last, markers.is_valid); + + return ESP_OK; +} + +void dw_gdma_channel_default_isr(void *args) +{ + dw_gdma_channel_t *chan = (dw_gdma_channel_t *)args; + dw_gdma_group_t *group = chan->group; + dw_gdma_hal_context_t *hal = &group->hal; + int chan_id = chan->chan_id; + bool need_yield = false; + // clear pending interrupt event + uint32_t intr_status = dw_gdma_ll_channel_get_intr_status(hal->dev, chan_id); + dw_gdma_ll_channel_clear_intr(hal->dev, chan_id, intr_status); + + // call user callbacks + if (intr_status & DW_GDMA_LL_CHANNEL_EVENT_SHADOWREG_OR_LLI_INVALID_ERR) { + if (chan->cbs.on_invalid_block) { + intptr_t invalid_lli_addr = dw_gdma_ll_channel_get_current_link_list_item_addr(hal->dev, chan_id); + dw_gdma_break_event_data_t edata = { + .invalid_lli = (dw_gdma_lli_handle_t)DW_GDMA_GET_NON_CACHE_ADDR(invalid_lli_addr), + }; + if (chan->cbs.on_invalid_block(chan, &edata, chan->user_data)) { + need_yield = true; + } + } + } + + if (intr_status & DW_GDMA_LL_CHANNEL_EVENT_BLOCK_TFR_DONE) { + if (chan->cbs.on_block_trans_done) { + dw_gdma_trans_done_event_data_t edata = {}; + if (chan->cbs.on_block_trans_done(chan, &edata, chan->user_data)) { + need_yield = true; + } + } + } + + if (intr_status & DW_GDMA_LL_CHANNEL_EVENT_DMA_TFR_DONE) { + if (chan->cbs.on_full_trans_done) { + dw_gdma_trans_done_event_data_t edata = {}; + if (chan->cbs.on_full_trans_done(chan, &edata, chan->user_data)) { + need_yield = true; + } + } + } + + if (need_yield) { + portYIELD_FROM_ISR(); + } +} + +static esp_err_t dw_gdma_install_channel_interrupt(dw_gdma_channel_t *chan) +{ + esp_err_t ret = ESP_OK; + dw_gdma_group_t *group = chan->group; + dw_gdma_hal_context_t *hal = &group->hal; + int chan_id = chan->chan_id; + // clear pending events + dw_gdma_ll_channel_enable_intr_propagation(hal->dev, chan_id, UINT32_MAX, false); + dw_gdma_ll_channel_clear_intr(hal->dev, chan_id, UINT32_MAX); + + // pre-alloc a interrupt handle, with handler disabled + // DW_GDMA multiple channels share the same interrupt source, so we use a shared interrupt handle + intr_handle_t intr = NULL; + int isr_flags = DW_GDMA_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED; + if (group->intr_priority) { + isr_flags |= 1 << (group->intr_priority); + } else { + isr_flags |= DW_GDMA_ALLOW_INTR_PRIORITY_MASK; + } + ret = esp_intr_alloc_intrstatus(ETS_DW_GDMA_INTR_SOURCE, isr_flags, + (uint32_t)dw_gdma_ll_get_intr_status_reg(hal->dev), DW_GDMA_LL_CHANNEL_EVENT_MASK(chan_id), + dw_gdma_channel_default_isr, chan, &intr); + ESP_RETURN_ON_ERROR(ret, TAG, "alloc interrupt failed"); + + ESP_LOGD(TAG, "install interrupt service for channel (%d,%d)", group->group_id, chan_id); + chan->intr = intr; + return ESP_OK; +} + +esp_err_t dw_gdma_channel_register_event_callbacks(dw_gdma_channel_handle_t chan, dw_gdma_event_callbacks_t *cbs, void *user_data) +{ + ESP_RETURN_ON_FALSE(chan && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + dw_gdma_group_t *group = chan->group; + dw_gdma_hal_context_t *hal = &group->hal; + int chan_id = chan->chan_id; + +#if CONFIG_DW_GDMA_ISR_IRAM_SAFE + if (cbs->on_block_trans_done) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_block_trans_done), ESP_ERR_INVALID_ARG, + TAG, "on_block_trans_done not in IRAM"); + } + if (cbs->on_full_trans_done) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_full_trans_done), ESP_ERR_INVALID_ARG, + TAG, "on_full_trans_done not in IRAM"); + } + if (cbs->on_invalid_block) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_invalid_block), ESP_ERR_INVALID_ARG, + TAG, "on_invalid_block not in IRAM"); + } + if (user_data) { + ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, + TAG, "user context not in internal RAM"); + } +#endif // CONFIG_DW_GDMA_ISR_IRAM_SAFE + + // lazy install interrupt service + if (!chan->intr) { + ESP_RETURN_ON_ERROR(dw_gdma_install_channel_interrupt(chan), TAG, "install interrupt service failed"); + } + + // enable the event to be able to trigger an interrupt + dw_gdma_ll_channel_enable_intr_propagation(hal->dev, chan_id, DW_GDMA_LL_CHANNEL_EVENT_BLOCK_TFR_DONE, cbs->on_block_trans_done != NULL); + dw_gdma_ll_channel_enable_intr_propagation(hal->dev, chan_id, DW_GDMA_LL_CHANNEL_EVENT_DMA_TFR_DONE, cbs->on_full_trans_done != NULL); + dw_gdma_ll_channel_enable_intr_propagation(hal->dev, chan_id, DW_GDMA_LL_CHANNEL_EVENT_SHADOWREG_OR_LLI_INVALID_ERR, cbs->on_invalid_block != NULL); + + chan->user_data = user_data; + memcpy(&chan->cbs, cbs, sizeof(dw_gdma_event_callbacks_t)); + + return ESP_OK; +} + +esp_err_t dw_gdma_channel_get_id(dw_gdma_channel_handle_t chan, int *channel_id) +{ + ESP_RETURN_ON_FALSE(chan && channel_id, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + *channel_id = chan->chan_id; + return ESP_OK; +} diff --git a/components/esp_hw_support/dma/esp_async_memcpy.c b/components/esp_hw_support/dma/esp_async_memcpy.c index 966ad2371c7..c57c92fa124 100644 --- a/components/esp_hw_support/dma/esp_async_memcpy.c +++ b/components/esp_hw_support/dma/esp_async_memcpy.c @@ -22,10 +22,11 @@ esp_err_t esp_async_memcpy(async_memcpy_handle_t asmcp, void *dst, void *src, si return asmcp->memcpy(asmcp, dst, src, n, cb_isr, cb_args); } -#if SOC_GDMA_SUPPORT_ETM +#if SOC_ETM_SUPPORTED esp_err_t esp_async_memcpy_new_etm_event(async_memcpy_handle_t asmcp, async_memcpy_etm_event_t event_type, esp_etm_event_handle_t *out_event) { ESP_RETURN_ON_FALSE(asmcp && out_event, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(asmcp->new_etm_event, ESP_ERR_NOT_SUPPORTED, TAG, "ETM is not supported"); return asmcp->new_etm_event(asmcp, event_type, out_event); } #endif diff --git a/components/esp_hw_support/dma/esp_async_memcpy_priv.h b/components/esp_hw_support/dma/esp_async_memcpy_priv.h index 2d9be6ce77b..bf64f83495f 100644 --- a/components/esp_hw_support/dma/esp_async_memcpy_priv.h +++ b/components/esp_hw_support/dma/esp_async_memcpy_priv.h @@ -33,10 +33,10 @@ typedef struct async_memcpy_context_t async_memcpy_context_t; struct async_memcpy_context_t { /// @brief Start a new async memcpy transaction esp_err_t (*memcpy)(async_memcpy_context_t *ctx, void *dst, void *src, size_t n, async_memcpy_isr_cb_t cb_isr, void *cb_args); -#if SOC_GDMA_SUPPORT_ETM +#if SOC_ETM_SUPPORTED /// @brief Create ETM event handle of specific event type esp_err_t (*new_etm_event)(async_memcpy_context_t *ctx, async_memcpy_etm_event_t event_type, esp_etm_event_handle_t *out_event); -#endif // SOC_GDMA_SUPPORT_ETM +#endif // SOC_ETM_SUPPORTED /// @brief Delete async memcpy driver context esp_err_t (*del)(async_memcpy_context_t *ctx); }; diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index feca5dfe53a..19cb718460e 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -213,9 +213,6 @@ esp_err_t gdma_new_ahb_channel(const gdma_channel_alloc_config_t *config, gdma_c }; return do_allocate_gdma_channel(&search_info, config, ret_chan); } - -esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan) -__attribute__((alias("gdma_new_ahb_channel"))); #endif // SOC_AHB_GDMA_SUPPORTED #if SOC_AXI_GDMA_SUPPORTED @@ -232,6 +229,14 @@ esp_err_t gdma_new_axi_channel(const gdma_channel_alloc_config_t *config, gdma_c } #endif // SOC_AXI_GDMA_SUPPORTED +#if SOC_AHB_GDMA_SUPPORTED +esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan) +__attribute__((alias("gdma_new_ahb_channel"))); +#elif SOC_AXI_GDMA_SUPPORTED +esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_channel_handle_t *ret_chan) +__attribute__((alias("gdma_new_axi_channel"))); +#endif + esp_err_t gdma_del_channel(gdma_channel_handle_t dma_chan) { ESP_RETURN_ON_FALSE(dma_chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); @@ -358,15 +363,15 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t ESP_RETURN_ON_FALSE((sram_alignment & (sram_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "invalid sram alignment: %zu", sram_alignment); - uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); + uint32_t ext_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); if (psram_alignment == 0) { // fall back to use the same size of the psram data cache line size - psram_alignment = data_cache_line_size; + psram_alignment = ext_mem_cache_line_size; } - if (psram_alignment > data_cache_line_size) { - ESP_RETURN_ON_FALSE(((psram_alignment % data_cache_line_size) == 0), ESP_ERR_INVALID_ARG, - TAG, "psram_alignment(%d) should be multiple of the data_cache_line_size(%"PRIu32")", - psram_alignment, data_cache_line_size); + if (psram_alignment > ext_mem_cache_line_size) { + ESP_RETURN_ON_FALSE(((psram_alignment % ext_mem_cache_line_size) == 0), ESP_ERR_INVALID_ARG, + TAG, "psram_alignment(%d) should be multiple of the ext_mem_cache_line_size(%"PRIu32")", + psram_alignment, ext_mem_cache_line_size); } // if the DMA can't access the PSRAM, this HAL function is no-op @@ -535,7 +540,7 @@ esp_err_t gdma_register_rx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_ // enable/disable GDMA interrupt events for RX channel portENTER_CRITICAL(&pair->spinlock); - gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_SUC_EOF, cbs->on_recv_eof != NULL); + gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_ERR_EOF, cbs->on_recv_eof != NULL); gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_DESC_ERROR, cbs->on_descr_err != NULL); gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_DONE, cbs->on_recv_done != NULL); portEXIT_CRITICAL(&pair->spinlock); @@ -799,39 +804,44 @@ void gdma_default_rx_isr(void *args) gdma_hal_context_t *hal = &group->hal; int pair_id = pair->pair_id; bool need_yield = false; - // clear pending interrupt event - uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX); + bool abnormal_eof = false; + bool normal_eof = false; + + // clear pending interrupt event first + // reading the raw interrupt status because we also want to know the EOF status, even if the EOF interrupt is not enabled + uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, true); gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, intr_status); - /* Call on_recv_done before eof callbacks to ensure a correct sequence */ - if ((intr_status & GDMA_LL_EVENT_RX_DONE) && rx_chan->cbs.on_recv_done) { - /* Here we don't return an event data in this callback. - * Because we can't get a determinant descriptor address - * that just finished processing by DMA controller. - * When the `rx_done` interrupt triggers, the finished descriptor should ideally - * stored in `in_desc_bf1` register, however, as it takes a while to - * get the `in_desc_bf1` in software, `in_desc_bf1` might have already refreshed, - * Therefore, instead of returning an unreliable descriptor, we choose to return nothing. - */ - need_yield |= rx_chan->cbs.on_recv_done(&rx_chan->base, NULL, rx_chan->user_data); - } + // prepare data for different events + uint32_t eof_addr = 0; + if (intr_status & GDMA_LL_EVENT_RX_SUC_EOF) { + eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, true); + normal_eof = true; + } + if (intr_status & GDMA_LL_EVENT_RX_ERR_EOF) { + eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, false); + abnormal_eof = true; + } + gdma_event_data_t edata = { + .rx_eof_desc_addr = eof_addr, + .flags = { + .abnormal_eof = abnormal_eof, + .normal_eof = normal_eof, + } + }; + if ((intr_status & GDMA_LL_EVENT_RX_DESC_ERROR) && rx_chan->cbs.on_descr_err) { + // in the future, we may add more information about the error descriptor into the event data, + // but for now, we just pass NULL need_yield |= rx_chan->cbs.on_descr_err(&rx_chan->base, NULL, rx_chan->user_data); } - if ((intr_status & GDMA_LL_EVENT_RX_SUC_EOF) && rx_chan->cbs.on_recv_eof) { - uint32_t eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, true); - gdma_event_data_t suc_eof_data = { - .rx_eof_desc_addr = eof_addr, - }; - need_yield |= rx_chan->cbs.on_recv_eof(&rx_chan->base, &suc_eof_data, rx_chan->user_data); + + // we expect the caller will do data process in the recv_done callback first, and handle the EOF event later + if ((intr_status & GDMA_LL_EVENT_RX_DONE) && rx_chan->cbs.on_recv_done) { + need_yield |= rx_chan->cbs.on_recv_done(&rx_chan->base, &edata, rx_chan->user_data); } - if ((intr_status & GDMA_LL_EVENT_RX_ERR_EOF) && rx_chan->cbs.on_recv_eof) { - uint32_t eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, false); - gdma_event_data_t err_eof_data = { - .rx_eof_desc_addr = eof_addr, - .flags.abnormal_eof = true, - }; - need_yield |= rx_chan->cbs.on_recv_eof(&rx_chan->base, &err_eof_data, rx_chan->user_data); + if ((intr_status & (GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_ERR_EOF)) && rx_chan->cbs.on_recv_eof) { + need_yield |= rx_chan->cbs.on_recv_eof(&rx_chan->base, &edata, rx_chan->user_data); } if (need_yield) { @@ -848,13 +858,14 @@ void gdma_default_tx_isr(void *args) int pair_id = pair->pair_id; bool need_yield = false; // clear pending interrupt event - uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX); + uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, false); gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, intr_status); if ((intr_status & GDMA_LL_EVENT_TX_EOF) && tx_chan->cbs.on_trans_eof) { uint32_t eof_addr = gdma_hal_get_eof_desc_addr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, true); gdma_event_data_t edata = { .tx_eof_desc_addr = eof_addr, + .flags.normal_eof = true, }; need_yield |= tx_chan->cbs.on_trans_eof(&tx_chan->base, &edata, tx_chan->user_data); } diff --git a/components/esp_hw_support/dma/gdma_etm.c b/components/esp_hw_support/dma/gdma_etm.c index f849a40e3cc..5749c1cc786 100644 --- a/components/esp_hw_support/dma/gdma_etm.c +++ b/components/esp_hw_support/dma/gdma_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,11 +40,9 @@ static esp_err_t gdma_del_etm_task(esp_etm_task_t *task) gdma_channel_t *dma_chan = gdma_task->chan; gdma_pair_t *pair = dma_chan->pair; gdma_group_t *group = pair->group; - if (dma_chan->direction == GDMA_CHANNEL_DIRECTION_RX) { - gdma_ll_rx_enable_etm_task(group->hal.dev, pair->pair_id, false); - } else { - gdma_ll_tx_enable_etm_task(group->hal.dev, pair->pair_id, false); - } + gdma_hal_context_t* hal = &group->hal; + + gdma_hal_enable_etm_task(hal, pair->pair_id, dma_chan->direction, false); free(gdma_task); dma_chan->flags.start_stop_by_etm = false; return ESP_OK; @@ -95,14 +93,14 @@ esp_err_t gdma_new_etm_task(gdma_channel_handle_t dma_chan, const gdma_etm_task_ gdma_pair_t *pair = dma_chan->pair; gdma_group_t *group = pair->group; + gdma_hal_context_t* hal = &group->hal; uint32_t task_id = 0; + gdma_hal_enable_etm_task(hal, pair->pair_id, dma_chan->direction, true); if (dma_chan->direction == GDMA_CHANNEL_DIRECTION_RX) { task_id = GDMA_LL_RX_ETM_TASK_TABLE(group->group_id, pair->pair_id, config->task_type); - gdma_ll_rx_enable_etm_task(group->hal.dev, pair->pair_id, true); } else { task_id = GDMA_LL_TX_ETM_TASK_TABLE(group->group_id, pair->pair_id, config->task_type); - gdma_ll_tx_enable_etm_task(group->hal.dev, pair->pair_id, true); } ESP_GOTO_ON_FALSE(task_id != 0, ESP_ERR_NOT_SUPPORTED, err, TAG, "not supported task type"); diff --git a/components/esp_hw_support/dma/linker.lf b/components/esp_hw_support/dma/linker.lf index 176d6b1021a..7dd8eeb8a14 100644 --- a/components/esp_hw_support/dma/linker.lf +++ b/components/esp_hw_support/dma/linker.lf @@ -67,3 +67,18 @@ entries: gdma_hal_axi: gdma_axi_hal_stop (noflash) gdma_hal_axi: gdma_axi_hal_append (noflash) gdma_hal_axi: gdma_axi_hal_reset (noflash) + +[mapping:dw_gdma_driver] +archive: libesp_hw_support.a +entries: + # performance optimization, always put the DW_GDMA default interrupt handler in IRAM + if SOC_DW_GDMA_SUPPORTED = y: + dw_gdma: dw_gdma_channel_default_isr (noflash) + + # put DW_GDMA control functions in IRAM + if DW_GDMA_CTRL_FUNC_IN_IRAM = y: + dw_gdma: dw_gdma_channel_continue (noflash) + + if DW_GDMA_SETTER_FUNC_IN_IRAM = y: + dw_gdma: dw_gdma_channel_set_block_markers (noflash) + dw_gdma: dw_gdma_lli_set_block_markers (noflash) diff --git a/components/esp_hw_support/include/dport_access.h b/components/esp_hw_support/include/dport_access.h index 6f8aeab2ed4..30bc9004b19 100644 --- a/components/esp_hw_support/include/dport_access.h +++ b/components/esp_hw_support/include/dport_access.h @@ -13,7 +13,7 @@ extern "C" { #endif -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND +#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND #define DPORT_STALL_OTHER_CPU_START() #define DPORT_STALL_OTHER_CPU_END() #else diff --git a/components/esp_hw_support/include/esp_async_memcpy.h b/components/esp_hw_support/include/esp_async_memcpy.h index 6932aff3fb0..033bb9ed917 100644 --- a/components/esp_hw_support/include/esp_async_memcpy.h +++ b/components/esp_hw_support/include/esp_async_memcpy.h @@ -159,7 +159,7 @@ esp_err_t esp_async_memcpy_uninstall(async_memcpy_handle_t mcp); */ esp_err_t esp_async_memcpy(async_memcpy_handle_t mcp, void *dst, void *src, size_t n, async_memcpy_isr_cb_t cb_isr, void *cb_args); -#if SOC_GDMA_SUPPORT_ETM +#if SOC_ETM_SUPPORTED /** * @brief Async memory copy specific events that supported by the ETM module */ @@ -182,7 +182,7 @@ typedef enum { * - ESP_FAIL: Get ETM event failed because of other error */ esp_err_t esp_async_memcpy_new_etm_event(async_memcpy_handle_t mcp, async_memcpy_etm_event_t event_type, esp_etm_event_handle_t *out_event); -#endif // SOC_GDMA_SUPPORT_ETM +#endif // SOC_ETM_SUPPORTED #ifdef __cplusplus } diff --git a/components/esp_hw_support/include/esp_chip_info.h b/components/esp_hw_support/include/esp_chip_info.h index a4509f5b0eb..3922c0aeb6a 100644 --- a/components/esp_hw_support/include/esp_chip_info.h +++ b/components/esp_hw_support/include/esp_chip_info.h @@ -28,6 +28,7 @@ typedef enum { CHIP_ESP32C6 = 13, //!< ESP32-C6 CHIP_ESP32H2 = 16, //!< ESP32-H2 CHIP_ESP32P4 = 18, //!< ESP32-P4 + CHIP_ESP32C5 = 19, //!< ESP32-C5 CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator } esp_chip_model_t; diff --git a/components/esp_hw_support/include/esp_cpu.h b/components/esp_hw_support/include/esp_cpu.h index 46ea42a2aef..e4e43236c5b 100644 --- a/components/esp_hw_support/include/esp_cpu.h +++ b/components/esp_hw_support/include/esp_cpu.h @@ -12,7 +12,7 @@ #include #include "soc/soc_caps.h" #ifdef __XTENSA__ -#include "xtensa/xtensa_api.h" +#include "xtensa_api.h" #include "xt_utils.h" #elif __riscv #include "riscv/rv_utils.h" @@ -482,9 +482,15 @@ esp_err_t esp_cpu_clear_breakpoint(int bp_num); * the CPU accesses (according to the trigger type) on a certain memory range. * * @note Overwrites previously set watchpoint with same watchpoint number. + * On RISC-V chips, this API uses method0(Exact matching) and method1(NAPOT matching) according to the + * riscv-debug-spec-0.13 specification for address matching. + * If the watch region size is 1byte, it uses exact matching (method 0). + * If the watch region size is larger than 1byte, it uses NAPOT matching (method 1). This mode requires + * the watching region start address to be aligned to the watching region size. + * * @param wp_num Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1] - * @param wp_addr Watchpoint's base address - * @param size Size of the region to watch. Must be one of 2^n, with n in [0..6]. + * @param wp_addr Watchpoint's base address, must be naturally aligned to the size of the region + * @param size Size of the region to watch. Must be one of 2^n and in the range of [1 ... SOC_CPU_WATCHPOINT_MAX_REGION_SIZE] * @param trigger Trigger type * @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise */ diff --git a/components/esp_hw_support/include/esp_memory_utils.h b/components/esp_hw_support/include/esp_memory_utils.h index dbee7464786..1e22dc4c679 100644 --- a/components/esp_hw_support/include/esp_memory_utils.h +++ b/components/esp_hw_support/include/esp_memory_utils.h @@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) { */ __attribute__((always_inline)) inline static bool esp_ptr_in_iram(const void *p) { -#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE +#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH); #else return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH); @@ -230,7 +230,7 @@ inline static bool esp_ptr_executable(const void *p) return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH) || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH) || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH) -#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE) +#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH) #endif #if SOC_RTC_FAST_MEM_SUPPORTED diff --git a/components/esp_hw_support/include/esp_private/dw_gdma.h b/components/esp_hw_support/include/esp_private/dw_gdma.h new file mode 100644 index 00000000000..14968015b54 --- /dev/null +++ b/components/esp_hw_support/include/esp_private/dw_gdma.h @@ -0,0 +1,405 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_err.h" +#include "hal/dw_gdma_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of DW_GDMA channel handle + */ +typedef struct dw_gdma_channel_t *dw_gdma_channel_handle_t; + +/** + * @brief Type of DW_GDMA link list handle + */ +typedef struct dw_gdma_link_list_t *dw_gdma_link_list_handle_t; + +/** + * @brief Type of DW_GDMA link list item handle + */ +typedef struct dw_gdma_link_list_item_t *dw_gdma_lli_handle_t; + +/** + * @brief A group of channel's static configurations + * + * @note By static, we mean these channel end configurations shouldn't be changed after the DMA channel is created. + */ +typedef struct { + dw_gdma_block_transfer_type_t block_transfer_type; /*!< Block transfer type */ + dw_gdma_role_t role; /*!< Role of the DMA channel end */ + dw_gdma_handshake_type_t handshake_type; /*!< Handshake type */ + uint8_t num_outstanding_requests; /*!< Number of R/W requests that the AXI master can issue to the slave before receiving a response. + Suggest value range: [1,16] */ + uint32_t status_fetch_addr; /*!< Address where to fetch the status of the peripheral */ +} dw_gdma_channel_static_config_t; + +/** + * @brief Configurations for allocating a DMA channel + */ +typedef struct { + dw_gdma_channel_static_config_t src; /*!< source end static configuration */ + dw_gdma_channel_static_config_t dst; /*!< destination end static configuration */ + dw_gdma_flow_controller_t flow_controller; /*!< Transfer flow controller */ + int chan_priority; /*!< DMA channel priority */ + int intr_priority; /*!< DMA interrupt priority, + if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3) */ +} dw_gdma_channel_alloc_config_t; + +/** + * @brief Create a DMA channel + * + * @param[in] config Channel allocation configuration + * @param[out] ret_chan Returned channel handle + * @return + * - ESP_OK: Create DMA channel successfully + * - ESP_ERR_INVALID_ARG: Create DMA channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA channel failed because out of memory + * - ESP_FAIL: Create DMA channel failed because of other error + */ +esp_err_t dw_gdma_new_channel(const dw_gdma_channel_alloc_config_t *config, dw_gdma_channel_handle_t *ret_chan); + +/** + * @brief Delete DMA channel + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Delete DMA channel successfully + * - ESP_ERR_INVALID_ARG: Delete DMA channel failed because of invalid argument + * - ESP_FAIL: Delete DMA channel failed because of other error + */ +esp_err_t dw_gdma_del_channel(dw_gdma_channel_handle_t chan); + +/** + * @brief Get the DMA channel ID + * + * @note This API breaks the encapsulation of DW_GDMA Channel Object. + * With the returned channel ID, you can even bypass all other driver API and access Low Level API directly. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[out] channel_id Returned channel ID + * @return + * - ESP_OK: Get DW_GDMA channel ID successfully + * - ESP_ERR_INVALID_ARG: Get DW_GDMA channel ID failed because of invalid argument + * - ESP_FAIL: Get DW_GDMA channel ID failed because of other error + */ +esp_err_t dw_gdma_channel_get_id(dw_gdma_channel_handle_t chan, int *channel_id); + +/** + * @brief A group of channel's dynamic configurations + * + * @note By dynamic, we mean these channel end configurations can be changed in each transfer. + */ +typedef struct { + uint32_t addr; /*!< Memory address */ + dw_gdma_transfer_width_t width; /*!< Transfer width */ + dw_gdma_burst_mode_t burst_mode; /*!< Burst mode */ + dw_gdma_burst_items_t burst_items; /*!< Number of data items that are contained in one burst transaction */ + uint8_t burst_len; /*!< Burst transaction length, if set to 0, the hardware will apply a possible value as burst length */ + struct { + uint32_t en_status_write_back: 1; /*!< Enable peripheral status write back */ + } flags; +} dw_gdma_channel_dynamic_config_t; + +/** + * @brief Channel block transfer configurations + */ +typedef struct { + dw_gdma_channel_dynamic_config_t src; /*!< source configuration */ + dw_gdma_channel_dynamic_config_t dst; /*!< destination configuration */ + size_t size; /*!< Transfer size */ +} dw_gdma_block_transfer_config_t; + +/** + * @brief Configure transfer parameters for a DMA channel + * + * @note This is an "all-in-one" function for set up the block transfer. + * @note This function can't work with Link-List transfer type. For Link-List transfer, please use `dw_gdma_lli_config_transfer` instead. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] config Block transfer configurations + * @return + * - ESP_OK: Configure DMA channel block transfer successfully + * - ESP_ERR_INVALID_ARG: Configure DMA channel block transfer failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Configure DMA channel block transfer failed because the channel has Link-List transfer type + * - ESP_FAIL: Configure DMA channel block transfer failed because of other error + */ +esp_err_t dw_gdma_channel_config_transfer(dw_gdma_channel_handle_t chan, const dw_gdma_block_transfer_config_t *config); + +/** + * @brief Enable or disable a DMA channel + * + * @note Before enabling a channel, you need to setup the channel transfer by either `dw_gdma_channel_config_transfer` or `dw_gdma_lli_config_transfer` + * @note When a DMA channel is disabled, the DMA engine will stop working. You need to reconfigure the channel before enabling it again. + * @note After all block transfers are completed, the DMA channel will be disabled automatically. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] en_or_dis True to enable, false to disable the DMA channel + * @return + * - ESP_OK: Enable or disable DMA channel successfully + * - ESP_ERR_INVALID_ARG: Enable or disable DMA channel failed because of invalid argument + * - ESP_FAIL: Enable or disable DMA channel failed because of other error + */ +esp_err_t dw_gdma_channel_enable_ctrl(dw_gdma_channel_handle_t chan, bool en_or_dis); + +/** + * @brief Suspend or resume a DMA channel + * + * @note When a DMA channel is suspended, the DMA engine will stop working gracefully and the channel's status will be saved. + * @note The channel will exit the suspend state automatically if it is disabled. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] enter_or_exit True to suspend, false to resume the DMA channel + * @return + * - ESP_OK: Suspend or resume DMA channel successfully + * - ESP_ERR_INVALID_ARG: Suspend or resume DMA channel failed because of invalid argument + * - ESP_FAIL: Suspend or resume DMA channel failed because of other error + */ +esp_err_t dw_gdma_channel_suspend_ctrl(dw_gdma_channel_handle_t chan, bool enter_or_exit); + +/** + * @brief Abort the DMA channel + * + * @note If the channel is aborted, it will be diabled immediately, which may cause AXI bus protocol violation. + * @note This function is recommended to only be used when the channel hangs. Recommend to try `dw_gdma_channel_enable_ctrl` first, then opt for aborting. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Abort DMA channel successfully + * - ESP_ERR_INVALID_ARG: Abort DMA channel failed because of invalid argument + * - ESP_FAIL: Abort DMA channel failed because of other error + */ +esp_err_t dw_gdma_channel_abort(dw_gdma_channel_handle_t chan); + +/** + * @brief Lock the DMA channel at specific transfer level + * + * @note When a DMA channel is locked, no other channels are granted control of the master bus for the duration specified by the lock level. + * @note Only lock the channel if you want to exclusive access to the master bus. + * @note Channel locking feature is only for M2M transfer. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] level Transfer level + * @return + * - ESP_OK: Lock DMA channel successfully + * - ESP_ERR_INVALID_ARG: Lock DMA channel failed because of invalid argument + * - ESP_FAIL: Lock DMA channel failed because of other error + */ +esp_err_t dw_gdma_channel_lock(dw_gdma_channel_handle_t chan, dw_gdma_lock_level_t level); + +/** + * @brief Unlock the DMA channel + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Unlock DMA channel successfully + * - ESP_ERR_INVALID_ARG: Unlock DMA channel failed because of invalid argument + * - ESP_FAIL: Unlock DMA channel failed because of other error + */ +esp_err_t dw_gdma_channel_unlock(dw_gdma_channel_handle_t chan); + +/** + * @brief Continue the temporarily stopped DMA transfer because of invalid block + * + * @note You should only call this API when the block becomes valid again, + * by calling `dw_gdma_lli_set_block_markers`/`dw_gdma_channel_set_block_markers` with `is_valid` set to true. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Continue DMA transfer successfully + * - ESP_ERR_INVALID_ARG: Continue DMA transfer failed because of invalid argument + * - ESP_FAIL: Continue DMA transfer failed because of other error + */ +esp_err_t dw_gdma_channel_continue(dw_gdma_channel_handle_t chan); + +/** + * @brief Type of DW_GDMA trans done event data + */ +typedef struct { +} dw_gdma_trans_done_event_data_t; + +/** + * @brief Type of DW_GDMA trans_done event callback + * @param chan GDMA channel handle, created from `dw_gdma_new_channel` + * @param event_data GDMA event data + * @param user_data User registered data from `dw_gdma_channel_register_event_callbacks` + * + * @return Whether a task switch is needed after the callback function returns, + * this is usually due to the callback wakes up some high priority task. + */ +typedef bool (*dw_gdma_trans_done_event_callback_t)(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data); + +/** + * @brief Type of DW_GDMA break event data + */ +typedef struct { + dw_gdma_lli_handle_t invalid_lli; /*!< Invalid link list item */ +} dw_gdma_break_event_data_t; + +/** + * @brief Type of DW_GDMA break event callback + * @param chan GDMA channel handle, created from `dw_gdma_new_channel` + * @param event_data GDMA event data + * @param user_data User registered data from `dw_gdma_channel_register_event_callbacks` + * + * @return Whether a task switch is needed after the callback function returns, + * this is usually due to the callback wakes up some high priority task. + */ +typedef bool (*dw_gdma_break_event_callback_t)(dw_gdma_channel_handle_t chan, const dw_gdma_break_event_data_t *event_data, void *user_data); + +/** + * @brief Group of supported DW_GDMA callbacks + * @note The callbacks are all running under ISR environment + */ +typedef struct { + dw_gdma_trans_done_event_callback_t on_block_trans_done; /*!< Invoked when a block transfer is completed */ + dw_gdma_trans_done_event_callback_t on_full_trans_done; /*!< Invoked when all block transfers are completed */ + dw_gdma_break_event_callback_t on_invalid_block; /*!< Invoked when an invalid block is detected */ +} dw_gdma_event_callbacks_t; + +/** + * @brief Set DW_GDMA event callbacks for a channel + * @note This API will lazy install the DW_GDMA interrupt service + * + * @param[in] chan DW_GDMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be passed to callback functions directly + * @return + * - ESP_OK: Set event callbacks successfully + * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + * - ESP_FAIL: Set event callbacks failed because of other error + */ +esp_err_t dw_gdma_channel_register_event_callbacks(dw_gdma_channel_handle_t chan, dw_gdma_event_callbacks_t *cbs, void *user_data); + +/** + * @brief DMA link list type + */ +typedef enum { + DW_GDMA_LINKED_LIST_TYPE_SINGLY, /*!< Singly linked list */ + DW_GDMA_LINKED_LIST_TYPE_CIRCULAR, /*!< Circular linked list */ +} dw_gdma_link_list_type_t; + +/** + * @brief DMA link list configurations + */ +typedef struct { + uint32_t num_items; //!< Number of link list items + dw_gdma_link_list_type_t link_type; //!< Link list type +} dw_gdma_link_list_config_t; + +/** + * @brief Create a DMA link list + * + * @param[in] config Link list configurations + * @param[out] ret_list Returned link list handle + * @return + * - ESP_OK: Create DMA link list successfully + * - ESP_ERR_INVALID_ARG: Create DMA link list failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA link list failed because out of memory + * - ESP_FAIL: Create DMA link list failed because of other error + */ +esp_err_t dw_gdma_new_link_list(const dw_gdma_link_list_config_t *config, dw_gdma_link_list_handle_t *ret_list); + +/** + * @brief Delete a DMA link list + * + * @param[in] list Link list handle, allocated by `dw_gdma_new_link_list` + * @return + * - ESP_OK: Delete DMA link list successfully + * - ESP_ERR_INVALID_ARG: Delete DMA link list failed because of invalid argument + * - ESP_FAIL: Delete DMA link list failed because of other error + */ +esp_err_t dw_gdma_del_link_list(dw_gdma_link_list_handle_t list); + +/** + * @brief Apply a link list to a DMA channel + * + * @note This function can only work with Link-List transfer type. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] list Link list handle, allocated by `dw_gdma_new_link_list` + * @return + * - ESP_OK: Apply link list to DMA channel successfully + * - ESP_ERR_INVALID_ARG: Apply link list to DMA channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Apply link list to DMA channel failed because the channel is not with Link-List transfer type + * - ESP_FAIL: Apply link list to DMA channel failed because of other error + */ +esp_err_t dw_gdma_channel_use_link_list(dw_gdma_channel_handle_t chan, dw_gdma_link_list_handle_t list); + +/** + * @brief A helper function to return an item from a given link list, by index + * + * @param[in] list Link list handle, allocated by `dw_gdma_new_link_list` + * @param[in] item_index Index of the item + * @return + * - NULL: Invalid argument + * - Others: Link list item handle + */ +dw_gdma_lli_handle_t dw_gdma_link_list_get_item(dw_gdma_link_list_handle_t list, int item_index); + +/** + * @brief Configure transfer parameters for a DMA link list item + * + * @note This is an "all-in-one" function for set up the link list item. + * @note This function can only work with Link-List transfer type. For other transfer types, please use `dw_gdma_channel_config_transfer` instead. + * + * @param[in] lli Link list item + * @param[in] config Block transfer configurations + * @return + * - ESP_OK: Configure link list item block transfer successfully + * - ESP_ERR_INVALID_ARG: Configure link list item block transfer failed because of invalid argument + * - ESP_FAIL: Configure link list item block transfer failed because of other error + */ +esp_err_t dw_gdma_lli_config_transfer(dw_gdma_lli_handle_t lli, dw_gdma_block_transfer_config_t *config); + +/** + * @brief Markers of a DW_GDMA block + */ +typedef struct { + uint32_t is_last: 1; /*!< Set if this block is the last one */ + uint32_t is_valid: 1; /*!< Set if this block is valid */ + uint32_t en_trans_done_intr: 1; /*!< Set if to enable the transfer done interrupt for this block */ +} dw_gdma_block_markers_t; + +/** + * @brief Set block markers for a DMA channel + * + * @note This function doesn't work for Link-List transfer type. For Link-List transfer, please use `dw_gdma_lli_set_block_markers` instead. + * @note Setting the markers should always be the last step of configuring a block transfer, before enabling/continuing the channel. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] markers Block markers + * @return + * - ESP_OK: Set block markers successfully + * - ESP_ERR_INVALID_ARG: Set block markers failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Set block markers failed because the channel has Link-List transfer type + * - ESP_FAIL: Set block markers failed because of other error + */ +esp_err_t dw_gdma_channel_set_block_markers(dw_gdma_channel_handle_t chan, dw_gdma_block_markers_t markers); + +/** + * @brief Set block markers for a DMA link list item + * + * @note Setting the markers should always be the last step of configuring a block transfer, before enabling/continuing the channel. + * + * @param[in] lli Link list item + * @param[in] markers Block markers + * @return + * - ESP_OK: Set block markers successfully + * - ESP_ERR_INVALID_ARG: Set block markers failed because of invalid argument + * - ESP_FAIL: Set block markers failed because of other error + */ +esp_err_t dw_gdma_lli_set_block_markers(dw_gdma_lli_handle_t lli, dw_gdma_block_markers_t markers); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/esp_private/esp_ldo.h b/components/esp_hw_support/include/esp_private/esp_ldo.h new file mode 100644 index 00000000000..3736eb0d708 --- /dev/null +++ b/components/esp_hw_support/include/esp_private/esp_ldo.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP_LDO_ID_1 0 ///< See datasheet `VFB/VO1` +#define ESP_LDO_ID_2 1 ///< See datasheet `VFB/VO2` +#define ESP_LDO_ID_3 2 ///< See datasheet `VFB/VO3` +#define ESP_LDO_ID_4 3 ///< See datasheet `VFB/VO4` + +/** + * @brief Type of LDO unit handle + */ +typedef struct ldo_unit_ctx_t *esp_ldo_unit_handle_t; + +/** + * @brief LDO unit configurations + */ +typedef struct { + int voltage_mv; ///< LDO output voltage in mV +} esp_ldo_unit_cfg_t; + +/** + * @brief LDO driver initial configurations + */ +typedef struct { + int unit_id; ///< LDO unit + esp_ldo_unit_cfg_t cfg; ///< LDO unit configuration + struct { + uint32_t enable_unit: 1; ///< Enable the LDO unit after it's initialised + uint32_t shared_ldo: 1; ///< Mark this LDO unit as shared + } flags; ///< LDO unit flags +} esp_ldo_unit_init_cfg_t; + +/** + * @Brief Init a LDO during early stage + * + * @note This API is only for early stage usage + * + * @param[in] unit_id LDO unit ID + * @param[in] cfg LDO unit configuration + * + * @return LDO unit handle + */ +esp_ldo_unit_handle_t esp_ldo_init_unit_early(const esp_ldo_unit_init_cfg_t *init_config); + +/** + * @Brief Init a LDO + * + * @param[in] init_config LDO initial configurations + * @param[out] ret_unit LDO unit handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_NOT_FOUND: LDO unit is in use already + */ +esp_err_t esp_ldo_init_unit(const esp_ldo_unit_init_cfg_t *init_config, esp_ldo_unit_handle_t *ret_unit); + +/** + * @Brief Enable a LDO + * + * @param[in] unit LDO unit handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_INVALID_STATE: LDO is enabled already + */ +esp_err_t esp_ldo_enable_unit(esp_ldo_unit_handle_t unit); + +/** + * @Brief Disable a LDO + * + * @param[in] unit LDO unit handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_INVALID_STATE: LDO is disabled already + */ +esp_err_t esp_ldo_disable_unit(esp_ldo_unit_handle_t unit); + +/** + * @Brief Deinit a LDO + * + * @param[in] unit LDO unit handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_INVALID_STATE: LDO is still enabled + */ +esp_err_t esp_ldo_deinit_unit(esp_ldo_unit_handle_t unit); + +/** + * Dump LDO usages + * + * @note This API shall not be called from an ISR. + * @note This API does not guarantee thread safety + * + * @param stream stream to print information to; use stdout or stderr to print + * to the console; use fmemopen/open_memstream to print to a + * string buffer. + * @return + * - ESP_OK + */ +esp_err_t esp_ldo_usage_dump(FILE* stream); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/esp_private/esp_modem_clock.h b/components/esp_hw_support/include/esp_private/esp_modem_clock.h index 1aae8638e84..a09d450ac37 100644 --- a/components/esp_hw_support/include/esp_private/esp_modem_clock.h +++ b/components/esp_hw_support/include/esp_private/esp_modem_clock.h @@ -70,15 +70,6 @@ void modem_clock_module_disable(periph_module_t module); */ void modem_clock_module_mac_reset(periph_module_t module); -/** - * @brief Initialize the clock gating control signal of each clock domain of the modem - * - * This is a global modem clock gating signal initialization interface, which is - * only configured during system initialization, and each modem module cannot - * use this interface. - */ -void modem_clock_domain_pmu_state_icg_map_init(void); - #if SOC_PMU_SUPPORTED /** * @brief Enable modem clock domain clock gate to gate it's output diff --git a/components/esp_hw_support/include/esp_private/esp_pau.h b/components/esp_hw_support/include/esp_private/esp_pau.h index db6b059d271..7fdbaaa98d7 100644 --- a/components/esp_hw_support/include/esp_private/esp_pau.h +++ b/components/esp_hw_support/include/esp_private/esp_pau.h @@ -43,7 +43,7 @@ void pau_regdma_trigger_modem_link_backup(void); void pau_regdma_trigger_modem_link_restore(void); #endif -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA /** * @brief Set the address of system REGDMA Link in active state * @param link_addr linked lists address diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 3420e9afdf9..1d8d2c309bf 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -291,6 +291,11 @@ void pmu_init(void); */ void pmu_sleep_enable_hp_sleep_sysclk(bool enable); +/** + * Get the time overhead used by regdma to work on the retention link during the hardware wake-up process + * @return regdma time cost during hardware wake-up stage in microseconds + */ +uint32_t pmu_sleep_get_wakup_retention_cost(void); #endif //#if SOC_PMU_SUPPORTED diff --git a/components/esp_hw_support/include/esp_private/gdma.h b/components/esp_hw_support/include/esp_private/gdma.h index 460309580c5..fc04a92a51d 100644 --- a/components/esp_hw_support/include/esp_private/gdma.h +++ b/components/esp_hw_support/include/esp_private/gdma.h @@ -55,16 +55,13 @@ typedef struct { */ typedef struct { union { - intptr_t rx_eof_desc_addr; /*!< EOF descriptor address of RX channel */ - intptr_t tx_eof_desc_addr; /*!< EOF descriptor address of TX channel */ + intptr_t rx_eof_desc_addr; /*!< EOF descriptor address of RX channel (only valid for EOF event) */ + intptr_t tx_eof_desc_addr; /*!< EOF descriptor address of TX channel (only valid for EOF event) */ }; struct { - uint32_t abnormal_eof: 1; /*!< 0: normal/success EOF; - * 1: abnormal/error EOF, - * it doesn't mean GDMA goes into an error condition, - * but the other peripheral goes into an abnormal state. - * For GDMA, it's still a valid EOF - */ + uint32_t abnormal_eof: 1; /*!< If set, means the current DMA block has an abnormal/error EOF flag being set. + It doesn't mean GDMA goes into an error condition, but indicates peripheral (e.g. UHCI) goes into an abnormal state */ + uint32_t normal_eof: 1; /*!< If set, means the current DMA block has a normal/successful EOF flag being set */ } flags; } gdma_event_data_t; diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h index 7edf69be069..620b03654f3 100644 --- a/components/esp_hw_support/include/esp_private/rtc_clk.h +++ b/components/esp_hw_support/include/esp_private/rtc_clk.h @@ -7,6 +7,8 @@ #pragma once #include +#include +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -44,6 +46,27 @@ void rtc_clk_bbpll_add_consumer(void); */ void rtc_clk_bbpll_remove_consumer(void); +#if SOC_CLK_MPLL_SUPPORTED +//------------------------------------MPLL-------------------------------------// +/** + * @brief Enable MPLL + */ +void rtc_clk_mpll_enable(void); + +/** + * @brief Disable MPLL + */ +void rtc_clk_mpll_disable(void); + +/** + * @brief Configure MPLL + * + * @param[in] xtal_freq XTAL frequency + * @param[in] mpll_freq MPLL frequency + */ +void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq); +#endif //#if SOC_CLK_MPLL_SUPPORTED + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/include/esp_private/sleep_console.h b/components/esp_hw_support/include/esp_private/sleep_console.h new file mode 100644 index 00000000000..612c51692cf --- /dev/null +++ b/components/esp_hw_support/include/esp_private/sleep_console.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_USB_SERIAL_JTAG_SUPPORTED +typedef struct { + bool usj_clock_enabled; + bool usj_pad_enabled; +} sleep_console_usj_enable_state_t; + +/** + * @brief Disable usb-serial-jtag pad during light sleep to avoid current leakage and + * backup the enable state before light sleep + */ +void sleep_console_usj_pad_backup_and_disable(void); + +/** + * @brief Restore initial usb-serial-jtag pad enable state when wakeup from light sleep + */ +void sleep_console_usj_pad_restore(void); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/esp_private/sleep_modem.h b/components/esp_hw_support/include/esp_private/sleep_modem.h index fe8e3ea2205..7922c24fc8b 100644 --- a/components/esp_hw_support/include/esp_private/sleep_modem.h +++ b/components/esp_hw_support/include/esp_private/sleep_modem.h @@ -9,6 +9,7 @@ #include #include "sdkconfig.h" #include "esp_err.h" +#include "esp_sleep.h" #ifdef __cplusplus extern "C" { @@ -40,6 +41,42 @@ void mac_bb_power_up_cb_execute(void); #endif // CONFIG_MAC_BB_PD +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD +/** + * @brief Register sleep prepare callback for Bluetooth/IEEE802154 MAC and baseband + * + * @param pd_cb function to call when power down + * @param pu_cb function to call when power up + */ +void sleep_modem_register_mac_bb_module_prepare_callback(mac_bb_power_down_cb_t pd_cb, + mac_bb_power_up_cb_t pu_cb); + +/** + * @brief Unregister sleep prepare callback for Bluetooth/IEEE802154 MAC and baseband + * + * @param pd_cb function to call when power down + * @param pu_cb function to call when power up + */ +void sleep_modem_unregister_mac_bb_module_prepare_callback(mac_bb_power_down_cb_t pd_cb, + mac_bb_power_up_cb_t pu_cb); + +/** + * @brief MAC and baseband power up operation + * + * In light sleep mode, execute IEEE802154/Bluetooth module MAC and baseband + * power down and backup prepare operations. + */ +void sleep_modem_mac_bb_power_down_prepare(void); + +/** + * @brief MAC and baseband power up operation + * + * In light sleep mode, execute IEEE802154/Bluetooth module MAC and baseband + * power up and restore prepare operations. + */ +void sleep_modem_mac_bb_power_up_prepare(void); +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + #if SOC_PM_SUPPORT_PMU_MODEM_STATE /** diff --git a/components/esp_hw_support/include/esp_private/sleep_retention.h b/components/esp_hw_support/include/esp_private/sleep_retention.h index e64a95a9c04..fd9a6220722 100644 --- a/components/esp_hw_support/include/esp_private/sleep_retention.h +++ b/components/esp_hw_support/include/esp_private/sleep_retention.h @@ -108,8 +108,6 @@ void sleep_retention_entries_get(sleep_retention_entries_t *entries); * or false for restore to register from memory */ void sleep_retention_do_extra_retention(bool backup_or_restore); - -void sleep_retention_module_deinit(void); #endif /** @@ -124,7 +122,7 @@ void sleep_retention_module_deinit(void); */ uint32_t sleep_retention_get_modules(void); -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA /** * @brief Software trigger REGDMA to do system linked list retention * diff --git a/components/driver/include/esp_private/spi_common_internal.h b/components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h similarity index 65% rename from components/driver/include/esp_private/spi_common_internal.h rename to components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h index 92f4a0e8992..cc86465590a 100644 --- a/components/driver/include/esp_private/spi_common_internal.h +++ b/components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h @@ -1,44 +1,27 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - -// Internal header, don't use it in the user code - #pragma once -#include -#include "driver/spi_common.h" -#include "freertos/FreeRTOS.h" -#include "hal/spi_types.h" -#include "hal/dma_types.h" -#include "soc/gdma_channel.h" -#include "esp_pm.h" -#if SOC_GDMA_SUPPORTED -#include "esp_private/gdma.h" -#endif +#include +#include "soc/soc_caps.h" +#include "hal/spi_types.h" +#include "esp_private/periph_ctrl.h" +#include "freertos/FreeRTOS.h" #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - -#ifdef CONFIG_SPI_MASTER_ISR_IN_IRAM -#define SPI_MASTER_ISR_ATTR IRAM_ATTR +#if !SOC_RCC_IS_INDEPENDENT +#define SPI_COMMON_RCC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC() #else -#define SPI_MASTER_ISR_ATTR +#define SPI_COMMON_RCC_CLOCK_ATOMIC() #endif -#ifdef CONFIG_SPI_MASTER_IN_IRAM -#define SPI_MASTER_ATTR IRAM_ATTR -#else -#define SPI_MASTER_ATTR -#endif - - #define BUS_LOCK_DEBUG 0 #if BUS_LOCK_DEBUG @@ -47,15 +30,6 @@ extern "C" #define BUS_LOCK_DEBUG_EXECUTE_CHECK(x) #endif -#if SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AHB -#define DMA_DESC_MEM_ALIGN_SIZE 4 -#define SPI_GDMA_NEW_CHANNEL gdma_new_ahb_channel -typedef dma_descriptor_align4_t spi_dma_desc_t; -#else -#define DMA_DESC_MEM_ALIGN_SIZE 8 -#define SPI_GDMA_NEW_CHANNEL gdma_new_axi_channel -typedef dma_descriptor_align8_t spi_dma_desc_t; -#endif struct spi_bus_lock_t; struct spi_bus_lock_dev_t; @@ -63,32 +37,9 @@ struct spi_bus_lock_dev_t; typedef struct spi_bus_lock_t* spi_bus_lock_handle_t; /// Handle to lock of one of the device on an SPI bus typedef struct spi_bus_lock_dev_t* spi_bus_lock_dev_handle_t; - /// Background operation control function typedef void (*bg_ctrl_func_t)(void*); -/// Attributes of an SPI bus -typedef struct { - spi_bus_config_t bus_cfg; ///< Config used to initialize the bus - uint32_t flags; ///< Flags (attributes) of the bus - int max_transfer_sz; ///< Maximum length of bytes available to send - bool dma_enabled; ///< To enable DMA or not - uint16_t internal_mem_align_size; ///< Buffer align byte requirement for internal memory - int tx_dma_chan; ///< TX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan are same - int rx_dma_chan; ///< RX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan are same - int dma_desc_num; ///< DMA descriptor number of dmadesc_tx or dmadesc_rx. - spi_dma_desc_t *dmadesc_tx; ///< DMA descriptor array for TX - spi_dma_desc_t *dmadesc_rx; ///< DMA descriptor array for RX - spi_bus_lock_handle_t lock; -#ifdef CONFIG_PM_ENABLE - esp_pm_lock_handle_t pm_lock; ///< Power management lock -#endif -} spi_bus_attr_t; - -/// Destructor called when a bus is deinitialized. -typedef esp_err_t (*spi_destroy_func_t)(void*); - - /** * @brief Try to claim a SPI peripheral * @@ -119,223 +70,6 @@ bool spicommon_periph_in_use(spi_host_device_t host); */ bool spicommon_periph_free(spi_host_device_t host); -/** - * @brief Alloc DMA for SPI - * - * @param host_id SPI host ID - * @param dma_chan DMA channel to be used - * @param[out] out_actual_tx_dma_chan Actual TX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) - * @param[out] out_actual_rx_dma_chan Actual RX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) - * - * @return - * - ESP_OK: On success - * - ESP_ERR_NO_MEM: No enough memory - * - ESP_ERR_NOT_FOUND: There is no available DMA channel - */ -esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan); - -/** - * @brief Free DMA for SPI - * - * @param host_id SPI host ID - * - * @return - * - ESP_OK: On success - */ -esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id); - -#if SOC_GDMA_SUPPORTED -/** - * @brief Get SPI GDMA Handle for GMDA Supported Chip - * - * @param host_id SPI host ID - * @param gdma_handle GDMA Handle to Return - * @param gdma_direction GDMA Channel Direction in Enum - * - GDMA_CHANNEL_DIRECTION_TX - * - GDMA_CHANNEL_DIRECTION_RX - * - * @return - * - ESP_OK: On success - */ -esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction); -#endif - -/** - * @brief Connect a SPI peripheral to GPIO pins - * - * This routine is used to connect a SPI peripheral to the IO-pads and DMA channel given in - * the arguments. Depending on the IO-pads requested, the routing is done either using the - * IO_mux or using the GPIO matrix. - * - * @param host SPI peripheral to be routed - * @param bus_config Pointer to a spi_bus_config struct detailing the GPIO pins - * @param flags Combination of SPICOMMON_BUSFLAG_* flags, set to ensure the pins set are capable with some functions: - * - ``SPICOMMON_BUSFLAG_MASTER``: Initialize I/O in master mode - * - ``SPICOMMON_BUSFLAG_SLAVE``: Initialize I/O in slave mode - * - ``SPICOMMON_BUSFLAG_IOMUX_PINS``: Pins set should match the iomux pins of the controller. - * - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: - * Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capability according to the mode. - * - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so that DIO mode is capable. - * - ``SPICOMMON_BUSFLAG_WPHD`` Make sure WP and HD are set to valid output GPIOs. - * - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``. - * - ``SPICOMMON_BUSFLAG_IO4_IO7``: Make sure spi data4 ~ spi data7 are set to valid output GPIOs. - * - ``SPICOMMON_BUSFLAG_OCTAL``: Combination of ``SPICOMMON_BUSFLAG_QUAL`` and ``SPICOMMON_BUSFLAG_IO4_IO7``. - * @param[out] flags_o A SPICOMMON_BUSFLAG_* flag combination of bus abilities will be written to this address. - * Leave to NULL if not needed. - * - ``SPICOMMON_BUSFLAG_IOMUX_PINS``: The bus is connected to iomux pins. - * - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: The bus has - * CLK/MISO/MOSI connected. - * - ``SPICOMMON_BUSFLAG_DUAL``: The bus is capable with DIO mode. - * - ``SPICOMMON_BUSFLAG_WPHD`` The bus has WP and HD connected. - * - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``. - * - ``SPICOMMON_BUSFLAG_IO4_IO7``: The bus has spi data4 ~ spi data7 connected. - * - ``SPICOMMON_BUSFLAG_OCTAL``: Combination of ``SPICOMMON_BUSFLAG_QUAL`` and ``SPICOMMON_BUSFLAG_IO4_IO7``. - * @return - * - ESP_ERR_INVALID_ARG if parameter is invalid - * - ESP_OK on success - */ -esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, uint32_t flags, uint32_t *flags_o); - -/** - * @brief Free the IO used by a SPI peripheral - * - * @param bus_cfg Bus config struct which defines which pins to be used. - * - * @return - * - ESP_ERR_INVALID_ARG if parameter is invalid - * - ESP_OK on success - */ -esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg); - -/** - * @brief Initialize a Chip Select pin for a specific SPI peripheral - * - * @param host SPI peripheral - * @param cs_io_num GPIO pin to route - * @param cs_num CS id to route - * @param force_gpio_matrix If true, CS will always be routed through the GPIO matrix. If false, - * if the GPIO number allows it, the routing will happen through the IO_mux. - */ -void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix); - -/** - * @brief Free a chip select line - * - * @param cs_gpio_num CS gpio num to free - */ -void spicommon_cs_free_io(int cs_gpio_num); - -/** - * @brief Check whether all pins used by a host are through IOMUX. - * - * @param host SPI peripheral - * - * @return false if any pins are through the GPIO matrix, otherwise true. - */ -bool spicommon_bus_using_iomux(spi_host_device_t host); - -/** - * @brief Get the IRQ source for a specific SPI host - * - * @param host The SPI host - * - * @return The hosts IRQ source - */ -int spicommon_irqsource_for_host(spi_host_device_t host); - -/** - * @brief Get the IRQ source for a specific SPI DMA - * - * @param host The SPI host - * - * @return The hosts IRQ source - */ -int spicommon_irqdma_source_for_host(spi_host_device_t host); - -/** - * Callback, to be called when a DMA engine reset is completed -*/ -typedef void(*dmaworkaround_cb_t)(void *arg); - -#if CONFIG_IDF_TARGET_ESP32 -//This workaround is only for esp32 -/** - * @brief Request a reset for a certain DMA channel - * - * @note In some (well-defined) cases in the ESP32 (at least rev v.0 and v.1), a SPI DMA channel will get confused. This can be remedied - * by resetting the SPI DMA hardware in case this happens. Unfortunately, the reset knob used for thsi will reset _both_ DMA channels, and - * as such can only done safely when both DMA channels are idle. These functions coordinate this. - * - * Essentially, when a reset is needed, a driver can request this using spicommon_dmaworkaround_req_reset. This is supposed to be called - * with an user-supplied function as an argument. If both DMA channels are idle, this call will reset the DMA subsystem and return true. - * If the other DMA channel is still busy, it will return false; as soon as the other DMA channel is done, however, it will reset the - * DMA subsystem and call the callback. The callback is then supposed to be used to continue the SPI drivers activity. - * - * @param dmachan DMA channel associated with the SPI host that needs a reset - * @param cb Callback to call in case DMA channel cannot be reset immediately - * @param arg Argument to the callback - * - * @return True when a DMA reset could be executed immediately. False when it could not; in this - * case the callback will be called with the specified argument when the logic can execute - * a reset, after that reset. - */ -bool spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg); - - -/** - * @brief Check if a DMA reset is requested but has not completed yet - * - * @return True when a DMA reset is requested but hasn't completed yet. False otherwise. - */ -bool spicommon_dmaworkaround_reset_in_progress(void); - - -/** - * @brief Mark a DMA channel as idle. - * - * A call to this function tells the workaround logic that this channel will - * not be affected by a global SPI DMA reset. - */ -void spicommon_dmaworkaround_idle(int dmachan); - -/** - * @brief Mark a DMA channel as active. - * - * A call to this function tells the workaround logic that this channel will - * be affected by a global SPI DMA reset, and a reset like that should not be attempted. - */ -void spicommon_dmaworkaround_transfer_active(int dmachan); -#endif //#if CONFIG_IDF_TARGET_ESP32 - -/******************************************************************************* - * Bus attributes - ******************************************************************************/ -/** - * @brief Set bus lock for the main bus, called by startup code. - * - * @param lock The lock to be used by the main SPI bus. - */ -void spi_bus_main_set_lock(spi_bus_lock_handle_t lock); - -/** - * @brief Get the attributes of a specified SPI bus. - * - * @param host_id The specified host to get attribute - * @return (Const) Pointer to the attributes - */ -const spi_bus_attr_t* spi_bus_get_attr(spi_host_device_t host_id); - -/** - * @brief Register a function to a initialized bus to make it called when deinitializing the bus. - * - * @param host_id The SPI bus to register the destructor. - * @param f Destructor to register - * @param arg The argument to call the destructor - * @return Always ESP_OK. - */ -esp_err_t spi_bus_register_destroy_func(spi_host_device_t host_id, - spi_destroy_func_t f, void *arg); - /******************************************************************************* * SPI Bus Lock for arbitration among SPI master (intr, polling) trans, SPI flash operations and * flash/psram cache access. @@ -760,13 +494,6 @@ bool spi_bus_lock_bg_req_exist(spi_bus_lock_handle_t lock); /// The lock for the main bus extern const spi_bus_lock_handle_t g_main_spi_bus_lock; -/** - * @brief Initialize the main SPI bus, called during chip startup. - * - * @return always ESP_OK - */ -esp_err_t spi_bus_lock_init_main_bus(void); - /// The lock for the main flash device extern const spi_bus_lock_dev_handle_t g_spi_lock_main_flash_dev; @@ -779,7 +506,6 @@ extern const spi_bus_lock_dev_handle_t g_spi_lock_main_flash_dev; */ esp_err_t spi_bus_lock_init_main_dev(void); - #ifdef __cplusplus } #endif diff --git a/components/driver/include/esp_private/uart_private.h b/components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h similarity index 100% rename from components/driver/include/esp_private/uart_private.h rename to components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h index bb5db22e7de..29c2af96d8c 100644 --- a/components/esp_hw_support/include/esp_sleep.h +++ b/components/esp_hw_support/include/esp_sleep.h @@ -267,6 +267,10 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level); * the pins during sleep. HOLD feature will be acted on the pin internally * before the system entering sleep, and this can further reduce power consumption. * + * @note Call this func will reset the previous ext1 configuration. + * + * @note This function will be deprecated in release/v6.0. Please switch to use `esp_sleep_enable_ext1_wakeup_io` and `esp_sleep_disable_ext1_wakeup_io` + * * @param io_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs * which have RTC functionality can be used in this bit map. * For different SoCs, the related GPIOs are: @@ -284,11 +288,80 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level); * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high * @return * - ESP_OK on success - * - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO, + * - ESP_ERR_INVALID_ARG if io_mask is zero,, * or mode is invalid */ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t io_mask, esp_sleep_ext1_wakeup_mode_t level_mode); +/** + * @brief Enable ext1 wakeup pins with IO masks. + * + * This will append selected IOs to the wakeup IOs, it will not reset previously enabled IOs. + * To reset specific previously enabled IOs, call esp_sleep_disable_ext1_wakeup_io with the io_mask. + * To reset all the enabled IOs, call esp_sleep_disable_ext1_wakeup_io(0). + * + * This function uses external wakeup feature of RTC controller. + * It will work even if RTC peripherals are shut down during sleep. + * + * This feature can monitor any number of pins which are in RTC IOs. + * Once selected pins go into the state given by level_mode argument, + * the chip will be woken up. + * + * @note This function does not modify pin configuration. The pins are + * configured in esp_deep_sleep_start/esp_light_sleep_start, + * immediately before entering sleep mode. + * + * @note Internal pullups and pulldowns don't work when RTC peripherals are + * shut down. In this case, external resistors need to be added. + * Alternatively, RTC peripherals (and pullups/pulldowns) may be + * kept enabled using esp_sleep_pd_config function. If we turn off the + * ``RTC_PERIPH`` domain or certain chips lack the ``RTC_PERIPH`` domain, + * we will use the HOLD feature to maintain the pull-up and pull-down on + * the pins during sleep. HOLD feature will be acted on the pin internally + * before the system entering sleep, and this can further reduce power consumption. + * + * @param io_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs + * which have RTC functionality can be used in this bit map. + * For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39 + * - ESP32-S2: 0-21 + * - ESP32-S3: 0-21 + * - ESP32-C6: 0-7 + * - ESP32-H2: 7-14 + * @param level_mode Select logic function used to determine wakeup condition: + * When target chip is ESP32: + * - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low + * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high + * When target chip is ESP32-S2, ESP32-S3, ESP32-C6 or ESP32-H2: + * - ESP_EXT1_WAKEUP_ANY_LOW: wake up when any of the selected GPIOs is low + * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO, + * or mode is invalid + * - ESP_ERR_NOT_ALLOWED when wakeup level will become different between + * ext1 IOs if !SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + */ +esp_err_t esp_sleep_enable_ext1_wakeup_io(uint64_t io_mask, esp_sleep_ext1_wakeup_mode_t level_mode); + +/** + * @brief Disable ext1 wakeup pins with IO masks. This will remove selected IOs from the wakeup IOs. + * @param io_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs + * which have RTC functionality can be used in this bit map. + * If value is zero, this func will remove all previous ext1 configuration. + * For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39 + * - ESP32-S2: 0-21 + * - ESP32-S3: 0-21 + * - ESP32-C6: 0-7 + * - ESP32-H2: 7-14 + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO. + */ +esp_err_t esp_sleep_disable_ext1_wakeup_io(uint64_t io_mask); + #if SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN /** * @brief Enable wakeup using multiple pins, allows different trigger mode per pin @@ -327,7 +400,9 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t io_mask, esp_sleep_ext1_wakeup_m * - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO, * or mode is invalid */ -esp_err_t esp_sleep_enable_ext1_wakeup_with_level_mask(uint64_t io_mask, uint64_t level_mask); +esp_err_t esp_sleep_enable_ext1_wakeup_with_level_mask(uint64_t io_mask, uint64_t level_mask) +__attribute__((deprecated("please use 'esp_sleep_enable_ext1_wakeup_io' and 'esp_sleep_disable_ext1_wakeup_io' instead"))); + #endif // SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN #endif // SOC_PM_SUPPORT_EXT1_WAKEUP diff --git a/components/esp_hw_support/include/soc/esp32c5/.gitkeep b/components/esp_hw_support/include/soc/esp32c5/.gitkeep new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_hw_support/include/spinlock.h b/components/esp_hw_support/include/spinlock.h index 4bf65f76d0d..c19d088ee3f 100644 --- a/components/esp_hw_support/include/spinlock.h +++ b/components/esp_hw_support/include/spinlock.h @@ -51,7 +51,7 @@ typedef struct { static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock) { assert(lock); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE lock->owner = SPINLOCK_FREE; lock->count = 0; #endif @@ -73,7 +73,7 @@ static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t */ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *lock, int32_t timeout) { -#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD uint32_t irq_status; uint32_t core_owner_id, other_core_owner_id; bool lock_set; @@ -151,7 +151,7 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l #endif return lock_set; -#else // !CONFIG_FREERTOS_UNICORE +#else // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE return true; #endif } @@ -171,7 +171,7 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l */ static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *lock) { -#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD uint32_t irq_status; uint32_t core_owner_id; @@ -198,7 +198,7 @@ static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *l #else rv_utils_restore_intlevel(irq_status); #endif //#if __XTENSA__ -#endif //#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD +#endif //#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD } #ifdef __cplusplus diff --git a/components/esp_hw_support/ldo/esp_ldo.c b/components/esp_hw_support/ldo/esp_ldo.c new file mode 100644 index 00000000000..6003fec4f8d --- /dev/null +++ b/components/esp_hw_support/ldo/esp_ldo.c @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "sdkconfig.h" +#include "stdatomic.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_heap_caps.h" +#include "freertos/FreeRTOS.h" +#include "soc/soc_caps.h" +#include "hal/ldo_ll.h" +#include "esp_private/esp_ldo.h" + +static const DRAM_ATTR char TAG[] = "ldo"; + +typedef struct ldo_unit_ctx_t { + int unit_id; + int voltage_mv; + bool enabled; + int ref_cnt; + portMUX_TYPE spinlock; +} ldo_unit_ctx_t; + +typedef struct ldo_ctx_t { + _lock_t mutex; + ldo_unit_ctx_t units[LDO_LL_UNIT_NUM]; +} ldo_ctx_t; + +static ldo_ctx_t s_ctx; //LDO context +//LDO1 is always reserved for Flash usage +static atomic_bool s_ldo_unit_claimed[LDO_LL_UNIT_NUM] = {ATOMIC_VAR_INIT(true), + ATOMIC_VAR_INIT(false), + ATOMIC_VAR_INIT(false), + ATOMIC_VAR_INIT(false)}; + +static bool s_ldo_unit_claim(uint32_t unit); +static bool s_ldo_unit_free(uint32_t unit); +static bool s_ldo_unit_needs_claim(const esp_ldo_unit_init_cfg_t *init_config); + + +//This API should always success +esp_ldo_unit_handle_t esp_ldo_init_unit_early(const esp_ldo_unit_init_cfg_t *init_config) +{ + assert(init_config); + assert(init_config->unit_id < LDO_LL_UNIT_NUM); + + ldo_unit_ctx_t *unit = &s_ctx.units[init_config->unit_id]; + bool needs_claim = s_ldo_unit_needs_claim(init_config); + bool success_claim = false; + + if (needs_claim) { + success_claim = s_ldo_unit_claim(init_config->unit_id); + assert(success_claim); + unit->unit_id = init_config->unit_id; + unit->voltage_mv = init_config->cfg.voltage_mv; + unit->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + ldo_ll_set_output_voltage_mv(init_config->unit_id, init_config->cfg.voltage_mv); + + if (init_config->flags.enable_unit) { + ldo_ll_enable(init_config->unit_id, true); + unit->enabled = true; + } + } else { + bool same_voltage = init_config->cfg.voltage_mv == unit->voltage_mv; + assert(same_voltage); + } + + unit->ref_cnt++; + + return unit; +} + +esp_err_t esp_ldo_init_unit(const esp_ldo_unit_init_cfg_t *init_config, esp_ldo_unit_handle_t *ret_unit) +{ + ESP_RETURN_ON_FALSE(init_config && ret_unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(init_config->unit_id < LDO_LL_UNIT_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid unit"); + + ldo_unit_ctx_t *unit = &s_ctx.units[init_config->unit_id]; + bool needs_claim = s_ldo_unit_needs_claim(init_config); + bool success_claim = false; + + if (needs_claim) { + success_claim = s_ldo_unit_claim(init_config->unit_id); + ESP_RETURN_ON_FALSE(success_claim, ESP_ERR_NOT_FOUND, TAG, "ldo%d is already in use", init_config->unit_id + 1); + unit->unit_id = init_config->unit_id; + unit->voltage_mv = init_config->cfg.voltage_mv; + unit->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + ldo_ll_set_output_voltage_mv(init_config->unit_id, init_config->cfg.voltage_mv); + if (init_config->flags.enable_unit) { + ldo_ll_enable(init_config->unit_id, true); + unit->enabled = true; + } + ESP_LOGD(TAG, "new ldo unit%d is created", unit->unit_id); + } else { + bool same_voltage = init_config->cfg.voltage_mv == unit->voltage_mv; + ESP_RETURN_ON_FALSE(same_voltage, ESP_ERR_INVALID_ARG, TAG, "not same voltage, cannot share ldo%d", init_config->unit_id + 1); + ESP_LOGD(TAG, "new ldo unit%d is shared", unit->unit_id); + } + + portENTER_CRITICAL(&unit->spinlock); + unit->ref_cnt++; + portEXIT_CRITICAL(&unit->spinlock); + + *ret_unit = unit; + return ESP_OK; +} + +esp_err_t esp_ldo_deinit_unit(esp_ldo_unit_handle_t unit) +{ + ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(unit->enabled == false, ESP_ERR_INVALID_STATE, TAG, "invalid state: ldo unit is still enabled"); + + bool needs_free = false; + portENTER_CRITICAL(&unit->spinlock); + unit->ref_cnt -= 1; + if (unit->ref_cnt == 0) { + needs_free = true; + } + portEXIT_CRITICAL(&unit->spinlock); + + if (needs_free) { + bool success_free = false; + success_free = s_ldo_unit_free(unit->unit_id); + ESP_RETURN_ON_FALSE(success_free, ESP_ERR_NOT_FOUND, TAG, "ldo%d isn't in use", unit->unit_id + 1); + ESP_LOGD(TAG, "ldo unit%d is deleted", unit->unit_id + 1); + _lock_acquire(&s_ctx.mutex); + memset(&s_ctx.units[unit->unit_id], 0x0, sizeof(ldo_unit_ctx_t)); + _lock_release(&s_ctx.mutex); + } + + return ESP_OK; +} + +esp_err_t esp_ldo_enable_unit(esp_ldo_unit_handle_t unit) +{ + ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(unit->enabled == false, ESP_ERR_INVALID_STATE, TAG, "invalid state: ldo unit is enabled already"); + + ldo_ll_enable(unit->unit_id, true); + unit->enabled = true; + + return ESP_OK; +} + +esp_err_t esp_ldo_disable_unit(esp_ldo_unit_handle_t unit) +{ + ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(unit->enabled == true, ESP_ERR_INVALID_STATE, TAG, "invalid state: ldo unit is disabled already"); + + ldo_ll_enable(unit->unit_id, false); + unit->enabled = false; + + return ESP_OK; +} + +esp_err_t esp_ldo_usage_dump(FILE* stream) +{ + char line[100]; + fprintf(stream, "LDOs Info:\n"); + for (int i = 0; i < LDO_LL_UNIT_NUM; i++) { + fprintf(stream, "%-15s %-14s %-14s\n", "LDO ID", "voltage_mv", "enabled"); + + char *buf = line; + size_t len = sizeof(line); + memset(line, 0x0, len); + snprintf(buf, len, "%-15d 0x%-12d %-11x\n", + s_ctx.units[i].unit_id + 1, + s_ctx.units[i].voltage_mv, + s_ctx.units[i].enabled); + fputs(line, stream); + } + + fprintf(stream, "You can use a disabled LDO unit, or share an enabled LDO unit\n"); + + return ESP_OK; +} + +static bool s_ldo_unit_claim(uint32_t unit) +{ + bool false_var = false; + return atomic_compare_exchange_strong(&s_ldo_unit_claimed[unit], &false_var, true); +} + +static bool s_ldo_unit_free(uint32_t unit) +{ + bool true_var = true; + return atomic_compare_exchange_strong(&s_ldo_unit_claimed[unit], &true_var, false); +} + +static bool s_ldo_unit_needs_claim(const esp_ldo_unit_init_cfg_t *init_config) +{ + bool needs_claim = false; + + if (s_ctx.units[init_config->unit_id].ref_cnt == 0) { + needs_claim = true; + } else { + if (!init_config->flags.shared_ldo) { + needs_claim = true; + } + } + + return needs_claim; +} diff --git a/components/esp_hw_support/ldo/linker.lf b/components/esp_hw_support/ldo/linker.lf new file mode 100644 index 00000000000..2d1732faca8 --- /dev/null +++ b/components/esp_hw_support/ldo/linker.lf @@ -0,0 +1,4 @@ +[mapping:ldo_driver] +archive: libesp_hw_support.a +entries: + esp_ldo: esp_ldo_init_unit_early (noflash) diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index f7b88173cbe..4f366e13f53 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -23,6 +23,8 @@ entries: rtc_time (noflash_text) if SOC_PMU_SUPPORTED = y: pmu_sleep (noflash) + if SOC_USB_SERIAL_JTAG_SUPPORTED = y: + sleep_console (noflash) if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y: rtc_wdt (noflash_text) if PERIPH_CTRL_FUNC_IN_IRAM = y: diff --git a/components/esp_hw_support/mac_addr.c b/components/esp_hw_support/mac_addr.c index c917b57c109..a73f40e8e6e 100644 --- a/components/esp_hw_support/mac_addr.c +++ b/components/esp_hw_support/mac_addr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,7 +63,7 @@ static mac_t s_mac_table[] = { #define ITEMS_IN_MAC_TABLE (sizeof(s_mac_table) / sizeof(mac_t)) static esp_err_t generate_mac(uint8_t *mac, uint8_t *base_mac_addr, esp_mac_type_t type); -static esp_err_t get_efuse_mac_get_default(uint8_t *mac); +static esp_err_t get_efuse_factory_mac(uint8_t *mac); static esp_err_t get_efuse_mac_custom(uint8_t *mac); #if CONFIG_SOC_IEEE802154_SUPPORTED static esp_err_t get_efuse_mac_ext(uint8_t *mac); @@ -89,11 +89,19 @@ static esp_err_t get_mac_addr_from_mac_table(uint8_t *mac, int idx, bool silent) esp_mac_type_t type = s_mac_table[idx].type; if (ESP_MAC_BASE <= type && type <= ESP_MAC_EFUSE_EXT) { esp_err_t err = ESP_OK; - if (type == ESP_MAC_BASE || type == ESP_MAC_EFUSE_FACTORY) { - err = get_efuse_mac_get_default(s_mac_table[idx].mac); - } else if (type == ESP_MAC_EFUSE_CUSTOM) { - err = get_efuse_mac_custom(s_mac_table[idx].mac); - } + if (type == ESP_MAC_EFUSE_FACTORY +#ifndef CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC + || type == ESP_MAC_BASE +#endif + ) { + err = get_efuse_factory_mac(s_mac_table[idx].mac); + } else if (type == ESP_MAC_EFUSE_CUSTOM +#ifdef CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC + || type == ESP_MAC_BASE +#endif + ) { + err = get_efuse_mac_custom(s_mac_table[idx].mac); + } #if CONFIG_SOC_IEEE802154_SUPPORTED else if (type == ESP_MAC_EFUSE_EXT) { err = get_efuse_mac_ext(s_mac_table[idx].mac); @@ -246,7 +254,7 @@ static esp_err_t get_efuse_mac_custom(uint8_t *mac) esp_err_t esp_efuse_mac_get_default(uint8_t *mac) { - esp_err_t err = get_efuse_mac_get_default(mac); + esp_err_t err = get_efuse_factory_mac(mac); if (err != ESP_OK) { return err; } @@ -257,7 +265,7 @@ esp_err_t esp_efuse_mac_get_default(uint8_t *mac) #endif } -static esp_err_t get_efuse_mac_get_default(uint8_t *mac) +static esp_err_t get_efuse_factory_mac(uint8_t *mac) { size_t size_bits = esp_efuse_get_field_size(ESP_EFUSE_MAC_FACTORY); assert((size_bits % 8) == 0); diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index f48a281bc94..f1755137888 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -157,36 +157,6 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi } #if SOC_PM_SUPPORT_PMU_MODEM_STATE -static void IRAM_ATTR modem_clock_domain_power_state_icg_map_init(modem_clock_context_t *ctx) -{ - #define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP)) - #define ICG_NOGATING_MODEM (BIT(PMU_HP_ICG_MODEM_CODE_MODEM)) - #define ICG_NOGATING_ACTIVE (BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE)) - - /* the ICG code's bit 0, 1 and 2 indicates the ICG state - * of pmu SLEEP, MODEM and ACTIVE mode respectively */ - const uint32_t code[MODEM_CLOCK_DOMAIN_MAX] = { - [MODEM_CLOCK_DOMAIN_MODEM_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ICG_NOGATING_ACTIVE, - [MODEM_CLOCK_DOMAIN_WIFI] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_BT] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_IEEE802154] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_LP_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_I2C_MASTER] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_COEX] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - [MODEM_CLOCK_DOMAIN_WIFIPWR] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, - }; - for (modem_clock_domain_t domain = MODEM_CLOCK_DOMAIN_MODEM_APB; domain < MODEM_CLOCK_DOMAIN_MAX; domain++) { - modem_clock_hal_set_clock_domain_icg_bitmap(ctx->hal, domain, code[domain]); - } -} - -void modem_clock_domain_pmu_state_icg_map_init(void) -{ - modem_clock_domain_power_state_icg_map_init(MODEM_CLOCK_instance()); -} - esp_err_t modem_clock_domain_clk_gate_enable(modem_clock_domain_t domain, pmu_hp_icg_modem_mode_t mode) { if (domain >= MODEM_CLOCK_DOMAIN_MAX || domain < MODEM_CLOCK_DOMAIN_MODEM_APB) { @@ -319,9 +289,43 @@ static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module) return deps; } +#if SOC_PM_SUPPORT_PMU_MODEM_STATE +/* the ICG code's bit 0, 1 and 2 indicates the ICG state + * of pmu SLEEP, MODEM and ACTIVE mode respectively */ +#define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP)) +#define ICG_NOGATING_MODEM (BIT(PMU_HP_ICG_MODEM_CODE_MODEM)) +#define ICG_NOGATING_ACTIVE (BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE)) + +static const DRAM_ATTR uint32_t initial_gating_mode[MODEM_CLOCK_DOMAIN_MAX] = { + [MODEM_CLOCK_DOMAIN_MODEM_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, + [MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ICG_NOGATING_ACTIVE, + [MODEM_CLOCK_DOMAIN_WIFI] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, + [MODEM_CLOCK_DOMAIN_BT] = ICG_NOGATING_ACTIVE, + [MODEM_CLOCK_DOMAIN_MODEM_FE] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, + [MODEM_CLOCK_DOMAIN_IEEE802154] = ICG_NOGATING_ACTIVE, + [MODEM_CLOCK_DOMAIN_LP_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, + [MODEM_CLOCK_DOMAIN_I2C_MASTER] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, + [MODEM_CLOCK_DOMAIN_COEX] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, + [MODEM_CLOCK_DOMAIN_WIFIPWR] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM, +}; + +static IRAM_ATTR void modem_clock_module_icg_map_init_all(void) +{ + portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); + for (int domain = 0; domain < MODEM_CLOCK_DOMAIN_MAX; domain++) { + uint32_t code = modem_clock_hal_get_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain); + modem_clock_hal_set_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain, initial_gating_mode[domain] | code); + } + portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +} +#endif // SOC_PM_SUPPORT_PMU_MODEM_STATE + void IRAM_ATTR modem_clock_module_enable(periph_module_t module) { assert(IS_MODEM_MODULE(module)); +#if SOC_PM_SUPPORT_PMU_MODEM_STATE + modem_clock_module_icg_map_init_all(); +#endif uint32_t deps = modem_clock_get_module_deps(module); modem_clock_device_enable(MODEM_CLOCK_instance(), deps); } diff --git a/components/esp_hw_support/periph_ctrl.c b/components/esp_hw_support/periph_ctrl.c index 51bb15b99f1..a560cd29901 100644 --- a/components/esp_hw_support/periph_ctrl.c +++ b/components/esp_hw_support/periph_ctrl.c @@ -92,7 +92,7 @@ IRAM_ATTR void wifi_bt_common_module_enable(void) #else portENTER_CRITICAL_SAFE(&periph_spinlock); if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) { - periph_ll_wifi_bt_module_enable_clk_clear_rst(); + periph_ll_wifi_bt_module_enable_clk(); } ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++; portEXIT_CRITICAL_SAFE(&periph_spinlock); @@ -107,7 +107,7 @@ IRAM_ATTR void wifi_bt_common_module_disable(void) portENTER_CRITICAL_SAFE(&periph_spinlock); ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]--; if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) { - periph_ll_wifi_bt_module_disable_clk_set_rst(); + periph_ll_wifi_bt_module_disable_clk(); } portEXIT_CRITICAL_SAFE(&periph_spinlock); #endif diff --git a/components/esp_hw_support/port/esp32/CMakeLists.txt b/components/esp_hw_support/port/esp32/CMakeLists.txt index 27a9809b213..b51ba1d5c68 100644 --- a/components/esp_hw_support/port/esp32/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32/CMakeLists.txt @@ -1,5 +1,4 @@ target_include_directories(${COMPONENT_LIB} PUBLIC .) -target_include_directories(${COMPONENT_LIB} PUBLIC private_include) set(srcs "rtc_clk.c" diff --git a/components/esp_hw_support/port/esp32/Kconfig.rtc b/components/esp_hw_support/port/esp32/Kconfig.rtc index a2dd64dfb61..117edae8aef 100644 --- a/components/esp_hw_support/port/esp32/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32/Kconfig.rtc @@ -22,7 +22,7 @@ choice RTC_CLK_SRC the internal 150kHz oscillator. It does not require external components. config RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" + bool "Internal 150 kHz RC oscillator" config RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL diff --git a/components/esp_hw_support/port/esp32/rtc_time.c b/components/esp_hw_support/port/esp32/rtc_time.c index 960d160e912..227aed8a958 100644 --- a/components/esp_hw_support/port/esp32/rtc_time.c +++ b/components/esp_hw_support/port/esp32/rtc_time.c @@ -112,6 +112,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); @@ -127,6 +128,7 @@ static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slo uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); @@ -142,6 +144,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32c2/CMakeLists.txt b/components/esp_hw_support/port/esp32c2/CMakeLists.txt index 482f65e4f4d..9943669d5bf 100644 --- a/components/esp_hw_support/port/esp32c2/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c2/CMakeLists.txt @@ -15,5 +15,3 @@ endif() add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") -target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) -target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32c2/rtc_time.c b/components/esp_hw_support/port/esp32c2/rtc_time.c index 3772b4d4236..26332a12c22 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_time.c +++ b/components/esp_hw_support/port/esp32c2/rtc_time.c @@ -126,6 +126,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); @@ -141,6 +142,7 @@ static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slo uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); @@ -156,6 +158,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32c3/CMakeLists.txt b/components/esp_hw_support/port/esp32c3/CMakeLists.txt index b383b815a6a..03cf2f4cc97 100644 --- a/components/esp_hw_support/port/esp32c3/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c3/CMakeLists.txt @@ -22,5 +22,3 @@ endif() add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") -target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) -target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32c3/Kconfig.hw_support b/components/esp_hw_support/port/esp32c3/Kconfig.hw_support index d6a924afd4e..8e7c12f8d74 100644 --- a/components/esp_hw_support/port/esp32c3/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32c3/Kconfig.hw_support @@ -40,7 +40,7 @@ config ESP_REV_MIN_FULL # MAX Revision # - comment "Maximum Supported ESP32-C3 Revision (Rev v0.99)" + comment "Maximum Supported ESP32-C3 Revision (Rev v1.99)" # Maximum revision that IDF supports. # It can not be changed by user. # Only Espressif can change it when a new version will be supported in IDF. @@ -48,14 +48,9 @@ config ESP_REV_MIN_FULL config ESP32C3_REV_MAX_FULL int - default 199 if ESP32C3_REV101_DEVELOPMENT - default 99 if !ESP32C3_REV101_DEVELOPMENT + default 199 # keep in sync the "Maximum Supported Revision" description with this value config ESP_REV_MAX_FULL int default ESP32C3_REV_MAX_FULL - -config ESP32C3_REV101_DEVELOPMENT - bool "Develop on ESP32-C3 v1.1 (Preview)" - default y if IDF_CI_BUILD diff --git a/components/esp_hw_support/port/esp32c3/rtc_time.c b/components/esp_hw_support/port/esp32c3/rtc_time.c index ce83921a31a..b002ea1a7dc 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_time.c +++ b/components/esp_hw_support/port/esp32c3/rtc_time.c @@ -129,6 +129,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); @@ -144,6 +145,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); @@ -159,6 +161,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32c5/CMakeLists.txt b/components/esp_hw_support/port/esp32c5/CMakeLists.txt new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_hw_support/port/esp32c5/cpu_region_protect.c b/components/esp_hw_support/port/esp32c5/cpu_region_protect.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_hw_support/port/esp32c5/io_mux.c b/components/esp_hw_support/port/esp32c5/io_mux.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt index e82e407cb0e..4f251876b0e 100644 --- a/components/esp_hw_support/port/esp32c6/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt @@ -22,4 +22,3 @@ add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) -target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.rtc b/components/esp_hw_support/port/esp32c6/Kconfig.rtc index 297ffc1c4ab..e58391029ca 100644 --- a/components/esp_hw_support/port/esp32c6/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32c6/Kconfig.rtc @@ -5,7 +5,7 @@ choice RTC_CLK_SRC Choose which clock is used as RTC clock source. config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" + bool "Internal 150 kHz RC oscillator" config RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c index faa6a4d0084..9628cc794f8 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c @@ -286,3 +286,8 @@ void pmu_sleep_enable_hp_sleep_sysclk(bool enable) { pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable); } + +uint32_t pmu_sleep_get_wakup_retention_cost(void) +{ + return PMU_REGDMA_S2A_WORK_TIME_US; +} diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h index 0938e058b88..75e1f99ff21 100644 --- a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h @@ -44,6 +44,8 @@ extern "C" { #define PMU_HP_XPD_DEEPSLEEP 0 #define PMU_LP_DRVB_DEEPSLEEP 0 +#define PMU_REGDMA_S2A_WORK_TIME_US 480 + #define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 12 #define PMU_LP_DBIAS_DEEPSLEEP_0V7 23 @@ -456,7 +458,7 @@ typedef struct pmu_sleep_machine_constant { .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ .regdma_s2m_work_time_us = 172, \ - .regdma_s2a_work_time_us = 480, \ + .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \ .regdma_m2a_work_time_us = 278, \ .regdma_a2s_work_time_us = 382, \ .regdma_rf_on_work_time_us = 70, \ diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c index 06ef4967381..53aaed511cc 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_time.c +++ b/components/esp_hw_support/port/esp32c6/rtc_time.c @@ -210,6 +210,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); /*The Fosc CLK of calibration circuit is divided by 32 for ECO1. @@ -235,6 +236,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32h2/CMakeLists.txt b/components/esp_hw_support/port/esp32h2/CMakeLists.txt index 9c1949a12c1..2c4cd900da7 100644 --- a/components/esp_hw_support/port/esp32h2/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32h2/CMakeLists.txt @@ -16,4 +16,3 @@ add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) -target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32h2/Kconfig.rtc b/components/esp_hw_support/port/esp32h2/Kconfig.rtc index 297ffc1c4ab..e58391029ca 100644 --- a/components/esp_hw_support/port/esp32h2/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32h2/Kconfig.rtc @@ -5,7 +5,7 @@ choice RTC_CLK_SRC Choose which clock is used as RTC clock source. config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" + bool "Internal 150 kHz RC oscillator" config RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c index 1f39dd0a7fc..75a170d6a4c 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c @@ -228,3 +228,8 @@ bool pmu_sleep_finish(void) { return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); } + +uint32_t pmu_sleep_get_wakup_retention_cost(void) +{ + return PMU_REGDMA_S2A_WORK_TIME_US; +} diff --git a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h index 824ccb9db71..50f55ed258c 100644 --- a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h @@ -41,6 +41,8 @@ extern "C" { #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1 #define PMU_LP_DBIAS_LIGHTSLEEP_0V7 6 +#define PMU_REGDMA_S2A_WORK_TIME_US 0 + // FOR DEEPSLEEP #define PMU_HP_XPD_DEEPSLEEP 0 #define PMU_LP_DRVB_DEEPSLEEP 7 @@ -438,7 +440,7 @@ typedef struct pmu_sleep_machine_constant { .analog_wait_time_us = 154, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ - .regdma_s2a_work_time_us = 0, \ + .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \ .regdma_a2s_work_time_us = 0, \ .xtal_wait_stable_time_us = 250, \ .pll_wait_stable_time_us = 1 \ diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c index e3b421b25bf..58816b1b024 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_time.c +++ b/components/esp_hw_support/port/esp32h2/rtc_time.c @@ -209,6 +209,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); /*The Fosc CLK of calibration circuit is divided by 32 for ECO2. @@ -234,6 +235,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32p4/CMakeLists.txt b/components/esp_hw_support/port/esp32p4/CMakeLists.txt index aa294129f6a..5bb37ab371a 100644 --- a/components/esp_hw_support/port/esp32p4/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32p4/CMakeLists.txt @@ -25,5 +25,3 @@ list(REMOVE_ITEM srcs add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") -target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) -target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.rtc b/components/esp_hw_support/port/esp32p4/Kconfig.rtc index 70c41dbe234..0ca1162422f 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32p4/Kconfig.rtc @@ -7,7 +7,7 @@ choice RTC_CLK_SRC Choose which clock is used as RTC clock source. config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" + bool "Internal 150 kHz RC oscillator" config RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c index 6c67021a9b2..df3890a6c35 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c @@ -405,3 +405,26 @@ bool rtc_dig_8m_enabled(void) * TODO: update the library to use rtc_clk_xtal_freq_get */ rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get"))); + +//------------------------------------MPLL-------------------------------------// +void rtc_clk_mpll_disable(void) +{ + clk_ll_mpll_disable(); +} + +void rtc_clk_mpll_enable(void) +{ + clk_ll_mpll_enable(); +} + +void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq) +{ + /* Analog part */ + /* MPLL calibration start */ + regi2c_ctrl_ll_mpll_calibration_start(); + clk_ll_mpll_set_config(mpll_freq, xtal_freq); + /* wait calibration done */ + while(!regi2c_ctrl_ll_mpll_calibration_is_done()); + /* MPLL calibration stop */ + regi2c_ctrl_ll_mpll_calibration_stop(); +} diff --git a/components/esp_hw_support/port/esp32p4/rtc_time.c b/components/esp_hw_support/port/esp32p4/rtc_time.c index 95075cedf27..d1d20b6f149 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_time.c +++ b/components/esp_hw_support/port/esp32p4/rtc_time.c @@ -181,6 +181,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); @@ -196,6 +197,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32s2/CMakeLists.txt b/components/esp_hw_support/port/esp32s2/CMakeLists.txt index a2a386d9d09..a0ee667fd6f 100644 --- a/components/esp_hw_support/port/esp32s2/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32s2/CMakeLists.txt @@ -1,5 +1,4 @@ target_include_directories(${COMPONENT_LIB} PUBLIC .) -target_include_directories(${COMPONENT_LIB} PUBLIC private_include) set(srcs "rtc_clk.c" diff --git a/components/esp_hw_support/port/esp32s2/rtc_time.c b/components/esp_hw_support/port/esp32s2/rtc_time.c index 506dd63a6f2..9222d784a4b 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_time.c +++ b/components/esp_hw_support/port/esp32s2/rtc_time.c @@ -123,6 +123,7 @@ static uint32_t rtc_clk_cal_internal_cycling(rtc_cal_sel_t cal_clk, uint32_t slo */ static uint32_t rtc_clk_xtal_to_slowclk(uint64_t xtal_cycles, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; @@ -191,6 +192,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE); uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); @@ -224,6 +226,7 @@ uint32_t rtc_clk_cal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32s3/CMakeLists.txt b/components/esp_hw_support/port/esp32s3/CMakeLists.txt index bb4a29c5af0..4829b57f349 100644 --- a/components/esp_hw_support/port/esp32s3/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32s3/CMakeLists.txt @@ -1,5 +1,4 @@ target_include_directories(${COMPONENT_LIB} PUBLIC .) -target_include_directories(${COMPONENT_LIB} PUBLIC private_include) set(srcs "rtc_clk.c" diff --git a/components/esp_hw_support/port/esp32s3/rtc_time.c b/components/esp_hw_support/port/esp32s3/rtc_time.c index f719c14a8ad..720ef8e0fdf 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_time.c +++ b/components/esp_hw_support/port/esp32s3/rtc_time.c @@ -128,6 +128,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); @@ -143,6 +144,7 @@ static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slo uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { + assert(slowclk_cycles); rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); @@ -158,6 +160,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c index aab6b17860f..0ff2a8e6cd2 100644 --- a/components/esp_hw_support/port/pau_regdma.c +++ b/components/esp_hw_support/port/pau_regdma.c @@ -62,7 +62,7 @@ void pau_regdma_trigger_modem_link_restore(void) } #endif -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA void IRAM_ATTR pau_regdma_set_system_link_addr(void *link_addr) { /* ESP32H2 use software to trigger REGDMA to restore instead of PMU, @@ -88,18 +88,18 @@ void IRAM_ATTR pau_regdma_trigger_system_link_restore(void) } #endif -void pau_regdma_set_extra_link_addr(void *link_addr) +void IRAM_ATTR pau_regdma_set_extra_link_addr(void *link_addr) { pau_hal_set_regdma_extra_link_addr(PAU_instance()->hal, link_addr); } -void pau_regdma_trigger_extra_link_backup(void) +void IRAM_ATTR pau_regdma_trigger_extra_link_backup(void) { pau_hal_start_regdma_extra_link(PAU_instance()->hal, true); pau_hal_stop_regdma_extra_link(PAU_instance()->hal); } -void pau_regdma_trigger_extra_link_restore(void) +void IRAM_ATTR pau_regdma_trigger_extra_link_restore(void) { pau_hal_start_regdma_extra_link(PAU_instance()->hal, false); pau_hal_stop_regdma_extra_link(PAU_instance()->hal); diff --git a/components/esp_hw_support/sdkconfig.rename.esp32 b/components/esp_hw_support/sdkconfig.rename.esp32 index 91bac13a640..058f8515389 100644 --- a/components/esp_hw_support/sdkconfig.rename.esp32 +++ b/components/esp_hw_support/sdkconfig.rename.esp32 @@ -21,7 +21,8 @@ CONFIG_SPIRAM_SUPPORT CONFIG_SPIRAM CONFIG_ESP32_SPIRAM_SUPPORT CONFIG_SPIRAM CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP -CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY CONFIG_ESP32_XTAL_FREQ_26 CONFIG_XTAL_FREQ_26 CONFIG_ESP32_XTAL_FREQ_40 CONFIG_XTAL_FREQ_40 diff --git a/components/esp_hw_support/sdkconfig.rename.esp32s3 b/components/esp_hw_support/sdkconfig.rename.esp32s3 index 77e595a9076..39a3d34cca0 100644 --- a/components/esp_hw_support/sdkconfig.rename.esp32s3 +++ b/components/esp_hw_support/sdkconfig.rename.esp32s3 @@ -10,4 +10,5 @@ CONFIG_ESP32S3_RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RE CONFIG_ESP32S3_SPIRAM_SUPPORT CONFIG_SPIRAM -CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY diff --git a/components/esp_hw_support/sleep_clock.c b/components/esp_hw_support/sleep_clock.c index b18f0cb23f7..ab60b0980fc 100644 --- a/components/esp_hw_support/sleep_clock.c +++ b/components/esp_hw_support/sleep_clock.c @@ -23,7 +23,7 @@ #include "soc/pcr_reg.h" #include "modem/modem_syscon_reg.h" -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA #include "modem/modem_lpcon_reg.h" #endif @@ -54,13 +54,13 @@ void sleep_clock_system_retention_deinit(void) esp_err_t sleep_clock_modem_retention_init(void) { #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA #define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) #endif const static sleep_retention_entries_config_t modem_regs_retention[] = { [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) } /* MODEM LPCON */ #endif }; @@ -89,7 +89,7 @@ bool clock_domain_pd_allowed(void) } #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP || CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE -ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, BIT(0), 106) +ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) { #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP sleep_clock_system_retention_init(); diff --git a/components/esp_hw_support/sleep_console.c b/components/esp_hw_support/sleep_console.c new file mode 100644 index 00000000000..02a0f5bb276 --- /dev/null +++ b/components/esp_hw_support/sleep_console.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/soc_caps.h" +#include "esp_private/sleep_console.h" +#include "esp_attr.h" + +#if SOC_USB_SERIAL_JTAG_SUPPORTED +#include "hal/usb_serial_jtag_ll.h" + +static sleep_console_usj_enable_state_t s_usj_state = {0}; + +void sleep_console_usj_pad_backup_and_disable(void) +{ + // This function can be called in sleep process only, and sleep process code + // is in critical region and thread safe already, so to avoid build errors/warnings + // declare __DECLARE_RCC_ATOMIC_ENV here. + int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); + + s_usj_state.usj_clock_enabled = usb_serial_jtag_ll_module_is_enabled(); + if (!s_usj_state.usj_clock_enabled) { + // Enable USJ clock and clear reset + usb_serial_jtag_ll_enable_bus_clock(true); + usb_serial_jtag_ll_reset_register(); + } + s_usj_state.usj_pad_enabled = usb_serial_jtag_ll_pad_backup_and_disable(); + // Disable USJ clock + usb_serial_jtag_ll_enable_bus_clock(false); +} + +void sleep_console_usj_pad_restore(void) +{ + // This function can be called in sleep process only, and sleep process code + // is in critical region and thread safe already, so to avoid build errors/warnings + // declare __DECLARE_RCC_ATOMIC_ENV here. + int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); + + usb_serial_jtag_ll_enable_bus_clock(true); + usb_serial_jtag_ll_enable_pad(s_usj_state.usj_pad_enabled); + if (!s_usj_state.usj_clock_enabled) { + usb_serial_jtag_ll_enable_bus_clock(false); + } +} +#endif diff --git a/components/esp_hw_support/sleep_cpu.c b/components/esp_hw_support/sleep_cpu.c index 815942f95b6..f77c4e336c7 100644 --- a/components/esp_hw_support/sleep_cpu.c +++ b/components/esp_hw_support/sleep_cpu.c @@ -92,7 +92,7 @@ static DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention; #if SOC_PM_SUPPORT_TAGMEM_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL -#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP +#if CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t code_seg_size, uint32_t data_seg_vaddr, uint32_t data_seg_size) { uint32_t sets; /* i/d-cache total set counts */ @@ -153,11 +153,11 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c * i/d-cache tagmem blocks (128 bits * 3 = 96 bits * 4) */ return (((icache_tagmem_blk_gs + dcache_tagmem_blk_gs) << 2) * 3); } -#endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP +#endif // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP static esp_err_t esp_sleep_tagmem_pd_low_init(void) { -#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP +#if CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP if (s_cpu_retention.retent.tagmem.link_addr == NULL) { extern char _stext[], _etext[]; uint32_t code_start = (uint32_t)_stext; @@ -186,11 +186,11 @@ static esp_err_t esp_sleep_tagmem_pd_low_init(void) return ESP_ERR_NO_MEM; } } -#else // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP +#else // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP s_cpu_retention.retent.tagmem.icache.enable = 0; s_cpu_retention.retent.tagmem.dcache.enable = 0; s_cpu_retention.retent.tagmem.link_addr = NULL; -#endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP +#endif // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP return ESP_OK; } diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index 759659d1a9a..d29541f6342 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -185,7 +185,7 @@ void esp_deep_sleep_wakeup_io_reset(void) } #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO -ESP_SYSTEM_INIT_FN(esp_sleep_startup_init, BIT(0), 105) +ESP_SYSTEM_INIT_FN(esp_sleep_startup_init, SECONDARY, BIT(0), 105) { /* If the TOP domain is powered off, the GPIO will also be powered off during sleep, and all configurations in the sleep state of GPIO will not take effect.*/ diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c index 7e963aa64d0..b9a6f6c2526 100644 --- a/components/esp_hw_support/sleep_modem.c +++ b/components/esp_hw_support/sleep_modem.c @@ -28,6 +28,7 @@ #if SOC_PM_SUPPORT_PMU_MODEM_STATE #include "soc/pmu_reg.h" #include "esp_private/esp_pau.h" +#include "esp_private/esp_pmu.h" #endif static __attribute__((unused)) const char *TAG = "sleep_modem"; @@ -36,9 +37,15 @@ static __attribute__((unused)) const char *TAG = "sleep_modem"; static void esp_pm_light_sleep_default_params_config(int min_freq_mhz, int max_freq_mhz); #endif +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD +static bool s_modem_sleep = false; +static uint8_t s_modem_prepare_ref = 0; +static _lock_t s_modem_prepare_lock; +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + #if CONFIG_MAC_BB_PD -#define MAC_BB_POWER_DOWN_CB_NO (2) -#define MAC_BB_POWER_UP_CB_NO (2) +#define MAC_BB_POWER_DOWN_CB_NO (3) +#define MAC_BB_POWER_UP_CB_NO (3) static DRAM_ATTR mac_bb_power_down_cb_t s_mac_bb_power_down_cb[MAC_BB_POWER_DOWN_CB_NO]; static DRAM_ATTR mac_bb_power_up_cb_t s_mac_bb_power_up_cb[MAC_BB_POWER_UP_CB_NO]; @@ -390,3 +397,78 @@ static void esp_pm_light_sleep_default_params_config(int min_freq_mhz, int max_f } } #endif + +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD +void sleep_modem_register_mac_bb_module_prepare_callback(mac_bb_power_down_cb_t pd_cb, + mac_bb_power_up_cb_t pu_cb) +{ + _lock_acquire(&s_modem_prepare_lock); + if (s_modem_prepare_ref++ == 0) { + esp_register_mac_bb_pd_callback(pd_cb); + esp_register_mac_bb_pu_callback(pu_cb); + } + _lock_release(&s_modem_prepare_lock); +} + +void sleep_modem_unregister_mac_bb_module_prepare_callback(mac_bb_power_down_cb_t pd_cb, + mac_bb_power_up_cb_t pu_cb) +{ + _lock_acquire(&s_modem_prepare_lock); + assert(s_modem_prepare_ref); + if (--s_modem_prepare_ref == 0) { + esp_unregister_mac_bb_pd_callback(pd_cb); + esp_unregister_mac_bb_pu_callback(pu_cb); + } + _lock_release(&s_modem_prepare_lock); + +} + +/** + * @brief Switch root clock source to PLL do retention and switch back + * + * This function is used when Bluetooth/IEEE802154 module requires register backup/restore, this function + * is called ONLY when SOC_PM_RETENTION_HAS_CLOCK_BUG is set. + * @param backup true for backup, false for restore + * @param cpu_freq_mhz cpu frequency to do retention + * @param do_retention function for retention + */ +static void IRAM_ATTR rtc_clk_cpu_freq_to_pll_mhz_and_do_retention(bool backup, int cpu_freq_mhz, void (*do_retention)(bool)) +{ +#if SOC_PM_SUPPORT_PMU_MODEM_STATE + if (pmu_sleep_pll_already_enabled()) { + return; + } +#endif + rtc_cpu_freq_config_t config, pll_config; + rtc_clk_cpu_freq_get_config(&config); + + rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &pll_config); + rtc_clk_cpu_freq_set_config(&pll_config); + + if (do_retention) { + (*do_retention)(backup); + } + + rtc_clk_cpu_freq_set_config(&config); +} + +void IRAM_ATTR sleep_modem_mac_bb_power_down_prepare(void) +{ + if (s_modem_sleep == false) { + rtc_clk_cpu_freq_to_pll_mhz_and_do_retention(true, + CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, + sleep_retention_do_extra_retention); + s_modem_sleep = true; + } +} + +void IRAM_ATTR sleep_modem_mac_bb_power_up_prepare(void) +{ + if (s_modem_sleep) { + rtc_clk_cpu_freq_to_pll_mhz_and_do_retention(false, + CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, + sleep_retention_do_extra_retention); + s_modem_sleep = false; + } +} +#endif /* SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD */ diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 6f8d6a07ef6..4fbe9edf999 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -37,8 +37,6 @@ #include "hal/rtc_hal.h" #endif -#include "driver/uart.h" - #include "soc/rtc.h" #include "soc/soc_caps.h" #include "regi2c_ctrl.h" //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp @@ -49,8 +47,6 @@ #include "hal/uart_hal.h" #if SOC_TOUCH_SENSOR_SUPPORTED #include "hal/touch_sensor_hal.h" -#include "driver/touch_sensor.h" -#include "driver/touch_sensor_common.h" #endif #include "hal/clk_gate_ll.h" @@ -58,6 +54,7 @@ #include "esp_rom_uart.h" #include "esp_rom_sys.h" #include "esp_private/brownout.h" +#include "esp_private/sleep_console.h" #include "esp_private/sleep_cpu.h" #include "esp_private/sleep_modem.h" #include "esp_private/esp_clk.h" @@ -102,15 +99,15 @@ #include "esp_private/sleep_clock.h" #endif -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA #include "esp_private/sleep_retention.h" #endif // If light sleep time is less than that, don't power down flash #define FLASH_PD_MIN_SLEEP_TIME_US 2000 -// Time from VDD_SDIO power up to first flash read in ROM code -#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700 +// Default waiting time for the software to wait for Flash ready after waking up from sleep +#define ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US 700 // Cycles for RTC Timer clock source (internal oscillator) calibrate #define RTC_CLK_SRC_CAL_CYCLES (10) @@ -159,12 +156,6 @@ #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) #endif -#if CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY -#define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY -#else -#define DEEP_SLEEP_WAKEUP_DELAY 0 -#endif - // Minimal amount of time we can sleep for #define LIGHT_SLEEP_MIN_TIME_US 200 @@ -361,13 +352,16 @@ void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR); _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG, _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR)); -#if DEEP_SLEEP_WAKEUP_DELAY > 0 +#if CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY > 0 // ROM code has not started yet, so we need to set delay factor // used by esp_rom_delay_us first. ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000); - // This delay is configured in menuconfig, it can be used to give - // the flash chip some time to become ready. - esp_rom_delay_us(DEEP_SLEEP_WAKEUP_DELAY); + // Time from VDD_SDIO power up to first flash read in ROM code is 700 us, + // for some flash chips is not sufficient, this delay is configured in menuconfig, + // it can be used to give the flash chip some extra time to become ready. + // For later chips, we have EFUSE_FLASH_TPUW field to configure it and do + // this delay in the ROM. + esp_rom_delay_us(CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY); #endif #elif CONFIG_IDF_TARGET_ESP32S2 REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN); @@ -538,6 +532,10 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep) } } } else { +#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP + // Only avoid USJ pad leakage here, USB OTG pad leakage is prevented through USB Host driver. + sleep_console_usj_pad_backup_and_disable(); +#endif #if CONFIG_MAC_BB_PD mac_bb_power_down_cb_execute(); #endif @@ -549,9 +547,6 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep) #endif #if REGI2C_ANA_CALI_PD_WORKAROUND regi2c_analog_cali_reg_read(); -#endif -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG - sleep_retention_do_system_retention(true); #endif } @@ -566,8 +561,8 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep) */ FORCE_INLINE_ATTR void misc_modules_wake_prepare(void) { -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG - sleep_retention_do_system_retention(false); +#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP + sleep_console_usj_pad_restore(); #endif sar_periph_ctrl_power_enable(); #if SOC_PM_SUPPORT_CPU_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL @@ -584,6 +579,44 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(void) #endif } +static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp) +{ + // Calibrate rtc slow clock +#ifdef CONFIG_ESP_SYSTEM_RTC_EXT_XTAL + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + uint64_t time_per_us = 1000000ULL; + s_config.rtc_clk_cal_period = (time_per_us << RTC_CLK_CAL_FRACT) / rtc_clk_slow_freq_get_hz(); + } else { + // If the external 32 kHz XTAL does not exist, use the internal 150 kHz RC oscillator + // as the RTC slow clock source. + s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); + esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); + } +#elif CONFIG_RTC_CLK_SRC_INT_RC && CONFIG_IDF_TARGET_ESP32S2 + s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); + esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); +#else +#if CONFIG_PM_ENABLE + if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp) +#endif + { + s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); + esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); + } +#endif + + // Calibrate rtc fast clock, only PMU supported chips sleep process is needed. +#if SOC_PMU_SUPPORTED +#if CONFIG_PM_ENABLE + if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp) +#endif + { + s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES); + } +#endif +} + + inline static uint32_t call_rtc_sleep_start(uint32_t reject_triggers, uint32_t lslp_mem_inf_fpu, bool dslp); static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mode, bool allow_sleep_rejection) @@ -620,6 +653,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m // Will switch to XTAL turn down MSPI speed mspi_timing_change_speed_mode_cache_safe(true); +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA + if (!deep_sleep && (pd_flags & PMU_SLEEP_PD_TOP)) { + sleep_retention_do_system_retention(true); + } +#endif + // Save current frequency and switch to XTAL rtc_cpu_freq_config_t cpu_freq_config; rtc_clk_cpu_freq_get_config(&cpu_freq_config); @@ -630,11 +669,13 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) { ext0_wakeup_prepare(); } + // for !(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN), ext0 wakeup will be turned off in hardware in the real call to sleep #endif #if SOC_PM_SUPPORT_EXT1_WAKEUP if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) { ext1_wakeup_prepare(); } + // for !(s_config.wakeup_triggers & RTC_EXT1_TRIG_EN), ext1 wakeup will be turned off in hardware in the real call to sleep #endif #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP @@ -842,18 +883,23 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m rtc_clk_cpu_freq_set_config(&cpu_freq_config); } - if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) { - // Turn up MSPI speed if switch to PLL - mspi_timing_change_speed_mode_cache_safe(false); - } - esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CLK_READY, (void *)0); if (!deep_sleep) { s_config.ccount_ticks_record = esp_cpu_get_cycle_count(); +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA + if (pd_flags & PMU_SLEEP_PD_TOP) { + sleep_retention_do_system_retention(false); + } +#endif misc_modules_wake_prepare(); } + if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) { + // Turn up MSPI speed if switch to PLL + mspi_timing_change_speed_mode_cache_safe(false); + } + // re-enable UART output resume_uarts(); return result ? ESP_ERR_SLEEP_REJECT : ESP_OK; @@ -899,7 +945,8 @@ static esp_err_t IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection) // Decide which power domains can be powered down uint32_t pd_flags = get_power_down_flags(); - s_config.rtc_clk_cal_period = esp_clk_slowclk_cal_get(); + // Re-calibrate the RTC clock + sleep_low_power_clock_calibration(true); // Correct the sleep time s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US; @@ -993,6 +1040,18 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags, // If SPI flash was powered down, wait for it to become ready if (pd_flags & RTC_SLEEP_PD_VDDSDIO) { +#if SOC_PM_SUPPORT_TOP_PD + if (pd_flags & PMU_SLEEP_PD_TOP) { + uint32_t flash_ready_hw_waited_time_us = pmu_sleep_get_wakup_retention_cost(); + uint32_t flash_ready_sw_waited_time_us = (esp_cpu_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / MHZ); + uint32_t flash_ready_waited_time_us = flash_ready_hw_waited_time_us + flash_ready_sw_waited_time_us; + if (flash_enable_time_us > flash_ready_waited_time_us){ + flash_enable_time_us -= flash_ready_waited_time_us; + } else { + flash_enable_time_us = 0; + } + } +#endif // Wait for the flash chip to start up esp_rom_delay_us(flash_enable_time_us); } @@ -1085,29 +1144,8 @@ esp_err_t esp_light_sleep_start(void) pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH; #endif - // Re-calibrate the RTC Timer clock -#ifdef CONFIG_ESP_SYSTEM_RTC_EXT_XTAL - if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - uint64_t time_per_us = 1000000ULL; - s_config.rtc_clk_cal_period = (time_per_us << RTC_CLK_CAL_FRACT) / rtc_clk_slow_freq_get_hz(); - } else { - // If the external 32 kHz XTAL does not exist, use the internal 150 kHz RC oscillator - // as the RTC slow clock source. - s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); - esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); - } -#elif CONFIG_RTC_CLK_SRC_INT_RC && CONFIG_IDF_TARGET_ESP32S2 - s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); - esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); -#else -#if CONFIG_PM_ENABLE - if (s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) -#endif - { - s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); - esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period); - } -#endif + // Re-calibrate the RTC clock + sleep_low_power_clock_calibration(false); /* * Adjustment time consists of parts below: @@ -1116,14 +1154,7 @@ esp_err_t esp_light_sleep_start(void) * 3. Code execution time when clock is not stable; * 4. Code execution time which can be measured; */ - #if SOC_PMU_SUPPORTED -#if CONFIG_PM_ENABLE - if (s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) -#endif - { - s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES); - } int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out; int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(pd_flags, s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period); s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment; @@ -1133,12 +1164,9 @@ esp_err_t esp_light_sleep_start(void) + rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period); #endif -#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6930 - const uint32_t flash_enable_time_us = 0; -#else // Decide if VDD_SDIO needs to be powered down; // If it needs to be powered down, adjust sleep time. - const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US + DEEP_SLEEP_WAKEUP_DELAY; + const uint32_t flash_enable_time_us = ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US + CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY; /** * If VDD_SDIO power domain is requested to be turned off, bit `RTC_SLEEP_PD_VDDSDIO` @@ -1177,7 +1205,6 @@ esp_err_t esp_light_sleep_start(void) } } } -#endif periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in); @@ -1423,9 +1450,8 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void) return TOUCH_PAD_MAX; } touch_pad_t pad_num; - esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b - assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero"); - return (ret == ESP_OK) ? pad_num : TOUCH_PAD_MAX; + touch_hal_get_wakeup_status(&pad_num); + return pad_num; } #endif // SOC_TOUCH_SENSOR_SUPPORTED @@ -1468,12 +1494,25 @@ static void ext0_wakeup_prepare(void) rtcio_hal_function_select(rtc_gpio_num, RTCIO_LL_FUNC_RTC); rtcio_hal_input_enable(rtc_gpio_num); } + #endif // SOC_PM_SUPPORT_EXT0_WAKEUP #if SOC_PM_SUPPORT_EXT1_WAKEUP esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t io_mask, esp_sleep_ext1_wakeup_mode_t level_mode) { - if (level_mode > ESP_EXT1_WAKEUP_ANY_HIGH) { + if (io_mask == 0 && level_mode > ESP_EXT1_WAKEUP_ANY_HIGH) { + return ESP_ERR_INVALID_ARG; + } + // Reset all EXT1 configs + esp_sleep_disable_ext1_wakeup_io(0); + + return esp_sleep_enable_ext1_wakeup_io(io_mask, level_mode); +} + + +esp_err_t esp_sleep_enable_ext1_wakeup_io(uint64_t io_mask, esp_sleep_ext1_wakeup_mode_t level_mode) +{ + if (io_mask == 0 && level_mode > ESP_EXT1_WAKEUP_ANY_HIGH) { return ESP_ERR_INVALID_ARG; } // Translate bit map of GPIO numbers into the bit map of RTC IO numbers @@ -1488,16 +1527,61 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t io_mask, esp_sleep_ext1_wakeup_m } rtc_gpio_mask |= BIT(rtc_io_number_get(gpio)); } - s_config.ext1_rtc_gpio_mask = rtc_gpio_mask; + +#if !SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + uint32_t ext1_rtc_gpio_mask = 0; + uint32_t ext1_trigger_mode = 0; + + ext1_rtc_gpio_mask = s_config.ext1_rtc_gpio_mask | rtc_gpio_mask; if (level_mode) { - s_config.ext1_trigger_mode = rtc_gpio_mask; + ext1_trigger_mode = s_config.ext1_trigger_mode | rtc_gpio_mask; } else { - s_config.ext1_trigger_mode = 0; + ext1_trigger_mode = s_config.ext1_trigger_mode & (~rtc_gpio_mask); + } + if (((ext1_rtc_gpio_mask & ext1_trigger_mode) != ext1_rtc_gpio_mask) && + ((ext1_rtc_gpio_mask & ext1_trigger_mode) != 0)) { + return ESP_ERR_NOT_ALLOWED; + } +#endif + + s_config.ext1_rtc_gpio_mask |= rtc_gpio_mask; + if (level_mode) { + s_config.ext1_trigger_mode |= rtc_gpio_mask; + } else { + s_config.ext1_trigger_mode &= (~rtc_gpio_mask); } s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN; return ESP_OK; } +esp_err_t esp_sleep_disable_ext1_wakeup_io(uint64_t io_mask) +{ + if (io_mask == 0) { + s_config.ext1_rtc_gpio_mask = 0; + s_config.ext1_trigger_mode = 0; + } else { + // Translate bit map of GPIO numbers into the bit map of RTC IO numbers + uint32_t rtc_gpio_mask = 0; + for (int gpio = 0; io_mask; ++gpio, io_mask >>= 1) { + if ((io_mask & 1) == 0) { + continue; + } + if (!esp_sleep_is_valid_wakeup_gpio(gpio)) { + ESP_LOGE(TAG, "Not an RTC IO Considering io_mask: GPIO%d", gpio); + return ESP_ERR_INVALID_ARG; + } + rtc_gpio_mask |= BIT(rtc_io_number_get(gpio)); + } + s_config.ext1_rtc_gpio_mask &= (~rtc_gpio_mask); + s_config.ext1_trigger_mode &= (~rtc_gpio_mask); + } + + if (s_config.ext1_rtc_gpio_mask == 0) { + s_config.wakeup_triggers &= (~RTC_EXT1_TRIG_EN); + } + return ESP_OK; +} + #if SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN esp_err_t esp_sleep_enable_ext1_wakeup_with_level_mask(uint64_t io_mask, uint64_t level_mask) { diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c index 95e90d5e074..744b9808635 100644 --- a/components/esp_hw_support/sleep_retention.c +++ b/components/esp_hw_support/sleep_retention.c @@ -94,15 +94,11 @@ typedef struct { uint32_t modules; #if SOC_PM_RETENTION_HAS_CLOCK_BUG #define EXTRA_LINK_NUM (REGDMA_LINK_ENTRY_NUM - 1) - int extra_refs; #endif } sleep_retention_t; static DRAM_ATTR __attribute__((unused)) sleep_retention_t s_retention = { .highpri = (uint8_t)-1, .modules = 0 -#if SOC_PM_RETENTION_HAS_CLOCK_BUG - , .extra_refs = 0 -#endif }; #define SLEEP_RETENTION_ENTRY_BITMAP_MASK (BIT(REGDMA_LINK_ENTRY_NUM) - 1) @@ -503,43 +499,23 @@ uint32_t IRAM_ATTR sleep_retention_get_modules(void) } #if SOC_PM_RETENTION_HAS_CLOCK_BUG -void sleep_retention_do_extra_retention(bool backup_or_restore) +void IRAM_ATTR sleep_retention_do_extra_retention(bool backup_or_restore) { - _lock_acquire_recursive(&s_retention.lock); if (s_retention.highpri < SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY || s_retention.highpri > SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) { - _lock_release_recursive(&s_retention.lock); return; } - const uint32_t clk_bug_modules = SLEEP_RETENTION_MODULE_BLE_MAC | SLEEP_RETENTION_MODULE_802154_MAC; - const int cnt_modules = __builtin_popcount(clk_bug_modules & s_retention.modules); // Set extra linked list head pointer to hardware pau_regdma_set_extra_link_addr(s_retention.lists[s_retention.highpri].entries[EXTRA_LINK_NUM]); if (backup_or_restore) { - if (s_retention.extra_refs++ == (cnt_modules - 1)) { - pau_regdma_trigger_extra_link_backup(); - } + pau_regdma_trigger_extra_link_backup(); } else { - if (--s_retention.extra_refs == (cnt_modules - 1)) { - pau_regdma_trigger_extra_link_restore(); - } + pau_regdma_trigger_extra_link_restore(); } - int refs = s_retention.extra_refs; - _lock_release_recursive(&s_retention.lock); - assert(refs >= 0 && refs <= cnt_modules); -} - -void sleep_retention_module_deinit(void) -{ - _lock_acquire_recursive(&s_retention.lock); - if (s_retention.extra_refs) { - s_retention.extra_refs--; - } - _lock_release_recursive(&s_retention.lock); } #endif -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA void IRAM_ATTR sleep_retention_do_system_retention(bool backup_or_restore) { #define SYSTEM_LINK_NUM (0) diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c index 22d236dcd6a..4bf9be2e7ca 100644 --- a/components/esp_hw_support/sleep_system_peripheral.c +++ b/components/esp_hw_support/sleep_system_peripheral.c @@ -259,7 +259,7 @@ bool peripheral_domain_pd_allowed(void) } #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP -ESP_SYSTEM_INIT_FN(sleep_sys_periph_startup_init, BIT(0), 107) +ESP_SYSTEM_INIT_FN(sleep_sys_periph_startup_init, SECONDARY, BIT(0), 107) { sleep_sys_periph_retention_init(); return ESP_OK; diff --git a/components/driver/spi/spi_bus_lock.c b/components/esp_hw_support/spi_bus_lock.c similarity index 92% rename from components/driver/spi/spi_bus_lock.c rename to components/esp_hw_support/spi_bus_lock.c index c74998ecf78..ab3a20ec657 100644 --- a/components/driver/spi/spi_bus_lock.c +++ b/components/esp_hw_support/spi_bus_lock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,7 +8,7 @@ #include "freertos/semphr.h" #include #include "sdkconfig.h" -#include "esp_private/spi_common_internal.h" +#include "esp_private/spi_share_hw_ctrl.h" #include "esp_intr_alloc.h" #include "soc/soc_caps.h" #include "stdatomic.h" @@ -17,6 +17,17 @@ #include #include "esp_heap_caps.h" +#ifdef CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM +#define SPI_BUS_LOCK_ISR_ATTR IRAM_ATTR +#else +#define SPI_BUS_LOCK_ISR_ATTR +#endif + +#ifdef CONFIG_ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM +#define SPI_BUSLOCK_ATTR IRAM_ATTR +#else +#define SPI_BUSLOCK_ATTR +#endif /* * This lock is designed to solve the conflicts between SPI devices (used in tasks) and @@ -145,7 +156,6 @@ typedef struct spi_bus_lock_dev_t spi_bus_lock_dev_t; typedef struct spi_bus_lock_t spi_bus_lock_t; - #define MAX_DEV_NUM 10 // Bit 29-20: lock bits, Bit 19-10: pending bits @@ -264,7 +274,7 @@ static inline int dev_lock_get_id(spi_bus_lock_dev_t *dev_lock); /******************************************************************************* * atomic operations to the status ******************************************************************************/ -SPI_MASTER_ISR_ATTR static inline uint32_t lock_status_fetch_set(spi_bus_lock_t *lock, uint32_t set) +SPI_BUS_LOCK_ISR_ATTR static inline uint32_t lock_status_fetch_set(spi_bus_lock_t *lock, uint32_t set) { return atomic_fetch_or(&lock->status, set); } @@ -279,7 +289,7 @@ IRAM_ATTR static inline uint32_t lock_status_fetch(spi_bus_lock_t *lock) return atomic_load(&lock->status); } -SPI_MASTER_ISR_ATTR static inline void lock_status_init(spi_bus_lock_t *lock) +SPI_BUS_LOCK_ISR_ATTR static inline void lock_status_init(spi_bus_lock_t *lock) { atomic_store(&lock->status, 0); } @@ -302,7 +312,7 @@ IRAM_ATTR static inline uint32_t lock_status_clear(spi_bus_lock_t* lock, uint32_ * Most of them should be atomic, and special attention should be paid to the operation * sequence. ******************************************************************************/ -SPI_MASTER_ISR_ATTR static inline void resume_dev_in_isr(spi_bus_lock_dev_t *dev_lock, BaseType_t *do_yield) +SPI_BUS_LOCK_ISR_ATTR static inline void resume_dev_in_isr(spi_bus_lock_dev_t *dev_lock, BaseType_t *do_yield) { xSemaphoreGiveFromISR(dev_lock->semphr, do_yield); } @@ -312,7 +322,7 @@ IRAM_ATTR static inline void resume_dev(const spi_bus_lock_dev_t *dev_lock) xSemaphoreGive(dev_lock->semphr); } -SPI_MASTER_ISR_ATTR static inline void bg_disable(spi_bus_lock_t *lock) +SPI_BUS_LOCK_ISR_ATTR static inline void bg_disable(spi_bus_lock_t *lock) { BUS_LOCK_DEBUG_EXECUTE_CHECK(lock->bg_disable); lock->bg_disable(lock->bg_arg); @@ -326,14 +336,14 @@ IRAM_ATTR static inline void bg_enable(spi_bus_lock_t* lock) // Set the REQ bit. If we become the acquiring processor, invoke the ISR and pass that to it. // The caller will never become the acquiring processor after this function returns. -SPI_MASTER_ATTR static inline void req_core(spi_bus_lock_dev_t *dev_handle) +SPI_BUSLOCK_ATTR static inline void req_core(spi_bus_lock_dev_t *dev_handle) { spi_bus_lock_t *lock = dev_handle->parent; // Though `acquired_dev` is critical resource, `dev_handle == lock->acquired_dev` // is a stable statement unless `acquire_start` or `acquire_end` is called by current // device. - if (dev_handle == lock->acquiring_dev){ + if (dev_handle == lock->acquiring_dev) { // Set the REQ bit and check BG bits if we are the acquiring processor. // If the BG bits were not active before, invoke the BG again. @@ -353,7 +363,7 @@ SPI_MASTER_ATTR static inline void req_core(spi_bus_lock_dev_t *dev_handle) } //Set the LOCK bit. Handle related stuff and return true if we become the acquiring processor. -SPI_MASTER_ISR_ATTR static inline bool acquire_core(spi_bus_lock_dev_t *dev_handle) +SPI_BUS_LOCK_ISR_ATTR static inline bool acquire_core(spi_bus_lock_dev_t *dev_handle) { spi_bus_lock_t* lock = dev_handle->parent; @@ -457,7 +467,7 @@ IRAM_ATTR static inline void acquire_end_core(spi_bus_lock_dev_t *dev_handle) // Move the REQ bits to corresponding PEND bits. Must be called by acquiring processor. // Have no side effects on the acquiring device/processor. -SPI_MASTER_ISR_ATTR static inline void update_pend_core(spi_bus_lock_t *lock, uint32_t status) +SPI_BUS_LOCK_ISR_ATTR static inline void update_pend_core(spi_bus_lock_t *lock, uint32_t status) { uint32_t active_req_bits = status & REQ_MASK; #if PENDING_SHIFT > REQ_SHIFT @@ -474,7 +484,7 @@ SPI_MASTER_ISR_ATTR static inline void update_pend_core(spi_bus_lock_t *lock, ui // Clear the PEND bit (not REQ bit!) of a device, return the suggestion whether we can try to quit the ISR. // Lost the acquiring processor immediately when the BG bits for active device are inactive, indiciating by the return value. // Can be called only when ISR is acting as the acquiring processor. -SPI_MASTER_ISR_ATTR static inline bool clear_pend_core(spi_bus_lock_dev_t *dev_handle) +SPI_BUS_LOCK_ISR_ATTR static inline bool clear_pend_core(spi_bus_lock_dev_t *dev_handle) { bool finished; spi_bus_lock_t *lock = dev_handle->parent; @@ -497,7 +507,7 @@ SPI_MASTER_ISR_ATTR static inline bool clear_pend_core(spi_bus_lock_dev_t *dev_h // Return true if the ISR has already touched the HW, which means previous operations should // be terminated first, before we use the HW again. Otherwise return false. // In either case `in_isr` will be marked as true, until call to `bg_exit_core` with `wip=false` successfully. -SPI_MASTER_ISR_ATTR static inline bool bg_entry_core(spi_bus_lock_t *lock) +SPI_BUS_LOCK_ISR_ATTR static inline bool bg_entry_core(spi_bus_lock_t *lock) { BUS_LOCK_DEBUG_EXECUTE_CHECK(!lock->acquiring_dev || lock->acq_dev_bg_active); /* @@ -523,7 +533,7 @@ SPI_MASTER_ISR_ATTR static inline bool bg_entry_core(spi_bus_lock_t *lock) // When called with `wip=true`, means the ISR is performing some operations. Will enable the interrupt again and exit unconditionally. // When called with `wip=false`, will only return `true` when there is no coming BG request. If return value is `false`, the ISR should try again. // Will not change acquiring device. -SPI_MASTER_ISR_ATTR static inline bool bg_exit_core(spi_bus_lock_t *lock, bool wip, BaseType_t *do_yield) +SPI_BUS_LOCK_ISR_ATTR static inline bool bg_exit_core(spi_bus_lock_t *lock, bool wip, BaseType_t *do_yield) { //See comments in `bg_entry_core`, re-enable interrupt disabled in entry if we do need the interrupt if (wip) { @@ -560,11 +570,13 @@ IRAM_ATTR static inline void dev_wait_prepare(spi_bus_lock_dev_t *dev_handle) xSemaphoreTake(dev_handle->semphr, 0); } -SPI_MASTER_ISR_ATTR static inline esp_err_t dev_wait(spi_bus_lock_dev_t *dev_handle, TickType_t wait) +SPI_BUS_LOCK_ISR_ATTR static inline esp_err_t dev_wait(spi_bus_lock_dev_t *dev_handle, TickType_t wait) { BaseType_t ret = xSemaphoreTake(dev_handle->semphr, wait); - if (ret == pdFALSE) return ESP_ERR_TIMEOUT; + if (ret == pdFALSE) { + return ESP_ERR_TIMEOUT; + } return ESP_OK; } @@ -607,7 +619,7 @@ static int try_acquire_free_dev(spi_bus_lock_t *lock, bool cs_required) break; } } - return ((i == lock->periph_cs_num)? -1: i); + return ((i == lock->periph_cs_num) ? -1 : i); } else { int i; for (i = DEV_NUM_MAX - 1; i >= 0; i--) { @@ -624,9 +636,13 @@ static int try_acquire_free_dev(spi_bus_lock_t *lock, bool cs_required) esp_err_t spi_bus_lock_register_dev(spi_bus_lock_handle_t lock, spi_bus_lock_dev_config_t *config, spi_bus_lock_dev_handle_t *out_dev_handle) { - if (lock == NULL) return ESP_ERR_INVALID_ARG; + if (lock == NULL) { + return ESP_ERR_INVALID_ARG; + } int id = try_acquire_free_dev(lock, config->flags & SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED); - if (id == -1) return ESP_ERR_NOT_SUPPORTED; + if (id == -1) { + return ESP_ERR_NOT_SUPPORTED; + } spi_bus_lock_dev_t* dev_lock = (spi_bus_lock_dev_t*)heap_caps_calloc(sizeof(spi_bus_lock_dev_t), 1, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); if (dev_lock == NULL) { @@ -654,7 +670,9 @@ void spi_bus_lock_unregister_dev(spi_bus_lock_dev_handle_t dev_handle) spi_bus_lock_t* lock = dev_handle->parent; BUS_LOCK_DEBUG_EXECUTE_CHECK(atomic_load(&lock->dev[id]) == (intptr_t)dev_handle); - if (lock->last_dev == dev_handle) lock->last_dev = NULL; + if (lock->last_dev == dev_handle) { + lock->last_dev = NULL; + } atomic_store(&lock->dev[id], (intptr_t)NULL); if (dev_handle->semphr) { @@ -683,7 +701,7 @@ void spi_bus_lock_set_bg_control(spi_bus_lock_handle_t lock, bg_ctrl_func_t bg_e IRAM_ATTR int spi_bus_lock_get_dev_id(spi_bus_lock_dev_handle_t dev_handle) { - return (dev_handle? dev_lock_get_id(dev_handle): -1); + return (dev_handle ? dev_lock_get_id(dev_handle) : -1); } //will be called when cache disabled @@ -692,9 +710,9 @@ IRAM_ATTR bool spi_bus_lock_touch(spi_bus_lock_dev_handle_t dev_handle) spi_bus_lock_dev_t* last_dev = dev_handle->parent->last_dev; dev_handle->parent->last_dev = dev_handle; if (last_dev != dev_handle) { - int last_dev_id = (last_dev? dev_lock_get_id(last_dev): -1); + int last_dev_id = (last_dev ? dev_lock_get_id(last_dev) : -1); ESP_DRAM_LOGV(TAG, "SPI dev changed from %d to %d", - last_dev_id, dev_lock_get_id(dev_handle)); + last_dev_id, dev_lock_get_id(dev_handle)); } return (dev_handle != last_dev); } @@ -714,7 +732,9 @@ IRAM_ATTR esp_err_t spi_bus_lock_acquire_start(spi_bus_lock_dev_t *dev_handle, T //block until becoming the acquiring processor (help by previous acquiring processor) esp_err_t err = dev_wait(dev_handle, wait); //TODO: add timeout handling here. - if (err != ESP_OK) return err; + if (err != ESP_OK) { + return err; + } } ESP_DRAM_LOGV(TAG, "dev %d acquired.", dev_lock_get_id(dev_handle)); @@ -740,7 +760,7 @@ IRAM_ATTR esp_err_t spi_bus_lock_acquire_end(spi_bus_lock_dev_t *dev_handle) return ESP_OK; } -SPI_MASTER_ISR_ATTR spi_bus_lock_dev_handle_t spi_bus_lock_get_acquiring_dev(spi_bus_lock_t *lock) +SPI_BUS_LOCK_ISR_ATTR spi_bus_lock_dev_handle_t spi_bus_lock_get_acquiring_dev(spi_bus_lock_t *lock) { return lock->acquiring_dev; } @@ -748,17 +768,17 @@ SPI_MASTER_ISR_ATTR spi_bus_lock_dev_handle_t spi_bus_lock_get_acquiring_dev(spi /******************************************************************************* * BG (background operation) service ******************************************************************************/ -SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_entry(spi_bus_lock_t* lock) +SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_entry(spi_bus_lock_t* lock) { return bg_entry_core(lock); } -SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_exit(spi_bus_lock_t* lock, bool wip, BaseType_t* do_yield) +SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_exit(spi_bus_lock_t* lock, bool wip, BaseType_t* do_yield) { return bg_exit_core(lock, wip, do_yield); } -SPI_MASTER_ATTR esp_err_t spi_bus_lock_bg_request(spi_bus_lock_dev_t *dev_handle) +SPI_BUSLOCK_ATTR esp_err_t spi_bus_lock_bg_request(spi_bus_lock_dev_t *dev_handle) { req_core(dev_handle); return ESP_OK; @@ -780,7 +800,9 @@ IRAM_ATTR esp_err_t spi_bus_lock_wait_bg_done(spi_bus_lock_dev_handle_t dev_hand //block until becoming the acquiring processor (help by previous acquiring processor) esp_err_t err = dev_wait(dev_handle, wait); //TODO: add timeout handling here. - if (err != ESP_OK) return err; + if (err != ESP_OK) { + return err; + } } } @@ -789,14 +811,14 @@ IRAM_ATTR esp_err_t spi_bus_lock_wait_bg_done(spi_bus_lock_dev_handle_t dev_hand return ESP_OK; } -SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_clear_req(spi_bus_lock_dev_t *dev_handle) +SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_clear_req(spi_bus_lock_dev_t *dev_handle) { bool finished = clear_pend_core(dev_handle); ESP_EARLY_LOGV(TAG, "dev %d served from bg.", dev_lock_get_id(dev_handle)); return finished; } -SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_check_dev_acq(spi_bus_lock_t *lock, +SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_check_dev_acq(spi_bus_lock_t *lock, spi_bus_lock_dev_handle_t *out_dev_lock) { BUS_LOCK_DEBUG_EXECUTE_CHECK(!lock->acquiring_dev); @@ -804,7 +826,7 @@ SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_check_dev_acq(spi_bus_lock_t *lock, return schedule_core(lock, status, out_dev_lock); } -SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_check_dev_req(spi_bus_lock_dev_t *dev_lock) +SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_check_dev_req(spi_bus_lock_dev_t *dev_lock) { spi_bus_lock_t* lock = dev_lock->parent; uint32_t status = lock_status_fetch(lock); @@ -820,7 +842,7 @@ SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_check_dev_req(spi_bus_lock_dev_t *dev_l } } -SPI_MASTER_ISR_ATTR bool spi_bus_lock_bg_req_exist(spi_bus_lock_t *lock) +SPI_BUS_LOCK_ISR_ATTR bool spi_bus_lock_bg_req_exist(spi_bus_lock_t *lock) { uint32_t status = lock_status_fetch(lock); return status & BG_MASK; @@ -845,12 +867,6 @@ static spi_bus_lock_t main_spi_bus_lock = { }; const spi_bus_lock_handle_t g_main_spi_bus_lock = &main_spi_bus_lock; -esp_err_t spi_bus_lock_init_main_bus(void) -{ - spi_bus_main_set_lock(g_main_spi_bus_lock); - return ESP_OK; -} - static StaticSemaphore_t main_flash_semphr; static spi_bus_lock_dev_t lock_main_flash_dev = { diff --git a/components/esp_hw_support/spi_share_hw_ctrl.c b/components/esp_hw_support/spi_share_hw_ctrl.c new file mode 100644 index 00000000000..3d610bb49f4 --- /dev/null +++ b/components/esp_hw_support/spi_share_hw_ctrl.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_private/spi_share_hw_ctrl.h" + +#include + +#include "sdkconfig.h" +#include "soc/soc_caps.h" +#include "hal/spi_ll.h" +#include "esp_log.h" + +static const char* SPI_TAG = "spi_share_hw_ctrl"; + +//Periph 1 is 'claimed' by SPI flash code. +static atomic_bool spi_periph_claimed[SOC_SPI_PERIPH_NUM] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false), +#if (SOC_SPI_PERIPH_NUM >= 3) + ATOMIC_VAR_INIT(false), +#endif +#if (SOC_SPI_PERIPH_NUM >= 4) + ATOMIC_VAR_INIT(false), +#endif + }; + +static const char* spi_claiming_func[3] = {NULL, NULL, NULL}; + +//----------------------------------------------------------alloc spi periph-------------------------------------------------------// +//Returns true if this peripheral is successfully claimed, false if otherwise. +bool spicommon_periph_claim(spi_host_device_t host, const char* source) +{ + bool false_var = false; + bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &false_var, true); + if (ret) { + spi_claiming_func[host] = source; + SPI_COMMON_RCC_CLOCK_ATOMIC() { + spi_ll_enable_bus_clock(host, true); + spi_ll_reset_register(host); + } + } else { + ESP_EARLY_LOGE(SPI_TAG, "SPI%d already claimed by %s.", host + 1, spi_claiming_func[host]); + } + return ret; +} + +bool spicommon_periph_in_use(spi_host_device_t host) +{ + return atomic_load(&spi_periph_claimed[host]); +} + +//Returns true if this peripheral is successfully freed, false if otherwise. +bool spicommon_periph_free(spi_host_device_t host) +{ + bool true_var = true; + bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &true_var, false); + if (ret) { + SPI_COMMON_RCC_CLOCK_ATOMIC() { + spi_ll_enable_bus_clock(host, false); + } + } + return ret; +} diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index badd45f01ac..43acc7dfd8a 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -16,8 +16,9 @@ components/esp_hw_support/test_apps/etm: depends_components: - esp_driver_gptimer - esp_driver_gpio + - esp_driver_mcpwm - esp_timer - - driver # TODO: replace with esp_driver_mcpwm, esp_driver_ana_cmpr + - esp_driver_ana_cmpr components/esp_hw_support/test_apps/host_test_linux: enable: diff --git a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt index 54b23982095..b923e9882f6 100644 --- a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt @@ -8,6 +8,10 @@ if(CONFIG_SOC_GDMA_SUPPORTED) list(APPEND srcs "test_gdma.c") endif() +if(CONFIG_SOC_DW_GDMA_SUPPORTED) + list(APPEND srcs "test_dw_gdma.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} diff --git a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c index fa750b20121..9c0236a5a4c 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c +++ b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c @@ -27,6 +27,7 @@ #if CONFIG_IDF_TARGET_ESP32P4 #define TEST_MEMCPY_DST_BASE_ALIGN 64 +#define TEST_MEMCPY_BUFFER_SIZE_MUST_ALIGN_CACHE 1 #else #define TEST_MEMCPY_DST_BASE_ALIGN 4 #endif @@ -112,7 +113,7 @@ TEST_CASE("memory copy the same buffer with different content", "[async mcp]") async_memcpy_config_t config = ASYNC_MEMCPY_DEFAULT_CONFIG(); async_memcpy_handle_t driver = NULL; TEST_ESP_OK(esp_async_memcpy_install(&config, &driver)); - uint8_t *sbuf = heap_caps_malloc(256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + uint8_t *sbuf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); uint8_t *dbuf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); for (int j = 0; j < 20; j++) { TEST_ESP_OK(esp_async_memcpy(driver, dbuf, sbuf, 256, NULL, NULL)); @@ -133,15 +134,29 @@ TEST_CASE("memory copy the same buffer with different content", "[async mcp]") static void test_memory_copy_one_by_one(async_memcpy_handle_t driver) { - uint32_t test_buffer_len[] = {256, 512, 1024, 2048, 4096, 5011}; + uint32_t aligned_test_buffer_size[] = {256, 512, 1024, 2048, 4096}; memcpy_testbench_context_t test_context = { .align = TEST_MEMCPY_DST_BASE_ALIGN, }; - for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) { + for (int i = 0; i < sizeof(aligned_test_buffer_size) / sizeof(aligned_test_buffer_size[0]); i++) { + test_context.buffer_size = aligned_test_buffer_size[i]; + test_context.seed = i; + test_context.offset = 0; + async_memcpy_setup_testbench(&test_context); + + TEST_ESP_OK(esp_async_memcpy(driver, test_context.to_addr, test_context.from_addr, test_context.copy_size, NULL, NULL)); + vTaskDelay(pdMS_TO_TICKS(10)); + async_memcpy_verify_and_clear_testbench(test_context.seed, test_context.copy_size, test_context.src_buf, + test_context.dst_buf, test_context.from_addr, test_context.to_addr); + } + +#if !TEST_MEMCPY_BUFFER_SIZE_MUST_ALIGN_CACHE + uint32_t unaligned_test_buffer_size[] = {255, 511, 1023, 2047, 4095, 5011}; + for (int i = 0; i < sizeof(unaligned_test_buffer_size) / sizeof(unaligned_test_buffer_size[0]); i++) { // Test different align edge for (int off = 0; off < 4; off++) { - test_context.buffer_size = test_buffer_len[i]; + test_context.buffer_size = unaligned_test_buffer_size[i]; test_context.seed = i; test_context.offset = off; async_memcpy_setup_testbench(&test_context); @@ -152,6 +167,7 @@ static void test_memory_copy_one_by_one(async_memcpy_handle_t driver) test_context.dst_buf, test_context.from_addr, test_context.to_addr); } } +#endif } TEST_CASE("memory copy by DMA one by one", "[async mcp]") @@ -200,7 +216,7 @@ TEST_CASE("memory copy done callback", "[async mcp]") async_memcpy_handle_t driver = NULL; TEST_ESP_OK(esp_async_memcpy_install(&config, &driver)); - uint8_t *src_buf = heap_caps_malloc(256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + uint8_t *src_buf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); // destination address should aligned to data cache line uint8_t *dst_buf = heap_caps_aligned_alloc(TEST_MEMCPY_DST_BASE_ALIGN, 256, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); @@ -239,6 +255,7 @@ TEST_CASE("memory copy by DMA on the fly", "[async mcp]") async_memcpy_verify_and_clear_testbench(i, test_context[i].copy_size, test_context[i].src_buf, test_context[i].dst_buf, test_context[i].from_addr, test_context[i].to_addr); } +#if !TEST_MEMCPY_BUFFER_SIZE_MUST_ALIGN_CACHE // Non-aligned case for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) { test_context[i].seed = i; @@ -252,6 +269,7 @@ TEST_CASE("memory copy by DMA on the fly", "[async mcp]") for (int i = 0; i < sizeof(test_buffer_len) / sizeof(test_buffer_len[0]); i++) { async_memcpy_verify_and_clear_testbench(i, test_context[i].copy_size, test_context[i].src_buf, test_context[i].dst_buf, test_context[i].from_addr, test_context[i].to_addr); } +#endif TEST_ESP_OK(esp_async_memcpy_uninstall(driver)); } diff --git a/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c new file mode 100644 index 00000000000..3ffe52c1122 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c @@ -0,0 +1,517 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "esp_private/dw_gdma.h" +#include "hal/dw_gdma_ll.h" +#include "esp_cache.h" + +TEST_CASE("DW_GDMA channel allocation", "[DW_GDMA]") +{ + printf("install DMA channels exhaustively\r\n"); + dw_gdma_channel_static_config_t static_config = { + .block_transfer_type = DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS, + .role = DW_GDMA_ROLE_MEM, + .num_outstanding_requests = 1, + }; + dw_gdma_channel_alloc_config_t alloc_config = { + .src = static_config, + .dst = static_config, + }; + dw_gdma_channel_handle_t chans[DW_GDMA_LL_GROUPS][DW_GDMA_LL_CHANNELS_PER_GROUP]; + for (int i = 0; i < DW_GDMA_LL_GROUPS; i++) { + for (int j = 0; j < DW_GDMA_LL_CHANNELS_PER_GROUP; j++) { + TEST_ESP_OK(dw_gdma_new_channel(&alloc_config, &chans[i][j])); + } + } + TEST_ESP_ERR(ESP_ERR_NOT_FOUND, dw_gdma_new_channel(&alloc_config, &chans[0][0])); + + printf("delete DMA channels\r\n"); + for (int i = 0; i < DW_GDMA_LL_GROUPS; i++) { + for (int j = 0; j < DW_GDMA_LL_CHANNELS_PER_GROUP; j++) { + TEST_ESP_OK(dw_gdma_del_channel(chans[i][j])); + } + } +} + +static bool test_dw_gdma_conti_mode_trans_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data) +{ + BaseType_t task_woken = pdFALSE; + SemaphoreHandle_t done_sem = (SemaphoreHandle_t)user_data; + xSemaphoreGiveFromISR(done_sem, &task_woken); + return task_woken == pdTRUE; +} + +TEST_CASE("DW_GDMA M2M Test: Contiguous Mode", "[DW_GDMA]") +{ + SemaphoreHandle_t done_sem = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(done_sem); + + printf("prepare the source and destination buffers\r\n"); + uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(src_buf); + TEST_ASSERT_NOT_NULL(dst_buf); + for (int i = 0; i < 256; i++) { + src_buf[i] = i; + } +#if CONFIG_IDF_TARGET_ESP32P4 + // do write-back for the source data because it's in the cache + TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); +#endif + + printf("allocate a channel for memory copy\r\n"); + dw_gdma_channel_static_config_t static_config = { + .block_transfer_type = DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS, + .role = DW_GDMA_ROLE_MEM, + .num_outstanding_requests = 1, + }; + dw_gdma_channel_alloc_config_t alloc_config = { + .src = static_config, + .dst = static_config, + .flow_controller = DW_GDMA_FLOW_CTRL_SELF, // DMA as the flow controller + .chan_priority = 1, + }; + dw_gdma_channel_handle_t m2m_chan = NULL; + TEST_ESP_OK(dw_gdma_new_channel(&alloc_config, &m2m_chan)); + + printf("register event handler\r\n"); + dw_gdma_event_callbacks_t cbs = { + .on_full_trans_done = test_dw_gdma_conti_mode_trans_done_cb, + }; + TEST_ESP_OK(dw_gdma_channel_register_event_callbacks(m2m_chan, &cbs, done_sem)); + + printf("set up memory copy transaction\r\n"); + dw_gdma_block_transfer_config_t transfer_config = { + .src = { + .addr = (uint32_t)src_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .dst = { + .addr = (uint32_t)dst_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .size = 256, + }; + TEST_ESP_OK(dw_gdma_channel_config_transfer(m2m_chan, &transfer_config)); + + printf("start the DMA engine\r\n"); + TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true)); + + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100))); + // DMA should stop after the first block transfer is done + TEST_ASSERT_EQUAL(pdFALSE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100))); + + printf("check the memory copy result\r\n"); +#if CONFIG_IDF_TARGET_ESP32P4 + // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data + TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C)); +#endif + for (int i = 0; i < 256; i++) { + TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]); + } + + TEST_ESP_OK(dw_gdma_del_channel(m2m_chan)); + free(src_buf); + free(dst_buf); + vSemaphoreDelete(done_sem); +} + +static bool test_dw_gdma_reload_mode_block_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data) +{ + BaseType_t task_woken = pdFALSE; + SemaphoreHandle_t done_sem = (SemaphoreHandle_t)user_data; + xSemaphoreGiveFromISR(done_sem, &task_woken); + return task_woken == pdTRUE; +} + +TEST_CASE("DW_GDMA M2M Test: Reload Mode", "[DW_GDMA]") +{ + SemaphoreHandle_t done_sem = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(done_sem); + + printf("prepare the source and destination buffers\r\n"); + uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(src_buf); + TEST_ASSERT_NOT_NULL(dst_buf); + for (int i = 0; i < 256; i++) { + src_buf[i] = i; + } +#if CONFIG_IDF_TARGET_ESP32P4 + // do write-back for the source data because it's in the cache + TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); +#endif + + printf("allocate a channel for memory copy\r\n"); + dw_gdma_channel_static_config_t static_config = { + .block_transfer_type = DW_GDMA_BLOCK_TRANSFER_RELOAD, + .role = DW_GDMA_ROLE_MEM, + .num_outstanding_requests = 1, + }; + dw_gdma_channel_alloc_config_t alloc_config = { + .src = static_config, + .dst = static_config, + .flow_controller = DW_GDMA_FLOW_CTRL_SELF, // DMA as the flow controller + .chan_priority = 1, + }; + dw_gdma_channel_handle_t m2m_chan = NULL; + TEST_ESP_OK(dw_gdma_new_channel(&alloc_config, &m2m_chan)); + + printf("register event handler\r\n"); + dw_gdma_event_callbacks_t cbs = { + .on_block_trans_done = test_dw_gdma_reload_mode_block_done_cb, + }; + TEST_ESP_OK(dw_gdma_channel_register_event_callbacks(m2m_chan, &cbs, done_sem)); + + printf("set up memory copy transaction\r\n"); + dw_gdma_block_transfer_config_t transfer_config = { + .src = { + .addr = (uint32_t)src_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .dst = { + .addr = (uint32_t)dst_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .size = 256, + }; + TEST_ESP_OK(dw_gdma_channel_config_transfer(m2m_chan, &transfer_config)); + + dw_gdma_block_markers_t markers = { + .en_trans_done_intr = true, // enable block trans done interrupt + }; + TEST_ESP_OK(dw_gdma_channel_set_block_markers(m2m_chan, markers)); + + printf("start the DMA engine\r\n"); + TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true)); + + // because of the auto-reload, we can keep receiving the block trans done event + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100))); + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100))); + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(100))); + + printf("check the memory copy result\r\n"); +#if CONFIG_IDF_TARGET_ESP32P4 + // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data + TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C)); +#endif + for (int i = 0; i < 256; i++) { + TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]); + } + + // stop the DMA channel + TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, false)); + TEST_ESP_OK(dw_gdma_del_channel(m2m_chan)); + free(src_buf); + free(dst_buf); + vSemaphoreDelete(done_sem); +} + +typedef struct { + SemaphoreHandle_t done_sem; + uint8_t count; +} test_gdma_shadow_mode_user_data_t; + +static bool test_dw_gdma_shadow_mode_block_invalid_cb(dw_gdma_channel_handle_t chan, const dw_gdma_break_event_data_t *event_data, void *user_data) +{ + BaseType_t task_woken = pdFALSE; + test_gdma_shadow_mode_user_data_t *udata = (test_gdma_shadow_mode_user_data_t *)user_data; + udata->count++; + + dw_gdma_block_markers_t markers = { + .is_last = true, // mark the block as the last one + .is_valid = true, // mark the block as valid so that the DMA can continue the transfer + }; + dw_gdma_channel_set_block_markers(chan, markers); + // after the block is marked as valid again, tell the DMA to continue the transfer + dw_gdma_channel_continue(chan); + return task_woken == pdTRUE; +} + +static bool test_dw_gdma_shadow_mode_trans_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data) +{ + BaseType_t task_woken = pdFALSE; + test_gdma_shadow_mode_user_data_t *udata = (test_gdma_shadow_mode_user_data_t *)user_data; + SemaphoreHandle_t done_sem = udata->done_sem; + xSemaphoreGiveFromISR(done_sem, &task_woken); + return task_woken == pdTRUE; +} + +TEST_CASE("DW_GDMA M2M Test: Shadow Mode", "[DW_GDMA]") +{ + SemaphoreHandle_t done_sem = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(done_sem); + + printf("prepare the source and destination buffers\r\n"); + uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(src_buf); + TEST_ASSERT_NOT_NULL(dst_buf); + for (int i = 0; i < 256; i++) { + src_buf[i] = i; + } +#if CONFIG_IDF_TARGET_ESP32P4 + // do write-back for the source data because it's in the cache + TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); +#endif + + printf("allocate a channel for memory copy\r\n"); + dw_gdma_channel_static_config_t static_config = { + .block_transfer_type = DW_GDMA_BLOCK_TRANSFER_SHADOW, + .role = DW_GDMA_ROLE_MEM, + .num_outstanding_requests = 1, + }; + dw_gdma_channel_alloc_config_t alloc_config = { + .src = static_config, + .dst = static_config, + .flow_controller = DW_GDMA_FLOW_CTRL_SELF, // DMA as the flow controller + .chan_priority = 1, + }; + dw_gdma_channel_handle_t m2m_chan = NULL; + TEST_ESP_OK(dw_gdma_new_channel(&alloc_config, &m2m_chan)); + + printf("set up memory copy transaction\r\n"); + dw_gdma_block_transfer_config_t transfer_config = { + .src = { + .addr = (uint32_t)src_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .dst = { + .addr = (uint32_t)dst_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .size = 256, + }; + TEST_ESP_OK(dw_gdma_channel_config_transfer(m2m_chan, &transfer_config)); + dw_gdma_block_markers_t markers = { + .is_valid = true, // mark the block as valid so that the DMA can start the transfer + }; + TEST_ESP_OK(dw_gdma_channel_set_block_markers(m2m_chan, markers)); + + printf("register event handler\r\n"); + dw_gdma_event_callbacks_t cbs = { + .on_invalid_block = test_dw_gdma_shadow_mode_block_invalid_cb, + .on_full_trans_done = test_dw_gdma_shadow_mode_trans_done_cb, + }; + test_gdma_shadow_mode_user_data_t user_data = { + .done_sem = done_sem, + .count = 0, + }; + TEST_ESP_OK(dw_gdma_channel_register_event_callbacks(m2m_chan, &cbs, &user_data)); + + printf("start the DMA engine\r\n"); + TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true)); + + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(1000))); + // should only go into the block invalid callback for once + TEST_ASSERT_EQUAL_UINT8(1, user_data.count); + + printf("check the memory copy result\r\n"); +#if CONFIG_IDF_TARGET_ESP32P4 + // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data + TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C)); +#endif + for (int i = 0; i < 256; i++) { + TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]); + } + + TEST_ESP_OK(dw_gdma_del_channel(m2m_chan)); + free(src_buf); + free(dst_buf); + vSemaphoreDelete(done_sem); +} + +typedef struct { + SemaphoreHandle_t done_sem; + void *dst_buffer_addr; + size_t dst_buffer_size; + uint8_t count; +} test_gdma_list_mode_user_data_t; + +static bool test_dw_gdma_list_mode_trans_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data) +{ + BaseType_t task_woken = pdFALSE; + test_gdma_list_mode_user_data_t *udata = (test_gdma_list_mode_user_data_t *)user_data; + SemaphoreHandle_t done_sem = udata->done_sem; + xSemaphoreGiveFromISR(done_sem, &task_woken); + return task_woken == pdTRUE; +} + +static bool test_dw_gdma_list_mode_invalid_block_cb(dw_gdma_channel_handle_t chan, const dw_gdma_break_event_data_t *event_data, void *user_data) +{ + test_gdma_list_mode_user_data_t *udata = (test_gdma_list_mode_user_data_t *)user_data; + dw_gdma_lli_handle_t lli = event_data->invalid_lli; + udata->count++; + // clear the destination buffer + memset(udata->dst_buffer_addr, 0, udata->dst_buffer_size); + dw_gdma_block_markers_t markers = { + .is_last = true, // mark the next block as the last one + .is_valid = true, // mark the block as valid so that the DMA can continue the transfer + }; + dw_gdma_lli_set_block_markers(lli, markers); + // after the item is marked as valid again, tell the DMA to continue the transfer + dw_gdma_channel_continue(chan); + return false; +} + +TEST_CASE("DW_GDMA M2M Test: Link-List Mode", "[DW_GDMA]") +{ + SemaphoreHandle_t done_sem = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(done_sem); + + printf("prepare the source and destination buffers\r\n"); + uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + uint8_t *dst_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(src_buf); + TEST_ASSERT_NOT_NULL(dst_buf); + for (int i = 0; i < 256; i++) { + src_buf[i] = i; + } +#if CONFIG_IDF_TARGET_ESP32P4 + // do write-back for the source data because it's in the cache + TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M)); +#endif + + printf("allocate a channel for memory copy\r\n"); + dw_gdma_channel_static_config_t static_config = { + .block_transfer_type = DW_GDMA_BLOCK_TRANSFER_LIST, + .role = DW_GDMA_ROLE_MEM, + .num_outstanding_requests = 1, + }; + dw_gdma_channel_alloc_config_t alloc_config = { + .src = static_config, + .dst = static_config, + .flow_controller = DW_GDMA_FLOW_CTRL_SELF, // DMA as the flow controller + .chan_priority = 1, + }; + dw_gdma_channel_handle_t m2m_chan = NULL; + TEST_ESP_OK(dw_gdma_new_channel(&alloc_config, &m2m_chan)); + + printf("create singly DMA link list\r\n"); + dw_gdma_link_list_config_t link_list_config = { + .num_items = 2, + .link_type = DW_GDMA_LINKED_LIST_TYPE_SINGLY, + }; + dw_gdma_link_list_handle_t link_list = NULL; + TEST_ESP_OK(dw_gdma_new_link_list(&link_list_config, &link_list)); + + printf("set up memory copy transaction\r\n"); + dw_gdma_block_transfer_config_t transfer_config = { + .src = { + .addr = (uint32_t)src_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .dst = { + .addr = (uint32_t)dst_buf, + .burst_mode = DW_GDMA_BURST_MODE_INCREMENT, + .width = DW_GDMA_TRANS_WIDTH_8, + .burst_items = 4, + .burst_len = 0, + }, + .size = 128, + }; + dw_gdma_block_markers_t markers = { + .is_valid = true, // mark the block as valid so that the DMA can start the transfer + }; + TEST_ESP_OK(dw_gdma_lli_config_transfer(dw_gdma_link_list_get_item(link_list, 0), &transfer_config)); + TEST_ESP_OK(dw_gdma_lli_set_block_markers(dw_gdma_link_list_get_item(link_list, 0), markers)); + transfer_config.src.addr = (uint32_t)(src_buf + 128); + transfer_config.dst.addr = (uint32_t)(dst_buf + 128); + markers.is_last = true; + TEST_ESP_OK(dw_gdma_lli_config_transfer(dw_gdma_link_list_get_item(link_list, 1), &transfer_config)); + TEST_ESP_OK(dw_gdma_lli_set_block_markers(dw_gdma_link_list_get_item(link_list, 1), markers)); + + printf("register event handler\r\n"); + dw_gdma_event_callbacks_t cbs = { + .on_full_trans_done = test_dw_gdma_list_mode_trans_done_cb, + .on_invalid_block = test_dw_gdma_list_mode_invalid_block_cb, + }; + test_gdma_list_mode_user_data_t user_data = { + .done_sem = done_sem, + .count = 0, + .dst_buffer_addr = dst_buf, + .dst_buffer_size = 256, + }; + TEST_ESP_OK(dw_gdma_channel_register_event_callbacks(m2m_chan, &cbs, &user_data)); + + printf("use the link list\r\n"); + TEST_ESP_OK(dw_gdma_channel_use_link_list(m2m_chan, link_list)); + printf("start the DMA engine\r\n"); + TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true)); + + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(1000))); + + printf("check the memory copy result\r\n"); +#if CONFIG_IDF_TARGET_ESP32P4 + // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data + TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C)); +#endif + for (int i = 0; i < 256; i++) { + TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]); + } + + // delete the singly link list, and create a circular link list instead + TEST_ESP_OK(dw_gdma_del_link_list(link_list)); + printf("create circular DMA link list\r\n"); + link_list_config.link_type = DW_GDMA_LINKED_LIST_TYPE_CIRCULAR; + link_list_config.num_items = 1; + TEST_ESP_OK(dw_gdma_new_link_list(&link_list_config, &link_list)); + // set the transfer parameters for the link list item + transfer_config.size = 256; + transfer_config.src.addr = (uint32_t)src_buf; + transfer_config.dst.addr = (uint32_t)dst_buf; + TEST_ESP_OK(dw_gdma_lli_config_transfer(dw_gdma_link_list_get_item(link_list, 0), &transfer_config)); + markers.is_valid = true; + markers.is_last = false; + TEST_ESP_OK(dw_gdma_lli_set_block_markers(dw_gdma_link_list_get_item(link_list, 0), markers)); + + printf("use the link list\r\n"); + TEST_ESP_OK(dw_gdma_channel_use_link_list(m2m_chan, link_list)); + TEST_ESP_OK(dw_gdma_channel_enable_ctrl(m2m_chan, true)); + + TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(done_sem, pdMS_TO_TICKS(1000))); + + printf("check the memory copy result\r\n"); +#if CONFIG_IDF_TARGET_ESP32P4 + // the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data + TEST_ESP_OK(esp_cache_msync((void *)dst_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_M2C)); +#endif + for (int i = 0; i < 256; i++) { + TEST_ASSERT_EQUAL_UINT8(i, dst_buf[i]); + } + + TEST_ESP_OK(dw_gdma_del_link_list(link_list)); + TEST_ESP_OK(dw_gdma_del_channel(m2m_chan)); + free(src_buf); + free(dst_buf); + vSemaphoreDelete(done_sem); +} diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt index 0f499f0d84f..40a5a7555bc 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt @@ -8,6 +8,10 @@ set(srcs "test_app_main.c" "test_random.c" ) +if(CONFIG_SOC_MULTI_USAGE_LDO_SUPPORTED) + list(APPEND srcs "test_ldo.c") +endif() + if(CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX OR CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX) list(APPEND srcs "test_esp_clock_output.c") endif() @@ -15,5 +19,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - REQUIRES unity driver test_utils efuse + REQUIRES unity esp_driver_gpio esp_driver_gptimer esp_driver_uart test_utils efuse WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c index 6c8494e57be..755d75a94a2 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c @@ -17,7 +17,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" -#include "freertos/xtensa_timer.h" +#include "xtensa_timer.h" #include "driver/uart.h" #include "unity.h" #include "test_utils.h" diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S index 2e7b15fceae..40589b11923 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S @@ -9,7 +9,7 @@ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_private/panic_reason.h" #include "soc/soc.h" #include "soc/dport_reg.h" diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c new file mode 100644 index 00000000000..47c806bcb3d --- /dev/null +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "sdkconfig.h" +#include "unity.h" +#include "esp_private/esp_ldo.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +TEST_CASE("LDO unit early / normal allocation", "[LDO]") +{ + esp_ldo_unit_init_cfg_t init_early_unit_cfg = { + .unit_id = ESP_LDO_ID_3, + .cfg = { + .voltage_mv = 1800, + }, + .flags.enable_unit = true, + }; + esp_ldo_unit_handle_t early_unit = esp_ldo_init_unit_early(&init_early_unit_cfg); + TEST_ASSERT(esp_ldo_enable_unit(early_unit) == ESP_ERR_INVALID_STATE); + TEST_ESP_OK(esp_ldo_disable_unit(early_unit)); + + esp_ldo_unit_handle_t unit = NULL; + esp_ldo_unit_init_cfg_t init_unit_cfg = { + .unit_id = ESP_LDO_ID_4, + .cfg = { + .voltage_mv = 2500, + }, + }; + TEST_ESP_OK(esp_ldo_init_unit(&init_unit_cfg, &unit)); + TEST_ESP_OK(esp_ldo_enable_unit(unit)); + TEST_ESP_OK(esp_ldo_disable_unit(unit)); + + init_unit_cfg.flags.shared_ldo = true; + esp_ldo_unit_handle_t shared_unit = NULL; + TEST_ESP_OK(esp_ldo_init_unit(&init_unit_cfg, &shared_unit)); + + TEST_ESP_OK(esp_ldo_deinit_unit(early_unit)); + TEST_ESP_OK(esp_ldo_deinit_unit(shared_unit)); + TEST_ESP_OK(esp_ldo_deinit_unit(unit)); +} + +TEST_CASE("LDO unit output", "[LDO][mannual][ignore]") +{ + esp_ldo_unit_init_cfg_t early_unit_cfg = { + .unit_id = ESP_LDO_ID_2, + .cfg = { + .voltage_mv = 2500, + }, + .flags.enable_unit = true, + }; + esp_ldo_unit_handle_t early_unit2 = esp_ldo_init_unit_early(&early_unit_cfg); + assert(early_unit2); + + early_unit_cfg.unit_id = ESP_LDO_ID_3; + early_unit_cfg.cfg.voltage_mv = 3300; + esp_ldo_unit_handle_t early_unit3 = esp_ldo_init_unit_early(&early_unit_cfg); + assert(early_unit3); + + early_unit_cfg.unit_id = ESP_LDO_ID_4; + early_unit_cfg.cfg.voltage_mv = 1100; + esp_ldo_unit_handle_t early_unit4 = esp_ldo_init_unit_early(&early_unit_cfg); + assert(early_unit4); + + esp_ldo_usage_dump(stdout); + + while (1) { + vTaskDelay(1); + } +} diff --git a/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt b/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt index 7b84296f731..214712238d3 100644 --- a/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt @@ -30,5 +30,5 @@ endif() # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} PRIV_REQUIRES unity esp_timer esp_driver_gptimer esp_driver_gpio - driver # TODO: replace with esp_driver_mcpwm (IDF-8379), esp_driver_ana_cmpr + esp_driver_mcpwm esp_driver_ana_cmpr WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/etm/main/test_gdma_etm.c b/components/esp_hw_support/test_apps/etm/main/test_gdma_etm.c index 82f66383c76..3ecedea8585 100644 --- a/components/esp_hw_support/test_apps/etm/main/test_gdma_etm.c +++ b/components/esp_hw_support/test_apps/etm/main/test_gdma_etm.c @@ -61,9 +61,9 @@ TEST_CASE("async_memcpy_eof_event", "[etm]") TEST_ESP_OK(esp_etm_dump(stdout)); const uint32_t buffer_size = 1024; - uint8_t *src_buf = heap_caps_malloc(buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + uint8_t *src_buf = heap_caps_aligned_alloc(64, buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); TEST_ASSERT_NOT_NULL(src_buf); - uint8_t *dst_buf = heap_caps_malloc(buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); + uint8_t *dst_buf = heap_caps_aligned_alloc(64, buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); TEST_ASSERT_NOT_NULL(dst_buf); printf("start memcpy\r\n"); diff --git a/components/esp_hw_support/test_apps/rtc_8md256/main/CMakeLists.txt b/components/esp_hw_support/test_apps/rtc_8md256/main/CMakeLists.txt index 3e8fc6861e3..c99a60f5ac5 100644 --- a/components/esp_hw_support/test_apps/rtc_8md256/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/rtc_8md256/main/CMakeLists.txt @@ -4,5 +4,5 @@ set(srcs "test_app_main.c" # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver + PRIV_REQUIRES unity esp_driver_uart WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt b/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt index 37e22584de9..a9565cef393 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt @@ -4,5 +4,5 @@ set(srcs "test_app_main.c" # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - REQUIRES unity driver test_utils + REQUIRES unity esp_driver_gpio test_utils WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/rtc_power_modes/main/CMakeLists.txt b/components/esp_hw_support/test_apps/rtc_power_modes/main/CMakeLists.txt index 802123e7983..ae51e0fd580 100644 --- a/components/esp_hw_support/test_apps/rtc_power_modes/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/rtc_power_modes/main/CMakeLists.txt @@ -4,5 +4,5 @@ set(srcs "test_app_main.c" # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity driver + PRIV_REQUIRES unity esp_driver_uart driver WHOLE_ARCHIVE) diff --git a/components/esp_lcd/CMakeLists.txt b/components/esp_lcd/CMakeLists.txt index aa0595a54db..d748393fab8 100644 --- a/components/esp_lcd/CMakeLists.txt +++ b/components/esp_lcd/CMakeLists.txt @@ -18,6 +18,7 @@ set(priv_requires "esp_mm" "esp_psram") if(CONFIG_SOC_I2S_LCD_I80_VARIANT) list(APPEND srcs "src/esp_lcd_panel_io_i2s.c") + list(APPEND priv_requires "esp_driver_i2s") endif() if(CONFIG_SOC_LCDCAM_SUPPORTED) @@ -27,5 +28,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_REQUIRES ${priv_requires} - REQUIRES driver esp_driver_gpio + REQUIRES driver esp_driver_gpio esp_driver_spi esp_driver_i2c LDFRAGMENTS linker.lf) diff --git a/components/esp_lcd/include/esp_lcd_panel_io.h b/components/esp_lcd/include/esp_lcd_panel_io.h index 7fe5bc97470..4a6e7c45e54 100644 --- a/components/esp_lcd/include/esp_lcd_panel_io.h +++ b/components/esp_lcd/include/esp_lcd_panel_io.h @@ -13,6 +13,8 @@ #include "hal/i2c_types.h" #include "driver/i2c_types.h" +#define ESP_LCD_I80_BUS_WIDTH_MAX 16 /*!< Maximum width of I80 bus */ + #ifdef __cplusplus extern "C" { #endif @@ -231,7 +233,7 @@ typedef struct { int dc_gpio_num; /*!< GPIO used for D/C line */ int wr_gpio_num; /*!< GPIO used for WR line */ lcd_clock_source_t clk_src; /*!< Clock source for the I80 LCD peripheral */ - int data_gpio_nums[SOC_LCD_I80_BUS_WIDTH]; /*!< GPIOs used for data lines */ + int data_gpio_nums[ESP_LCD_I80_BUS_WIDTH_MAX]; /*!< GPIOs used for data lines */ size_t bus_width; /*!< Number of data lines, 8 or 16 */ size_t max_transfer_bytes; /*!< Maximum transfer size, this determines the length of internal DMA link */ size_t psram_trans_align; /*!< DMA transfer alignment for data allocated from PSRAM */ diff --git a/components/esp_lcd/include/esp_lcd_panel_rgb.h b/components/esp_lcd/include/esp_lcd_panel_rgb.h index a58cdd6240e..3b0bdbb933c 100644 --- a/components/esp_lcd/include/esp_lcd_panel_rgb.h +++ b/components/esp_lcd/include/esp_lcd_panel_rgb.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_lcd/src/esp_lcd_common.h b/components/esp_lcd/src/esp_lcd_common.h index f036bc5fa8f..ecce3c62d9b 100644 --- a/components/esp_lcd/src/esp_lcd_common.h +++ b/components/esp_lcd/src/esp_lcd_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,12 @@ extern "C" { #define LCD_PERIPH_CLOCK_PRE_SCALE (2) // This is the minimum divider that can be applied to LCD peripheral +#if SOC_PERIPH_CLK_CTRL_SHARED +#define LCD_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define LCD_CLOCK_SRC_ATOMIC() +#endif + #if SOC_LCDCAM_SUPPORTED typedef enum { diff --git a/components/esp_lcd/src/esp_lcd_panel_io_i2s.c b/components/esp_lcd/src/esp_lcd_panel_io_i2s.c index a835f26558f..c146c94d0f6 100644 --- a/components/esp_lcd/src/esp_lcd_panel_io_i2s.c +++ b/components/esp_lcd/src/esp_lcd_panel_io_i2s.c @@ -128,7 +128,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc esp_err_t ret = ESP_OK; esp_lcd_i80_bus_t *bus = NULL; ESP_GOTO_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - // although I2S bus supports up to 24 parallel data lines, we restrict users to only use 8 or 16 bit width, due to limited GPIO numbers + // although I2S bus supports up to 24 parallel data lines, we restrict users to only use 8 or 16 bit width ESP_GOTO_ON_FALSE(bus_config->bus_width == 8 || bus_config->bus_width == 16, ESP_ERR_INVALID_ARG, err, TAG, "invalid bus width:%d", bus_config->bus_width); size_t max_transfer_bytes = (bus_config->max_transfer_bytes + 3) & ~0x03; // align up to 4 bytes diff --git a/components/esp_lcd/src/esp_lcd_panel_io_i80.c b/components/esp_lcd/src/esp_lcd_panel_io_i80.c index d90d57fe36a..5f2911e5737 100644 --- a/components/esp_lcd/src/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/src/esp_lcd_panel_io_i80.c @@ -131,7 +131,10 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc #endif esp_err_t ret = ESP_OK; esp_lcd_i80_bus_t *bus = NULL; - ESP_GOTO_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + // although LCD_CAM can support up to 24 data lines, we restrict users to only use 8 or 16 bit width + ESP_RETURN_ON_FALSE(bus_config->bus_width == 8 || bus_config->bus_width == 16, ESP_ERR_INVALID_ARG, + TAG, "invalid bus width:%d", bus_config->bus_width); size_t num_dma_nodes = bus_config->max_transfer_bytes / DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1; // DMA descriptors must be placed in internal SRAM bus = heap_caps_calloc(1, sizeof(esp_lcd_i80_bus_t) + num_dma_nodes * sizeof(dma_descriptor_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA); @@ -153,13 +156,15 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc } // initialize HAL layer, so we can call LL APIs later lcd_hal_init(&bus->hal, bus_id); - // reset peripheral and FIFO - lcd_ll_reset(bus->hal.dev); - lcd_ll_fifo_reset(bus->hal.dev); - lcd_ll_enable_clock(bus->hal.dev, true); + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_enable_clock(bus->hal.dev, true); + } // set peripheral clock resolution ret = lcd_i80_select_periph_clock(bus, bus_config->clk_src); ESP_GOTO_ON_ERROR(ret, err, TAG, "select periph clock %d failed", bus_config->clk_src); + // reset peripheral and FIFO after we select a correct clock source + lcd_ll_reset(bus->hal.dev); + lcd_ll_fifo_reset(bus->hal.dev); // install interrupt service, (LCD peripheral shares the same interrupt source with Camera peripheral with different mask) // interrupt is disabled by default int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; @@ -172,12 +177,17 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc // install DMA service bus->psram_trans_align = bus_config->psram_trans_align; bus->sram_trans_align = bus_config->sram_trans_align; + bus->bus_width = bus_config->bus_width; ret = lcd_i80_init_dma_link(bus); ESP_GOTO_ON_ERROR(ret, err, TAG, "install DMA failed"); - // enable 8080 mode and set bus width + // disable RGB-LCD mode lcd_ll_enable_rgb_mode(bus->hal.dev, false); - lcd_ll_set_data_width(bus->hal.dev, bus_config->bus_width); - bus->bus_width = bus_config->bus_width; + // disable YUV-RGB converter + lcd_ll_enable_rgb_yuv_convert(bus->hal.dev, false); + // set how much data to read from DMA each time + lcd_ll_set_dma_read_stride(bus->hal.dev, bus->bus_width); + // sometime, we need to change the output data order: ABAB->BABA + lcd_ll_set_swizzle_mode(bus->hal.dev, LCD_LL_SWIZZLE_AB2BA); // number of data cycles is controlled by DMA buffer size lcd_ll_enable_output_always_on(bus->hal.dev, true); // enable trans done interrupt @@ -435,8 +445,9 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons // switch devices if necessary lcd_i80_switch_devices(cur_device, next_device); // set data format - lcd_ll_reverse_bit_order(bus->hal.dev, false); - lcd_ll_swap_byte_order(bus->hal.dev, bus->bus_width, next_device->lcd_param_bits > bus->bus_width); + lcd_ll_reverse_dma_data_bit_order(bus->hal.dev, false); + // whether to swap the adjacent data bytes + lcd_ll_enable_swizzle(bus->hal.dev, next_device->lcd_param_bits > bus->bus_width); bus->cur_trans = NULL; bus->cur_device = next_device; // package a transaction @@ -444,8 +455,9 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons trans_desc->i80_device = next_device; trans_desc->cmd_cycles = cmd_cycles; trans_desc->cmd_value = lcd_cmd; - trans_desc->data = param ? bus->format_buffer : NULL; - trans_desc->data_length = param ? param_len : 0; + // either the param is NULL or the param_size is zero, means there isn't a data phase in this transaction + trans_desc->data = (param && param_len) ? bus->format_buffer : NULL; + trans_desc->data_length = trans_desc->data ? param_len : 0; trans_desc->trans_done_cb = NULL; // no callback for parameter transaction // mount data to DMA links lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length); @@ -514,9 +526,11 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), TAG, "get clock source frequency failed"); - // force to use integer division, as fractional division might lead to clock jitter - lcd_ll_select_clk_src(bus->hal.dev, clk_src); - lcd_ll_set_group_clock_coeff(bus->hal.dev, LCD_PERIPH_CLOCK_PRE_SCALE, 0, 0); + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_select_clk_src(bus->hal.dev, clk_src); + // force to use integer division, as fractional division might lead to clock jitter + lcd_ll_set_group_clock_coeff(bus->hal.dev, LCD_PERIPH_CLOCK_PRE_SCALE, 0, 0); + } // save the resolution of the i80 bus bus->resolution_hz = src_clk_hz / LCD_PERIPH_CLOCK_PRE_SCALE; @@ -578,6 +592,8 @@ static esp_err_t lcd_i80_bus_configure_gpio(esp_lcd_i80_bus_handle_t bus, const if (!valid_gpio) { return ESP_ERR_INVALID_ARG; } + // Set the number of output data lines + lcd_ll_set_data_wire_width(bus->hal.dev, bus_config->bus_width); // connect peripheral signals via GPIO matrix for (size_t i = 0; i < bus_config->bus_width; i++) { gpio_set_direction(bus_config->data_gpio_nums[i], GPIO_MODE_OUTPUT); @@ -700,8 +716,8 @@ IRAM_ATTR static void lcd_default_isr_handler(void *args) // switch devices if necessary lcd_i80_switch_devices(cur_device, next_device); // only reverse data bit/bytes for color data - lcd_ll_reverse_bit_order(bus->hal.dev, next_device->flags.reverse_color_bits); - lcd_ll_swap_byte_order(bus->hal.dev, bus->bus_width, next_device->flags.swap_color_bytes); + lcd_ll_reverse_dma_data_bit_order(bus->hal.dev, next_device->flags.reverse_color_bits); + lcd_ll_enable_swizzle(bus->hal.dev, next_device->flags.swap_color_bytes); bus->cur_trans = trans_desc; bus->cur_device = next_device; // mount data to DMA links diff --git a/components/esp_lcd/src/esp_lcd_panel_rgb.c b/components/esp_lcd/src/esp_lcd_panel_rgb.c index 2a5c57d0da4..bfe09699746 100644 --- a/components/esp_lcd/src/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/src/esp_lcd_panel_rgb.c @@ -35,6 +35,7 @@ #include "esp_private/periph_ctrl.h" #include "esp_psram.h" #include "esp_lcd_common.h" +#include "esp_memory_utils.h" #include "soc/lcd_periph.h" #include "hal/lcd_hal.h" #include "hal/lcd_ll.h" @@ -176,7 +177,9 @@ static esp_err_t lcd_rgb_panel_alloc_frame_buffers(const esp_lcd_rgb_panel_confi static esp_err_t lcd_rgb_panel_destory(esp_rgb_panel_t *rgb_panel) { - lcd_ll_enable_clock(rgb_panel->hal.dev, false); + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_enable_clock(rgb_panel->hal.dev, false); + } if (rgb_panel->panel_id >= 0) { PERIPH_RCC_RELEASE_ATOMIC(lcd_periph_signals.panels[rgb_panel->panel_id].module, ref_count) { if (ref_count == 0) { @@ -218,19 +221,20 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf #endif esp_err_t ret = ESP_OK; esp_rgb_panel_t *rgb_panel = NULL; - ESP_GOTO_ON_FALSE(rgb_panel_config && ret_panel, ESP_ERR_INVALID_ARG, err, TAG, "invalid parameter"); - ESP_GOTO_ON_FALSE(rgb_panel_config->data_width == 16 || rgb_panel_config->data_width == 8, - ESP_ERR_NOT_SUPPORTED, err, TAG, "unsupported data width %d", rgb_panel_config->data_width); - ESP_GOTO_ON_FALSE(!(rgb_panel_config->flags.double_fb && rgb_panel_config->flags.no_fb), - ESP_ERR_INVALID_ARG, err, TAG, "double_fb conflicts with no_fb"); - ESP_GOTO_ON_FALSE(!(rgb_panel_config->num_fbs > 0 && rgb_panel_config->num_fbs != 2 && rgb_panel_config->flags.double_fb), - ESP_ERR_INVALID_ARG, err, TAG, "num_fbs conflicts with double_fb"); - ESP_GOTO_ON_FALSE(!(rgb_panel_config->num_fbs > 0 && rgb_panel_config->flags.no_fb), - ESP_ERR_INVALID_ARG, err, TAG, "num_fbs conflicts with no_fb"); - ESP_GOTO_ON_FALSE(!(rgb_panel_config->flags.no_fb && rgb_panel_config->bounce_buffer_size_px == 0), - ESP_ERR_INVALID_ARG, err, TAG, "must set bounce buffer if there's no frame buffer"); - ESP_GOTO_ON_FALSE(!(rgb_panel_config->flags.refresh_on_demand && rgb_panel_config->bounce_buffer_size_px), - ESP_ERR_INVALID_ARG, err, TAG, "refresh on demand is not supported under bounce buffer mode"); + ESP_RETURN_ON_FALSE(rgb_panel_config && ret_panel, ESP_ERR_INVALID_ARG, TAG, "invalid parameter"); + size_t data_width = rgb_panel_config->data_width; + ESP_RETURN_ON_FALSE((data_width >= 8) && (data_width <= SOC_LCD_RGB_DATA_WIDTH) && ((data_width & (data_width - 1)) == 0), ESP_ERR_INVALID_ARG, + TAG, "unsupported data width %d", data_width); + ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.double_fb && rgb_panel_config->flags.no_fb), + ESP_ERR_INVALID_ARG, TAG, "double_fb conflicts with no_fb"); + ESP_RETURN_ON_FALSE(!(rgb_panel_config->num_fbs > 0 && rgb_panel_config->num_fbs != 2 && rgb_panel_config->flags.double_fb), + ESP_ERR_INVALID_ARG, TAG, "num_fbs conflicts with double_fb"); + ESP_RETURN_ON_FALSE(!(rgb_panel_config->num_fbs > 0 && rgb_panel_config->flags.no_fb), + ESP_ERR_INVALID_ARG, TAG, "num_fbs conflicts with no_fb"); + ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.no_fb && rgb_panel_config->bounce_buffer_size_px == 0), + ESP_ERR_INVALID_ARG, TAG, "must set bounce buffer if there's no frame buffer"); + ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.refresh_on_demand && rgb_panel_config->bounce_buffer_size_px), + ESP_ERR_INVALID_ARG, TAG, "refresh on demand is not supported under bounce buffer mode"); // determine number of framebuffers size_t num_fbs = 1; @@ -241,11 +245,11 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf } else if (rgb_panel_config->num_fbs > 0) { num_fbs = rgb_panel_config->num_fbs; } - ESP_GOTO_ON_FALSE(num_fbs <= RGB_LCD_PANEL_MAX_FB_NUM, ESP_ERR_INVALID_ARG, err, TAG, "too many frame buffers"); + ESP_RETURN_ON_FALSE(num_fbs <= RGB_LCD_PANEL_MAX_FB_NUM, ESP_ERR_INVALID_ARG, TAG, "too many frame buffers"); // bpp defaults to the number of data lines, but for serial RGB interface, they're not equal // e.g. for serial RGB 8-bit interface, data lines are 8, whereas the bpp is 24 (RGB888) - size_t fb_bits_per_pixel = rgb_panel_config->data_width; + size_t fb_bits_per_pixel = data_width; if (rgb_panel_config->bits_per_pixel) { // override bpp if it's set fb_bits_per_pixel = rgb_panel_config->bits_per_pixel; } @@ -255,8 +259,8 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf size_t expect_bb_eof_count = 0; if (bb_size) { // we want the bounce can always end in the second buffer - ESP_GOTO_ON_FALSE(fb_size % (2 * bb_size) == 0, ESP_ERR_INVALID_ARG, err, TAG, - "fb size must be even multiple of bounce buffer size"); + ESP_RETURN_ON_FALSE(fb_size % (2 * bb_size) == 0, ESP_ERR_INVALID_ARG, TAG, + "fb size must be even multiple of bounce buffer size"); expect_bb_eof_count = fb_size / bb_size; } @@ -299,11 +303,16 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf // initialize HAL layer, so we can call LL APIs later lcd_hal_init(&rgb_panel->hal, panel_id); - // enable clock gating - lcd_ll_enable_clock(rgb_panel->hal.dev, true); + // enable clock + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_enable_clock(rgb_panel->hal.dev, true); + } // set clock source ret = lcd_rgb_panel_select_clock_src(rgb_panel, rgb_panel_config->clk_src); ESP_GOTO_ON_ERROR(ret, err, TAG, "set source clock failed"); + // reset peripheral and FIFO after we select a correct clock source + lcd_ll_fifo_reset(rgb_panel->hal.dev); + lcd_ll_reset(rgb_panel->hal.dev); // set minimal PCLK divider // A limitation in the hardware, if the LCD_PCLK == LCD_CLK, then the PCLK polarity can't be adjustable if (!(rgb_panel_config->timings.flags.pclk_active_neg || rgb_panel_config->timings.flags.pclk_idle_high)) { @@ -512,13 +521,17 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel) esp_err_t ret = ESP_OK; esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base); // set pixel clock frequency - rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz, rgb_panel->lcd_clk_flags); + hal_utils_clk_div_t lcd_clk_div = {}; + rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz, rgb_panel->lcd_clk_flags, &lcd_clk_div); + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_set_group_clock_coeff(rgb_panel->hal.dev, lcd_clk_div.integer, lcd_clk_div.denominator, lcd_clk_div.numerator); + } // pixel clock phase and polarity lcd_ll_set_clock_idle_level(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_idle_high); lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_active_neg); // enable RGB mode and set data width lcd_ll_enable_rgb_mode(rgb_panel->hal.dev, true); - lcd_ll_set_data_width(rgb_panel->hal.dev, rgb_panel->data_width); + lcd_ll_set_dma_read_stride(rgb_panel->hal.dev, rgb_panel->data_width); lcd_ll_set_phase_cycles(rgb_panel->hal.dev, 0, 0, 1); // enable data phase only // number of data cycles is controlled by DMA buffer size lcd_ll_enable_output_always_on(rgb_panel->hal.dev, true); @@ -829,6 +842,8 @@ static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_ if (!valid_gpio) { return ESP_ERR_INVALID_ARG; } + // Set the number of output data lines + lcd_ll_set_data_wire_width(panel->hal.dev, panel_config->data_width); // connect peripheral signals via GPIO matrix for (size_t i = 0; i < panel_config->data_width; i++) { gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->data_gpio_nums[i]], PIN_FUNC_GPIO); @@ -878,7 +893,9 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_cloc ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), TAG, "get clock source frequency failed"); panel->src_clk_hz = src_clk_hz; - lcd_ll_select_clk_src(panel->hal.dev, clk_src); + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_select_clk_src(panel->hal.dev, clk_src); + } // create pm lock based on different clock source // clock sources like PLL and XTAL will be turned off in light sleep @@ -1099,10 +1116,14 @@ static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel) IRAM_ATTR static void lcd_rgb_panel_try_update_pclk(esp_rgb_panel_t *rgb_panel) { + hal_utils_clk_div_t lcd_clk_div = {}; portENTER_CRITICAL_ISR(&rgb_panel->spinlock); if (unlikely(rgb_panel->flags.need_update_pclk)) { rgb_panel->flags.need_update_pclk = false; - rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz, rgb_panel->lcd_clk_flags); + rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz, rgb_panel->lcd_clk_flags, &lcd_clk_div); + LCD_CLOCK_SRC_ATOMIC() { + lcd_ll_set_group_clock_coeff(rgb_panel->hal.dev, lcd_clk_div.integer, lcd_clk_div.denominator, lcd_clk_div.numerator); + } } portEXIT_CRITICAL_ISR(&rgb_panel->spinlock); } diff --git a/components/esp_lcd/test_apps/.build-test-rules.yml b/components/esp_lcd/test_apps/.build-test-rules.yml index 7067d63dd96..75564d3e091 100644 --- a/components/esp_lcd/test_apps/.build-test-rules.yml +++ b/components/esp_lcd/test_apps/.build-test-rules.yml @@ -5,8 +5,7 @@ components/esp_lcd/test_apps/i2c_lcd: - if: SOC_I2C_SUPPORTED != 1 depends_components: - esp_lcd - depends_filepatterns: - - components/driver/i2c/**/* + - esp_driver_i2c disable_test: - if: IDF_TARGET not in ["esp32c3"] temporary: true @@ -27,8 +26,7 @@ components/esp_lcd/test_apps/i2c_lcd_legacy: components/esp_lcd/test_apps/i80_lcd: depends_components: - esp_lcd - depends_filepatterns: - - components/driver/i2s/**/* # i80 IO driver relies on I2S on esp32 and esp32s2 + - esp_driver_i2s disable: - if: SOC_LCD_I80_SUPPORTED != 1 @@ -41,7 +39,6 @@ components/esp_lcd/test_apps/rgb_lcd: components/esp_lcd/test_apps/spi_lcd: depends_components: - esp_lcd - depends_filepatterns: - - components/driver/spi/**/* + - esp_driver_spi disable: - if: SOC_GPSPI_SUPPORTED != 1 diff --git a/components/esp_lcd/test_apps/i80_lcd/main/CMakeLists.txt b/components/esp_lcd/test_apps/i80_lcd/main/CMakeLists.txt index e6bea3170f2..2a3cea972db 100644 --- a/components/esp_lcd/test_apps/i80_lcd/main/CMakeLists.txt +++ b/components/esp_lcd/test_apps/i80_lcd/main/CMakeLists.txt @@ -4,5 +4,5 @@ set(srcs "test_app_main.c" # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES esp_lcd unity driver + PRIV_REQUIRES esp_lcd unity driver esp_driver_i2s WHOLE_ARCHIVE) diff --git a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe index 8800405f61d..0643ce8884a 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe +++ b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe @@ -6,5 +6,6 @@ CONFIG_GDMA_ISR_IRAM_SAFE=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y # place non-ISR FreeRTOS functions in Flash CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y diff --git a/components/esp_local_ctrl/CMakeLists.txt b/components/esp_local_ctrl/CMakeLists.txt index 92df4d4db98..5c7da2fc496 100644 --- a/components/esp_local_ctrl/CMakeLists.txt +++ b/components/esp_local_ctrl/CMakeLists.txt @@ -11,7 +11,7 @@ set(srcs "src/esp_local_ctrl.c" "proto-c/esp_local_ctrl.pb-c.c") if(CONFIG_BT_ENABLED) - if(CONFIG_BT_BLUEDROID_ENABLED) + if(CONFIG_BT_BLUEDROID_ENABLED OR CONFIG_BT_NIMBLE_ENABLED) list(APPEND srcs "src/esp_local_ctrl_transport_ble.c") endif() diff --git a/components/esp_local_ctrl/include/esp_local_ctrl.h b/components/esp_local_ctrl/include/esp_local_ctrl.h index 2e9a56a0d36..30b00fd0aec 100644 --- a/components/esp_local_ctrl/include/esp_local_ctrl.h +++ b/components/esp_local_ctrl/include/esp_local_ctrl.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -195,7 +195,7 @@ const esp_local_ctrl_transport_t *esp_local_ctrl_get_transport_httpd(void); * @brief Configuration for transport mode BLE * * This is a forward declaration for `protocomm_ble_config_t`. - * To use this, application must set CONFIG_BT_BLUEDROID_ENABLED + * To use this, application must set CONFIG_BT_ENABLED * and include `protocomm_ble.h`. */ typedef struct protocomm_ble_config esp_local_ctrl_transport_config_ble_t; diff --git a/components/esp_mm/cache_esp32.c b/components/esp_mm/cache_esp32.c index c907a057cde..37e0fc537c6 100644 --- a/components/esp_mm/cache_esp32.c +++ b/components/esp_mm/cache_esp32.c @@ -27,7 +27,7 @@ void cache_sync(void) } s_cache_drv.cache_flush(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE s_cache_drv.cache_flush(1); -#endif // !CONFIG_FREERTOS_UNICORE +#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE } diff --git a/components/esp_mm/esp_mmu_map.c b/components/esp_mm/esp_mmu_map.c index 3ac6879917c..ec30c966469 100644 --- a/components/esp_mm/esp_mmu_map.c +++ b/components/esp_mm/esp_mmu_map.c @@ -402,9 +402,9 @@ FORCE_INLINE_ATTR uint32_t s_mapping_operation(mmu_target_t target, uint32_t vad mmu_hal_map_region(0, target, vaddr_start, paddr_start, size, &actual_mapped_len); #if (SOC_MMU_PERIPH_NUM == 2) -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE mmu_hal_map_region(1, target, vaddr_start, paddr_start, size, &actual_mapped_len); -#endif // #if !CONFIG_FREERTOS_UNICORE +#endif // #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #endif // #if (SOC_MMU_PERIPH_NUM == 2) return actual_mapped_len; @@ -424,7 +424,7 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size); cache_ll_l1_enable_bus(0, bus_mask); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size); cache_ll_l1_enable_bus(1, bus_mask); #endif @@ -602,9 +602,9 @@ FORCE_INLINE_ATTR void s_unmapping_operation(uint32_t vaddr_start, uint32_t size { mmu_hal_unmap_region(0, vaddr_start, size); #if (SOC_MMU_PERIPH_NUM == 2) -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE mmu_hal_unmap_region(1, vaddr_start, size); -#endif // #if !CONFIG_FREERTOS_UNICORE +#endif // #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #endif // #if (SOC_MMU_PERIPH_NUM == 2) } #endif diff --git a/components/esp_mm/port/esp32c5/ext_mem_layout.c b/components/esp_mm/port/esp32c5/ext_mem_layout.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_netif/CMakeLists.txt b/components/esp_netif/CMakeLists.txt index 7c6f04e41b6..d1aa21974b8 100644 --- a/components/esp_netif/CMakeLists.txt +++ b/components/esp_netif/CMakeLists.txt @@ -1,5 +1,3 @@ -idf_build_get_property(target IDF_TARGET) - set(srcs_lwip "lwip/esp_netif_lwip.c" "lwip/esp_netif_sntp.c" @@ -17,12 +15,6 @@ set(srcs set(include_dirs "include") set(priv_include_dirs "private_include") -idf_build_get_property(target IDF_TARGET) -if(${target} STREQUAL "linux") - list(APPEND include_dirs - "linux/stubs/include") -endif() - if(CONFIG_PPP_SUPPORT) list(APPEND srcs_lwip lwip/esp_netif_lwip_ppp.c lwip/netif/ppp.c) endif() diff --git a/components/esp_netif/lwip/esp_netif_lwip.c b/components/esp_netif/lwip/esp_netif_lwip.c index ef41ef19e54..7f51aed896e 100644 --- a/components/esp_netif/lwip/esp_netif_lwip.c +++ b/components/esp_netif/lwip/esp_netif_lwip.c @@ -2258,6 +2258,23 @@ esp_err_t esp_netif_dhcps_option_api(esp_netif_api_msg_t *msg) break; } case ESP_NETIF_SUBNET_MASK: { + esp_netif_ip_info_t *default_ip = esp_netif->ip_info; + ip4_addr_t *config_netmask = (ip4_addr_t *)opt->val; + if (!memcmp(&default_ip->netmask, config_netmask, sizeof(struct ip4_addr))) { + ESP_LOGE(TAG, "Please use esp_netif_set_ip_info interface to configure subnet mask"); + /* + * This API directly changes the subnet mask of dhcp server + * but the subnet mask of the network interface has not changed + * If you need to change the subnet mask of dhcp server + * you need to change the subnet mask of the network interface first. + * If the subnet mask of dhcp server is changed + * and the subnet mask of network interface is inconsistent + * with the subnet mask of dhcp sever, it may lead to the failure of sending packets. + * If want to configure the subnet mask of dhcp server + * please use esp_netif_set_ip_info to change the subnet mask of network interface first. + */ + return ESP_ERR_ESP_NETIF_INVALID_PARAMS; + } memcpy(opt_info, opt->val, opt->len); break; } @@ -2298,10 +2315,7 @@ esp_err_t esp_netif_dhcps_option_api(esp_netif_api_msg_t *msg) if ((end_ip - start_ip + 1 > DHCPS_MAX_LEASE) || (start_ip >= end_ip)) { return ESP_ERR_ESP_NETIF_INVALID_PARAMS; } - } else { - return ESP_ERR_ESP_NETIF_INVALID_PARAMS; } - memcpy(opt_info, opt->val, opt->len); break; } diff --git a/components/esp_netif/test_apps/.build-test-rules.yml b/components/esp_netif/test_apps/.build-test-rules.yml index e51cb4f773b..cdab540eee3 100644 --- a/components/esp_netif/test_apps/.build-test-rules.yml +++ b/components/esp_netif/test_apps/.build-test-rules.yml @@ -5,9 +5,18 @@ components/esp_netif/test_apps/test_app_esp_netif: - if: IDF_TARGET not in ["esp32s2", "esp32c3"] temporary: false reason: Not needed to test on all targets (chosen two, one for each architecture) + depends_components: + - esp_netif + - lwip + - esp_eth + - esp_wifi components/esp_netif/test_apps/test_app_vfs_l2tap: disable: - if: SOC_EMAC_SUPPORTED != 1 temporary: false reason: test uses internal EMAC + depends_components: + - esp_netif + - lwip + - esp_eth diff --git a/components/esp_partition/include/esp_partition.h b/components/esp_partition/include/esp_partition.h index b4f8c2d2e5a..f52d1469452 100644 --- a/components/esp_partition/include/esp_partition.h +++ b/components/esp_partition/include/esp_partition.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -459,6 +459,11 @@ esp_err_t esp_partition_register_external(esp_flash_t* flash_chip, size_t offset */ esp_err_t esp_partition_deregister_external(const esp_partition_t* partition); +/** + * @brief Unload partitions and free space allocated by them + */ +void esp_partition_unload_all(void); + #ifdef __cplusplus } #endif diff --git a/components/esp_partition/include/esp_private/partition_linux.h b/components/esp_partition/include/esp_private/partition_linux.h index 673155dd53b..4cbde8d3bba 100644 --- a/components/esp_partition/include/esp_private/partition_linux.h +++ b/components/esp_partition/include/esp_private/partition_linux.h @@ -236,10 +236,6 @@ esp_partition_file_mmap_ctrl_t* esp_partition_get_file_mmap_ctrl_input(void); */ esp_partition_file_mmap_ctrl_t* esp_partition_get_file_mmap_ctrl_act(void); -// private function in partition.c to unload partitions and free space allocated by them -void unload_partitions(void); - - #ifdef __cplusplus } #endif diff --git a/components/esp_partition/partition.c b/components/esp_partition/partition.c index ae4ca4b7ba1..66cc84c2fab 100644 --- a/components/esp_partition/partition.c +++ b/components/esp_partition/partition.c @@ -234,7 +234,7 @@ static esp_err_t load_partitions(void) return err; } -void unload_partitions(void) +void esp_partition_unload_all(void) { _lock_acquire(&s_partition_list_lock); partition_list_item_t *it; diff --git a/components/esp_partition/partition_linux.c b/components/esp_partition/partition_linux.c index 9303498282e..b086e57f65c 100644 --- a/components/esp_partition/partition_linux.c +++ b/components/esp_partition/partition_linux.c @@ -331,7 +331,7 @@ esp_err_t esp_partition_file_munmap(void) return ESP_ERR_NOT_FOUND; } - unload_partitions(); + esp_partition_unload_all(); #ifdef CONFIG_ESP_PARTITION_ENABLE_STATS free(s_esp_partition_stat_sector_erase_count); diff --git a/components/esp_phy/esp32c5/include/.gitkeep b/components/esp_phy/esp32c5/include/.gitkeep new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_phy/lib b/components/esp_phy/lib index a8e8b9532e2..bf6003e60c8 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit a8e8b9532e2874ac167d4ade7808fda70fe05820 +Subproject commit bf6003e60c8bf7205ff16db660df7d7022a284d1 diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index e9c7fad554e..cae9c2fbb4c 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -325,14 +325,18 @@ void IRAM_ATTR esp_wifi_bt_power_domain_on(void) _lock_acquire(&s_wifi_bt_pd_controller.lock); if (s_wifi_bt_pd_controller.count++ == 0) { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); - -#if !CONFIG_IDF_TARGET_ESP32 + esp_rom_delay_us(10); + wifi_bt_common_module_enable(); +#if CONFIG_IDF_TARGET_ESP32 + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); + DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); +#else // modem reset when power on SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU); #endif - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); + wifi_bt_common_module_disable(); } _lock_release(&s_wifi_bt_pd_controller.lock); #endif // !SOC_PMU_SUPPORTED @@ -777,7 +781,11 @@ void esp_phy_load_cal_and_init(void) // Set PHY whether in combo module // For comode mode, phy enable will be not in WiFi RX state #if SOC_PHY_COMBO_MODULE +#if (CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3) phy_init_param_set(0); +#else + phy_init_param_set(1); +#endif #endif esp_phy_calibration_data_t* cal_data = diff --git a/components/esp_pm/CMakeLists.txt b/components/esp_pm/CMakeLists.txt index a4b414e99b2..27ce9ada3cf 100644 --- a/components/esp_pm/CMakeLists.txt +++ b/components/esp_pm/CMakeLists.txt @@ -6,5 +6,5 @@ endif() idf_component_register(SRCS "pm_locks.c" "pm_trace.c" "pm_impl.c" INCLUDE_DIRS include - PRIV_REQUIRES esp_system driver esp_driver_gpio esp_timer + PRIV_REQUIRES esp_system esp_driver_gpio esp_timer LDFRAGMENTS linker.lf) diff --git a/components/esp_pm/Kconfig b/components/esp_pm/Kconfig index 3bfb9e3b243..35a1c000beb 100644 --- a/components/esp_pm/Kconfig +++ b/components/esp_pm/Kconfig @@ -108,21 +108,31 @@ menu "Power Management" config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP bool "Power down CPU in light sleep" depends on SOC_PM_SUPPORT_CPU_PD - select PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB + select PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB default y help - If enabled, the CPU will be powered down in light sleep. On esp32c3 soc, enabling this - option will consume 1.68 KB of internal RAM and will reduce sleep current consumption - by about 100 uA. On esp32s3 soc, enabling this option will consume 8.58 KB of internal - RAM and will reduce sleep current consumption by about 650 uA. - - config PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP - bool "Power down I/D-cache tag memory in light sleep" + If enabled, the CPU will be powered down in light sleep, ESP chips supports saving and restoring CPU's running + context before and after light sleep, the feature provides applications with seamless CPU powerdowned lightsleep + without user awareness. + But this will takes up some internal memory. On esp32c3 soc, enabling this option will consume 1.68 KB of internal + RAM and will reduce sleep current consumption by about 100 uA. On esp32s3 soc, enabling this option will consume + 8.58 KB of internal RAM and will reduce sleep current consumption by about 650 uA. + + config PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP + bool "Restore I/D-cache tag memory after power down CPU light sleep" depends on IDF_TARGET_ESP32S3 && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP default y help - If enabled, the I/D-cache tag memory will be retained in light sleep. Depending on the the - cache configuration, if this option is enabled, it will consume up to 9 KB of internal RAM. + Cache tag memory and CPU both belong to the CPU power domain. ESP chips supports saving and restoring Cache tag memory + before and after sleep, this feature supports accesses to the external memory that was cached before sleep still + be cached when the CPU wakes up from a powerdowned CPU lightsleep. This option controls the restore method for Cache + tag memory in lightsleep. + If this option is enabled, the I/D-cache tag memory will be backuped to the internal RAM before sleep and restored + upon wakeup. Depending on the the cache configuration, if this option is enabled, it will consume up to 9 KB + of internal RAM. + If this option is disabled, all cached data won't be kept after sleep, the DCache will be writeback before + sleep and invalid all cached data after sleep, all accesses to external memory(Flash/PSRAM) will be cache + missed after waking up, resulting in performance degradation due to increased memory accesses latency. config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)" diff --git a/components/esp_pm/include/esp_pm.h b/components/esp_pm/include/esp_pm.h index b7f7d045fdd..cb6919084bb 100644 --- a/components/esp_pm/include/esp_pm.h +++ b/components/esp_pm/include/esp_pm.h @@ -55,6 +55,7 @@ typedef enum { * Argument is unused and should be set to 0. */ ESP_PM_NO_LIGHT_SLEEP, + ESP_PM_LOCK_MAX, } esp_pm_lock_type_t; /** @@ -100,10 +101,13 @@ typedef struct esp_pm_lock* esp_pm_lock_handle_t; * @param[out] out_handle handle returned from this function. Use this handle when calling * esp_pm_lock_delete, esp_pm_lock_acquire, esp_pm_lock_release. * Must not be NULL. + * + * @note If the lock_type argument is not valid, it will cause an abort. + * * @return * - ESP_OK on success * - ESP_ERR_NO_MEM if the lock structure can not be allocated - * - ESP_ERR_INVALID_ARG if out_handle is NULL or type argument is not valid + * - ESP_ERR_INVALID_ARG if out_handle is NULL * - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig */ esp_err_t esp_pm_lock_create(esp_pm_lock_type_t lock_type, int arg, diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf index b1809a422a8..6930c619956 100644 --- a/components/esp_pm/linker.lf +++ b/components/esp_pm/linker.lf @@ -97,5 +97,5 @@ entries: if SOC_PM_CPU_RETENTION_BY_RTCCNTL = y: if PM_SLP_IRAM_OPT = y && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y: rtc_cntl_hal:rtc_cntl_hal_enable_cpu_retention (noflash) - if PM_SLP_IRAM_OPT = y && PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP = y: + if PM_SLP_IRAM_OPT = y && PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP = y: rtc_cntl_hal:rtc_cntl_hal_enable_tagmem_retention (noflash) diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index bbf4eea7b6b..09e42125adc 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -15,20 +15,21 @@ #include "esp_pm.h" #include "esp_log.h" #include "esp_cpu.h" +#include "esp_clk_tree.h" +#include "soc/soc_caps.h" #include "esp_private/crosscore_int.h" -#include "esp_private/uart_private.h" +#include "esp_private/periph_ctrl.h" #include "soc/rtc.h" #include "hal/uart_ll.h" #include "hal/uart_types.h" -#include "driver/uart.h" #include "driver/gpio.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #if CONFIG_FREERTOS_SYSTICK_USES_CCOUNT -#include "freertos/xtensa_timer.h" +#include "xtensa_timer.h" #include "xtensa/core-macros.h" #endif @@ -43,11 +44,17 @@ #include "esp_private/sleep_cpu.h" #include "esp_private/sleep_gpio.h" #include "esp_private/sleep_modem.h" +#include "esp_private/uart_share_hw_ctrl.h" #include "esp_sleep.h" #include "esp_memory_utils.h" #include "sdkconfig.h" +#if SOC_PERIPH_CLK_CTRL_SHARED +#define HP_UART_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define HP_UART_SRC_CLK_ATOMIC() +#endif #define MHZ (1000000) @@ -439,8 +446,11 @@ esp_err_t esp_pm_configure(const void* vconfig) min_freq_mhz, config->light_sleep_enable ? "ENABLED" : "DISABLED"); - portENTER_CRITICAL(&s_switch_lock); + // CPU & Modem power down initialization, which must be initialized before s_light_sleep_en set true, + // to avoid entering idle and sleep in this function. + esp_pm_sleep_configure(config); + portENTER_CRITICAL(&s_switch_lock); bool res __attribute__((unused)); res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]); assert(res); @@ -453,8 +463,6 @@ esp_err_t esp_pm_configure(const void* vconfig) s_config_changed = true; portEXIT_CRITICAL(&s_switch_lock); - esp_pm_sleep_configure(config); - return ESP_OK; } @@ -903,7 +911,7 @@ void esp_pm_impl_init(void) uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source); } uint32_t sclk_freq; - esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq); + esp_err_t err = esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_source, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq); assert(err == ESP_OK); HP_UART_SRC_CLK_ATOMIC() { uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq); diff --git a/components/esp_pm/sdkconfig.rename b/components/esp_pm/sdkconfig.rename index c1ce6dbd66b..ecaaa20a8d7 100644 --- a/components/esp_pm/sdkconfig.rename +++ b/components/esp_pm/sdkconfig.rename @@ -1,3 +1,4 @@ # sdkconfig replacement configurations for deprecated options formatted as # CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c index 5245c7527a2..14c1d5c2cb3 100644 --- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c +++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c @@ -182,7 +182,7 @@ TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]") rtc_gpio_set_level(ext1_wakeup_gpio, 0); /* Enable wakeup */ - TEST_ESP_OK(esp_sleep_enable_ext1_wakeup(1ULL << ext1_wakeup_gpio, ESP_EXT1_WAKEUP_ANY_HIGH)); + TEST_ESP_OK(esp_sleep_enable_ext1_wakeup_io(1ULL << ext1_wakeup_gpio, ESP_EXT1_WAKEUP_ANY_HIGH)); /* To simplify test environment, we'll use a ULP program to set GPIO high */ ulp_insn_t ulp_code[] = { diff --git a/components/esp_psram/Kconfig.spiram.common b/components/esp_psram/Kconfig.spiram.common index 9cce77667c8..dd584a55b41 100644 --- a/components/esp_psram/Kconfig.spiram.common +++ b/components/esp_psram/Kconfig.spiram.common @@ -13,11 +13,19 @@ config SPIRAM_BOOT_INIT config SPIRAM_IGNORE_NOTFOUND bool "Ignore PSRAM when not found" default "n" - depends on SPIRAM_BOOT_INIT && !SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY + depends on SPIRAM_BOOT_INIT && !SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY && !SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY help Normally, if psram initialization is enabled during compile time but not found at runtime, it is seen as an error making the CPU panic. If this is enabled, booting will complete - but no PSRAM will be available. + but no PSRAM will be available. If PSRAM failed to initialize, the following configs may be affected + and may need to be corrected manually. SPIRAM_TRY_ALLOCATE_WIFI_LWIP will affect some LWIP and WiFi buffer + default values and range values. Enable SPIRAM_TRY_ALLOCATE_WIFI_LWIP, ESP_WIFI_AMSDU_TX_ENABLED, + ESP_WIFI_CACHE_TX_BUFFER_NUM and use static WiFi Tx buffer may cause potential memory exhaustion issues. + Suggest disable SPIRAM_TRY_ALLOCATE_WIFI_LWIP. + Suggest disable ESP_WIFI_AMSDU_TX_ENABLED. + Suggest disable ESP_WIFI_CACHE_TX_BUFFER_NUM, need clear CONFIG_FEATURE_CACHE_TX_BUF_BIT of config->feature_caps. + Suggest change ESP_WIFI_TX_BUFFER from static to dynamic. Also suggest to adjust some buffer numbers to the + values used without PSRAM case. Such as, ESP_WIFI_STATIC_TX_BUFFER_NUM, ESP_WIFI_DYNAMIC_TX_BUFFER_NUM. choice SPIRAM_USE prompt "SPI RAM access method" diff --git a/components/esp_psram/device/esp_psram_impl_ap_hex.c b/components/esp_psram/device/esp_psram_impl_ap_hex.c index cbf79906906..5e586823a3a 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_hex.c +++ b/components/esp_psram/device/esp_psram_impl_ap_hex.c @@ -9,9 +9,11 @@ #include "esp_err.h" #include "esp_log.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/esp_ldo.h" #include "../esp_psram_impl.h" #include "rom/opi_flash.h" #include "hal/psram_ctrlr_ll.h" +#include "hal/ldo_ll.h" // Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section #define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC() @@ -122,7 +124,7 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co hex_psram_mode_reg_t mode_reg = {0}; int data_bit_len = 16; - //read + //read MR0 and MR1 s_psram_common_transaction(spi_num, AP_HEX_PSRAM_REG_READ, cmd_len, addr, addr_bit_len, @@ -131,12 +133,24 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co &mode_reg.mr0.val, data_bit_len, false); + addr = 0x4; + //read MR4 and MR8 + s_psram_common_transaction(spi_num, + AP_HEX_PSRAM_REG_READ, cmd_len, + addr, addr_bit_len, + dummy, + NULL, 0, + &mode_reg.mr4.val, data_bit_len, + false); + //modify mode_reg.mr0.lt = mode_reg_config->mr0.lt; mode_reg.mr0.read_latency = mode_reg_config->mr0.read_latency; mode_reg.mr0.drive_str = mode_reg_config->mr0.drive_str; + mode_reg.mr4.wr_latency = mode_reg_config->mr4.wr_latency; //write + addr = 0x0; s_psram_common_transaction(spi_num, AP_HEX_PSRAM_REG_WRITE, cmd_len, addr, addr_bit_len, @@ -145,6 +159,16 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co NULL, 0, false); + addr = 0x4; + //write + s_psram_common_transaction(spi_num, + AP_HEX_PSRAM_REG_WRITE, cmd_len, + addr, addr_bit_len, + 0, + &mode_reg.mr4.val, 16, + NULL, 0, + false); + addr = 0x8; data_bit_len = 8; //read @@ -241,11 +265,13 @@ static void s_print_psram_info(hex_psram_mode_reg_t *reg_val) static void s_config_mspi_for_psram(void) { + //TODO: IDF-6495, to change back to burst cmd //Config Write CMD phase for SPI0 to access PSRAM - psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_WR_CMD_BITLEN, AP_HEX_PSRAM_BURST_WRITE); + psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_WR_CMD_BITLEN, AP_HEX_PSRAM_SYNC_WRITE); + //TODO: IDF-6495, to change back to burst cmd //Config Read CMD phase for SPI0 to access PSRAM - psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_RD_CMD_BITLEN, AP_HEX_PSRAM_BURST_READ); + psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_RD_CMD_BITLEN, AP_HEX_PSRAM_SYNC_READ); //Config ADDR phase psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_2, AP_HEX_PSRAM_ADDR_BITLEN); @@ -324,10 +350,25 @@ static void s_configure_psram_ecc(void) esp_err_t esp_psram_impl_enable(void) { +#if CONFIG_SPIRAM_LDO_ID + if (CONFIG_SPIRAM_LDO_ID != -1) { + esp_ldo_unit_init_cfg_t unit_cfg = { + .unit_id = LDO_ID2UNIT(CONFIG_SPIRAM_LDO_ID), + .cfg = { + .voltage_mv = CONFIG_SPIRAM_LDO_VOLTAGE_MV, + }, + .flags.enable_unit = true, + }; + esp_ldo_unit_handle_t early_unit = esp_ldo_init_unit_early(&unit_cfg); + assert(early_unit); + } +#endif + PSRAM_RCC_ATOMIC() { psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true); psram_ctrlr_ll_reset_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2); psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL); + psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL); } s_set_psram_cs_timing(); @@ -336,13 +377,16 @@ esp_err_t esp_psram_impl_enable(void) #endif //enter MSPI slow mode to init PSRAM device registers psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_2, 2); - psram_ctrlr_ll_enable_dll(PSRAM_CTRLR_LL_MSPI_ID_2, true); - psram_ctrlr_ll_enable_dll(PSRAM_CTRLR_LL_MSPI_ID_3, true); + psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_3, 2); + //TODO: IDF-6495, to add back + // psram_ctrlr_ll_enable_dll(PSRAM_CTRLR_LL_MSPI_ID_2, true); + // psram_ctrlr_ll_enable_dll(PSRAM_CTRLR_LL_MSPI_ID_3, true); static hex_psram_mode_reg_t mode_reg = {}; mode_reg.mr0.lt = 1; mode_reg.mr0.read_latency = 2; mode_reg.mr0.drive_str = 0; + mode_reg.mr4.wr_latency = 2; mode_reg.mr8.bl = 3; mode_reg.mr8.bt = 0; mode_reg.mr8.rbx = 1; diff --git a/components/esp_psram/esp32/esp_psram_extram_cache.c b/components/esp_psram/esp32/esp_psram_extram_cache.c index 31841601000..1ee185e1ed2 100644 --- a/components/esp_psram/esp32/esp_psram_extram_cache.c +++ b/components/esp_psram/esp32/esp_psram_extram_cache.c @@ -9,7 +9,7 @@ #include "esp_psram.h" #include "esp_private/esp_psram_extram.h" -#if CONFIG_FREERTOS_UNICORE +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #else #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH @@ -38,7 +38,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void) cache_was_disabled |= (1 << 0); DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); } -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) { cache_was_disabled |= (1 << 1); DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S); @@ -70,7 +70,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void) while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ; DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); } -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE if (cache_was_disabled & (1 << 1)) { while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1); DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S); diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index cac52cf9a95..3ef1deafeb2 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -201,7 +201,7 @@ typedef enum { PSRAM_VADDR_MODE_EVENODD, ///< App and pro CPU share external RAM caches: pro CPU does even 32yte ranges, app does odd ones. } psram_vaddr_mode_t; -#if CONFIG_FREERTOS_UNICORE +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #else #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH diff --git a/components/esp_psram/esp32p4/Kconfig.spiram b/components/esp_psram/esp32p4/Kconfig.spiram index dd25eee8692..958d5be9c8a 100644 --- a/components/esp_psram/esp32p4/Kconfig.spiram +++ b/components/esp_psram/esp32p4/Kconfig.spiram @@ -46,6 +46,31 @@ menu "PSRAM config" If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code. + config SPIRAM_LDO_ID + int "PSRAM connected LDO ID, set -1 for using external power supply" + default 2 + range -1 4 + help + PSRAM VDD needs to be connected to an voltage output. This option selects the on-chip + LDO which is connected to the PSRAM VDD. + Set to -1 for connecting to external voltage output. + + choice SPIRAM_LDO_VOLTAGE_MV + prompt "PSRAM connected LDO voltage" + depends on SPIRAM_LDO_ID != -1 + default SPIRAM_LDO_VOLTAGE_MV_1800 + help + Select the speed for the PSRAM chip. + + config SPIRAM_LDO_VOLTAGE_MV_1800 + bool "1.8V" + endchoice + + config SPIRAM_LDO_VOLTAGE_MV + int + default 1800 if SPIRAM_LDO_VOLTAGE_MV_1800 + + config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY bool "Allow external memory as an argument to xTaskCreateStatic" default y diff --git a/components/esp_psram/esp32s2/esp_psram_impl_quad.c b/components/esp_psram/esp32s2/esp_psram_impl_quad.c index a151af93a9f..41fc38e8347 100644 --- a/components/esp_psram/esp32s2/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s2/esp_psram_impl_quad.c @@ -531,7 +531,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy, SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT); DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT); if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) { diff --git a/components/esp_psram/esp_psram.c b/components/esp_psram/esp_psram.c index 10abd43b891..1201540dc37 100644 --- a/components/esp_psram/esp_psram.c +++ b/components/esp_psram/esp_psram.c @@ -96,7 +96,7 @@ static void IRAM_ATTR s_mapping(int v_start, int size) //Enable external RAM in MMU cache_sram_mmu_set(0, 0, v_start, 0, 32, (size / 1024 / 32)); //Flush and enable icache for APP CPU -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1); cache_sram_mmu_set(1, 0, v_start, 0, 32, (size / 1024 / 32)); #endif @@ -126,7 +126,7 @@ esp_err_t esp_psram_init(void) ESP_EARLY_LOGI(TAG, "Found %dMB PSRAM device", psram_physical_size / (1024 * 1024)); ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED); #if CONFIG_IDF_TARGET_ESP32 -#if CONFIG_FREERTOS_UNICORE +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in normal (1-core) mode."); #else ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in low/high (2-core) mode."); @@ -206,7 +206,7 @@ esp_err_t esp_psram_init(void) cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_8bit_aligned, actual_mapped_len); cache_ll_l1_enable_bus(0, bus_mask); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE bus_mask = cache_ll_l1_get_bus(1, (uint32_t)v_start_8bit_aligned, actual_mapped_len); cache_ll_l1_enable_bus(1, bus_mask); #endif diff --git a/components/esp_psram/mmu_psram_flash.c b/components/esp_psram/mmu_psram_flash.c index e6e4d36fabd..90b698fe27d 100644 --- a/components/esp_psram/mmu_psram_flash.c +++ b/components/esp_psram/mmu_psram_flash.c @@ -64,7 +64,7 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size //Enable the most high bus, which is used for copying FLASH .text to PSRAM cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, SOC_EXTRAM_DATA_HIGH, 0); cache_ll_l1_enable_bus(0, bus_mask); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE bus_mask = cache_ll_l1_get_bus(1, SOC_EXTRAM_DATA_HIGH, 0); cache_ll_l1_enable_bus(1, bus_mask); #endif @@ -108,7 +108,7 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si //Enable the most high bus, which is used for copying FLASH .text to PSRAM cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, SOC_EXTRAM_DATA_HIGH, 0); cache_ll_l1_enable_bus(0, bus_mask); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE bus_mask = cache_ll_l1_get_bus(1, SOC_EXTRAM_DATA_HIGH, 0); cache_ll_l1_enable_bus(1, bus_mask); #endif diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 0701edc6c82..de6d90dcae4 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -11,7 +11,6 @@ if(target STREQUAL "linux") "${target}/esp_rom_crc.c" "${target}/esp_rom_md5.c" "${target}/esp_rom_efuse.c") - list(APPEND include_dirs "${IDF_PATH}/tools/mocks/soc/include") else() list(APPEND include_dirs "${target}") list(APPEND sources "patches/esp_rom_crc.c" @@ -23,7 +22,7 @@ else() # Override regi2c implementation in ROM if(CONFIG_ESP_ROM_HAS_REGI2C_BUG OR CONFIG_ESP_ROM_WITHOUT_REGI2C) - if(target STREQUAL "esp32c6") + if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5") list(APPEND sources "patches/esp_rom_hp_regi2c_${target}.c") else() list(APPEND sources "patches/esp_rom_regi2c_${target}.c") @@ -124,6 +123,9 @@ if(BOOTLOADER_BUILD) endif() rom_linker_script("version") + elseif(target STREQUAL "esp32c5") + rom_linker_script("newlib") + elseif(target STREQUAL "esp32h2") rom_linker_script("newlib") if(CONFIG_HAL_WDT_USE_ROM_IMPL) @@ -244,6 +246,7 @@ else() # Regular app build rom_linker_script("version") # esp32c6.rom.api.ld has been split to several lds by components. + # esp32c6.rom.api.ld is still reserved to map the APIs rom_linker_script("phy") rom_linker_script("coexist") rom_linker_script("net80211") @@ -262,6 +265,21 @@ else() # Regular app build rom_linker_script("newlib-normal") endif() + elseif(target STREQUAL "esp32c5") + rom_linker_script("newlib") + rom_linker_script("version") + + # esp32c5.rom.api.ld has been split to several lds by components. + # esp32c5.rom.api.ld is still reserved to map the APIs + if(CONFIG_SPI_FLASH_ROM_IMPL) + rom_linker_script("spiflash") + endif() + + if(NOT CONFIG_NEWLIB_NANO_FORMAT) + # Normal(Non-nano) formatting functions in ROM are also built for 64-bit time_t. + rom_linker_script("newlib-normal") + endif() + elseif(target STREQUAL "esp32h2") rom_linker_script("newlib") rom_linker_script("version") diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in index c53676fa51b..1e2fb931a33 100644 --- a/components/esp_rom/esp32/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32/Kconfig.soc_caps.in @@ -30,3 +30,7 @@ config ESP_ROM_NEEDS_SWSETUP_WORKAROUND config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h index e9473e4f232..f072c6cc8fb 100644 --- a/components/esp_rom/esp32/esp_rom_caps.h +++ b/components/esp_rom/esp32/esp_rom_caps.h @@ -13,3 +13,4 @@ #define ESP_ROM_HAS_UART_BUF_SWITCH (1) // ROM has exported the uart buffer switch function #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld index 6f5e1a6eadf..814eb8219bd 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.ld @@ -1623,4 +1623,12 @@ PROVIDE ( ld_acl_sniff_trans_sched = 0x40033734 ); PROVIDE ( lc_pwr_decr_ind_handler = 0x4002859c ); PROVIDE ( lc_pwr_incr_ind_handler = 0x400284a8 ); PROVIDE ( lc_pwr_max_ind_handler = 0x40028690 ); + +PROVIDE ( lm_sync_conf = 0x3ffb8348 ); +PROVIDE ( lm_nb_sync_active = 0x3ffb8346 ); +PROVIDE ( lm_sync_nego = 0x3ffb8345 ); +PROVIDE ( lm_nego_cnt = 0x3ffb8344 ); +PROVIDE ( lm_nego_cntl = 0x3ffb8342 ); +PROVIDE ( lm_nego_max_cnt = 0x3ffb8343 ); +PROVIDE ( lm_nego_pkt_used = 0x3ffb8340 ); /* Above are static data, but can be used, not generated by script >>>>> btdm data */ diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in index b2d3381e8c5..18d2f1fa74b 100644 --- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in @@ -62,3 +62,7 @@ config ESP_ROM_RAM_APP_NEEDS_MMU_INIT config ESP_ROM_HAS_MBEDTLS_CRYPTO_LIB bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h index cc3fdc51804..8478361c90b 100644 --- a/components/esp_rom/esp32c2/esp_rom_caps.h +++ b/components/esp_rom/esp32c2/esp_rom_caps.h @@ -21,3 +21,4 @@ #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_MBEDTLS_CRYPTO_LIB (1) // ROM has the mbedtls crypto algorithm lib +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld index eb9702f174a..99be4b28f34 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld @@ -638,7 +638,6 @@ r_ble_ll_adv_get_local_rpa = 0x40000c30; r_ble_ll_adv_get_peer_rpa = 0x40000c34; r_ble_ll_adv_hci_set_random_addr = 0x40000c38; r_ble_ll_adv_init = 0x40000c3c; -r_ble_ll_adv_legacy_pdu_make = 0x40000c40; r_ble_ll_adv_next_chan = 0x40000c44; r_ble_ll_adv_pdu_make = 0x40000c48; r_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c; @@ -659,7 +658,6 @@ r_ble_ll_adv_scan_req_rxd = 0x40000c98; r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c; r_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0; r_ble_ll_adv_scheduled = 0x40000ca4; -r_ble_ll_adv_send_conn_comp_ev = 0x40000ca8; r_ble_ll_adv_set_adv_params = 0x40000cb0; r_ble_ll_adv_set_enable = 0x40000cb4; r_ble_ll_adv_set_random_addr = 0x40000cb8; @@ -695,7 +693,6 @@ r_ble_ll_conn_calc_itvl_ticks = 0x40000d44; r_ble_ll_conn_chk_csm_flags = 0x40000d48; r_ble_ll_conn_chk_phy_upd_start = 0x40000d4c; r_ble_ll_conn_comp_event_send = 0x40000d50; -r_ble_ll_conn_connect_ind_pdu_make = 0x40000d54; r_ble_ll_conn_create_cancel = 0x40000d5c; r_ble_ll_conn_cth_flow_enable = 0x40000d64; r_ble_ll_conn_cth_flow_error_fn = 0x40000d68; @@ -734,7 +731,6 @@ r_ble_ll_conn_module_reset = 0x40000e04; r_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c; r_ble_ll_conn_process_conn_params = 0x40000e14; r_ble_ll_conn_req_peer_sca = 0x40000e18; -r_ble_ll_conn_rx_data_pdu = 0x40000e1c; r_ble_ll_conn_set_csa = 0x40000e20; r_ble_ll_conn_set_ext_con_params = 0x40000e24; r_ble_ll_conn_set_global_chanmap = 0x40000e28; @@ -889,7 +885,6 @@ r_ble_ll_pdu_max_tx_octets_get = 0x400010ec; r_ble_ll_pdu_tx_time_get = 0x400010f0; r_ble_ll_phy_to_phy_mode = 0x400010f4; r_ble_ll_qa_enable = 0x400010f8; -r_ble_ll_rand = 0x400010fc; r_ble_ll_rand_data_get = 0x40001100; r_ble_ll_rand_init = 0x4000110c; r_ble_ll_rand_prand_get = 0x40001110; @@ -1106,7 +1101,6 @@ r_ble_lll_conn_free_rx_mbuf = 0x40001518; r_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c; r_ble_lll_conn_get_ce_end_time = 0x40001520; r_ble_lll_conn_get_next_sched_time = 0x40001524; -r_ble_lll_conn_halt = 0x4000152c; r_ble_lll_conn_master_common_init = 0x40001530; r_ble_lll_conn_master_new = 0x40001534; r_ble_lll_conn_module_reset = 0x40001540; @@ -1164,7 +1158,6 @@ r_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638; r_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c; r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640; r_ble_lll_reset = 0x40001644; -r_ble_lll_rfmgmt_enable_now = 0x40001658; r_ble_lll_rfmgmt_is_enabled = 0x40001660; r_ble_lll_rfmgmt_release = 0x40001664; r_ble_lll_rfmgmt_scan_changed = 0x40001670; @@ -1203,10 +1196,8 @@ r_ble_lll_sched_adv_resched_pdu = 0x40001720; r_ble_lll_sched_adv_reschedule = 0x40001724; r_ble_lll_sched_aux_scan = 0x40001728; r_ble_lll_sched_conn_overlap = 0x4000172c; -r_ble_lll_sched_conn_reschedule = 0x40001730; r_ble_lll_sched_dtm = 0x40001738; r_ble_lll_sched_execute_item = 0x40001744; -r_ble_lll_sched_init = 0x40001748; r_ble_lll_sched_insert_if_empty = 0x4000174c; r_ble_lll_sched_is_overlap = 0x40001750; r_ble_lll_sched_master_new = 0x40001754; @@ -1328,7 +1319,6 @@ r_hal_timer_read = 0x4000197c; r_hal_timer_read_tick = 0x40001980; r_hal_timer_set_cb = 0x40001984; r_hal_timer_start = 0x4000198c; -r_hal_timer_stop = 0x40001994; r_hal_timer_task_start = 0x40001998; r_ll_assert = 0x4000199c; r_mem_init_mbuf_pool = 0x400019a0; @@ -1624,7 +1614,7 @@ wdev_mac_sleep = 0x40001d04; wdevProcessRxSucDataAll = 0x40001d10; wdev_csi_len_align = 0x40001d14; ppDequeueTxDone_Locked = 0x40001d18; -ppProcTxDone = 0x40001d1c; +/*ppProcTxDone = 0x40001d1c;*/ /*pm_tx_data_done_process = 0x40001d20;*/ config_is_cache_tx_buf_enabled = 0x40001d24; //ppMapWaitTxq = 0x40001d28; diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index 03b25e62ee0..ba3797fccf1 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -66,3 +66,7 @@ config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE config ESP_ROM_RAM_APP_NEEDS_MMU_INIT bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index 8ff06b7601e..0bf8742c40b 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -22,3 +22,4 @@ #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld index 8de0f1f37d4..403f198d4c7 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld @@ -32,7 +32,7 @@ wDevCheckBlockError = 0x400017b4; /* wDev_IndicateFrame = 0x400017c8;*/ wDev_ProcessFiq = 0x400017f0; wDev_ProcessRxSucData = 0x400017f4; -ppProcTxDone = 0x40001804; +/*ppProcTxDone = 0x40001804;*/ pm_tx_data_done_process = 0x40001808; ppMapWaitTxq = 0x40001810; ieee80211_encap_esfbuf = 0x4000185c; @@ -116,7 +116,6 @@ r_lld_con_evt_time_update_eco = 0x40001d0c; r_lld_con_start_eco = 0x40001d10; r_lld_con_frm_isr_eco = 0x40001d14; r_lld_con_tx_eco = 0x40001d18; -r_lld_con_evt_start_cbk_eco = 0x40001d1c; r_lld_scan_evt_start_cbk_eco = 0x40001d20; r_lld_scan_start_eco = 0x40001d24; r_lld_ext_scan_dynamic_pti_process_eco = 0x40001d28; @@ -205,7 +204,6 @@ r_sch_arb_event_start_isr = 0x400014f8; r_sch_plan_set = 0x40001534; r_sch_prog_end_isr = 0x40001538; r_lld_adv_ext_chain_scannable_construct = 0x40001b58; -r_lld_con_tx_prog_new_packet = 0x40001b74; r_lld_scan_process_pkt_rx = 0x40001280; r_llm_le_features_get = 0x400013b0; @@ -220,6 +218,8 @@ r_lld_adv_frm_isr_eco = 0x40001d00; r_lld_res_list_clear = 0x40004638; r_lld_res_list_rem = 0x40004680; r_lld_adv_start_hook = 0x40001c80; +r_lld_con_evt_start_cbk_eco = 0x40001d1c; +r_lld_con_tx_prog_new_packet = 0x40001b74; */ diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in new file mode 100644 index 00000000000..62c92152b0f --- /dev/null +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -0,0 +1,80 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config ESP_ROM_HAS_CRC_LE + bool + default y + +config ESP_ROM_HAS_CRC_BE + bool + default y + +config ESP_ROM_HAS_JPEG_DECODE + bool + default y + +config ESP_ROM_UART_CLK_IS_XTAL + bool + default y + +config ESP_ROM_USB_SERIAL_DEVICE_NUM + int + default 3 + +config ESP_ROM_HAS_RETARGETABLE_LOCKING + bool + default y + +config ESP_ROM_GET_CLK_FREQ + bool + default y + +config ESP_ROM_HAS_RVFPLIB + bool + default y + +config ESP_ROM_HAS_HAL_WDT + bool + default y + +config ESP_ROM_HAS_HAL_SYSTIMER + bool + default y + +config ESP_ROM_HAS_HEAP_TLSF + bool + default y + +config ESP_ROM_TLSF_CHECK_PATCH + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y + +config ESP_ROM_WITHOUT_REGI2C + bool + default y + +config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT + bool + default y + +config ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE + bool + default y + +config ESP_ROM_WDT_INIT_PATCH + bool + default y + +config ESP_ROM_RAM_APP_NEEDS_MMU_INIT + bool + default y diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h new file mode 100644 index 00000000000..f6fd8b12f19 --- /dev/null +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib +#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs +#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) +#define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it +#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld new file mode 100644 index 00000000000..cf8c34778ee --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** ROM APIs + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); +PROVIDE ( esp_rom_crc32_be = crc32_be ); +PROVIDE ( esp_rom_crc16_be = crc16_be ); +PROVIDE ( esp_rom_crc8_be = crc8_be ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char2 ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_md5_init = MD5Init ); +PROVIDE ( esp_rom_md5_update = MD5Update ); +PROVIDE ( esp_rom_md5_final = MD5Final ); + +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); +PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); +PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); +PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); + +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); +PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); +PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); +PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); + +PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); +PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); +PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); +PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld new file mode 100644 index 00000000000..62200c5af54 --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.heap.ld @@ -0,0 +1,76 @@ +/* ROM function interface esp32c5.rom.heap.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group heap + ***************************************/ + +/* Functions */ +tlsf_create = 0x400003f8; +tlsf_create_with_pool = 0x400003fc; +tlsf_get_pool = 0x40000400; +tlsf_add_pool = 0x40000404; +tlsf_remove_pool = 0x40000408; +tlsf_malloc = 0x4000040c; +tlsf_memalign = 0x40000410; +tlsf_memalign_offs = 0x40000414; +tlsf_realloc = 0x40000418; +tlsf_free = 0x4000041c; +tlsf_block_size = 0x40000420; +tlsf_size = 0x40000424; +tlsf_align_size = 0x40000428; +tlsf_block_size_min = 0x4000042c; +tlsf_block_size_max = 0x40000430; +tlsf_pool_overhead = 0x40000434; +tlsf_alloc_overhead = 0x40000438; +tlsf_walk_pool = 0x4000043c; +tlsf_check = 0x40000440; +tlsf_check_pool = 0x40000444; +tlsf_poison_fill_pfunc_set = 0x40000448; +tlsf_poison_check_pfunc_set = 0x4000044c; +multi_heap_get_block_address_impl = 0x40000450; +multi_heap_get_allocated_size_impl = 0x40000454; +multi_heap_register_impl = 0x40000458; +multi_heap_set_lock = 0x4000045c; +multi_heap_os_funcs_init = 0x40000460; +multi_heap_internal_lock = 0x40000464; +multi_heap_internal_unlock = 0x40000468; +multi_heap_get_first_block = 0x4000046c; +multi_heap_get_next_block = 0x40000470; +multi_heap_is_free = 0x40000474; +multi_heap_malloc_impl = 0x40000478; +multi_heap_free_impl = 0x4000047c; +multi_heap_realloc_impl = 0x40000480; +multi_heap_aligned_alloc_impl_offs = 0x40000484; +multi_heap_aligned_alloc_impl = 0x40000488; +multi_heap_check = 0x4000048c; +multi_heap_dump = 0x40000490; +multi_heap_free_size_impl = 0x40000494; +multi_heap_minimum_free_size_impl = 0x40000498; +multi_heap_get_info_impl = 0x4000049c; +/* Data (.data, .bss, .rodata) */ +heap_tlsf_table_ptr = 0x4087ffd8; + +PROVIDE (multi_heap_malloc = multi_heap_malloc_impl); +PROVIDE (multi_heap_free = multi_heap_free_impl); +PROVIDE (multi_heap_realloc = multi_heap_realloc_impl); +PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl); +PROVIDE (multi_heap_register = multi_heap_register_impl); +PROVIDE (multi_heap_get_info = multi_heap_get_info_impl); +PROVIDE (multi_heap_free_size = multi_heap_free_size_impl); +PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl); +PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl); +PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl); +PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl); +PROVIDE (multi_heap_check = multi_heap_check); +PROVIDE (multi_heap_set_lock = multi_heap_set_lock); +PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init); +PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock); +PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock); diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld new file mode 100644 index 00000000000..ce63a26314b --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld @@ -0,0 +1,578 @@ +/* ROM function interface esp32c5.rom.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +rtc_get_wakeup_cause = 0x4000001c; +pmu_enable_unhold_pads = 0x40000020; +ets_printf = 0x40000024; +ets_install_putc1 = 0x40000028; +ets_install_putc2 = 0x4000002c; +ets_install_uart_printf = 0x40000030; +ets_install_usb_printf = 0x40000034; +ets_get_printf_channel = 0x40000038; +ets_delay_us = 0x4000003c; +ets_get_cpu_frequency = 0x40000040; +ets_update_cpu_frequency = 0x40000044; +ets_install_lock = 0x40000048; +UartRxString = 0x4000004c; +UartGetCmdLn = 0x40000050; +uart_tx_one_char = 0x40000054; +uart_tx_one_char2 = 0x40000058; +uart_tx_one_char3 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +uart_buff_switch = 0x40000088; +roundup2 = 0x4000008c; +multofup = 0x40000090; +software_reset = 0x40000094; +software_reset_cpu = 0x40000098; +ets_clk_assist_debug_clock_enable = 0x4000009c; +clear_super_wdt_reset_flag = 0x400000a0; +disable_default_watchdog = 0x400000a4; +esp_rom_set_rtc_wake_addr = 0x400000a8; +esp_rom_get_rtc_wake_addr = 0x400000ac; +send_packet = 0x400000b0; +recv_packet = 0x400000b4; +GetUartDevice = 0x400000b8; +UartDwnLdProc = 0x400000bc; +GetSecurityInfoProc = 0x400000c0; +Uart_Init = 0x400000c4; +ets_set_user_start = 0x400000c8; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4004fffc; +ets_ops_table_ptr = 0x4087fff8; +g_saved_pc = 0x4087fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000cc; +mz_free = 0x400000d0; +tdefl_compress = 0x400000d4; +tdefl_compress_buffer = 0x400000d8; +tdefl_compress_mem_to_heap = 0x400000dc; +tdefl_compress_mem_to_mem = 0x400000e0; +tdefl_compress_mem_to_output = 0x400000e4; +tdefl_get_adler32 = 0x400000e8; +tdefl_get_prev_return_status = 0x400000ec; +tdefl_init = 0x400000f0; +tdefl_write_image_to_png_file_in_memory = 0x400000f4; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f8; +tinfl_decompress = 0x400000fc; +tinfl_decompress_mem_to_callback = 0x40000100; +tinfl_decompress_mem_to_heap = 0x40000104; +tinfl_decompress_mem_to_mem = 0x40000108; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x4000010c; +esp_rom_spiflash_write_encrypted = 0x40000110; +esp_rom_spiflash_write_encrypted_dest = 0x40000114; +esp_rom_spiflash_write_encrypted_enable = 0x40000118; +esp_rom_spiflash_write_encrypted_disable = 0x4000011c; +esp_rom_spiflash_erase_chip = 0x40000120; +_esp_rom_spiflash_erase_sector = 0x40000124; +_esp_rom_spiflash_erase_block = 0x40000128; +_esp_rom_spiflash_write = 0x4000012c; +_esp_rom_spiflash_read = 0x40000130; +_esp_rom_spiflash_unlock = 0x40000134; +_SPIEraseArea = 0x40000138; +_SPI_write_enable = 0x4000013c; +esp_rom_spiflash_erase_sector = 0x40000140; +esp_rom_spiflash_erase_block = 0x40000144; +esp_rom_spiflash_write = 0x40000148; +esp_rom_spiflash_read = 0x4000014c; +esp_rom_spiflash_unlock = 0x40000150; +SPIEraseArea = 0x40000154; +SPI_write_enable = 0x40000158; +esp_rom_spiflash_config_param = 0x4000015c; +esp_rom_spiflash_read_user_cmd = 0x40000160; +esp_rom_spiflash_select_qio_pins = 0x40000164; +esp_rom_spi_flash_auto_sus_res = 0x40000168; +esp_rom_spi_flash_send_resume = 0x4000016c; +esp_rom_spi_flash_update_id = 0x40000170; +esp_rom_spiflash_config_clk = 0x40000174; +esp_rom_spiflash_config_readmode = 0x40000178; +esp_rom_spiflash_read_status = 0x4000017c; +esp_rom_spiflash_read_statushigh = 0x40000180; +esp_rom_spiflash_write_status = 0x40000184; +esp_rom_spiflash_write_disable = 0x40000188; +spi_cache_mode_switch = 0x4000018c; +spi_common_set_dummy_output = 0x40000190; +spi_common_set_flash_cs_timing = 0x40000194; +esp_rom_spi_set_address_bit_len = 0x40000198; +SPILock = 0x4000019c; +SPIMasterReadModeCnfig = 0x400001a0; +SPI_Common_Command = 0x400001a4; +SPI_WakeUp = 0x400001a8; +SPI_block_erase = 0x400001ac; +SPI_chip_erase = 0x400001b0; +SPI_init = 0x400001b4; +SPI_page_program = 0x400001b8; +SPI_read_data = 0x400001bc; +SPI_sector_erase = 0x400001c0; +SelectSpiFunction = 0x400001c4; +SetSpiDrvs = 0x400001c8; +Wait_SPI_Idle = 0x400001cc; +spi_dummy_len_fix = 0x400001d0; +Disable_QMode = 0x400001d4; +Enable_QMode = 0x400001d8; +spi_flash_attach = 0x400001dc; +spi_flash_get_chip_size = 0x400001e0; +spi_flash_guard_set = 0x400001e4; +spi_flash_guard_get = 0x400001e8; +spi_flash_read_encrypted = 0x400001ec; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4087fff0; +rom_spiflash_legacy_data = 0x4087ffec; +g_flash_guard_ops = 0x4087fff4; + + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ +wdt_hal_init = 0x40000390; +wdt_hal_deinit = 0x40000394; +wdt_hal_config_stage = 0x40000398; +wdt_hal_write_protect_disable = 0x4000039c; +wdt_hal_write_protect_enable = 0x400003a0; +wdt_hal_enable = 0x400003a4; +wdt_hal_disable = 0x400003a8; +wdt_hal_handle_intr = 0x400003ac; +wdt_hal_feed = 0x400003b0; +wdt_hal_set_flashboot_en = 0x400003b4; +wdt_hal_is_enabled = 0x400003b8; + + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x400003bc; +systimer_hal_deinit = 0x400003c0; +systimer_hal_set_tick_rate_ops = 0x400003c4; +systimer_hal_get_counter_value = 0x400003c8; +systimer_hal_get_time = 0x400003cc; +systimer_hal_set_alarm_target = 0x400003d0; +systimer_hal_set_alarm_period = 0x400003d4; +systimer_hal_get_alarm_value = 0x400003d8; +systimer_hal_enable_alarm_int = 0x400003dc; +systimer_hal_on_apb_freq_update = 0x400003e0; +systimer_hal_counter_value_advance = 0x400003e4; +systimer_hal_enable_counter = 0x400003e8; +systimer_hal_select_alarm_mode = 0x400003ec; +systimer_hal_connect_alarm_counter = 0x400003f0; +systimer_hal_counter_can_stall_by_cpu = 0x400003f4; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_ICache_Line_Size = 0x40000624; +Cache_Get_Mode = 0x40000628; +Cache_Address_Through_Cache = 0x4000062c; +ROM_Boot_Cache_Init = 0x40000630; +MMU_Set_Page_Mode = 0x40000634; +MMU_Get_Page_Mode = 0x40000638; +Cache_Invalidate_ICache_Items = 0x4000063c; +Cache_Op_Addr = 0x40000640; +Cache_Invalidate_Addr = 0x40000644; +Cache_Invalidate_ICache_All = 0x40000648; +Cache_Mask_All = 0x4000064c; +Cache_UnMask_Dram0 = 0x40000650; +Cache_Suspend_ICache_Autoload = 0x40000654; +Cache_Resume_ICache_Autoload = 0x40000658; +Cache_Start_ICache_Preload = 0x4000065c; +Cache_ICache_Preload_Done = 0x40000660; +Cache_End_ICache_Preload = 0x40000664; +Cache_Config_ICache_Autoload = 0x40000668; +Cache_Enable_ICache_Autoload = 0x4000066c; +Cache_Disable_ICache_Autoload = 0x40000670; +Cache_Enable_ICache_PreLock = 0x40000674; +Cache_Disable_ICache_PreLock = 0x40000678; +Cache_Lock_ICache_Items = 0x4000067c; +Cache_Unlock_ICache_Items = 0x40000680; +Cache_Lock_Addr = 0x40000684; +Cache_Unlock_Addr = 0x40000688; +Cache_Disable_ICache = 0x4000068c; +Cache_Enable_ICache = 0x40000690; +Cache_Suspend_ICache = 0x40000694; +Cache_Resume_ICache = 0x40000698; +Cache_Freeze_ICache_Enable = 0x4000069c; +Cache_Freeze_ICache_Disable = 0x400006a0; +Cache_Set_IDROM_MMU_Size = 0x400006a4; +Cache_Get_IROM_MMU_End = 0x400006a8; +Cache_Get_DROM_MMU_End = 0x400006ac; +Cache_MMU_Init = 0x400006b0; +Cache_MSPI_MMU_Set = 0x400006b4; +Cache_MSPI_MMU_Set_Secure = 0x400006b8; +Cache_Travel_Tag_Memory = 0x400006bc; +Cache_Get_Virtual_Addr = 0x400006c0; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4087ffcc; +rom_cache_internal_table_ptr = 0x4087ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x400006c4; +ets_clk_get_cpu_freq = 0x400006c8; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_set_output_level = 0x400006cc; +gpio_get_input_level = 0x400006d0; +gpio_matrix_in = 0x400006d4; +gpio_matrix_out = 0x400006d8; +gpio_bypass_matrix_in = 0x400006dc; +gpio_output_disable = 0x400006e0; +gpio_output_enable = 0x400006e4; +gpio_pad_input_disable = 0x400006e8; +gpio_pad_input_enable = 0x400006ec; +gpio_pad_pulldown = 0x400006f0; +gpio_pad_pullup = 0x400006f4; +gpio_pad_select_gpio = 0x400006f8; +gpio_pad_set_drv = 0x400006fc; +gpio_pad_unhold = 0x40000700; +gpio_pad_hold = 0x40000704; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x40000708; +esprv_intc_int_set_threshold = 0x4000070c; +esprv_intc_int_enable = 0x40000710; +esprv_intc_int_disable = 0x40000714; +esprv_intc_int_set_type = 0x40000718; +PROVIDE( intr_handler_set = 0x4000071c ); +intr_matrix_set = 0x40000720; +ets_intr_lock = 0x40000724; +ets_intr_unlock = 0x40000728; +ets_isr_attach = 0x4000072c; +ets_isr_mask = 0x40000730; +ets_isr_unmask = 0x40000734; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000738; +MD5Init = 0x4000073c; +MD5Update = 0x40000740; +MD5Final = 0x40000744; +crc32_le = 0x40000748; +crc16_le = 0x4000074c; +crc8_le = 0x40000750; +crc32_be = 0x40000754; +crc16_be = 0x40000758; +crc8_be = 0x4000075c; +esp_crc8 = 0x40000760; +ets_sha_enable = 0x40000764; +ets_sha_disable = 0x40000768; +ets_sha_get_state = 0x4000076c; +ets_sha_init = 0x40000770; +ets_sha_process = 0x40000774; +ets_sha_starts = 0x40000778; +ets_sha_update = 0x4000077c; +ets_sha_finish = 0x40000780; +ets_sha_clone = 0x40000784; +ets_hmac_enable = 0x40000788; +ets_hmac_disable = 0x4000078c; +ets_hmac_calculate_message = 0x40000790; +ets_hmac_calculate_downstream = 0x40000794; +ets_hmac_invalidate_downstream = 0x40000798; +ets_jtag_enable_temporarily = 0x4000079c; +ets_aes_enable = 0x400007a0; +ets_aes_disable = 0x400007a4; +ets_aes_setkey = 0x400007a8; +ets_aes_block = 0x400007ac; +ets_aes_setkey_dec = 0x400007b0; +ets_aes_setkey_enc = 0x400007b4; +ets_bigint_enable = 0x400007b8; +ets_bigint_disable = 0x400007bc; +ets_bigint_multiply = 0x400007c0; +ets_bigint_modmult = 0x400007c4; +ets_bigint_modexp = 0x400007c8; +ets_bigint_wait_finish = 0x400007cc; +ets_bigint_getz = 0x400007d0; +ets_ds_enable = 0x400007d4; +ets_ds_disable = 0x400007d8; +ets_ds_start_sign = 0x400007dc; +ets_ds_is_busy = 0x400007e0; +ets_ds_finish_sign = 0x400007e4; +ets_ds_encrypt_params = 0x400007e8; +ets_mgf1_sha256 = 0x400007ec; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4004fff8; +crc16_le_table_ptr = 0x4004fff4; +crc8_le_table_ptr = 0x4004fff0; +crc32_be_table_ptr = 0x4004ffec; +crc16_be_table_ptr = 0x4004ffe8; +crc8_be_table_ptr = 0x4004ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x400007f0; +ets_efuse_program = 0x400007f4; +ets_efuse_clear_program_registers = 0x400007f8; +ets_efuse_write_key = 0x400007fc; +ets_efuse_get_read_register_address = 0x40000800; +ets_efuse_get_key_purpose = 0x40000804; +ets_efuse_key_block_unused = 0x40000808; +ets_efuse_find_unused_key_block = 0x4000080c; +ets_efuse_rs_calculate = 0x40000810; +ets_efuse_count_unused_key_blocks = 0x40000814; +ets_efuse_secure_boot_enabled = 0x40000818; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000081c; +ets_efuse_cache_encryption_enabled = 0x40000820; +ets_efuse_download_modes_disabled = 0x40000824; +ets_efuse_find_purpose = 0x40000828; +ets_efuse_force_send_resume = 0x4000082c; +ets_efuse_get_flash_delay_us = 0x40000830; +ets_efuse_get_uart_print_control = 0x40000834; +ets_efuse_direct_boot_mode_disabled = 0x40000838; +ets_efuse_security_download_modes_enabled = 0x4000083c; +ets_efuse_jtag_disabled = 0x40000840; +ets_efuse_usb_print_is_disabled = 0x40000844; +ets_efuse_usb_download_mode_disabled = 0x40000848; +ets_efuse_usb_device_disabled = 0x4000084c; +ets_efuse_secure_boot_fast_wake_enabled = 0x40000850; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x40000854; +ets_rsa_pss_verify = 0x40000858; +ets_ecdsa_verify = 0x4000085c; +ets_secure_boot_verify_bootloader_with_keys = 0x40000860; +ets_secure_boot_verify_signature = 0x40000864; +ets_secure_boot_read_key_digests = 0x40000868; +ets_secure_boot_revoke_public_key_digest = 0x4000086c; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x40000a6c; +usb_serial_device_rx_one_char_block = 0x40000a70; +usb_serial_device_tx_flush = 0x40000a74; +usb_serial_device_tx_one_char = 0x40000a78; + + +/*************************************** + Group usb_dwcotg_uart + ***************************************/ + +/* Functions */ +Uart_Init_USB = 0x40000a7c; +usb_serial_otg_rx_one_char = 0x40000a80; +usb_serial_otg_rx_one_char_block = 0x40000a84; +usb_serial_otg_tx_flush = 0x40000a88; +usb_serial_otg_tx_one_char = 0x40000a8c; +/* Data (.data, .bss, .rodata) */ +uart_acm_dev = 0x4087ffc4; + + +/*************************************** + Group usb_dwcotg_module + ***************************************/ + +/* Functions */ +cdc_acm_class_handle_req = 0x40000a90; +cdc_acm_init = 0x40000a94; +cdc_acm_fifo_fill = 0x40000a98; +cdc_acm_rx_fifo_cnt = 0x40000a9c; +cdc_acm_fifo_read = 0x40000aa0; +cdc_acm_irq_tx_enable = 0x40000aa4; +cdc_acm_irq_tx_disable = 0x40000aa8; +cdc_acm_irq_state_enable = 0x40000aac; +cdc_acm_irq_state_disable = 0x40000ab0; +cdc_acm_irq_tx_ready = 0x40000ab4; +cdc_acm_irq_rx_enable = 0x40000ab8; +cdc_acm_irq_rx_disable = 0x40000abc; +cdc_acm_irq_rx_ready = 0x40000ac0; +cdc_acm_irq_is_pending = 0x40000ac4; +cdc_acm_irq_callback_set = 0x40000ac8; +cdc_acm_line_ctrl_set = 0x40000acc; +cdc_acm_line_ctrl_get = 0x40000ad0; +cdc_acm_poll_out = 0x40000ad4; +chip_usb_dw_did_persist = 0x40000ad8; +chip_usb_dw_init = 0x40000adc; +chip_usb_detach = 0x40000ae0; +chip_usb_dw_prepare_persist = 0x40000ae4; +chip_usb_get_persist_flags = 0x40000ae8; +chip_usb_set_persist_flags = 0x40000aec; +cpio_start = 0x40000af0; +cpio_feed = 0x40000af4; +cpio_done = 0x40000af8; +cpio_destroy = 0x40000afc; +dfu_flash_init = 0x40000b00; +dfu_flash_erase = 0x40000b04; +dfu_flash_program = 0x40000b08; +dfu_flash_read = 0x40000b0c; +dfu_flash_attach = 0x40000b10; +dfu_cpio_callback = 0x40000b14; +dfu_updater_get_err = 0x40000b18; +dfu_updater_clear_err = 0x40000b1c; +dfu_updater_enable = 0x40000b20; +dfu_updater_begin = 0x40000b24; +dfu_updater_feed = 0x40000b28; +dfu_updater_end = 0x40000b2c; +dfu_updater_set_raw_addr = 0x40000b30; +dfu_updater_flash_read = 0x40000b34; +usb_dc_prepare_persist = 0x40000b38; +usb_dw_isr_handler = 0x40000b3c; +usb_dc_attach = 0x40000b40; +usb_dc_detach = 0x40000b44; +usb_dc_reset = 0x40000b48; +usb_dc_set_address = 0x40000b4c; +usb_dc_ep_check_cap = 0x40000b50; +usb_dc_ep_configure = 0x40000b54; +usb_dc_ep_set_stall = 0x40000b58; +usb_dc_ep_clear_stall = 0x40000b5c; +usb_dc_ep_halt = 0x40000b60; +usb_dc_ep_is_stalled = 0x40000b64; +usb_dc_ep_enable = 0x40000b68; +usb_dc_ep_disable = 0x40000b6c; +usb_dc_ep_flush = 0x40000b70; +usb_dc_ep_write_would_block = 0x40000b74; +usb_dc_ep_write = 0x40000b78; +usb_dc_ep_read_wait = 0x40000b7c; +usb_dc_ep_read_continue = 0x40000b80; +usb_dc_ep_read = 0x40000b84; +usb_dc_ep_set_callback = 0x40000b88; +usb_dc_set_status_callback = 0x40000b8c; +usb_dc_ep_mps = 0x40000b90; +usb_dc_check_poll_for_interrupts = 0x40000b94; +mac_addr_to_serial_str_desc = 0x40000b98; +usb_set_current_descriptor = 0x40000b9c; +usb_get_descriptor = 0x40000ba0; +usb_dev_resume = 0x40000ba4; +usb_dev_get_configuration = 0x40000ba8; +usb_set_config = 0x40000bac; +usb_deconfig = 0x40000bb0; +usb_enable = 0x40000bb4; +usb_disable = 0x40000bb8; +usb_write_would_block = 0x40000bbc; +usb_write = 0x40000bc0; +usb_read = 0x40000bc4; +usb_ep_set_stall = 0x40000bc8; +usb_ep_clear_stall = 0x40000bcc; +usb_ep_read_wait = 0x40000bd0; +usb_ep_read_continue = 0x40000bd4; +usb_transfer_ep_callback = 0x40000bd8; +usb_transfer = 0x40000bdc; +usb_cancel_transfer = 0x40000be0; +usb_transfer_sync = 0x40000be4; +usb_dfu_set_detach_cb = 0x40000be8; +dfu_class_handle_req = 0x40000bec; +dfu_status_cb = 0x40000bf0; +dfu_custom_handle_req = 0x40000bf4; +usb_dfu_init = 0x40000bf8; +usb_dfu_force_detach = 0x40000bfc; +usb_dev_deinit = 0x40000c00; +usb_dw_ctrl_deinit = 0x40000c04; +/* Data (.data, .bss, .rodata) */ +s_usb_osglue = 0x4087ffb8; + + +/*************************************** + Group lldesc + ***************************************/ + +/* Functions */ +lldesc_build_chain = 0x40000c08; + + +/*************************************** + Group sip + ***************************************/ + +/* Functions */ +sip_after_tx_complete = 0x40000c0c; +sip_alloc_to_host_evt = 0x40000c10; +sip_download_begin = 0x40000c14; +sip_get_ptr = 0x40000c18; +sip_get_state = 0x40000c1c; +sip_init_attach = 0x40000c20; +sip_install_rx_ctrl_cb = 0x40000c24; +sip_install_rx_data_cb = 0x40000c28; +sip_is_active = 0x40000c2c; +sip_post_init = 0x40000c30; +sip_reclaim_from_host_cmd = 0x40000c34; +sip_reclaim_tx_data_pkt = 0x40000c38; +sip_send = 0x40000c3c; +sip_to_host_chain_append = 0x40000c40; +sip_to_host_evt_send_done = 0x40000c44; + + +/*************************************** + Group slc + ***************************************/ + +/* Functions */ +slc_add_credits = 0x40000c48; +slc_enable = 0x40000c4c; +slc_from_host_chain_fetch = 0x40000c50; +slc_from_host_chain_recycle = 0x40000c54; +slc_has_pkt_to_host = 0x40000c58; +slc_init_attach = 0x40000c5c; +slc_init_credit = 0x40000c60; +slc_reattach = 0x40000c64; +slc_send_to_host_chain = 0x40000c68; +slc_set_host_io_max_window = 0x40000c6c; +slc_to_host_chain_recycle = 0x40000c70; + diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld new file mode 100644 index 00000000000..2634ce20ba8 --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.libgcc.ld @@ -0,0 +1,115 @@ +/* ROM function interface esp32c5.rom.libgcc.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgccsf + ***************************************/ + +/* Functions */ +__addsf3 = 0x40000870; +__divsf3 = 0x40000874; +__eqsf2 = 0x40000878; +__fixsfsi = 0x4000087c; +__floatsisf = 0x40000880; +__floatunsisf = 0x40000884; +__gesf2 = 0x40000888; +__gtsf2 = 0x4000088c; +__lesf2 = 0x40000890; +__ltsf2 = 0x40000894; +__mulsf3 = 0x40000898; +__negsf2 = 0x4000089c; +__nesf2 = 0x400008a0; +__powisf2 = 0x400008a4; +__subsf3 = 0x400008a8; +__truncdfsf2 = 0x400008ac; +__unordsf2 = 0x400008b0; + + +/*************************************** + Group libgccdf + ***************************************/ + +/* Functions */ +__absvdi2 = 0x400008b4; +__absvsi2 = 0x400008b8; +__adddf3 = 0x400008bc; +__addvdi3 = 0x400008c0; +__addvsi3 = 0x400008c4; +__ashldi3 = 0x400008c8; +__ashrdi3 = 0x400008cc; +__bswapdi2 = 0x400008d0; +__bswapsi2 = 0x400008d4; +__clear_cache = 0x400008d8; +__clrsbdi2 = 0x400008dc; +__clrsbsi2 = 0x400008e0; +__clzdi2 = 0x400008e4; +__clzsi2 = 0x400008e8; +__cmpdi2 = 0x400008ec; +__ctzdi2 = 0x400008f0; +__ctzsi2 = 0x400008f4; +__divdc3 = 0x400008f8; +__divdf3 = 0x400008fc; +__divdi3 = 0x40000900; +__divsc3 = 0x40000904; +__divsi3 = 0x40000908; +__eqdf2 = 0x4000090c; +__extendsfdf2 = 0x40000910; +__ffsdi2 = 0x40000914; +__ffssi2 = 0x40000918; +__fixdfdi = 0x4000091c; +__fixdfsi = 0x40000920; +__fixsfdi = 0x40000924; +__fixunsdfsi = 0x40000928; +__fixunssfdi = 0x4000092c; +__fixunssfsi = 0x40000930; +__floatdidf = 0x40000934; +__floatdisf = 0x40000938; +__floatsidf = 0x4000093c; +__floatundidf = 0x40000940; +__floatundisf = 0x40000944; +__floatunsidf = 0x40000948; +__gcc_bcmp = 0x4000094c; +__gedf2 = 0x40000950; +__gtdf2 = 0x40000954; +__ledf2 = 0x40000958; +__lshrdi3 = 0x4000095c; +__ltdf2 = 0x40000960; +__moddi3 = 0x40000964; +__modsi3 = 0x40000968; +__muldc3 = 0x4000096c; +__muldf3 = 0x40000970; +__muldi3 = 0x40000974; +__mulsc3 = 0x40000978; +__mulsi3 = 0x4000097c; +__mulvdi3 = 0x40000980; +__mulvsi3 = 0x40000984; +__nedf2 = 0x40000988; +__negdf2 = 0x4000098c; +__negdi2 = 0x40000990; +__negvdi2 = 0x40000994; +__negvsi2 = 0x40000998; +__paritysi2 = 0x4000099c; +__popcountdi2 = 0x400009a0; +__popcountsi2 = 0x400009a4; +__powidf2 = 0x400009a8; +__subdf3 = 0x400009ac; +__subvdi3 = 0x400009b0; +__subvsi3 = 0x400009b4; +__ucmpdi2 = 0x400009b8; +__udivdi3 = 0x400009bc; +__udivmoddi4 = 0x400009c0; +__udivsi3 = 0x400009c4; +__udiv_w_sdiv = 0x400009c8; +__umoddi3 = 0x400009cc; +__umodsi3 = 0x400009d0; +__unorddf2 = 0x400009d4; +__extenddftf2 = 0x400009d8; +__trunctfdf2 = 0x400009dc; + diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld new file mode 100644 index 00000000000..aa93ad13559 --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib-normal.ld @@ -0,0 +1,37 @@ +/* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib_normal_format + ***************************************/ + +/* Functions */ +__sprint_r = 0x400005d0; +_fiprintf_r = 0x400005d4; +_fprintf_r = 0x400005d8; +_vfiprintf_r = 0x400005dc; +_vfprintf_r = 0x400005e0; +fiprintf = 0x400005e4; +fprintf = 0x400005e8; +printf = 0x400005ec; +vfiprintf = 0x400005f0; +vfprintf = 0x400005f4; +asprintf = 0x400005f8; +sprintf = 0x400005fc; +snprintf = 0x40000600; +siprintf = 0x40000604; +sniprintf = 0x40000608; +vprintf = 0x4000060c; +viprintf = 0x40000610; +vsnprintf = 0x40000614; +vsniprintf = 0x40000618; +sscanf = 0x4000061c; +siscanf = 0x40000620; + diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld new file mode 100644 index 00000000000..d36e57b7ec9 --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.newlib.ld @@ -0,0 +1,95 @@ +/* ROM function interface esp32c5.rom.newlib.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib + ***************************************/ + +/* Functions */ +esp_rom_newlib_init_common_mutexes = 0x400004a0; +memset = 0x400004a4; +memcpy = 0x400004a8; +memmove = 0x400004ac; +memcmp = 0x400004b0; +strcpy = 0x400004b4; +strncpy = 0x400004b8; +strcmp = 0x400004bc; +strncmp = 0x400004c0; +strlen = 0x400004c4; +strstr = 0x400004c8; +bzero = 0x400004cc; +_isatty_r = 0x400004d0; +sbrk = 0x400004d4; +isalnum = 0x400004d8; +isalpha = 0x400004dc; +isascii = 0x400004e0; +isblank = 0x400004e4; +iscntrl = 0x400004e8; +isdigit = 0x400004ec; +islower = 0x400004f0; +isgraph = 0x400004f4; +isprint = 0x400004f8; +ispunct = 0x400004fc; +isspace = 0x40000500; +isupper = 0x40000504; +toupper = 0x40000508; +tolower = 0x4000050c; +toascii = 0x40000510; +memccpy = 0x40000514; +memchr = 0x40000518; +memrchr = 0x4000051c; +strcasecmp = 0x40000520; +strcasestr = 0x40000524; +strcat = 0x40000528; +strdup = 0x4000052c; +strchr = 0x40000530; +strcspn = 0x40000534; +strcoll = 0x40000538; +strlcat = 0x4000053c; +strlcpy = 0x40000540; +strlwr = 0x40000544; +strncasecmp = 0x40000548; +strncat = 0x4000054c; +strndup = 0x40000550; +strnlen = 0x40000554; +strrchr = 0x40000558; +strsep = 0x4000055c; +strspn = 0x40000560; +strtok_r = 0x40000564; +strupr = 0x40000568; +longjmp = 0x4000056c; +setjmp = 0x40000570; +abs = 0x40000574; +div = 0x40000578; +labs = 0x4000057c; +ldiv = 0x40000580; +qsort = 0x40000584; +rand_r = 0x40000588; +rand = 0x4000058c; +srand = 0x40000590; +utoa = 0x40000594; +itoa = 0x40000598; +atoi = 0x4000059c; +atol = 0x400005a0; +strtol = 0x400005a4; +strtoul = 0x400005a8; +fflush = 0x400005ac; +_fflush_r = 0x400005b0; +_fwalk = 0x400005b4; +_fwalk_reent = 0x400005b8; +__smakebuf_r = 0x400005bc; +__swhatbuf_r = 0x400005c0; +__swbuf_r = 0x400005c4; +__swbuf = 0x400005c8; +__swsetup_r = 0x400005cc; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4087ffd4; +_global_impure_ptr = 0x4087ffd0; + diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld new file mode 100644 index 00000000000..8fbe9c26516 --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.rvfp.ld @@ -0,0 +1,120 @@ +/* ROM function interface esp32c5.rom.rvfp.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rvfplibsf + ***************************************/ + +/* Functions */ +__addsf3 = 0x400009e0; +__eqsf2 = 0x400009e4; +__extendsfdf2 = 0x400009e8; +__fixsfsi = 0x400009ec; +__fixunssfsi = 0x400009f0; +__floatdisf = 0x400009f4; +__floatsisf = 0x400009f8; +__floatundisf = 0x400009fc; +__floatunsisf = 0x40000a00; +__gesf2 = 0x40000a04; +__gtsf2 = 0x40000a08; +__lesf2 = 0x40000a0c; +__ltsf2 = 0x40000a10; +__mulsf3 = 0x40000a14; +__nesf2 = 0x40000a18; +__subsf3 = 0x40000a1c; +__truncdfsf2 = 0x40000a20; + + +/*************************************** + Group rvfplibdf + ***************************************/ + +/* Functions */ +__adddf3 = 0x40000a24; +__eqdf2 = 0x40000a28; +__fixdfdi = 0x40000a2c; +__fixdfsi = 0x40000a30; +__fixsfdi = 0x40000a34; +__fixunsdfsi = 0x40000a38; +__fixunssfdi = 0x40000a3c; +__floatdidf = 0x40000a40; +__floatsidf = 0x40000a44; +__floatundidf = 0x40000a48; +__floatunsidf = 0x40000a4c; +__gedf2 = 0x40000a50; +__gtdf2 = 0x40000a54; +__ledf2 = 0x40000a58; +__ltdf2 = 0x40000a5c; +__muldf3 = 0x40000a60; +__nedf2 = 0x40000a64; +__subdf3 = 0x40000a68; + +/*************************************** + Group libgcc +***************************************/ + +/* Functions */ +__divsf3 = 0x40000874; +__negsf2 = 0x4000089c; +__powisf2 = 0x400008a4; +__unordsf2 = 0x400008b0; +__absvdi2 = 0x400008b4; +__absvsi2 = 0x400008b8; +__addvdi3 = 0x400008c0; +__addvsi3 = 0x400008c4; +__ashldi3 = 0x400008c8; +__ashrdi3 = 0x400008cc; +__bswapdi2 = 0x400008d0; +__bswapsi2 = 0x400008d4; +__clear_cache = 0x400008d8; +__clrsbdi2 = 0x400008dc; +__clrsbsi2 = 0x400008e0; +__clzdi2 = 0x400008e4; +__clzsi2 = 0x400008e8; +__cmpdi2 = 0x400008ec; +__ctzdi2 = 0x400008f0; +__ctzsi2 = 0x400008f4; +__divdc3 = 0x400008f8; +__divdf3 = 0x400008fc; +__divdi3 = 0x40000900; +__divsc3 = 0x40000904; +__divsi3 = 0x40000908; +__ffsdi2 = 0x40000914; +__ffssi2 = 0x40000918; +__gcc_bcmp = 0x4000094c; +__lshrdi3 = 0x4000095c; +__moddi3 = 0x40000964; +__modsi3 = 0x40000968; +__muldc3 = 0x4000096c; +__muldi3 = 0x40000974; +__mulsc3 = 0x40000978; +__mulsi3 = 0x4000097c; +__mulvdi3 = 0x40000980; +__mulvsi3 = 0x40000984; +__negdf2 = 0x4000098c; +__negdi2 = 0x40000990; +__negvdi2 = 0x40000994; +__negvsi2 = 0x40000998; +__paritysi2 = 0x4000099c; +__popcountdi2 = 0x400009a0; +__popcountsi2 = 0x400009a4; +__powidf2 = 0x400009a8; +__subvdi3 = 0x400009b0; +__subvsi3 = 0x400009b4; +__ucmpdi2 = 0x400009b8; +__udivdi3 = 0x400009bc; +__udivmoddi4 = 0x400009c0; +__udivsi3 = 0x400009c4; +__udiv_w_sdiv = 0x400009c8; +__umoddi3 = 0x400009cc; +__umodsi3 = 0x400009d0; +__unorddf2 = 0x400009d4; +__extenddftf2 = 0x400009d8; +__trunctfdf2 = 0x400009dc; diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld new file mode 100644 index 00000000000..7528ca7c743 --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld @@ -0,0 +1,161 @@ +/* ROM function interface esp32c5.rom.spiflash.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group spi_flash_cache + ***************************************/ + +/* Functions */ +spi_flash_disable_cache = 0x400001f0; +spi_flash_restore_cache = 0x400001f4; +spi_flash_cache_enabled = 0x400001f8; +spi_flash_enable_cache = 0x400001fc; +esp_enable_cache_flash_wrap = 0x40000200; + + +/*************************************** + Group spi_flash_mmap + ***************************************/ + +/* Functions */ +spi_flash_mmap_os_func_set = 0x40000204; +spi_flash_mmap_page_num_init = 0x40000208; +spi_flash_mmap = 0x4000020c; +spi_flash_mmap_pages = 0x40000210; +spi_flash_munmap = 0x40000214; +spi_flash_mmap_dump = 0x40000218; +spi_flash_check_and_flush_cache = 0x4000021c; +spi_flash_mmap_get_free_pages = 0x40000220; +spi_flash_cache2phys = 0x40000224; +spi_flash_phys2cache = 0x40000228; + + +/*************************************** + Group esp_flash + ***************************************/ + +/* Functions */ +esp_flash_chip_driver_initialized = 0x4000022c; +esp_flash_read_id = 0x40000230; +esp_flash_get_size = 0x40000234; +esp_flash_erase_chip = 0x40000238; +esp_flash_erase_region = 0x4000023c; +esp_flash_get_chip_write_protect = 0x40000240; +esp_flash_set_chip_write_protect = 0x40000244; +esp_flash_get_protectable_regions = 0x40000248; +esp_flash_get_protected_region = 0x4000024c; +esp_flash_set_protected_region = 0x40000250; +esp_flash_read = 0x40000254; +esp_flash_write = 0x40000258; +esp_flash_write_encrypted = 0x4000025c; +esp_flash_read_encrypted = 0x40000260; +esp_flash_get_io_mode = 0x40000264; +esp_flash_set_io_mode = 0x40000268; +spi_flash_boot_attach = 0x4000026c; +esp_flash_read_chip_id = 0x40000270; +detect_spi_flash_chip = 0x40000274; +esp_flash_suspend_cmd_init = 0x40000278; +/* Data (.data, .bss, .rodata) */ +esp_flash_default_chip = 0x4087ffe8; +esp_flash_api_funcs = 0x4087ffe4; + + +/*************************************** + Group spi_flash_chips + ***************************************/ + +/* Functions */ +spi_flash_chip_generic_probe = 0x4000027c; +spi_flash_chip_generic_detect_size = 0x40000280; +spi_flash_chip_generic_write = 0x40000284; +spi_flash_chip_generic_write_encrypted = 0x40000288; +spi_flash_chip_generic_set_write_protect = 0x4000028c; +spi_flash_common_write_status_16b_wrsr = 0x40000290; +spi_flash_chip_generic_reset = 0x40000294; +spi_flash_chip_generic_erase_chip = 0x40000298; +spi_flash_chip_generic_erase_sector = 0x4000029c; +spi_flash_chip_generic_erase_block = 0x400002a0; +spi_flash_chip_generic_page_program = 0x400002a4; +spi_flash_chip_generic_get_write_protect = 0x400002a8; +spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400002ac; +spi_flash_chip_generic_read_reg = 0x400002b0; +spi_flash_chip_generic_yield = 0x400002b4; +spi_flash_generic_wait_host_idle = 0x400002b8; +spi_flash_chip_generic_wait_idle = 0x400002bc; +spi_flash_chip_generic_config_host_io_mode = 0x400002c0; +spi_flash_chip_generic_read = 0x400002c4; +spi_flash_common_read_status_8b_rdsr2 = 0x400002c8; +spi_flash_chip_generic_get_io_mode = 0x400002cc; +spi_flash_common_read_status_8b_rdsr = 0x400002d0; +spi_flash_common_write_status_8b_wrsr = 0x400002d4; +spi_flash_common_write_status_8b_wrsr2 = 0x400002d8; +spi_flash_common_set_io_mode = 0x400002dc; +spi_flash_chip_generic_set_io_mode = 0x400002e0; +spi_flash_chip_generic_read_unique_id = 0x400002e4; +spi_flash_chip_generic_get_caps = 0x400002e8; +spi_flash_chip_generic_suspend_cmd_conf = 0x400002ec; +spi_flash_chip_gd_get_io_mode = 0x400002f0; +spi_flash_chip_gd_probe = 0x400002f4; +spi_flash_chip_gd_set_io_mode = 0x400002f8; +/* Data (.data, .bss, .rodata) */ +spi_flash_chip_generic_config_data = 0x4087ffe0; +spi_flash_encryption = 0x4087ffdc; + + +/*************************************** + Group memspi_host + ***************************************/ + +/* Functions */ +memspi_host_read_id_hs = 0x400002fc; +memspi_host_read_status_hs = 0x40000300; +memspi_host_flush_cache = 0x40000304; +memspi_host_erase_chip = 0x40000308; +memspi_host_erase_sector = 0x4000030c; +memspi_host_erase_block = 0x40000310; +memspi_host_program_page = 0x40000314; +memspi_host_read = 0x40000318; +memspi_host_set_write_protect = 0x4000031c; +memspi_host_set_max_read_len = 0x40000320; +memspi_host_read_data_slicer = 0x40000324; +memspi_host_write_data_slicer = 0x40000328; + + +/*************************************** + Group hal_spiflash + ***************************************/ + +/* Functions */ +spi_flash_hal_poll_cmd_done = 0x4000032c; +spi_flash_hal_device_config = 0x40000330; +spi_flash_hal_configure_host_io_mode = 0x40000334; +spi_flash_hal_common_command = 0x40000338; +spi_flash_hal_read = 0x4000033c; +spi_flash_hal_erase_chip = 0x40000340; +spi_flash_hal_erase_sector = 0x40000344; +spi_flash_hal_erase_block = 0x40000348; +spi_flash_hal_program_page = 0x4000034c; +spi_flash_hal_set_write_protect = 0x40000350; +spi_flash_hal_host_idle = 0x40000354; +spi_flash_hal_check_status = 0x40000358; +spi_flash_hal_setup_read_suspend = 0x4000035c; +spi_flash_hal_setup_auto_suspend_mode = 0x40000360; +spi_flash_hal_setup_auto_resume_mode = 0x40000364; +spi_flash_hal_disable_auto_suspend_mode = 0x40000368; +spi_flash_hal_disable_auto_resume_mode = 0x4000036c; +spi_flash_hal_resume = 0x40000370; +spi_flash_hal_suspend = 0x40000374; +spi_flash_encryption_hal_enable = 0x40000378; +spi_flash_encryption_hal_disable = 0x4000037c; +spi_flash_encryption_hal_prepare = 0x40000380; +spi_flash_encryption_hal_done = 0x40000384; +spi_flash_encryption_hal_destroy = 0x40000388; +spi_flash_encryption_hal_check = 0x4000038c; + diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld new file mode 100644 index 00000000000..e139c043c9d --- /dev/null +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.version.ld @@ -0,0 +1,8 @@ +/* ROM version variables for esp32c5 + * + * These addresses should be compatible with any ROM version for this chip. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ +_rom_chip_id = 0x40000010; +_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in index df5e153a0d2..53c794d20e4 100644 --- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -82,3 +82,7 @@ config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE config ESP_ROM_RAM_APP_NEEDS_MMU_INIT bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h index 1eeab3bd3e8..adf8d09a88d 100644 --- a/components/esp_rom/esp32c6/esp_rom_caps.h +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -26,3 +26,4 @@ #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index 9e95fbf265f..be23a754fbc 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -70,3 +70,7 @@ config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE config ESP_ROM_RAM_APP_NEEDS_MMU_INIT bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 375f91137d5..d61be8f2606 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -23,3 +23,4 @@ #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32p4/Kconfig.soc_caps.in b/components/esp_rom/esp32p4/Kconfig.soc_caps.in index f91659d514b..ec068d6ac89 100644 --- a/components/esp_rom/esp32p4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32p4/Kconfig.soc_caps.in @@ -46,3 +46,11 @@ config ESP_ROM_HAS_LAYOUT_TABLE config ESP_ROM_WDT_INIT_PATCH bool default y + +config ESP_ROM_HAS_LP_ROM + bool + default y + +config ESP_ROM_WITHOUT_REGI2C + bool + default y diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h index 80885d5a96d..3f9478162f4 100644 --- a/components/esp_rom/esp32p4/esp_rom_caps.h +++ b/components/esp_rom/esp32p4/esp_rom_caps.h @@ -17,3 +17,5 @@ #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_HAS_LP_ROM (1) // ROM also has a LP ROM placed in LP memory +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld index d39827a70a5..92dd194fd51 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld @@ -175,8 +175,9 @@ g_flash_guard_ops = 0x4ff3fff0; ***************************************/ /* Functions */ -systimer_hal_init = 0x4fc00228; -systimer_hal_deinit = 0x4fc0022c; +/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ +/* systimer_hal_init = 0x4fc00228; */ +/* systimer_hal_deinit = 0x4fc0022c; */ systimer_hal_set_tick_rate_ops = 0x4fc00230; systimer_hal_get_counter_value = 0x4fc00234; systimer_hal_get_time = 0x4fc00238; diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index c748eef1660..c8dc1b24b96 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -34,3 +34,7 @@ config ESP_ROM_USB_OTG_NUM config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index 100711d8274..b80ede21ceb 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -14,3 +14,4 @@ #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_USB_OTG_NUM (3) // The serial port ID (UART, USB, ...) of USB_OTG CDC in the ROM. #define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index 94b178a10e6..c0f584018dd 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -86,3 +86,7 @@ config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG config ESP_ROM_HAS_CACHE_WRITEBACK_BUG bool default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index abb4bd39e01..0ad7ed84180 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -27,3 +27,4 @@ #define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value #define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti #define ESP_ROM_HAS_CACHE_WRITEBACK_BUG (1) // ROM api Cache_WriteBack_Addr address or size misalignment may cause cache hit with wrong value. +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/include/esp32c5/rom/aes.h b/components/esp_rom/include/esp32c5/rom/aes.h new file mode 100644 index 00000000000..0af20666374 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/aes.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_AES_H_ +#define _ROM_AES_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AES_BLOCK_SIZE 16 + +enum AES_TYPE { + AES_ENC, + AES_DEC, +}; + +enum AES_BITS { + AES128, + AES192, + AES256 +}; + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); + +int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); + +int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); + +void ets_aes_block(const void *input, void *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_AES_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/bigint.h b/components/esp_rom/include/esp32c5/rom/bigint.h new file mode 100644 index 00000000000..ef82674b330 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/bigint.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_BIGINT_H_ +#define _ROM_BIGINT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void ets_bigint_enable(void); + +void ets_bigint_disable(void); + +int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); + +int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); + +int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); + +void ets_bigint_wait_finish(void); + +int ets_bigint_getz(uint32_t *z, uint32_t len_words); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_BIGINT_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/cache.h b/components/esp_rom/include/esp32c5/rom/cache.h new file mode 100644 index 00000000000..b2f09f32122 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/cache.h @@ -0,0 +1,609 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 16384 +#define MIN_ICACHE_WAYS 8 +#define MAX_ICACHE_WAYS 8 +#define MAX_CACHE_WAYS 8 +#define MIN_CACHE_LINE_SIZE 32 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 1 +#define CACHE_MEMORY_BANK_NUM 1 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +typedef enum { + MMU_PAGE_MODE_64KB = 0, + MMU_PAGE_MODE_32KB = 1, + MMU_PAGE_MODE_16KB = 2, + MMU_PAGE_MODE_8KB = 3, + MMU_PAGE_MODE_INVALID, +} mmu_page_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid:1; /*!< the tag item is valid or not */ + uint32_t lock:1; /*!< the cache line is locked or not */ + uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ + uint32_t reserved:14; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +struct cache_internal_stub_table { + uint32_t (* icache_line_size)(void); + uint32_t (* icache_addr)(uint32_t addr); + uint32_t (* dcache_addr)(uint32_t addr); + void (* invalidate_icache_items)(uint32_t addr, uint32_t items); + void (* lock_icache_items)(uint32_t addr, uint32_t items); + void (* unlock_icache_items)(uint32_t addr, uint32_t items); + uint32_t (* suspend_icache_autoload)(void); + void (* resume_icache_autoload)(uint32_t autoload); + void (* freeze_icache_enable)(cache_freeze_mode_t mode); + void (* freeze_icache_disable)(void); + int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); +}; + +/* Defined in the interface file, default value is rom_default_cache_internal_table */ +extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; + +typedef void (* cache_op_start)(void); +typedef void (* cache_op_end)(void); + +typedef struct { + cache_op_start start; + cache_op_end end; +} cache_op_cb_t; + +/* Defined in the interface file, default value is NULL */ +extern const cache_op_cb_t* rom_cache_op_cb; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus. + * + * @param None + * + * @return None + */ +void ROM_Boot_Cache_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t senitive : Config this page should apply flash encryption or not + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c5, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c5, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode * mode); + +/** + * @brief Set cache page mode. + * + * @param mmu_page_mode_t + * + * @return None + */ +void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode); + +/** + * @brief Get cache page mode. + * + * @param None + * + * @return page mode + */ +mmu_page_mode_t MMU_Get_Page_Mode(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_ICache_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_ICache_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_ICache_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_ICache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_ICache_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_ICache_Autoload(const struct autoload_config * config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_ICache_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_ICache_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_ICache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_ICache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_ICache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_ICache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_ICache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_ICache_Line_Size(void); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_ICache_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + +#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ + Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c5/rom/crc.h b/components/esp_rom/include/esp32c5/rom/crc.h new file mode 100644 index 00000000000..de7002f7a52 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/crc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ROM_CRC_H +#define ROM_CRC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup crc_apis, uart configuration and communication related apis + * @brief crc apis + */ + +/** @addtogroup crc_apis + * @{ + */ + + +/* Standard CRC8/16/32 algorithms. */ +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/components/esp_rom/include/esp32c5/rom/digital_signature.h b/components/esp_rom/include/esp32c5/rom/digital_signature.h new file mode 100644 index 00000000000..e2f62bb15ef --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/digital_signature.h @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ETS_DS_MAX_BITS 3072 + +#define ETS_DS_IV_LEN 16 + +/* Length of parameter 'C' stored in flash (not including IV) + + Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8) + + Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware +*/ +#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8) + +/* Encrypted ETS data. Recommended to store in flash in this format. + */ +typedef struct { + /* RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + */ + unsigned rsa_length; + + /* IV value used to encrypt 'c' */ + uint8_t iv[ETS_DS_IV_LEN]; + + /* Encrypted Digital Signature parameters. Result of AES-CBC encryption + of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ETS_DS_C_LEN]; +} ets_ds_data_t; + +typedef enum { + ETS_DS_OK, + ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ + ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ + ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ + ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ +} ets_ds_result_t; + +void ets_ds_enable(void); + +void ets_ds_disable(void); + + +/* + * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral + * + * - @param message Pointer to message (or padded digest) containing the message to sign. Should be + * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data + * in flash. + * + * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling + * this function, and is responsible for calling ets_ds_finish_sign() and then + * ets_hmac_invalidate_downstream() afterwards. + * + * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, + * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. + */ +ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); + + +/* + * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() + * + * A result of false indicates that a call to ets_ds_finish_sign() will not block. + * + * Only valid if ets_ds_enable() has been called. + */ +bool ets_ds_is_busy(void); + + +/* @brief Finish signing a message using the Digital Signature peripheral + * + * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until + * peripheral is no longer busy. + * + * - @param signature Pointer to buffer to contain the signature. Should be + * (data->rsa_length + 1)*4 bytes long. + * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() + * + * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, + * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the + * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a + * digest is produced anyhow.) + */ +ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); + + +/* Plaintext parameters used by Digital Signature. + + Not used for signing with DS peripheral, but can be encrypted + in-device by calling ets_ds_encrypt_params() +*/ +typedef struct { + uint32_t Y[ETS_DS_MAX_BITS / 32]; + uint32_t M[ETS_DS_MAX_BITS / 32]; + uint32_t Rb[ETS_DS_MAX_BITS / 32]; + uint32_t M_prime; + uint32_t length; +} ets_ds_p_data_t; + +typedef enum { + ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ + ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ +} ets_ds_key_t; + +/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. + * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) + * + * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. + */ +ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); + + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c5/rom/ecdsa.h b/components/esp_rom/include/esp32c5/rom/ecdsa.h new file mode 100644 index 00000000000..7be1fada95b --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/ecdsa.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef enum { + ECDSA_CURVE_P192 = 1, + ECDSA_CURVE_P256 = 2 +} ECDSA_CURVE; + +int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c5/rom/efuse.h b/components/esp_rom/include/esp32c5/rom/efuse.h new file mode 100644 index 00000000000..6cd9f4b377e --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/efuse.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_EFUSE_H_ +#define _ROM_EFUSE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO8 is low when digital reset. + * 2 for uart print when GPIO8 is high when digital reset. + * 3 for uart force slient + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_EFUSE_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/ets_sys.h b/components/esp_rom/include/esp32c5/rom/ets_sys.h new file mode 100644 index 00000000000..7c04af3a54c --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/ets_sys.h @@ -0,0 +1,432 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_ETS_SYS_H_ +#define _ROM_ETS_SYS_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + + + + + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + + + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +/** + * @} + */ + +#ifndef MAC2STR +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" +#endif + +#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) + +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) +typedef enum { + OK = 0, + FAIL, + PENDING, + BUSY, + CANCEL, +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_ETS_SYS_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/hmac.h b/components/esp_rom/include/esp32c5/rom/hmac.h new file mode 100644 index 00000000000..126b8a46a10 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/hmac.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_HMAC_H_ +#define _ROM_HMAC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "efuse.h" + +void ets_hmac_enable(void); + +void ets_hmac_disable(void); + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); + +#ifdef __cplusplus +} +#endif + +#endif // _ROM_HMAC_H_ diff --git a/components/esp_rom/include/esp32c5/rom/libc_stubs.h b/components/esp_rom/include/esp32c5/rom/libc_stubs.h new file mode 100644 index 00000000000..e31dcc6e679 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/libc_stubs.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ROM_LIBC_STUBS_H_ +#define _ROM_LIBC_STUBS_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* +ESP32-C5 ROM code contains implementations of some of C library functions. +Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall +implementation defined in the following struct. + +The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to +set the address + +So, before using any of the C library functions (except for pure functions and memcpy/memset functions), +application must allocate syscall table structure for each CPU being used, and populate it with pointers +to actual implementations of corresponding syscalls. +*/ + +struct syscall_stub_table { + struct _reent *(*__getreent)(void); + void *(*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void *); + void *(*_realloc_r)(struct _reent *r, void *, size_t); + void *(*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char *); + int (*_rename_r)(struct _reent *r, const char *, const char *); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char *); + int (*_link_r)(struct _reent *r, const char *, const char *); + int (*_stat_r)(struct _reent *r, const char *, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void *(*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); + void (*_retarget_lock_init)(_LOCK_T *lock); + void (*_retarget_lock_init_recursive)(_LOCK_T *lock); + void (*_retarget_lock_close)(_LOCK_T lock); + void (*_retarget_lock_close_recursive)(_LOCK_T lock); + void (*_retarget_lock_acquire)(_LOCK_T lock); + void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); + int (*_retarget_lock_try_acquire)(_LOCK_T lock); + int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); + void (*_retarget_lock_release)(_LOCK_T lock); + void (*_retarget_lock_release_recursive)(_LOCK_T lock); + int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); + void (*__assert_func) (const char *file, int line, const char *func, const char *failedexpr) __attribute__((__noreturn__)); + void (*__sinit) (struct _reent *r); + void (*_cleanup_r) (struct _reent *r); +}; + +extern struct syscall_stub_table *syscall_table_ptr; + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* _ROM_LIBC_STUBS_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/lldesc.h b/components/esp_rom/include/esp32c5/rom/lldesc.h new file mode 100644 index 00000000000..d5cb674df16 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/lldesc.h @@ -0,0 +1,139 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_LLDESC_H_ +#define _ROM_LLDESC_H_ + +#include + +#include "sys/queue.h" +#include "esp_rom_lldesc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LLDESC_TX_MBLK_SIZE 268 /* */ +#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ +#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ +#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ +#ifdef ESP_MAC_5 +#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ +#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 +#else +#ifdef SBUF_RXTX +#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ +#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ +#endif +#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ + +#ifdef IEEE80211_RX_AMPDU +#define LLDESC_RX_MBLK_NUM 30 +#else +#define LLDESC_RX_MBLK_NUM 10 +#endif /*IEEE80211_RX_AMPDU*/ + +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 +#endif /* !ESP_MAC_5 */ + +typedef struct tx_ampdu_entry_s { + uint32_t sub_len : 12, + dili_num : 7, + : 1, + null_byte: 2, + data : 1, + enc : 1, + seq : 8; +} tx_ampdu_entry_t; + +typedef struct lldesc_chain_s { + lldesc_t *head; + lldesc_t *tail; +} lldesc_chain_t; + +#ifdef SBUF_RXTX +enum sbuf_mask_s { + SBUF_MOVE_NO = 0, + SBUF_MOVE_TX2RX, + SBUF_MOVE_RX2TX, +} ; + +#define SBUF_MOVE_STEP 8 +#endif +#define LLDESC_SIZE sizeof(struct lldesc_s) + +/* SLC Descriptor */ +#define LLDESC_OWNER_MASK 0x80000000 +#define LLDESC_OWNER_SHIFT 31 +#define LLDESC_SW_OWNED 0 +#define LLDESC_HW_OWNED 1 + +#define LLDESC_EOF_MASK 0x40000000 +#define LLDESC_EOF_SHIFT 30 + +#define LLDESC_SOSF_MASK 0x20000000 +#define LLDESC_SOSF_SHIFT 29 + +#define LLDESC_LENGTH_MASK 0x00fff000 +#define LLDESC_LENGTH_SHIFT 12 + +#define LLDESC_SIZE_MASK 0x00000fff +#define LLDESC_SIZE_SHIFT 0 + +#define LLDESC_ADDR_MASK 0x000fffff + +void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner, + lldesc_t **head, +#ifdef TO_HOST_RESTART + lldesc_t **one_before_tail, +#endif + lldesc_t **tail); + +static inline uint32_t lldesc_get_chain_length(lldesc_t *head) +{ + lldesc_t *ds = head; + uint32_t len = 0; + + while (ds) { + len += ds->length; + ds = STAILQ_NEXT(ds, qe); + } + + return len; +} + +static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) +{ + ds->owner = owner; + ds->eof = eof; + ds->sosf = sosf; + ds->length = len; +} + +#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \ + (_desc)->owner = (_owner); \ + (_desc)->eof = (_eof); \ + (_desc)->sosf = (_sosf); \ + (_desc)->length = (_len); \ +} while(0) + +#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) + +#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_LLDESC_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/md5_hash.h b/components/esp_rom/include/esp32c5/rom/md5_hash.h new file mode 100644 index 00000000000..3c5e10d1bf6 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/md5_hash.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * MD5 internal definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#ifndef _ROM_MD5_HASH_H_ +#define _ROM_MD5_HASH_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +}; + +void MD5Init(struct MD5Context *context); +void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *context); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_MD5_HASH_H_ */ diff --git a/components/nvs_flash/host_test/nvs_host_test/main/main.cpp b/components/esp_rom/include/esp32c5/rom/miniz.h similarity index 50% rename from components/nvs_flash/host_test/nvs_host_test/main/main.cpp rename to components/esp_rom/include/esp32c5/rom/miniz.h index dddf85b1d5a..f0baecabdce 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/main.cpp +++ b/components/esp_rom/include/esp32c5/rom/miniz.h @@ -3,5 +3,6 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#define CATCH_CONFIG_MAIN -#include "catch.hpp" + +#warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead" +#include "../../miniz.h" diff --git a/components/esp_rom/include/esp32c5/rom/rom_layout.h b/components/esp_rom/include/esp32c5/rom/rom_layout.h new file mode 100644 index 00000000000..18b6d79ba7c --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/rom_layout.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SUPPORT_BTDM 0 +#define SUPPORT_BTBB 0 +#define SUPPORT_WIFI 1 +#define SUPPORT_USB_DWCOTG 0 +#define SUPPORT_COEXIST 1 +#define SUPPORT_MBEDTLS 0 + +/* Structure and functions for returning ROM global layout + * + * This is for address symbols defined in the linker script, which may change during ECOs. + */ +typedef struct { + void *dram0_stack_shared_mem_start; + void *dram0_rtos_reserved_start; + void *stack_sentry; + void *stack; + +#if SUPPORT_BTDM + void *data_start_btdm; + void *data_end_btdm; + void *bss_start_btdm; + void *bss_end_btdm; + void *data_start_btdm_rom; + void *data_start_interface_btdm; + void *data_end_interface_btdm; + void *bss_start_interface_btdm; + void *bss_end_interface_btdm; +#endif + +#if SUPPORT_BTBB + void *dram_start_btbbrom; + void *dram_end_btbbrom; +#endif + +#if SUPPORT_BTDM || SUPPORT_WIFI + void *dram_start_phyrom; + void *dram_end_phyrom; +#endif + +#if SUPPORT_WIFI + void *dram_start_net80211; + void *dram_end_net80211; + void *data_start_interface_net80211; + void *data_end_interface_net80211; + void *bss_start_interface_net80211; + void *bss_end_interface_net80211; + void *dram_start_pp; + void *dram_end_pp; + void *data_start_interface_pp; + void *data_end_interface_pp; + void *bss_start_interface_pp; + void *bss_end_interface_pp; +#endif + +#if SUPPORT_COEXIST + void *dram_start_coexist; + void *dram_end_coexist; + void *data_start_interface_coexist; + void *data_end_interface_coexist; + void *bss_start_interface_coexist; + void *bss_end_interface_coexist; +#endif + +#if SUPPORT_MBEDTLS + void *dram_start_mbedtls_rom; + void *dram_end_mbedtls_rom; +#endif + +#if SUPPORT_USB_DWCOTG + void *dram_start_usb_dwcotg_rom; + void *dram_end_usb_dwcotg_rom; +#else + //Two reserved members are defined here, so the structure will not be broken, + //please keep in mind that there is no memory can be released between + //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom. + void *dram_start_usb_reserved_rom; + void *dram_end_usb_reserved_rom; +#endif + + void *dram_start_uart_rom; + void *dram_end_uart_rom; +} ets_rom_layout_t; + +extern const ets_rom_layout_t *const ets_rom_layout_p; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c5/rom/rsa_pss.h b/components/esp_rom/include/esp32c5/rom/rsa_pss.h new file mode 100644 index 00000000000..d6140879c83 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/rsa_pss.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_RSA_PSS_H_ +#define _ROM_RSA_PSS_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_SIG_LEN 384 /* Bytes */ +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef struct { + uint8_t n[384]; /* Public key modulus */ + uint32_t e; /* Public key exponent */ + uint8_t rinv[384]; + uint32_t mdash; +} ets_rsa_pubkey_t; + +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); + +void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); + +bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/esp_rom/include/esp32c5/rom/rtc.h b/components/esp_rom/include/esp32c5/rom/rtc.h new file mode 100644 index 00000000000..6a046fa25a4 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/rtc.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_assert.h" + +#include "soc/soc.h" +#include "soc/lp_aon_reg.h" +#include "soc/reset_reasons.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * LP Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP + * + * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * LP_AON_STORE0_REG Reserved + * LP_AON_STORE1_REG RTC_SLOW_CLK calibration value + * LP_AON_STORE2_REG Boot time, low word + * LP_AON_STORE3_REG Boot time, high word + * LP_AON_STORE4_REG External XTAL frequency + * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH + * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY + * LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC + * LP_AON_STORE8_REG Store light sleep wake stub addr + * LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep) + ************************************************************************************* + */ + +#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG +#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG +#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG +#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG +#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG +#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG +#define SLEEP_MODE_REG LP_AON_STORE9_REG + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. + +typedef enum { + AWAKE = 0, // +#include +#include "ets_sys.h" +#include "ecdsa.h" +#include "rsa_pss.h" +#include "esp_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Anti-FI measure: use full words for success/fail, instead of + 0/non-zero +*/ +typedef enum { + SB_SUCCESS = 0x3A5A5AA5, + SB_FAILED = 0x7533885E, +} ets_secure_boot_status_t; + +/* Verify bootloader image (reconfigures cache to map), + with key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If stage_load parameter is true, bootloader is copied into staging + buffer in RAM at the same time. + + If result is SB_SUCCESS, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL +*/ +ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access except for RSA peripheral. + + If result is SB_SUCCESS, the image_digest value is copied into verified_digest. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); + +/* Revoke a public key digest in efuse. + @param index Digest to revoke. Must be 0, 1 or 2. + */ +void ets_secure_boot_revoke_public_key_digest(int index); + +#define CRC_SIGN_BLOCK_LEN 1196 +#define SIG_BLOCK_PADDING 4096 +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block + + (Up to 3 in a signature sector are appended to the image) + */ +#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME + +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME + +struct __attribute((packed)) ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + struct { + struct { + uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */ + uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */ + } key; + uint8_t signature[64]; /* r followed by s (both little-endian) */ + uint8_t padding[1031]; + } ecdsa; + uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */ + uint8_t _padding[16]; +}; +#endif + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); + +#define MAX_KEY_DIGESTS 3 + +struct ets_secure_boot_key_digests { + const void *key_digests[MAX_KEY_DIGESTS]; + bool allow_key_revoke; +}; + +#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c5/rom/sha.h b/components/esp_rom/include/esp32c5/rom/sha.h new file mode 100644 index 00000000000..c9eda2fd99f --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/sha.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ROM_SHA_H_ +#define _ROM_SHA_H_ + +#include +#include +#include "ets_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SHA_H_ */ diff --git a/components/esp_rom/include/esp32c5/rom/spi_flash.h b/components/esp_rom/include/esp32c5/rom/spi_flash.h new file mode 100644 index 00000000000..2d782dee4f3 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/spi_flash.h @@ -0,0 +1,458 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_attr.h" +#include "esp_rom_spiflash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +typedef void (* spi_flash_func_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); + +typedef struct { + uint8_t pp_addr_bit_len; + uint8_t se_addr_bit_len; + uint8_t be_addr_bit_len; + uint8_t rd_addr_bit_len; + uint32_t read_sub_len; + uint32_t write_sub_len; + spi_flash_op_t unlock; + spi_flash_erase_t erase_sector; + spi_flash_erase_t erase_block; + spi_flash_rd_t read; + spi_flash_wr_t write; + spi_flash_ewr_t encrypt_write; + spi_flash_func_t check_sus; + spi_flash_wren_t wren; + spi_flash_op_t wait_idle; + spi_flash_erase_area_t erase_area; +} spiflash_legacy_funcs_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** + * @brief Clear WEL bit unconditionally. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); + +/** + * @brief Set WREN bit. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from falsh by rom code, function usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c5/rom/uart.h b/components/esp_rom/include/esp32c5/rom/uart.h new file mode 100644 index 00000000000..9045c42f6f6 --- /dev/null +++ b/components/esp_rom/include/esp32c5/rom/uart.h @@ -0,0 +1,353 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_UART_H_ +#define _ROM_UART_H_ + +#include "esp_types.h" +#include "esp_attr.h" +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +#define RX_BUFF_SIZE 0x400 +#define TX_BUFF_SIZE 100 + +//uart int enalbe register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_UART_H_ */ diff --git a/components/esp_rom/include/esp32p4/rom/gpio.h b/components/esp_rom/include/esp32p4/rom/gpio.h index c5439256eb3..214eaff048c 100644 --- a/components/esp_rom/include/esp32p4/rom/gpio.h +++ b/components/esp_rom/include/esp32p4/rom/gpio.h @@ -85,7 +85,7 @@ void gpio_init(void); void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); /** - * @brief Change GPIO(32-56) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * @brief Change GPIO(32-54) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). * There is no particular ordering guaranteed; so if the order of writes is significant, * calling code should divide a single call into multiple calls. * @@ -111,7 +111,7 @@ void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enabl uint32_t gpio_input_get(void); /** - * @brief Sample the value of GPIO input pins(32-56) and returns a bitmask. + * @brief Sample the value of GPIO input pins(32-54) and returns a bitmask. * * @param None * @@ -197,7 +197,7 @@ void gpio_pin_wakeup_disable(void); /** * @brief set gpio input to a signal, one gpio can input to several signals. * - * @param uint32_t gpio : gpio number, 0~56 + * @param uint32_t gpio : gpio number, 0~54 * gpio == 0x3E, input 0 to signal * gpio == 0x3F, input 1 to signal * @@ -212,7 +212,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); /** * @brief set signal output to gpio, one signal can output to several gpios. * - * @param uint32_t gpio : gpio number, 0~56 + * @param uint32_t gpio : gpio number, 0~54 * * @param uint32_t signal_idx : signal index. * signal_idx == 0x100, cancel output put to the gpio @@ -228,7 +228,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_ /** * @brief Select pad as a gpio function from IOMUX. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ @@ -237,7 +237,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num); /** * @brief Set pad driver capability. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @param uint32_t drv : 0-3 * @@ -248,7 +248,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); /** * @brief Pull up the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ @@ -257,7 +257,7 @@ void gpio_pad_pullup(uint32_t gpio_num); /** * @brief Pull down the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ @@ -266,7 +266,7 @@ void gpio_pad_pulldown(uint32_t gpio_num); /** * @brief Unhold the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ @@ -275,7 +275,7 @@ void gpio_pad_unhold(uint32_t gpio_num); /** * @brief Hold the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ @@ -284,7 +284,7 @@ void gpio_pad_hold(uint32_t gpio_num); /** * @brief enable gpio pad input. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ @@ -293,7 +293,7 @@ void gpio_pad_input_enable(uint32_t gpio_num); /** * @brief disable gpio pad input. * - * @param uint32_t gpio_num : gpio number, 0~56 + * @param uint32_t gpio_num : gpio number, 0~54 * * @return None */ diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c new file mode 100644 index 00000000000..c9695022ecf --- /dev/null +++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c @@ -0,0 +1,197 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +// TODO: [ESP32C5] IDF-8824 (inherit from C6) +// #include "soc/i2c_ana_mst_reg.h" +// #include "modem/modem_lpcon_reg.h" +/** + * BB - 0x67 - BIT0 + * TXRF - 0x6B - BIT1 + * SDM - 0x63 - BIT2 + * PLL - 0x62 - BIT3 + * BIAS - 0x6A - BIT4 + * BBPLL - 0x66 - BIT5 + * ULP - 0x61 - BIT6 + * SAR - 0x69 - BIT7 + * PMU - 0x6d - BIT8 +*/ + +#define REGI2C_BIAS_MST_SEL (BIT(8)) +#define REGI2C_BBPLL_MST_SEL (BIT(9)) +#define REGI2C_ULP_CAL_MST_SEL (BIT(10)) +#define REGI2C_SAR_I2C_MST_SEL (BIT(11)) +#define REGI2C_DIG_REG_MST_SEL (BIT(12)) + +#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_ANA_MST_ANA_CONF1_M) + +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ + +#define REGI2C_BBPLL (0x66) +#define REGI2C_BBPLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_DIG_REG (0x6d) +#define REGI2C_DIG_REG_HOSTID 0 + +#define REGI2C_ULP_CAL (0x61) +#define REGI2C_ULP_CAL_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 + +/* SLAVE END */ + +uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); +uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); +void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); +void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); + +__attribute__((unused)) +static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +{ + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // uint32_t i2c_sel = 0; + + // REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + // REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); + + // /* Before config I2C register, enable corresponding slave. */ + // switch (block) { + // case REGI2C_BBPLL : + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); + // break; + // case REGI2C_BIAS : + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); + // break; + // case REGI2C_DIG_REG: + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); + // break; + // case REGI2C_ULP_CAL: + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); + // break; + // case REGI2C_SAR_I2C: + // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); + // break; + // } + + // return (uint8_t)(i2c_sel ? 0: 1); + return (uint8_t)0; +} + +uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // (void)host_id; + // uint8_t i2c_sel = regi2c_enable_block(block); + + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + // return ret; + return (uint8_t)0; +} + +uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // assert(msb - lsb < 8); + // uint8_t i2c_sel = regi2c_enable_block(block); + + // (void)host_id; + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + // uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + // return ret; + return (uint8_t)0; +} + +void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // (void)host_id; + // uint8_t i2c_sel = regi2c_enable_block(block); + + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + // | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + // | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} + +void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + // TODO: [ESP32C5] IDF-8824 (inherit from C6) + // (void)host_id; + // assert(msb - lsb < 8); + // uint8_t i2c_sel = regi2c_enable_block(block); + + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // /*Read the i2c bus register*/ + // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + // temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + // /*Write the i2c bus register*/ + // temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + // temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + // temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + // | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + // | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + // | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c new file mode 100644 index 00000000000..08fff85a74f --- /dev/null +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "soc/i2c_ana_mst_reg.h" +#include "soc/lpperi_reg.h" +/** + * DIG_REG - 0x6D - BIT10 + * PLL_CPU - 0x67 - BIT11 + * PLL_SDIO - 0x62 - BIT6 + * BIAS - 0x6A - BIT12 + * MSPI_XTAL - 0x63 - BIT9 + * PLL_SYS - 0x66 - BIT5 + * PLLA - 0x6F - BIT8 + * SAR_I2C - 0x69 - BIT7 +*/ + +#define REGI2C_DIG_REG_MST_SEL (BIT(10)) +#define REGI2C_PLL_CPU_MST_SEL (BIT(11)) +#define REGI2C_PLL_SDIO_MST_SEL (BIT(6)) +#define REGI2C_BIAS_MST_SEL (BIT(12)) +#define REGI2C_MSPI_XTAL_MST_SEL (BIT(9)) +#define REGI2C_PLL_SYS_MST_SEL (BIT(5)) +#define REGI2C_PLLA_MST_SEL (BIT(8)) +#define REGI2C_SAR_I2C_MST_SEL (BIT(7)) + +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ +#define REGI2C_DIG_REG (0x6d) +#define REGI2C_DIG_REG_HOSTID 0 + +#define REGI2C_CPU_PLL (0x67) +#define REGI2C_CPU_PLL_HOSTID 0 + +#define REGI2C_SDIO_PLL (0x62) +#define REGI2C_SDIO_PLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_MSPI (0x63) +#define REGI2C_MSPI_HOSTID 0 + +#define REGI2C_SYS_PLL (0x66) +#define REGI2C_SYS_PLL_HOSTID 0 + +#define REGI2C_PLLA (0x6f) +#define REGI2C_PLLA_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 +/* SLAVE END */ + +uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); +uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); +void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); +void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); + +static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +{ + REG_SET_BIT(LPPERI_CLK_EN_REG, LPPERI_CK_EN_LP_I2CMST); + SET_PERI_REG_MASK(I2C_ANA_MST_CLK160M_REG, I2C_ANA_MST_CLK_I2C_MST_SEL_160M); + REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0); + REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0); + + switch (block) { + case REGI2C_DIG_REG: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + break; + case REGI2C_CPU_PLL: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL); + break; + case REGI2C_SDIO_PLL: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL); + break; + case REGI2C_BIAS: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + break; + case REGI2C_MSPI: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL); + break; + case REGI2C_SYS_PLL: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL); + break; + case REGI2C_PLLA: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL); + break; + case REGI2C_SAR_I2C: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + break; + } + + return 0; +} + +uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + return ret; +} + +uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + (void)host_id; + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + return ret; +} + +void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + +} + +void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + (void)host_id; + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c index 2d354aebb78..322a236fcad 100644 --- a/components/esp_rom/patches/esp_rom_sys.c +++ b/components/esp_rom/patches/esp_rom_sys.c @@ -44,7 +44,7 @@ IRAM_ATTR void esp_rom_install_uart_printf(void) #if CONFIG_IDF_TARGET_ESP32 extern uint32_t g_ticks_per_us_pro; #if SOC_CPU_CORES_NUM > 1 -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE extern uint32_t g_ticks_per_us_app; #endif #endif @@ -53,7 +53,7 @@ IRAM_ATTR void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us) /* Update scale factors used by esp_rom_delay_us */ g_ticks_per_us_pro = ticks_per_us; #if SOC_CPU_CORES_NUM > 1 -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE g_ticks_per_us_app = ticks_per_us; #endif #endif diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c index 686fc24689e..673220bcc67 100644 --- a/components/esp_rom/patches/esp_rom_systimer.c +++ b/components/esp_rom/patches/esp_rom_systimer.c @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co } #endif // CONFIG_IDF_TARGET_ESP32C2 -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 void systimer_hal_init(systimer_hal_context_t *hal) { hal->dev = &SYSTIMER; diff --git a/components/esp_rom/test_apps/.build-test-rules.yml b/components/esp_rom/test_apps/.build-test-rules.yml index 5d711a1bc06..1eb663e7974 100644 --- a/components/esp_rom/test_apps/.build-test-rules.yml +++ b/components/esp_rom/test_apps/.build-test-rules.yml @@ -1,11 +1,11 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps -components/esp_rom/test_apps: +components/esp_rom/test_apps/linux_rom_apis: + enable: + - if: IDF_TARGET == "linux" + +components/esp_rom/test_apps/rom_tests: disable_test: - if: IDF_TARGET in ["esp32", "esp32c2"] temporary: false reason: lack of memory for testing miniz compressing - disable: - - if: IDF_TARGET in ["esp32p4"] - temporary: true - reason: Not supported on p4 # TODO: IDF-8071 diff --git a/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt b/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt index f0f082fde32..baaac731700 100644 --- a/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt +++ b/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt @@ -1,5 +1,8 @@ idf_component_register(SRCS "rom_test.cpp" - INCLUDE_DIRS - "." - $ENV{IDF_PATH}/tools/catch - REQUIRES esp_rom) + INCLUDE_DIRS "." + REQUIRES esp_rom + WHOLE_ARCHIVE) + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/esp_rom/test_apps/linux_rom_apis/main/idf_component.yml b/components/esp_rom/test_apps/linux_rom_apis/main/idf_component.yml new file mode 100644 index 00000000000..f7982136b97 --- /dev/null +++ b/components/esp_rom/test_apps/linux_rom_apis/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/catch2: "^3.4.0" diff --git a/components/esp_rom/test_apps/linux_rom_apis/main/rom_test.cpp b/components/esp_rom/test_apps/linux_rom_apis/main/rom_test.cpp index 664f8a65483..96654d84438 100644 --- a/components/esp_rom/test_apps/linux_rom_apis/main/rom_test.cpp +++ b/components/esp_rom/test_apps/linux_rom_apis/main/rom_test.cpp @@ -15,7 +15,6 @@ Note that the printf function is roughly tested in the log host test. */ -#define CATCH_CONFIG_MAIN #include #include #include @@ -24,12 +23,10 @@ #include "esp_rom_crc.h" #include "esp_rom_md5.h" -#include "catch.hpp" +#include using namespace std; -static const char *TEST_TAG = "test"; - // ESP_LOG_EARLY functions are tested in the log host tests and also test rom printf. TEST_CASE("esp_rom printf returns correct char num") { diff --git a/components/esp_rom/test_apps/rom_tests/README.md b/components/esp_rom/test_apps/rom_tests/README.md index a8b7833fa30..bf47d80ec64 100644 --- a/components/esp_rom/test_apps/rom_tests/README.md +++ b/components/esp_rom/test_apps/rom_tests/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_rom/test_apps/rom_tests/main/test_libgcc.c b/components/esp_rom/test_apps/rom_tests/main/test_libgcc.c index 438b1027abe..c0a09267894 100644 --- a/components/esp_rom/test_apps/rom_tests/main/test_libgcc.c +++ b/components/esp_rom/test_apps/rom_tests/main/test_libgcc.c @@ -5,6 +5,7 @@ */ #include #include "unity.h" +#include "esp_rom_caps.h" TEST_CASE("libgcc math functions", "[rom][libgcc]") { @@ -14,8 +15,6 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__absvsi2(-1) == 1); extern double __adddf3(double x, double y); TEST_ASSERT(__adddf3(1.0, 4.0) == 5.0); - extern float __addsf3(float x, float y); - TEST_ASSERT(__addsf3(1.0f, 4.0f) == 5.0f); extern int64_t __addvdi3(int64_t x, int64_t y); TEST_ASSERT(__addvdi3(1L, 4L) == 5L); extern int __addvsi3(int x, int y); @@ -56,8 +55,7 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__divsi3(16, 2) == 8); extern int __eqdf2(double x, double y); TEST_ASSERT(__eqdf2(4.0, 4.0) == 0); - extern int __eqsf2(float x, float y); - TEST_ASSERT(__eqsf2(4.0f, 4.0f) == 0); + extern double __extendsfdf2(float x); TEST_ASSERT(__extendsfdf2(4.0f) == 4.0); extern int __ffsdi2(uint64_t x); @@ -70,8 +68,6 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__fixdfsi(4.0) == 4); extern int64_t __fixsfdi(float x); TEST_ASSERT(__fixsfdi(4.0f) == 4LL); - extern int __fixsfsi(float x); - TEST_ASSERT(__fixsfsi(4.0f) == 4); extern unsigned __fixunsdfsi(double x); TEST_ASSERT(__fixunsdfsi(16.0) == 16); extern uint64_t __fixunssfdi(float x); @@ -84,34 +80,24 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__floatdisf(-1LL) == -1.0f); extern double __floatsidf(int x); TEST_ASSERT(__floatsidf(-1) == -1.0); - extern float __floatsisf(int x); - TEST_ASSERT(__floatsisf(-1) == -1.0f); + extern double __floatundidf(uint64_t x); TEST_ASSERT(__floatundidf(16) == 16.0); extern float __floatundisf(uint64_t x); TEST_ASSERT(__floatundisf(16) == 16.0f); extern double __floatunsidf(unsigned x); TEST_ASSERT(__floatunsidf(16) == 16.0); - extern float __floatunsisf(unsigned x); - TEST_ASSERT(__floatunsisf(16) == 16.0f); extern int __gedf2(double x, double y); - TEST_ASSERT(__gedf2(2.0, 0.0) >= 0); - extern int __gesf2(float x, float y); - TEST_ASSERT(__gesf2(2.0f, 0.0f) >= 0); extern int __gtdf2(double x, double y); TEST_ASSERT(__gtdf2(2.0, 0.0) >= 0); - extern int __gtsf2(float x, float y); - TEST_ASSERT(__gtsf2(2.0f, 0.0f) >= 0); extern int __ledf2(double x, double y); TEST_ASSERT(__ledf2(0.0, 2.0) <= 0); - extern int __lesf2(float x, float y); - TEST_ASSERT(__lesf2(0.0f, 2.0f) <= 0); + extern int64_t __lshrdi3(int64_t x, int y); TEST_ASSERT(__lshrdi3(0x8000000000000000LL, 1) == 0x4000000000000000LL); extern int __ltdf2(double x, double y); TEST_ASSERT(__ltdf2(0.0, 2.0) < 0); - extern int __ltsf2(float x, float y); - TEST_ASSERT(__ltsf2(0.0f, 2.0f) < 0); + extern int64_t __moddi3(int64_t x, int64_t y); TEST_ASSERT(__moddi3(15, 2) == 1); extern int __modsi3(int x, int y); @@ -124,8 +110,7 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__muldi3(2, 8) == 16); extern complex float __mulsc3(float a, float b, float c, float d); TEST_ASSERT(__mulsc3(1.0f, 0.0f, 0.0f, -1.0f) == -I); - extern float __mulsf3(float a, float b); - TEST_ASSERT(__mulsf3(2.0f, 8.0f) == 16.0f); + extern int __mulsi3(int x, int y); TEST_ASSERT(__mulsi3(2, 8) == 16); extern int __mulvdi3(int64_t x, int64_t y); @@ -138,14 +123,12 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__negdf2(1.0) == -1.0); extern int64_t __negdi2(int64_t x); TEST_ASSERT(__negdi2(-1LL) == 1); - extern float __negsf2(float x); - TEST_ASSERT(__negsf2(-1.0f) == 1.0f); + extern int64_t __negvdi2(int64_t x); TEST_ASSERT(__negvdi2(-1LL) == 1); extern int __negvsi2(int x); TEST_ASSERT(__negvsi2(-1) == 1); - extern int __nesf2(float x, float y); - TEST_ASSERT(__nesf2(2.0, 0.0) != 0); + extern int __paritysi2(unsigned x); TEST_ASSERT(__paritysi2(0x10101010) == 0); extern int __popcountdi2(uint64_t); @@ -158,8 +141,7 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__powisf2(2.0f, 2) == 4.0f); extern double __subdf3(double x, double y); TEST_ASSERT(__subdf3(2.0, 1.0) == 1.0); - extern float __subsf3(float x, float y); - TEST_ASSERT(__subsf3(5.0f, 4.0f) == 1.0f); + extern int64_t __subvdi3(int64_t x, int64_t y); TEST_ASSERT(__subvdi3(-1LL, -1LL) == 0); extern int __subvsi3(int x, int y); @@ -186,6 +168,36 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") #endif extern int __unorddf2(double x, double y); TEST_ASSERT(__unorddf2(1.0, 2.0) == 0); + +#if ESP_ROM_HAS_SW_FLOAT + extern float __addsf3(float x, float y); + TEST_ASSERT(__addsf3(1.0f, 4.0f) == 5.0f); + extern int __eqsf2(float x, float y); + TEST_ASSERT(__eqsf2(4.0f, 4.0f) == 0); + extern int __fixsfsi(float x); + TEST_ASSERT(__fixsfsi(4.0f) == 4); + extern float __floatsisf(int x); + TEST_ASSERT(__floatsisf(-1) == -1.0f); + extern float __floatunsisf(unsigned x); + TEST_ASSERT(__floatunsisf(16) == 16.0f); + TEST_ASSERT(__gedf2(2.0, 0.0) >= 0); + extern int __gesf2(float x, float y); + TEST_ASSERT(__gesf2(2.0f, 0.0f) >= 0); + extern int __gtsf2(float x, float y); + TEST_ASSERT(__gtsf2(2.0f, 0.0f) >= 0); + extern int __lesf2(float x, float y); + TEST_ASSERT(__lesf2(0.0f, 2.0f) <= 0); + extern int __ltsf2(float x, float y); + TEST_ASSERT(__ltsf2(0.0f, 2.0f) < 0); + extern float __mulsf3(float a, float b); + TEST_ASSERT(__mulsf3(2.0f, 8.0f) == 16.0f); + extern float __negsf2(float x); + TEST_ASSERT(__negsf2(-1.0f) == 1.0f); + extern int __nesf2(float x, float y); + TEST_ASSERT(__nesf2(2.0, 0.0) != 0); + extern float __subsf3(float x, float y); + TEST_ASSERT(__subsf3(5.0f, 4.0f) == 1.0f); extern int __unordsf2(float x, float y); TEST_ASSERT(__unordsf2(2.0f, 1.0f) == 0); +#endif //ESP_ROM_HAS_SW_FLOAT } diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index c63a27df0b8..53bab1f35a3 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -13,7 +13,11 @@ endif() set(srcs "esp_err.c") if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_CPU_CLK_SETTING) - list(APPEND srcs "fpga_overrides.c") + list(APPEND srcs "fpga_overrides_clk.c") +endif() + +if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING) + list(APPEND srcs "fpga_overrides_rng.c") endif() if(BOOTLOADER_BUILD) @@ -29,6 +33,7 @@ else() "panic.c" "esp_system.c" "startup.c" + "startup_funcs.c" "system_time.c" "stack_check.c" "ubsan.c" @@ -63,11 +68,9 @@ else() # [refactor-todo] requirements due to init code, # should be removable once using component init functions # link-time registration is used. - # [refactor-todo] requires "driver" for headers: - # - spi_common_internal.h # [refactor-todo] esp_partition required for virtual efuse # init code. Move to esp_efuse component. - pthread bootloader_support efuse driver esp_partition + pthread bootloader_support efuse esp_partition esp_pm LDFRAGMENTS "linker.lf" "app.lf") add_subdirectory(port) @@ -92,13 +95,19 @@ endif() if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_CPU_CLK_SETTING) # Forces the linker to include fpga stubs from this component - target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides") + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides_clk") +endif() + +if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING) + # Forces the linker to include fpga stubs from this component + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides_rng") endif() # Force linking UBSAN hooks. If UBSAN is not enabled, the hooks will ultimately be removed # due to -ffunction-sections -Wl,--gc-sections options. target_link_libraries(${COMPONENT_LIB} INTERFACE "-u __ubsan_include") +target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_system_include_startup_funcs") # [refactor-todo] requirements due to init code, should be removable # once link-time registration of component init functions is used. diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index e202c51fbb9..e0b42653d22 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -92,7 +92,7 @@ menu "ESP System Settings" config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK bool - default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE + default y if IDF_TARGET_ESP32 && ESP_SYSTEM_SINGLE_CORE_MODE default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 @@ -275,13 +275,9 @@ menu "ESP System Settings" bool default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM - config ESP_CONSOLE_MULTIPLE_UART - bool - default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 - choice ESP_CONSOLE_UART_NUM prompt "UART peripheral to use for console output (0-1)" - depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART + depends on ESP_CONSOLE_UART_CUSTOM default ESP_CONSOLE_UART_CUSTOM_NUM_0 help This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. @@ -301,7 +297,6 @@ menu "ESP System Settings" config ESP_CONSOLE_UART_NUM int default 0 if ESP_CONSOLE_UART_DEFAULT - default 0 if !ESP_CONSOLE_MULTIPLE_UART default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 default -1 if !ESP_CONSOLE_UART @@ -309,7 +304,7 @@ menu "ESP System Settings" config ESP_CONSOLE_UART_TX_GPIO int "UART TX on GPIO#" depends on ESP_CONSOLE_UART_CUSTOM - range 0 46 + range 0 SOC_GPIO_OUT_RANGE_MAX default 1 if IDF_TARGET_ESP32 default 20 if IDF_TARGET_ESP32C2 default 21 if IDF_TARGET_ESP32C3 @@ -327,7 +322,7 @@ menu "ESP System Settings" config ESP_CONSOLE_UART_RX_GPIO int "UART RX on GPIO#" depends on ESP_CONSOLE_UART_CUSTOM - range 0 46 + range 0 SOC_GPIO_IN_RANGE_MAX default 3 if IDF_TARGET_ESP32 default 19 if IDF_TARGET_ESP32C2 default 20 if IDF_TARGET_ESP32C3 @@ -595,7 +590,7 @@ menu "IPC (Inter-Processor Call)" config ESP_IPC_ISR_ENABLE bool - default y if !FREERTOS_UNICORE + default y if !ESP_SYSTEM_SINGLE_CORE_MODE help The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the context of a High Priority Interrupt. The IPC ISR feature is intended for low latency execution of simple diff --git a/components/esp_system/check_system_init_priorities.py b/components/esp_system/check_system_init_priorities.py index 4bb1741c080..91afafc36d5 100644 --- a/components/esp_system/check_system_init_priorities.py +++ b/components/esp_system/check_system_init_priorities.py @@ -1,6 +1,6 @@ #!/usr/bin/env python # -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # # This file is used to check the order of execution of ESP_SYSTEM_INIT_FN functions. @@ -18,19 +18,20 @@ ESP_SYSTEM_INIT_FN_STR = r'ESP_SYSTEM_INIT_FN' ESP_SYSTEM_INIT_FN_REGEX_SIMPLE = re.compile(r'ESP_SYSTEM_INIT_FN') -ESP_SYSTEM_INIT_FN_REGEX = re.compile(r'ESP_SYSTEM_INIT_FN\(([a-zA-Z0-9_]+)\s*,\s*([a-zA-Z\ _0-9\(\)|]+)\s*,\s*([0-9]+)\)') +ESP_SYSTEM_INIT_FN_REGEX = re.compile(r'ESP_SYSTEM_INIT_FN\(([a-zA-Z0-9_]+)\s*,\s*([a-zA-Z\ _0-9\(\)|]+)\s*,\s*([a-zA-Z\ _0-9\(\)|]+)\s*,\s*([0-9]+)\)') STARTUP_ENTRIES_FILE = 'components/esp_system/system_init_fn.txt' class StartupEntry: - def __init__(self, filename: str, func: str, affinity: str, priority: int) -> None: + def __init__(self, filename: str, func: str, stage: str, affinity: str, priority: int) -> None: self.filename = filename self.func = func + self.stage = stage self.affinity = affinity self.priority = priority def __str__(self) -> str: - return f'{self.priority:3d}: {self.func} in {self.filename} on {self.affinity}' + return f'{self.stage}: {self.priority:3d}: {self.func} in {self.filename} on {self.affinity}' def main() -> None: @@ -65,15 +66,20 @@ def main() -> None: entry = StartupEntry( filename=os.path.relpath(filename, idf_path), func=match[0], - affinity=match[1], - priority=int(match[2]) + stage=match[1], + affinity=match[2], + priority=int(match[3]) ) startup_entries.append(entry) # - # 2. Sort the ESP_SYSTEM_INIT_FN functions in C source files by priority + # 2. Sort the ESP_SYSTEM_INIT_FN functions in C source files by stage and then priority # - startup_entries = list(sorted(startup_entries, key=lambda e: e.priority)) + def sort_key(entry: StartupEntry) -> typing.Tuple[str, int]: + # luckily 'core' and 'secondary' are in alphabetical order, so we can return the string + return (entry.stage, entry.priority) + + startup_entries = list(sorted(startup_entries, key=sort_key)) startup_entries_lines = [str(entry) for entry in startup_entries] # diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides_clk.c similarity index 78% rename from components/esp_system/fpga_overrides.c rename to components/esp_system/fpga_overrides_clk.c index 210517bb573..72c7aa5ff23 100644 --- a/components/esp_system/fpga_overrides.c +++ b/components/esp_system/fpga_overrides_clk.c @@ -31,13 +31,12 @@ #include "esp_log.h" #include "esp_rom_sys.h" #include "esp_rom_uart.h" -#include "esp_attr.h" -static const char *TAG = "fpga"; +static const char *TAG = "fpga_clk"; static void s_warn(void) { - ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work"); + ESP_EARLY_LOGE(TAG, "Project configuration is for internal FPGA use, clock functions will not work"); } void bootloader_clock_configure(void) @@ -58,15 +57,6 @@ void bootloader_clock_configure(void) REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16)); } -/* Placed in IRAM since test_apps expects it to be */ -void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length) -{ - uint8_t *buffer_bytes = (uint8_t *)buffer; - for (int i = 0; i < length; i++) { - buffer_bytes[i] = 0x5A; - } -} - void esp_clk_init(void) { s_warn(); @@ -83,6 +73,6 @@ void esp_perip_clk_init(void) * @brief No-op function, used to force linking this file * */ -void esp_common_include_fpga_overrides(void) +void esp_common_include_fpga_overrides_clk(void) { } diff --git a/components/esp_system/fpga_overrides_rng.c b/components/esp_system/fpga_overrides_rng.c new file mode 100644 index 00000000000..10014e5cecf --- /dev/null +++ b/components/esp_system/fpga_overrides_rng.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "esp_log.h" +#include "esp_attr.h" + +static const char *TAG = "fpga_rng"; + +/* Placed in IRAM since test_apps expects it to be */ +void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length) +{ + ESP_EARLY_LOGE(TAG, "Project configuration is for internal FPGA use, RNG will not work"); + + uint8_t *buffer_bytes = (uint8_t *)buffer; + for (int i = 0; i < length; i++) { + buffer_bytes[i] = 0x5A; + } +} + +/** + * @brief No-op function, used to force linking this file + * + */ +void esp_common_include_fpga_overrides_rng(void) +{ +} diff --git a/components/esp_system/hw_stack_guard.c b/components/esp_system/hw_stack_guard.c index 1f5eee429c5..6789093f1a8 100644 --- a/components/esp_system/hw_stack_guard.c +++ b/components/esp_system/hw_stack_guard.c @@ -11,7 +11,7 @@ #include "esp_rom_sys.h" #include "esp_cpu.h" -ESP_SYSTEM_INIT_FN(esp_hw_stack_guard_init, ESP_SYSTEM_INIT_ALL_CORES, 101) +ESP_SYSTEM_INIT_FN(esp_hw_stack_guard_init, SECONDARY, ESP_SYSTEM_INIT_ALL_CORES, 101) { uint32_t core_id = esp_cpu_get_core_id(); diff --git a/components/esp_system/include/esp_debug_helpers.h b/components/esp_system/include/esp_debug_helpers.h index 02b7bc6a54a..116fec70426 100644 --- a/components/esp_system/include/esp_debug_helpers.h +++ b/components/esp_system/include/esp_debug_helpers.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,8 +13,9 @@ extern "C" { #ifndef __ASSEMBLER__ #include -#include "esp_err.h" +#include "sdkconfig.h" #include "soc/soc.h" // [refactor-todo] IDF-2297 +#include "esp_err.h" #include "esp_cpu.h" /* @@ -114,6 +115,20 @@ esp_err_t esp_backtrace_print_from_frame(int depth, const esp_backtrace_frame_t* */ esp_err_t esp_backtrace_print(int depth); +/** + * @brief Print the backtrace of all tasks + * + * @param depth The maximum number of stack frames to print (must be > 0) + * + * @note Users must ensure that no tasks are created or deleted while this function is running. + * @note This function must be called from a task context. + * + * @return + * - ESP_OK All backtraces successfully printed to completion or to depth limit + * - ESP_FAIL One or more backtraces are corrupt + */ +esp_err_t esp_backtrace_print_all_tasks(int depth); + /** * @brief Set a watchpoint to break/panic when a certain memory range is accessed. * Superseded by esp_cpu_set_watchpoint in esp_cpu.h. diff --git a/components/esp_system/include/esp_private/panic_internal.h b/components/esp_system/include/esp_private/panic_internal.h index 9d35c7524dd..203643d0691 100644 --- a/components/esp_system/include/esp_private/panic_internal.h +++ b/components/esp_system/include/esp_private/panic_internal.h @@ -75,6 +75,8 @@ void panic_arch_fill_info(void *frame, panic_info_t *info); void panic_soc_fill_info(void *frame, panic_info_t *info); +bool panic_soc_check_pseudo_cause(void *f, panic_info_t *info); + void panic_print_registers(const void *frame, int core); void panic_print_backtrace(const void *frame, int core); diff --git a/components/esp_system/include/esp_private/startup_internal.h b/components/esp_system/include/esp_private/startup_internal.h index 9886da8ca11..a1ca5c927c9 100644 --- a/components/esp_system/include/esp_private/startup_internal.h +++ b/components/esp_system/include/esp_private/startup_internal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,13 +43,18 @@ void startup_resume_other_cores(void); */ typedef struct { esp_err_t (*fn)(void); /*!< Pointer to the startup function */ - uint32_t cores; /*!< Bit map of cores where the function has to be called */ + uint16_t cores; /*!< Bit mask of cores where the function has to be called */ + uint16_t stage; /*!< Init stage number (0 or 1) */ } esp_system_init_fn_t; +#define ESP_SYSTEM_INIT_STAGE_CORE 0 +#define ESP_SYSTEM_INIT_STAGE_SECONDARY 1 + /** * @brief Define a system initialization function which will be executed on the specified cores * * @param f function name (identifier) + * @param stage_ init stage name (CORE or SECONDARY) * @param c bit mask of cores to execute the function on (ex. if BIT0 is set, the function * will be executed on CPU 0, if BIT1 is set - on CPU 1, and so on) * @param priority integer, priority of the initialization function. Higher values mean that @@ -65,10 +70,14 @@ typedef struct { * It is, on the other hand, a good practice to make sure the initialization function does get * discarded if the related feature is not used. */ -#define ESP_SYSTEM_INIT_FN(f, c, priority, ...) \ +#define ESP_SYSTEM_INIT_FN(f, stage_, c, priority, ...) \ static esp_err_t __VA_ARGS__ __esp_system_init_fn_##f(void); \ static __attribute__((used)) _SECTION_ATTR_IMPL(".esp_system_init_fn", priority) \ - esp_system_init_fn_t esp_system_init_fn_##f = { .fn = ( __esp_system_init_fn_##f), .cores = (c) }; \ + esp_system_init_fn_t esp_system_init_fn_##f = { \ + .fn = ( __esp_system_init_fn_##f), \ + .cores = (c), \ + .stage = ESP_SYSTEM_INIT_STAGE_##stage_ \ + }; \ static esp_err_t __esp_system_init_fn_##f(void) #ifdef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE diff --git a/components/esp_system/include/esp_task_wdt.h b/components/esp_system/include/esp_task_wdt.h index cf7e8dacfba..58b6482a408 100644 --- a/components/esp_system/include/esp_task_wdt.h +++ b/components/esp_system/include/esp_task_wdt.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -179,6 +179,31 @@ esp_err_t esp_task_wdt_status(TaskHandle_t task_handle); */ void __attribute__((weak)) esp_task_wdt_isr_user_handler(void); +typedef void (*task_wdt_msg_handler)(void *opaque, const char *msg); + +/** + * @brief Prints or retrieves information about tasks/users that triggered the Task Watchdog Timeout. + * + * This function provides various operations to handle tasks/users that did not reset the Task Watchdog in time. + * It can print detailed information about these tasks/users, such as their names, associated CPUs, and whether they have been reset. + * Additionally, it can retrieve the total length of the printed information or the CPU affinity of the failing tasks. + * + * @param[in] msg_handler Optional message handler function that will be called for each printed line. + * @param[in] opaque Optional pointer to opaque data that will be passed to the message handler function. + * @param[out] cpus_fail Optional pointer to an integer where the CPU affinity of the failing tasks will be stored. + * + * @return + * - ESP_OK: The function executed successfully. + * - ESP_FAIL: No triggered tasks were found, and thus no information was printed or retrieved. + * + * @note + * - If `msg_handler` is not provided, the information will be printed to console using ESP_EARLY_LOGE. + * - If `msg_handler` is provided, the function will send the printed information to the provided message handler function. + * - If `cpus_fail` is provided, the function will store the CPU affinity of the failing tasks in the provided integer. + * - During the execution of this function, logging is allowed in critical sections, as TWDT timeouts are considered fatal errors. + */ +esp_err_t esp_task_wdt_print_triggered_tasks(task_wdt_msg_handler msg_handler, void *opaque, int *cpus_fail); + #ifdef __cplusplus } #endif diff --git a/components/esp_system/ld/esp32c5/memory.ld.in b/components/esp_system/ld/esp32c5/memory.ld.in new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_system/linker.lf b/components/esp_system/linker.lf index e30a7fccecc..f512f550a99 100644 --- a/components/esp_system/linker.lf +++ b/components/esp_system/linker.lf @@ -5,7 +5,7 @@ entries: panic (noflash) panic_handler (noflash) panic_arch (noflash) - cache_err_int:esp_cache_err_get_cpuid (noflash) + cache_err_int (noflash) reset_reason:esp_reset_reason_get_hint (noflash) if ESP_SYSTEM_HW_STACK_GUARD = y: hw_stack_guard:esp_hw_stack_guard_get_bounds (noflash) diff --git a/components/esp_system/port/arch/riscv/debug_helpers.c b/components/esp_system/port/arch/riscv/debug_helpers.c index 9fef778c79c..9ebeeb6d28a 100644 --- a/components/esp_system/port/arch/riscv/debug_helpers.c +++ b/components/esp_system/port/arch/riscv/debug_helpers.c @@ -39,7 +39,7 @@ esp_err_t IRAM_ATTR esp_backtrace_print(int depth) const int current_core = xPortGetCoreID(); TaskSnapshot_t snapshot = { 0 }; - BaseType_t ret = vTaskGetSnapshot(xTaskGetCurrentTaskHandleForCPU(current_core), &snapshot); + BaseType_t ret = vTaskGetSnapshot(xTaskGetCurrentTaskHandleForCore(current_core), &snapshot); if (ret != pdTRUE) { return ESP_ERR_NOT_FOUND; diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c index c24c2f712ec..a4f64dbdc7f 100644 --- a/components/esp_system/port/arch/riscv/panic_arch.c +++ b/components/esp_system/port/arch/riscv/panic_arch.c @@ -41,124 +41,20 @@ #define DIM(array) (sizeof(array)/sizeof(*array)) -/** - * Structure used to define a flag/bit to test in case of cache error. - * The message describes the cause of the error when the bit is set in - * a given status register. - */ -typedef struct { - const uint32_t bit; - const char *msg; -} register_bit_t; - -/** - * Function to check each bits defined in the array reg_bits in the given - * status register. The first bit from the array to be set in the status - * register will have its associated message printed. This function returns - * true. If not bit was set in the register, it returns false. - * The order of the bits in the array is important as only the first bit to - * be set in the register will have its associated message printed. - */ -static inline bool test_and_print_register_bits(const uint32_t status, - const register_bit_t *reg_bits, - const uint32_t size) -{ - /* Browse the flag/bit array and test each one with the given status - * register. */ - for (int i = 0; i < size; i++) { - const uint32_t bit = reg_bits[i].bit; - if ((status & bit) == bit) { - /* Reason of the panic found, print the reason. */ - panic_print_str(reg_bits[i].msg); - panic_print_str("\r\n"); - - return true; - } - } - - /* Panic cause not found, no message was printed. */ - return false; -} - /** * Function called when a cache error occurs. It prints details such as the * explanation of why the panic occured. */ static inline void print_cache_err_details(const void *frame) { -#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // ESP32P4-TODO, ESP32C6-TODO, ESP32H2-TODO: IDF-5657 - /* Define the array that contains the status (bits) to test on the register - * EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. each bit is accompanied by a small - * message. - * The messages have been pulled from the header file where the status bit - * are defined. */ - const register_bit_t core0_acs_bits[] = { - { - .bit = EXTMEM_CORE0_DBUS_WR_ICACHE_ST, - .msg = "dbus tried to write cache" - }, - { - .bit = EXTMEM_CORE0_DBUS_REJECT_ST, - .msg = "dbus authentication failed" - }, - { - .bit = EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST, - .msg = "access to cache while dbus or cache is disabled" - }, - { - .bit = EXTMEM_CORE0_IBUS_REJECT_ST, - .msg = "ibus authentication failed" - }, - { - .bit = EXTMEM_CORE0_IBUS_WR_ICACHE_ST, - .msg = "ibus tried to write cache" - }, - { - .bit = EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST, - .msg = "access to cache while ibus or cache is disabled" - }, - }; - - /* Same goes for the register EXTMEM_CACHE_ILG_INT_ST_REG and its bits. */ - const register_bit_t cache_ilg_bits[] = { - { - .bit = EXTMEM_MMU_ENTRY_FAULT_ST, - .msg = "MMU entry fault" - }, - { - .bit = EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST, - .msg = "preload configurations fault" - }, - { - .bit = EXTMEM_ICACHE_SYNC_OP_FAULT_ST, - .msg = "sync configurations fault" - }, - }; - - /* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status - * register is not equal to 0 when a cache access error occured. */ - const uint32_t core0_status = REG_READ(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG); - - /* If the panic is due to a cache access error, one of the bit of the - * register is set. Thus, this function will return true. */ - bool handled = test_and_print_register_bits(core0_status, core0_acs_bits, DIM(core0_acs_bits)); - - /* If the panic was due to a cache illegal error, the previous call returned false and this - * EXTMEM_CACHE_ILG_INT_ST_REG register should not me equal to 0. - * Check each bit of it and print the message associated if found. */ - if (!handled) { - const uint32_t cache_ilg_status = REG_READ(EXTMEM_CACHE_ILG_INT_ST_REG); - handled = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits)); - - /* If the error was not found, print the both registers value */ - if (!handled) { - panic_print_str("EXTMEM_CORE0_ACS_CACHE_INT_ST_REG = 0x"); - panic_print_hex(core0_status); - panic_print_str("\r\nEXTMEM_CACHE_ILG_INT_ST_REG = 0x"); - panic_print_hex(cache_ilg_status); - panic_print_str("\r\n"); - } +#if !CONFIG_IDF_TARGET_ESP32P4 + const char* cache_err_msg = esp_cache_err_panic_string(); + if (cache_err_msg) { + panic_print_str(cache_err_msg); + } else { + panic_print_str("Cache error active, but failed to find a corresponding error message"); } + panic_print_str("\r\n"); #endif } @@ -167,7 +63,7 @@ static inline void print_assist_debug_details(const void *frame) { uint32_t core_id = esp_cpu_get_core_id(); uint32_t sp_min, sp_max; - const char *task_name = pcTaskGetName(xTaskGetCurrentTaskHandleForCPU(core_id)); + const char *task_name = pcTaskGetName(xTaskGetCurrentTaskHandleForCore(core_id)); esp_hw_stack_guard_get_bounds(&sp_min, &sp_max); panic_print_str("\r\n"); @@ -294,6 +190,27 @@ void panic_print_registers(const void *f, int core) panic_print_register_array(desc, f, DIM(desc)); } +/** + * This function will be called before the SoC-level panic is handled, + * allowing us to check and override the exception cause for certain + * pseudo-causes that do not have their own trigger + */ +bool panic_soc_check_pseudo_cause(void *f, panic_info_t *info) +{ + RvExcFrame *frame = (RvExcFrame *) f; + bool pseudo_cause = false; + + /* Cache errors when reading instructions will result in an illegal instructions, + before any cache error interrupts trigger. We override the exception cause if + any cache errors are active to more accurately report the actual reason */ + if(esp_cache_err_has_active_err() && (frame->mcause == MCAUSE_ILLEGAL_INSTRUCTION) ) { + pseudo_cause = true; + frame->mcause = ETS_CACHEERR_INUM; + } + + return pseudo_cause; +} + /** * This function will be called when a SoC-level panic occurs. * SoC-level panics include cache errors and watchdog interrupts. diff --git a/components/esp_system/port/arch/xtensa/debug_helpers.c b/components/esp_system/port/arch/xtensa/debug_helpers.c index 9cb55d2eff8..f2f89441166 100644 --- a/components/esp_system/port/arch/xtensa/debug_helpers.c +++ b/components/esp_system/port/arch/xtensa/debug_helpers.c @@ -1,25 +1,28 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include - #include "sdkconfig.h" +#include +#include +#include "soc/soc_memory_layout.h" #include "esp_types.h" #include "esp_attr.h" #include "esp_err.h" +#include "esp_check.h" +#include "esp_ipc.h" #include "esp_debug_helpers.h" -#include "soc/soc_memory_layout.h" #include "esp_cpu_utils.h" #include "esp_private/panic_internal.h" - -#include "xtensa/xtensa_context.h" - -#include "sdkconfig.h" - +#include "esp_private/freertos_debug.h" #include "esp_rom_sys.h" +#include "xtensa_context.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +const char *DEBUG_HELPER_TAG = "DBG HLPR"; bool IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame) { @@ -101,3 +104,149 @@ esp_err_t IRAM_ATTR esp_backtrace_print(int depth) esp_backtrace_get_start(&(start.pc), &(start.sp), &(start.next_pc)); return esp_backtrace_print_from_frame(depth, &start, false); } + +typedef struct { +#if !CONFIG_FREERTOS_UNICORE + volatile bool start_tracing; + volatile bool finished_tracing; +#endif // !CONFIG_FREERTOS_UNICORE + struct { + TaskHandle_t task_hdl; + uint32_t starting_pc; + uint32_t starting_sp; + uint32_t next_pc; + } cur_tasks[configNUMBER_OF_CORES]; +} cur_task_backtrace_ctrl_t; + +#if !CONFIG_FREERTOS_UNICORE +static void backtrace_other_cores_ipc_func(void *arg) +{ + cur_task_backtrace_ctrl_t *ctrl = (cur_task_backtrace_ctrl_t *)arg; + + // Suspend the scheduler to prevent task switching + vTaskSuspendAll(); + /* + Initialize backtracing for this core: + + - Flush current core's register windows back onto current task's stack using esp_backtrace_get_start() + - Get starting frame for backtracing (starting frame is the caller of this function) using esp_backtrace_get_start() + - Save the starting frame details into the control block + */ + BaseType_t core_id = xPortGetCoreID(); // Get core ID now that task switching is disabled + ctrl->cur_tasks[core_id].task_hdl = xTaskGetCurrentTaskHandle(); + esp_backtrace_get_start(&ctrl->cur_tasks[core_id].starting_pc, + &ctrl->cur_tasks[core_id].starting_sp, + &ctrl->cur_tasks[core_id].next_pc); + + // Indicate to backtracing core that this core is ready for backtracing + ctrl->start_tracing = true; + // Wait for backtracing core to indicate completion + while (!ctrl->finished_tracing) { + ; + } + // Resume the scheduler to allow task switching again + xTaskResumeAll(); +} +#endif // !CONFIG_FREERTOS_UNICORE + +esp_err_t IRAM_ATTR esp_backtrace_print_all_tasks(int depth) +{ + esp_err_t ret = ESP_OK; + TaskSnapshot_t *task_snapshots; + cur_task_backtrace_ctrl_t ctrl = {0}; + + /* + Allocate array to store task snapshots. Users are responsible for ensuring + tasks don't get created/deleted while backtracing. + */ + const UBaseType_t num_tasks = uxTaskGetNumberOfTasks(); + task_snapshots = calloc(num_tasks, sizeof(TaskSnapshot_t)); + ESP_GOTO_ON_FALSE(task_snapshots, ESP_ERR_NO_MEM, malloc_err, DEBUG_HELPER_TAG, "Task snapshot alloc failed"); + +#if !CONFIG_FREERTOS_UNICORE + // Use IPC call to prepare other core for backtracing + ESP_GOTO_ON_ERROR(esp_ipc_call(!xPortGetCoreID(), backtrace_other_cores_ipc_func, (void *)&ctrl), + ipc_err, + DEBUG_HELPER_TAG, + "IPC call failed"); + // Wait for other core to confirm its ready for backtracing + while (!ctrl.start_tracing) { + ; + } +#endif // !CONFIG_FREERTOS_UNICORE + + // Suspend the scheduler to prevent task switching + vTaskSuspendAll(); + + /* + Initialize backtracing for this core: + + - Flush current core's register windows back onto current task's stack using esp_backtrace_get_start() + - Get starting frame for backtracing (starting frame is the caller of this function) using esp_backtrace_get_start() + - Save the starting frame details into the control block + */ + BaseType_t core_id = xPortGetCoreID(); // Get core ID now that task switching is disabled + ctrl.cur_tasks[core_id].task_hdl = xTaskGetCurrentTaskHandle(); + esp_backtrace_get_start(&ctrl.cur_tasks[core_id].starting_pc, + &ctrl.cur_tasks[core_id].starting_sp, + &ctrl.cur_tasks[core_id].next_pc); + + // Get snapshot of all tasks in the system + const UBaseType_t num_snapshots = MIN(num_tasks, uxTaskGetSnapshotAll(task_snapshots, num_tasks, NULL)); + // Print the backtrace of every task in the system + for (UBaseType_t task_idx = 0; task_idx < num_snapshots; task_idx++) { + bool cur_running = false; + TaskHandle_t task_hdl = (TaskHandle_t) task_snapshots[task_idx].pxTCB; + esp_backtrace_frame_t stk_frame; + + // Check if the task is one of the currently running tasks + for (BaseType_t core_id = 0; core_id < configNUMBER_OF_CORES; core_id++) { + if (task_hdl == ctrl.cur_tasks[core_id].task_hdl) { + cur_running = true; + break; + } + } + // Initialize the starting backtrace frame of the task + if (cur_running) { + /* + Setting the starting backtrace frame for currently running tasks is different. We cannot + use the current frame of each running task as the starting frame (due to the possibility + of the SP changing). Thus, each currently running task will have initialized their callers + as the starting frame for backtracing, which is saved inside the + cur_task_backtrace_ctrl_t block. + */ + stk_frame.pc = ctrl.cur_tasks[core_id].starting_pc; + stk_frame.sp = ctrl.cur_tasks[core_id].starting_sp; + stk_frame.next_pc = ctrl.cur_tasks[core_id].next_pc; + } else { + // Set the starting backtrace frame using the task's saved stack pointer + XtExcFrame* exc_frame = (XtExcFrame*) task_snapshots[task_idx].pxTopOfStack; + stk_frame.pc = exc_frame->pc; + stk_frame.sp = exc_frame->a1; + stk_frame.next_pc = exc_frame->a0; + } + // Print backtrace + char* name = pcTaskGetName(task_hdl); + print_str(name ? name : "No Name" , false); + esp_err_t bt_ret = esp_backtrace_print_from_frame(depth, &stk_frame, false); + if (bt_ret != ESP_OK) { + ret = bt_ret; + } + } + + // Resume the scheduler to allow task switching again + xTaskResumeAll(); +#if !CONFIG_FREERTOS_UNICORE + // Indicate to the other core that backtracing is complete + ctrl.finished_tracing = true; +#endif // !CONFIG_FREERTOS_UNICORE + free(task_snapshots); + return ret; + +#if !CONFIG_FREERTOS_UNICORE +ipc_err: + free(task_snapshots); +#endif // !CONFIG_FREERTOS_UNICORE +malloc_err: + return ret; +} diff --git a/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S b/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S index 20638a68956..2d6d6a5032a 100644 --- a/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S +++ b/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S @@ -7,7 +7,7 @@ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_private/panic_reason.h" #include "sdkconfig.h" #include "soc/soc.h" diff --git a/components/esp_system/port/arch/xtensa/expression_with_stack_asm.S b/components/esp_system/port/arch/xtensa/expression_with_stack_asm.S index 38c0dd998c1..b38e5acaeda 100644 --- a/components/esp_system/port/arch/xtensa/expression_with_stack_asm.S +++ b/components/esp_system/port/arch/xtensa/expression_with_stack_asm.S @@ -1,18 +1,10 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ -#include +#include .extern xtensa_shared_stack .extern xtensa_shared_stack_callback diff --git a/components/esp_system/port/arch/xtensa/panic_arch.c b/components/esp_system/port/arch/xtensa/panic_arch.c index b64752c3a98..2e66fa12802 100644 --- a/components/esp_system/port/arch/xtensa/panic_arch.c +++ b/components/esp_system/port/arch/xtensa/panic_arch.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -146,7 +146,7 @@ static void print_debug_exception_details(const void *f) } #endif - const char *name = pcTaskGetName(xTaskGetCurrentTaskHandleForCPU(core)); + const char *name = pcTaskGetName(xTaskGetCurrentTaskHandleForCore(core)); panic_print_str("Stack canary watchpoint triggered ("); panic_print_str(name); panic_print_str(") "); @@ -392,6 +392,17 @@ void panic_arch_fill_info(void *f, panic_info_t *info) info->addr = ((void *) ((XtExcFrame *) frame)->pc); } +/** + * This function will be called before the SoC-level panic is handled, + * allowing us to check and override the exception cause for certain + * pseudo-causes that do not have their own trigger + */ +bool panic_soc_check_pseudo_cause(void *f, panic_info_t *info) +{ + // Currently only needed on riscv targets + return false; +} + void panic_soc_fill_info(void *f, panic_info_t *info) { // [refactor-todo] this should be in the common port panic_handler.c, once diff --git a/components/esp_system/port/brownout.c b/components/esp_system/port/brownout.c index cb1e8232218..568e1044dde 100644 --- a/components/esp_system/port/brownout.c +++ b/components/esp_system/port/brownout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +11,7 @@ #include "esp_private/system_internal.h" #include "esp_private/rtc_ctrl.h" #include "esp_private/spi_flash_os.h" -#include "esp_rom_sys.h" +#include "esp_log.h" #include "esp_cpu.h" #include "soc/soc.h" #include "soc/rtc_periph.h" @@ -28,6 +28,8 @@ #define BROWNOUT_DET_LVL 0 #endif +static __attribute__((unused)) DRAM_ATTR const char *TAG = "BOD"; + #if CONFIG_ESP_SYSTEM_BROWNOUT_INTR IRAM_ATTR static void rtc_brownout_isr_handler(void *arg) { @@ -51,7 +53,7 @@ IRAM_ATTR static void rtc_brownout_isr_handler(void *arg) } else #endif // CONFIG_SPI_FLASH_BROWNOUT_RESET { - esp_rom_printf("\r\nBrownout detector was triggered\r\n\r\n"); + ESP_DRAM_LOGI(TAG, "Brownout detector was triggered\r\n\r\n"); } esp_restart_noos(); diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 99d6e8b42d8..09fde98aedc 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -66,6 +66,7 @@ #include "soc/hp_sys_clkrst_reg.h" #include "soc/interrupt_core0_reg.h" #include "soc/interrupt_core1_reg.h" +#include "soc/keymng_reg.h" #endif #include "esp_private/esp_mmu_map_private.h" @@ -299,6 +300,11 @@ static void start_other_core(void) if(REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)){ REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL); } + // The following operation makes the Key Manager to use eFuse key for ECDSA and XTS-AES operation by default + // This is to keep the default behavior same as the other chips + // If the Key Manager configuration is already locked then following operation does not have any effect + // TODO-IDF 7925 (Move this under SOC_KEY_MANAGER_SUPPORTED) + REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 3); #endif ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1); diff --git a/components/esp_system/port/esp_system_chip.c b/components/esp_system/port/esp_system_chip.c index 06b029c614b..d211df41228 100644 --- a/components/esp_system/port/esp_system_chip.c +++ b/components/esp_system/port/esp_system_chip.c @@ -51,7 +51,7 @@ void IRAM_ATTR esp_restart_noos_dig(void) // esp_restart_noos_dig() will generates a core reset, which does not reset the // registers of the RTC domain, so the CPU's stall state remains after the reset, // we need to release them here -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE // unstall all other cores int core_id = esp_cpu_get_core_id(); for (uint32_t i = 0; i < SOC_CPU_CORES_NUM; i++) { diff --git a/components/esp_system/port/include/private/esp_private/cache_err_int.h b/components/esp_system/port/include/private/esp_private/cache_err_int.h index 22e1c3ec7ce..c070179a5f4 100644 --- a/components/esp_system/port/include/private/esp_private/cache_err_int.h +++ b/components/esp_system/port/include/private/esp_private/cache_err_int.h @@ -1,15 +1,18 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include + #ifdef __cplusplus extern "C" { #endif + /** * @brief initialize cache invalid access interrupt * @@ -32,6 +35,22 @@ void esp_cache_err_int_init(void); */ int esp_cache_err_get_cpuid(void); + +/** + * @brief Returns a pointer to the cache error message + * + * @return const char* Pointer to the error message + */ +const char *esp_cache_err_panic_string(void); + +/** + * @brief Checks if any cache errors are active + * + * @return true + * @return false + */ +bool esp_cache_err_has_active_err(void); + #ifdef __cplusplus } #endif diff --git a/components/esp_system/port/panic_handler.c b/components/esp_system/port/panic_handler.c index a936a01b4ec..a8ccce4a8c7 100644 --- a/components/esp_system/port/panic_handler.c +++ b/components/esp_system/port/panic_handler.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,9 +104,10 @@ static void frame_to_panic_info(void *frame, panic_info_t *info, bool pseudo_exc info->exception = PANIC_EXCEPTION_FAULT; info->details = NULL; info->reason = "Unknown"; - info->pseudo_excause = pseudo_excause; - if (pseudo_excause) { + info->pseudo_excause = panic_soc_check_pseudo_cause(frame, info) | pseudo_excause; + + if (info->pseudo_excause) { panic_soc_fill_info(frame, info); } else { panic_arch_fill_info(frame, info); diff --git a/components/esp_system/port/soc/esp32/Kconfig.memory b/components/esp_system/port/soc/esp32/Kconfig.memory index 4481fd98d2a..146c461ee1b 100644 --- a/components/esp_system/port/soc/esp32/Kconfig.memory +++ b/components/esp_system/port/soc/esp32/Kconfig.memory @@ -3,11 +3,11 @@ menu "Memory" config ESP32_RTCDATA_IN_FAST_MEM bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment" default n - depends on FREERTOS_UNICORE + depends on ESP_SYSTEM_SINGLE_CORE_MODE help This option allows to place .rtc_data and .rtc_rodata sections into RTC fast memory segment to free the slow memory region for ULP programs. - This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory + This option depends on the CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE option because RTC fast memory can be accessed only by PRO_CPU core. config ESP32_USE_FIXED_STATIC_RAM_SIZE @@ -33,7 +33,7 @@ menu "Memory" config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY bool "Enable IRAM as 8 bit accessible memory" - depends on FREERTOS_UNICORE + depends on ESP_SYSTEM_SINGLE_CORE_MODE help If enabled, application can use IRAM as byte accessible region for storing data (Note: IRAM region cannot be used as task stack) diff --git a/components/esp_system/port/soc/esp32/Kconfig.system b/components/esp_system/port/soc/esp32/Kconfig.system index 484a249fd0e..26cbcddfd7e 100644 --- a/components/esp_system/port/soc/esp32/Kconfig.system +++ b/components/esp_system/port/soc/esp32/Kconfig.system @@ -66,4 +66,4 @@ config ESP32_DISABLE_BASIC_ROM_CONSOLE config ESP32_ECO3_CACHE_LOCK_FIX bool default y - depends on !FREERTOS_UNICORE && SPIRAM + depends on !ESP_SYSTEM_SINGLE_CORE_MODE && SPIRAM diff --git a/components/esp_system/port/soc/esp32/Kconfig.tracemem b/components/esp_system/port/soc/esp32/Kconfig.tracemem index f886d17feca..e0d4452d2e1 100644 --- a/components/esp_system/port/soc/esp32/Kconfig.tracemem +++ b/components/esp_system/port/soc/esp32/Kconfig.tracemem @@ -21,7 +21,7 @@ menu "Trace memory" config ESP32_TRAX_TWOBANKS bool "Reserve memory for tracing both pro as well as app cpu execution" default "n" - depends on ESP32_TRAX && !FREERTOS_UNICORE + depends on ESP32_TRAX && !ESP_SYSTEM_SINGLE_CORE_MODE select ESP32_MEMMAP_TRACEMEM_TWOBANKS help The ESP32 contains a feature which allows you to trace the execution path the processor diff --git a/components/esp_system/port/soc/esp32/clk.c b/components/esp_system/port/soc/esp32/clk.c index 8772a3158bd..3cda5c5bae6 100644 --- a/components/esp_system/port/soc/esp32/clk.c +++ b/components/esp_system/port/soc/esp32/clk.c @@ -12,7 +12,7 @@ #include "bootloader_clock.h" #include "hal/wdt_hal.h" -#include "esp_private/spi_common_internal.h" // [refactor-todo]: for spicommon_periph_in_use +#include "esp_private/spi_share_hw_ctrl.h" #include "esp_log.h" #include "esp_cpu.h" @@ -199,14 +199,14 @@ __attribute__((weak)) void esp_perip_clk_init(void) uint32_t hwcrypto_perip_clk; uint32_t wifi_bt_sdio_clk; -#if CONFIG_FREERTOS_UNICORE +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE soc_reset_reason_t rst_reas[1]; #else soc_reset_reason_t rst_reas[2]; #endif rst_reas[0] = esp_rom_get_reset_reason(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE rst_reas[1] = esp_rom_get_reset_reason(1); #endif @@ -214,7 +214,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) * that have been enabled before reset. */ if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE || (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) #endif ) { diff --git a/components/esp_system/port/soc/esp32/highint_hdl.S b/components/esp_system/port/soc/esp32/highint_hdl.S index a27f0e6bfd9..58097bfe07b 100644 --- a/components/esp_system/port/soc/esp32/highint_hdl.S +++ b/components/esp_system/port/soc/esp32/highint_hdl.S @@ -8,7 +8,7 @@ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "freertos/xtensa_rtos.h" #include "esp_private/panic_reason.h" #include "sdkconfig.h" @@ -163,7 +163,7 @@ _lx_intr_livelock_pro: .align 4 xt_highintx: -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE /* See if we're here for the IPC_ISR interrupt */ rsr a0, INTERRUPT extui a0, a0, ETS_IPC_ISR_INUM, 1 @@ -176,7 +176,7 @@ xt_highintx: movi a0, esp_ipc_isr_handler jx a0 1: -#endif /* not CONFIG_FREERTOS_UNICORE */ +#endif /* not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */ #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c index 96a55e52875..47a0b1ace20 100644 --- a/components/esp_system/port/soc/esp32/system_internal.c +++ b/components/esp_system/port/soc/esp32/system_internal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,7 +22,6 @@ #include "soc/rtc.h" #include "esp_private/rtc_clk.h" #include "hal/wdt_hal.h" -#include "freertos/xtensa_api.h" #include "soc/soc_memory_layout.h" #include "esp_private/cache_err_int.h" @@ -32,9 +31,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Reset wifi/bluetooth/ethernet/sdio (bb/mac) DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, @@ -59,7 +60,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - xt_ints_off(0xFFFFFFFF); + esp_cpu_intr_disable(0xFFFFFFFF); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; diff --git a/components/esp_system/port/soc/esp32c2/cache_err_int.c b/components/esp_system/port/soc/esp32c2/cache_err_int.c index 4f241e021d2..82153533133 100644 --- a/components/esp_system/port/soc/esp32c2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c2/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,119 @@ static const char *TAG = "CACHE_ERR"; + +#define DIM(array) (sizeof(array)/sizeof(*array)) + +/** + * Structure used to define a flag/bit to test in case of cache error. + * The message describes the cause of the error when the bit is set in + * a given status register. + */ +typedef struct { + const uint32_t bit; + const char *msg; +} register_bit_t; + +/* Define the array that contains the status (bits) to test on the register + * EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. each bit is accompanied by a small + * message. + * The messages have been pulled from the header file where the status bit + * are defined. */ +const register_bit_t core0_acs_bits[] = { + { + .bit = EXTMEM_CORE0_DBUS_WR_ICACHE_ST, + .msg = "Dbus tried to write cache" + }, + { + .bit = EXTMEM_CORE0_DBUS_REJECT_ST, + .msg = "Dbus authentication failed" + }, + { + .bit = EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST, + .msg = "Cached memory region accessed while dbus or cache is disabled" + }, + { + .bit = EXTMEM_CORE0_IBUS_REJECT_ST, + .msg = "Ibus authentication failed" + }, + { + .bit = EXTMEM_CORE0_IBUS_WR_ICACHE_ST, + .msg = "Ibus tried to write cache" + }, + { + .bit = EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST, + .msg = "Cached memory region accessed while ibus or cache is disabled" + }, +}; + +/* Same goes for the register EXTMEM_CACHE_ILG_INT_ST_REG and its bits. */ +const register_bit_t cache_ilg_bits[] = { + { + .bit = EXTMEM_MMU_ENTRY_FAULT_ST, + .msg = "MMU entry fault" + }, + { + .bit = EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST, + .msg = "Preload configurations fault" + }, + { + .bit = EXTMEM_ICACHE_SYNC_OP_FAULT_ST, + .msg = "Sync configurations fault" + }, +}; + +/** + * Function to check each bits defined in the array reg_bits in the given + * status register. The first bit from the array to be set in the status + * register will have its associated message printed. This function returns + * true. If not bit was set in the register, it returns false. + * The order of the bits in the array is important as only the first bit to + * be set in the register will have its associated message printed. + */ +static inline const char* test_and_print_register_bits(const uint32_t status, + const register_bit_t *reg_bits, + const uint32_t size) +{ + /* Browse the flag/bit array and test each one with the given status + * register. */ + for (int i = 0; i < size; i++) { + const uint32_t bit = reg_bits[i].bit; + if ((status & bit) == bit) { + /* Reason of the panic found, print the reason. */ + return reg_bits[i].msg; + } + } + + /* Panic cause not found, no message was printed. */ + return NULL; +} + +const char *esp_cache_err_panic_string(void) +{ + /* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status + * register is not equal to 0 when a cache access error occured. */ + const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + + /* If the panic is due to a cache access error, one of the bit of the + * register is set. Thus, this function will return an error string. */ + const char* err_str = test_and_print_register_bits(access_err_status, core0_acs_bits, DIM(core0_acs_bits)); + + /* If the panic was due to a cache illegal error, the previous call returned NULL and this + * EXTMEM_CACHE_ILG_INT_ST_REG register should not be equal to 0. + * Check each bit of it and print the message associated if found. */ + if (err_str == NULL) { + const uint32_t cache_ilg_status = cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK); + err_str = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits)); + } + + return err_str; +} + +bool esp_cache_err_has_active_err(void) +{ + return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK) || cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c2/system_internal.c b/components/esp_system/port/soc/esp32c2/system_internal.c index bff2149fae8..da9094272a6 100644 --- a/components/esp_system/port/soc/esp32c2/system_internal.c +++ b/components/esp_system/port/soc/esp32c2/system_internal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,8 +30,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Reset wifi/bluetooth/ethernet/sdio (bb/mac) diff --git a/components/esp_system/port/soc/esp32c3/cache_err_int.c b/components/esp_system/port/soc/esp32c3/cache_err_int.c index 05b5d6773c8..28f9877cd2e 100644 --- a/components/esp_system/port/soc/esp32c3/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c3/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,118 @@ static const char *TAG = "CACHE_ERR"; +#define DIM(array) (sizeof(array)/sizeof(*array)) + +/** + * Structure used to define a flag/bit to test in case of cache error. + * The message describes the cause of the error when the bit is set in + * a given status register. + */ +typedef struct { + const uint32_t bit; + const char *msg; +} register_bit_t; + +/* Define the array that contains the status (bits) to test on the register + * EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. each bit is accompanied by a small + * message. + * The messages have been pulled from the header file where the status bit + * are defined. */ +const register_bit_t core0_acs_bits[] = { + { + .bit = EXTMEM_CORE0_DBUS_WR_ICACHE_ST, + .msg = "Dbus tried to write cache" + }, + { + .bit = EXTMEM_CORE0_DBUS_REJECT_ST, + .msg = "Dbus authentication failed" + }, + { + .bit = EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST, + .msg = "Cached memory region accessed while dbus or cache is disabled" + }, + { + .bit = EXTMEM_CORE0_IBUS_REJECT_ST, + .msg = "Ibus authentication failed" + }, + { + .bit = EXTMEM_CORE0_IBUS_WR_ICACHE_ST, + .msg = "Ibus tried to write cache" + }, + { + .bit = EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST, + .msg = "Cached memory region accessed while ibus or cache is disabled" + }, +}; + +/* Same goes for the register EXTMEM_CACHE_ILG_INT_ST_REG and its bits. */ +const register_bit_t cache_ilg_bits[] = { + { + .bit = EXTMEM_MMU_ENTRY_FAULT_ST, + .msg = "MMU entry fault" + }, + { + .bit = EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST, + .msg = "Preload configurations fault" + }, + { + .bit = EXTMEM_ICACHE_SYNC_OP_FAULT_ST, + .msg = "Sync configurations fault" + }, +}; + +/** + * Function to check each bits defined in the array reg_bits in the given + * status register. The first bit from the array to be set in the status + * register will have its associated message printed. This function returns + * true. If not bit was set in the register, it returns false. + * The order of the bits in the array is important as only the first bit to + * be set in the register will have its associated message printed. + */ +static inline const char* test_and_print_register_bits(const uint32_t status, + const register_bit_t *reg_bits, + const uint32_t size) +{ + /* Browse the flag/bit array and test each one with the given status + * register. */ + for (int i = 0; i < size; i++) { + const uint32_t bit = reg_bits[i].bit; + if ((status & bit) == bit) { + /* Reason of the panic found, print the reason. */ + return reg_bits[i].msg; + } + } + + /* Panic cause not found, no message was printed. */ + return NULL; +} + +const char *esp_cache_err_panic_string(void) +{ + /* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status + * register is not equal to 0 when a cache access error occured. */ + const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + + /* If the panic is due to a cache access error, one of the bit of the + * register is set. Thus, this function will return an error string. */ + const char* err_str = test_and_print_register_bits(access_err_status, core0_acs_bits, DIM(core0_acs_bits)); + + /* If the panic was due to a cache illegal error, the previous call returned NULL and this + * EXTMEM_CACHE_ILG_INT_ST_REG register should not be equal to 0. + * Check each bit of it and return the message associated if found. */ + if (err_str == NULL) { + const uint32_t cache_ilg_status = cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK); + err_str = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits)); + } + + return err_str; +} + +bool esp_cache_err_has_active_err(void) +{ + return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK) || cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c3/system_internal.c b/components/esp_system/port/soc/esp32c3/system_internal.c index 9372edd56f3..5113bc2b721 100644 --- a/components/esp_system/port/soc/esp32c3/system_internal.c +++ b/components/esp_system/port/soc/esp32c3/system_internal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,8 +31,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Reset wifi/bluetooth/ethernet/sdio (bb/mac) SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, diff --git a/components/esp_system/port/soc/esp32c5/CMakeLists.txt b/components/esp_system/port/soc/esp32c5/CMakeLists.txt new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_system/port/soc/esp32c5/Kconfig.cpu b/components/esp_system/port/soc/esp32c5/Kconfig.cpu new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_system/port/soc/esp32c5/Kconfig.system b/components/esp_system/port/soc/esp32c5/Kconfig.system new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/esp_system/port/soc/esp32c6/cache_err_int.c b/components/esp_system/port/soc/esp32c6/cache_err_int.c index 82cf3895e45..7f4eda7112f 100644 --- a/components/esp_system/port/soc/esp32c6/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c6/cache_err_int.c @@ -20,6 +20,24 @@ static const char *TAG = "CACHE_ERR"; + +const char cache_error_msg[] = "Cache access error"; + +const char *esp_cache_err_panic_string(void) +{ + const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + + /* Return the error string if a cache error is active */ + const char* err_str = access_err_status ? cache_error_msg : NULL; + + return err_str; +} + +bool esp_cache_err_has_active_err(void) +{ + return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 2f309bd27ee..e16b6971148 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -178,8 +178,6 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { - modem_clock_domain_pmu_state_icg_map_init(); - /* During system initialization, the low-power clock source of the modem * (WiFi, BLE or Coexist) follows the configuration of the slow clock source * of the system. If the WiFi, BLE or Coexist module needs a higher diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c index 75e43bf2d18..2829b4de67a 100644 --- a/components/esp_system/port/soc/esp32c6/system_internal.c +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -31,8 +31,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } modem_syscon_ll_reset_all(&MODEM_SYSCON); modem_lpcon_ll_reset_all(&MODEM_LPCON); diff --git a/components/esp_system/port/soc/esp32h2/Kconfig.system b/components/esp_system/port/soc/esp32h2/Kconfig.system index 1bc6be4b1ee..c76dcd88b44 100644 --- a/components/esp_system/port/soc/esp32h2/Kconfig.system +++ b/components/esp_system/port/soc/esp32h2/Kconfig.system @@ -11,7 +11,7 @@ menu "Brownout Detector" choice ESP_BROWNOUT_DET_LVL_SEL prompt "Brownout voltage level" depends on ESP_BROWNOUT_DET - default ESP_BROWNOUT_DET_LVL_SEL_7 + default ESP_BROWNOUT_DET_LVL_SEL_0 help The brownout detector will reset the chip when the supply voltage is approximately below this level. Note that there may be some variation of brownout voltage level @@ -20,21 +20,27 @@ menu "Brownout Detector" #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages #of the brownout threshold levels. config ESP_BROWNOUT_DET_LVL_SEL_7 - bool "2.51V" + bool "2.94V" config ESP_BROWNOUT_DET_LVL_SEL_6 - bool "2.64V" + bool "2.88V" config ESP_BROWNOUT_DET_LVL_SEL_5 - bool "2.76V" + bool "2.83V" config ESP_BROWNOUT_DET_LVL_SEL_4 - bool "2.92V" + bool "2.78V" config ESP_BROWNOUT_DET_LVL_SEL_3 - bool "3.10V" + bool "2.73V" config ESP_BROWNOUT_DET_LVL_SEL_2 - bool "3.27V" + bool "2.67V" + config ESP_BROWNOUT_DET_LVL_SEL_1 + bool "2.62V" + config ESP_BROWNOUT_DET_LVL_SEL_0 + bool "2.57V" endchoice config ESP_BROWNOUT_DET_LVL int + default 0 if ESP_BROWNOUT_DET_LVL_SEL_0 + default 1 if ESP_BROWNOUT_DET_LVL_SEL_1 default 2 if ESP_BROWNOUT_DET_LVL_SEL_2 default 3 if ESP_BROWNOUT_DET_LVL_SEL_3 default 4 if ESP_BROWNOUT_DET_LVL_SEL_4 diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c index 1997f547da2..e989d69ce02 100644 --- a/components/esp_system/port/soc/esp32h2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c @@ -20,6 +20,23 @@ static const char *TAG = "CACHE_ERR"; +const char cache_error_msg[] = "Cache access error"; + +const char *esp_cache_err_panic_string(void) +{ + const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + + /* Return the error string if a cache error is active */ + const char* err_str = access_err_status ? cache_error_msg : NULL; + + return err_str; +} + +bool esp_cache_err_has_active_err(void) +{ + return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index d6669894466..93cbb12d55b 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -32,8 +32,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Set Peripheral clk rst SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); diff --git a/components/esp_system/port/soc/esp32p4/cache_err_int.c b/components/esp_system/port/soc/esp32p4/cache_err_int.c index 673953660da..5024e470830 100644 --- a/components/esp_system/port/soc/esp32p4/cache_err_int.c +++ b/components/esp_system/port/soc/esp32p4/cache_err_int.c @@ -20,6 +20,18 @@ static const char *TAG = "CACHE_ERR"; +//TODO: IDF-7515 +const char *esp_cache_err_panic_string(void) +{ + return NULL; +} + +//TODO: IDF-7515 +bool esp_cache_err_has_active_err(void) +{ + return false; +} + //TODO: IDF-7515 void esp_cache_err_int_init(void) { @@ -53,7 +65,7 @@ void esp_cache_err_int_init(void) ESP_INTR_ENABLE(ETS_CACHEERR_INUM); } -int IRAM_ATTR esp_cache_err_get_cpuid(void) +int esp_cache_err_get_cpuid(void) { //TODO: IDF-7515 //Should return hart ID according to the cache error diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index b5ecc7e6dd7..86c1ab2766f 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -174,8 +174,6 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { - modem_clock_domain_pmu_state_icg_map_init(); - ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); #if 0 // TODO: IDF-5658 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; diff --git a/components/esp_system/port/soc/esp32p4/reset_reason.c b/components/esp_system/port/soc/esp32p4/reset_reason.c index 0615ce2b521..305a8bea260 100644 --- a/components/esp_system/port/soc/esp32p4/reset_reason.c +++ b/components/esp_system/port/soc/esp32p4/reset_reason.c @@ -97,8 +97,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint) REG_WRITE(RTC_RESET_CAUSE_REG, val); } -/* in IRAM, can be called from panic handler */ -esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) +esp_reset_reason_t esp_reset_reason_get_hint(void) { uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index 288483c5c7f..be53f1a61ee 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -31,8 +31,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Set Peripheral clk rst SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0); @@ -81,7 +84,7 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_write_protect_enable(&rtc_wdt_ctx); const uint32_t core_id = esp_cpu_get_core_id(); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE const uint32_t other_core_id = (core_id == 0) ? 1 : 0; esp_cpu_reset(other_core_id); esp_cpu_stall(other_core_id); @@ -108,7 +111,7 @@ void IRAM_ATTR esp_restart_noos(void) rtc_clk_cpu_freq_set_xtal(); #endif -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE // clear entry point for APP CPU ets_set_appcpu_boot_addr(0); #endif @@ -122,12 +125,12 @@ void IRAM_ATTR esp_restart_noos(void) // Reset CPUs if (core_id == 0) { // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE esp_cpu_reset(1); #endif esp_cpu_reset(0); } -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE else { // Running on APP CPU: need to reset PRO CPU and unstall it, // then reset APP CPU diff --git a/components/esp_system/port/soc/esp32s2/highint_hdl.S b/components/esp_system/port/soc/esp32s2/highint_hdl.S index c3d7dc0d8f0..7e16cd24073 100644 --- a/components/esp_system/port/soc/esp32s2/highint_hdl.S +++ b/components/esp_system/port/soc/esp32s2/highint_hdl.S @@ -1,22 +1,14 @@ -// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_private/panic_reason.h" #include "sdkconfig.h" #include "soc/soc.h" diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c index db71cf1feba..b790f36b654 100644 --- a/components/esp_system/port/soc/esp32s2/system_internal.c +++ b/components/esp_system/port/soc/esp32s2/system_internal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,7 +22,6 @@ #include "soc/syscon_reg.h" #include "soc/rtc_periph.h" #include "hal/wdt_hal.h" -#include "freertos/xtensa_api.h" #include "soc/soc_memory_layout.h" #include "esp32s2/rom/rtc.h" @@ -34,8 +33,11 @@ extern int _bss_end; void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Reset wifi/bluetooth/ethernet/sdio (bb/mac) DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, @@ -58,7 +60,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - xt_ints_off(0xFFFFFFFF); + esp_cpu_intr_disable(0xFFFFFFFF); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; diff --git a/components/esp_system/port/soc/esp32s3/Kconfig.tracemem b/components/esp_system/port/soc/esp32s3/Kconfig.tracemem index 4d4ba103a31..2bc24c1094e 100644 --- a/components/esp_system/port/soc/esp32s3/Kconfig.tracemem +++ b/components/esp_system/port/soc/esp32s3/Kconfig.tracemem @@ -21,7 +21,7 @@ menu "Trace memory" config ESP32S3_TRAX_TWOBANKS bool "Reserve memory for tracing both pro as well as app cpu execution" default "n" - depends on ESP32S3_TRAX && !FREERTOS_UNICORE + depends on ESP32S3_TRAX && !ESP_SYSTEM_SINGLE_CORE_MODE select ESP32S3_MEMMAP_TRACEMEM_TWOBANKS help The esp32-s3 contains a feature which allows you to trace the execution path the processor diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 07b1b933ed8..4c51e7fd9e6 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -197,14 +197,14 @@ __attribute__((weak)) void esp_perip_clk_init(void) uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk1 = 0; -#if CONFIG_FREERTOS_UNICORE +#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE soc_reset_reason_t rst_reas[1]; #else soc_reset_reason_t rst_reas[2]; #endif rst_reas[0] = esp_rom_get_reset_reason(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE rst_reas[1] = esp_rom_get_reset_reason(1); #endif @@ -213,7 +213,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) */ if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT || rst_reas[0] == RESET_REASON_CPU0_MWDT1) -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE || (rst_reas[1] == RESET_REASON_CPU1_MWDT0 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT || rst_reas[1] == RESET_REASON_CPU1_MWDT1) #endif diff --git a/components/esp_system/port/soc/esp32s3/highint_hdl.S b/components/esp_system/port/soc/esp32s3/highint_hdl.S index 78a5c711a34..298b0cf07f8 100644 --- a/components/esp_system/port/soc/esp32s3/highint_hdl.S +++ b/components/esp_system/port/soc/esp32s3/highint_hdl.S @@ -8,7 +8,7 @@ #include #include #include -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_private/panic_reason.h" #include "sdkconfig.h" #include "soc/soc.h" @@ -37,12 +37,12 @@ _l4_intr_stack: .align 4 xt_highint4: -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE /* See if we're here for the IPC_ISR interrupt */ rsr a0, INTERRUPT extui a0, a0, ETS_IPC_ISR_INUM, 1 bnez a0, jump_to_esp_ipc_isr_handler -#endif // not CONFIG_FREERTOS_UNICORE +#endif // not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE /* Allocate exception frame and save minimal context. */ mov a0, sp diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index 4748098e521..aa6de2ece6b 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,6 @@ #include "soc/syscon_reg.h" #include "soc/rtc_periph.h" #include "hal/wdt_hal.h" -#include "freertos/xtensa_api.h" #include "soc/soc_memory_layout.h" #include "esp32s3/rom/cache.h" @@ -34,9 +33,11 @@ extern int _bss_end; void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_uart_tx_wait_idle(i); + } + } // Reset wifi/bluetooth/ethernet/sdio (bb/mac) SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, @@ -66,7 +67,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - xt_ints_off(0xFFFFFFFF); + esp_cpu_intr_disable(0xFFFFFFFF); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; @@ -110,7 +111,7 @@ void IRAM_ATTR esp_restart_noos(void) // instruction. This would cause memory pool to be locked by arbiter // to the stalled CPU, preventing current CPU from accessing this pool. const uint32_t core_id = esp_cpu_get_core_id(); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE const uint32_t other_core_id = (core_id == 0) ? 1 : 0; esp_rom_software_reset_cpu(other_core_id); esp_cpu_stall(other_core_id); @@ -133,7 +134,7 @@ void IRAM_ATTR esp_restart_noos(void) rtc_clk_cpu_set_to_default_config(); #endif -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE // Clear entry point for APP CPU REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0); #endif @@ -141,12 +142,12 @@ void IRAM_ATTR esp_restart_noos(void) // Reset CPUs if (core_id == 0) { // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE esp_rom_software_reset_cpu(1); #endif esp_rom_software_reset_cpu(0); } -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE else { // Running on APP CPU: need to reset PRO CPU and unstall it, // then reset APP CPU diff --git a/components/esp_system/port/usb_console.c b/components/esp_system/port/usb_console.c index 7e5dc5b7a7a..fe8bf815877 100644 --- a/components/esp_system/port/usb_console.c +++ b/components/esp_system/port/usb_console.c @@ -310,7 +310,7 @@ esp_err_t esp_usb_console_init(void) * too early, before esp_timer is fully initialized. * This gets called a bit later in the process when we can already register a timer. */ -ESP_SYSTEM_INIT_FN(esp_usb_console_init_restart_timer, BIT(0), 220) +ESP_SYSTEM_INIT_FN(esp_usb_console_init_restart_timer, SECONDARY, BIT(0), 220) { esp_timer_create_args_t timer_create_args = { .callback = &esp_usb_console_on_restart_timeout, diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index 3a964925031..5fd5772bf48 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -16,65 +16,8 @@ #include "sdkconfig.h" #include "soc/soc_caps.h" -#include "hal/wdt_hal.h" -#include "hal/uart_types.h" -#include "hal/uart_ll.h" -#include "hal/efuse_hal.h" - -#include "esp_heap_caps_init.h" -#include "spi_flash_mmap.h" -#include "esp_flash_internal.h" -#include "esp_newlib.h" -#include "esp_timer.h" -#include "esp_efuse.h" -#include "esp_flash_encrypt.h" -#include "esp_secure_boot.h" -#include "esp_xt_wdt.h" #include "esp_cpu.h" -#include "esp_partition.h" - -/***********************************************/ -// Headers for other components init functions -#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE -#include "private/esp_coexist_internal.h" -#endif - -#if __has_include("esp_app_desc.h") -#define WITH_APP_IMAGE_INFO -#include "esp_app_desc.h" -#endif - -#if CONFIG_ESP_COREDUMP_ENABLE -#include "esp_core_dump.h" -#endif - -#include "esp_private/dbg_stubs.h" - -#if CONFIG_PM_ENABLE -#include "esp_pm.h" -#include "esp_private/pm_impl.h" -#endif - -#if CONFIG_VFS_SUPPORT_IO -#include "esp_vfs_dev.h" -#include "esp_vfs_console.h" -#endif - -#include "esp_pthread.h" -#include "esp_private/esp_clk.h" -#include "esp_private/spi_flash_os.h" -#include "esp_private/brownout.h" - -#include "esp_rom_caps.h" -#include "esp_rom_sys.h" - -#if CONFIG_SPIRAM -#include "esp_psram.h" -#include "esp_private/esp_psram_extram.h" -#endif -/***********************************************/ - #include "esp_private/startup_internal.h" // Ensure that system configuration matches the underlying number of cores. @@ -83,26 +26,8 @@ #error "System has been configured to run on multiple cores, but target SoC only has a single core." #endif -// Set efuse ROM_LOG_MODE on first boot -// -// For CONFIG_BOOT_ROM_LOG_ALWAYS_ON (default) or undefined (ESP32), leave -// ROM_LOG_MODE undefined (no need to call this function during startup) -#if CONFIG_BOOT_ROM_LOG_ALWAYS_OFF -#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ALWAYS_OFF -#elif CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW -#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_LOW -#elif CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH -#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_HIGH -#endif - - uint64_t g_startup_time = 0; -#if SOC_APB_BACKUP_DMA -// APB DMA lock initialising API -extern void esp_apb_backup_dma_lock_init(void); -#endif - // App entry point for core 0 extern void esp_startup_start_app(void); @@ -129,34 +54,8 @@ static volatile bool s_system_full_inited = false; const sys_startup_fn_t g_startup_fn[1] = { start_cpu0 }; #endif -#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS -// workaround for C++ exception crashes -void _Unwind_SetNoFunctionContextInstall(unsigned char enable) __attribute__((weak, alias("_Unwind_SetNoFunctionContextInstall_Default"))); -// workaround for C++ exception large memory allocation -void _Unwind_SetEnableExceptionFdeSorting(unsigned char enable); - -static IRAM_ATTR void _Unwind_SetNoFunctionContextInstall_Default(unsigned char enable __attribute__((unused))) -{ - (void)0; -} -#endif // CONFIG_COMPILER_CXX_EXCEPTIONS - static const char* TAG = "cpu_start"; -/** - * This function overwrites a the same function of libsupc++ (part of libstdc++). - * Consequently, libsupc++ will then follow our configured exception emergency pool size. - * - * It will be called even with -fno-exception for user code since the stdlib still uses exceptions. - */ -size_t __cxx_eh_arena_size_get(void) -{ -#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS - return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE; -#else - return 0; -#endif -} /** * Xtensa gcc is configured to emit a .ctors section, RISC-V gcc is configured with --enable-initfini-array @@ -209,9 +108,10 @@ static void do_global_ctors(void) * linker. The functions are sorted by their priority value. * The sequence of the init function calls (sorted by priority) is documented in * system_init_fn.txt file. + * @param stage_num Stage number of the init function call (0, 1). */ __attribute__((no_sanitize_undefined)) /* TODO: IDF-8133 */ -static void do_system_init_fn(void) +static void do_system_init_fn(uint32_t stage_num) { extern esp_system_init_fn_t _esp_system_init_fn_array_start; extern esp_system_init_fn_t _esp_system_init_fn_array_end; @@ -220,11 +120,12 @@ static void do_system_init_fn(void) int core_id = esp_cpu_get_core_id(); for (p = &_esp_system_init_fn_array_start; p < &_esp_system_init_fn_array_end; ++p) { - if (p->cores & BIT(core_id)) { - ESP_LOGD(TAG, "calling init function: %p on core: %d", p->fn, core_id); + if (p->stage == stage_num && (p->cores & BIT(core_id)) != 0) { + // During core init, stdout is not initialized yet, so use early logging. + ESP_EARLY_LOGD(TAG, "calling init function: %p on core: %d", p->fn, core_id); esp_err_t err = (*(p->fn))(); if (err != ESP_OK) { - ESP_LOGE(TAG, "init function %p has failed (0x%x), aborting", p->fn, err); + ESP_EARLY_LOGE(TAG, "init function %p has failed (0x%x), aborting", p->fn, err); abort(); } } @@ -248,7 +149,7 @@ static void esp_startup_start_app_other_cores_default(void) */ static void IRAM_ATTR start_cpu_other_cores_default(void) { - do_system_init_fn(); + do_system_init_fn(ESP_SYSTEM_INIT_STAGE_SECONDARY); while (!s_system_full_inited) { esp_rom_delay_us(100); @@ -260,120 +161,7 @@ static void IRAM_ATTR start_cpu_other_cores_default(void) static void do_core_init(void) { - /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted. - If the heap allocator is initialized first, it will put free memory linked list items into - memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory, - corrupting those linked lists. Initializing the allocator *after* the app cpu has booted - works around this problem. - With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the - app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may - fail initializing it properly. */ - heap_caps_init(); - - // When apptrace module is enabled, there will be SEGGER_SYSVIEW calls in the newlib init. - // SEGGER_SYSVIEW relies on apptrace module - // apptrace module uses esp_timer_get_time to determine timeout conditions. - // esp_timer early initialization is required for esp_timer_get_time to work. - esp_timer_early_init(); - esp_newlib_init(); - -#if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) - if (esp_psram_is_initialized()) { - esp_err_t r=esp_psram_extram_add_to_heap_allocator(); - if (r != ESP_OK) { - ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!"); - abort(); - } -#if CONFIG_SPIRAM_USE_MALLOC - heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL); -#endif - } -#endif - -#if CONFIG_ESP_BROWNOUT_DET - // [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) -> - // malloc (newlib) -> heap_caps_malloc (heap), so heap must be at least initialized - esp_brownout_init(); -#endif - - esp_newlib_time_init(); - -#if CONFIG_VFS_SUPPORT_IO - // VFS console register. - esp_err_t vfs_err = esp_vfs_console_register(); - assert(vfs_err == ESP_OK && "Failed to register vfs console"); -#endif - -#if defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE) - esp_newlib_init_global_stdio(ESP_VFS_DEV_CONSOLE); -#else - esp_newlib_init_global_stdio(NULL); -#endif - - esp_err_t err __attribute__((unused)); - - err = esp_pthread_init(); - assert(err == ESP_OK && "Failed to init pthread module!"); - -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP -#if CONFIG_SPI_FLASH_ROM_IMPL - spi_flash_rom_impl_init(); -#endif - - esp_flash_app_init(); - esp_err_t flash_ret = esp_flash_init_default_chip(); - assert(flash_ret == ESP_OK); - (void)flash_ret; -#if CONFIG_SPI_FLASH_BROWNOUT_RESET - spi_flash_needs_reset_check(); -#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET -#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - -#ifdef CONFIG_EFUSE_VIRTUAL - ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); -#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - const esp_partition_t *efuse_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM, NULL); - if (efuse_partition) { - esp_efuse_init_virtual_mode_in_flash(efuse_partition->address, efuse_partition->size); - } -#endif -#endif - -#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED - esp_flash_encryption_init_checks(); -#endif - -#if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT) - // Note: in some configs this may read flash, so placed after flash init - esp_secure_boot_init_checks(); -#endif - -#if CONFIG_SECURE_DISABLE_ROM_DL_MODE - err = esp_efuse_disable_rom_download_mode(); - assert(err == ESP_OK && "Failed to disable ROM download mode"); -#endif - -#if CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE - err = esp_efuse_enable_rom_secure_download_mode(); - assert(err == ESP_OK && "Failed to enable Secure Download mode"); -#endif - -#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE - esp_efuse_disable_basic_rom_console(); -#endif - -#ifdef ROM_LOG_MODE - esp_efuse_set_rom_log_scheme(ROM_LOG_MODE); -#endif - -#if CONFIG_ESP_XT_WDT - esp_xt_wdt_config_t cfg = { - .timeout = CONFIG_ESP_XT_WDT_TIMEOUT, - .auto_backup_clk_enable = CONFIG_ESP_XT_WDT_BACKUP_CLK_ENABLE, - }; - err = esp_xt_wdt_init(&cfg); - assert(err == ESP_OK && "Failed to init xtwdt"); -#endif + do_system_init_fn(ESP_SYSTEM_INIT_STAGE_CORE); } static void do_secondary_init(void) @@ -387,7 +175,7 @@ static void do_secondary_init(void) // Execute initialization functions esp_system_init_fn_t assigned to the main core. While // this is happening, all other cores are executing the initialization functions // assigned to them since they have been resumed already. - do_system_init_fn(); + do_system_init_fn(ESP_SYSTEM_INIT_STAGE_SECONDARY); #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE // Wait for all cores to finish secondary init. @@ -405,41 +193,6 @@ static void do_secondary_init(void) static void start_cpu0_default(void) { - - ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); - int cpu_freq = esp_clk_cpu_freq(); - ESP_EARLY_LOGI(TAG, "cpu freq: %d Hz", cpu_freq); - -#ifdef WITH_APP_IMAGE_INFO - // Display information about the current running image. - if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { - const esp_app_desc_t *app_desc = esp_app_get_description(); - ESP_EARLY_LOGI(TAG, "Application information:"); -#ifndef CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR - ESP_EARLY_LOGI(TAG, "Project name: %s", app_desc->project_name); -#endif -#ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR - ESP_EARLY_LOGI(TAG, "App version: %s", app_desc->version); -#endif -#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION - ESP_EARLY_LOGI(TAG, "Secure version: %d", app_desc->secure_version); -#endif -#ifdef CONFIG_APP_COMPILE_TIME_DATE - ESP_EARLY_LOGI(TAG, "Compile time: %s %s", app_desc->date, app_desc->time); -#endif - char buf[17]; - esp_app_get_elf_sha256(buf, sizeof(buf)); - ESP_EARLY_LOGI(TAG, "ELF file SHA256: %s...", buf); - ESP_EARLY_LOGI(TAG, "ESP-IDF: %s", app_desc->idf_ver); - - ESP_EARLY_LOGI(TAG, "Min chip rev: v%d.%d", CONFIG_ESP_REV_MIN_FULL / 100, CONFIG_ESP_REV_MIN_FULL % 100); - ESP_EARLY_LOGI(TAG, "Max chip rev: v%d.%d %s",CONFIG_ESP_REV_MAX_FULL / 100, CONFIG_ESP_REV_MAX_FULL % 100, - efuse_hal_get_disable_wafer_version_major() ? "(constraint ignored)" : ""); - unsigned revision = efuse_hal_chip_revision(); - ESP_EARLY_LOGI(TAG, "Chip rev: v%d.%d", revision / 100, revision % 100); - } -#endif - // Initialize core components and services. do_core_init(); @@ -450,14 +203,6 @@ static void start_cpu0_default(void) // until all cores finish (when !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE). do_secondary_init(); - // Now that the application is about to start, disable boot watchdog -#ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE - wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT(); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_disable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#endif - #if SOC_CPU_CORES_NUM > 1 && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE s_system_full_inited = true; #endif @@ -465,35 +210,3 @@ static void start_cpu0_default(void) esp_startup_start_app(); while (1); } - -ESP_SYSTEM_INIT_FN(init_components0, BIT(0), 200) -{ -#if CONFIG_ESP_DEBUG_STUBS_ENABLE - esp_dbg_stubs_init(); -#endif - -#if defined(CONFIG_PM_ENABLE) - esp_pm_impl_init(); -#endif - -#if CONFIG_ESP_COREDUMP_ENABLE - esp_core_dump_init(); -#endif - -#if SOC_APB_BACKUP_DMA - esp_apb_backup_dma_lock_init(); -#endif - -#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE - esp_coex_adapter_register(&g_coex_adapter_funcs); - coex_pre_init(); -#endif - -#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS - ESP_EARLY_LOGD(TAG, "Setting C++ exception workarounds."); - _Unwind_SetNoFunctionContextInstall(1); - _Unwind_SetEnableExceptionFdeSorting(0); -#endif // CONFIG_COMPILER_CXX_EXCEPTIONS - - return ESP_OK; -} diff --git a/components/esp_system/startup_funcs.c b/components/esp_system/startup_funcs.c new file mode 100644 index 00000000000..85cb9eee4b5 --- /dev/null +++ b/components/esp_system/startup_funcs.c @@ -0,0 +1,357 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_err.h" +#include "esp_check.h" +#include "esp_system.h" +#include "esp_log.h" +#include "esp_heap_caps_init.h" +#include "spi_flash_mmap.h" +#include "esp_flash_internal.h" +#include "esp_newlib.h" +#include "esp_timer.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_flash_encrypt.h" +#include "esp_partition.h" +#include "esp_secure_boot.h" +#include "esp_xt_wdt.h" +#include "esp_cpu.h" +#include "esp_private/startup_internal.h" +#include "soc/soc_caps.h" +#include "hal/wdt_hal.h" +#include "hal/uart_types.h" +#include "hal/uart_ll.h" +#include "hal/efuse_hal.h" + +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE +#include "private/esp_coexist_internal.h" +#endif + +#if __has_include("esp_app_desc.h") +#define WITH_APP_IMAGE_INFO +#include "esp_app_desc.h" +#endif + +#if CONFIG_ESP_COREDUMP_ENABLE +#include "esp_core_dump.h" +#endif + +#include "esp_private/dbg_stubs.h" + +#if CONFIG_PM_ENABLE +#include "esp_pm.h" +#include "esp_private/pm_impl.h" +#endif + +#include "esp_pthread.h" +#include "esp_private/esp_clk.h" +#include "esp_private/spi_flash_os.h" +#include "esp_private/brownout.h" + +#include "esp_rom_caps.h" +#include "esp_rom_sys.h" + +#if CONFIG_SPIRAM +#include "esp_psram.h" +#include "esp_private/esp_psram_extram.h" +#endif + +// Using the same tag as in startup.c to keep the logs unchanged +static const char* TAG = "cpu_start"; + +// Hook to force the linker to include this file +void esp_system_include_startup_funcs(void) +{ +} + +// [refactor-todo] Most of these init functions should be moved to the respective components. + +ESP_SYSTEM_INIT_FN(init_show_cpu_freq, CORE, BIT(0), 10) +{ + ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); + int cpu_freq = esp_clk_cpu_freq(); + ESP_EARLY_LOGI(TAG, "cpu freq: %d Hz", cpu_freq); + + return ESP_OK; +} + +#ifdef WITH_APP_IMAGE_INFO +ESP_SYSTEM_INIT_FN(init_show_app_info, CORE, BIT(0), 20) +{ + // Display information about the current running image. + if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { + const esp_app_desc_t *app_desc = esp_app_get_description(); + ESP_EARLY_LOGI(TAG, "Application information:"); +#ifndef CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR + ESP_EARLY_LOGI(TAG, "Project name: %s", app_desc->project_name); +#endif +#ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR + ESP_EARLY_LOGI(TAG, "App version: %s", app_desc->version); +#endif +#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION + ESP_EARLY_LOGI(TAG, "Secure version: %d", app_desc->secure_version); +#endif +#ifdef CONFIG_APP_COMPILE_TIME_DATE + ESP_EARLY_LOGI(TAG, "Compile time: %s %s", app_desc->date, app_desc->time); +#endif + char buf[17]; + esp_app_get_elf_sha256(buf, sizeof(buf)); + ESP_EARLY_LOGI(TAG, "ELF file SHA256: %s...", buf); + ESP_EARLY_LOGI(TAG, "ESP-IDF: %s", app_desc->idf_ver); + + ESP_EARLY_LOGI(TAG, "Min chip rev: v%d.%d", CONFIG_ESP_REV_MIN_FULL / 100, CONFIG_ESP_REV_MIN_FULL % 100); + ESP_EARLY_LOGI(TAG, "Max chip rev: v%d.%d %s", CONFIG_ESP_REV_MAX_FULL / 100, CONFIG_ESP_REV_MAX_FULL % 100, + efuse_hal_get_disable_wafer_version_major() ? "(constraint ignored)" : ""); + unsigned revision = efuse_hal_chip_revision(); + ESP_EARLY_LOGI(TAG, "Chip rev: v%d.%d", revision / 100, revision % 100); + } + return ESP_OK; +} +#endif // WITH_APP_IMAGE_INFO + +ESP_SYSTEM_INIT_FN(init_heap, CORE, BIT(0), 100) +{ + heap_caps_init(); + return ESP_OK; +} + +ESP_SYSTEM_INIT_FN(init_timer, CORE, BIT(0), 101) +{ + esp_timer_early_init(); + return ESP_OK; +} + +ESP_SYSTEM_INIT_FN(init_psram_heap, CORE, BIT(0), 103) +{ +#if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if (esp_psram_is_initialized()) { + esp_err_t r = esp_psram_extram_add_to_heap_allocator(); + if (r != ESP_OK) { + ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!"); + abort(); + } +#if CONFIG_SPIRAM_USE_MALLOC + heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL); +#endif + } +#endif + return ESP_OK; +} + +#if CONFIG_ESP_BROWNOUT_DET +ESP_SYSTEM_INIT_FN(init_brownout, CORE, BIT(0), 104) +{ + // [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) -> + // malloc (newlib) -> heap_caps_malloc (heap), so heap must be at least initialized + esp_brownout_init(); + return ESP_OK; +} +#endif + +ESP_SYSTEM_INIT_FN(init_newlib_time, CORE, BIT(0), 105) +{ + esp_newlib_time_init(); + return ESP_OK; +} + +ESP_SYSTEM_INIT_FN(init_pthread, CORE, BIT(0), 120) +{ + return esp_pthread_init(); +} + +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +ESP_SYSTEM_INIT_FN(init_flash, CORE, BIT(0), 130) +{ +#if CONFIG_SPI_FLASH_ROM_IMPL + spi_flash_rom_impl_init(); +#endif + + esp_flash_app_init(); + esp_err_t flash_ret = esp_flash_init_default_chip(); + assert(flash_ret == ESP_OK); + (void)flash_ret; +#if CONFIG_SPI_FLASH_BROWNOUT_RESET + spi_flash_needs_reset_check(); +#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET + return ESP_OK; +} +#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + +#ifdef CONFIG_EFUSE_VIRTUAL +ESP_SYSTEM_INIT_FN(init_virtual_efuse, CORE, BIT(0), 140) +{ + ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); +#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + const esp_partition_t *efuse_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM, NULL); + if (efuse_partition) { + esp_efuse_init_virtual_mode_in_flash(efuse_partition->address, efuse_partition->size); + } +#endif + return ESP_OK; +} +#endif // CONFIG_EFUSE_VIRTUAL + +ESP_SYSTEM_INIT_FN(init_secure, CORE, BIT(0), 150) +{ +#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED + esp_flash_encryption_init_checks(); +#endif + +#if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT) + // Note: in some configs this may read flash, so placed after flash init + esp_secure_boot_init_checks(); +#endif + +#if SOC_EFUSE_ECDSA_USE_HARDWARE_K + if (esp_efuse_find_purpose(ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, NULL)) { + // ECDSA key purpose block is present and hence permanently enable + // the hardware TRNG supplied k mode (most secure mode) + ESP_RETURN_ON_ERROR(esp_efuse_write_field_bit(ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K), TAG, "Failed to enable hardware k mode"); + } +#endif + +#if CONFIG_SECURE_DISABLE_ROM_DL_MODE + ESP_RETURN_ON_ERROR(esp_efuse_disable_rom_download_mode(), TAG, "Failed to disable ROM download mode"); +#endif + +#if CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE + ESP_RETURN_ON_ERROR(esp_efuse_enable_rom_secure_download_mode(), TAG, "Failed to enable Secure Download mode"); +#endif + +#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE + esp_efuse_disable_basic_rom_console(); +#endif + return ESP_OK; +} + +// Set efuse ROM_LOG_MODE on first boot +// +// For CONFIG_BOOT_ROM_LOG_ALWAYS_ON (default) or undefined (ESP32), leave +// ROM_LOG_MODE undefined (no need to call this function during startup) +#if CONFIG_BOOT_ROM_LOG_ALWAYS_OFF +#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ALWAYS_OFF +#elif CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW +#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_LOW +#elif CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH +#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_HIGH +#endif + +#ifdef ROM_LOG_MODE +ESP_SYSTEM_INIT_FN(init_rom_log, CORE, BIT(0), 160) +{ + esp_err_t err = esp_efuse_set_rom_log_scheme(ROM_LOG_MODE); + if (err == ESP_ERR_NOT_SUPPORTED) { + err = ESP_OK; + } + ESP_RETURN_ON_ERROR(err, TAG, "Failed to set ROM log scheme"); + return ESP_OK; +} +#endif // ROM_LOG_MODE + +#if CONFIG_ESP_XT_WDT +ESP_SYSTEM_INIT_FN(init_xt_wdt, CORE, BIT(0), 170) +{ + esp_xt_wdt_config_t cfg = { + .timeout = CONFIG_ESP_XT_WDT_TIMEOUT, + .auto_backup_clk_enable = CONFIG_ESP_XT_WDT_BACKUP_CLK_ENABLE, + }; + return esp_xt_wdt_init(&cfg); +} +#endif // CONFIG_ESP_XT_WDT + +#if CONFIG_ESP_DEBUG_STUBS_ENABLE +ESP_SYSTEM_INIT_FN(init_dbg_stubs, SECONDARY, BIT(0), 200) +{ + esp_dbg_stubs_init(); + return ESP_OK; +} +#endif // CONFIG_ESP_DEBUG_STUBS_ENABLE + +#if CONFIG_PM_ENABLE +ESP_SYSTEM_INIT_FN(init_pm, SECONDARY, BIT(0), 201) +{ + esp_pm_impl_init(); + return ESP_OK; +} +#endif // CONFIG_PM_ENABLE + +#if CONFIG_ESP_COREDUMP_ENABLE +ESP_SYSTEM_INIT_FN(init_coredump, SECONDARY, BIT(0), 202) +{ + esp_core_dump_init(); + return ESP_OK; +} +#endif // CONFIG_ESP_COREDUMP_ENABLE + +#if SOC_APB_BACKUP_DMA +ESP_SYSTEM_INIT_FN(init_apb_dma, SECONDARY, BIT(0), 203) +{ + extern void esp_apb_backup_dma_lock_init(void); + esp_apb_backup_dma_lock_init(); + return ESP_OK; +} +#endif + +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE +ESP_SYSTEM_INIT_FN(init_coexist, SECONDARY, BIT(0), 204) +{ + esp_coex_adapter_register(&g_coex_adapter_funcs); + coex_pre_init(); + return ESP_OK; +} +#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + +#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS +/** + * This function overwrites a the same function of libsupc++ (part of libstdc++). + * Consequently, libsupc++ will then follow our configured exception emergency pool size. + * + * It will be called even with -fno-exception for user code since the stdlib still uses exceptions. + */ +size_t __cxx_eh_arena_size_get(void) +{ +#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS + return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE; +#else + return 0; +#endif +} + +// workaround for C++ exception crashes +void _Unwind_SetNoFunctionContextInstall(unsigned char enable) __attribute__((weak, alias("_Unwind_SetNoFunctionContextInstall_Default"))); +// workaround for C++ exception large memory allocation +void _Unwind_SetEnableExceptionFdeSorting(unsigned char enable); + +static IRAM_ATTR void _Unwind_SetNoFunctionContextInstall_Default(unsigned char enable __attribute__((unused))) +{ + (void)0; +} + +ESP_SYSTEM_INIT_FN(init_cxx_exceptions, SECONDARY, BIT(0), 205) +{ + ESP_EARLY_LOGD(TAG, "Setting C++ exception workarounds."); + _Unwind_SetNoFunctionContextInstall(1); + _Unwind_SetEnableExceptionFdeSorting(0); + return ESP_OK; +} +#endif // CONFIG_COMPILER_CXX_EXCEPTIONS + +#ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE +ESP_SYSTEM_INIT_FN(init_disable_rtc_wdt, SECONDARY, BIT(0), 999) +{ + wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT(); + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + return ESP_OK; +} +#endif // CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index b336c1c5991..921bb5cbd40 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -7,35 +7,91 @@ # # Entries are ordered by the order of execution (i.e. from low priority values to high ones). # Each line has the following format: -# prio: function_name in path/to/source_file on affinity_expression +# stage: prio: function_name in path/to/source_file on affinity_expression # Where: +# stage: which startup stage the function is executed in (CORE or SECONDARY) # prio: priority value (higher value means function is executed later) # affinity_expression: bit map of cores the function is executed on +########### CORE startup stage ########### +# [refactor-todo]: move init calls into respective components + +# Log some information about the system +CORE: 10: init_show_cpu_freq in components/esp_system/startup_funcs.c on BIT(0) +CORE: 20: init_show_app_info in components/esp_system/startup_funcs.c on BIT(0) + +# Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted. +# If the heap allocator is initialized first, it will put free memory linked list items into +# memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory, +# corrupting those linked lists. Initializing the allocator *after* the app cpu has booted +# works around this problem. +# With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the +# app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may +# fail initializing it properly. +CORE: 100: init_heap in components/esp_system/startup_funcs.c on BIT(0) + +# When apptrace module is enabled, there will be SEGGER_SYSVIEW calls in the newlib init. +# SEGGER_SYSVIEW relies on apptrace module +# apptrace module uses esp_timer_get_time to determine timeout conditions. +# esp_timer early initialization is required for esp_timer_get_time to work. +CORE: 101: init_timer in components/esp_system/startup_funcs.c on BIT(0) + +CORE: 102: init_newlib in components/newlib/newlib_init.c on BIT(0) +CORE: 103: init_psram_heap in components/esp_system/startup_funcs.c on BIT(0) +CORE: 104: init_brownout in components/esp_system/startup_funcs.c on BIT(0) +CORE: 105: init_newlib_time in components/esp_system/startup_funcs.c on BIT(0) + +# Peripheral-specific implementation operators should be filled first +# Then register vfs console, and follow by newlib stdio initialization +CORE: 110: init_vfs_uart in components/esp_driver_uart/src/uart_vfs.c on BIT(0) +CORE: 114: init_vfs_console in components/vfs/vfs_console.c on BIT(0) +CORE: 115: init_newlib_stdio in components/newlib/newlib_init.c on BIT(0) + +CORE: 120: init_pthread in components/esp_system/startup_funcs.c on BIT(0) +CORE: 130: init_flash in components/esp_system/startup_funcs.c on BIT(0) +CORE: 140: init_virtual_efuse in components/esp_system/startup_funcs.c on BIT(0) +CORE: 150: init_secure in components/esp_system/startup_funcs.c on BIT(0) +CORE: 160: init_rom_log in components/esp_system/startup_funcs.c on BIT(0) +CORE: 170: init_xt_wdt in components/esp_system/startup_funcs.c on BIT(0) + + +########### SECONDARY startup stage ########### + # esp_timer has to be initialized early, since it is used by several other components -100: esp_timer_startup_init in components/esp_timer/src/esp_timer.c on CONFIG_ESP_TIMER_ISR_AFFINITY +SECONDARY: 100: esp_timer_startup_init in components/esp_timer/src/esp_timer.c on ESP_TIMER_INIT_MASK # HW stack guard via assist-debug module. -101: esp_hw_stack_guard_init in components/esp_system/hw_stack_guard.c on ESP_SYSTEM_INIT_ALL_CORES +SECONDARY: 101: esp_hw_stack_guard_init in components/esp_system/hw_stack_guard.c on ESP_SYSTEM_INIT_ALL_CORES # esp_sleep doesn't have init dependencies -105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0) -106: sleep_clock_startup_init in components/esp_hw_support/sleep_clock.c on BIT(0) -107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0) +SECONDARY: 105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0) +SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/sleep_clock.c on BIT(0) +SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0) # app_trace has to be initialized before systemview -115: esp_apptrace_init in components/app_trace/app_trace.c on ESP_SYSTEM_INIT_ALL_CORES -120: sysview_init in components/app_trace/sys_view/esp/SEGGER_RTT_esp.c on BIT(0) +SECONDARY: 115: esp_apptrace_init in components/app_trace/app_trace.c on ESP_SYSTEM_INIT_ALL_CORES +SECONDARY: 120: sysview_init in components/app_trace/sys_view/esp/SEGGER_RTT_esp.c on BIT(0) -# the rest of the components which are initialized from startup.c +# the rest of the components which are initialized from startup_funcs.c # [refactor-todo]: move init calls into respective components -200: init_components0 in components/esp_system/startup.c on BIT(0) +SECONDARY: 200: init_dbg_stubs in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 201: init_pm in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 202: init_coredump in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 203: init_apb_dma in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 204: init_coexist in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 205: init_cxx_exceptions in components/esp_system/startup_funcs.c on BIT(0) # usb_console needs to create an esp_timer at startup. -# This can be done only after esp_timer initialization, which is now in init_components0. -220: esp_usb_console_init_restart_timer in components/esp_system/port/usb_console.c on BIT(0) +# This can be done only after esp_timer initialization (esp_timer_startup_init). +SECONDARY: 220: esp_usb_console_init_restart_timer in components/esp_system/port/usb_console.c on BIT(0) + +# usb_serial_jtag needs to create and acquire a PM lock at startup. +# This makes more sense to be done after esp_pm_impl_init (called from init_pm). +SECONDARY: 230: usb_serial_jtag_conn_status_init in components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c on BIT(0) + +# Has to be the last step! +# Now that the application is about to start, disable boot watchdog +SECONDARY: 999: init_disable_rtc_wdt in components/esp_system/startup_funcs.c on BIT(0) -# usb_serial_jtag needs to create and acquire a PM clock at startup. -# This makes more sense to be done after esp_pm_impl_init, which is initialized in init_components0. -230: usb_serial_jtag_conn_status_init in components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c on BIT(0) +# DO NOT add new init functions here. Add them to the correct stage above. diff --git a/components/esp_system/task_wdt/task_wdt.c b/components/esp_system/task_wdt/task_wdt.c index 1eafe09836c..e1a4017b864 100644 --- a/components/esp_system/task_wdt/task_wdt.c +++ b/components/esp_system/task_wdt/task_wdt.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -279,7 +280,7 @@ static void unsubscribe_idle(uint32_t core_mask) ESP_ERROR_CHECK(esp_task_wdt_delete_user(core_user_handles[core_num])); core_user_handles[core_num] = NULL; #else // CONFIG_FREERTOS_SMP - TaskHandle_t idle_task_handle = xTaskGetIdleTaskHandleForCPU(core_num); + TaskHandle_t idle_task_handle = xTaskGetIdleTaskHandleForCore(core_num); assert(idle_task_handle); esp_deregister_freertos_idle_hook_for_cpu(idle_hook_cb, core_num); ESP_ERROR_CHECK(esp_task_wdt_delete(idle_task_handle)); @@ -306,7 +307,7 @@ static void subscribe_idle(uint32_t core_mask) ESP_ERROR_CHECK(esp_task_wdt_add_user((const char *)core_user_names[core_num], &core_user_handles[core_num])); ESP_ERROR_CHECK(esp_register_freertos_idle_hook_for_cpu(idle_hook_cb, core_num)); #else // CONFIG_FREERTOS_SMP - TaskHandle_t idle_task_handle = xTaskGetIdleTaskHandleForCPU(core_num); + TaskHandle_t idle_task_handle = xTaskGetIdleTaskHandleForCore(core_num); assert(idle_task_handle); ESP_ERROR_CHECK(esp_task_wdt_add(idle_task_handle)); ESP_ERROR_CHECK(esp_register_freertos_idle_hook_for_cpu(idle_hook_cb, core_num)); @@ -337,6 +338,32 @@ static void subscribe_idle(uint32_t core_mask) * */ +static UBaseType_t get_task_affinity(const TaskHandle_t xTask) +{ + if (xTask == NULL) { + /* User entry, we cannot predict on which core it is scheduled to run, + * so let's mark all cores as failing */ +#if configNUM_CORES > 1 + return BIT(1) | BIT(0); +#else + return BIT(0); +#endif + } + +#if CONFIG_FREERTOS_SMP + #if configNUM_CORES > 1 + return vTaskCoreAffinityGet(xTask); + #else + return BIT(0); + #endif +#else + BaseType_t task_affinity = xTaskGetCoreID(xTask); + if (task_affinity == 0 || task_affinity == 1) { + return BIT(task_affinity); + } + return BIT(1) | BIT(0); +#endif +} /** * Function simulating an abort coming from the interrupted task of the current @@ -386,7 +413,7 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic) const int current_core = xPortGetCoreID(); if (panic) { -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE const int other_core = !current_core; if ((cores_fail & BIT(0)) && (cores_fail & BIT(1))) { @@ -404,7 +431,7 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic) esp_crosscore_int_send_twdt_abort(other_core); while (1) {} } -#endif // !CONFIG_FREERTOS_UNICORE +#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE /* Current core is failing, abort right now */ task_wdt_timeout_abort(true); } else { @@ -413,13 +440,13 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic) ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core); esp_backtrace_print(100); } -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE const int other_core = !current_core; if (cores_fail & BIT(other_core)) { ESP_EARLY_LOGE(TAG, "Print CPU %d backtrace", other_core); esp_crosscore_int_send_print_backtrace(other_core); } -#endif // !CONFIG_FREERTOS_UNICORE +#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE } } @@ -456,68 +483,20 @@ static void task_wdt_isr(void *arg) portENTER_CRITICAL_ISR(&spinlock); esp_task_wdt_impl_timeout_triggered(p_twdt_obj->impl_ctx); - // If there are no entries, there's nothing to do. - if (SLIST_EMPTY(&p_twdt_obj->entries_slist)) { - portEXIT_CRITICAL_ISR(&spinlock); - return; - } - // Find what entries triggered the TWDT timeout (i.e., which entries have not been reset) - /* - Note: We are currently in a critical section, thus under normal circumstances, logging should not be allowed. - However, TWDT timeouts count as fatal errors, thus reporting the fatal error is considered more important than - minimizing interrupt latency. Thus we allow logging in critical sections in this narrow case. - */ - ESP_EARLY_LOGE(TAG, "Task watchdog got triggered. The following tasks/users did not reset the watchdog in time:"); - twdt_entry_t *entry; /* Keep a bitmap of CPU cores having tasks that have not reset TWDT. * Bit 0 represents core 0, bit 1 represents core 1, and so on. */ int cpus_fail = 0; bool panic = p_twdt_obj->panic; - SLIST_FOREACH(entry, &p_twdt_obj->entries_slist, slist_entry) { - if (!entry->has_reset) { - if (entry->task_handle) { -#if CONFIG_FREERTOS_SMP -#if configNUM_CORES > 1 - // Log the task's name and its affinity - const UBaseType_t affinity = vTaskCoreAffinityGet(entry->task_handle); - ESP_EARLY_LOGE(TAG, " - %s (0x%x)", pcTaskGetName(entry->task_handle), affinity); - cpus_fail |= affinity; -#else // configNUM_CORES > 1 - // Log the task's name - ESP_EARLY_LOGE(TAG, " - %s", pcTaskGetName(entry->task_handle)); - cpus_fail |= BIT(0); -#endif // configNUM_CORES > 1 -#else // CONFIG_FREERTOS_SMP - BaseType_t task_affinity = xTaskGetAffinity(entry->task_handle); - const char *cpu; - if (task_affinity == 0) { - cpu = DRAM_STR("CPU 0"); - cpus_fail |= BIT(0); - } else if (task_affinity == 1) { - cpu = DRAM_STR("CPU 1"); - cpus_fail |= BIT(1); - } else { - cpu = DRAM_STR("CPU 0/1"); - cpus_fail |= BIT(1) | BIT(0); - } - ESP_EARLY_LOGE(TAG, " - %s (%s)", pcTaskGetName(entry->task_handle), cpu); -#endif // CONFIG_FREERTOS_SMP - } else { - /* User entry, we cannot predict on which core it is scheduled to run, - * so let's mark all cores as failing */ -#if configNUM_CORES > 1 - cpus_fail = BIT(1) | BIT(0); -#else // configNUM_CORES > 1 - cpus_fail = BIT(0); -#endif // configNUM_CORES > 1 - ESP_EARLY_LOGE(TAG, " - %s", entry->user_name); - } - } - } + if (esp_task_wdt_print_triggered_tasks(NULL, NULL, &cpus_fail) != ESP_OK) { + // If there are no entries, there's nothing to do. + portEXIT_CRITICAL_ISR(&spinlock); + return; + } + ESP_EARLY_LOGE(TAG, "%s", DRAM_STR("Tasks currently running:")); for (int x = 0; x < portNUM_PROCESSORS; x++) { - ESP_EARLY_LOGE(TAG, "CPU %d: %s", x, pcTaskGetName(xTaskGetCurrentTaskHandleForCPU(x))); + ESP_EARLY_LOGE(TAG, "CPU %d: %s", x, pcTaskGetName(xTaskGetCurrentTaskHandleForCore(x))); } portEXIT_CRITICAL_ISR(&spinlock); @@ -806,3 +785,47 @@ esp_err_t esp_task_wdt_status(TaskHandle_t task_handle) return ret; } + +esp_err_t esp_task_wdt_print_triggered_tasks(task_wdt_msg_handler msg_handler, void *opaque, int *cpus_fail) +{ + if (SLIST_EMPTY(&p_twdt_obj->entries_slist)) { + return ESP_FAIL; + } + + twdt_entry_t *entry; + const char *caption = "Task watchdog got triggered. " + "The following tasks/users did not reset the watchdog in time:"; + + if (msg_handler == NULL) { + ESP_EARLY_LOGE(TAG, "%s", caption); + } else { + msg_handler(opaque, caption); + } + + // Find what entries triggered the TWDT timeout (i.e., which entries have not been reset) + SLIST_FOREACH(entry, &p_twdt_obj->entries_slist, slist_entry) { + if (!entry->has_reset) { + const char *cpu; + const char *name = entry->task_handle ? pcTaskGetName(entry->task_handle) : entry->user_name; + const UBaseType_t affinity = get_task_affinity(entry->task_handle); + if (cpus_fail) { + *cpus_fail |= affinity; + } + if (affinity == BIT(0)) { + cpu = " (CPU 0)"; + } else if (affinity == BIT(1)) { + cpu = " (CPU 1)"; + } else { + cpu = " (CPU 0/1)"; + } + if (msg_handler == NULL) { + ESP_EARLY_LOGE(TAG, " - %s%s", name, cpu); + } else { + msg_handler(opaque, "\n - "); + msg_handler(opaque, name); + msg_handler(opaque, cpu); + } + } + } + return ESP_OK; +} diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt b/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt index 3e822ddec19..7bccda3753b 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt @@ -1,6 +1,7 @@ set(requires "unity" "test_utils" - "driver" + "esp_driver_uart" + "esp_driver_gpio" "esp_timer" "nvs_flash" "esp_psram") @@ -10,6 +11,7 @@ set(SRC "test_app_main.c" "test_delay.c" "test_ipc.c" "test_reset_reason.c" + "test_shared_stack_printf.c" "test_sleep.c" "test_stack_check.c" "test_system_time.c" diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_app_main.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_app_main.c index d894e9325e1..fdaa6101fca 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_app_main.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_app_main.c @@ -11,7 +11,7 @@ #include "freertos/task.h" // Some resources are lazy allocated, the threshold is left for that case -#define TEST_MEMORY_LEAK_THRESHOLD (-800) +#define TEST_MEMORY_LEAK_THRESHOLD (-900) static size_t before_free_8bit; static size_t before_free_32bit; diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c index d1309f906e3..7724bc990a9 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,12 +10,14 @@ */ #include #include "unity.h" +#include "test_utils.h" #if __XTENSA__ #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "freertos/xtensa_api.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) +#include "esp_debug_helpers.h" #include "esp_intr_alloc.h" #include "esp_rom_sys.h" #include "esp_rom_uart.h" @@ -26,6 +28,8 @@ #define RECUR_DEPTH 3 #define ACTION_ABORT -1 #define ACTION_INT_WDT -2 +#define TASK_PRIORITY 5 + // Set to (-1) for abort(), (-2) for interrupt watchdog static int backtrace_trigger_source; @@ -118,4 +122,32 @@ TEST_CASE_MULTIPLE_STAGES("Test backtrace with a ROM function", "[reset_reason][ do_rom_crash, check_reset_reason_panic) + +#define NUM_TEST_FUNCS 2 + +static void backtrace_suspend_func(void *arg) +{ + // Simply suspend and wait to be deleted + vTaskSuspend(NULL); +} + +TEST_CASE("Test esp_backtrace_print_all_tasks()", "[esp_system]") +{ + TaskHandle_t task_handles[NUM_TEST_FUNCS]; + + for (int i = 0; i < NUM_TEST_FUNCS; i++) { + // Create multiple unpinned tasks at higher priorities + xTaskCreate(backtrace_suspend_func, "trace_func", 2048, NULL, UNITY_FREERTOS_PRIORITY + i + 1, &task_handles[i]); + } + // Short delay to allow tasks to suspend + vTaskDelay(10); + // Print backtraces of all tasks + esp_backtrace_print_all_tasks(3); + + // Clean up tasks + for (int i = 0; i < NUM_TEST_FUNCS; i++) { + vTaskDelete(task_handles[i]); + } +} + #endif diff --git a/components/newlib/test_apps/newlib/main/test_shared_stack_printf.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_shared_stack_printf.c similarity index 85% rename from components/newlib/test_apps/newlib/main/test_shared_stack_printf.c rename to components/esp_system/test_apps/esp_system_unity_tests/main/test_shared_stack_printf.c index 0fd2e0742f8..a2a85850ef0 100644 --- a/components/newlib/test_apps/newlib/main/test_shared_stack_printf.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_shared_stack_printf.c @@ -13,6 +13,10 @@ #include "test_utils.h" #include "esp_expression_with_stack.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-8832: RISC-V FPU does not work on shared stack, + // esp_execute_shared_stack_function might be deprecated because of + // the FPU issue and all the other issues with it. + #define SHARED_STACK_SIZE 8192 static StackType_t *shared_stack_sp = NULL; @@ -40,7 +44,7 @@ void another_external_stack_function(void) shared_stack_sp = (StackType_t *)esp_cpu_get_sp(); } -TEST_CASE("test printf using shared buffer stack", "[newlib]") +TEST_CASE("test printf using shared buffer stack", "[shared_stack]") { StackType_t *shared_stack = malloc(SHARED_STACK_SIZE); @@ -72,3 +76,4 @@ TEST_CASE("test printf using shared buffer stack", "[newlib]") vSemaphoreDelete(printf_lock); free(shared_stack); } +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c index e5cb5a31762..d830f3f27c4 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c @@ -26,7 +26,7 @@ #include "esp_rom_sys.h" #include "esp_timer.h" #include "esp_private/esp_clk.h" -#include "esp_private/uart_private.h" +#include "esp_private/uart_share_hw_ctrl.h" #include "esp_random.h" #include "nvs_flash.h" #include "nvs.h" @@ -416,7 +416,7 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is off (13 high)", "[deepsleep][ig { // This test needs external pulldown ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13)); - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_HIGH)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_HIGH)); esp_deep_sleep_start(); } @@ -425,9 +425,9 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is off (13 low)", "[deepsleep][ign // This test needs external pullup ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13)); #if CONFIG_IDF_TARGET_ESP32 - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW)); #else - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW)); #endif esp_deep_sleep_start(); } @@ -438,7 +438,7 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 high)", "[deepsleep][ign ESP_ERROR_CHECK(gpio_pullup_dis(GPIO_NUM_13)); ESP_ERROR_CHECK(gpio_pulldown_en(GPIO_NUM_13)); ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON)); - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_HIGH)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_HIGH)); esp_deep_sleep_start(); } @@ -449,9 +449,9 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][igno ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13)); ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON)); #if CONFIG_IDF_TARGET_ESP32 - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW)); #else - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW)); #endif esp_deep_sleep_start(); } diff --git a/components/esp_timer/Kconfig b/components/esp_timer/Kconfig index cbce3ae3a84..6cd748fa33a 100644 --- a/components/esp_timer/Kconfig +++ b/components/esp_timer/Kconfig @@ -74,12 +74,6 @@ menu "High resolution timer (esp_timer)" depends on !FREERTOS_UNICORE && ESP_TIMER_SHOW_EXPERIMENTAL endchoice - config ESP_TIMER_ISR_AFFINITY - hex - default 0x1 if ESP_TIMER_ISR_AFFINITY_CPU0 - default 0x2 if ESP_TIMER_ISR_AFFINITY_CPU1 - default FREERTOS_NO_AFFINITY if ESP_TIMER_ISR_AFFINITY_NO_AFFINITY - choice ESP_TIMER_ISR_AFFINITY prompt "timer interrupt core affinity" default ESP_TIMER_ISR_AFFINITY_CPU0 diff --git a/components/esp_timer/src/esp_timer.c b/components/esp_timer/src/esp_timer.c index 5fffae57702..7440a2c9355 100644 --- a/components/esp_timer/src/esp_timer.c +++ b/components/esp_timer/src/esp_timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -574,7 +574,16 @@ esp_err_t esp_timer_init(void) return err; } -ESP_SYSTEM_INIT_FN(esp_timer_startup_init, CONFIG_ESP_TIMER_ISR_AFFINITY, 100) +#if CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0 +#define ESP_TIMER_INIT_MASK BIT(0) +#elif CONFIG_ESP_TIMER_ISR_AFFINITY_CPU1 +#define ESP_TIMER_INIT_MASK BIT(1) +#elif CONFIG_ESP_TIMER_ISR_AFFINITY_NO_AFFINITY +#define ESP_TIMER_INIT_MASK ESP_SYSTEM_INIT_ALL_CORES +#endif // CONFIG_ESP_TIMER_ISR_AFFINITY_* + + +ESP_SYSTEM_INIT_FN(esp_timer_startup_init, SECONDARY, ESP_TIMER_INIT_MASK, 100) { return esp_timer_init(); } diff --git a/components/esp_timer/src/esp_timer_impl_systimer.c b/components/esp_timer/src/esp_timer_impl_systimer.c index dbd701ee62f..2c1a9362d74 100644 --- a/components/esp_timer/src/esp_timer_impl_systimer.c +++ b/components/esp_timer/src/esp_timer_impl_systimer.c @@ -156,7 +156,12 @@ void esp_timer_impl_advance(int64_t time_diff_us) esp_err_t esp_timer_impl_early_init(void) { - periph_module_enable(PERIPH_SYSTIMER_MODULE); + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_SYSTIMER_MODULE, ref_count) { + if (ref_count == 0) { + systimer_ll_enable_bus_clock(true); + systimer_ll_reset_register(); + } + } systimer_hal_tick_rate_ops_t ops = { .ticks_to_us = systimer_ticks_to_us, .us_to_ticks = systimer_us_to_ticks, diff --git a/components/esp_wifi/CMakeLists.txt b/components/esp_wifi/CMakeLists.txt index 14d5d423a81..8605bed5dfa 100644 --- a/components/esp_wifi/CMakeLists.txt +++ b/components/esp_wifi/CMakeLists.txt @@ -71,4 +71,8 @@ if(CONFIG_ESP_WIFI_ENABLED) endforeach() endif() + if(CONFIG_SPIRAM) + idf_component_optional_requires(PRIVATE esp_psram) + endif() + endif() diff --git a/components/esp_wifi/esp32/esp_adapter.c b/components/esp_wifi/esp32/esp_adapter.c index a1d6914a877..5d2ae86a132 100644 --- a/components/esp_wifi/esp32/esp_adapter.c +++ b/components/esp_wifi/esp32/esp_adapter.c @@ -17,7 +17,7 @@ #include "freertos/semphr.h" #include "freertos/event_groups.h" #include "freertos/portmacro.h" -#include "freertos/xtensa_api.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/esp_wifi/esp32s2/esp_adapter.c b/components/esp_wifi/esp32s2/esp_adapter.c index b0672498cc7..826b6a4fa37 100644 --- a/components/esp_wifi/esp32s2/esp_adapter.c +++ b/components/esp_wifi/esp32s2/esp_adapter.c @@ -17,7 +17,7 @@ #include "freertos/semphr.h" #include "freertos/event_groups.h" #include "freertos/portmacro.h" -#include "freertos/xtensa_api.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/esp_wifi/esp32s3/esp_adapter.c b/components/esp_wifi/esp32s3/esp_adapter.c index e6ca995af7f..662041d4ae6 100644 --- a/components/esp_wifi/esp32s3/esp_adapter.c +++ b/components/esp_wifi/esp32s3/esp_adapter.c @@ -17,7 +17,7 @@ #include "freertos/semphr.h" #include "freertos/event_groups.h" #include "freertos/portmacro.h" -#include "freertos/xtensa_api.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/esp_wifi/include/esp_now.h b/components/esp_wifi/include/esp_now.h index 3e8e8e299d3..0f01054d8cf 100644 --- a/components/esp_wifi/include/esp_now.h +++ b/components/esp_wifi/include/esp_now.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -41,6 +41,7 @@ extern "C" { #define ESP_ERR_ESPNOW_INTERNAL (ESP_ERR_ESPNOW_BASE + 6) /*!< Internal error */ #define ESP_ERR_ESPNOW_EXIST (ESP_ERR_ESPNOW_BASE + 7) /*!< ESPNOW peer has existed */ #define ESP_ERR_ESPNOW_IF (ESP_ERR_ESPNOW_BASE + 8) /*!< Interface error */ +#define ESP_ERR_ESPNOW_CHAN (ESP_ERR_ESPNOW_BASE + 9) /*!< Channel error */ #define ESP_NOW_ETH_ALEN 6 /*!< Length of ESPNOW peer MAC address */ #define ESP_NOW_KEY_LEN 16 /*!< Length of ESPNOW peer local master key */ @@ -205,7 +206,8 @@ esp_err_t esp_now_unregister_send_cb(void); * - ESP_ERR_ESPNOW_INTERNAL : internal error * - ESP_ERR_ESPNOW_NO_MEM : out of memory, when this happens, you can delay a while before sending the next data * - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found - * - ESP_ERR_ESPNOW_IF : current WiFi interface doesn't match that of peer + * - ESP_ERR_ESPNOW_IF : current Wi-Fi interface doesn't match that of peer + * - ESP_ERR_ESPNOW_CHAN: current Wi-Fi channel doesn't match that of peer */ esp_err_t esp_now_send(const uint8_t *peer_addr, const uint8_t *data, size_t len); diff --git a/components/esp_wifi/include/esp_private/wifi_os_adapter.h b/components/esp_wifi/include/esp_private/wifi_os_adapter.h index 4b55b9c6b49..84ace9fd1be 100644 --- a/components/esp_wifi/include/esp_private/wifi_os_adapter.h +++ b/components/esp_wifi/include/esp_private/wifi_os_adapter.h @@ -8,6 +8,10 @@ #define ESP_WIFI_OS_ADAPTER_H_ #include +#include +#include +#include +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { diff --git a/components/esp_wifi/include/esp_wifi.h b/components/esp_wifi/include/esp_wifi.h index f5a8d974681..e4ea220cf7e 100644 --- a/components/esp_wifi/include/esp_wifi.h +++ b/components/esp_wifi/include/esp_wifi.h @@ -88,6 +88,7 @@ extern "C" { #define ESP_ERR_WIFI_TWT_SETUP_TXFAIL (ESP_ERR_WIFI_BASE + 25) /*!< TWT setup frame tx failed */ #define ESP_ERR_WIFI_TWT_SETUP_REJECT (ESP_ERR_WIFI_BASE + 26) /*!< The twt setup request was rejected by the AP */ #define ESP_ERR_WIFI_DISCARD (ESP_ERR_WIFI_BASE + 27) /*!< Discard frame */ +#define ESP_ERR_WIFI_ROC_IN_PROGRESS (ESP_ERR_WIFI_BASE + 28) /*!< ROC op is in progress */ /** * @brief WiFi stack configuration parameters passed to esp_wifi_init call. @@ -180,7 +181,6 @@ typedef struct { #endif extern const wpa_crypto_funcs_t g_wifi_default_wpa_crypto_funcs; -extern uint64_t g_wifi_feature_caps; #define WIFI_INIT_CONFIG_MAGIC 0x1F2F3F4F @@ -214,11 +214,41 @@ extern uint64_t g_wifi_feature_caps; #define WIFI_STA_DISCONNECTED_PM_ENABLED false #endif -#define CONFIG_FEATURE_WPA3_SAE_BIT (1<<0) +#if CONFIG_ESP_WIFI_ENABLE_WPA3_SAE +#define WIFI_ENABLE_WPA3_SAE (1<<0) +#else +#define WIFI_ENABLE_WPA3_SAE 0 +#endif + +#if CONFIG_SPIRAM +#define WIFI_ENABLE_SPIRAM (1<<1) +#else +#define WIFI_ENABLE_SPIRAM 0 +#endif + +#if CONFIG_ESP_WIFI_FTM_INITIATOR_SUPPORT +#define WIFI_FTM_INITIATOR (1<<2) +#else +#define WIFI_FTM_INITIATOR 0 +#endif + +#if CONFIG_ESP_WIFI_FTM_RESPONDER_SUPPORT +#define WIFI_FTM_RESPONDER (1<<3) +#else +#define WIFI_FTM_RESPONDER 0 +#endif + +#define CONFIG_FEATURE_WPA3_SAE_BIT (1<<0) #define CONFIG_FEATURE_CACHE_TX_BUF_BIT (1<<1) #define CONFIG_FEATURE_FTM_INITIATOR_BIT (1<<2) #define CONFIG_FEATURE_FTM_RESPONDER_BIT (1<<3) +/* Set additional WiFi features and capabilities */ +#define WIFI_FEATURE_CAPS (WIFI_ENABLE_WPA3_SAE | \ + WIFI_ENABLE_SPIRAM | \ + WIFI_FTM_INITIATOR | \ + WIFI_FTM_RESPONDER) + #define WIFI_INIT_CONFIG_DEFAULT() { \ .osi_funcs = &g_wifi_osi_funcs, \ .wpa_crypto_funcs = g_wifi_default_wpa_crypto_funcs, \ @@ -240,7 +270,7 @@ extern uint64_t g_wifi_feature_caps; .wifi_task_core_id = WIFI_TASK_CORE_ID,\ .beacon_max_len = WIFI_SOFTAP_BEACON_MAX_LEN, \ .mgmt_sbuf_num = WIFI_MGMT_SBUF_NUM, \ - .feature_caps = g_wifi_feature_caps, \ + .feature_caps = WIFI_FEATURE_CAPS, \ .sta_disconnected_pm = WIFI_STA_DISCONNECTED_PM_ENABLED, \ .espnow_max_encrypt_num = CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM, \ .magic = WIFI_INIT_CONFIG_MAGIC\ @@ -411,9 +441,9 @@ esp_err_t esp_wifi_deauth_sta(uint16_t aid); /** * @brief Scan all available APs. * - * @attention If this API is called, the found APs are stored in WiFi driver dynamic allocated memory and the - * will be freed in esp_wifi_scan_get_ap_records, so generally, call esp_wifi_scan_get_ap_records to cause - * the memory to be freed once the scan is done + * @attention If this API is called, the found APs are stored in WiFi driver dynamic allocated memory. And then + * can be freed in esp_wifi_scan_get_ap_records(), esp_wifi_scan_get_ap_record() or esp_wifi_clear_ap_list(), + * so call any one to free the memory once the scan is done. * @attention The values of maximum active scan time and passive scan time per channel are limited to 1500 milliseconds. * Values above 1500ms may cause station to disconnect from AP and are not recommended. * @@ -460,7 +490,9 @@ esp_err_t esp_wifi_scan_stop(void); esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number); /** - * @brief Get AP list found in last scan + * @brief Get AP list found in last scan. + * + * @attention This API will free all memory occupied by scanned AP list. * * @param[inout] number As input param, it stores max AP number ap_records can hold. * As output param, it receives the actual AP number this API returns. @@ -475,11 +507,30 @@ esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number); */ esp_err_t esp_wifi_scan_get_ap_records(uint16_t *number, wifi_ap_record_t *ap_records); +/** + * @brief Get one AP record from the scanned AP list. + * + * @attention Different from esp_wifi_scan_get_ap_records(), this API only gets one AP record + * from the scanned AP list each time. This API will free the memory of one AP record, + * if the user doesn't get all records in the scannned AP list, then needs to call esp_wifi_clear_ap_list() + * to free the remaining memory. + * + * @param[out] ap_record pointer to one AP record + * + * @return + * - ESP_OK: succeed + * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start + * - ESP_ERR_INVALID_ARG: invalid argument + * - ESP_FAIL: scan APs is NULL, means all AP records fetched or no AP found + */ +esp_err_t esp_wifi_scan_get_ap_record(wifi_ap_record_t *ap_record); /** * @brief Clear AP list found in last scan * - * @attention When the obtained ap list fails,bss info must be cleared,otherwise it may cause memory leakage. + * @attention This API will free all memory occupied by scanned AP list. + * When the obtained AP list fails, AP records must be cleared,otherwise it may cause memory leakage. * * @return * - ESP_OK: succeed diff --git a/components/esp_wifi/include/esp_wifi_crypto_types.h b/components/esp_wifi/include/esp_wifi_crypto_types.h index 31832560fd5..6b41cc524a8 100644 --- a/components/esp_wifi/include/esp_wifi_crypto_types.h +++ b/components/esp_wifi/include/esp_wifi_crypto_types.h @@ -14,6 +14,9 @@ During normal operation, you don't need to use any of these types or functions in this header. See esp_wifi.h & esp_wifi_types.h instead. */ +#include +#include +#include #ifdef __cplusplus extern "C" { @@ -131,7 +134,7 @@ typedef int (*esp_sha256_prf_t)(const unsigned char *key, int key_len, const cha * * @param key Key for HMAC operations * @param key_len Length of the key in bytes - * @param dataPointers to the data area + * @param data Pointers to the data area * @param data_len Length of the data area * @param mac Buffer for the hash (16 bytes) * Returns: 0 on success, -1 on failure @@ -324,7 +327,7 @@ typedef int (*esp_omac1_aes_128_t)(const uint8_t *key, const uint8_t *data, size * Counter Mode Cipher Block Chaining Message Authentication * Code Protocol) which is used in IEEE 802.11i RSN standard. * @param tk 128-bit Temporal Key for obtained during 4-way handshake - * @param hdr Pointer to IEEE802.11 frame headeri needed for AAD + * @param ieee80211_hdr Pointer to IEEE802.11 frame headeri needed for AAD * @param data Pointer to encrypted data buffer * @param data_len Encrypted data length in bytes * @param decrypted_len Length of decrypted data @@ -370,7 +373,7 @@ typedef int (*esp_aes_gmac_t)(const uint8_t *key, size_t keylen, const uint8_t * * @param num_elem Number of elements in the data vector * @param addr Pointers to the data areas * @param len Lengths of the data blocks - * @param mac Buffer for the hash + * @param buf Buffer for the hash * Returns: 0 on success, -1 on failure */ typedef int (*esp_sha256_vector_t)(size_t num_elem, const uint8_t *addr[], const size_t *len, uint8_t *buf); diff --git a/components/esp_wifi/include/esp_wifi_default.h b/components/esp_wifi/include/esp_wifi_default.h index 0bb6450ab79..d30d512e358 100644 --- a/components/esp_wifi/include/esp_wifi_default.h +++ b/components/esp_wifi/include/esp_wifi_default.h @@ -8,6 +8,7 @@ #define _ESP_WIFI_DEFAULT_H #include "esp_netif.h" +#include "esp_wifi_types.h" #ifdef __cplusplus extern "C" { diff --git a/components/esp_wifi/include/esp_wifi_he_types.h b/components/esp_wifi/include/esp_wifi_he_types.h index 507367e53a3..41d4424abda 100644 --- a/components/esp_wifi/include/esp_wifi_he_types.h +++ b/components/esp_wifi/include/esp_wifi_he_types.h @@ -54,7 +54,8 @@ typedef struct { 1- acquire the complete HE-LTF2 2- sample evenly among the HE-LTF1 and HE-LTF2 */ uint32_t val_scale_cfg : 2; /**< value 0-3 */ - uint32_t reserved : 20; /**< reserved */ + uint32_t dump_ack_en : 1; /**< enable to dump 802.11 ACK frame, default disabled */ + uint32_t reserved : 19; /**< reserved */ } wifi_csi_acquire_config_t; /** diff --git a/components/esp_wifi/include/esp_wifi_netif.h b/components/esp_wifi/include/esp_wifi_netif.h index c25c52edd9f..7dfa724b066 100644 --- a/components/esp_wifi/include/esp_wifi_netif.h +++ b/components/esp_wifi/include/esp_wifi_netif.h @@ -1,11 +1,17 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include +#include +#include "esp_err.h" +#include "esp_wifi_types.h" +#include "esp_netif_types.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_wifi/include/esp_wifi_types.h b/components/esp_wifi/include/esp_wifi_types.h index 8500fb3b762..b5d9affc5b8 100644 --- a/components/esp_wifi/include/esp_wifi_types.h +++ b/components/esp_wifi/include/esp_wifi_types.h @@ -133,6 +133,9 @@ typedef enum { WIFI_REASON_ROAMING = 207, WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG = 208, WIFI_REASON_SA_QUERY_TIMEOUT = 209, + WIFI_REASON_NO_AP_FOUND_W_COMPATIBLE_SECURITY = 210, + WIFI_REASON_NO_AP_FOUND_IN_AUTHMODE_THRESHOLD = 211, + WIFI_REASON_NO_AP_FOUND_IN_RSSI_THRESHOLD = 212, } wifi_err_reason_t; typedef enum { @@ -450,24 +453,26 @@ typedef struct { signed rssi:8; /**< Received Signal Strength Indicator(RSSI) of packet. unit: dBm */ unsigned rate:5; /**< PHY rate encoding of the packet. Only valid for non HT(11bg) packet */ unsigned :1; /**< reserved */ - unsigned sig_mode:2; /**< 0: non HT(11bg) packet; 1: HT(11n) packet; 3: VHT(11ac) packet */ + unsigned sig_mode:2; /**< Protocol of the reveived packet, 0: non HT(11bg) packet; 1: HT(11n) packet; 3: VHT(11ac) packet */ unsigned :16; /**< reserved */ unsigned mcs:7; /**< Modulation Coding Scheme. If is HT(11n) packet, shows the modulation, range from 0 to 76(MSC0 ~ MCS76) */ unsigned cwb:1; /**< Channel Bandwidth of the packet. 0: 20MHz; 1: 40MHz */ unsigned :16; /**< reserved */ - unsigned smoothing:1; /**< reserved */ - unsigned not_sounding:1; /**< reserved */ + unsigned smoothing:1; /**< Set to 1 indicates that channel estimate smoothing is recommended. + Set to 0 indicates that only per-carrierindependent (unsmoothed) channel estimate is recommended. */ + unsigned not_sounding:1; /**< Set to 0 indicates that PPDU is a sounding PPDU. Set to 1indicates that the PPDU is not a sounding PPDU. + sounding PPDU is used for channel estimation by the request receiver */ unsigned :1; /**< reserved */ unsigned aggregation:1; /**< Aggregation. 0: MPDU packet; 1: AMPDU packet */ unsigned stbc:2; /**< Space Time Block Code(STBC). 0: non STBC packet; 1: STBC packet */ - unsigned fec_coding:1; /**< Flag is set for 11n packets which are LDPC */ + unsigned fec_coding:1; /**< Forward Error Correction(FEC). Flag is set for 11n packets which are LDPC */ unsigned sgi:1; /**< Short Guide Interval(SGI). 0: Long GI; 1: Short GI */ #if CONFIG_IDF_TARGET_ESP32 signed noise_floor:8; /**< noise floor of Radio Frequency Module(RF). unit: dBm*/ #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 unsigned :8; /**< reserved */ #endif - unsigned ampdu_cnt:8; /**< ampdu cnt */ + unsigned ampdu_cnt:8; /**< the number of subframes aggregated in AMPDU */ unsigned channel:4; /**< primary channel on which this packet is received */ unsigned secondary_channel:4; /**< secondary channel on which this packet is received. 0: none; 1: above; 2: below */ unsigned :8; /**< reserved */ @@ -561,6 +566,7 @@ typedef struct { bool channel_filter_en; /**< enable to turn on channel filter to smooth adjacent sub-carrier. Disable it to keep independence of adjacent sub-carrier. Default enabled */ bool manu_scale; /**< manually scale the CSI data by left shifting or automatically scale the CSI data. If set true, please set the shift bits. false: automatically. true: manually. Default false */ uint8_t shift; /**< manually left shift bits of the scale of the CSI data. The range of the left shift bits is 0~15 */ + bool dump_ack_en; /**< enable to dump 802.11 ACK frame, default disabled */ } wifi_csi_config_t; #endif @@ -572,9 +578,12 @@ typedef struct { wifi_pkt_rx_ctrl_t rx_ctrl;/**< received packet radio metadata header of the CSI data */ uint8_t mac[6]; /**< source MAC address of the CSI data */ uint8_t dmac[6]; /**< destination MAC address of the CSI data */ - bool first_word_invalid; /**< first four bytes of the CSI data is invalid or not */ - int8_t *buf; /**< buffer of CSI data */ - uint16_t len; /**< length of CSI data */ + bool first_word_invalid; /**< first four bytes of the CSI data is invalid or not, true indicates the first four bytes is invalid due to hardware limition */ + int8_t *buf; /**< valid buffer of CSI data */ + uint16_t len; /**< valid length of CSI data */ + uint8_t *hdr; /**< header of the wifi packet */ + uint8_t *payload; /**< payload of the wifi packet */ + uint16_t payload_len; /**< payload len of the wifi packet */ } wifi_csi_info_t; /** @@ -894,6 +903,7 @@ typedef enum { WIFI_EVENT_NDP_INDICATION, /**< Received NDP Request from a NAN Peer */ WIFI_EVENT_NDP_CONFIRM, /**< NDP Confirm Indication */ WIFI_EVENT_NDP_TERMINATED, /**< NAN Datapath terminated indication */ + WIFI_EVENT_HOME_CHANNEL_CHANGE, /**< WiFi home channel change，doesn't occur when scanning */ WIFI_EVENT_MAX, /**< Invalid WiFi event ID */ } wifi_event_t; @@ -986,6 +996,14 @@ typedef struct { int32_t rssi; /**< RSSI value of bss */ } wifi_event_bss_rssi_low_t; +/** Argument structure for WIFI_EVENT_HOME_CHANNEL_CHANGE event */ +typedef struct { + uint8_t old_chan; /**< old home channel of the device */ + wifi_second_chan_t old_snd; /**< old second channel of the device */ + uint8_t new_chan; /**< new home channel of the device */ + wifi_second_chan_t new_snd; /**< new second channel of the device */ +} wifi_event_home_channel_change_t; + /** * @brief FTM operation status types * diff --git a/components/esp_wifi/include/smartconfig_ack.h b/components/esp_wifi/include/smartconfig_ack.h index abfada3ffaa..ea2cee59437 100644 --- a/components/esp_wifi/include/smartconfig_ack.h +++ b/components/esp_wifi/include/smartconfig_ack.h @@ -1,20 +1,16 @@ -// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef SMARTCONFIG_ACK_H #define SMARTCONFIG_ACK_H +#include "esp_smartconfig.h" +#include "esp_err.h" +#include + #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index c9cff30ae4a..0105d2a2df2 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit c9cff30ae4aa2aaf251d9823f3feef4e784c7fd2 +Subproject commit 0105d2a2df2735a121bb1cd585658e59be03cf61 diff --git a/components/esp_wifi/src/wifi_init.c b/components/esp_wifi/src/wifi_init.c index e0594aec940..73b11acf9ab 100644 --- a/components/esp_wifi/src/wifi_init.c +++ b/components/esp_wifi/src/wifi_init.c @@ -19,10 +19,15 @@ #include "private/esp_coexist_internal.h" #include "esp_phy_init.h" #include "esp_private/phy.h" +#if __has_include("esp_psram.h") +#include "esp_psram.h" +#endif #ifdef CONFIG_ESP_WIFI_NAN_ENABLE #include "apps_private/wifi_apps_private.h" #endif +static bool s_wifi_inited = false; + #if (CONFIG_ESP_WIFI_RX_BA_WIN > CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM) #error "WiFi configuration check: WARNING, WIFI_RX_BA_WIN should not be larger than WIFI_DYNAMIC_RX_BUFFER_NUM!" #endif @@ -43,22 +48,6 @@ static esp_pm_lock_handle_t s_wifi_modem_sleep_lock; wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb = NULL; #endif -/* Set additional WiFi features and capabilities */ -uint64_t g_wifi_feature_caps = -#if CONFIG_ESP_WIFI_ENABLE_WPA3_SAE - CONFIG_FEATURE_WPA3_SAE_BIT | -#endif -#if CONFIG_SPIRAM - CONFIG_FEATURE_CACHE_TX_BUF_BIT | -#endif -#if CONFIG_ESP_WIFI_FTM_INITIATOR_SUPPORT - CONFIG_FEATURE_FTM_INITIATOR_BIT | -#endif -#if CONFIG_ESP_WIFI_FTM_RESPONDER_SUPPORT - CONFIG_FEATURE_FTM_RESPONDER_BIT | -#endif -0; - #if SOC_PM_SUPPORT_PMU_MODEM_STATE # define WIFI_BEACON_MONITOR_CONFIG_DEFAULT(ena) { \ .enable = (ena), \ @@ -116,7 +105,7 @@ static void esp_wifi_set_log_level(void) esp_wifi_internal_set_log_level(wifi_log_level); } -esp_err_t esp_wifi_deinit(void) +static esp_err_t wifi_deinit_internal(void) { esp_err_t err = ESP_OK; @@ -140,6 +129,13 @@ esp_err_t esp_wifi_deinit(void) ESP_LOGE(TAG, "Failed to deinit Wi-Fi driver (0x%x)", err); return err; } +#ifdef CONFIG_PM_ENABLE + if (s_wifi_modem_sleep_lock) { + esp_pm_lock_delete(s_wifi_modem_sleep_lock); + s_wifi_modem_sleep_lock = NULL; + } +#endif + esp_wifi_power_domain_off(); #if CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT wifi_beacon_monitor_config_t monitor_config = WIFI_BEACON_MONITOR_CONFIG_DEFAULT(false); @@ -163,7 +159,6 @@ esp_err_t esp_wifi_deinit(void) esp_unregister_mac_bb_pd_callback(pm_mac_sleep); esp_unregister_mac_bb_pu_callback(pm_mac_wakeup); #endif - esp_wifi_power_domain_off(); #if CONFIG_MAC_BB_PD esp_wifi_internal_set_mac_sleep(false); esp_mac_bb_pd_mem_deinit(); @@ -174,9 +169,20 @@ esp_err_t esp_wifi_deinit(void) #endif esp_phy_modem_deinit(); + s_wifi_inited = false; + return err; } +esp_err_t esp_wifi_deinit(void) +{ + if (s_wifi_inited == false) { + return ESP_ERR_WIFI_NOT_INIT; + } + + return wifi_deinit_internal(); +} + static void esp_wifi_config_info(void) { #ifdef CONFIG_ESP_WIFI_RX_BA_WIN @@ -216,21 +222,44 @@ static void esp_wifi_config_info(void) #endif } -esp_err_t esp_wifi_init(const wifi_init_config_t *config) +#if CONFIG_SPIRAM +static esp_err_t esp_wifi_psram_check(const wifi_init_config_t *config) { - if ((config->feature_caps & CONFIG_FEATURE_CACHE_TX_BUF_BIT) && (WIFI_CACHE_TX_BUFFER_NUM == 0)) - { +#if CONFIG_SPIRAM_IGNORE_NOTFOUND + if (!esp_psram_is_initialized()) { + if (config->feature_caps & CONFIG_FEATURE_CACHE_TX_BUF_BIT) { + ESP_LOGW(TAG, "WiFi cache TX buffers should be disabled when initialize SPIRAM failed"); + } + if (config->tx_buf_type == 0) { + ESP_LOGW(TAG, "TX buffers type should be changed from static to dynamic when initialize SPIRAM failed"); + } +#ifdef CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP + ESP_LOGW(TAG, "WiFi/LWIP prefer SPIRAM should be disabled when initialize SPIRAM failed"); +#endif + if (config->amsdu_tx_enable) { + ESP_LOGW(TAG, "WiFi AMSDU TX should be disabled when initialize SPIRAM failed"); + } + } +#endif + if ((config->feature_caps & CONFIG_FEATURE_CACHE_TX_BUF_BIT) && (WIFI_CACHE_TX_BUFFER_NUM == 0)) { ESP_LOGE(TAG, "Number of WiFi cache TX buffers should not equal 0 when enable SPIRAM"); return ESP_ERR_NOT_SUPPORTED; } - esp_wifi_power_domain_on(); -#ifdef CONFIG_PM_ENABLE - if (s_wifi_modem_sleep_lock == NULL) { - esp_err_t err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "wifi", - &s_wifi_modem_sleep_lock); - if (err != ESP_OK) { - return err; - } + return ESP_OK; +} +#endif + +esp_err_t esp_wifi_init(const wifi_init_config_t *config) +{ + if (s_wifi_inited) { + return ESP_OK; + } + + esp_err_t result = ESP_OK; +#ifdef CONFIG_SPIRAM + result = esp_wifi_psram_check(config); + if (result != ESP_OK) { + return result; } #endif @@ -288,7 +317,8 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config) coex_init(); #endif esp_wifi_set_log_level(); - esp_err_t result = esp_wifi_init_internal(config); + esp_wifi_power_domain_on(); + result = esp_wifi_init_internal(config); if (result == ESP_OK) { #if CONFIG_MAC_BB_PD esp_mac_bb_pd_mem_init(); @@ -305,16 +335,24 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config) s_wifi_mac_time_update_cb = esp_wifi_internal_update_mac_time; #endif +#ifdef CONFIG_PM_ENABLE + if (s_wifi_modem_sleep_lock == NULL) { + result = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "wifi", + &s_wifi_modem_sleep_lock); + if (result != ESP_OK) { + ESP_LOGE(TAG, "Failed to create pm lock (0x%x)", result); + goto _deinit; + } + } +#endif + result = esp_supplicant_init(); if (result != ESP_OK) { ESP_LOGE(TAG, "Failed to init supplicant (0x%x)", result); - esp_err_t deinit_ret = esp_wifi_deinit(); - if (deinit_ret != ESP_OK) { - ESP_LOGE(TAG, "Failed to deinit Wi-Fi (0x%x)", deinit_ret); - } - - return result; + goto _deinit; } + } else { + goto _deinit; } #if CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT wifi_beacon_monitor_config_t monitor_config = WIFI_BEACON_MONITOR_CONFIG_DEFAULT(true); @@ -328,6 +366,17 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config) esp_nan_app_init(); #endif + s_wifi_inited = true; + + return result; + +_deinit: + ; + esp_err_t deinit_ret = wifi_deinit_internal(); + if (deinit_ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to deinit Wi-Fi (0x%x)", deinit_ret); + } + return result; } diff --git a/components/esp_wifi/test_apps/wifi_connect/main/test_wifi_conn.c b/components/esp_wifi/test_apps/wifi_connect/main/test_wifi_conn.c index d65d4bc75f8..9608f122cbe 100644 --- a/components/esp_wifi/test_apps/wifi_connect/main/test_wifi_conn.c +++ b/components/esp_wifi/test_apps/wifi_connect/main/test_wifi_conn.c @@ -72,6 +72,8 @@ static void wifi_event_handler(void* arg, esp_event_base_t event_base, break; case WIFI_EVENT_STA_DISCONNECTED: ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); + wifi_event_sta_disconnected_t *event = (wifi_event_sta_disconnected_t *)event_data; + ESP_LOGI(TAG, "disconnect reason: %u", event->reason); if (! (EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT & wifi_event_handler_flag) ) { TEST_ESP_OK(esp_wifi_connect()); } @@ -279,6 +281,7 @@ static void esp_wifi_connect_first_time(void) memset(&w_config, 0, sizeof(w_config)); memcpy(w_config.sta.ssid, TEST_DEFAULT_SSID, strlen(TEST_DEFAULT_SSID)); memcpy(w_config.sta.password, TEST_DEFAULT_PWD, strlen(TEST_DEFAULT_PWD)); + w_config.sta.channel = 1; wifi_event_handler_flag |= EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT; @@ -307,7 +310,7 @@ static void test_wifi_connect_before_connected_phase(void) esp_wifi_connect_first_time(); // connect before connected - vTaskDelay(800/portTICK_PERIOD_MS); + vTaskDelay(730/portTICK_PERIOD_MS); ESP_LOGI(TAG, "connect when first connect after scan before connected"); TEST_ESP_ERR(ESP_ERR_WIFI_CONN, esp_wifi_connect()); wifi_event_handler_flag |= EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT; diff --git a/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py b/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py index b53cf631f7b..1604e790173 100644 --- a/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py +++ b/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Unlicense OR CC0-1.0 import pytest -from idf_unity_tester import CaseTester +from pytest_embedded_idf.unity_tester import CaseTester @pytest.mark.esp32 diff --git a/components/esp_wifi/wifi_apps/include/esp_nan.h b/components/esp_wifi/wifi_apps/include/esp_nan.h index ae0ae463522..17c369f2425 100644 --- a/components/esp_wifi/wifi_apps/include/esp_nan.h +++ b/components/esp_wifi/wifi_apps/include/esp_nan.h @@ -128,7 +128,7 @@ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req); /** * @brief Respond to a NAN Datapath request with Accept or Reject * - * @attention This API should be called if ndp_auto_accept is not set True by the Publisher and + * @attention This API should be called if ndp_resp_needed is set True by the Publisher and * a WIFI_EVENT_NDP_INDICATION event is received due to an incoming NDP request. * * @param resp NAN Datapath Response parameters. diff --git a/components/esp_wifi/wifi_apps/src/nan_app.c b/components/esp_wifi/wifi_apps/src/nan_app.c index cc4025cd609..8e52bc7de74 100644 --- a/components/esp_wifi/wifi_apps/src/nan_app.c +++ b/components/esp_wifi/wifi_apps/src/nan_app.c @@ -40,6 +40,10 @@ static const char *TAG = "nan_app"; static EventGroupHandle_t nan_event_group; static bool s_app_default_handlers_set = false; static uint8_t null_mac[MACADDR_LEN] = {0}; +static void *s_nan_data_lock = NULL; + +#define NAN_DATA_LOCK() os_mutex_lock(s_nan_data_lock) +#define NAN_DATA_UNLOCK() os_mutex_unlock(s_nan_data_lock) struct peer_svc_info { SLIST_ENTRY(peer_svc_info) next; @@ -182,16 +186,6 @@ static struct peer_svc_info *nan_find_peer_svc(uint8_t own_svc_id, uint8_t peer_ return p_peer_svc; } -static bool nan_update_peer_svc(uint8_t own_svc_id, uint8_t peer_svc_id, uint8_t peer_nmi[]) -{ - struct peer_svc_info *peer_info = nan_find_peer_svc(own_svc_id, 0, peer_nmi); - if (peer_info) { - peer_info->svc_id = peer_svc_id; - return true; - } - return false; -} - static bool nan_record_peer_svc(uint8_t own_svc_id, uint8_t peer_svc_id, uint8_t peer_nmi[]) { struct own_svc_info *p_own_svc; @@ -216,10 +210,23 @@ static bool nan_record_peer_svc(uint8_t own_svc_id, uint8_t peer_svc_id, uint8_t SLIST_INSERT_HEAD(&(p_own_svc->peer_list), p_peer_svc, next); p_own_svc->num_peer_records++; } else { - struct peer_svc_info *temp; - temp = SLIST_FIRST(&(p_own_svc->peer_list)); - SLIST_REMOVE_HEAD(&(p_own_svc->peer_list), next); - os_free(temp); + /* Remove the oldest peer service entry */ + struct peer_svc_info *prev_ele = NULL, *cur_ele = NULL; + + SLIST_FOREACH(cur_ele, &(p_own_svc->peer_list), next) { + if (SLIST_NEXT(cur_ele, next) == NULL) { + if (SLIST_FIRST(&(p_own_svc->peer_list)) == cur_ele) { + SLIST_REMOVE_HEAD(&(p_own_svc->peer_list), next); + } else { + SLIST_REMOVE_AFTER(prev_ele, next); + } + break; + } + prev_ele = cur_ele; + } + /* Insert new peer service entry */ + SLIST_INSERT_HEAD(&(p_own_svc->peer_list), p_peer_svc, next); + os_free(cur_ele); } return true; @@ -362,6 +369,19 @@ static bool nan_is_datapath_active(void) return false; } +static void nan_update_peer_svc(uint8_t own_svc_id, uint8_t peer_svc_id, uint8_t peer_nmi[]) +{ + struct peer_svc_info *peer_info = nan_find_peer_svc(own_svc_id, 0, peer_nmi); + if (peer_info) { + peer_info->svc_id = peer_svc_id; + } + + struct ndl_info *ndl = nan_find_ndl(0, peer_nmi); + if (ndl) { + ndl->publisher_id = peer_svc_id; + } +} + static void nan_fill_params_from_event(void *evt_data, uint8_t event) { switch (event) { @@ -401,10 +421,9 @@ static void nan_fill_params_from_event(void *evt_data, uint8_t event) wifi_event_nan_svc_match_t *evt = (wifi_event_nan_svc_match_t *)evt_data; if (evt->update_pub_id) { - if (nan_update_peer_svc(evt->subscribe_id, evt->publish_id, evt->pub_if_mac)) { - break; - } + nan_update_peer_svc(evt->subscribe_id, evt->publish_id, evt->pub_if_mac); } + if (!nan_find_peer_svc(evt->subscribe_id, evt->publish_id, evt->pub_if_mac)) { nan_record_peer_svc(evt->subscribe_id, evt->publish_id, evt->pub_if_mac); } @@ -424,7 +443,10 @@ static void nan_app_action_service_match(void *arg, esp_event_base_t event_base, ESP_LOGI(TAG, "Service matched with "MACSTR" [Peer Publish id - %d]", MAC2STR(evt->pub_if_mac), evt->publish_id); + + NAN_DATA_LOCK(); nan_fill_params_from_event(evt, WIFI_EVENT_NAN_SVC_MATCH); + NAN_DATA_UNLOCK(); } static void nan_app_action_replied(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) @@ -436,7 +458,10 @@ static void nan_app_action_replied(void *arg, esp_event_base_t event_base, int32 ESP_LOGD(TAG, "Sent Publish to Peer "MACSTR" [Peer Subscribe id - %d]", MAC2STR(evt->sub_if_mac), evt->subscribe_id); + + NAN_DATA_LOCK(); nan_fill_params_from_event(evt, WIFI_EVENT_NAN_REPLIED); + NAN_DATA_UNLOCK(); } static void nan_app_action_receive(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) @@ -448,7 +473,10 @@ static void nan_app_action_receive(void *arg, esp_event_base_t event_base, int32 ESP_LOGI(TAG, "Received message '%s' from Peer "MACSTR" [Peer Service id - %d]", evt->peer_svc_info, MAC2STR(evt->peer_if_mac), evt->peer_inst_id); + + NAN_DATA_LOCK(); nan_fill_params_from_event(evt, WIFI_EVENT_NAN_RECEIVE); + NAN_DATA_UNLOCK(); } static void nan_app_action_ndp_indication(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) @@ -457,15 +485,17 @@ static void nan_app_action_ndp_indication(void *arg, esp_event_base_t event_base return; } wifi_event_ndp_indication_t *evt = (wifi_event_ndp_indication_t *)data; + + NAN_DATA_LOCK(); struct own_svc_info *p_own_svc = nan_find_own_svc(evt->publish_id); if (!p_own_svc) { ESP_LOGE(TAG, "No Publish found with id %d", evt->publish_id); - return; + goto done; } if (ndl_limit_reached()) { ESP_LOGE(TAG, "NDP limit reached"); - return; + goto done; } nan_fill_params_from_event(evt, WIFI_EVENT_NDP_INDICATION); @@ -481,6 +511,9 @@ static void nan_app_action_ndp_indication(void *arg, esp_event_base_t event_base esp_nan_internal_datapath_resp(&ndp_resp); } + +done: + NAN_DATA_UNLOCK(); } static void nan_app_action_ndp_confirm(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) @@ -489,29 +522,31 @@ static void nan_app_action_ndp_confirm(void *arg, esp_event_base_t event_base, i return; } wifi_event_ndp_confirm_t *evt = (wifi_event_ndp_confirm_t *)data; + + NAN_DATA_LOCK(); wifi_netif_driver_t driver = esp_netif_get_io_driver(s_nan_ctx.nan_netif); ip_addr_t target_addr = {0}; if (!s_nan_ctx.nan_netif) { ESP_LOGE(TAG, "%s: NAN netif is NULL", __func__); - return; + goto done; } if (nan_find_ndl(evt->ndp_id, NULL) == NULL) { /* As ndl isn't found, timeout has occured for NDP response and datapath request is rejected */ - return; + goto done; } if (evt->status == NDP_STATUS_REJECTED) { ESP_LOGE(TAG, "NDP request to Peer "MACSTR" rejected [NDP ID - %d]", MAC2STR(evt->peer_nmi), evt->ndp_id); nan_reset_ndl(evt->ndp_id, false); os_event_group_set_bits(nan_event_group, NDP_REJECTED); - return; + goto done; } /* If interface not ready when started, rxcb to be registered on connection */ if (esp_wifi_register_if_rxcb(driver, esp_netif_receive, s_nan_ctx.nan_netif) != ESP_OK) { ESP_LOGE(TAG, "%s: esp_wifi_register_if_rxcb failed", __func__); - return; + goto done; } nan_fill_params_from_event(evt, WIFI_EVENT_NDP_CONFIRM); @@ -519,11 +554,17 @@ static void nan_app_action_ndp_confirm(void *arg, esp_event_base_t event_base, i esp_netif_action_connected(s_nan_ctx.nan_netif, event_base, event_id, data); esp_netif_create_ip6_linklocal(s_nan_ctx.nan_netif); + NAN_DATA_UNLOCK(); esp_wifi_nan_get_ipv6_linklocal_from_mac(&target_addr.u_addr.ip6, evt->peer_ndi); target_addr.type = IPADDR_TYPE_V6; ESP_LOGI(TAG, "NDP confirmed with Peer "MACSTR" [NDP ID - %d, Peer IPv6 - %s]", MAC2STR(evt->peer_nmi), evt->ndp_id, inet6_ntoa(*ip_2_ip6(&target_addr))); os_event_group_set_bits(nan_event_group, NDP_ACCEPTED); + return; + +done: + NAN_DATA_UNLOCK(); + return; } static void nan_app_action_ndp_terminated(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) @@ -533,6 +574,7 @@ static void nan_app_action_ndp_terminated(void *arg, esp_event_base_t event_base } wifi_event_ndp_terminated_t *evt = (wifi_event_ndp_terminated_t *)data; + NAN_DATA_LOCK(); if (s_nan_ctx.nan_netif && !nan_is_datapath_active()) { esp_netif_action_disconnected(s_nan_ctx.nan_netif, event_base, event_id, data); } @@ -540,6 +582,7 @@ static void nan_app_action_ndp_terminated(void *arg, esp_event_base_t event_base nan_reset_ndl(evt->ndp_id, false); s_nan_ctx.event &= ~(NDP_INDICATION); + NAN_DATA_UNLOCK(); os_event_group_set_bits(nan_event_group, NDP_TERMINATED); } @@ -560,11 +603,13 @@ static void nan_app_action_got_ipv6(void *arg, esp_event_base_t event_base, int3 } ip_event_got_ip6_t *event = (ip_event_got_ip6_t *)data; + NAN_DATA_LOCK(); if (event->esp_netif == s_nan_ctx.nan_netif) { esp_ip6_addr_type_t ipv6_type = esp_netif_ip6_get_addr_type(&event->ip6_info.ip); ESP_LOGD(TAG, "NAN Data Interface ready [IPv6 - "IPV6STR", type - %s]", IPV62STR(event->ip6_info.ip), s_ipv6_addr_types[ipv6_type]); } + NAN_DATA_UNLOCK(); } static esp_err_t nan_clear_app_default_handlers(void) @@ -618,21 +663,32 @@ static esp_err_t nan_set_app_default_handlers(void) return ESP_FAIL; } -void esp_nan_app_init(void) +void esp_nan_app_deinit(void) { if (nan_event_group) { os_event_group_delete(nan_event_group); nan_event_group = NULL; } - nan_event_group = os_event_group_create(); + + if (s_nan_data_lock) { + os_semphr_delete(s_nan_data_lock); + s_nan_data_lock = NULL; + } } -void esp_nan_app_deinit(void) +void esp_nan_app_init(void) { if (nan_event_group) { os_event_group_delete(nan_event_group); nan_event_group = NULL; } + nan_event_group = os_event_group_create(); + + s_nan_data_lock = os_recursive_mutex_create(); + if (!s_nan_data_lock) { + ESP_LOGE(TAG, "Failed to create NAN data lock"); + esp_nan_app_deinit(); + } } void esp_nan_action_start(esp_netif_t *nan_netif) @@ -642,9 +698,11 @@ void esp_nan_action_start(esp_netif_t *nan_netif) return; } + NAN_DATA_LOCK(); s_nan_ctx.nan_netif = nan_netif; - s_nan_ctx.state = NAN_STARTED_BIT; + NAN_DATA_UNLOCK(); + ESP_LOGI(TAG, "NAN Discovery started."); os_event_group_set_bits(nan_event_group, NAN_STARTED_BIT); } @@ -653,6 +711,7 @@ void esp_nan_action_stop(void) { nan_clear_app_default_handlers(); + NAN_DATA_LOCK(); if (nan_is_datapath_active()) { nan_reset_ndl(0, true); esp_wifi_internal_reg_rxcb(WIFI_IF_NAN, NULL); @@ -661,6 +720,8 @@ void esp_nan_action_stop(void) nan_reset_service(0, true); s_nan_ctx.state &= ~NAN_STARTED_BIT; s_nan_ctx.state |= NAN_STOPPED_BIT; + NAN_DATA_UNLOCK(); + os_event_group_set_bits(nan_event_group, NAN_STOPPED_BIT); } @@ -678,10 +739,19 @@ esp_err_t esp_wifi_nan_start(const wifi_nan_config_t *nan_cfg) ESP_LOGE(TAG, "Unable to get mode"); return ret; } + + if (!s_nan_data_lock) { + ESP_LOGE(TAG, "NAN Data lock doesn't exist"); + return ESP_FAIL; + } + + NAN_DATA_LOCK(); if (s_nan_ctx.state & NAN_STARTED_BIT) { ESP_LOGI(TAG, "NAN already started"); + NAN_DATA_UNLOCK(); return ESP_OK; } + NAN_DATA_UNLOCK(); ESP_RETURN_ON_ERROR(esp_wifi_set_mode(WIFI_MODE_NAN), TAG, "Set mode NAN failed"); @@ -690,13 +760,17 @@ esp_err_t esp_wifi_nan_start(const wifi_nan_config_t *nan_cfg) if (esp_wifi_start() != ESP_OK) { ESP_LOGE(TAG, "Starting wifi failed"); + NAN_DATA_LOCK(); s_nan_ctx.nan_netif = NULL; + NAN_DATA_UNLOCK(); return ESP_FAIL; } EventBits_t bits = os_event_group_wait_bits(nan_event_group, NAN_STARTED_BIT, pdFALSE, pdFALSE, portMAX_DELAY); if (!(bits & NAN_STARTED_BIT)) { + NAN_DATA_LOCK(); s_nan_ctx.nan_netif = NULL; + NAN_DATA_UNLOCK(); return ESP_FAIL; } return ESP_OK; @@ -704,8 +778,10 @@ esp_err_t esp_wifi_nan_start(const wifi_nan_config_t *nan_cfg) esp_err_t esp_wifi_nan_stop(void) { + NAN_DATA_LOCK(); if (!(s_nan_ctx.state & NAN_STARTED_BIT)) { ESP_LOGE(TAG, "NAN isn't started"); + NAN_DATA_UNLOCK(); return ESP_FAIL; } @@ -721,11 +797,14 @@ esp_err_t esp_wifi_nan_stop(void) } nan_reset_ndl(0, true); + NAN_DATA_UNLOCK(); os_event_group_clear_bits(nan_event_group, NDP_TERMINATED); os_event_group_wait_bits(nan_event_group, NDP_TERMINATED, pdFALSE, pdFALSE, portMAX_DELAY); os_event_group_clear_bits(nan_event_group, NDP_TERMINATED); /* Wait for 1 NAN DW interval (512 TU's ~= 524 mSec) for successful termination */ g_wifi_osi_funcs._task_delay(NAN_DW_INTVL_MS/portTICK_PERIOD_MS); + } else { + NAN_DATA_UNLOCK(); } ESP_RETURN_ON_ERROR(esp_wifi_stop(), TAG, "Stopping NAN failed"); @@ -735,7 +814,9 @@ esp_err_t esp_wifi_nan_stop(void) return ESP_FAIL; } + NAN_DATA_LOCK(); memset(&s_nan_ctx, 0, sizeof(nan_ctx_t)); + NAN_DATA_UNLOCK(); return ESP_OK; } @@ -743,78 +824,94 @@ uint8_t esp_wifi_nan_publish_service(const wifi_nan_publish_cfg_t *publish_cfg, { uint8_t pub_id; + NAN_DATA_LOCK(); if (!(s_nan_ctx.state & NAN_STARTED_BIT)) { ESP_LOGE(TAG, "NAN not started!"); - return 0; + goto fail; } if (nan_services_limit_reached()) { ESP_LOGE(TAG, "Maximum services limit reached"); - return 0; + goto fail; } if (nan_find_own_svc_by_name(publish_cfg->service_name)) { - ESP_LOGE(TAG, "Service name already used!"); - return 0; + ESP_LOGE(TAG, "Service name %s already used!", publish_cfg->service_name); + goto fail; } if (esp_nan_internal_publish_service(publish_cfg, &pub_id, false) != ESP_OK) { ESP_LOGE(TAG, "Failed to publish service '%s'", publish_cfg->service_name); - return 0; + goto fail; } ESP_LOGI(TAG, "Started Publishing %s [Service ID - %u]", publish_cfg->service_name, pub_id); nan_record_own_svc(pub_id, ESP_NAN_PUBLISH, publish_cfg->service_name, ndp_resp_needed); + NAN_DATA_UNLOCK(); return pub_id; +fail: + NAN_DATA_UNLOCK(); + return 0; } uint8_t esp_wifi_nan_subscribe_service(const wifi_nan_subscribe_cfg_t *subscribe_cfg) { uint8_t sub_id; + NAN_DATA_LOCK(); if (!(s_nan_ctx.state & NAN_STARTED_BIT)) { ESP_LOGE(TAG, "NAN not started!"); - return 0; + goto fail; } if (nan_services_limit_reached()) { ESP_LOGE(TAG, "Maximum services limit reached"); - return 0; + goto fail; } if (nan_find_own_svc_by_name(subscribe_cfg->service_name)) { ESP_LOGE(TAG, "Service name already used!"); - return 0; + goto fail; } if (esp_nan_internal_subscribe_service(subscribe_cfg, &sub_id, false) != ESP_OK) { ESP_LOGE(TAG, "Failed to subscribe to service '%s'", subscribe_cfg->service_name); - return 0; + goto fail; } ESP_LOGI(TAG, "Started Subscribing to %s [Service ID - %u]", subscribe_cfg->service_name, sub_id); nan_record_own_svc(sub_id, ESP_NAN_SUBSCRIBE, subscribe_cfg->service_name, false); + NAN_DATA_UNLOCK(); return sub_id; +fail: + NAN_DATA_UNLOCK(); + return 0; } esp_err_t esp_wifi_nan_send_message(wifi_nan_followup_params_t *fup_params) { struct peer_svc_info *p_peer_svc; + NAN_DATA_LOCK(); p_peer_svc = nan_find_peer_svc(fup_params->inst_id, fup_params->peer_inst_id, fup_params->peer_mac); if (!p_peer_svc) { ESP_LOGE(TAG, "Cannot send Follow-up, peer not found!"); + NAN_DATA_UNLOCK(); return ESP_FAIL; } if (!fup_params->inst_id) { fup_params->inst_id = p_peer_svc->own_svc_id; } + if (!fup_params->peer_inst_id) { + fup_params->peer_inst_id = p_peer_svc->svc_id; + } if (!MACADDR_EQUAL(fup_params->peer_mac, null_mac)) { MACADDR_COPY(fup_params->peer_mac, p_peer_svc->peer_nmi); } + NAN_DATA_UNLOCK(); if (esp_nan_internal_send_followup(fup_params) != ESP_OK) { ESP_LOGE(TAG, "Failed to send Follow-up message!"); return ESP_FAIL; @@ -826,18 +923,19 @@ esp_err_t esp_wifi_nan_send_message(wifi_nan_followup_params_t *fup_params) esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id) { + NAN_DATA_LOCK(); struct own_svc_info *p_own_svc = nan_find_own_svc(service_id); if (!p_own_svc) { ESP_LOGE(TAG, "Cannot find own service with id %d!", service_id); - return ESP_FAIL; + goto fail; } if (p_own_svc->type == ESP_NAN_PUBLISH) { if (esp_nan_internal_publish_service(NULL, &service_id, true) == ESP_OK) { nan_reset_service(service_id, false); ESP_LOGI(TAG, "Cancelled Publish with Service ID %d", service_id); - return ESP_OK; + goto done; } } @@ -845,32 +943,40 @@ esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id) if (esp_nan_internal_subscribe_service(NULL, &service_id, true) == ESP_OK) { nan_reset_service(service_id, false); ESP_LOGI(TAG, "Cancelled Subscribe with Service ID %d", service_id); - return ESP_OK; + goto done; } } +fail: + NAN_DATA_UNLOCK(); return ESP_FAIL; + +done: + NAN_DATA_UNLOCK(); + return ESP_OK; } uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req) { uint8_t ndp_id = 0; + + NAN_DATA_LOCK(); struct peer_svc_info *p_peer_svc = nan_find_peer_svc(0, req->pub_id, req->peer_mac); if (!p_peer_svc) { ESP_LOGE(TAG, "Cannot send NDP Req, peer not found!"); - return 0; + goto fail; } if (req->pub_id == 0) req->pub_id = p_peer_svc->svc_id; if (p_peer_svc->type != ESP_NAN_PUBLISH) { ESP_LOGE(TAG, "Only subscriber can send an NDP Req to a Publisher"); - return 0; + goto fail; } if (ndl_limit_reached()) { ESP_LOGE(TAG, "Cannot establish new datapath, limit reached!"); - return 0; + goto fail; } if (!MACADDR_EQUAL(req->peer_mac, null_mac)) { @@ -879,9 +985,12 @@ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req) if (esp_nan_internal_datapath_req(req, &ndp_id) != ESP_OK) { ESP_LOGE(TAG, "Failed to initiate NDP req"); - return 0; + goto fail; } + nan_record_new_ndl(ndp_id, req->pub_id, req->peer_mac, ESP_WIFI_NDP_ROLE_INITIATOR); + NAN_DATA_UNLOCK(); + ESP_LOGD(TAG, "Requested NDP with "MACSTR" [NDP ID - %d]", MAC2STR(req->peer_mac), ndp_id); EventBits_t bits = os_event_group_wait_bits(nan_event_group, NDP_ACCEPTED | NDP_REJECTED, pdFALSE, pdFALSE, pdMS_TO_TICKS(NAN_NDP_RESP_TIMEOUT)); @@ -892,22 +1001,28 @@ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req) os_event_group_clear_bits(nan_event_group, NDP_REJECTED); return 0; } else { + NAN_DATA_LOCK(); nan_reset_ndl(ndp_id, false); + NAN_DATA_UNLOCK(); return 0; } +fail: + NAN_DATA_UNLOCK(); + return 0; } esp_err_t esp_wifi_nan_datapath_resp(wifi_nan_datapath_resp_t *resp) { + NAN_DATA_LOCK(); struct ndl_info *ndl = nan_find_ndl(resp->ndp_id, NULL); if (!ndl) { ESP_LOGE(TAG, "No NDL with ndp id %d", resp->ndp_id); - return ESP_FAIL; + goto fail; } if (!(s_nan_ctx.event & NDP_INDICATION)) { //INDICATION of specific peer ESP_LOGE(TAG, "Need NDP Indication before NDP Response can be sent"); - return ESP_FAIL; + goto fail; } if (!MACADDR_EQUAL(resp->peer_mac, null_mac)) { @@ -916,9 +1031,12 @@ esp_err_t esp_wifi_nan_datapath_resp(wifi_nan_datapath_resp_t *resp) if (esp_nan_internal_datapath_resp(resp) == ESP_OK) { s_nan_ctx.event &= ~NDP_INDICATION; + NAN_DATA_UNLOCK(); return ESP_OK; } +fail: + NAN_DATA_UNLOCK(); return ESP_FAIL; } @@ -926,20 +1044,25 @@ esp_err_t esp_wifi_nan_datapath_end(wifi_nan_datapath_end_req_t *req) { struct ndl_info *ndl = NULL; + NAN_DATA_LOCK(); if (!nan_is_datapath_active()) { ESP_LOGE(TAG, "No Datapath active"); + NAN_DATA_UNLOCK(); return ESP_FAIL; } ndl = nan_find_ndl(req->ndp_id, NULL); if (!ndl) { ESP_LOGE(TAG, "No NDL with ndp id %d", req->ndp_id); + NAN_DATA_UNLOCK(); return ESP_FAIL; } + if (!MACADDR_EQUAL(req->peer_mac, null_mac)) { MACADDR_COPY(req->peer_mac, ndl->peer_nmi); } + NAN_DATA_UNLOCK(); if (esp_nan_internal_datapath_end(req) == ESP_OK) { return ESP_OK; } @@ -956,25 +1079,30 @@ esp_err_t esp_wifi_nan_get_own_svc_info(uint8_t *own_svc_id, char *svc_name, int return ESP_FAIL; } + NAN_DATA_LOCK(); if (*own_svc_id == 0) { own_svc = nan_find_own_svc_by_name(svc_name); if (!own_svc) { ESP_LOGE(TAG, "No record found for given service name %s", svc_name); - return ESP_FAIL; + goto fail; } *own_svc_id = own_svc->svc_id; } else { own_svc = nan_find_own_svc(*own_svc_id); if (!own_svc) { ESP_LOGE(TAG, "No record found for given service ID %d", *own_svc_id); - return ESP_FAIL; + goto fail; } strlcpy(svc_name, own_svc->svc_name, ESP_WIFI_MAX_SVC_NAME_LEN); } *num_peer_records = own_svc->num_peer_records; - + NAN_DATA_UNLOCK(); return ESP_OK; + +fail: + NAN_DATA_UNLOCK(); + return ESP_FAIL; } esp_err_t esp_wifi_nan_get_peer_records(int *num_peer_records, uint8_t own_svc_id, struct nan_peer_record *peer_record) @@ -996,6 +1124,7 @@ esp_err_t esp_wifi_nan_get_peer_records(int *num_peer_records, uint8_t own_svc_i return ESP_FAIL; } + NAN_DATA_LOCK(); own_record = nan_find_own_svc(own_svc_id); if (own_record) { SLIST_FOREACH(temp, &(own_record->peer_list), next) { @@ -1031,10 +1160,13 @@ esp_err_t esp_wifi_nan_get_peer_records(int *num_peer_records, uint8_t own_svc_i if (*num_peer_records > peer_num) { *num_peer_records = peer_num; } + + NAN_DATA_UNLOCK(); return ESP_OK; } else { *num_peer_records = 0; ESP_LOGD(TAG, "No record found for own service id %d", own_svc_id); + NAN_DATA_UNLOCK(); return ESP_FAIL; } } @@ -1049,10 +1181,12 @@ esp_err_t esp_wifi_nan_get_peer_info(char *svc_name, uint8_t *peer_mac, struct n return ESP_FAIL; } + NAN_DATA_LOCK(); if (svc_name) { struct own_svc_info *own_svc = nan_find_own_svc_by_name(svc_name); if (!own_svc) { ESP_LOGE(TAG, "No record found for given service name %s", svc_name); + NAN_DATA_UNLOCK(); return ESP_FAIL; } own_svc_id = own_svc->svc_id; @@ -1073,9 +1207,11 @@ esp_err_t esp_wifi_nan_get_peer_info(char *svc_name, uint8_t *peer_mac, struct n peer_info->ndp_id = 0; MACADDR_COPY(peer_info->peer_ndi, null_mac); } + NAN_DATA_UNLOCK(); return ESP_OK; } else { ESP_LOGD(TAG, "No record found for Peer "MACSTR, MAC2STR(peer_mac)); + NAN_DATA_UNLOCK(); return ESP_FAIL; } } diff --git a/components/espcoredump/include_core_dump/esp_core_dump_port.h b/components/espcoredump/include_core_dump/esp_core_dump_port.h index 7f342972bfa..4ef51d46462 100644 --- a/components/espcoredump/include_core_dump/esp_core_dump_port.h +++ b/components/espcoredump/include_core_dump/esp_core_dump_port.h @@ -40,8 +40,10 @@ uint16_t esp_core_dump_get_arch_id(void); * * @param info Pointer to the panic information. It contains the execution * frame. + * @param isr_context A flag indicating whether the crash happened within an ISR context. + * Set to 1 if the crash occurred in an ISR, and 0 otherwise. */ -void esp_core_dump_port_init(panic_info_t *info); +void esp_core_dump_port_init(panic_info_t *info, bool isr_context); /** * @brief Reset fake stacks allocator, if any. diff --git a/components/espcoredump/src/core_dump_common.c b/components/espcoredump/src/core_dump_common.c index 70f8f77f6d3..c9d9e1cc9cb 100644 --- a/components/espcoredump/src/core_dump_common.c +++ b/components/espcoredump/src/core_dump_common.c @@ -151,8 +151,10 @@ inline void esp_core_dump_write(panic_info_t *info, core_dump_write_config_t *wr esp_err_t err = ESP_ERR_NOT_SUPPORTED; s_exc_frame = (void*) info->frame; + bool isr_context = esp_core_dump_in_isr_context(); + esp_core_dump_setup_stack(); - esp_core_dump_port_init(info); + esp_core_dump_port_init(info, isr_context); #if CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN err = esp_core_dump_write_binary(write_cfg); #elif CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF @@ -319,7 +321,7 @@ inline bool esp_core_dump_in_isr_context(void) inline core_dump_task_handle_t esp_core_dump_get_current_task_handle() { - return (core_dump_task_handle_t) xTaskGetCurrentTaskHandleForCPU(xPortGetCoreID()); + return (core_dump_task_handle_t) xTaskGetCurrentTaskHandleForCore(xPortGetCoreID()); } #endif diff --git a/components/espcoredump/src/core_dump_elf.c b/components/espcoredump/src/core_dump_elf.c index cd93d26b210..9fdcf9a6aea 100644 --- a/components/espcoredump/src/core_dump_elf.c +++ b/components/espcoredump/src/core_dump_elf.c @@ -14,6 +14,7 @@ #include "esp_core_dump_port_impl.h" #include "esp_core_dump_common.h" #include "hal/efuse_hal.h" +#include "esp_task_wdt.h" #ifdef CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF #include // for the MIN macro @@ -35,6 +36,8 @@ #define ELF_NOTE_NAME_MAX_SIZE 32 #define ELF_APP_SHA256_SIZE 66 +#define ELF_ESP_CORE_DUMP_PANIC_DETAILS_NOTE_NAME "ESP_PANIC_DETAILS" + #define ELF_CHECK_ERR(a, ret_val, str, ...) \ if (!(a)) { \ ESP_COREDUMP_LOGE("%s(%u): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ @@ -82,18 +85,23 @@ typedef struct _core_dump_elf_t uint32_t elf_next_data_offset; uint16_t segs_count; core_dump_write_config_t * write_cfg; + uint32_t note_data_size; /* can be used where static storage needed */ } core_dump_elf_t; -// Represents lightweight implementation to save core dump data into ELF formatted binary +typedef struct { + core_dump_elf_t *self; + uint32_t total_size; + bool size_only; +} core_dump_elf_opaque_t; -#define ALIGN(b, var) var = align(b, var) +// Represents lightweight implementation to save core dump data into ELF formatted binary #if CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF -static inline uint32_t align(uint32_t width, uint32_t in) -{ - return (in + (width - 1)) & -width; -} +#ifdef ALIGN_UP +#undef ALIGN_UP +#endif +#define ALIGN_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) // Builds elf header and check all data offsets static int elf_write_file_header(core_dump_elf_t *self, uint32_t seg_count) @@ -158,13 +166,11 @@ static int elf_add_segment(core_dump_elf_t *self, { esp_err_t err = ESP_FAIL; elf_phdr seg_hdr = { 0 }; - int data_len = data_sz; + int data_len = ALIGN_UP(data_sz, 4); ELF_CHECK_ERR((data != NULL), ELF_PROC_ERR_OTHER, "Invalid data for segment."); - ALIGN(4, data_len); - if (self->elf_stage == ELF_STAGE_CALC_SPACE) { self->segs_count++; return data_len + sizeof(elf_phdr); @@ -193,6 +199,29 @@ static int elf_add_segment(core_dump_elf_t *self, return data_len; } +static int elf_write_note_header(core_dump_elf_t *self, + const char* name, uint32_t name_len, uint32_t data_sz, uint32_t type) +{ + // temporary aligned buffer for note name + static char name_buffer[ELF_NOTE_NAME_MAX_SIZE] = { 0 }; + elf_note note_hdr = { 0 }; + + memcpy((void*)name_buffer, (void*)name, name_len); + note_hdr.n_namesz = name_len; + note_hdr.n_descsz = data_sz; + note_hdr.n_type = type; + // write note header + esp_err_t err = self->write_cfg->write(self->write_cfg->priv, ¬e_hdr, sizeof(note_hdr)); + ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, + "Write ELF note header failure (%d)", err); + // write note name + err = self->write_cfg->write(self->write_cfg->priv, name_buffer, name_len); + ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, + "Write ELF note name failure (%d)", err); + + return err; +} + static int elf_write_note(core_dump_elf_t *self, const char* name, uint32_t type, @@ -200,38 +229,34 @@ static int elf_write_note(core_dump_elf_t *self, uint32_t data_sz) { esp_err_t err = ESP_FAIL; - // temporary buffer for note name - static char name_buffer[ELF_NOTE_NAME_MAX_SIZE] = { 0 }; - elf_note note_hdr = { 0 }; - uint32_t name_len = strlen(name) + 1; // get name length including terminator - uint32_t data_len = data_sz; + uint32_t name_len = ALIGN_UP(strlen(name) + 1, 4); // get name length including terminator + uint32_t data_len = ALIGN_UP(data_sz, 4); - ELF_CHECK_ERR(data, ELF_PROC_ERR_OTHER, - "Invalid data pointer %x.", (uint32_t)data); ELF_CHECK_ERR((name_len <= ELF_NOTE_NAME_MAX_SIZE), 0, "Segment note name is too long %d.", name_len); - ALIGN(4, data_len); - ALIGN(4, name_len); - uint32_t note_size = name_len + data_len + sizeof(elf_note); - ALIGN(4, note_size); + uint32_t note_size = ALIGN_UP(name_len + data_len + sizeof(elf_note), 4); // write segment data during second pass if (self->elf_stage == ELF_STAGE_PLACE_DATA) { - memcpy((void*)name_buffer, (void*)name, name_len); - note_hdr.n_namesz = name_len; - note_hdr.n_descsz = data_sz; - note_hdr.n_type = type; - // write note header - err = self->write_cfg->write(self->write_cfg->priv, (void*)¬e_hdr, sizeof(note_hdr)); - ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, - "Write ELF note header failure (%d)", err); - // write note name - err = self->write_cfg->write(self->write_cfg->priv, (void*)name_buffer, name_len); - ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, - "Write ELF note name failure (%d)", err); - // write note data - err = self->write_cfg->write(self->write_cfg->priv, (void*)data, data_len); + ELF_CHECK_ERR(data, ELF_PROC_ERR_OTHER, "Invalid data pointer %x.", (uint32_t)data); + err = elf_write_note_header(self, name, name_len, data_sz, type); + if (err != ESP_OK) { + return err; + } + + // note data must be aligned in memory. we write aligned byte structures and panic details in strings, + // which might not be aligned by default. Therefore, we need to verify alignment and add padding if necessary. + err = self->write_cfg->write(self->write_cfg->priv, data, data_sz); + if (err == ESP_OK) { + int pad_size = data_len - data_sz; + if (pad_size != 0) { + uint8_t pad_bytes[3] = {0}; + ESP_COREDUMP_LOG_PROCESS("Core dump note data needs %d bytes padding", pad_size); + err = self->write_cfg->write(self->write_cfg->priv, pad_bytes, pad_size); + } + } + ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, "Write ELF note data failure (%d)", err); ESP_COREDUMP_LOG_PROCESS("Add note size=%d, start_off=0x%x", @@ -495,6 +520,65 @@ static int elf_write_core_dump_user_data(core_dump_elf_t *self) return total_sz; } +#if CONFIG_ESP_TASK_WDT_EN +static void elf_write_core_dump_note_cb(void *opaque, const char *data) +{ + core_dump_elf_opaque_t *param = opaque; + core_dump_elf_t *self = param->self; + const size_t data_len = strlen(data); + + ESP_COREDUMP_LOG_PROCESS("Core dump note cb data_len:(%d)", data_len); + + param->total_size += data_len; + + if (!param->size_only) { + esp_err_t err = self->write_cfg->write(self->write_cfg->priv, (void *)data, data_len); + if (err != ESP_OK) { + param->total_size = 0; + } + } +} + +static int elf_add_wdt_panic_details(core_dump_elf_t *self) +{ + uint32_t name_len = ALIGN_UP(sizeof(ELF_ESP_CORE_DUMP_PANIC_DETAILS_NOTE_NAME), 4); + core_dump_elf_opaque_t param = { + .self = self, + .total_size = 0, + .size_only = false, + }; + + if (self->elf_stage == ELF_STAGE_CALC_SPACE) { + param.size_only = true; + esp_task_wdt_print_triggered_tasks(elf_write_core_dump_note_cb, ¶m, NULL); + ELF_CHECK_ERR((param.total_size > 0), ELF_PROC_ERR_OTHER, "wdt panic message len is zero!"); + self->note_data_size = param.total_size; + } else if (self->elf_stage == ELF_STAGE_PLACE_DATA) { + esp_err_t err = elf_write_note_header(self, + ELF_ESP_CORE_DUMP_PANIC_DETAILS_NOTE_NAME, + name_len, + self->note_data_size, + ELF_ESP_CORE_DUMP_PANIC_DETAILS_TYPE); + if (err != ESP_OK) { + return err; + } + + esp_task_wdt_print_triggered_tasks(elf_write_core_dump_note_cb, ¶m, NULL); + ELF_CHECK_ERR((param.total_size > 0), ELF_PROC_ERR_WRITE_FAIL, "Write ELF note data failure (%d)", err); + const uint32_t mod = self->note_data_size & 3; + if (mod != 0) { + uint8_t pad_bytes[3] = {0}; + uint32_t pad_size = 4 - mod; + ESP_COREDUMP_LOG_PROCESS("Core dump note needs %d bytes padding", pad_size); + err = self->write_cfg->write(self->write_cfg->priv, pad_bytes, pad_size); + ELF_CHECK_ERR((err == ESP_OK), ELF_PROC_ERR_WRITE_FAIL, "Write ELF note padding failure (%d)", err); + } + } + + return ALIGN_UP(name_len + ALIGN_UP(self->note_data_size, 4) + sizeof(elf_note), 4); +} +#endif //CONFIG_ESP_TASK_WDT_EN + static int elf_write_core_dump_info(core_dump_elf_t *self) { void *extra_info = NULL; @@ -530,13 +614,22 @@ static int elf_write_core_dump_info(core_dump_elf_t *self) ELF_CHECK_ERR((ret > 0), ret, "Extra info note write failed. Returned (%d).", ret); data_len += ret; +#if CONFIG_ESP_TASK_WDT_EN + extern bool g_twdt_isr; + if (g_twdt_isr) { + ret = elf_add_wdt_panic_details(self); + if (ret <= 0) { return ret; } + data_len += ret; + } +#endif + if (g_panic_abort_details && strlen(g_panic_abort_details) > 0) { ret = elf_add_note(self, - "ESP_PANIC_DETAILS", - ELF_ESP_CORE_DUMP_PANIC_DETAILS_TYPE, - g_panic_abort_details, - strlen(g_panic_abort_details)); - ELF_CHECK_ERR((ret > 0), ret, "Panic details note write failed. Returned (%d).", ret); + ELF_ESP_CORE_DUMP_PANIC_DETAILS_NOTE_NAME, + ELF_ESP_CORE_DUMP_PANIC_DETAILS_TYPE, + g_panic_abort_details, + strlen(g_panic_abort_details)); + ELF_CHECK_ERR((ret > 0), ret, "Panic details note write failed. Returned (%d).", ret); data_len += ret; } @@ -769,8 +862,7 @@ static void esp_core_dump_parse_note_section(uint8_t *coredump_data, elf_note_co break; } } - consumed_note_sz += note->n_namesz + note->n_descsz + sizeof(elf_note); - ALIGN(4, consumed_note_sz); + consumed_note_sz += ALIGN_UP(note->n_namesz + note->n_descsz + sizeof(elf_note), 4); } } } diff --git a/components/espcoredump/src/port/riscv/core_dump_port.c b/components/espcoredump/src/port/riscv/core_dump_port.c index 00d76405023..e426c361241 100644 --- a/components/espcoredump/src/port/riscv/core_dump_port.c +++ b/components/espcoredump/src/port/riscv/core_dump_port.c @@ -141,6 +141,7 @@ _Static_assert(sizeof(riscv_prstatus) == PRSTATUS_SIZE, */ typedef struct { uint32_t crashed_task_tcb; + uint32_t isr_context; } riscv_extra_info_t; @@ -157,9 +158,10 @@ static uint32_t s_fake_stacks_num = 0; /* Statically initialize the extra information structure. */ static riscv_extra_info_t s_extra_info = { 0 }; -inline void esp_core_dump_port_init(panic_info_t *info) +inline void esp_core_dump_port_init(panic_info_t *info, bool isr_context) { s_extra_info.crashed_task_tcb = COREDUMP_CURR_TASK_MARKER; + s_extra_info.isr_context = isr_context; } /** diff --git a/components/espcoredump/src/port/xtensa/core_dump_port.c b/components/espcoredump/src/port/xtensa/core_dump_port.c index 452c4259f69..16442833917 100644 --- a/components/espcoredump/src/port/xtensa/core_dump_port.c +++ b/components/espcoredump/src/port/xtensa/core_dump_port.c @@ -14,7 +14,7 @@ #include "soc/soc_memory_layout.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_rom_sys.h" #include "esp_core_dump_common.h" #include "esp_core_dump_port.h" @@ -95,6 +95,7 @@ typedef struct core_dump_reg_pair_t exccause; core_dump_reg_pair_t excvaddr; core_dump_reg_pair_t extra_regs[COREDUMP_EXTRA_REG_NUM]; + uint32_t isr_context; } __attribute__((packed)) xtensa_extra_info_t; // Xtensa Program Status for GDB @@ -259,7 +260,7 @@ static esp_err_t esp_core_dump_get_regs_from_stack(void* stack_addr, return ESP_OK; } -inline void esp_core_dump_port_init(panic_info_t *info) +inline void esp_core_dump_port_init(panic_info_t *info, bool isr_context) { s_extra_info.crashed_task_tcb = COREDUMP_CURR_TASK_MARKER; // Initialize exccause register to default value (required if current task corrupted) @@ -271,6 +272,7 @@ inline void esp_core_dump_port_init(panic_info_t *info) if (info->pseudo_excause) { s_exc_frame->exccause += XCHAL_EXCCAUSE_NUM; } + s_extra_info.isr_context = isr_context; } /** diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index e00f53372c2..02528104076 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -122,7 +122,6 @@ idf_build_get_property(build_dir BUILD_DIR) idf_build_get_property(elf_name EXECUTABLE_NAME GENERATOR_EXPRESSION) idf_build_get_property(elf EXECUTABLE GENERATOR_EXPRESSION) -idf_build_get_property(elf_dir EXECUTABLE_DIR GENERATOR_EXPRESSION) if(CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES AND NOT BOOTLOADER_BUILD) set(unsigned_project_binary "${elf_name}-unsigned.bin") @@ -138,10 +137,10 @@ set(PROJECT_BIN "${elf_name}.bin") if(CONFIG_APP_BUILD_GENERATE_BINARIES) add_custom_command(OUTPUT "${build_dir}/.bin_timestamp" COMMAND ${ESPTOOLPY} elf2image ${esptool_elf2image_args} - -o "${build_dir}/${unsigned_project_binary}" "${elf_dir}/${elf}" + -o "${build_dir}/${unsigned_project_binary}" "$>" COMMAND ${CMAKE_COMMAND} -E echo "Generated ${build_dir}/${unsigned_project_binary}" COMMAND ${CMAKE_COMMAND} -E md5sum "${build_dir}/${unsigned_project_binary}" > "${build_dir}/.bin_timestamp" - DEPENDS ${elf} + DEPENDS "$>" VERBATIM WORKING_DIRECTORY ${build_dir} COMMENT "Generating binary image from built executable" @@ -237,7 +236,7 @@ add_custom_target(monitor COMMAND ${CMAKE_COMMAND} -D "IDF_PATH=${idf_path}" -D "SERIAL_TOOL=${ESPMONITOR}" - -D "SERIAL_TOOL_ARGS=--target;${target};${monitor_rev_args};${elf_dir}/${elf}" + -D "SERIAL_TOOL_ARGS=--target;${target};${monitor_rev_args};$>" -D "WORKING_DIRECTORY=${build_dir}" -P run_serial_tool.cmake WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR} diff --git a/components/fatfs/CMakeLists.txt b/components/fatfs/CMakeLists.txt index e9ae1f88744..f641ca860ab 100644 --- a/components/fatfs/CMakeLists.txt +++ b/components/fatfs/CMakeLists.txt @@ -22,7 +22,7 @@ else() list(APPEND include_dirs "vfs") - list(APPEND requires "sdmmc") + list(APPEND requires "sdmmc" "esp_driver_sdmmc" "esp_driver_sdspi") list(APPEND priv_requires "vfs" "esp_driver_gpio") endif() diff --git a/components/fatfs/Kconfig b/components/fatfs/Kconfig index f2c737a6ce1..31be7cbfee2 100644 --- a/components/fatfs/Kconfig +++ b/components/fatfs/Kconfig @@ -239,4 +239,18 @@ menu "FAT Filesystem support" vfs_fat_pwrite(), vfs_fat_link(), vfs_fat_truncate() and vfs_fat_ftruncate() functions. This feature improves file-consistency and size reporting accuracy for the FatFS, at a price on decreased performance due to frequent disk operations + + config FATFS_USE_LABEL + bool "Use FATFS volume label" + default n + help + Allows FATFS volume label to be specified using f_setlabel + + config FATFS_LINK_LOCK + bool "Perform the whole link operation under lock" + default y + help + If enabled, the whole link operation (including file copying) is performed under lock. + This ensures that the link operation is atomic, but may cause perfomance for large files. + It may create less fragmented file copy. endmenu diff --git a/components/fatfs/diskio/diskio_sdmmc.h b/components/fatfs/diskio/diskio_sdmmc.h index 2ba4c2d9bea..d6c881ae585 100644 --- a/components/fatfs/diskio/diskio_sdmmc.h +++ b/components/fatfs/diskio/diskio_sdmmc.h @@ -7,7 +7,7 @@ #pragma once #include "sdmmc_cmd.h" -#include "driver/sdmmc_defs.h" +#include "sd_protocol_defs.h" #ifdef __cplusplus extern "C" { diff --git a/components/fatfs/fatfs_utils/boot_sector.py b/components/fatfs/fatfs_utils/boot_sector.py index 615dd065112..389d27c7a22 100644 --- a/components/fatfs/fatfs_utils/boot_sector.py +++ b/components/fatfs/fatfs_utils/boot_sector.py @@ -1,9 +1,9 @@ -# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 from inspect import getmembers, isroutine from typing import Optional -from construct import Const, Int8ul, Int16ul, Int32ul, PaddedString, Struct, core +from construct import Bytes, Const, Int8ul, Int16ul, Int32ul, PaddedString, Padding, Struct, core from .exceptions import InconsistentFATAttributes, NotInitialized from .fatfs_state import BootSectorState @@ -29,8 +29,7 @@ class BootSector: BOOT_HEADER_SIZE = 512 BOOT_SECTOR_HEADER = Struct( - # this value reflects BS_jmpBoot used for ESP32 boot sector (any other accepted) - 'BS_jmpBoot' / Const(b'\xeb\xfe\x90'), + 'BS_jmpBoot' / Bytes(3), 'BS_OEMName' / PaddedString(MAX_OEM_NAME_SIZE, SHORT_NAMES_ENCODING), 'BPB_BytsPerSec' / Int16ul, 'BPB_SecPerClus' / Int8ul, @@ -45,12 +44,12 @@ class BootSector: 'BPB_HiddSec' / Int32ul, 'BPB_TotSec32' / Int32ul, # zero if the FAT type is 12/16, otherwise number of sectors 'BS_DrvNum' / Const(b'\x80'), - 'BS_Reserved1' / Const(EMPTY_BYTE), + 'BS_Reserved1' / Padding(1), 'BS_BootSig' / Const(b'\x29'), 'BS_VolID' / Int32ul, 'BS_VolLab' / PaddedString(MAX_VOL_LAB_SIZE, SHORT_NAMES_ENCODING), 'BS_FilSysType' / PaddedString(MAX_FS_TYPE_SIZE, SHORT_NAMES_ENCODING), - 'BS_EMPTY' / Const(448 * EMPTY_BYTE), + 'BS_EMPTY' / Padding(448), 'Signature_word' / Const(FATDefaults.SIGNATURE_WORD) ) assert BOOT_SECTOR_HEADER.sizeof() == BOOT_HEADER_SIZE @@ -73,7 +72,8 @@ def generate_boot_sector(self) -> None: * EMPTY_BYTE) self.boot_sector_state.binary_image = ( BootSector.BOOT_SECTOR_HEADER.build( - dict(BS_OEMName=pad_string(boot_sector_state.oem_name, size=BootSector.MAX_OEM_NAME_SIZE), + dict(BS_jmpBoot=(b'\xeb\xfe\x90'), + BS_OEMName=pad_string(boot_sector_state.oem_name, size=BootSector.MAX_OEM_NAME_SIZE), BPB_BytsPerSec=boot_sector_state.sector_size, BPB_SecPerClus=boot_sector_state.sectors_per_cluster, BPB_RsvdSecCnt=boot_sector_state.reserved_sectors_cnt, @@ -91,8 +91,7 @@ def generate_boot_sector(self) -> None: BS_VolLab=pad_string(boot_sector_state.volume_label, size=BootSector.MAX_VOL_LAB_SIZE), BS_FilSysType=pad_string(boot_sector_state.file_sys_type, - size=BootSector.MAX_FS_TYPE_SIZE) - ) + size=BootSector.MAX_FS_TYPE_SIZE)) ) + pad_header + fat_tables_content + root_dir_content + data_content ) diff --git a/components/fatfs/fatfsparse.py b/components/fatfs/fatfsparse.py index c5d3716c562..6eab1ff7cb1 100755 --- a/components/fatfs/fatfsparse.py +++ b/components/fatfs/fatfsparse.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 import argparse import os @@ -57,7 +57,7 @@ def traverse_folder_tree(directory_bytes_: bytes, try: obj_: dict = Entry.ENTRY_FORMAT_SHORT_NAME.parse( directory_bytes_[obj_address_: obj_address_ + FATDefaults.ENTRY_SIZE]) - except (construct.core.ConstError, UnicodeDecodeError): + except (construct.core.ConstError, UnicodeDecodeError, construct.core.StringError): args.long_name_support = True continue @@ -100,7 +100,7 @@ def remove_wear_levelling_if_exists(fs_: bytes) -> bytes: boot_sector__.parse_boot_sector(fs_) if boot_sector__.boot_sector_state.size == len(fs_): return fs_ - except construct.core.ConstError: + except UnicodeDecodeError: pass plain_fs: bytes = remove_wl(fs_) return plain_fs @@ -124,6 +124,9 @@ def remove_wear_levelling_if_exists(fs_: bytes) -> bytes: default=None, help="If detection doesn't work correctly, " 'you can force analyzer to or not to assume WL.') + argument_parser.add_argument('--verbose', + action='store_true', + help='Prints details about FAT image.') args = argument_parser.parse_args() @@ -157,6 +160,10 @@ def remove_wear_levelling_if_exists(fs_: bytes) -> bytes: boot_sector_ = BootSector() boot_sector_.parse_boot_sector(fs) + + if args.verbose: + print(str(boot_sector_)) + fat = FAT(boot_sector_.boot_sector_state, init_=False) boot_dir_start_ = boot_sector_.boot_sector_state.root_directory_start diff --git a/components/fatfs/host_test/.build-test-rules.yml b/components/fatfs/host_test/.build-test-rules.yml new file mode 100644 index 00000000000..668da2d3203 --- /dev/null +++ b/components/fatfs/host_test/.build-test-rules.yml @@ -0,0 +1,3 @@ +components/fatfs/host_test: + enable: + - if: IDF_TARGET == "linux" diff --git a/components/fatfs/host_test/CMakeLists.txt b/components/fatfs/host_test/CMakeLists.txt index 48267da8d39..7bf861b1b9d 100644 --- a/components/fatfs/host_test/CMakeLists.txt +++ b/components/fatfs/host_test/CMakeLists.txt @@ -2,9 +2,7 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -# Freertos is included via common components. However, CATCH isn't compatible with the FreeRTOS component yet, hence -# using the FreeRTOS mock component. -# target. +# This test doesn't require FreeRTOS, uses a mock instead list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") project(fatfs_host_test) diff --git a/components/fatfs/host_test/main/CMakeLists.txt b/components/fatfs/host_test/main/CMakeLists.txt index ef8aeb43dbf..046433c1307 100644 --- a/components/fatfs/host_test/main/CMakeLists.txt +++ b/components/fatfs/host_test/main/CMakeLists.txt @@ -1,6 +1,8 @@ -idf_component_register(SRCS "main.cpp" - "test_fatfs.cpp" - INCLUDE_DIRS "$ENV{IDF_PATH}/tools/catch" +idf_component_register(SRCS "test_fatfs.cpp" REQUIRES fatfs WHOLE_ARCHIVE ) + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/fatfs/host_test/main/idf_component.yml b/components/fatfs/host_test/main/idf_component.yml new file mode 100644 index 00000000000..f7982136b97 --- /dev/null +++ b/components/fatfs/host_test/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/catch2: "^3.4.0" diff --git a/components/fatfs/host_test/main/test_fatfs.cpp b/components/fatfs/host_test/main/test_fatfs.cpp index 1bb51cb9a47..5ceb7327579 100644 --- a/components/fatfs/host_test/main/test_fatfs.cpp +++ b/components/fatfs/host_test/main/test_fatfs.cpp @@ -12,9 +12,9 @@ #include "diskio_impl.h" #include "diskio_wl.h" -#include "catch.hpp" +#include -TEST_CASE("create volume, open file, write and read back data", "[fatfs]") +TEST_CASE("Create volume, open file, write and read back data", "[fatfs]") { FRESULT fr_result; BYTE pdrv; @@ -90,6 +90,195 @@ TEST_CASE("create volume, open file, write and read back data", "[fatfs]") fr_result = f_mount(0, "", 0); REQUIRE(fr_result == FR_OK); + // Clear free(read); free(data); + ff_diskio_unregister(pdrv); + ff_diskio_clear_pdrv_wl(wl_handle); + esp_result = wl_unmount(wl_handle); + REQUIRE(esp_result == ESP_OK); +} + +static void prepare_fatfs(const char* partition_label, const esp_partition_t** partition, wl_handle_t* wl_handle, BYTE* pdrv) +{ + FRESULT fr_result; + esp_err_t esp_result; + + *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, partition_label); + REQUIRE(partition != NULL); + printf("partition address=0x%x\n", (*partition)->address); + printf("partition size=0x%x\n", (*partition)->size); + + // Mount wear-levelled partition + esp_result = wl_mount(*partition, wl_handle); + REQUIRE(esp_result == ESP_OK); + + // Get a physical drive + BYTE _pdrv; + esp_result = ff_diskio_get_drive(&_pdrv); + REQUIRE(esp_result == ESP_OK); + printf("using pdrv=%i\n", _pdrv); + char drv[3] = {(char)('0' + _pdrv), ':', 0}; + *pdrv = _pdrv; + + // Register physical drive as wear-levelled partition + esp_result = ff_diskio_register_wl_partition(_pdrv, *wl_handle); + + // Create FAT volume on the entire disk + LBA_t part_list[] = {100, 0, 0, 0}; + BYTE work_area[FF_MAX_SS]; + + fr_result = f_fdisk(_pdrv, part_list, work_area); + REQUIRE(fr_result == FR_OK); + const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, 0}; + fr_result = f_mkfs(drv, &opt, work_area, sizeof(work_area)); // Use default volume + REQUIRE(fr_result == FR_OK); +} + +/* + * This just tests formatting from FATFS library itself, not directly VFS FATFS (SPIFLASH) API + * like `esp_vfs_fat_spiflash_format_rw_wl` function, since `vfs` is not buildable on linux host + * at the time of writing this - therefore there also is a device test_apps test in + * `components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c` which tests our VFS FATFS SPIFLASH API. + */ +TEST_CASE("Test mounting 2 volumes, writing data and formating the 2nd one, reading data", "[fatfs]") +{ + FRESULT fr_result; + esp_err_t esp_result; + + const char* partition_label0 = "storage"; + const esp_partition_t *partition0 = NULL; + BYTE pdrv0 = UINT8_MAX; + FATFS fs0; + wl_handle_t wl_handle0 = WL_INVALID_HANDLE; + + const char* partition_label1 = "storage2"; + const esp_partition_t *partition1 = NULL; + BYTE pdrv1 = UINT8_MAX; + FATFS fs1; + wl_handle_t wl_handle1 = WL_INVALID_HANDLE; + + size_t data_size = 10; + + + // Mount the volume 0 + prepare_fatfs(partition_label0, &partition0, &wl_handle0, &pdrv0); + REQUIRE(partition0 != NULL); + REQUIRE(wl_handle0 != WL_INVALID_HANDLE); + REQUIRE(pdrv0 == 0); + char drv0[3] = {(char)('0' + pdrv0), ':', 0}; + fr_result = f_mount(&fs0, drv0, 0); + REQUIRE(fr_result == FR_OK); + + // Open file and write data + FIL file0; + UINT bw0; + fr_result = f_open(&file0, "0:/test0.txt", FA_OPEN_ALWAYS | FA_WRITE); + REQUIRE(fr_result == FR_OK); + // Write data + const char *data0 = "123456789"; + char read0[10] = {0}; + fr_result = f_write(&file0, data0, data_size, &bw0); + REQUIRE(fr_result == FR_OK); + REQUIRE(bw0 == data_size); + // Close file + fr_result = f_close(&file0); + REQUIRE(fr_result == FR_OK); + + // Unmount volume 0 + fr_result = f_mount(0, drv0, 0); + REQUIRE(fr_result == FR_OK); + + + // Mount the volume 1 + prepare_fatfs(partition_label1, &partition1, &wl_handle1, &pdrv1); + REQUIRE(partition1 != NULL); + REQUIRE(wl_handle1 != WL_INVALID_HANDLE); + REQUIRE(pdrv1 == 1); + char drv1[3] = {(char)('0' + pdrv1), ':', 0}; + fr_result = f_mount(&fs1, drv1, 0); + REQUIRE(fr_result == FR_OK); + + // Open file and write data + FIL file1; + UINT bw1; + fr_result = f_open(&file1, "1:/test1.txt", FA_OPEN_ALWAYS | FA_WRITE); + REQUIRE(fr_result == FR_OK); + // Write data + const char* data1 = "987654321"; + char read1[10] = {0}; + fr_result = f_write(&file1, data1, data_size, &bw1); + REQUIRE(fr_result == FR_OK); + REQUIRE(bw1 == data_size); + // Close file + fr_result = f_close(&file1); + REQUIRE(fr_result == FR_OK); + + // Unmount volume 1 + fr_result = f_mount(0, drv1, 0); + REQUIRE(fr_result == FR_OK); + + // Format the volume 1 + const size_t workbuf_size = 4096; + void *workbuf = ff_memalloc(workbuf_size); + REQUIRE(workbuf != NULL); + const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 0, CONFIG_WL_SECTOR_SIZE}; + fr_result = f_mkfs(drv1, &opt, workbuf, workbuf_size); + free(workbuf); + workbuf = NULL; + REQUIRE(fr_result == FR_OK); + printf("partition1 formatted\n"); + + + // Remount the volume 1 + fr_result = f_mount(&fs1, drv1, 1); + REQUIRE(fr_result == FR_OK); + // Open file and read data from file1 + fr_result = f_open(&file1, "1:/test1.txt", FA_OPEN_ALWAYS | FA_READ); + REQUIRE(fr_result == FR_OK); + // Read written data from file1 + fr_result = f_read(&file1, read1, data_size, &bw1); + REQUIRE(fr_result == FR_OK); + REQUIRE(bw1 != data_size); + // Comapre data + printf("data1=%s, read1=%s\n", data1, read1); + REQUIRE(strncmp(data1, read1, data_size-1) != 0); // 987654321 should be ersead due to formatting + // Close file from file1 + fr_result = f_close(&file1); + REQUIRE(fr_result == FR_OK); + + + // Remount the volume 0 + fr_result = f_mount(&fs0, drv0, 1); + REQUIRE(fr_result == FR_OK); + // Open file and read data from file0 + fr_result = f_open(&file0, "0:/test0.txt", FA_OPEN_ALWAYS | FA_READ); + REQUIRE(fr_result == FR_OK); + // Read written data from file0 + fr_result = f_read(&file0, read0, data_size, &bw0); + REQUIRE(fr_result == FR_OK); + REQUIRE(bw0 == data_size); + // Comapre data + printf("data0=%s, read0=%s\n", data0, read0); + REQUIRE(strncmp(data0, read0, data_size-1) == 0); // should match since the partition was not formatted + // Close file from file0 + fr_result = f_close(&file0); + REQUIRE(fr_result == FR_OK); + + + // Unmount both volumes + fr_result = f_mount(0, drv0, 0); + REQUIRE(fr_result == FR_OK); + fr_result = f_mount(0, drv1, 0); + REQUIRE(fr_result == FR_OK); + + // Clear + ff_diskio_unregister(pdrv0); + ff_diskio_unregister(pdrv1); + ff_diskio_clear_pdrv_wl(wl_handle0); + ff_diskio_clear_pdrv_wl(wl_handle1); + esp_result = wl_unmount(wl_handle0); + REQUIRE(esp_result == ESP_OK); + esp_result = wl_unmount(wl_handle1); + REQUIRE(esp_result == ESP_OK); } diff --git a/components/fatfs/host_test/partition_table.csv b/components/fatfs/host_test/partition_table.csv index 1c79321a107..30d2d909258 100644 --- a/components/fatfs/host_test/partition_table.csv +++ b/components/fatfs/host_test/partition_table.csv @@ -4,3 +4,4 @@ nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, factory, app, factory, 0x10000, 1M, storage, data, fat, , 1M, +storage2, data, fat, , 1M, diff --git a/components/fatfs/host_test/sdkconfig.defaults b/components/fatfs/host_test/sdkconfig.defaults index b86c4111cd4..e0d9a692fdc 100644 --- a/components/fatfs/host_test/sdkconfig.defaults +++ b/components/fatfs/host_test/sdkconfig.defaults @@ -9,4 +9,4 @@ CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table.csv" CONFIG_ESPTOOLPY_FLASHSIZE="8MB" CONFIG_MMU_PAGE_SIZE=0X10000 CONFIG_ESP_PARTITION_ENABLE_STATS=y -CONFIG_FATFS_VOLUME_COUNT=2 +CONFIG_FATFS_VOLUME_COUNT=3 diff --git a/components/fatfs/sbom.yml b/components/fatfs/sbom.yml new file mode 100644 index 00000000000..d9e037070cb --- /dev/null +++ b/components/fatfs/sbom.yml @@ -0,0 +1,5 @@ +name: 'FatFs' +version: 'R0.15' +supplier: 'Organization: Espressif Systems (Shanghai) CO LTD' +originator: 'Person: ChaN' +description: 'Generic FAT Filesystem Module for embedded systems.' diff --git a/components/fatfs/src/ffconf.h b/components/fatfs/src/ffconf.h index 7e25dd08f0c..8d579002b6c 100644 --- a/components/fatfs/src/ffconf.h +++ b/components/fatfs/src/ffconf.h @@ -49,7 +49,7 @@ / (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ -#define FF_USE_LABEL 0 +#define FF_USE_LABEL CONFIG_FATFS_USE_LABEL /* This option switches volume label functions, f_getlabel() and f_setlabel(). / (0:Disable or 1:Enable) */ diff --git a/components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c b/components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c index 237728063c7..1af50fe6cbe 100644 --- a/components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c +++ b/components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c @@ -61,6 +61,30 @@ TEST_CASE("(WL) can format when the FAT is mounted already", "[fatfs][wear_level test_teardown(); } +TEST_CASE("(WL) can format specified FAT when more are mounted", "[fatfs][wear_levelling][timeout=180]") +{ + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = true, + .max_files = 5, + }; + wl_handle_t s_test_wl_handle1; + wl_handle_t s_test_wl_handle2; + TEST_ESP_OK(esp_vfs_fat_spiflash_mount_rw_wl("/spiflash1", "storage", &mount_config, &s_test_wl_handle1)); + TEST_ESP_OK(esp_vfs_fat_spiflash_mount_rw_wl("/spiflash2", "storage2", &mount_config, &s_test_wl_handle2)); + + test_fatfs_create_file_with_text("/spiflash1/hello.txt", fatfs_test_hello_str); + test_fatfs_create_file_with_text("/spiflash2/hello.txt", fatfs_test_hello_str); + + TEST_ESP_OK(esp_vfs_fat_spiflash_format_rw_wl("/spiflash2", "storage2")); + + FILE* f = fopen("/spiflash2/hello.txt", "r"); + TEST_ASSERT_NULL(f); // File is erased on the formatted FAT + test_fatfs_pread_file("/spiflash1/hello.txt"); // File is still readable on the other FAT + + TEST_ESP_OK(esp_vfs_fat_spiflash_unmount_rw_wl("/spiflash1", s_test_wl_handle1)); + TEST_ESP_OK(esp_vfs_fat_spiflash_unmount_rw_wl("/spiflash2", s_test_wl_handle2)); +} + TEST_CASE("(WL) can create and write file", "[fatfs][wear_levelling]") { test_setup(); diff --git a/components/fatfs/test_apps/flash_wl/partitions.csv b/components/fatfs/test_apps/flash_wl/partitions.csv index a929971141e..d1dcbae61db 100644 --- a/components/fatfs/test_apps/flash_wl/partitions.csv +++ b/components/fatfs/test_apps/flash_wl/partitions.csv @@ -1,3 +1,4 @@ # Name, Type, SubType, Offset, Size, Flags -factory, app, factory, 0x10000, 1M, +factory, app, factory, 0x10000, 768k, storage, data, fat, , 528k, +storage2, data, fat, , 528k, diff --git a/components/fatfs/vfs/esp_vfs_fat.h b/components/fatfs/vfs/esp_vfs_fat.h index 3e7b165b4e5..983dc8d6b7e 100644 --- a/components/fatfs/vfs/esp_vfs_fat.h +++ b/components/fatfs/vfs/esp_vfs_fat.h @@ -7,8 +7,7 @@ #pragma once #include #include "esp_err.h" -#include "driver/gpio.h" -#include "driver/sdmmc_types.h" +#include "sd_protocol_types.h" #include "driver/sdspi_host.h" #include "ff.h" #include "wear_levelling.h" diff --git a/components/fatfs/vfs/vfs_fat.c b/components/fatfs/vfs/vfs_fat.c index 4ae04c3d617..5d70c09b23c 100644 --- a/components/fatfs/vfs/vfs_fat.c +++ b/components/fatfs/vfs/vfs_fat.c @@ -396,10 +396,12 @@ static ssize_t vfs_fat_write(void* ctx, int fd, const void * data, size_t size) vfs_fat_ctx_t* fat_ctx = (vfs_fat_ctx_t*) ctx; FIL* file = &fat_ctx->files[fd]; FRESULT res; + _lock_acquire(&fat_ctx->lock); if (fat_ctx->o_append[fd]) { if ((res = f_lseek(file, f_size(file))) != FR_OK) { ESP_LOGD(TAG, "%s: fresult=%d", __func__, res); errno = fresult_to_errno(res); + _lock_release(&fat_ctx->lock); return -1; } } @@ -407,18 +409,19 @@ static ssize_t vfs_fat_write(void* ctx, int fd, const void * data, size_t size) res = f_write(file, data, size, &written); if (((written == 0) && (size != 0)) && (res == 0)) { errno = ENOSPC; + _lock_release(&fat_ctx->lock); return -1; } if (res != FR_OK) { ESP_LOGD(TAG, "%s: fresult=%d", __func__, res); errno = fresult_to_errno(res); if (written == 0) { + _lock_release(&fat_ctx->lock); return -1; } } #if CONFIG_FATFS_IMMEDIATE_FSYNC - _lock_acquire(&fat_ctx->lock); if (written > 0) { res = f_sync(file); if (res != FR_OK) { @@ -428,9 +431,8 @@ static ssize_t vfs_fat_write(void* ctx, int fd, const void * data, size_t size) return -1; } } - _lock_release(&fat_ctx->lock); #endif - + _lock_release(&fat_ctx->lock); return written; } @@ -549,10 +551,8 @@ static ssize_t vfs_fat_pwrite(void *ctx, int fd, const void *src, size_t size, o static int vfs_fat_fsync(void* ctx, int fd) { vfs_fat_ctx_t* fat_ctx = (vfs_fat_ctx_t*) ctx; - _lock_acquire(&fat_ctx->lock); FIL* file = &fat_ctx->files[fd]; FRESULT res = f_sync(file); - _lock_release(&fat_ctx->lock); int rc = 0; if (res != FR_OK) { ESP_LOGD(TAG, "%s: fresult=%d", __func__, res); @@ -707,74 +707,85 @@ static int vfs_fat_link(void* ctx, const char* n1, const char* n2) vfs_fat_ctx_t* fat_ctx = (vfs_fat_ctx_t*) ctx; _lock_acquire(&fat_ctx->lock); prepend_drive_to_path(fat_ctx, &n1, &n2); - const size_t copy_buf_size = fat_ctx->fs.csize; - FRESULT res; + + FRESULT res = FR_OK; + int ret = 0; + FIL* pf1 = (FIL*) ff_memalloc(sizeof(FIL)); FIL* pf2 = (FIL*) ff_memalloc(sizeof(FIL)); + + const size_t copy_buf_size = fat_ctx->fs.csize; void* buf = ff_memalloc(copy_buf_size); if (buf == NULL || pf1 == NULL || pf2 == NULL) { - _lock_release(&fat_ctx->lock); ESP_LOGD(TAG, "alloc failed, pf1=%p, pf2=%p, buf=%p", pf1, pf2, buf); - free(pf1); - free(pf2); - free(buf); + _lock_release(&fat_ctx->lock); errno = ENOMEM; - return -1; + ret = -1; + goto cleanup; } + memset(pf1, 0, sizeof(*pf1)); memset(pf2, 0, sizeof(*pf2)); + res = f_open(pf1, n1, FA_READ | FA_OPEN_EXISTING); if (res != FR_OK) { _lock_release(&fat_ctx->lock); - goto fail1; + goto cleanup; } + res = f_open(pf2, n2, FA_WRITE | FA_CREATE_NEW); + +#if !CONFIG_FATFS_LINK_LOCK _lock_release(&fat_ctx->lock); +#endif + if (res != FR_OK) { - goto fail2; + goto close_old; } + size_t size_left = f_size(pf1); while (size_left > 0) { size_t will_copy = (size_left < copy_buf_size) ? size_left : copy_buf_size; size_t read; res = f_read(pf1, buf, will_copy, &read); if (res != FR_OK) { - goto fail3; + goto close_both; } else if (read != will_copy) { res = FR_DISK_ERR; - goto fail3; + goto close_both; } size_t written; res = f_write(pf2, buf, will_copy, &written); if (res != FR_OK) { - goto fail3; + goto close_both; } else if (written != will_copy) { res = FR_DISK_ERR; - goto fail3; + goto close_both; } size_left -= will_copy; } -#if CONFIG_FATFS_IMMEDIATE_FSYNC - _lock_acquire(&fat_ctx->lock); - res = f_sync(pf2); +close_both: + f_close(pf2); + +close_old: + f_close(pf1); + +#if CONFIG_FATFS_LINK_LOCK _lock_release(&fat_ctx->lock); #endif -fail3: - f_close(pf2); -fail2: - f_close(pf1); -fail1: +cleanup: free(buf); free(pf2); free(pf1); - if (res != FR_OK) { + if (ret == 0 && res != FR_OK) { ESP_LOGD(TAG, "%s: fresult=%d", __func__, res); errno = fresult_to_errno(res); return -1; } - return 0; + + return ret; } static int vfs_fat_rename(void* ctx, const char *src, const char *dst) @@ -881,8 +892,10 @@ static long vfs_fat_telldir(void* ctx, DIR* pdir) static void vfs_fat_seekdir(void* ctx, DIR* pdir, long offset) { assert(pdir); + vfs_fat_ctx_t* fat_ctx = (vfs_fat_ctx_t*) ctx; vfs_fat_dir_t* fat_dir = (vfs_fat_dir_t*) pdir; FRESULT res; + _lock_acquire(&fat_ctx->lock); if (offset < fat_dir->offset) { res = f_rewinddir(&fat_dir->ffdir); if (res != FR_OK) { @@ -901,6 +914,7 @@ static void vfs_fat_seekdir(void* ctx, DIR* pdir, long offset) } fat_dir->offset++; } + _lock_release(&fat_ctx->lock); } static int vfs_fat_mkdir(void* ctx, const char* name, mode_t mode) diff --git a/components/fatfs/vfs/vfs_fat_sdmmc.c b/components/fatfs/vfs/vfs_fat_sdmmc.c index 1a5ac2150b9..f3742a4a6ad 100644 --- a/components/fatfs/vfs/vfs_fat_sdmmc.c +++ b/components/fatfs/vfs/vfs_fat_sdmmc.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include +#include "esp_check.h" #include "esp_log.h" #include "esp_vfs.h" #include "esp_vfs_fat.h" @@ -15,7 +16,7 @@ #include "diskio_impl.h" #include "diskio_sdmmc.h" #include "soc/soc_caps.h" -#include "driver/sdmmc_defs.h" +#include "sd_protocol_defs.h" #if SOC_SDMMC_HOST_SUPPORTED #include "driver/sdmmc_host.h" @@ -463,16 +464,20 @@ esp_err_t esp_vfs_fat_sdcard_format(const char *base_path, sdmmc_card_t *card) return ESP_ERR_INVALID_STATE; } + //unmount + char drv[3] = {(char)('0' + pdrv), ':', 0}; + FRESULT res = f_mount(0, drv, 0); + if (res != FR_OK) { + ESP_LOGE(TAG, "f_mount unmount failed (%d)", res); + return ESP_FAIL; + } + const size_t workbuf_size = 4096; void *workbuf = ff_memalloc(workbuf_size); if (workbuf == NULL) { return ESP_ERR_NO_MEM; } - //unmount - char drv[3] = {(char)('0' + pdrv), ':', 0}; - f_mount(0, drv, 0); - //format uint32_t id = FF_VOLUMES; bool found = s_get_context_id_by_card(card, &id); @@ -482,7 +487,7 @@ esp_err_t esp_vfs_fat_sdcard_format(const char *base_path, sdmmc_card_t *card) s_ctx[id]->mount_config.allocation_unit_size); ESP_LOGI(TAG, "Formatting card, allocation unit size=%d", alloc_unit_size); const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, alloc_unit_size}; - FRESULT res = f_mkfs(drv, &opt, workbuf, workbuf_size); + res = f_mkfs(drv, &opt, workbuf, workbuf_size); free(workbuf); if (res != FR_OK) { ret = ESP_FAIL; diff --git a/components/fatfs/vfs/vfs_fat_spiflash.c b/components/fatfs/vfs/vfs_fat_spiflash.c index 0db2f70e0a2..98e4160faf0 100644 --- a/components/fatfs/vfs/vfs_fat_spiflash.c +++ b/components/fatfs/vfs/vfs_fat_spiflash.c @@ -208,7 +208,6 @@ esp_err_t esp_vfs_fat_spiflash_format_rw_wl(const char* base_path, const char* p wl_handle_t temp_handle = WL_INVALID_HANDLE; uint32_t id = FF_VOLUMES; - char drv[3] = {0, ':', 0}; bool found = s_get_context_id_by_label(partition_label, &id); if (!found) { @@ -224,8 +223,10 @@ esp_err_t esp_vfs_fat_spiflash_format_rw_wl(const char* base_path, const char* p } //unmount - drv[1] = (char)('0' + s_ctx[id]->pdrv); - f_mount(0, drv, 0); + char drv[3] = {(char)('0' + s_ctx[id]->pdrv), ':', 0}; + FRESULT fresult = f_mount(0, drv, 0); + ESP_RETURN_ON_FALSE(fresult != FR_INVALID_DRIVE, ESP_FAIL, TAG, "f_mount unmount failed (%d) - the logical drive number is invalid", fresult); + ESP_GOTO_ON_FALSE(fresult == FR_OK, ESP_FAIL, recycle, TAG, "f_mount unmount failed (%d), go to recycle", fresult); const size_t workbuf_size = 4096; void *workbuf = ff_memalloc(workbuf_size); @@ -236,7 +237,7 @@ esp_err_t esp_vfs_fat_spiflash_format_rw_wl(const char* base_path, const char* p size_t alloc_unit_size = esp_vfs_fat_get_allocation_unit_size(CONFIG_WL_SECTOR_SIZE, s_ctx[id]->mount_config.allocation_unit_size); ESP_LOGI(TAG, "Formatting FATFS partition, allocation unit size=%d", alloc_unit_size); const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 0, alloc_unit_size}; - FRESULT fresult = f_mkfs(drv, &opt, workbuf, workbuf_size); + fresult = f_mkfs(drv, &opt, workbuf, workbuf_size); free(workbuf); workbuf = NULL; ESP_GOTO_ON_FALSE(fresult == FR_OK, ESP_FAIL, mount_back, TAG, "f_mkfs failed (%d)", fresult); diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h index e23af815dc1..d074fa1c035 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h @@ -9,7 +9,11 @@ #include "sdkconfig.h" /* Macros used instead ofsetoff() for better performance of interrupt handler */ +#if CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES +#define PORT_OFFSET_PX_STACK 0x40 +#else #define PORT_OFFSET_PX_STACK 0x30 +#endif /* #if CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES */ #define PORT_OFFSET_PX_END_OF_STACK (PORT_OFFSET_PX_STACK + \ /* void * pxDummy6 */ 4 + \ /* BaseType_t xDummy23[ 2 ] */ 8 + \ diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h index 26c6841036d..c545338c1a1 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h @@ -424,7 +424,7 @@ portmacro.h. Therefore, we need to keep these headers around for now to allow th #include "portbenchmark.h" #include #include -#include +#include /* [refactor-todo] introduce a port wrapper function to avoid including esp_timer.h into the public header */ #if CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c index cb84e809311..f238dbc6e68 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c @@ -13,7 +13,7 @@ #include "portmacro.h" #include "spinlock.h" #include "xt_instr_macros.h" -#include "xtensa/xtensa_context.h" +#include "xtensa_context.h" #include "xtensa/corebits.h" #include "xtensa/config/core.h" #include "xtensa/config/core-isa.h" diff --git a/components/freertos/FreeRTOS-Kernel/idf_changes.md b/components/freertos/FreeRTOS-Kernel/idf_changes.md index 28385a40c55..a3ef8454601 100644 --- a/components/freertos/FreeRTOS-Kernel/idf_changes.md +++ b/components/freertos/FreeRTOS-Kernel/idf_changes.md @@ -199,3 +199,8 @@ List of changes made to Vanilla FreeRTOS V10.5.1 header files to allow for build ### tasks.c - Backported a change where the IDLE tasks are created with the core ID as a suffix in the task name. + +### timers.c + +- Backported configTIMER_SERVICE_TASK_CORE_AFFINITY config option to enable configurability of the Timer Service task's core affinity. + - The change also entails updating the task creation APIs to use IDF-FreeRTOS task creation APIs, adding a assert check for valid affinity values and dropping the use of configUSE_CORE_AFFINITY. diff --git a/components/freertos/FreeRTOS-Kernel/include/freertos/FreeRTOS.h b/components/freertos/FreeRTOS-Kernel/include/freertos/FreeRTOS.h index dd8a67905af..157ddaf5282 100644 --- a/components/freertos/FreeRTOS-Kernel/include/freertos/FreeRTOS.h +++ b/components/freertos/FreeRTOS-Kernel/include/freertos/FreeRTOS.h @@ -1289,8 +1289,9 @@ typedef struct xSTATIC_TCB UBaseType_t uxDummy5; void * pxDummy6; uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; - /* Todo: Remove xCoreID for single core builds (IDF-7894) */ - BaseType_t xDummyCoreID; + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xDummyCoreID; + #endif /* configNUMBER_OF_CORES > 1 */ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) void * pxDummy8; #endif diff --git a/components/freertos/FreeRTOS-Kernel/include/freertos/task.h b/components/freertos/FreeRTOS-Kernel/include/freertos/task.h index 9da4e26cfbc..976894ee6b6 100644 --- a/components/freertos/FreeRTOS-Kernel/include/freertos/task.h +++ b/components/freertos/FreeRTOS-Kernel/include/freertos/task.h @@ -176,7 +176,9 @@ typedef struct xTASK_STATUS StackType_t * pxEndOfStack; /**< Points to the end address of the task's stack area. */ #endif configSTACK_DEPTH_TYPE usStackHighWaterMark; /**< The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ - BaseType_t xCoreID; /**< Core this task is pinned to (0, 1, or tskNO_AFFINITY). If configNUMBER_OF_CORES == 1, this will always be 0. */ + #if ( configTASKLIST_INCLUDE_COREID == 1 ) + BaseType_t xCoreID; /**< Core this task is pinned to (0, 1, or tskNO_AFFINITY). If configNUMBER_OF_CORES == 1, this will always be 0. */ + #endif } TaskStatus_t; /** Possible return values for eTaskConfirmSleepModeStatus(). */ @@ -204,6 +206,15 @@ typedef enum #define tskNO_AFFINITY ( ( BaseType_t ) 0x7FFFFFFF ) /* Todo: Update tskNO_AFFINITY value to -1 (IDF-7908) */ +/** + * Macro to check if an xCoreID value is valid + * + * @return pdTRUE if valid, pdFALSE otherwise. + * + * \ingroup Tasks + */ +#define taskVALID_CORE_ID( xCoreID ) ( ( ( ( BaseType_t ) xCoreID ) >= 0 && ( ( BaseType_t ) xCoreID ) < configNUMBER_OF_CORES ) ? pdTRUE : pdFALSE ) + /** * * Macro for forcing a context switch. diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h index 3691fa12fa4..b4405606d28 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h @@ -37,11 +37,24 @@ #include "freertos/FreeRTOSConfig.h" /* Macros used instead ofsetoff() for better performance of interrupt handler */ +#if CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES +#define PORT_OFFSET_PX_STACK 0x40 +#else #define PORT_OFFSET_PX_STACK 0x30 -#define PORT_OFFSET_PX_END_OF_STACK (PORT_OFFSET_PX_STACK + \ - /* void * pxDummy6 */ 4 + \ - /* uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ] */ CONFIG_FREERTOS_MAX_TASK_NAME_LEN + \ - /* BaseType_t xDummyCoreID */ 4) +#endif /* #if CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + +#if CONFIG_FREERTOS_UNICORE +#define CORE_ID_SIZE 0 +#else +#define CORE_ID_SIZE 4 +#endif + +#define PORT_OFFSET_PX_END_OF_STACK ( \ + PORT_OFFSET_PX_STACK \ + + 4 /* void * pxDummy6 */ \ + + CONFIG_FREERTOS_MAX_TASK_NAME_LEN /* uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ] */ \ + + CORE_ID_SIZE /* BaseType_t xDummyCoreID */ \ +) #ifndef __ASSEMBLER__ diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c index 5f7f52400ac..5e30219b19f 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c @@ -301,7 +301,11 @@ static void vPortCleanUpCoprocArea(void *pvTCB) * If yes, reset the owner. */ if (sa->sa_enable != 0) { /* Get the core the task is pinned on */ - const BaseType_t coreID = task->xDummyCoreID; + #if ( configNUM_CORES > 1 ) + const BaseType_t coreID = task->xDummyCoreID; + #else /* configNUM_CORES > 1 */ + const BaseType_t coreID = 0; + #endif /* configNUM_CORES > 1 */ for (int i = 0; i < SOC_CPU_COPROC_NUM; i++) { StaticTask_t** owner = &port_uxCoprocOwner[coreID][i]; @@ -767,11 +771,12 @@ void vPortTCBPreDeleteHook( void *pxTCB ) * are saved lazily, as soon as a task starts using one, it must always be scheduled on the core * it is currently executing on. */ +#if ( configNUM_CORES > 1 ) void vPortTaskPinToCore(StaticTask_t* task, int coreid) { task->xDummyCoreID = coreid; } - +#endif /* configNUM_CORES > 1 */ /** * @brief Get coprocessor save area out of the given task. If the coprocessor area is not created, diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S b/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S index d80c330f46f..f63c8803728 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S @@ -185,10 +185,12 @@ rtos_save_fpu_coproc: csrr a1, fcsr sw a1, RV_FPU_FCSR(a0) rtos_save_fpu_coproc_nosave: +#if ( configNUM_CORES > 1 ) /* Pin current task to current core */ mv a0, s1 csrr a1, mhartid call vPortTaskPinToCore +#endif /* configNUM_CORES > 1 */ /* Check if we have to restore a previous FPU context from the current TCB */ mv a0, s1 call pxPortGetCoprocArea diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index a386c686090..e6af16de0ae 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -61,7 +61,7 @@ /* [refactor-todo] These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */ #include #include -#include +#include /* [refactor-todo] introduce a port wrapper function to avoid including esp_timer.h into the public header */ #if CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c b/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c index d5f82a04ea5..e1cba7ab3e6 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include "soc/soc_caps.h" #include "esp_attr.h" #include "esp_private/crosscore_int.h" @@ -52,9 +52,6 @@ _Static_assert(portBYTE_ALIGNMENT == 16, "portBYTE_ALIGNMENT must be set to 16"); -_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value"); - - /* ---------------------------------------------------- Variables ------------------------------------------------------ * - Various variables used to maintain the FreeRTOS port's state. Used from both port.c and various .S files * - Constant offsets are used by assembly to jump to particular TCB members or a stack area (such as the CPSA). We use @@ -621,8 +618,12 @@ static void vPortCleanUpCoprocArea(void *pvTCB) uxCoprocArea = ( UBaseType_t ) ( ( ( StaticTask_t * ) pvTCB )->pxDummy8 ); /* Get TCB_t.pxEndOfStack */ uxCoprocArea = STACKPTR_ALIGN_DOWN(16, uxCoprocArea - XT_CP_SIZE); - /* Get xTargetCoreID from the TCB.xCoreID */ - xTargetCoreID = ( ( StaticTask_t * ) pvTCB )->xDummyCoreID; + #if ( configNUMBER_OF_CORES > 1 ) + /* Get xTargetCoreID from the TCB.xCoreID */ + xTargetCoreID = ( ( StaticTask_t * ) pvTCB )->xDummyCoreID; + #else /* configNUMBER_OF_CORES > 1 */ + xTargetCoreID = 0; + #endif /* configNUMBER_OF_CORES > 1 */ /* If task has live floating point registers somewhere, release them */ void _xt_coproc_release(volatile void *coproc_sa_base, BaseType_t xTargetCoreID); diff --git a/components/freertos/FreeRTOS-Kernel/tasks.c b/components/freertos/FreeRTOS-Kernel/tasks.c index 3ed1b0cad5f..e550825582a 100644 --- a/components/freertos/FreeRTOS-Kernel/tasks.c +++ b/components/freertos/FreeRTOS-Kernel/tasks.c @@ -130,27 +130,29 @@ /* Macros to check if an unblocked task causes a yield on the current core. * - pxTCB is the TCB of the task to check - * - xCurCoreID is the current core's ID - * - xYieldEqualPriority indicates whether a yield should occur if the unblocked - * task's priority is equal to the priority of the task currently running on the - * current core. * - uxTaskPriority is the task's priority - * - xTaskCoreID is the task's core affinity */ + * - xYieldEqualPriority if the task having equal priority as the currently + * executing task should cause a yield. + * + * In single-core, this macro simply checks the unblocked task has a high enough + * priority to preempt the current task, and returns pdTRUE if so. + * + * In SMP, this macro checks if the unblocked task can preempt either core: + * - If a yield is required on the current core, this macro return pdTRUE + * - if a yield is required on the other core, this macro will internally + * trigger it. + */ #if ( configNUMBER_OF_CORES > 1 ) - #define taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, xYieldEqualPriority ) prvIsYieldUsingPrioritySMP( ( pxTCB )->uxPriority, ( pxTCB )->xCoreID, xCurCoreID, xYieldEqualPriority ) - #define taskIS_YIELD_REQUIRED_USING_PRIORITY( uxTaskPriority, xTaskCoreID, xCurCoreID, xYieldEqualPriority ) prvIsYieldUsingPrioritySMP( uxTaskPriority, xTaskCoreID, xCurCoreID, xYieldEqualPriority ) + #define taskIS_YIELD_REQUIRED( pxTCB, xYieldEqualPriority ) prvIsYieldRequiredSMP( ( pxTCB ), ( pxTCB )->uxPriority, xYieldEqualPriority ) + #define taskIS_YIELD_REQUIRED_USING_PRIORITY( pxTCB, uxTaskPriority, xYieldEqualPriority ) prvIsYieldRequiredSMP( ( pxTCB ), uxTaskPriority, xYieldEqualPriority ) #else - #define taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, xYieldEqualPriority ) \ + #define taskIS_YIELD_REQUIRED( pxTCB, xYieldEqualPriority ) \ ( { \ - /* xCurCoreID is unused */ \ - ( void ) xCurCoreID; \ ( ( ( pxTCB )->uxPriority + ( ( xYieldEqualPriority == pdTRUE ) ? 1 : 0 ) ) > pxCurrentTCBs[ 0 ]->uxPriority ) ? pdTRUE : pdFALSE; \ } ) - #define taskIS_YIELD_REQUIRED_USING_PRIORITY( uxTaskPriority, xTaskCoreID, xCurCoreID, xYieldEqualPriority ) \ + #define taskIS_YIELD_REQUIRED_USING_PRIORITY( pxTCB, uxTaskPriority, xYieldEqualPriority ) \ ( { \ - /* xTaskCoreID and xCurCoreID are unused */ \ - ( void ) xTaskCoreID; \ - ( void ) xCurCoreID; \ + ( void ) pxTCB; \ ( ( uxTaskPriority + ( ( xYieldEqualPriority == pdTRUE ) ? 1 : 0 ) ) >= pxCurrentTCBs[ 0 ]->uxPriority ) ? pdTRUE : pdFALSE; \ } ) #endif /* configNUMBER_OF_CORES > 1 */ @@ -158,18 +160,19 @@ /* Macros to check if a task has a compatible affinity with a particular core. * - xCore is the target core - * - xCoreID is the affinity of the task to check + * - pxTCB is the task to check * * This macro will always return true on single core as the concept of core * affinity doesn't exist. */ #if ( configNUMBER_OF_CORES > 1 ) - #define taskIS_AFFINITY_COMPATIBLE( xCore, xCoreID ) ( ( ( ( xCoreID ) == xCore ) || ( ( xCoreID ) == tskNO_AFFINITY ) ) ? pdTRUE : pdFALSE ) + #define taskIS_AFFINITY_COMPATIBLE( xCore, pxTCB ) ( ( ( ( pxTCB )->xCoreID == xCore ) || ( ( pxTCB )->xCoreID == tskNO_AFFINITY ) ) ? pdTRUE : pdFALSE ) #else - #define taskIS_AFFINITY_COMPATIBLE( xCore, xCoreID ) \ - ( { \ - /* xCoreID is unused */ \ - ( void ) xCoreID; \ - pdTRUE; \ + #define taskIS_AFFINITY_COMPATIBLE( xCore, pxTCB ) \ + ( { \ + /* xCore and pxTCB are unused */ \ + ( void ) xCore; \ + ( void ) pxTCB; \ + pdTRUE; \ } ) #endif /* configNUMBER_OF_CORES > 1 */ /*-----------------------------------------------------------*/ @@ -387,8 +390,9 @@ typedef struct tskTaskControlBlock /* The old naming convention is used to StackType_t * pxStack; /*< Points to the start of the stack. */ char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - /* Todo: Remove xCoreID for single core builds (IDF-7894) */ - BaseType_t xCoreID; /*< The core that this task is pinned to */ + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xCoreID; /*< The core that this task is pinned to */ + #endif /* configNUMBER_OF_CORES > 1 */ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ @@ -568,10 +572,9 @@ static BaseType_t prvCreateIdleTasks( void ); */ #if ( configNUMBER_OF_CORES > 1 ) - static BaseType_t prvIsYieldUsingPrioritySMP( UBaseType_t uxTaskPriority, - BaseType_t xTaskCoreID, - BaseType_t xCurCoreID, - BaseType_t xYieldEqualPriority ) PRIVILEGED_FUNCTION; + static BaseType_t prvIsYieldRequiredSMP( TCB_t * pxTCB, + UBaseType_t uxTaskPriority, + BaseType_t xYieldEqualPriority ) PRIVILEGED_FUNCTION; #endif /* configNUMBER_OF_CORES > 1 */ @@ -765,13 +768,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; #if ( configNUMBER_OF_CORES > 1 ) - static BaseType_t prvIsYieldUsingPrioritySMP( UBaseType_t uxTaskPriority, - BaseType_t xTaskCoreID, - BaseType_t xCurCoreID, - BaseType_t xYieldEqualPriority ) + static BaseType_t prvIsYieldRequiredSMP( TCB_t * pxTCB, + UBaseType_t uxTaskPriority, + BaseType_t xYieldEqualPriority ) { configASSERT( uxTaskPriority < configMAX_PRIORITIES ); + /* Save core ID as we can no longer be preempted. */ + const BaseType_t xCurCoreID = portGET_CORE_ID(); + if( xYieldEqualPriority == pdTRUE ) { /* Increment the task priority to achieve the same affect as @@ -786,7 +791,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; * priority than the current core, and the core has not suspended * scheduling, then yield the current core. * Todo: Make fair scheduling a configurable option (IDF-5772). */ - if( ( taskIS_AFFINITY_COMPATIBLE( xCurCoreID, xTaskCoreID ) == pdTRUE ) && + if( ( taskIS_AFFINITY_COMPATIBLE( xCurCoreID, pxTCB ) == pdTRUE ) && ( uxTaskPriority > pxCurrentTCBs[ xCurCoreID ]->uxPriority ) && ( uxSchedulerSuspended[ xCurCoreID ] == ( UBaseType_t ) 0U ) ) { @@ -797,7 +802,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; /* If the target task can run on the other core, and has a higher * priority then the other core, and the other core has not suspended * scheduling, then yield the other core */ - else if( ( taskIS_AFFINITY_COMPATIBLE( !xCurCoreID, xTaskCoreID ) == pdTRUE ) && + else if( ( taskIS_AFFINITY_COMPATIBLE( !xCurCoreID, pxTCB ) == pdTRUE ) && ( uxTaskPriority > pxCurrentTCBs[ !xCurCoreID ]->uxPriority ) && ( uxSchedulerSuspended[ !xCurCoreID ] == ( UBaseType_t ) 0U ) ) { @@ -967,14 +972,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, StackType_t * pxTopOfStack; UBaseType_t x; - #if ( configNUMBER_OF_CORES > 1 ) - /* Check that xCoreID is valid */ - configASSERT( ( ( xCoreID >= 0 ) && ( xCoreID < configNUMBER_OF_CORES ) ) || ( xCoreID == tskNO_AFFINITY ) ); - #else - /* Hard code xCoreID to 0 */ - xCoreID = 0; - #endif - #if ( portUSING_MPU_WRAPPERS == 1 ) /* Should the task be created in privileged mode? */ BaseType_t xRunPrivileged; @@ -1073,7 +1070,16 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, } pxNewTCB->uxPriority = uxPriority; - pxNewTCB->xCoreID = xCoreID; /* Todo: Remove xCoreID for single core builds (IDF-7894) */ + #if ( configNUMBER_OF_CORES > 1 ) + { + pxNewTCB->xCoreID = xCoreID; + } + #else /* configNUMBER_OF_CORES > 1 */ + { + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) xCoreID; + } + #endif /* configNUMBER_OF_CORES > 1 */ #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; @@ -1194,7 +1200,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) mtCOVERAGE_TEST_MARKER(); } - if( ( pxCurrentTCBs[ 0 ] == NULL ) && ( taskIS_AFFINITY_COMPATIBLE( 0, pxNewTCB->xCoreID ) == pdTRUE ) ) + if( ( pxCurrentTCBs[ 0 ] == NULL ) && ( taskIS_AFFINITY_COMPATIBLE( 0, pxNewTCB ) == pdTRUE ) ) { /* On core 0, there are no other tasks, or all the other tasks * are in the suspended state - make this the current task. */ @@ -1202,7 +1208,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) } #if ( configNUMBER_OF_CORES > 1 ) - else if( ( pxCurrentTCBs[ 1 ] == NULL ) && ( taskIS_AFFINITY_COMPATIBLE( 1, pxNewTCB->xCoreID ) == pdTRUE ) ) + else if( ( pxCurrentTCBs[ 1 ] == NULL ) && ( taskIS_AFFINITY_COMPATIBLE( 1, pxNewTCB ) == pdTRUE ) ) { /* On core 1, there are no other tasks, or all the other tasks * are in the suspended state - make this the current task. */ @@ -1217,7 +1223,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) if( xSchedulerRunning == pdFALSE ) { if( ( pxCurrentTCBs[ 0 ] != NULL ) && - ( taskIS_AFFINITY_COMPATIBLE( 0, pxNewTCB->xCoreID ) == pdTRUE ) && + ( taskIS_AFFINITY_COMPATIBLE( 0, pxNewTCB ) == pdTRUE ) && ( pxCurrentTCBs[ 0 ]->uxPriority <= pxNewTCB->uxPriority ) ) { pxCurrentTCBs[ 0 ] = pxNewTCB; @@ -1225,7 +1231,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) #if ( configNUMBER_OF_CORES > 1 ) else if( ( pxCurrentTCBs[ 1 ] != NULL ) && - ( taskIS_AFFINITY_COMPATIBLE( 1, pxNewTCB->xCoreID ) == pdTRUE ) && + ( taskIS_AFFINITY_COMPATIBLE( 1, pxNewTCB ) == pdTRUE ) && ( pxCurrentTCBs[ 1 ]->uxPriority <= pxNewTCB->uxPriority ) ) { pxCurrentTCBs[ 1 ] = pxNewTCB; @@ -1260,7 +1266,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { /* If the created task is of a higher priority than the current task * then it should run now. */ - if( taskIS_YIELD_REQUIRED( pxNewTCB, portGET_CORE_ID(), pdTRUE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxNewTCB, pdTRUE ) == pdTRUE ) { taskYIELD_IF_USING_PREEMPTION(); } @@ -1777,7 +1783,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) /* The priority of a task other than the currently * running task is being raised. Is the priority being * raised above that of the running task? */ - if( taskIS_YIELD_REQUIRED_USING_PRIORITY( uxNewPriority, pxTCB->xCoreID, portGET_CORE_ID(), pdTRUE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED_USING_PRIORITY( pxTCB, uxNewPriority, pdTRUE ) == pdTRUE ) { xYieldRequired = pdTRUE; } @@ -2106,7 +2112,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) prvAddTaskToReadyList( pxTCB ); /* A higher priority task may have just been resumed. */ - if( taskIS_YIELD_REQUIRED( pxTCB, portGET_CORE_ID(), pdTRUE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdTRUE ) == pdTRUE ) { /* This yield may not cause the task just resumed to run, * but will leave the lists in the correct state for the @@ -2177,7 +2183,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { /* Ready lists can be accessed so move the task from the * suspended list to the ready list directly. */ - if( taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, pdTRUE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdTRUE ) == pdTRUE ) { xYieldRequired = pdTRUE; @@ -2220,9 +2226,9 @@ static BaseType_t prvCreateIdleTasks( void ) BaseType_t xReturn = pdPASS; BaseType_t xCoreID; -#if ( configNUMBER_OF_CORES > 1 ) - char cIdleName[ configMAX_TASK_NAME_LEN ]; -#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + #if ( configNUMBER_OF_CORES > 1 ) + char cIdleName[ configMAX_TASK_NAME_LEN ]; + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /* Add each idle task at the lowest priority. */ for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) @@ -2328,7 +2334,6 @@ static BaseType_t prvCreateIdleTasks( void ) portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ &xIdleTaskHandle[ xCoreID ], /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ xCoreID ); - } #endif /* configSUPPORT_STATIC_ALLOCATION */ } @@ -2568,8 +2573,7 @@ BaseType_t xTaskResumeAll( void ) * appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList[ xCurCoreID ] ) == pdFALSE ) { - /* Note: Add volatile cast (IDF-8361) */ - pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( volatile List_t * ) ( &xPendingReadyList[ xCurCoreID ] ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList[ xCurCoreID ] ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); portMEMORY_BARRIER(); listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); @@ -2577,7 +2581,7 @@ BaseType_t xTaskResumeAll( void ) /* If the moved task has a priority higher than or equal to * the current task then a yield must be performed. */ - if( taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, pdTRUE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdTRUE ) == pdTRUE ) { xYieldPending[ xCurCoreID ] = pdTRUE; } @@ -3139,7 +3143,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* Preemption is on, but a context switch should only be * performed if the unblocked task has a priority that is * higher than the currently executing task. */ - if( taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, pdFALSE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdFALSE ) == pdTRUE ) { /* Pend the yield to be performed when the scheduler * is unsuspended. */ @@ -3281,7 +3285,7 @@ BaseType_t xTaskIncrementTick( void ) * 0, we only need to context switch if the unblocked * task can run on core 0 and has a higher priority * than the current task. */ - if( ( taskIS_AFFINITY_COMPATIBLE( 0, pxTCB->xCoreID ) == pdTRUE ) && ( pxTCB->uxPriority > pxCurrentTCBs[ 0 ]->uxPriority ) ) + if( ( taskIS_AFFINITY_COMPATIBLE( 0, pxTCB ) == pdTRUE ) && ( pxTCB->uxPriority > pxCurrentTCBs[ 0 ]->uxPriority ) ) { xSwitchRequired = pdTRUE; } @@ -3544,7 +3548,7 @@ BaseType_t xTaskIncrementTick( void ) } /* Check if the current task has a compatible affinity */ - if( taskIS_AFFINITY_COMPATIBLE( xCurCoreID, pxTCBCur->xCoreID ) == pdFALSE ) + if( taskIS_AFFINITY_COMPATIBLE( xCurCoreID, pxTCBCur ) == pdFALSE ) { goto get_next_task; } @@ -3860,7 +3864,7 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, listINSERT_END( &( xPendingReadyList[ uxPendCore ] ), &( pxUnblockedTCB->xEventListItem ) ); } - if( taskIS_YIELD_REQUIRED( pxUnblockedTCB, xCurCoreID, pdFALSE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxUnblockedTCB, pdFALSE ) == pdTRUE ) { /* The unblocked task requires a the current core to yield */ xReturn = pdTRUE; @@ -4045,7 +4049,7 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); prvAddTaskToReadyList( pxUnblockedTCB ); - if( taskIS_YIELD_REQUIRED( pxUnblockedTCB, xCurCoreID, pdFALSE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxUnblockedTCB, pdFALSE ) == pdTRUE ) { /* The unblocked task has a priority above that of the calling task, so * a context switch is required. This function is called with the @@ -4571,8 +4575,19 @@ static void prvCheckTasksWaitingTermination( void ) pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack; #endif pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; - /* Todo: Remove xCoreID for single core builds (IDF-7894) */ - pxTaskStatus->xCoreID = pxTCB->xCoreID; + #if ( configTASKLIST_INCLUDE_COREID == 1 ) + { + #if ( configNUMBER_OF_CORES > 1 ) + { + pxTaskStatus->xCoreID = pxTCB->xCoreID; + } + #else /* configNUMBER_OF_CORES > 1 */ + { + pxTaskStatus->xCoreID = 0; + } + #endif /* configNUMBER_OF_CORES > 1 */ + } + #endif /* configTASKLIST_INCLUDE_COREID == 1 */ #if ( configUSE_MUTEXES == 1 ) { @@ -5423,8 +5438,16 @@ static void prvResetNextTaskUnblockTime( void ) pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); /* Write the rest of the string. */ - sprintf( pcWriteBuffer, "\t%c\t%u\t%d\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, pxTaskStatusArray[ x ].xCoreID, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ - pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + #if ( configTASKLIST_INCLUDE_COREID == 1 ) + { + sprintf( pcWriteBuffer, "\t%c\t%u\t%d\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].xCoreID, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #else /* configTASKLIST_INCLUDE_COREID == 1 */ + { + sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif /* configTASKLIST_INCLUDE_COREID == 1 */ + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ } /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION @@ -5885,7 +5908,7 @@ TickType_t uxTaskResetEventItemValue( void ) } #endif - if( taskIS_YIELD_REQUIRED( pxTCB, portGET_CORE_ID(), pdFALSE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdFALSE ) == pdTRUE ) { /* The notified task has a priority above the currently * executing task so a yield is required. */ @@ -6023,7 +6046,7 @@ TickType_t uxTaskResetEventItemValue( void ) listINSERT_END( &( xPendingReadyList[ xCurCoreID ] ), &( pxTCB->xEventListItem ) ); } - if( taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, pdFALSE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdFALSE ) == pdTRUE ) { /* The notified task has a priority above the currently * executing task so a yield is required. */ @@ -6117,7 +6140,7 @@ TickType_t uxTaskResetEventItemValue( void ) listINSERT_END( &( xPendingReadyList[ xCurCoreID ] ), &( pxTCB->xEventListItem ) ); } - if( taskIS_YIELD_REQUIRED( pxTCB, xCurCoreID, pdFALSE ) == pdTRUE ) + if( taskIS_YIELD_REQUIRED( pxTCB, pdFALSE ) == pdTRUE ) { /* The notified task has a priority above the currently * executing task so a yield is required. */ diff --git a/components/freertos/FreeRTOS-Kernel/timers.c b/components/freertos/FreeRTOS-Kernel/timers.c index 084c7d9b48b..c0e55d58c9b 100644 --- a/components/freertos/FreeRTOS-Kernel/timers.c +++ b/components/freertos/FreeRTOS-Kernel/timers.c @@ -66,12 +66,25 @@ #define tmrNO_DELAY ( ( TickType_t ) 0U ) #define tmrMAX_TIME_BEFORE_OVERFLOW ( ( TickType_t ) -1 ) -/* The name assigned to the timer service task. This can be overridden by - * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ +/* The name assigned to the timer service task. This can be overridden by + * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ #ifndef configTIMER_SERVICE_TASK_NAME #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" #endif + #if ( configNUMBER_OF_CORES > 1 ) + +/* The core affinity assigned to the timer service task on SMP systems. + * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY + #define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY + #endif + + #if ( !( ( configTIMER_SERVICE_TASK_CORE_AFFINITY == 0x0 ) || ( configTIMER_SERVICE_TASK_CORE_AFFINITY == 0x1 ) || ( configTIMER_SERVICE_TASK_CORE_AFFINITY == 0x7FFFFFFF /* tskNO_AFFINITY */ ) ) ) + #error Invalid Timer task affinity. Timer task core ID can only be 0x0, 0x1 or 0x7FFFFFFF (tskNO_AFFINITY). + #endif /* #if ( !( ( configTIMER_SERVICE_TASK_CORE_AFFINITY == 0x0 ) || ( configTIMER_SERVICE_TASK_CORE_AFFINITY == 0x01 ) || ( configTIMER_SERVICE_TASK_CORE_AFFINITY == 0x7FFFFFFF ) ) ) */ + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + /* Bit definitions used in the ucStatus member of a timer structure. */ #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) @@ -252,40 +265,78 @@ if( xTimerQueue != NULL ) { - #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + /* The following code block to set the timer task core affinity has been picked up from the FreeRTOS-Kernel + * upstream repository. Commit# 631ae9e6e4828cf5c7d58bb7ac78a64fc309bcb7. + * Necessary changes have been made for IDF-FreeRTOS compatibility. */ + #if ( configNUMBER_OF_CORES > 1 ) { - StaticTask_t * pxTimerTaskTCBBuffer = NULL; - StackType_t * pxTimerTaskStackBuffer = NULL; - uint32_t ulTimerTaskStackSize; - - /* Timer tasks is always pinned to core 0. Todo: IDF-7906 */ - vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); - xTimerTaskHandle = xTaskCreateStaticPinnedToCore( prvTimerTask, - configTIMER_SERVICE_TASK_NAME, - ulTimerTaskStackSize, - NULL, - ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, - pxTimerTaskStackBuffer, - pxTimerTaskTCBBuffer, - 0 ); - - if( xTimerTaskHandle != NULL ) + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStaticPinnedToCore( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer, + configTIMER_SERVICE_TASK_CORE_AFFINITY ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ { - xReturn = pdPASS; + xReturn = xTaskCreatePinnedToCore( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle, + configTIMER_SERVICE_TASK_CORE_AFFINITY ); } + #endif /* configSUPPORT_STATIC_ALLOCATION */ } - #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ { - /* Timer tasks is always pinned to core 0. Todo: IDF-7906 */ - xReturn = xTaskCreatePinnedToCore( prvTimerTask, - configTIMER_SERVICE_TASK_NAME, - configTIMER_TASK_STACK_DEPTH, - NULL, - ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, - &xTimerTaskHandle, - 0 ); + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ } - #endif /* configSUPPORT_STATIC_ALLOCATION */ + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ } else { diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig index d8ca79b487c..af2b9f0ac27 100644 --- a/components/freertos/Kconfig +++ b/components/freertos/Kconfig @@ -166,6 +166,27 @@ menu "FreeRTOS" help Sets the timer task's name (see configTIMER_SERVICE_TASK_NAME documentation for more details). + choice FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY + prompt "configTIMER_SERVICE_TASK_CORE_AFFINITY" + default FREERTOS_TIMER_TASK_NO_AFFINITY + help + Sets the timer task's core affinity (see configTIMER_SERVICE_TASK_CORE_AFFINITY documentation for more details). + + config FREERTOS_TIMER_TASK_AFFINITY_CPU0 + bool "CPU0" + config FREERTOS_TIMER_TASK_AFFINITY_CPU1 + bool "CPU1" + depends on !FREERTOS_UNICORE + config FREERTOS_TIMER_TASK_NO_AFFINITY + bool "No affinity" + endchoice + + config FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY + hex + default 0x0 if FREERTOS_TIMER_TASK_AFFINITY_CPU0 + default 0x1 if FREERTOS_TIMER_TASK_AFFINITY_CPU1 + default FREERTOS_NO_AFFINITY if FREERTOS_TIMER_TASK_NO_AFFINITY + config FREERTOS_TIMER_TASK_PRIORITY int "configTIMER_TASK_PRIORITY" range 1 25 @@ -224,6 +245,13 @@ menu "FreeRTOS" ``vTaskList()`` and ``vTaskGetRunTimeStats()`` functions in the build (see configUSE_STATS_FORMATTING_FUNCTIONS documentation for more details). + config FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES + bool "configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES" + #TODO: Enable by default for debug builds (IDF-8517) + default n + help + Enable list integrity checker (see configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES documentation for more details). + config FREERTOS_VTASKLIST_INCLUDE_COREID # Core affinity is supported in stats for Amazon FreeRTOS SMP by default bool "Enable display of xCoreID in vTaskList" diff --git a/components/freertos/config/include/freertos/FreeRTOSConfig.h b/components/freertos/config/include/freertos/FreeRTOSConfig.h index c8e7922615d..d60a1650871 100644 --- a/components/freertos/config/include/freertos/FreeRTOSConfig.h +++ b/components/freertos/config/include/freertos/FreeRTOSConfig.h @@ -180,11 +180,16 @@ /* ------------------- Software Timer ---------------------- */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY -#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH -#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH -#define configTIMER_SERVICE_TASK_NAME CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define configTIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define configTIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define configTIMER_SERVICE_TASK_NAME CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME +#define configTIMER_SERVICE_TASK_CORE_AFFINITY CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY + +/* ------------------------ List --------------------------- */ + +#define configLIST_VOLATILE volatile /* We define List elements as volatile to prevent the compiler from optimizing out essential code */ /* -------------------- API Includes ----------------------- */ @@ -247,6 +252,9 @@ #endif /* CONFIG_FREERTOS_SMP */ #endif /* def __ASSEMBLER__ */ +/* -------------- List Data Integrity Checks --------------- */ +#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES + /* ----------------------------------------------- Amazon SMP FreeRTOS ------------------------------------------------- * - All Amazon SMP FreeRTOS specific configurations * ------------------------------------------------------------------------------------------------------------------ */ diff --git a/components/freertos/esp_additions/freertos_tasks_c_additions.h b/components/freertos/esp_additions/freertos_tasks_c_additions.h index dc8cde3522e..ce15b52f0cd 100644 --- a/components/freertos/esp_additions/freertos_tasks_c_additions.h +++ b/components/freertos/esp_additions/freertos_tasks_c_additions.h @@ -29,9 +29,7 @@ */ _Static_assert( offsetof( StaticTask_t, pxDummy6 ) == offsetof( TCB_t, pxStack ) ); _Static_assert( offsetof( StaticTask_t, pxDummy8 ) == offsetof( TCB_t, pxEndOfStack ) ); -#if CONFIG_FREERTOS_SMP - _Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "CONFIG_FREERTOS_NO_AFFINITY must be the same as tskNO_AFFINITY" ); -#endif /* CONFIG_FREERTOS_SMP */ +_Static_assert( tskNO_AFFINITY == ( BaseType_t ) CONFIG_FREERTOS_NO_AFFINITY, "CONFIG_FREERTOS_NO_AFFINITY must be the same as tskNO_AFFINITY" ); /* ------------------------------------------------- Kernel Control ------------------------------------------------- */ @@ -177,6 +175,8 @@ _Static_assert( offsetof( StaticTask_t, pxDummy8 ) == offsetof( TCB_t, pxEndOfSt { BaseType_t xReturn; + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE || xCoreID == tskNO_AFFINITY ); + #if CONFIG_FREERTOS_SMP { /* If using Amazon SMP FreeRTOS. This function is just a wrapper around @@ -311,6 +311,10 @@ _Static_assert( offsetof( StaticTask_t, pxDummy8 ) == offsetof( TCB_t, pxEndOfSt { TaskHandle_t xReturn; + configASSERT( portVALID_STACK_MEM( puxStackBuffer ) ); + configASSERT( portVALID_TCB_MEM( pxTaskBuffer ) ); + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE || xCoreID == tskNO_AFFINITY ); + #if CONFIG_FREERTOS_SMP { /* If using Amazon SMP FreeRTOS. This function is just a wrapper around @@ -320,6 +324,10 @@ _Static_assert( offsetof( StaticTask_t, pxDummy8 ) == offsetof( TCB_t, pxEndOfSt /* Convert xCoreID into an affinity mask */ UBaseType_t uxCoreAffinityMask; + /* Bit shifting << xCoreID is only valid if we have less than + * 32 cores. */ + ESP_STATIC_ASSERT( configNUM_CORES < 32 ); + if( xCoreID == tskNO_AFFINITY ) { uxCoreAffinityMask = tskNO_AFFINITY; @@ -341,10 +349,6 @@ _Static_assert( offsetof( StaticTask_t, pxDummy8 ) == offsetof( TCB_t, pxEndOfSt { TCB_t * pxNewTCB; - configASSERT( portVALID_STACK_MEM( puxStackBuffer ) ); - configASSERT( portVALID_TCB_MEM( pxTaskBuffer ) ); - configASSERT( ( ( xCoreID >= 0 ) && ( xCoreID < configNUM_CORES ) ) || ( xCoreID == tskNO_AFFINITY ) ); - #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a @@ -460,7 +464,7 @@ BaseType_t xTaskGetCoreID( TaskHandle_t xTask ) { /* If xTaskGetIdleTaskHandle() is called before the scheduler has been * started, then xIdleTaskHandle will be NULL. */ - configASSERT( ( xCoreID < configNUMBER_OF_CORES ) && ( xCoreID != tskNO_AFFINITY ) ); + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); configASSERT( ( xIdleTaskHandle[ xCoreID ] != NULL ) ); return xIdleTaskHandle[ xCoreID ]; } @@ -474,15 +478,14 @@ BaseType_t xTaskGetCoreID( TaskHandle_t xTask ) { TaskHandle_t xReturn; + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); + #if ( CONFIG_FREERTOS_SMP ) { xReturn = xTaskGetCurrentTaskHandleCPU( ( UBaseType_t ) xCoreID ); } #else /* CONFIG_FREERTOS_SMP */ { - configASSERT( xCoreID < configNUMBER_OF_CORES ); - configASSERT( xCoreID != tskNO_AFFINITY ); - /* A critical section is not required as this function does not * guarantee that the TCB will still be valid when this function * returns. */ @@ -502,8 +505,7 @@ BaseType_t xTaskGetCoreID( TaskHandle_t xTask ) { uint32_t ulRunTimeCounter; - configASSERT( xCoreID < configNUMBER_OF_CORES ); - configASSERT( xCoreID != tskNO_AFFINITY ); + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); /* For SMP, we need to take the kernel lock here as we are about to * access kernel data structures. */ @@ -526,8 +528,7 @@ BaseType_t xTaskGetCoreID( TaskHandle_t xTask ) { configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn; - configASSERT( xCoreID < configNUMBER_OF_CORES ); - configASSERT( xCoreID != tskNO_AFFINITY ); + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE(); @@ -1103,7 +1104,10 @@ UBaseType_t uxTaskGetSnapshotAll( TaskSnapshot_t * const pxTaskSnapshotArray, pxCurTaskList = pxGetNextTaskList( pxCurTaskList ); } - *pxTCBSize = sizeof( TCB_t ); + if (pxTCBSize != NULL) { + *pxTCBSize = sizeof( TCB_t ); + } + return uxArrayNumFilled; } /*----------------------------------------------------------*/ @@ -1114,7 +1118,8 @@ void * pvTaskGetCurrentTCBForCore( BaseType_t xCoreID ) { void * pvRet; - configASSERT( ( xCoreID >= 0 ) && ( xCoreID < configNUM_CORES ) ); + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); + #if CONFIG_FREERTOS_SMP /* SMP FreeRTOS defines pxCurrentTCB as a macro function call */ pvRet = ( void * ) pxCurrentTCB; @@ -1192,6 +1197,11 @@ void * pvTaskGetCurrentTCBForCore( BaseType_t xCoreID ) configASSERT( uxStackMemoryCaps & ( MALLOC_CAP_8BIT ) ); configASSERT( ( uxStackMemoryCaps & MALLOC_CAP_SPIRAM ) || ( uxStackMemoryCaps & MALLOC_CAP_INTERNAL ) ); + #if ( !CONFIG_FREERTOS_SMP ) + { + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE || xCoreID == tskNO_AFFINITY ); + } + #endif /* !CONFIG_FREERTOS_SMP */ /* Allocate space for the stack used by the task being created. */ pxStack = heap_caps_malloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), uxStackMemoryCaps ); diff --git a/components/freertos/esp_additions/include/esp_private/freertos_debug.h b/components/freertos/esp_additions/include/esp_private/freertos_debug.h index dcf77dddbc3..40ba028d7e5 100644 --- a/components/freertos/esp_additions/include/esp_private/freertos_debug.h +++ b/components/freertos/esp_additions/include/esp_private/freertos_debug.h @@ -73,7 +73,7 @@ BaseType_t vTaskGetSnapshot( TaskHandle_t pxTask, * does not acquire any locks. * @param[out] pxTaskSnapshotArray Array of TaskSnapshot_t structures filled by this function * @param[in] uxArrayLength Length of the provided array - * @param[out] pxTCBSize Size of the a task's TCB structure + * @param[out] pxTCBSize Size of the a task's TCB structure (can be set to NULL) * @return UBaseType_t */ UBaseType_t uxTaskGetSnapshotAll( TaskSnapshot_t * const pxTaskSnapshotArray, diff --git a/components/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h b/components/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h index 2d520f8d3fa..316c332976d 100644 --- a/components/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h +++ b/components/freertos/esp_additions/include/esp_private/freertos_idf_additions_priv.h @@ -314,8 +314,8 @@ * should be set to ( 2 | portPRIVILEGE_BIT ). * * @param xCoreID (only IDF SMP FreeRTOS) - * The core to which the task is pinned to, or tskNO_AFFINITY if - * the task can run on any core. + * The core to which the task is pinned to, or tskNO_AFFINITY if the task has no + * core affinity. * * @param uxCoreAffinityMask (only Amazon SMP FreeRTOS) * A bitwise value that indicates the cores on which the task can run. diff --git a/components/freertos/esp_additions/include/freertos/idf_additions.h b/components/freertos/esp_additions/include/freertos/idf_additions.h index f230fc02bd5..6c989f05bec 100644 --- a/components/freertos/esp_additions/include/freertos/idf_additions.h +++ b/components/freertos/esp_additions/include/freertos/idf_additions.h @@ -43,7 +43,8 @@ * task. The task's pinned core is specified by the xCoreID argument. If xCoreID * is set to tskNO_AFFINITY, then the task is unpinned and can run on any core. * - * @note If ( configNUM_CORES == 1 ), xCoreID is ignored. + * @note If ( configNUMBER_OF_CORES == 1 ), setting xCoreID to tskNO_AFFINITY will be + * be treated as 0. * * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. @@ -55,7 +56,7 @@ * @param pxCreatedTask Used to pass back a handle by which the created task can * be referenced. * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if - * the task has no core affinity + * the task has no core affinity. * @return pdPASS if the task was successfully created and added to a ready * list, otherwise an error code defined in the file projdefs.h */ @@ -79,7 +80,8 @@ * xCoreID is set to tskNO_AFFINITY, then the task is unpinned and can run on any * core. * - * @note If ( configNUM_CORES == 1 ), xCoreID is ignored. + * @note If ( configNUMBER_OF_CORES == 1 ), setting xCoreID to tskNO_AFFINITY will be + * be treated as 0. * * @param pxTaskCode Pointer to the task entry function. * @param pcName A descriptive name for the task. @@ -93,7 +95,7 @@ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will * then be used to hold the task's data structures, * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if - * the task has no core affinity + * the task has no core affinity. * @return The task handle if the task was created, NULL otherwise. */ TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, @@ -129,15 +131,6 @@ */ BaseType_t xTaskGetCoreID( TaskHandle_t xTask ); -/** @cond */ -/* Todo: Deprecate this API in favor of xTaskGetIdleTaskHandleForCore (IDF-8163) */ -static inline __attribute__( ( always_inline ) ) -BaseType_t xTaskGetAffinity( TaskHandle_t xTask ) -{ - return xTaskGetCoreID( xTask ); -} -/** @endcond */ - /** * @brief Get the handle of idle task for the given core. * @@ -150,15 +143,6 @@ BaseType_t xTaskGetAffinity( TaskHandle_t xTask ) */ TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ); -/** @cond */ -/* Todo: Deprecate this API in favor of xTaskGetIdleTaskHandleForCore (IDF-8163) */ -static inline __attribute__( ( always_inline ) ) -TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ) -{ - return xTaskGetIdleTaskHandleForCore( xCoreID ); -} -/** @endcond */ - /** * @brief Get the handle of the task currently running on a certain core * @@ -175,14 +159,6 @@ TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ) */ TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ); -/** @cond */ -/* Todo: Deprecate this API in favor of xTaskGetCurrentTaskHandleForCore (IDF-8163) */ -static inline __attribute__( ( always_inline ) ) -TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ) -{ - return xTaskGetCurrentTaskHandleForCore( xCoreID ); -} -/** @endcond */ #if ( !CONFIG_FREERTOS_SMP && ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) @@ -644,6 +620,32 @@ void vStreamBufferGenericDeleteWithCaps( StreamBufferHandle_t xStreamBuffer, #endif /* configSUPPORT_STATIC_ALLOCATION == 1 */ + +/* --------------------------------------------------- Deprecated ------------------------------------------------------ + * Deprecated IDF FreeRTOS API additions. + * Todo: Remove in v6.0 (IDF-8499) + * ------------------------------------------------------------------------------------------------------------------ */ + +/** @cond */ +static inline __attribute__( ( always_inline, deprecated( "This function is deprecated and will be removed in ESP-IDF 6.0. Please use xTaskGetCoreID() instead." ) ) ) +BaseType_t xTaskGetAffinity( TaskHandle_t xTask ) +{ + return xTaskGetCoreID( xTask ); +} + +static inline __attribute__( ( always_inline, deprecated( "This function is deprecated and will be removed in ESP-IDF 6.0. Please use xTaskGetIdleTaskHandleForCore() instead." ) ) ) +TaskHandle_t xTaskGetIdleTaskHandleForCPU( BaseType_t xCoreID ) +{ + return xTaskGetIdleTaskHandleForCore( xCoreID ); +} + +static inline __attribute__( ( always_inline, deprecated( "This function is deprecated and will be removed in ESP-IDF 6.0. Please use xTaskGetCurrentTaskHandleForCore() instead." ) ) ) +TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t xCoreID ) +{ + return xTaskGetCurrentTaskHandleForCore( xCoreID ); +} +/** @endcond */ + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/components/freertos/port_systick.c b/components/freertos/port_systick.c index cc2fa3fc52a..20be1b87471 100644 --- a/components/freertos/port_systick.c +++ b/components/freertos/port_systick.c @@ -72,7 +72,12 @@ void vSystimerSetup(void) ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL)); if (cpuid == 0) { - periph_module_enable(PERIPH_SYSTIMER_MODULE); + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_SYSTIMER_MODULE, ref_count) { + if (ref_count == 0) { + systimer_ll_enable_bus_clock(true); + systimer_ll_reset_register(); + } + } systimer_hal_init(&systimer_hal); systimer_hal_tick_rate_ops_t ops = { .ticks_to_us = systimer_ticks_to_us, diff --git a/components/freertos/test_apps/freertos/kernel/CMakeLists.txt b/components/freertos/test_apps/freertos/kernel/CMakeLists.txt index cf385fa395a..f8ab455c508 100644 --- a/components/freertos/test_apps/freertos/kernel/CMakeLists.txt +++ b/components/freertos/test_apps/freertos/kernel/CMakeLists.txt @@ -19,5 +19,5 @@ set(priv_include_dirs # the final elf, the component can be registered as WHOLE_ARCHIVE idf_component_register(SRC_DIRS ${src_dirs} PRIV_INCLUDE_DIRS ${priv_include_dirs} - PRIV_REQUIRES test_utils esp_timer driver + PRIV_REQUIRES test_utils driver WHOLE_ARCHIVE) diff --git a/components/freertos/test_apps/freertos/kernel/queue/test_freertos_backported_functions.c b/components/freertos/test_apps/freertos/kernel/queue/test_freertos_backported_functions.c index 17a73c35258..2ca77ad31ea 100644 --- a/components/freertos/test_apps/freertos/kernel/queue/test_freertos_backported_functions.c +++ b/components/freertos/test_apps/freertos/kernel/queue/test_freertos_backported_functions.c @@ -184,7 +184,7 @@ TEST_CASE("Test FreeRTOS static task allocation", "[freertos]") (StaticTask_t *)&task_buffer, core); vTaskDelay(5); //Allow for static task to run, delete, and idle to clean up TEST_ASSERT_NOT_EQUAL(NULL, handle); //Check static task was successfully allocated - TEST_ASSERT_TRUE(has_run[core]) //Check static task has run + TEST_ASSERT_TRUE(has_run[core]); //Check static task has run } } diff --git a/components/freertos/test_apps/freertos/kernel/queue/test_freertos_debug_functions.c b/components/freertos/test_apps/freertos/kernel/queue/test_freertos_debug_functions.c index 491f035aa55..964c7bae49f 100644 --- a/components/freertos/test_apps/freertos/kernel/queue/test_freertos_debug_functions.c +++ b/components/freertos/test_apps/freertos/kernel/queue/test_freertos_debug_functions.c @@ -77,7 +77,7 @@ TEST_CASE("Test FreeRTOS Queue Registry", "[freertos]") } for(int i = 0; i < NO_OF_QUEUES_TOTAL; i++){ const char *addr = pcQueueGetName(handles[i]); - TEST_ASSERT(addr == names[i]) //Check vQueueAddToRegistry was successful + TEST_ASSERT(addr == names[i]); //Check vQueueAddToRegistry was successful } portDISABLE_INTERRUPTS(); @@ -90,7 +90,7 @@ TEST_CASE("Test FreeRTOS Queue Registry", "[freertos]") } for(int i = 0; i < NO_OF_QUEUES_TOTAL; i++){ const char *addr = pcQueueGetName(handles[i]); - TEST_ASSERT(addr == NULL) //Check vQueueUnregisterQueue was successful + TEST_ASSERT(addr == NULL); //Check vQueueUnregisterQueue was successful handles[i] = NULL; } diff --git a/components/freertos/test_apps/freertos/kernel/stream_buffer/test_stream_buffers.c b/components/freertos/test_apps/freertos/kernel/stream_buffer/test_stream_buffers.c index f7acea50a0c..c2c8961323e 100644 --- a/components/freertos/test_apps/freertos/kernel/stream_buffer/test_stream_buffers.c +++ b/components/freertos/test_apps/freertos/kernel/stream_buffer/test_stream_buffers.c @@ -61,8 +61,16 @@ TEST_CASE("Stream Buffer: Send-receive tasks", "[freertos]") test_args.done_sem = xSemaphoreCreateCounting(2, 0); TEST_ASSERT_NOT_NULL(test_args.stream_buffer); TEST_ASSERT_NOT_NULL(test_args.done_sem); - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(sender_task, "sender", 4096, &test_args, UNITY_FREERTOS_PRIORITY + 2, NULL, 0)); - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(receiver_task, "receiver", 4096, &test_args, UNITY_FREERTOS_PRIORITY + 1, NULL, 1)); + BaseType_t sender_core_id; + BaseType_t receiver_core_id; + sender_core_id = 0; + #if CONFIG_FREERTOS_UNICORE + receiver_core_id = 0; + #else + receiver_core_id = 1; + #endif + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(sender_task, "sender", 4096, &test_args, UNITY_FREERTOS_PRIORITY + 2, NULL, sender_core_id)); + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(receiver_task, "receiver", 4096, &test_args, UNITY_FREERTOS_PRIORITY + 1, NULL, receiver_core_id)); // Wait for both tasks to complete for (int i = 0; i < 2; i++) { diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c index 93919f676cb..872589347bb 100644 --- a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c +++ b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c @@ -107,7 +107,7 @@ typedef struct { static void task_report_corenum(void *arg) { report_corenum_info_t *info = (report_corenum_info_t*) arg; - info->recorded_core_num = xTaskGetAffinity(NULL); + info->recorded_core_num = xTaskGetCoreID(NULL); xTaskNotifyGive(info->parent_handle); vTaskSuspend(NULL); } diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_trace_utilities.c b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_trace_utilities.c index bce8992127d..116504dd37e 100644 --- a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_trace_utilities.c +++ b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_trace_utilities.c @@ -47,13 +47,13 @@ void task_test_trace_utilities(void *arg) //Tests on this core TEST_ASSERT(uxTaskGetTaskNumber(task_handles[core]) == (0x0F << (core))); TEST_ASSERT(uxQueueGetQueueNumber(test_queues[core]) == (0x0F << (core))); - TEST_ASSERT(ucQueueGetQueueType(test_queues[core]) == BIN_SEM_QUEUE_TYPE) + TEST_ASSERT(ucQueueGetQueueType(test_queues[core]) == BIN_SEM_QUEUE_TYPE); //Test on other core #ifndef CONFIG_FREERTOS_UNICORE TEST_ASSERT(uxTaskGetTaskNumber(task_handles[!core]) == (0x0F << (!core))); TEST_ASSERT(uxQueueGetQueueNumber(test_queues[!core]) == (0x0F << (!core))); - TEST_ASSERT(ucQueueGetQueueType(test_queues[!core]) == BIN_SEM_QUEUE_TYPE) + TEST_ASSERT(ucQueueGetQueueType(test_queues[!core]) == BIN_SEM_QUEUE_TYPE); #endif xSemaphoreGive(test_queues[core]); //Signal done diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_task_suspend_resume.c b/components/freertos/test_apps/freertos/kernel/tasks/test_task_suspend_resume.c index a961761a50d..be6faedbe3c 100644 --- a/components/freertos/test_apps/freertos/kernel/tasks/test_task_suspend_resume.c +++ b/components/freertos/test_apps/freertos/kernel/tasks/test_task_suspend_resume.c @@ -17,12 +17,7 @@ #include "unity.h" #include "test_utils.h" #include "driver/gptimer.h" -#ifndef CONFIG_FREERTOS_UNICORE -#include "esp_ipc.h" -#endif -#include "esp_freertos_hooks.h" #include "esp_rom_sys.h" -#include "esp_timer.h" /* Counter task counts a target variable forever */ static void task_count(void *vp_counter) @@ -210,197 +205,4 @@ TEST_CASE("Resume task from ISR (other core)", "[freertos]") { test_resume_task_from_isr(!UNITY_FREERTOS_CPU); } - -#if !CONFIG_FREERTOS_SMP -/* -Scheduler suspension behavior has changed in SMP FreeRTOS, thus these test are disabled for SMP FreeRTOS. -See IDF-5201 -*/ - -static volatile bool block; -static bool suspend_both_cpus; - -static void IRAM_ATTR suspend_scheduler_while_block_set(void *arg) -{ - vTaskSuspendAll(); - - while (block) { }; - esp_rom_delay_us(1); - xTaskResumeAll(); -} - -static void IRAM_ATTR suspend_scheduler_on_both_cpus(void) -{ - block = true; - if (suspend_both_cpus) { - TEST_ESP_OK(esp_ipc_call((xPortGetCoreID() == 0) ? 1 : 0, &suspend_scheduler_while_block_set, NULL)); - } - - vTaskSuspendAll(); -} - -static void IRAM_ATTR resume_scheduler_on_both_cpus(void) -{ - block = false; - xTaskResumeAll(); -} - -static const int waiting_ms = 2000; -static const int delta_ms = 100; -static int duration_wait_task_ms; -static int duration_ctrl_task_ms; - -static void waiting_task(void *pvParameters) -{ - int cpu_id = xPortGetCoreID(); - int64_t start_time = esp_timer_get_time(); - printf("Start waiting_task cpu=%d\n", cpu_id); - - vTaskDelay(waiting_ms / portTICK_PERIOD_MS); - - duration_wait_task_ms = (esp_timer_get_time() - start_time) / 1000; - printf("Finish waiting_task cpu=%d, time=%d ms\n", cpu_id, duration_wait_task_ms); - vTaskDelete(NULL); -} - -static void control_task(void *pvParameters) -{ - int cpu_id = xPortGetCoreID(); - esp_rom_delay_us(2000); // let to start the waiting_task first - printf("Start control_task cpu=%d\n", cpu_id); - int64_t start_time = esp_timer_get_time(); - - suspend_scheduler_on_both_cpus(); - esp_rom_delay_us(waiting_ms * 1000 + delta_ms * 1000); - resume_scheduler_on_both_cpus(); - - duration_ctrl_task_ms = (esp_timer_get_time() - start_time) / 1000; - printf("Finish control_task cpu=%d, time=%d ms\n", cpu_id, duration_ctrl_task_ms); - vTaskDelete(NULL); -} - -static void test_scheduler_suspend1(int cpu) -{ - /* This test tests a case then both CPUs were in suspend state and then resume CPUs back. - * A task for which a wait time has been set and this time has elapsed in the suspended state should in any case be ready to start. - * (In an old implementation of xTaskIncrementTick function the counting for waiting_task() will be continued - * (excluding time in suspended) after control_task() is finished.) - */ - duration_wait_task_ms = 0; - duration_ctrl_task_ms = 0; - - printf("Test for CPU%d\n", cpu); - int other_cpu = (cpu == 0) ? 1 : 0; - xTaskCreatePinnedToCore(&waiting_task, "waiting_task", 8192, NULL, 5, NULL, other_cpu); - xTaskCreatePinnedToCore(&control_task, "control_task", 8192, NULL, 5, NULL, cpu); - - vTaskDelay(waiting_ms * 2 / portTICK_PERIOD_MS); - TEST_ASSERT_INT_WITHIN(4, waiting_ms + delta_ms + 4, duration_ctrl_task_ms); - if (suspend_both_cpus == false && cpu == 1) { - // CPU0 continues to increase the TickCount and the wait_task does not depend on Suspended Scheduler on CPU1 - TEST_ASSERT_INT_WITHIN(2, waiting_ms, duration_wait_task_ms); - } else { - TEST_ASSERT_INT_WITHIN(4, waiting_ms + delta_ms + 4, duration_wait_task_ms); - } - - printf("\n"); -} - -TEST_CASE("Test the waiting task not missed due to scheduler suspension on both CPUs", "[freertos]") -{ - printf("Suspend both CPUs:\n"); - suspend_both_cpus = true; - test_scheduler_suspend1(0); - test_scheduler_suspend1(1); -} - -TEST_CASE("Test the waiting task not missed due to scheduler suspension on one CPU", "[freertos]") -{ - printf("Suspend only one CPU:\n"); - suspend_both_cpus = false; - test_scheduler_suspend1(0); - test_scheduler_suspend1(1); -} - -static uint32_t tick_hook_ms[2]; - -static void IRAM_ATTR tick_hook(void) -{ - tick_hook_ms[xPortGetCoreID()] += portTICK_PERIOD_MS; -} - -static void test_scheduler_suspend2(int cpu) -{ - esp_register_freertos_tick_hook_for_cpu(tick_hook, 0); - esp_register_freertos_tick_hook_for_cpu(tick_hook, 1); - - memset(tick_hook_ms, 0, sizeof(tick_hook_ms)); - - printf("Test for CPU%d\n", cpu); - xTaskCreatePinnedToCore(&control_task, "control_task", 8192, NULL, 5, NULL, cpu); - - vTaskDelay(waiting_ms * 2 / portTICK_PERIOD_MS); - esp_deregister_freertos_tick_hook(tick_hook); - - printf("tick_hook_ms[cpu0] = %"PRIu32", tick_hook_ms[cpu1] = %"PRIu32"\n", tick_hook_ms[0], tick_hook_ms[1]); - - TEST_ASSERT_INT_WITHIN(portTICK_PERIOD_MS * 2, waiting_ms * 2, tick_hook_ms[0]); - TEST_ASSERT_INT_WITHIN(portTICK_PERIOD_MS * 2, waiting_ms * 2, tick_hook_ms[1]); - printf("\n"); -} - -TEST_CASE("Test suspend-resume CPU. The number of tick_hook should be the same for both CPUs", "[freertos]") -{ - printf("Suspend both CPUs:\n"); - suspend_both_cpus = true; - test_scheduler_suspend2(0); - test_scheduler_suspend2(1); - - printf("Suspend only one CPU:\n"); - suspend_both_cpus = false; - test_scheduler_suspend2(0); - test_scheduler_suspend2(1); -} - -static int duration_timer_ms; - -static void timer_callback(TimerHandle_t arg) -{ - duration_timer_ms += portTICK_PERIOD_MS; -} - -static void test_scheduler_suspend3(int cpu) -{ - duration_timer_ms = 0; - duration_ctrl_task_ms = 0; - - printf("Test for CPU%d\n", cpu); - TimerHandle_t count_time = xTimerCreate("count_time", 1, pdTRUE, NULL, timer_callback); - xTimerStart( count_time, portMAX_DELAY); - xTaskCreatePinnedToCore(&control_task, "control_task", 8192, NULL, 5, NULL, cpu); - - vTaskDelay(waiting_ms * 2 / portTICK_PERIOD_MS); - xTimerDelete(count_time, portMAX_DELAY); - printf("Finish duration_timer_ms=%d ms\n", duration_timer_ms); - - TEST_ASSERT_INT_WITHIN(2, waiting_ms * 2, duration_timer_ms); - TEST_ASSERT_INT_WITHIN(5, waiting_ms + delta_ms, duration_ctrl_task_ms); - - printf("\n"); -} - -/* Temporarily disabled due to failure with FreeRTOS v10.5.1 (IDF-8364) */ -TEST_CASE("Test suspend-resume CPU works with xTimer", "[freertos][ignore]") -{ - printf("Suspend both CPUs:\n"); - suspend_both_cpus = true; - test_scheduler_suspend3(0); - test_scheduler_suspend3(1); - - printf("Suspend only one CPU:\n"); - suspend_both_cpus = false; - test_scheduler_suspend3(0); - test_scheduler_suspend3(1); -} #endif // CONFIG_FREERTOS_UNICORE -#endif // !CONFIG_FREERTOS_SMP diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c b/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c index 073b6efb1ca..1dc48cd8083 100644 --- a/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c +++ b/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c @@ -595,7 +595,7 @@ static void test_pended_running_task(void *arg) // While tasks which do not have affinity to the current core are unblocked. for (int i = 0; i < TEST_PENDED_NUM_BLOCKED_TASKS; i++) { // Note: We use eBlocked instead of eReady due to a bug in eTaskGetState(). See (IDF-5543) - if (xTaskGetAffinity(blkd_tsks[i]) == xPortGetCoreID()) { + if (xTaskGetCoreID(blkd_tsks[i]) == xPortGetCoreID()) { TEST_ASSERT_EQUAL(eBlocked, eTaskGetState(blkd_tsks[i])); TEST_ASSERT_EQUAL(false, has_run[i]); } else { @@ -751,4 +751,122 @@ TEST_CASE("Test xTaskSuspendAll on all cores pends all tasks and xTaskResumeAll } #endif // !CONFIG_FREERTOS_UNICORE +/* --------------------------------------------------------------------------------------------------------------------- +Test vTaskSuspendAll pinned task scheduling + +Purpose: + - Test that when we disable the scheduler on core X, core X does not schedule any unblocked tasks pinned to it until + scheduling is resumed. + - While the scheduler on a core X is suspended, test that... + - A task pinned to core X is not scheduled even if its unblock time has been met + - The task is scheduled as soon as the scheduler on the core is resumed + +Procedure: + Each core gets tested in the role of core X + - Create task A1 pinned to core X that will suspend scheduling on core X + - Create task A2 pinned to core X that will test unblocking on core X + - Put task A2 in blocked state with a finite delay + - Suspend the scheduler on core X from task A1 + - Make sure that the delay time on task A2 expires + - Resume scheduler on core X from task A1 + - Cleanup the tasks + +Expected: + - When A1 disables scheduling, A2 should not be scheduled even after expiry of its delay time + - When A1 resumes scheduling, A2 should be scheduled +--------------------------------------------------------------------------------------------------------------------- */ + +#define TEST_BLOCKED_TASK_DELAY_MS 100 + +volatile static bool has_run = false; +SemaphoreHandle_t done_sem1; + +void test_blocked_task(void *arg) +{ + // Wait to be started + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + + // Mark has_run as false to begin the test + has_run = false; + + // Got to blocked state + vTaskDelay( TEST_BLOCKED_TASK_DELAY_MS / portTICK_PERIOD_MS ); + + // Mark when this task runs + has_run = true; + + // Cleanup + vTaskDelete(NULL); +} + +void test_suspend_task(void *arg) +{ + TaskHandle_t blkd_task = (TaskHandle_t)arg; + + // Wait to be started + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + + // Start the task which would block + xTaskNotifyGive(blkd_task); + + // Verify the state of the blocked task is eBlocked + TEST_ASSERT_EQUAL(eBlocked, eTaskGetState(blkd_task)); + + // Suspend the scheduler on this core + vTaskSuspendAll(); + + // Busy spin for a time which ensures that the blocked task's delay expires + esp_rom_delay_us(TEST_BLOCKED_TASK_DELAY_MS * 1000 * 2); + + // Verify that the blocked task has not been scheduled + TEST_ASSERT_EQUAL(false, has_run); + + // Resume the scheduler + xTaskResumeAll(); + + // Let the blocked task to be scheduled + vTaskDelay(10); + + // Verify that state of the blocked task is not eBlocked + TEST_ASSERT_NOT_EQUAL(eBlocked, eTaskGetState(blkd_task)); + + // Verify that the blocked task has run after scheduler is resumed + TEST_ASSERT_EQUAL(true, has_run); + + // Signal test completion + xSemaphoreGive(done_sem1); + + // Cleanup + vTaskDelete(NULL); +} + +TEST_CASE("Test vTaskSuspendAll pinned task scheduling", "[freertos]") +{ + for (int x = 0; x < portNUM_PROCESSORS; x++) { + TaskHandle_t susp_task; + TaskHandle_t blkd_task; + done_sem1 = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_EQUAL(NULL, done_sem1); + + // Create pinned task on core x which will block + // Ensure that this has a higher priority than the suspension task so that it immediately runs when the scheduler resumes + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(test_blocked_task, "blkd", 4096, NULL, UNITY_FREERTOS_PRIORITY + 1, &blkd_task, x)); + + // Create pinned task on core x which will suspend its scheduler + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(test_suspend_task, "susp", 4096, (void *)blkd_task, UNITY_FREERTOS_PRIORITY, &susp_task, x)); + + // Start the scheduler suspension task + xTaskNotifyGive(susp_task); + + // Wait for test completion + xSemaphoreTake(done_sem1, portMAX_DELAY); + + // Cleanup + vSemaphoreDelete(done_sem1); + + // Add a short delay to allow the idle task to free any remaining task memory + vTaskDelay(10); + } +} + #endif // !CONFIG_FREERTOS_SMP diff --git a/components/freertos/test_apps/freertos/misc/CMakeLists.txt b/components/freertos/test_apps/freertos/misc/CMakeLists.txt index 40bb3aa087e..66163e48064 100644 --- a/components/freertos/test_apps/freertos/misc/CMakeLists.txt +++ b/components/freertos/test_apps/freertos/misc/CMakeLists.txt @@ -3,5 +3,5 @@ # In order for the cases defined by `TEST_CASE` in "misc" to be linked into # the final elf, the component can be registered as WHOLE_ARCHIVE idf_component_register(SRC_DIRS "." - PRIV_REQUIRES unity test_utils + PRIV_REQUIRES unity test_utils esp_timer WHOLE_ARCHIVE) diff --git a/components/freertos/test_apps/freertos/misc/test_idf_additions.c b/components/freertos/test_apps/freertos/misc/test_idf_additions.c index 8990221ad88..ceaf2e46a4d 100644 --- a/components/freertos/test_apps/freertos/misc/test_idf_additions.c +++ b/components/freertos/test_apps/freertos/misc/test_idf_additions.c @@ -15,6 +15,9 @@ #include "esp_memory_utils.h" #include "unity.h" #include "test_utils.h" +#include "esp_freertos_hooks.h" +#include +#include /* Test ...Create...WithCaps() functions @@ -163,3 +166,88 @@ TEST_CASE("IDF additions: Event group creation with memory caps", "[freertos]") // Free the event group vEventGroupDelete(evt_group_handle); } + +#if !CONFIG_FREERTOS_SMP +/* +Scheduler suspension behavior has changed in SMP FreeRTOS, thus these test are disabled for SMP FreeRTOS. +See IDF-5201 +*/ + +/* --------------------------------------------------------------------------------------------------------------------- +IDF additions: IDF tick hooks during scheduler suspension + +Purpose: + - Test that the IDF tick hooks are called even with scheduler suspension + +Procedure: + Each core gets tested in the role of core X + - Create suspend_task pinned to core X which will register a tick hook on core X and suspend scheduler on core X + - Register tick hook on core X + - suspend_task suspends scheduling on core X for Y milliseconds and then resumes scheduling + - Delay suspend_task for Y milliseconds more after scheduler resumption + - De-register the tick hook + - Verify the tick hook callback count + +Expected: + - The tick hook is called for Y * 2 times +--------------------------------------------------------------------------------------------------------------------- */ + +#define TEST_DELAY_MS 200 +static uint32_t tick_hook_count[portNUM_PROCESSORS]; + +static void IRAM_ATTR tick_hook(void) +{ + tick_hook_count[portGET_CORE_ID()] += portTICK_PERIOD_MS; +} + +static void suspend_task(void *arg) +{ + TaskHandle_t main_task_hdl = ( TaskHandle_t )arg; + + /* Fetch the current core ID */ + BaseType_t xCoreID = portGET_CORE_ID(); + + /* Register tick hook */ + memset(tick_hook_count, 0, sizeof(tick_hook_count)); + esp_register_freertos_tick_hook_for_cpu(tick_hook, xCoreID); + + /* Suspend scheduler */ + vTaskSuspendAll(); + + /* Suspend for TEST_DELAY_MS milliseconds */ + esp_rom_delay_us(TEST_DELAY_MS * 1000); + + /* Resume scheduler */ + xTaskResumeAll(); + + /* Delay for a further TEST_DELAY_MS milliseconds after scheduler resumption */ + vTaskDelay(pdMS_TO_TICKS(TEST_DELAY_MS)); + + /* De-register tick hook */ + esp_deregister_freertos_tick_hook_for_cpu(tick_hook, xCoreID); + + /* Verify that the tick hook callback count equals the scheduler suspension time + the delay time. + * We add a variation of 2 ticks to account for delays encountered during test setup and teardown. + */ + printf("Core%d tick_hook_count = %"PRIu32"\n", xCoreID, tick_hook_count[xCoreID]); + TEST_ASSERT_INT_WITHIN(portTICK_PERIOD_MS * 2, TEST_DELAY_MS * 2, tick_hook_count[xCoreID]); + + /* Signal main task of test completion */ + xTaskNotifyGive(main_task_hdl); + + /* Cleanup */ + vTaskDelete(NULL); +} + +TEST_CASE("IDF additions: IDF tick hooks during scheduler suspension", "[freertos]") +{ + /* Run test for each core */ + for (int x = 0; x < portNUM_PROCESSORS; x++) { + xTaskCreatePinnedToCore(&suspend_task, "suspend_task", 8192, (void *)xTaskGetCurrentTaskHandle(), UNITY_FREERTOS_PRIORITY, NULL, x); + + /* Wait for test completion */ + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + } +} + +#endif // !CONFIG_FREERTOS_SMP diff --git a/components/freertos/test_apps/freertos/performance/test_isr_latency.c b/components/freertos/test_apps/freertos/performance/test_isr_latency.c index 7a13d826680..2375516162d 100644 --- a/components/freertos/test_apps/freertos/performance/test_isr_latency.c +++ b/components/freertos/test_apps/freertos/performance/test_isr_latency.c @@ -18,7 +18,7 @@ #include "test_utils.h" #if CONFIG_IDF_TARGET_ARCH_XTENSA #include "xtensa/hal.h" -#include "freertos/xtensa_api.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) #define TEST_SET_INT_MASK(mask) xt_set_intset(mask) #define TEST_CLR_INT_MASK(mask) xt_set_intclear(mask) #elif CONFIG_IDF_TARGET_ARCH_RISCV diff --git a/components/freertos/test_apps/freertos/port/test_fpu_in_isr.c b/components/freertos/test_apps/freertos/port/test_fpu_in_isr.c index 3ca6e900460..5bdbc1375b2 100644 --- a/components/freertos/test_apps/freertos/port/test_fpu_in_isr.c +++ b/components/freertos/test_apps/freertos/port/test_fpu_in_isr.c @@ -16,7 +16,7 @@ #if SOC_CPU_HAS_FPU && CONFIG_FREERTOS_FPU_IN_ISR // We can use xtensa API here as currently, non of the RISC-V targets have an FPU -#include "xtensa/xtensa_api.h" +#include "xtensa_api.h" // Replace with interrupt allocator API (IDF-3891) #include "esp_intr_alloc.h" #define SW_ISR_LEVEL_1 7 @@ -119,7 +119,7 @@ static void unpinned_task(void *arg) #if CONFIG_FREERTOS_SMP TEST_ASSERT_EQUAL(tskNO_AFFINITY, vTaskCoreAffinityGet(NULL)); #else - TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetAffinity(NULL)); + TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetCoreID(NULL)); #endif #endif // !CONFIG_FREERTOS_UNICORE @@ -136,7 +136,7 @@ static void unpinned_task(void *arg) #if CONFIG_FREERTOS_SMP TEST_ASSERT_EQUAL(tskNO_AFFINITY, vTaskCoreAffinityGet(NULL)); #else - TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetAffinity(NULL)); + TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetCoreID(NULL)); #endif #endif // !CONFIG_FREERTOS_UNICORE // Reenable scheduling/preemption diff --git a/components/freertos/test_apps/freertos/port/test_fpu_in_task.c b/components/freertos/test_apps/freertos/port/test_fpu_in_task.c index 6bde01e3888..64ceaf06e1e 100644 --- a/components/freertos/test_apps/freertos/port/test_fpu_in_task.c +++ b/components/freertos/test_apps/freertos/port/test_fpu_in_task.c @@ -141,7 +141,7 @@ static void unpinned_task(void *arg) #if CONFIG_FREERTOS_SMP TEST_ASSERT_EQUAL(tskNO_AFFINITY, vTaskCoreAffinityGet(NULL)); #else - TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetAffinity(NULL)); + TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetCoreID(NULL)); #endif #endif // !CONFIG_FREERTOS_UNICORE @@ -162,7 +162,7 @@ static void unpinned_task(void *arg) #if CONFIG_FREERTOS_SMP TEST_ASSERT_EQUAL(1 << cur_core_num, vTaskCoreAffinityGet(NULL)); #else - TEST_ASSERT_EQUAL(cur_core_num, xTaskGetAffinity(NULL)); + TEST_ASSERT_EQUAL(cur_core_num, xTaskGetCoreID(NULL)); #endif #endif // !CONFIG_FREERTOS_UNICORE // Reenable scheduling/preemption diff --git a/components/freertos/test_apps/freertos/port/test_xtensa_loadstore_handler.c b/components/freertos/test_apps/freertos/port/test_xtensa_loadstore_handler.c index cbfc2774c50..1618b57a951 100644 --- a/components/freertos/test_apps/freertos/port/test_xtensa_loadstore_handler.c +++ b/components/freertos/test_apps/freertos/port/test_xtensa_loadstore_handler.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,10 +15,7 @@ #include "esp_random.h" #include "unity.h" -#if CONFIG_IDF_TARGET_ARCH_XTENSA -#include "freertos/xtensa_api.h" - -#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY +#if CONFIG_IDF_TARGET_ARCH_XTENSA && CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY TEST_CASE("LoadStore Exception handler", "[freertos]") { int32_t val0 = 0xDEADBEEF; @@ -128,5 +125,4 @@ TEST_CASE("LoadStore Exception handler", "[freertos]") TEST_ASSERT_TRUE(heap_caps_check_integrity_all(true)); heap_caps_free(arr); } -#endif // CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY -#endif // CONFIG_IDF_TARGET_ARCH_XTENSA +#endif // CONFIG_IDF_TARGET_ARCH_XTENSA && CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY diff --git a/components/freertos/test_apps/freertos/sdkconfig.ci.freertos_options b/components/freertos/test_apps/freertos/sdkconfig.ci.freertos_options index 38ae8ab7df4..747ee35c635 100644 --- a/components/freertos/test_apps/freertos/sdkconfig.ci.freertos_options +++ b/components/freertos/test_apps/freertos/sdkconfig.ci.freertos_options @@ -17,3 +17,5 @@ CONFIG_FREERTOS_RUN_TIME_COUNTER_TYPE_U64=y CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y CONFIG_FREERTOS_FPU_IN_ISR=y CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=2 +CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES=y +CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU1=y diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 58698a72195..6de6bcb5cf5 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -163,6 +163,10 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "lcd_hal.c") endif() + if(CONFIG_SOC_MIPI_DSI_SUPPORTED) + list(APPEND srcs "mipi_dsi_hal.c") + endif() + if(CONFIG_SOC_ECC_SUPPORTED) list(APPEND srcs "ecc_hal.c") endif() @@ -238,6 +242,13 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "huk_hal.c") endif() + if(CONFIG_SOC_USB_OTG_SUPPORTED) + list(APPEND srcs + "usb_hal.c" + "usb_dwc_hal.c" + "usb_phy_hal.c") + endif() + if(${target} STREQUAL "esp32") list(APPEND srcs "touch_sensor_hal.c" @@ -248,23 +259,17 @@ if(NOT BOOTLOADER_BUILD) if(${target} STREQUAL "esp32s2") list(APPEND srcs "touch_sensor_hal.c" - "usb_hal.c" - "usb_phy_hal.c" "xt_wdt_hal.c" "esp32s2/cp_dma_hal.c" - "esp32s2/touch_sensor_hal.c" - "usb_dwc_hal.c") + "esp32s2/touch_sensor_hal.c") endif() if(${target} STREQUAL "esp32s3") list(APPEND srcs "touch_sensor_hal.c" - "usb_hal.c" - "usb_phy_hal.c" "xt_wdt_hal.c" "esp32s3/touch_sensor_hal.c" - "esp32s3/rtc_cntl_hal.c" - "usb_dwc_hal.c") + "esp32s3/rtc_cntl_hal.c") endif() if(${target} STREQUAL "esp32c3") diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index 77b4809a75c..46a35a2e3c9 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -120,7 +120,11 @@ void adc_hal_digi_init(adc_hal_dma_ctx_t *hal) i2s_ll_rx_set_sample_bit(hal->dev, SAMPLE_BITS, SAMPLE_BITS); i2s_ll_rx_enable_mono_mode(hal->dev, 1); i2s_ll_rx_force_enable_fifo_mod(hal->dev, 1); - i2s_ll_enable_builtin_adc(hal->dev, 1); + i2s_ll_rx_enable_right_first(hal->dev, false); + i2s_ll_rx_enable_msb_shift(hal->dev, false); + i2s_ll_rx_set_ws_width(hal->dev, 16); + i2s_ll_rx_select_std_slot(hal->dev, I2S_STD_SLOT_LEFT, false); + i2s_ll_enable_builtin_adc_dac(hal->dev, 1); #endif adc_oneshot_ll_disable_all_unit(); diff --git a/components/hal/adc_oneshot_hal.c b/components/hal/adc_oneshot_hal.c index feddc3178ca..1a5b56da4eb 100644 --- a/components/hal/adc_oneshot_hal.c +++ b/components/hal/adc_oneshot_hal.c @@ -81,7 +81,7 @@ void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t chan) #endif //#if SOC_ADC_ARBITER_SUPPORTED } -static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz) +static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz, uint32_t *read_delay_us) { #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED (void)unit; @@ -112,10 +112,8 @@ static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz) * A rough estimate for this step should be at least ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL ADC sar clock cycle. */ uint32_t sar_clk = adc_ctrl_clk / ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT; - uint32_t read_delay_us = ((1000 * 1000) / sar_clk + 1) * ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL; + *read_delay_us = ((1000 * 1000) / sar_clk + 1) * ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL; HAL_EARLY_LOGD("adc_hal", "clk_src_freq_hz: %"PRIu32", sar_clk: %"PRIu32", read_delay_us: %"PRIu32"", clk_src_freq_hz, sar_clk, read_delay_us); - esp_rom_delay_us(read_delay_us); - #endif //ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL #else @@ -127,6 +125,7 @@ bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw) { bool valid = true; uint32_t event = 0; + uint32_t read_delay_us = 0; if (hal->unit == ADC_UNIT_1) { event = ADC_LL_EVENT_ADC1_ONESHOT_DONE; } else { @@ -137,10 +136,11 @@ bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw) adc_oneshot_ll_disable_all_unit(); adc_oneshot_ll_enable(hal->unit); - adc_hal_onetime_start(hal->unit, hal->clk_src_freq_hz); + adc_hal_onetime_start(hal->unit, hal->clk_src_freq_hz, &read_delay_us); while (!adc_oneshot_ll_get_event(event)) { ; } + esp_rom_delay_us(read_delay_us); *out_raw = adc_oneshot_ll_get_raw_result(hal->unit); #if (SOC_ADC_PERIPH_NUM == 2) if (hal->unit == ADC_UNIT_2) { diff --git a/components/hal/brownout_hal.c b/components/hal/brownout_hal.c index c46dd2e0916..b755bdb4fcd 100644 --- a/components/hal/brownout_hal.c +++ b/components/hal/brownout_hal.c @@ -15,6 +15,7 @@ void brownout_hal_config(const brownout_hal_config_t *cfg) brownout_ll_set_intr_wait_cycles(2); brownout_ll_enable_flash_power_down(cfg->flash_power_down); brownout_ll_enable_rf_power_down(cfg->rf_power_down); + brownout_ll_clear_count(); brownout_ll_reset_config(cfg->reset_enabled, 0x3ff, 1); brownout_ll_set_threshold(cfg->threshold); brownout_ll_bod_enable(cfg->enabled); diff --git a/components/hal/cache_hal.c b/components/hal/cache_hal.c index 423589e7a0a..c95ed97c039 100644 --- a/components/hal/cache_hal.c +++ b/components/hal/cache_hal.c @@ -67,7 +67,7 @@ void cache_hal_init(void) cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK); cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK); cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK); #endif diff --git a/components/hal/dw_gdma_hal.c b/components/hal/dw_gdma_hal.c index b1e576f34de..1549b0dde39 100644 --- a/components/hal/dw_gdma_hal.c +++ b/components/hal/dw_gdma_hal.c @@ -12,4 +12,14 @@ void dw_gdma_hal_init(dw_gdma_hal_context_t *hal, const dw_gdma_hal_config_t *config) { hal->dev = DW_GDMA_LL_GET_HW(); + dw_gdma_ll_reset(hal->dev); + dw_gdma_ll_enable_controller(hal->dev, true); + dw_gdma_ll_enable_intr_global(hal->dev, true); +} + +void dw_gdma_hal_deinit(dw_gdma_hal_context_t *hal) +{ + dw_gdma_ll_enable_intr_global(hal->dev, false); + dw_gdma_ll_enable_controller(hal->dev, false); + hal->dev = NULL; } diff --git a/components/hal/ecdsa_hal.c b/components/hal/ecdsa_hal.c index f0681dc8305..3737e793ba0 100644 --- a/components/hal/ecdsa_hal.c +++ b/components/hal/ecdsa_hal.c @@ -30,22 +30,17 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf) ecdsa_ll_set_curve(conf->curve); if (conf->mode != ECDSA_MODE_EXPORT_PUBKEY) { - ecdsa_ll_set_k_mode(conf->k_mode); ecdsa_ll_set_z_mode(conf->sha_mode); } } -void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *k, const uint8_t *hash, +void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, uint8_t *r_out, uint8_t *s_out, uint16_t len) { if (len != ECDSA_HAL_P192_COMPONENT_LEN && len != ECDSA_HAL_P256_COMPONENT_LEN) { HAL_ASSERT(false && "Incorrect length"); } - if (conf->k_mode == ECDSA_K_USER_PROVIDED && k == NULL) { - HAL_ASSERT(false && "Mismatch in K configuration"); - } - if (conf->sha_mode == ECDSA_Z_USER_PROVIDED && hash == NULL) { HAL_ASSERT(false && "Mismatch in SHA configuration"); } diff --git a/components/hal/esp32/cache_hal_esp32.c b/components/hal/esp32/cache_hal_esp32.c index 81592333277..33a7b1fb265 100644 --- a/components/hal/esp32/cache_hal_esp32.c +++ b/components/hal/esp32/cache_hal_esp32.c @@ -18,7 +18,7 @@ void cache_hal_suspend(uint32_t cache_level, cache_type_t type) { s_cache_status[0] = cache_ll_l1_get_enabled_bus(0); cache_ll_l1_disable_cache(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE s_cache_status[1] = cache_ll_l1_get_enabled_bus(1); cache_ll_l1_disable_cache(1); #endif @@ -29,7 +29,7 @@ void cache_hal_resume(uint32_t cache_level, cache_type_t type) { cache_ll_l1_enable_cache(0); cache_ll_l1_enable_bus(0, s_cache_status[0]); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE cache_ll_l1_enable_cache(1); cache_ll_l1_enable_bus(1, s_cache_status[1]); #endif @@ -39,7 +39,7 @@ void cache_hal_resume(uint32_t cache_level, cache_type_t type) bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type) { bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE result = result && cache_ll_l1_is_cache_enabled(1, CACHE_TYPE_ALL); #endif return result; diff --git a/components/hal/esp32/include/hal/brownout_ll.h b/components/hal/esp32/include/hal/brownout_ll.h index d18fcfd2459..3ebdd8ec8e5 100644 --- a/components/hal/esp32/include/hal/brownout_ll.h +++ b/components/hal/esp32/include/hal/brownout_ll.h @@ -112,6 +112,15 @@ static inline void brownout_ll_intr_clear(void) RTCCNTL.int_clr.rtc_brown_out = 1; } +/** + * @brief Clear BOD internal count. + */ +static inline void brownout_ll_clear_count(void) +{ + // Not supported on esp32 +} + + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32/include/hal/clk_gate_ll.h b/components/hal/esp32/include/hal/clk_gate_ll.h index 4ab3a9aceb9..951fa390bf6 100644 --- a/components/hal/esp32/include/hal/clk_gate_ll.h +++ b/components/hal/esp32/include/hal/clk_gate_ll.h @@ -230,16 +230,14 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk(void) { DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk(void) { DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); } static inline void periph_ll_reset(periph_module_t periph) diff --git a/components/hal/esp32/include/hal/i2s_ll.h b/components/hal/esp32/include/hal/i2s_ll.h index a6a7a1b15fa..f56f2fe6c1f 100644 --- a/components/hal/esp32/include/hal/i2s_ll.h +++ b/components/hal/esp32/include/hal/i2s_ll.h @@ -1131,36 +1131,15 @@ static inline void i2s_ll_enable_camera(i2s_dev_t *hw, bool enable) } /** - * @brief Enable I2S build in ADC mode + * @brief Enable I2S built-in ADC/DAC mode * * @param hw Peripheral I2S hardware instance address. - * @param enable Set true to enable build in ADC + * @param enable Set true to enable built-in ADC/DAC */ -static inline void i2s_ll_enable_builtin_adc(i2s_dev_t *hw, bool enable) +static inline void i2s_ll_enable_builtin_adc_dac(i2s_dev_t *hw, bool enable) { hw->conf2.lcd_en = enable; hw->conf2.camera_en = 0; - hw->conf.rx_right_first = 0; - hw->conf.rx_msb_shift = 0; - hw->conf.rx_mono = 0; - hw->conf.rx_short_sync = 0; - hw->fifo_conf.rx_fifo_mod = enable; - hw->conf_chan.rx_chan_mod = enable; -} - -/** - * @brief Enable I2S build in DAC mode - * - * @param hw Peripheral I2S hardware instance address. - * * @param enable Set true to enable build in DAC - */ -static inline void i2s_ll_enable_builtin_dac(i2s_dev_t *hw, bool enable) -{ - hw->conf2.lcd_en = enable; - hw->conf2.camera_en = 0; - hw->conf.tx_right_first = enable; - hw->conf.tx_msb_shift = 0; - hw->conf.tx_short_sync = 0; } #ifdef __cplusplus diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h index d92ab124fde..d10deaa96b9 100644 --- a/components/hal/esp32/include/hal/rtc_io_ll.h +++ b/components/hal/esp32/include/hal/rtc_io_ll.h @@ -360,7 +360,7 @@ static inline void rtcio_ll_disable_sleep_setting(int rtcio_num) } /** - * Set specific logic level on an RTC IO pin as a wakeup trigger. + * Set specific logic level on an RTC IO pin as a ext0 wakeup trigger. * * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). * @param level Logic level (0) diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h index 21850c9b970..c12200fc523 100644 --- a/components/hal/esp32/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32/include/hal/touch_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,6 +32,8 @@ extern "C" { #define TOUCH_LL_BIT_SWAP(data, n, m) (((data >> n) & 0x1) == ((data >> m) & 0x1) ? (data) : ((data) ^ ((0x1 <intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; + if (raw) { + return dev->intr[channel].raw.val & GDMA_LL_RX_EVENT_MASK; + } else { + return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; + } } /** @@ -303,9 +307,13 @@ static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t c * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; + if (raw) { + return dev->intr[channel].raw.val & GDMA_LL_TX_EVENT_MASK; + } else { + return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; + } } /** diff --git a/components/hal/esp32c2/include/hal/spimem_flash_ll.h b/components/hal/esp32c2/include/hal/spimem_flash_ll.h index 649414084d0..23bddd1ba2f 100644 --- a/components/hal/esp32c2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c2/include/hal/spimem_flash_ll.h @@ -245,6 +245,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + // Not supported on this chip. +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32c2/include/hal/systimer_ll.h b/components/hal/esp32c2/include/hal/systimer_ll.h index f5bb4d1ffd1..5bcc86cdd80 100644 --- a/components/hal/esp32c2/include/hal/systimer_ll.h +++ b/components/hal/esp32c2/include/hal/systimer_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "soc/systimer_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/system_struct.h" #include "hal/assert.h" #ifdef __cplusplus @@ -35,6 +36,35 @@ static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) return SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + SYSTEM.perip_clk_en0.systimer_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + SYSTEM.perip_rst_en0.systimer_rst = 1; + SYSTEM.perip_rst_en0.systimer_rst = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /******************* Counter *************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) diff --git a/components/hal/esp32c2/include/hal/temperature_sensor_ll.h b/components/hal/esp32c2/include/hal/temperature_sensor_ll.h index 6f4f58897ba..685f77b7941 100644 --- a/components/hal/esp32c2/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32c2/include/hal/temperature_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,6 +23,7 @@ #include "soc/soc_caps.h" #include "hal/temperature_sensor_types.h" #include "hal/assert.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -92,7 +93,7 @@ static inline void temperature_sensor_ll_set_range(uint32_t range) */ static inline uint32_t temperature_sensor_ll_get_raw_value(void) { - return APB_SARADC.saradc_apb_tsens_ctrl.saradc_reg_tsens_out; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_reg_tsens_out); } /** @@ -116,7 +117,7 @@ static inline uint32_t temperature_sensor_ll_get_offset(void) */ static inline uint32_t temperature_sensor_ll_get_clk_div(void) { - return APB_SARADC.saradc_apb_tsens_ctrl.saradc_reg_tsens_clk_div; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_reg_tsens_clk_div); } /** @@ -129,7 +130,7 @@ static inline uint32_t temperature_sensor_ll_get_clk_div(void) */ static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) { - APB_SARADC.saradc_apb_tsens_ctrl.saradc_reg_tsens_clk_div = clk_div; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_reg_tsens_clk_div, clk_div); } #ifdef __cplusplus diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index dd9784b1a9a..2c84599ea62 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -121,19 +121,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way #define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__) -/** - * @brief Configure the UART core reset. - * - * @param hw Beginning address of the peripheral registers. - * @param core_rst_en True to enable the core reset, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) -{ - hw->clk_conf.rst_core = core_rst_en; -} - /** * @brief Enable the UART clock. * diff --git a/components/hal/esp32c3/include/hal/brownout_ll.h b/components/hal/esp32c3/include/hal/brownout_ll.h index d415ebed53c..4a60eb44247 100644 --- a/components/hal/esp32c3/include/hal/brownout_ll.h +++ b/components/hal/esp32c3/include/hal/brownout_ll.h @@ -115,6 +115,15 @@ static inline void brownout_ll_intr_clear(void) RTCCNTL.int_clr.rtc_brown_out = 1; } +/** + * @brief Clear BOD internal count. + */ +static inline void brownout_ll_clear_count(void) +{ + RTCCNTL.brown_out.cnt_clr = 1; + RTCCNTL.brown_out.cnt_clr = 0; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/clk_gate_ll.h b/components/hal/esp32c3/include/hal/clk_gate_ll.h index b76993c0481..5765a5e57e1 100644 --- a/components/hal/esp32c3/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c3/include/hal/clk_gate_ll.h @@ -229,16 +229,14 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk(void) { DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk(void) { DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } static inline void periph_ll_reset(periph_module_t periph) diff --git a/components/hal/esp32c3/include/hal/gdma_ll.h b/components/hal/esp32c3/include/hal/gdma_ll.h index d3deb43181b..f51f47a90e8 100644 --- a/components/hal/esp32c3/include/hal/gdma_ll.h +++ b/components/hal/esp32c3/include/hal/gdma_ll.h @@ -89,9 +89,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable) * @brief Get DMA RX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; + if (raw) { + return dev->intr[channel].raw.val & GDMA_LL_RX_EVENT_MASK; + } else { + return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; + } } /** @@ -303,9 +307,13 @@ static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t c * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; + if (raw) { + return dev->intr[channel].raw.val & GDMA_LL_TX_EVENT_MASK; + } else { + return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; + } } /** diff --git a/components/hal/esp32c3/include/hal/spimem_flash_ll.h b/components/hal/esp32c3/include/hal/spimem_flash_ll.h index 3a4e4389ef8..73df69e3e18 100644 --- a/components/hal/esp32c3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c3/include/hal/spimem_flash_ll.h @@ -247,6 +247,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + // Not supported on this chip. +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32c3/include/hal/systimer_ll.h b/components/hal/esp32c3/include/hal/systimer_ll.h index f5bb4d1ffd1..c5c8efe4840 100644 --- a/components/hal/esp32c3/include/hal/systimer_ll.h +++ b/components/hal/esp32c3/include/hal/systimer_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "soc/systimer_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/system_struct.h" #include "hal/assert.h" #ifdef __cplusplus @@ -35,6 +36,35 @@ static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) return SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + SYSTEM.perip_clk_en0.reg_systimer_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + SYSTEM.perip_rst_en0.reg_systimer_rst = 1; + SYSTEM.perip_rst_en0.reg_systimer_rst = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /******************* Counter *************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) diff --git a/components/hal/esp32c3/include/hal/temperature_sensor_ll.h b/components/hal/esp32c3/include/hal/temperature_sensor_ll.h index d39f660d693..4dac4061ae5 100644 --- a/components/hal/esp32c3/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32c3/include/hal/temperature_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,6 +23,7 @@ #include "soc/soc_caps.h" #include "hal/temperature_sensor_types.h" #include "hal/assert.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -92,7 +93,7 @@ static inline void temperature_sensor_ll_set_range(uint32_t range) */ static inline uint32_t temperature_sensor_ll_get_raw_value(void) { - return APB_SARADC.apb_tsens_ctrl.tsens_out; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.apb_tsens_ctrl, tsens_out); } /** @@ -116,7 +117,7 @@ static inline uint32_t temperature_sensor_ll_get_offset(void) */ static inline uint32_t temperature_sensor_ll_get_clk_div(void) { - return APB_SARADC.apb_tsens_ctrl.tsens_clk_div; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.apb_tsens_ctrl, tsens_clk_div); } /** @@ -129,7 +130,7 @@ static inline uint32_t temperature_sensor_ll_get_clk_div(void) */ static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) { - APB_SARADC.apb_tsens_ctrl.tsens_clk_div = clk_div; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_tsens_ctrl, tsens_clk_div, clk_div); } #ifdef __cplusplus diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index 409e1e463c1..f73bf79f38c 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -104,14 +104,19 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) */ static inline void uart_ll_reset_register(uart_port_t uart_num) { + // ESP32C3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value switch (uart_num) { case 0: + UART0.clk_conf.rst_core = 1; SYSTEM.perip_rst_en0.reg_uart_rst = 1; SYSTEM.perip_rst_en0.reg_uart_rst = 0; + UART0.clk_conf.rst_core = 0; break; case 1: + UART1.clk_conf.rst_core = 1; SYSTEM.perip_rst_en0.reg_uart1_rst = 1; SYSTEM.perip_rst_en0.reg_uart1_rst = 0; + UART1.clk_conf.rst_core = 0; break; default: abort(); @@ -121,19 +126,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way #define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__) -/** - * @brief Configure the UART core reset. - * - * @param hw Beginning address of the peripheral registers. - * @param core_rst_en True to enable the core reset, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) -{ - hw->clk_conf.rst_core = core_rst_en; -} - /** * @brief Enable the UART clock. * diff --git a/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h index 0a6e382efd0..1a62070718c 100644 --- a/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,8 +7,11 @@ // The LL layer of the USB-serial-jtag controller #pragma once +#include +#include "esp_attr.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" +#include "soc/system_struct.h" #ifdef __cplusplus extern "C" { @@ -158,8 +161,14 @@ static inline int usb_serial_jtag_ll_txfifo_writable(void) * @brief Flushes the TX buffer, that is, make it available for the * host to pick up. * - * @note When fifo is full (with 64 byte), HW will flush the buffer automatically. - * It won't be executed if there is nothing in the fifo. + * @note When fifo is full (with 64 byte), HW will flush the buffer automatically, + * if this function is called directly after, this effectively turns into a + * no-op. Because a 64-byte packet will be interpreted as a not-complete USB + * transaction, you need to transfer either more data or a zero-length packet + * for the data to actually end up at the program listening to the CDC-ACM + * serial port. To send a zero-length packet, call + * usb_serial_jtag_ll_txfifo_flush() again when + * usb_serial_jtag_ll_txfifo_writable() returns true. * * @return na */ @@ -168,6 +177,65 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void) USB_SERIAL_JTAG.ep1_conf.wr_done=1; } +/** + * @brief Disable usb serial jtag pad during light sleep to avoid current leakage + * + * @return Initial configuration of usb serial jtag pad enable before light sleep + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void) +{ + bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable; + + // Disable USB pad function + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + + return pad_enabled; +} + +/** + * @brief Enable the internal USJ PHY control to D+/D- pad + * + * @param enable_pad Enable the USJ PHY control to D+/D- pad + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad) +{ + USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad; +} + +/** + * @brief Enable the bus clock for USB Serial_JTAG module + * @param clk_en True if enable the clock of USB Serial_JTAG module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) +{ + SYSTEM.perip_clk_en0.reg_usb_device_clk_en = clk_en; +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the usb serial jtag module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void) +{ + SYSTEM.perip_rst_en0.reg_usb_device_rst = 1; + SYSTEM.perip_rst_en0.reg_usb_device_rst = 0; +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_serial_jtag_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_reset_register(__VA_ARGS__) + +/** + * Get the enable status USB Serial_JTAG module + * + * @return Return true if USB Serial_JTAG module is enabled + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void) +{ + return (SYSTEM.perip_clk_en0.reg_usb_device_clk_en && !SYSTEM.perip_rst_en0.reg_usb_device_rst); +} + #ifdef __cplusplus } diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h new file mode 100644 index 00000000000..2f460651ade --- /dev/null +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -0,0 +1,328 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Cache register operations + +#pragma once + +#include +// TODO: [ESP32C5] IDF-8646 (inherit from C6) +// #include "soc/extmem_reg.h" +// #include "soc/ext_mem_defs.h" +#include "hal/cache_types.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state. + +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 + +#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4) + +#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID +#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem +#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem +#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level +#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels +#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0) + +/** + * @brief Check if Cache auto preload is enabled or not. + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * + * @return true: enabled; false: disabled + */ +__attribute__((always_inline)) +static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // bool enabled = false; + // if (REG_GET_BIT(EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG, EXTMEM_L1_CACHE_AUTOLOAD_ENA)) { + // enabled = true; + // } + // return enabled; + return (bool)0; +} + +/** + * @brief Disable Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // (void) type; + // Cache_Disable_ICache(); +} + +/** + * @brief Enable Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * @param data_autoload_en data autoload enabled or not + * @param inst_autoload_en inst autoload enabled or not + */ +__attribute__((always_inline)) +static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); +} + +/** + * @brief Suspend Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Suspend_ICache(); +} + +/** + * @brief Resume Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * @param data_autoload_en data autoload enabled or not + * @param inst_autoload_en inst autoload enabled or not + */ +__attribute__((always_inline)) +static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0); +} + +/** + * @brief Invalidate cache supported addr + * + * Invalidate a cache item + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * @param vaddr start address of the region to be invalidated + * @param size size of the region to be invalidated + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Invalidate_Addr(vaddr, size); +} + +/** + * @brief Freeze Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY); +} + +/** + * @brief Unfreeze Cache + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // Cache_Freeze_ICache_Disable(); +} + +/** + * @brief Get Cache line size, in bytes + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + * + * @return Cache line size, in bytes + */ +__attribute__((always_inline)) +static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // uint32_t size = 0; + // size = Cache_Get_ICache_Line_Size(); + // return size; + return (uint32_t)0; +} + +/** + * @brief Get the buses of a particular cache that are mapped to a virtual address range + * + * External virtual address can only be accessed when the involved cache buses are enabled. + * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside. + * + * @param cache_id cache ID (when l1 cache is per core) + * @param vaddr_start virtual address start + * @param len vaddr length + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // cache_bus_mask_t mask = (cache_bus_mask_t)0; + // // uint32_t vaddr_end = vaddr_start + len - 1; + // if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) { + // //c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0` + // mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0)); + // } else { + // HAL_ASSERT(0); //Out of region + // } + // // return mask; + return (cache_bus_mask_t)0; +} + +/** + * Enable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be enabled + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + // HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + // // uint32_t ibus_mask = 0; + // ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0); + // REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); + // // uint32_t dbus_mask = 0; + // dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0); + // REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); +} + +/** + * Disable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be disabled + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); + // //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + // HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + // // uint32_t ibus_mask = 0; + // ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0); + // REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); + // // uint32_t dbus_mask = 0; + // dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0); + // REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); +} + +/** + * @brief Get Cache level and the ID of the vaddr + * + * @param vaddr_start virtual address start + * @param len vaddr length + * @param out_level cache level + * @param out_id cache id + * + * @return true for valid + */ +__attribute__((always_inline)) +static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // bool valid = false; + // uint32_t vaddr_end = vaddr_start + len - 1; + // // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)); + // valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end)); + // // if (valid) { + // *out_level = 1; + // *out_id = 0; + // } + // // return valid; + return (bool)0; +} + +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8646 (inherit from C6) + // return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); + return (uint32_t)0; +} + +#ifdef __cplusplus + return (uint32_t)0; +} +#endif diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h new file mode 100644 index 00000000000..cbf18441002 --- /dev/null +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -0,0 +1,173 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32p4/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_repeat_data1.wdt_delay_sel; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_mac_sys_0.mac_0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_mac_sys_1.mac_1; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.rd_repeat_data2.secure_boot_en; + return (bool)0; +} + +// use efuse_hal_get_major_chip_version() to get major chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // // return EFUSE.rd_mac_sys_5; + // return 0; + return (uint32_t)0; +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (bool)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (bool)0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return 0; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.conf.cfg_ecdsa_blk = efuse_blk; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.cmd.read_cmd; + return (bool)0; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // return EFUSE.cmd.pgm_cmd; + return (bool)0; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + // EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void) +{ + // TODO: [ESP32C5] IDF-8674 (inherit from C6) + // EFUSE.wr_tim_conf0_rs_bypass.update = 1; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/lpwdt_ll.h b/components/hal/esp32c5/include/hal/lpwdt_ll.h new file mode 100644 index 00000000000..7bd643be2d9 --- /dev/null +++ b/components/hal/esp32c5/include/hal/lpwdt_ll.h @@ -0,0 +1,349 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/misc.h" +#include "hal/wdt_types.h" +#include "soc/rtc_cntl_periph.h" +#include "soc/efuse_reg.h" +#include "esp_attr.h" +#include "esp_assert.h" + +#include "esp32c5/rom/ets_sys.h" + +/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */ +#define LP_WDT_WKEY_VALUE 0x50D83AA1 +/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */ +#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1 + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ +#define LP_WDT_RESET_LENGTH_100_NS 0 +#define LP_WDT_RESET_LENGTH_200_NS 1 +#define LP_WDT_RESET_LENGTH_300_NS 2 +#define LP_WDT_RESET_LENGTH_400_NS 3 +#define LP_WDT_RESET_LENGTH_500_NS 4 +#define LP_WDT_RESET_LENGTH_800_NS 5 +#define LP_WDT_RESET_LENGTH_1600_NS 6 +#define LP_WDT_RESET_LENGTH_3200_NS 7 + +#define LP_WDT_STG_SEL_OFF 0 +#define LP_WDT_STG_SEL_INT 1 +#define LP_WDT_STG_SEL_RESET_CPU 2 +#define LP_WDT_STG_SEL_RESET_SYSTEM 3 +#define LP_WDT_STG_SEL_RESET_RTC 4 + +//Type check wdt_stage_action_t +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the RWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_en = 1; +} + +/** + * @brief Disable the RWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_en = 0; +} + +/** + * @brief Check if the RWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if RTC WDT is enabled + */ +FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // return (hw->config0.wdt_en) ? true : false; + return (bool)0; +} + +/** + * @brief Configure a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout (see note). + * @param behavior What action to take when the stage times out + * + * @note The value of of RWDT stage 0 timeout register is special, in + * that an implicit multiplier is applied to that value to produce + * and effective timeout tick value. The multiplier is dependent + * on an EFuse value. Therefore, when configuring stage 0, the valid + * values for the timeout argument are: + * - If Efuse value is 0, any even number between [2,2*UINT32_MAX] + * - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX] + * - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX] + * - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX] + */ +FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->config0.wdt_stg0 = behavior; + // //Account of implicty multiplier applied to stage 0 timeout tick config value + // hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + // break; + // case WDT_STAGE1: + // hw->config0.wdt_stg1 = behavior; + // hw->config2.val = timeout_ticks; + // break; + // case WDT_STAGE2: + // hw->config0.wdt_stg2 = behavior; + // hw->config3.val = timeout_ticks; + // break; + // case WDT_STAGE3: + // hw->config0.wdt_stg3 = behavior; + // hw->config4.val = timeout_ticks; + // break; + // default: + // abort(); + // } +} + +/** + * @brief Disable a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE1: + // hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE2: + // hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE3: + // hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + // break; + // default: + // abort(); + // } +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_cpu_reset_length = length; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_sys_reset_length = length; +} + +/** + * @brief Enable/Disable the RWDT flashboot mode. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU0 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU1 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the RWDT pause during sleep functionality + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable chip reset on RWDT timeout. + * + * A chip reset also resets the analog portion of the chip. It will appear as a + * POWERON reset rather than an RTC reset. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Set width of chip reset signal + * + * @param hw Start address of the peripheral registers. + * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width); +} + +/** + * @brief Feed the RWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->feed.rtc_wdt_feed = 1; +} + +/** + * @brief Enable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->wprotect.val = 0; +} + +/** + * @brief Disable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->wprotect.val = LP_WDT_WKEY_VALUE; +} + +/** + * @brief Enable the RWDT interrupt. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT interrupt, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0; +} + +/** + * @brief Check if the RWDT interrupt has been triggered + * + * @param hw Start address of the peripheral registers. + * @return True if the RWDT interrupt was triggered + */ +FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // return (hw->int_st.lp_wdt_int_st) ? true : false; + return (bool)0; +} + +/** + * @brief Clear the RWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // hw->int_clr.lp_wdt_int_clr = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h new file mode 100644 index 00000000000..c63225b0d54 --- /dev/null +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -0,0 +1,433 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for MMU register operations + +#pragma once + +#include "soc/spi_mem_reg.h" +// #include "soc/ext_mem_defs.h" +#include "hal/assert.h" +#include "hal/mmu_types.h" +#include "hal/efuse_ll.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Convert MMU virtual address to linear address + * + * @param vaddr virtual address + * + * @return linear address + */ +static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // return vaddr & SOC_MMU_LINEAR_ADDR_MASK; + return (uint32_t)0; +} + +/** + * Convert MMU linear address to virtual address + * + * @param laddr linear address + * @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * @param target virtual address aimed physical memory target, not used + * + * @return virtual address + */ +static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)target; + // (void)vaddr_type; + // //On ESP32C5, I/D share the same vaddr range + // return SOC_MMU_IBUS_VADDR_BASE | laddr; + return (uint32_t)0; +} + +__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // unsigned cnt = efuse_ll_get_flash_crypt_cnt(); + // // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on + // cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1; + // return (cnt == 1); + return (bool)0; +} + +/** + * Get MMU page size + * + * @param mmu_id MMU ID + * + * @return MMU page size code + */ +__attribute__((always_inline)) +static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); + // return (page_size_code == 0) ? MMU_PAGE_64KB : + // (page_size_code == 1) ? MMU_PAGE_32KB : + // (page_size_code == 2) ? MMU_PAGE_16KB : + // MMU_PAGE_8KB; + return (mmu_page_size_t)0; +} + +/** + * Set MMU page size + * + * @param size MMU page size + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : + // (size == MMU_PAGE_32KB) ? 1 : + // (size == MMU_PAGE_16KB) ? 2 : + // (size == MMU_PAGE_8KB) ? 3 : 0; + // REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val); +} + +/** + * Check if the external memory vaddr region is valid + * + * @param mmu_id MMU ID + * @param vaddr_start start of the virtual address + * @param len length, in bytes + * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * + * @return + * True for valid + */ +__attribute__((always_inline)) +static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // (void)type; + // uint32_t vaddr_end = vaddr_start + len - 1; + // return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end)); + return (bool)0; +} + +/** + * Check if the paddr region is valid + * + * @param mmu_id MMU ID + * @param paddr_start start of the physical address + * @param len length, in bytes + * + * @return + * True for valid + */ +static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && + // (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && + // ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)); + return (bool)0; +} + +/** + * To get the MMU table entry id to be mapped + * + * @param mmu_id MMU ID + * @param vaddr virtual address to be mapped + * + * @return + * MMU table entry id + */ +__attribute__((always_inline)) +static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); + return (uint32_t)0; +} + +/** + * Format the paddr to be mappable + * + * @param mmu_id MMU ID + * @param paddr physical address to be mapped + * @param target paddr memory target, not used + * + * @return + * mmu_val - paddr in MMU table supported format + */ +__attribute__((always_inline)) +static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // (void)target; + // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // return paddr >> shift_code; + return (uint32_t)0; +} + +/** + * Write to the MMU table to map the virtual memory and the physical memory + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param mmu_val Value to be set into an MMU entry, for physical address + * @param target MMU target physical memory. + */ +__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // (void)target; + // uint32_t mmu_raw_value; + // if (mmu_ll_cache_encryption_enabled()) { + // mmu_val |= SOC_MMU_SENSITIVE; + // } + // // mmu_raw_value = mmu_val | SOC_MMU_VALID; + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); +} + +/** + * Read the raw value from MMU table + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param mmu_val Value to be read from MMU table + */ +__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // uint32_t mmu_raw_value; + // uint32_t ret; + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); + // if (mmu_ll_cache_encryption_enabled()) { + // mmu_raw_value &= ~SOC_MMU_SENSITIVE; + // } + // if (!(mmu_raw_value & SOC_MMU_VALID)) { + // return 0; + // } + // ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK; + // return ret; + return (uint32_t)0; +} + +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry + */ +__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID); +} + +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { + // mmu_ll_set_entry_invalid(mmu_id, i); + // } +} + +/** + * Check MMU table entry value is valid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * + * @return Ture for MMU entry is valid; False for invalid + */ +static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); + // // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false; + return (bool)0; +} + +/** + * Get the MMU table entry target + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * + * @return Target, see `mmu_target_t` + */ +static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // return MMU_TARGET_FLASH0; + return (mmu_target_t)0; +} + +/** + * Convert MMU entry ID to paddr base + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * + * @return paddr base + */ +static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); + // // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + // return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code; + return (uint32_t)0; +} + +/** + * Find the MMU table entry ID based on table map value + * @note This function can only find the first match entry ID. However it is possible that a physical address + * is mapped to multiple virtual addresses + * + * @param mmu_id MMU ID + * @param mmu_val map value to be read from MMU table standing for paddr + * @param target physical memory target, see `mmu_target_t` + * + * @return MMU entry ID, -1 for invalid + */ +static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { + // if (mmu_ll_check_entry_valid(mmu_id, i)) { + // if (mmu_ll_get_entry_target(mmu_id, i) == target) { + // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i); + // if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) { + // return i; + // } + // } + // } + // } + // // return -1; + return (int)0; +} + +/** + * Convert MMU entry ID to vaddr base + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + */ +static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type) +{ + // TODO: [ESP32C5] IDF-8658 (inherit from C6) + // (void)mmu_id; + // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + // uint32_t shift_code = 0; + // // switch (page_size) { + // case MMU_PAGE_64KB: + // shift_code = 16; + // break; + // case MMU_PAGE_32KB: + // shift_code = 15; + // break; + // case MMU_PAGE_16KB: + // shift_code = 14; + // break; + // case MMU_PAGE_8KB: + // shift_code = 13; + // break; + // default: + // HAL_ASSERT(shift_code); + // } + // uint32_t laddr = entry_id << shift_code; + // // /** + // * For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip. + // * Here we just pass MMU_TARGET_FLASH0 to get vaddr + // */ + // return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0); + return (uint32_t)0; +} + +#ifdef __cplusplus + return (uint32_t)0; +} +#endif diff --git a/components/hal/esp32c5/include/hal/mwdt_ll.h b/components/hal/esp32c5/include/hal/mwdt_ll.h new file mode 100644 index 00000000000..48e6af7d278 --- /dev/null +++ b/components/hal/esp32c5/include/hal/mwdt_ll.h @@ -0,0 +1,341 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" +#include "hal/wdt_types.h" +#include "hal/assert.h" +#include "esp_attr.h" +#include "esp_assert.h" +#include "hal/misc.h" + +/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */ +#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000 + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 + +//Type check wdt_stage_action_t +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the MWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_en = 1; +} + +/** + * @brief Disable the MWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_en = 0; +} + +/** + * Check if the MWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if the MWDT is enabled, false otherwise + */ +FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // return (hw->wdtconfig0.wdt_en) ? true : false; + return (bool)0; +} + +/** + * @brief Configure a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout + * @param behavior What action to take when the stage times out + */ +FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->wdtconfig0.wdt_stg0 = behavior; + // hw->wdtconfig2.wdt_stg0_hold = timeout; + // break; + // case WDT_STAGE1: + // hw->wdtconfig0.wdt_stg1 = behavior; + // hw->wdtconfig3.wdt_stg1_hold = timeout; + // break; + // case WDT_STAGE2: + // hw->wdtconfig0.wdt_stg2 = behavior; + // hw->wdtconfig4.wdt_stg2_hold = timeout; + // break; + // case WDT_STAGE3: + // hw->wdtconfig0.wdt_stg3 = behavior; + // hw->wdtconfig5.wdt_stg3_hold = timeout; + // break; + // default: + // HAL_ASSERT(false && "unsupported WDT stage"); + // break; + // } + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Disable a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // switch (stage) { + // case WDT_STAGE0: + // hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE1: + // hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE2: + // hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + // break; + // case WDT_STAGE3: + // hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + // break; + // default: + // HAL_ASSERT(false && "unsupported WDT stage"); + // break; + // } + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_cpu_reset_length = length; + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_sys_reset_length = length; + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Enable/Disable the MWDT flashboot mode. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the clock prescaler of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param prescaler Prescaler value between 1 to 65535 + */ +FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) + // // We take care of the "read-modify-write" procedure by ourselves. + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); + // //Config registers are updated asynchronously + // hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Feed the MWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtfeed.wdt_feed = 1; +} + +/** + * @brief Enable write protection of the MWDT registers + * + * Locking the MWDT will prevent any of the MWDT's registers from being modified + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtwprotect.wdt_wkey = 0; +} + +/** + * @brief Disable write protection of the MWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; +} + +/** + * @brief Clear the MWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->int_clr_timers.wdt_int_clr = 1; +} + +/** + * @brief Set the interrupt enable bit for the MWDT interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Whether to enable the MWDT interrupt + */ +FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; +} + +/** + * @brief Set the clock source for the MWDT. + * + * @param hw Beginning address of the peripheral registers. + * @param clk_src Clock source + */ +FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // uint8_t clk_id = 0; + // switch (clk_src) { + // case MWDT_CLK_SRC_XTAL: + // clk_id = 0; + // break; + // case MWDT_CLK_SRC_PLL_F80M: + // clk_id = 1; + // break; + // case MWDT_CLK_SRC_RC_FAST: + // clk_id = 2; + // break; + // default: + // HAL_ASSERT(false); + // break; + // } + // // if (hw == &TIMERG0) { + // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id; + // } else { + // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id; + // } +} + +/** + * @brief Enable MWDT module clock + * + * @param hw Beginning address of the peripheral registers. + * @param en true to enable, false to disable + */ +__attribute__((always_inline)) +static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en) +{ + // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // if (hw == &TIMERG0) { + // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en; + // } else { + // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en; + // } +} + + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/rwdt_ll.h b/components/hal/esp32c5/include/hal/rwdt_ll.h new file mode 100644 index 00000000000..f4f05993426 --- /dev/null +++ b/components/hal/esp32c5/include/hal/rwdt_ll.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +// The LL layer for RTC(LP) watchdog register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "hal/lpwdt_ll.h" + +typedef lp_wdt_dev_t rwdt_dev_t; + +#define RWDT_DEV_GET() &LP_WDT + +#define rwdt_ll_enable(hw) \ + lpwdt_ll_enable(hw) + +#define rwdt_ll_disable(hw) \ + lpwdt_ll_disable(hw) + +#define rwdt_ll_check_if_enabled(hw) \ + lpwdt_ll_check_if_enabled(hw) + +#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \ + lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) + +#define rwdt_ll_disable_stage(hw, stage) \ + lpwdt_ll_disable_stage(hw, stage) + +#define rwdt_ll_set_cpu_reset_length(hw, length) \ + lpwdt_ll_set_cpu_reset_length(hw, length) + +#define rwdt_ll_set_sys_reset_length(hw, length) \ + lpwdt_ll_set_sys_reset_length(hw, length) + +#define rwdt_ll_set_flashboot_en(hw, enable) \ + lpwdt_ll_set_flashboot_en(hw, enable) + +#define rwdt_ll_set_procpu_reset_en(hw, enable) \ + lpwdt_ll_set_procpu_reset_en(hw, enable) + +#define rwdt_ll_set_appcpu_reset_en(hw, enable) \ + lpwdt_ll_set_appcpu_reset_en(hw, enable) + +#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \ + lpwdt_ll_set_pause_in_sleep_en(hw, enable) + +#define rwdt_ll_set_chip_reset_en(hw, enable) \ + lpwdt_ll_set_chip_reset_en(hw, enable) + +#define rwdt_ll_set_chip_reset_width(hw, width) \ + lpwdt_ll_set_chip_reset_width(hw, width) + +#define rwdt_ll_feed(hw) \ + lpwdt_ll_feed(hw) + +#define rwdt_ll_write_protect_enable(hw) \ + lpwdt_ll_write_protect_enable(hw) + +#define rwdt_ll_write_protect_disable(hw) \ + lpwdt_ll_write_protect_disable(hw) + +#define rwdt_ll_set_intr_enable(hw, enable) \ + lpwdt_ll_set_intr_enable(hw, enable) + +#define rwdt_ll_check_intr_status(hw) \ + lpwdt_ll_check_intr_status(hw) + +#define rwdt_ll_clear_intr_status(hw) \ + lpwdt_ll_clear_intr_status(hw) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h new file mode 100644 index 00000000000..ab304bc657a --- /dev/null +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -0,0 +1,1413 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for UART register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include "esp_attr.h" +#include "hal/misc.h" +#include "hal/uart_types.h" +#include "soc/uart_reg.h" +#include "soc/uart_struct.h" +#include "soc/lp_uart_reg.h" +#include "soc/pcr_struct.h" +#include "soc/pcr_reg.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/lpperi_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// The default fifo depth +#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) +#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN) +// Get UART hardware instance with giving uart num +#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&LP_UART))) + +#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0) + +#define UART_LL_MIN_WAKEUP_THRESH (2) +#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask + +#define UART_LL_FSM_IDLE (0x0) +#define UART_LL_FSM_TX_WAIT_SEND (0xf) + +#define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ + if ((hw) == &UART0) { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \ + } else { \ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \ + } + +#define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ + (((hw) == &UART0) ? \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix) : \ + HAL_FORCE_READ_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix)) + +#define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ + if ((hw) == &UART0) { \ + PCR.uart0_##reg_suffix.uart0_##field_suffix = (val); \ + } else { \ + PCR.uart1_##reg_suffix.uart1_##field_suffix = (val); \ + } + +#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ + (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix) + +// Define UART interrupts +typedef enum { + UART_INTR_RXFIFO_FULL = (0x1 << 0), + UART_INTR_TXFIFO_EMPTY = (0x1 << 1), + UART_INTR_PARITY_ERR = (0x1 << 2), + UART_INTR_FRAM_ERR = (0x1 << 3), + UART_INTR_RXFIFO_OVF = (0x1 << 4), + UART_INTR_DSR_CHG = (0x1 << 5), + UART_INTR_CTS_CHG = (0x1 << 6), + UART_INTR_BRK_DET = (0x1 << 7), + UART_INTR_RXFIFO_TOUT = (0x1 << 8), + UART_INTR_SW_XON = (0x1 << 9), + UART_INTR_SW_XOFF = (0x1 << 10), + UART_INTR_GLITCH_DET = (0x1 << 11), + UART_INTR_TX_BRK_DONE = (0x1 << 12), + UART_INTR_TX_BRK_IDLE = (0x1 << 13), + UART_INTR_TX_DONE = (0x1 << 14), + UART_INTR_RS485_PARITY_ERR = (0x1 << 15), + UART_INTR_RS485_FRM_ERR = (0x1 << 16), + UART_INTR_RS485_CLASH = (0x1 << 17), + UART_INTR_CMD_CHAR_DET = (0x1 << 18), + UART_INTR_WAKEUP = (0x1 << 19), +} uart_intr_t; + +/** + * @brief Sync the update to UART core clock domain + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->reg_update.reg_update = 1; + // while (hw->reg_update.reg_update); +} + +/****************************************** LP_UART Specific ********************************************/ +/** + * @brief Get the LP_UART source clock. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk Current LP_UART clock source, one in soc_periph_lp_uart_clk_src_t. + */ +FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw; + // switch (LP_CLKRST.lpperi.lp_uart_clk_sel) { + // default: + // case 0: + // *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST; + // break; + // case 1: + // *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2; + // break; + // } +} + +/** + * @brief Set LP UART source clock + * + * @param hw Address offset of the LP UART peripheral registers + * @param src_clk Source clock for the LP UART peripheral + */ +static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw; + // switch (src_clk) { + // case LP_UART_SCLK_LP_FAST: + // LP_CLKRST.lpperi.lp_uart_clk_sel = 0; + // break; + // case LP_UART_SCLK_XTAL_D2: + // LP_CLKRST.lpperi.lp_uart_clk_sel = 1; + // break; + // default: + // // Invalid LP_UART clock source + // HAL_ASSERT(false); + // } +} + +/// LP_CLKRST.lpperi is a shared register, so this function must be used in an atomic way +#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__) + +/** + * @brief Configure the lp uart baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return None + */ +FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // ine DIV_UP(a, b) (((a) + (b) - 1) / (b)) + // const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + // uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + // // if (sclk_div == 0) abort(); + // // uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // // The baud rate configuration register is divided into + // // an integer part and a fractional part. + // hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + // hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); + // uart_ll_update(hw); +} + +/** + * @brief Enable bus clock for the LP UART module + * + * @param hw_id LP UART instance ID + * @param enable True to enable, False to disable + */ +static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw_id; + // LPPERI.clk_en.lp_uart_ck_en = enable; +} + +/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset LP UART module + * + * @param hw_id LP UART instance ID + */ +static inline void lp_uart_ll_reset_register(int hw_id) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // (void)hw_id; + // LPPERI.reset_en.lp_uart_reset_en = 1; + // LPPERI.reset_en.lp_uart_reset_en = 0; +} + +/// LPPERI.reset_en is a shared register, so this function must be used in an atomic way +#define lp_uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_reset_register(__VA_ARGS__) + +/*************************************** General LL functions ******************************************/ + +/** + * @brief Check if UART is enabled or disabled. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return true: enabled; false: disabled + */ +FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // HAL_ASSERT(uart_num < SOC_UART_HP_NUM); + // uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : + // (uart_num == 1) ? PCR_UART1_CONF_REG : 0); + // uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : + // (uart_num == 1) ? PCR_UART1_RST_EN : 0); + // uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : + // (uart_num == 1) ? PCR_UART1_CLK_EN : 0); + // return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && + // REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; + return (bool)0; +} + +/** + * @brief Enable the bus clock for uart + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * @param enable true to enable, false to disable + */ +static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // switch (uart_num) { + // case 0: + // PCR.uart0_conf.uart0_clk_en = enable; + // break; + // case 1: + // PCR.uart1_conf.uart1_clk_en = enable; + // break; + // default: + // // LP_UART + // abort(); + // break; + // } +} + +/** + * @brief Reset UART module + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + */ +static inline void uart_ll_reset_register(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // switch (uart_num) { + // case 0: + // PCR.uart0_conf.uart0_rst_en = 1; + // PCR.uart0_conf.uart0_rst_en = 0; + // break; + // case 1: + // PCR.uart1_conf.uart1_rst_en = 1; + // PCR.uart1_conf.uart1_rst_en = 0; + // break; + // default: + // // LP_UART + // abort(); + // break; + // } +} + +/** + * @brief Enable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1); + // } else { + // // LP_UART clk_en shares the same register with other LP peripherals + // // Needs to be protected with a lock, therefore, it has its unique LL function + // abort(); + // } +} + +/** + * @brief Disable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0); + // } else { + // // LP_UART clk_en shares the same register with other LP peripherals + // // Needs to be protected with a lock, therefore, it has its unique LL function + // abort(); + // } +} + +/** + * @brief Set the UART source clock. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The UART source clock. The source clock can be PLL_F80M clock, RTC clock or XTAL clock. + * All clock sources can remain at their original frequencies during DFS. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // uint32_t sel_value = 0; + // switch (source_clk) { + // case UART_SCLK_PLL_F80M: + // sel_value = 1; + // break; + // case UART_SCLK_RTC: + // sel_value = 2; + // break; + // case UART_SCLK_XTAL: + // sel_value = 3; + // break; + // default: + // // Invalid HP_UART clock source + // abort(); + // } + // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value); + // } else { + // // LP_UART clk_sel shares the same register with other LP peripherals + // // Needs to be protected with a lock, therefore, it has its unique LL function + // abort(); + // } +} + +/** + * @brief Get the UART source clock type. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The pointer to accept the UART source clock type. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if ((hw) != &LP_UART) { + // switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { + // default: + // case 1: + // *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; + // break; + // case 2: + // *source_clk = (soc_module_clk_t)UART_SCLK_RTC; + // break; + // case 3: + // *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; + // break; + // } + // } else { + // lp_uart_ll_get_sclk(hw, source_clk); + // } +} + +/** + * @brief Configure the baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // ine DIV_UP(a, b) (((a) + (b) - 1) / (b)) + // const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + // uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + // // if (sclk_div == 0) abort(); + // // uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // // The baud rate configuration register is divided into + // // an integer part and a fractional part. + // hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + // hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + // if ((hw) == &LP_UART) { + // abort(); + // } else { + // UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); + // } + // ef DIV_UP + // uart_ll_update(hw); +} + +/** + * @brief Get the current baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return The current baudrate + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // typeof(hw->clkdiv_sync) div_reg; + // div_reg.val = hw->clkdiv_sync.val; + // int sclk_div; + // if ((hw) == &LP_UART) { + // sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; + // } else { + // sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; + // } + // return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div); + return (uint32_t)0; +} + +/** + * @brief Enable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->int_ena.val = hw->int_ena.val | mask; +} + +/** + * @brief Disable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->int_ena.val = hw->int_ena.val & (~mask); +} + +/** + * @brief Get the UART raw interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART interrupt status. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->int_raw.val; + return (uint32_t)0; +} + +/** + * @brief Get the UART interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART interrupt status. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->int_st.val; + return (uint32_t)0; +} + +/** + * @brief Clear the UART interrupt status based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @param hw Beginning address of the peripheral registers. + * + * @return interrupt enable value + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->int_ena.val; + return (uint32_t)0; +} + +/** + * @brief Read the UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. The buffer size should be large than 128 byts. + * @param rd_len The data length needs to be read. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // for (int i = 0; i < (int)rd_len; i++) { + // buf[i] = hw->fifo.rxfifo_rd_byte; + // } +} + +/** + * @brief Write byte to the UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. + * @param wr_len The data length needs to be written. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // for (int i = 0; i < (int)wr_len; i++) { + // hw->fifo.rxfifo_rd_byte = buf[i]; + // } +} + +/** + * @brief Reset the UART hw rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.rxfifo_rst = 1; + // uart_ll_update(hw); + // hw->conf0_sync.rxfifo_rst = 0; + // uart_ll_update(hw); +} + +/** + * @brief Reset the UART hw txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.txfifo_rst = 1; + // uart_ll_update(hw); + // hw->conf0_sync.txfifo_rst = 0; + // uart_ll_update(hw); +} + +/** + * @brief Get the length of readable data in UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The readable data length in rxfifo. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); + return (uint32_t)0; +} + +/** + * @brief Get the writable data length of UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The data length of txfifo can be written. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN; + // uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); + // return (total_fifo_len - txfifo_len); + return (uint32_t)0; +} + +/** + * @brief Configure the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The stop bit number to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.stop_bit_num = stop_bit; + // uart_ll_update(hw); +} + +/** + * @brief Get the configuration of the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The pointer to accept the stop bit configuration + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num; +} + +/** + * @brief Configure the UART parity check mode. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The parity check mode to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (parity_mode != UART_PARITY_DISABLE) { + // hw->conf0_sync.parity = parity_mode & 0x1; + // } + // hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1; + // uart_ll_update(hw); +} + +/** + * @brief Get the UART parity check mode configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The pointer to accept the parity check mode configuration. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (hw->conf0_sync.parity_en) { + // *parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity); + // } else { + // *parity_mode = UART_PARITY_DISABLE; + // } +} + +/** + * @brief Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, + * it will produce rxfifo_full_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `(LP_)UART_LL_FIFO_DEF_LEN`. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); +} + +/** + * @brief Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, + * it will produce txfifo_empty_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param empty_thrhd The empty threshold of txfifo. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); +} + +/** + * @brief Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, + * it will produce frame end signal for uhci to stop receiving data. + * + * @param hw Beginning address of the peripheral registers. + * @param rx_idle_thr The rx-idle threshold to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr; + // uart_ll_update(hw); +} + +/** + * @brief Configure the duration time between transfers. + * + * @param hw Beginning address of the peripheral registers. + * @param idle_num the duration time between transfers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->idle_conf_sync.tx_idle_num = idle_num; + // uart_ll_update(hw); +} + +/** + * @brief Configure the transmiter to send break chars. + * + * @param hw Beginning address of the peripheral registers. + * @param break_num The number of the break chars need to be send. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (break_num > 0) { + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); + // hw->conf0_sync.txd_brk = 1; + // } else { + // hw->conf0_sync.txd_brk = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The hw flow control configuration. + * @param rx_thrs The rx flow control signal will be active if the data length in rxfifo is more than this value. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. + // if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { + // hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw); + // hw->hwfc_conf_sync.rx_flow_en = 1; + // } else { + // hw->hwfc_conf_sync.rx_flow_en = 0; + // } + // if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { + // hw->conf0_sync.tx_flow_en = 1; + // } else { + // hw->conf0_sync.tx_flow_en = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Configure the hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl A pointer to accept the hw flow control configuration. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + // if (hw->hwfc_conf_sync.rx_flow_en) { + // *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS); + // } + // if (hw->conf0_sync.tx_flow_en) { + // *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS); + // } +} + +/** + * @brief Configure the software flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The UART sofware flow control settings. + * @param sw_flow_ctrl_en Set true to enable software flow control, otherwise set it false. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // if (sw_flow_ctrl_en) { + // hw->swfc_conf0_sync.xonoff_del = 1; + // hw->swfc_conf0_sync.sw_flow_con_en = 1; + // hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); + // hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); + // } else { + // hw->swfc_conf0_sync.sw_flow_con_en = 0; + // hw->swfc_conf0_sync.xonoff_del = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The AT cmd char configuration.The configuration member is: + * - cmd_char The AT cmd character + * - char_num The number of received AT cmd char must be equal to or greater than this value + * - gap_tout The interval between each AT cmd char, when the duration is less than this value, it will not take this data as AT cmd char + * - pre_idle The idle time before the first AT cmd char, when the duration is less than this value, it will not take the previous data as the last AT cmd char + * - post_idle The idle time after the last AT cmd char, when the duration is less than this value, it will not take this data as the first AT cmd char + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle); + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout); + // uart_ll_update(hw); +} + +/** + * @brief Set the UART data bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The data bit mode to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.bit_num = data_bit; + // uart_ll_update(hw); +} + +/** + * @brief Set the rts active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The rts active level, 0 or 1. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.sw_rts = level & 0x1; + // uart_ll_update(hw); +} + +/** + * @brief Set the dtr active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The dtr active level, 0 or 1. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf1.sw_dtr = level & 0x1; +} + +/** + * @brief Set the UART wakeup threshold. + * + * @param hw Beginning address of the peripheral registers. + * @param wakeup_thrd The wakeup threshold value to be set. When the input rx edge changes more than this value, + * the UART will active from light sleeping mode. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; +} + +/** + * @brief Configure the UART work in normal mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->rs485_conf_sync.rs485_en = 0; + // hw->rs485_conf_sync.rs485tx_rx_en = 0; + // hw->rs485_conf_sync.rs485rxby_tx_en = 0; + // hw->conf0_sync.irda_en = 0; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in rs485_app_ctrl mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // // Application software control, remove echo + // hw->rs485_conf_sync.rs485rxby_tx_en = 1; + // hw->conf0_sync.irda_en = 0; + // hw->conf0_sync.sw_rts = 0; + // hw->conf0_sync.irda_en = 0; + // hw->rs485_conf_sync.dl0_en = 1; + // hw->rs485_conf_sync.dl1_en = 1; + // hw->rs485_conf_sync.rs485_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in rs485_half_duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // // Enable receiver, sw_rts = 1 generates low level on RTS pin + // hw->conf0_sync.sw_rts = 1; + // // Half duplex mode + // hw->rs485_conf_sync.rs485tx_rx_en = 0; + // // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). + // // But note that this full-duplex mode has no conflict detection function + // hw->rs485_conf_sync.rs485rxby_tx_en = 0; + // hw->conf0_sync.irda_en = 0; + // hw->rs485_conf_sync.dl0_en = 1; + // hw->rs485_conf_sync.dl1_en = 1; + // hw->rs485_conf_sync.rs485_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in collision_detect mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->conf0_sync.irda_en = 0; + // // Enable full-duplex mode + // hw->rs485_conf_sync.rs485tx_rx_en = 1; + // // Transmitter should send data when the receiver is busy, + // hw->rs485_conf_sync.rs485rxby_tx_en = 1; + // hw->rs485_conf_sync.dl0_en = 1; + // hw->rs485_conf_sync.dl1_en = 1; + // hw->conf0_sync.sw_rts = 0; + // hw->rs485_conf_sync.rs485_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Configure the UART work in irda mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // This function is only for HP_UART use + // // LP_UART can only work in normal mode + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->rs485_conf_sync.rs485_en = 0; + // hw->rs485_conf_sync.rs485tx_rx_en = 0; + // hw->rs485_conf_sync.rs485rxby_tx_en = 0; + // hw->conf0_sync.sw_rts = 0; + // hw->conf0_sync.irda_en = 1; + // uart_ll_update(hw); +} + +/** + * @brief Set uart mode. + * + * @param hw Beginning address of the peripheral registers. + * @param mode The UART mode to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // switch (mode) { + // default: + // case UART_MODE_UART: + // uart_ll_set_mode_normal(hw); + // break; + // case UART_MODE_RS485_COLLISION_DETECT: + // // Only HP_UART support this mode + // uart_ll_set_mode_collision_detect(hw); + // break; + // case UART_MODE_RS485_APP_CTRL: + // // Only HP_UART support this mode + // uart_ll_set_mode_rs485_app_ctrl(hw); + // break; + // case UART_MODE_RS485_HALF_DUPLEX: + // // Only HP_UART support this mode + // uart_ll_set_mode_rs485_half_duplex(hw); + // break; + // case UART_MODE_IRDA: + // // Only HP_UART support this mode + // uart_ll_set_mode_irda(hw); + // break; + // } +} + +/** + * @brief Get the UART AT cmd char configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The Pointer to accept value of UART AT cmd char. + * @param char_num Pointer to accept the repeat number of UART AT cmd char. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data); + // *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num); +} + +/** + * @brief Get the UART wakeup threshold value. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART wakeup threshold value. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH; + return (uint32_t)0; +} + +/** + * @brief Get the UART data bit configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The pointer to accept the UART data bit configuration. + * + * @return The bit mode. + */ +FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // *data_bit = (uart_word_length_t)hw->conf0_sync.bit_num; +} + +/** + * @brief Check if the UART sending state machine is in the IDLE state. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if the state machine is in the IDLE state, otherwise false is returned. + */ +FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0)); + return (bool)0; +} + +/** + * @brief Check if the UART rts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw rts flow control is enabled, otherwise false is returned. + */ +FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->hwfc_conf_sync.rx_flow_en; + return (bool)0; +} + +/** + * @brief Check if the UART cts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw cts flow control is enabled, otherwise false is returned. + */ +FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return hw->conf0_sync.tx_flow_en; + return (bool)0; +} + +/** + * @brief Configure TX signal loop back to RX module, just for the testing purposes + * + * @param hw Beginning address of the peripheral registers. + * @param loop_back_en Set ture to enable the loop back function, else set it false. + * + * @return None + */ +FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.loopback = loop_back_en; + // uart_ll_update(hw); +} + +FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->swfc_conf0_sync.force_xon = 1; + // uart_ll_update(hw); + // if (!always_on) { + // hw->swfc_conf0_sync.force_xon = 0; + // uart_ll_update(hw); + // } +} + +/** + * @brief Inverse the UART signal with the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param inv_mask The UART signal bitmap needs to be inversed. + * Use the ORred mask of `uart_signal_inv_t`; + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV + // // lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // typeof(hw->conf0_sync) conf0_reg; + // conf0_reg.val = hw->conf0_sync.val; + // conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; + // conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; + // conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; + // conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; + // hw->conf0_sync.val = conf0_reg.val; + // // typeof(hw->conf1) conf1_reg; + // conf1_reg.val = hw->conf1.val; + // conf1_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; + // conf1_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; + // conf1_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; + // conf1_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; + // hw->conf1.val = conf1_reg.val; + // uart_ll_update(hw); +} + +/** + * @brief Configure the timeout value for receiver receiving a byte, and enable rx timeout function. + * + * @param hw Beginning address of the peripheral registers. + * @param tout_thrd The timeout value as UART bit time. The rx timeout function will be disabled if `tout_thrd == 0`. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uint16_t tout_val = tout_thrd; + // if (tout_thrd > 0) { + // hw->tout_conf_sync.rx_tout_thrhd = tout_val; + // hw->tout_conf_sync.rx_tout_en = 1; + // } else { + // hw->tout_conf_sync.rx_tout_en = 0; + // } + // uart_ll_update(hw); +} + +/** + * @brief Get the timeout value for receiver receiving a byte. + * + * @param hw Beginning address of the peripheral registers. + * + * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. + */ +FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uint16_t tout_thrd = 0; + // if (hw->tout_conf_sync.rx_tout_en > 0) { + // tout_thrd = hw->tout_conf_sync.rx_tout_thrhd; + // } + // return tout_thrd; + return (uint16_t)0; +} + +/** + * @brief Get UART maximum timeout threshold. + * + * @param hw Beginning address of the peripheral registers. + * + * @return maximum timeout threshold. + */ +FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V; + return (uint16_t)0; +} + +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support autobaud + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // hw->conf0_sync.autobaud_en = enable ? 1 : 0; + // uart_ll_update(hw); +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->rxd_cnt.rxd_edge_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->pospulse.posedge_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->negpulse.negedge_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->highpulse.highpulse_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // // LP_UART does not support this feature + // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + // // return hw->lowpulse.lowpulse_min_cnt; + return (uint32_t)0; +} + +/** + * @brief Force UART xoff. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uart_dev_t *hw = UART_LL_GET_HW(uart_num); + // hw->swfc_conf0_sync.force_xon = 0; + // hw->swfc_conf0_sync.sw_flow_con_en = 1; + // hw->swfc_conf0_sync.force_xoff = 1; + // uart_ll_update(hw); +} + +/** + * @brief Force UART xon. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uart_dev_t *hw = UART_LL_GET_HW(uart_num); + // hw->swfc_conf0_sync.force_xoff = 0; + // hw->swfc_conf0_sync.force_xon = 1; + // hw->swfc_conf0_sync.sw_flow_con_en = 0; + // hw->swfc_conf0_sync.force_xon = 0; + // uart_ll_update(hw); +} + +/** + * @brief Get UART finite-state machine status. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return UART module FSM status. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_tx_fsm_status(uart_port_t uart_num) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // uart_dev_t *hw = UART_LL_GET_HW(uart_num); + // return hw->fsm_status.st_utx_out; + return (uint32_t)0; +} + +/** + * @brief Configure UART whether to discard when receiving wrong data + * + * @param hw Beginning address of the peripheral registers. + * @param discard true: Receiver stops storing data into FIFO when data is wrong + * false: Receiver continue storing data into FIFO when data is wrong + */ +FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard) +{ + // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) + // hw->conf0_sync.err_wr_mask = discard ? 1 : 0; + // uart_ll_update(hw); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/brownout_ll.h b/components/hal/esp32c6/include/hal/brownout_ll.h index e0614583a44..913f99ff0bf 100644 --- a/components/hal/esp32c6/include/hal/brownout_ll.h +++ b/components/hal/esp32c6/include/hal/brownout_ll.h @@ -115,6 +115,15 @@ static inline void brownout_ll_intr_clear(void) LP_ANA_PERI.int_clr.bod_mode0 = 1; } +/** + * @brief Clear BOD internal count. + */ +static inline void brownout_ll_clear_count(void) +{ + LP_ANA_PERI.bod_mode0_cntl.bod_mode0_cnt_clr = 1; + LP_ANA_PERI.bod_mode0_cntl.bod_mode0_cnt_clr = 0; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h index 237c10d645a..071a0e8d887 100644 --- a/components/hal/esp32c6/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h @@ -93,7 +93,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en switch (periph) { case PERIPH_SARADC_MODULE: - return PCR_SARADC_RST_EN; + return PCR_SARADC_REG_RST_EN; case PERIPH_RMT_MODULE: return PCR_RMT_RST_EN; case PERIPH_PCNT_MODULE: diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h index 22bc8351773..a40dd68b125 100644 --- a/components/hal/esp32c6/include/hal/etm_ll.h +++ b/components/hal/esp32c6/include/hal/etm_ll.h @@ -11,6 +11,7 @@ #include #include "hal/assert.h" #include "hal/misc.h" +#include "hal/lp_aon_ll.h" #include "soc/soc_etm_struct.h" #include "soc/pcr_struct.h" @@ -112,6 +113,10 @@ static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uin hw->channel[chan].task_id.task_id = task; } +#define etm_ll_is_lpcore_wakeup_triggered() lp_aon_ll_get_lpcore_etm_wakeup_flag() + +#define etm_ll_clear_lpcore_wakeup_status() lp_aon_ll_clear_lpcore_etm_wakeup_flag() + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/gdma_ll.h b/components/hal/esp32c6/include/hal/gdma_ll.h index bdccf27035d..054bd741a4e 100644 --- a/components/hal/esp32c6/include/hal/gdma_ll.h +++ b/components/hal/esp32c6/include/hal/gdma_ll.h @@ -125,9 +125,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable) * @brief Get DMA RX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->in_intr[channel].st.val; + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } } /** @@ -349,9 +353,13 @@ static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->out_intr[channel].st.val; + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } } /** diff --git a/components/hal/esp32c6/include/hal/lp_aon_ll.h b/components/hal/esp32c6/include/hal/lp_aon_ll.h index ef77b7561d2..c212d33b9ae 100644 --- a/components/hal/esp32c6/include/hal/lp_aon_ll.h +++ b/components/hal/esp32c6/include/hal/lp_aon_ll.h @@ -47,21 +47,14 @@ static inline void lp_aon_ll_ext1_clear_wakeup_status(void) */ static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) { - uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); - wakeup_sel_mask |= io_mask; - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask); - - uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv); - wakeup_level_mask |= io_mask & level_mask; - wakeup_level_mask &= ~(io_mask & ~level_mask); - - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask); } /** * @brief Clear all ext1 wakup-source setting */ -static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) { HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0); } @@ -92,6 +85,24 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp) } } +/** + * @brief Get the flag that marks whether LP CPU is awakened by ETM + * + * @return Return true if lpcore is woken up by soc_etm + */ +static inline bool lp_aon_ll_get_lpcore_etm_wakeup_flag(void) +{ + return REG_GET_BIT(LP_AON_LPCORE_REG, LP_AON_LPCORE_ETM_WAKEUP_FLAG); +} + +/** + * @brief Clear the flag that marks whether LP CPU is awakened by soc_etm + */ +static inline void lp_aon_ll_clear_lpcore_etm_wakeup_flag(void) +{ + REG_SET_BIT(LP_AON_LPCORE_REG, LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/lp_core_ll.h b/components/hal/esp32c6/include/hal/lp_core_ll.h new file mode 100644 index 00000000000..c79830f5f0b --- /dev/null +++ b/components/hal/esp32c6/include/hal/lp_core_ll.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use it in application code. + ******************************************************************************/ + +#pragma once + +#include +#include "soc/lpperi_struct.h" +#include "soc/pmu_struct.h" +#include "soc/lp_aon_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses +#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt +#define LP_CORE_LL_WAKEUP_SOURCE_ETM BIT(3) // Enable wake-up by ETM event +#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER BIT(4) // Enable wake-up by LP timer + +/** + * @brief Enable the bus clock for LP-core + * + * @param enable Enable if true, disable if false + */ +static inline void lp_core_ll_enable_bus_clock(bool enable) +{ + /* ESP32C6 does not have clk/rst periph control for LP-core */ + (void)enable; +} + +/** + * @brief Reset the lp_core module + * + */ +static inline void lp_core_ll_reset_register(void) +{ + /* ESP32C6 does not have clk/rst periph control for LP-core */ +} + +/** + * @brief Enable fast access of LP memory + * + * @note When fast access is activated, LP-core cannot access LP mem during deep sleep + * + * @param enable Enable if true, disable if false + */ +static inline void lp_core_ll_fast_lp_mem_enable(bool enable) +{ + LP_AON.lpbus.fast_mem_mux_sel = enable; + LP_AON.lpbus.fast_mem_mux_sel_update = 1; +} + +/** + * @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the LP-core + * + */ +static inline void lp_core_ll_hp_wake_lp(void) +{ + PMU.hp_lp_cpu_comm.hp_trigger_lp = 1; +} + +/** + * @brief Enable the debug module of LP-core, allowing JTAG to connect + * + * @param enable Enable if true, disable if false + */ +static inline void lp_core_ll_debug_module_enable(bool enable) +{ + LPPERI.cpu.lpcore_dbgm_unavaliable = !enable; +} + +/** + * @brief Enable CPU reset at sleep + * + * @param enable Enable if true, disable if false + */ +static inline void lp_core_ll_rst_at_sleep_enable(bool enable) +{ + PMU.lp_ext.pwr0.slp_reset_en = enable; +} + +/** + * @brief Stall LP-core at sleep requests + * + * @param enable Enable if true, disable if false + */ +static inline void lp_core_ll_stall_at_sleep_request(bool enable) +{ + PMU.lp_ext.pwr0.slp_stall_en = enable; +} + +/** + * @brief Set wake-up sources for the LP-core + * + * @param flags Wake-up sources + */ +static inline void lp_core_ll_set_wakeup_source(uint32_t flags) +{ + PMU.lp_ext.pwr1.wakeup_en = flags; +} + +/** + * @brief Get wake-up sources for the LP-core + */ +static inline uint32_t lp_core_ll_get_wakeup_source(void) +{ + return PMU.lp_ext.pwr1.wakeup_en; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/lp_timer_ll.h b/components/hal/esp32c6/include/hal/lp_timer_ll.h index a99349240be..d04bccb5590 100644 --- a/components/hal/esp32c6/include/hal/lp_timer_ll.h +++ b/components/hal/esp32c6/include/hal/lp_timer_ll.h @@ -12,6 +12,7 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/lp_timer_struct.h" +#include "soc/lp_timer_reg.h" #include "soc/lp_aon_reg.h" #include "hal/lp_timer_types.h" #include "esp_attr.h" @@ -61,6 +62,16 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *de dev->lp_int_clr.alarm = 1; } +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev) +{ + return dev->lp_int_raw.val; +} + +FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask) +{ + dev->lp_int_clr.val = mask; +} + FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us) { uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG); diff --git a/components/hal/esp32c6/include/hal/pmu_ll.h b/components/hal/esp32c6/include/hal/pmu_ll.h index 15f39d10e49..2470f73247c 100644 --- a/components/hal/esp32c6/include/hal/pmu_ll.h +++ b/components/hal/esp32c6/include/hal/pmu_ll.h @@ -531,6 +531,16 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw) return hw->wakeup.status1; } +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw) +{ + return hw->lp_ext.int_raw.val; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask) +{ + hw->lp_ext.int_clr.val = mask; +} + FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle) { hw->wakeup.cntl3.lp_min_slp_val = slow_clk_cycle; diff --git a/components/hal/esp32c6/include/hal/spimem_flash_ll.h b/components/hal/esp32c6/include/hal/spimem_flash_ll.h index 3c5d93da482..b80187f2e01 100644 --- a/components/hal/esp32c6/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c6/include/hal/spimem_flash_ll.h @@ -248,6 +248,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + // Not supported on this chip. +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32c6/include/hal/systimer_ll.h b/components/hal/esp32c6/include/hal/systimer_ll.h index 74dedc721fc..aa680917575 100644 --- a/components/hal/esp32c6/include/hal/systimer_ll.h +++ b/components/hal/esp32c6/include/hal/systimer_ll.h @@ -37,6 +37,35 @@ static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + PCR.systimer_conf.systimer_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + PCR.systimer_conf.systimer_rst_en = 1; + PCR.systimer_conf.systimer_rst_en = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /********************** ETM *****************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en) diff --git a/components/hal/esp32c6/include/hal/temperature_sensor_ll.h b/components/hal/esp32c6/include/hal/temperature_sensor_ll.h index a50d56f489c..9ecd97727e1 100644 --- a/components/hal/esp32c6/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32c6/include/hal/temperature_sensor_ll.h @@ -103,7 +103,7 @@ static inline void temperature_sensor_ll_set_range(uint32_t range) __attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_raw_value(void) { - return APB_SARADC.saradc_apb_tsens_ctrl.saradc_tsens_out; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_out); } /** @@ -127,7 +127,7 @@ static inline uint32_t temperature_sensor_ll_get_offset(void) */ static inline uint32_t temperature_sensor_ll_get_clk_div(void) { - return APB_SARADC.saradc_apb_tsens_ctrl.saradc_tsens_clk_div; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_clk_div); } /** @@ -140,7 +140,7 @@ static inline uint32_t temperature_sensor_ll_get_clk_div(void) */ static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) { - APB_SARADC.saradc_apb_tsens_ctrl.saradc_tsens_clk_div = clk_div; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_clk_div, clk_div); } /** @@ -155,6 +155,17 @@ static inline void temperature_sensor_ll_wakeup_mode(uint8_t mode) APB_SARADC.tsens_wake.saradc_wakeup_mode = mode; } +/** + * @brief Get temperature sensor interrupt/wakeup in which reason + * + * @return uint8_t 0: temperature value lower than low threshold 1: otherwise, higher than high threshold. + */ +__attribute__((always_inline)) +static inline uint8_t temperature_sensor_ll_get_wakeup_reason(void) +{ + return APB_SARADC.tsens_wake.saradc_wakeup_over_upper_th; +} + /** * @brief Configure whether to enable temperature sensor wake up * @@ -172,7 +183,7 @@ static inline void temperature_sensor_ll_wakeup_enable(bool en) */ static inline void temperature_sensor_ll_set_th_low_val(uint8_t th_low) { - APB_SARADC.tsens_wake.saradc_wakeup_th_low = th_low; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_low, th_low); } /** @@ -182,7 +193,7 @@ static inline void temperature_sensor_ll_set_th_low_val(uint8_t th_low) */ static inline void temperature_sensor_ll_set_th_high_val(uint8_t th_high) { - APB_SARADC.tsens_wake.saradc_wakeup_th_high = th_high; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_high, th_high); } /** diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h index f24c417053f..f19c303cc00 100644 --- a/components/hal/esp32c6/include/hal/uart_ll.h +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -265,25 +265,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) } } -/** - * @brief Configure the UART core reset. - * - * @param hw Beginning address of the peripheral registers. - * @param core_rst_en True to enable the core reset, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) -{ - if ((hw) != &LP_UART) { - UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en); - } else { - // LP_UART reset shares the same register with other LP peripherals - // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c - abort(); - } -} - /** * @brief Enable the UART clock. * @@ -297,7 +278,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1); } else { // LP_UART clk_en shares the same register with other LP peripherals - // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + // Needs to be protected with a lock, therefore, it has its unique LL function abort(); } } @@ -315,7 +296,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0); } else { // LP_UART clk_en shares the same register with other LP peripherals - // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + // Needs to be protected with a lock, therefore, it has its unique LL function abort(); } } @@ -350,7 +331,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value); } else { // LP_UART clk_sel shares the same register with other LP peripherals - // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + // Needs to be protected with a lock, therefore, it has its unique LL function abort(); } } diff --git a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h index 56abbf38b9f..e0776eb9230 100644 --- a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h @@ -7,6 +7,9 @@ // The LL layer of the USB-serial-jtag controller #pragma once +#include +#include "esp_attr.h" +#include "soc/pcr_struct.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" @@ -158,8 +161,14 @@ static inline int usb_serial_jtag_ll_txfifo_writable(void) * @brief Flushes the TX buffer, that is, make it available for the * host to pick up. * - * @note When fifo is full (with 64 byte), HW will flush the buffer automatically. - * It won't be executed if there is nothing in the fifo. + * @note When fifo is full (with 64 byte), HW will flush the buffer automatically, + * if this function is called directly after, this effectively turns into a + * no-op. Because a 64-byte packet will be interpreted as a not-complete USB + * transaction, you need to transfer either more data or a zero-length packet + * for the data to actually end up at the program listening to the CDC-ACM + * serial port. To send a zero-length packet, call + * usb_serial_jtag_ll_txfifo_flush() again when + * usb_serial_jtag_ll_txfifo_writable() returns true. * * @return na */ @@ -169,6 +178,59 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void) } +/** + * @brief Disable usb serial jtag pad during light sleep to avoid current leakage + * + * @return Initial configuration of usb serial jtag pad enable before light sleep + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void) +{ + bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable; + + // Disable USB pad function + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + + return pad_enabled; +} + +/** + * @brief Enable the internal USJ PHY control to D+/D- pad + * + * @param enable_pad Enable the USJ PHY control to D+/D- pad + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad) +{ + USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad; +} + +/** + * @brief Enable the bus clock for USB Serial_JTAG module + * @param clk_en True if enable the clock of USB Serial_JTAG module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) +{ + PCR.usb_device_conf.usb_device_clk_en = clk_en; +} + +/** + * @brief Reset the usb serial jtag module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void) +{ + PCR.usb_device_conf.usb_device_rst_en = 1; + PCR.usb_device_conf.usb_device_rst_en = 0; +} + +/** + * Get the enable status USB Serial_JTAG module + * + * @return Return true if USB Serial_JTAG module is enabled + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void) +{ + return (PCR.usb_device_conf.usb_device_clk_en && !PCR.usb_device_conf.usb_device_rst_en); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/modem_clock_hal.c b/components/hal/esp32c6/modem_clock_hal.c index 6707c9b0123..ed242febec4 100644 --- a/components/hal/esp32c6/modem_clock_hal.c +++ b/components/hal/esp32c6/modem_clock_hal.c @@ -36,7 +36,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte case MODEM_CLOCK_DOMAIN_BT: modem_syscon_ll_set_bt_icg_bitmap(hal->syscon_dev, bitmap); break; - case MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE: + case MODEM_CLOCK_DOMAIN_MODEM_FE: modem_syscon_ll_set_fe_icg_bitmap(hal->syscon_dev, bitmap); break; case MODEM_CLOCK_DOMAIN_IEEE802154: @@ -55,11 +55,11 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte modem_lpcon_ll_set_wifipwr_icg_bitmap(hal->lpcon_dev, bitmap); break; default: - break; + HAL_ASSERT(0); } } -uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain) +uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; @@ -77,7 +77,7 @@ uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t * case MODEM_CLOCK_DOMAIN_BT: bitmap = modem_syscon_ll_get_bt_icg_bitmap(hal->syscon_dev); break; - case MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE: + case MODEM_CLOCK_DOMAIN_MODEM_FE: bitmap = modem_syscon_ll_get_fe_icg_bitmap(hal->syscon_dev); break; case MODEM_CLOCK_DOMAIN_IEEE802154: @@ -96,7 +96,7 @@ uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t * bitmap = modem_lpcon_ll_get_wifipwr_icg_bitmap(hal->lpcon_dev); break; default: - break; + HAL_ASSERT(0); } return bitmap; } @@ -163,7 +163,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); break; default: - break; + HAL_ASSERT(0); } } @@ -203,7 +203,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); break; default: - break; + HAL_ASSERT(0); } } @@ -243,7 +243,7 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); break; default: - break; + HAL_ASSERT(0); } } diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h index 5e4fbce2b26..dd9c8113798 100644 --- a/components/hal/esp32h2/include/hal/adc_ll.h +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -42,7 +42,7 @@ extern "C" { Oneshot ---------------------------------------------------------------*/ #define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) -#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (2) +#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5) /*--------------------------------------------------------------- DMA diff --git a/components/hal/esp32h2/include/hal/brownout_ll.h b/components/hal/esp32h2/include/hal/brownout_ll.h index 7885decbfd2..f0b3d63263e 100644 --- a/components/hal/esp32h2/include/hal/brownout_ll.h +++ b/components/hal/esp32h2/include/hal/brownout_ll.h @@ -115,6 +115,15 @@ static inline void brownout_ll_intr_clear(void) LP_ANA_PERI.int_clr.bod_mode0_int_clr = 1; } +/** + * @brief Clear BOD internal count. + */ +static inline void brownout_ll_clear_count(void) +{ + LP_ANA_PERI.bod_mode0_cntl.bod_mode0_cnt_clr = 1; + LP_ANA_PERI.bod_mode0_cntl.bod_mode0_cnt_clr = 0; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h index c0549ffdab8..d49ae217b6c 100644 --- a/components/hal/esp32h2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -106,7 +106,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en switch (periph) { case PERIPH_SARADC_MODULE: - return PCR_SARADC_RST_EN; + return PCR_SARADC_REG_RST_EN; case PERIPH_RMT_MODULE: return PCR_RMT_RST_EN; case PERIPH_PCNT_MODULE: @@ -358,16 +358,14 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +static inline void periph_ll_wifi_bt_module_enable_clk(void) { // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// ESP32H2-TODO: IDF-6400 - // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } -static inline void periph_ll_wifi_bt_module_disable_clk_set_rst(void) +static inline void periph_ll_wifi_bt_module_disable_clk(void) { // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// ESP32H2-TODO: IDF-6400 - // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } static inline void periph_ll_reset(periph_module_t periph) diff --git a/components/hal/esp32h2/include/hal/ecdsa_ll.h b/components/hal/esp32h2/include/hal/ecdsa_ll.h index fc1162603f6..3e16b9726cd 100644 --- a/components/hal/esp32h2/include/hal/ecdsa_ll.h +++ b/components/hal/esp32h2/include/hal/ecdsa_ll.h @@ -23,7 +23,6 @@ typedef enum { ECDSA_PARAM_R, ECDSA_PARAM_S, ECDSA_PARAM_Z, - ECDSA_PARAM_K, ECDSA_PARAM_QAX, ECDSA_PARAM_QAY } ecdsa_ll_param_t; @@ -190,26 +189,6 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve) } } -/** - * @brief Set the source of `K` - * - * @param mode Mode of K generation - */ -static inline void ecdsa_ll_set_k_mode(ecdsa_k_mode_t mode) -{ - switch (mode) { - case ECDSA_K_USE_TRNG: - REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_K); - break; - case ECDSA_K_USER_PROVIDED: - REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_K); - break; - default: - HAL_ASSERT(false && "Unsupported curve"); - break; - } -} - /** * @brief Set the source of `Z` (SHA message) * @@ -335,7 +314,6 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b case ECDSA_PARAM_Z: reg = ECDSA_Z_MEM; break; - case ECDSA_PARAM_K: case ECDSA_PARAM_QAX: reg = ECDSA_QAX_MEM; break; @@ -373,7 +351,6 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin case ECDSA_PARAM_Z: reg = ECDSA_Z_MEM; break; - case ECDSA_PARAM_K: case ECDSA_PARAM_QAX: reg = ECDSA_QAX_MEM; break; diff --git a/components/hal/esp32h2/include/hal/gdma_ll.h b/components/hal/esp32h2/include/hal/gdma_ll.h index bdccf27035d..054bd741a4e 100644 --- a/components/hal/esp32h2/include/hal/gdma_ll.h +++ b/components/hal/esp32h2/include/hal/gdma_ll.h @@ -125,9 +125,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable) * @brief Get DMA RX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->in_intr[channel].st.val; + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } } /** @@ -349,9 +353,13 @@ static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->out_intr[channel].st.val; + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } } /** diff --git a/components/hal/esp32h2/include/hal/lp_aon_ll.h b/components/hal/esp32h2/include/hal/lp_aon_ll.h index 38492a17286..53e1f1fa5d8 100644 --- a/components/hal/esp32h2/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h2/include/hal/lp_aon_ll.h @@ -47,21 +47,14 @@ static inline void lp_aon_ll_ext1_clear_wakeup_status(void) */ static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) { - uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); - wakeup_sel_mask |= io_mask; - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask); - - uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv); - wakeup_level_mask |= io_mask & level_mask; - wakeup_level_mask &= ~(io_mask & ~level_mask); - - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask); } /** * @brief Clear all ext1 wakup-source setting */ -static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) { HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0); } diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h index 34e13c02b77..76fca20e788 100644 --- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h @@ -249,6 +249,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + // Not supported on this chip. +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32h2/include/hal/systimer_ll.h b/components/hal/esp32h2/include/hal/systimer_ll.h index 74dedc721fc..aa680917575 100644 --- a/components/hal/esp32h2/include/hal/systimer_ll.h +++ b/components/hal/esp32h2/include/hal/systimer_ll.h @@ -37,6 +37,35 @@ static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + PCR.systimer_conf.systimer_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + PCR.systimer_conf.systimer_rst_en = 1; + PCR.systimer_conf.systimer_rst_en = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /********************** ETM *****************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en) diff --git a/components/hal/esp32h2/include/hal/temperature_sensor_ll.h b/components/hal/esp32h2/include/hal/temperature_sensor_ll.h index 94c9d4b7412..9ecd97727e1 100644 --- a/components/hal/esp32h2/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32h2/include/hal/temperature_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -103,7 +103,7 @@ static inline void temperature_sensor_ll_set_range(uint32_t range) __attribute__((always_inline)) static inline uint32_t temperature_sensor_ll_get_raw_value(void) { - return APB_SARADC.saradc_apb_tsens_ctrl.saradc_tsens_out; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_out); } /** @@ -127,7 +127,7 @@ static inline uint32_t temperature_sensor_ll_get_offset(void) */ static inline uint32_t temperature_sensor_ll_get_clk_div(void) { - return APB_SARADC.saradc_apb_tsens_ctrl.saradc_tsens_clk_div; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_clk_div); } /** @@ -140,7 +140,7 @@ static inline uint32_t temperature_sensor_ll_get_clk_div(void) */ static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) { - APB_SARADC.saradc_apb_tsens_ctrl.saradc_tsens_clk_div = clk_div; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_clk_div, clk_div); } /** @@ -155,6 +155,17 @@ static inline void temperature_sensor_ll_wakeup_mode(uint8_t mode) APB_SARADC.tsens_wake.saradc_wakeup_mode = mode; } +/** + * @brief Get temperature sensor interrupt/wakeup in which reason + * + * @return uint8_t 0: temperature value lower than low threshold 1: otherwise, higher than high threshold. + */ +__attribute__((always_inline)) +static inline uint8_t temperature_sensor_ll_get_wakeup_reason(void) +{ + return APB_SARADC.tsens_wake.saradc_wakeup_over_upper_th; +} + /** * @brief Configure whether to enable temperature sensor wake up * @@ -172,7 +183,7 @@ static inline void temperature_sensor_ll_wakeup_enable(bool en) */ static inline void temperature_sensor_ll_set_th_low_val(uint8_t th_low) { - APB_SARADC.tsens_wake.saradc_wakeup_th_low = th_low; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_low, th_low); } /** @@ -182,7 +193,7 @@ static inline void temperature_sensor_ll_set_th_low_val(uint8_t th_low) */ static inline void temperature_sensor_ll_set_th_high_val(uint8_t th_high) { - APB_SARADC.tsens_wake.saradc_wakeup_th_high = th_high; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_high, th_high); } /** diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index eacd7f8edb6..64b678e31b4 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -154,19 +154,6 @@ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) while (hw->reg_update.reg_update); } -/** - * @brief Configure the UART core reset. - * - * @param hw Beginning address of the peripheral registers. - * @param core_rst_en True to enable the core reset, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) -{ - UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en); -} - /** * @brief Enable the UART clock. * diff --git a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h index 0ad39802139..3e3cf1cea2e 100644 --- a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h @@ -7,6 +7,9 @@ // The LL layer of the USB-serial-jtag controller #pragma once +#include +#include "esp_attr.h" +#include "soc/pcr_struct.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" @@ -158,8 +161,14 @@ static inline int usb_serial_jtag_ll_txfifo_writable(void) * @brief Flushes the TX buffer, that is, make it available for the * host to pick up. * - * @note When fifo is full (with 64 byte), HW will flush the buffer automatically. - * It won't be executed if there is nothing in the fifo. + * @note When fifo is full (with 64 byte), HW will flush the buffer automatically, + * if this function is called directly after, this effectively turns into a + * no-op. Because a 64-byte packet will be interpreted as a not-complete USB + * transaction, you need to transfer either more data or a zero-length packet + * for the data to actually end up at the program listening to the CDC-ACM + * serial port. To send a zero-length packet, call + * usb_serial_jtag_ll_txfifo_flush() again when + * usb_serial_jtag_ll_txfifo_writable() returns true. * * @return na */ @@ -168,6 +177,58 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void) USB_SERIAL_JTAG.ep1_conf.wr_done=1; } +/** + * @brief Disable usb serial jtag pad during light sleep to avoid current leakage + * + * @return Initial configuration of usb serial jtag pad enable before light sleep + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void) +{ + bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable; + + // Disable USB pad function + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + + return pad_enabled; +} + +/** + * @brief Enable the internal USJ PHY control to D+/D- pad + * + * @param enable_pad Enable the USJ PHY control to D+/D- pad + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad) +{ + USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad; +} + +/** + * @brief Enable the bus clock for USB Serial_JTAG module + * @param clk_en True if enable the clock of USB Serial_JTAG module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) +{ + PCR.usb_device_conf.usb_device_clk_en = clk_en; +} + +/** + * @brief Reset the usb serial jtag module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void) +{ + PCR.usb_device_conf.usb_device_rst_en = 1; + PCR.usb_device_conf.usb_device_rst_en = 0; +} + +/** + * Get the enable status USB Serial_JTAG module + * + * @return Return true if USB Serial_JTAG module is enabled + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void) +{ + return (PCR.usb_device_conf.usb_device_clk_en && !PCR.usb_device_conf.usb_device_rst_en); +} #ifdef __cplusplus } diff --git a/components/hal/esp32h2/modem_clock_hal.c b/components/hal/esp32h2/modem_clock_hal.c index b120b52a369..879e694d2a4 100644 --- a/components/hal/esp32h2/modem_clock_hal.c +++ b/components/hal/esp32h2/modem_clock_hal.c @@ -22,6 +22,7 @@ typedef enum { void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) { modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable); } void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable) @@ -29,7 +30,6 @@ void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_con modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable); modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable); modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable); } @@ -79,7 +79,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE); break; default: - break; + HAL_ASSERT(0); } } @@ -119,6 +119,6 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE); break; default: - break; + HAL_ASSERT(0); } } diff --git a/components/hal/esp32p4/include/hal/ahb_dma_ll.h b/components/hal/esp32p4/include/hal/ahb_dma_ll.h index 99fb54b310d..ffdb2d5190c 100644 --- a/components/hal/esp32p4/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32p4/include/hal/ahb_dma_ll.h @@ -62,9 +62,13 @@ static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev) * @brief Get DMA RX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel) +static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw) { - return dev->in_intr[channel].st.val; + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } } /** @@ -286,9 +290,13 @@ static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel) +static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw) { - return dev->out_intr[channel].st.val; + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } } /** @@ -552,7 +560,7 @@ static inline void ahb_dma_ll_tx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t c * @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel */ static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit, - uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) + uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) { dev->out_crc[channel].crc_en_addr.tx_crc_en_addr_chn = crc_bit; dev->out_crc[channel].crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask; @@ -613,7 +621,7 @@ static inline void ahb_dma_ll_rx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t c * @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel */ static inline void ahb_dma_ll_rx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit, - uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) + uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) { dev->in_crc[channel].crc_en_addr.rx_crc_en_addr_chn = crc_bit; dev->in_crc[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask; diff --git a/components/hal/esp32p4/include/hal/axi_dma_ll.h b/components/hal/esp32p4/include/hal/axi_dma_ll.h index cb191e44159..fe06f790d5e 100644 --- a/components/hal/esp32p4/include/hal/axi_dma_ll.h +++ b/components/hal/esp32p4/include/hal/axi_dma_ll.h @@ -64,9 +64,13 @@ static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev) * @brief Get DMA RX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel) +static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw) { - return dev->in[channel].intr.st.val; + if (raw) { + return dev->in[channel].intr.raw.val; + } else { + return dev->in[channel].intr.st.val; + } } /** @@ -260,9 +264,13 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel) +static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw) { - return dev->out[channel].intr.st.val; + if (raw) { + return dev->out[channel].intr.raw.val; + } else { + return dev->out[channel].intr.st.val; + } } /** @@ -498,7 +506,7 @@ static inline void axi_dma_ll_tx_crc_latch_config(axi_dma_dev_t *dev, uint32_t c * @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel */ static inline void axi_dma_ll_tx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit, - uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) + uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) { dev->out[channel].crc.tx_crc_en_addr.tx_crc_en_addr_chn = crc_bit; dev->out[channel].crc.tx_crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask; @@ -559,7 +567,7 @@ static inline void axi_dma_ll_rx_crc_latch_config(axi_dma_dev_t *dev, uint32_t c * @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel */ static inline void axi_dma_ll_rx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit, - uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) + uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask) { dev->in[channel].crc.rx_crc_en_addr.rx_crc_en_addr_chn = crc_bit; dev->in[channel].crc.rx_crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask; diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index b431dd9186e..5349e06eec6 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -21,29 +21,10 @@ extern "C" { static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) { switch (periph) { - case PERIPH_MSPI_FLASH_MODULE: - return HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN; - case PERIPH_MSPI_PSRAM_MODULE: - return HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN; case PERIPH_EMAC_MODULE: return LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN | LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN | LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN; - case PERIPH_MIPI_DSI_MODULE: - return HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN; - // IDF-6500 - case PERIPH_MIPI_CSI_MODULE: - return 0; - case PERIPH_I2C0_MODULE: - return HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN; - case PERIPH_I2C1_MODULE: - return HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN; - case PERIPH_LCD_MODULE: - return HP_SYS_CLKRST_REG_LCD_CLK_EN; case PERIPH_I3C_MODULE: return HP_SYS_CLKRST_REG_I3C_MST_CLK_EN; - case PERIPH_CAM_MODULE: - return HP_SYS_CLKRST_REG_CAM_CLK_EN; - case PERIPH_SYSTIMER_MODULE: - return HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN; case PERIPH_SARADC_MODULE: return HP_SYS_CLKRST_REG_ADC_CLK_EN; case PERIPH_PVT_MODULE: @@ -77,34 +58,16 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en switch (periph) { case PERIPH_PVT_MODULE: return HP_SYS_CLKRST_REG_RST_EN_PVT_TOP; - case PERIPH_MSPI_FLASH_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI; - case PERIPH_MSPI_PSRAM_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI; - case PERIPH_MIPI_DSI_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_DSI_BRG; - case PERIPH_MIPI_CSI_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_CSI_BRG; case PERIPH_ISP_MODULE: return HP_SYS_CLKRST_REG_RST_EN_ISP; - case PERIPH_JPEG_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_JPEG; case PERIPH_DMA2D_MODULE: return HP_SYS_CLKRST_REG_RST_EN_DMA2D; case PERIPH_PPA_MODULE: return HP_SYS_CLKRST_REG_RST_EN_PPA; - case PERIPH_SYSTIMER_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_STIMER; case PERIPH_UHCI_MODULE: return HP_SYS_CLKRST_REG_RST_EN_UHCI; case PERIPH_I3C_MODULE: return HP_SYS_CLKRST_REG_RST_EN_I3CMST | HP_SYS_CLKRST_REG_RST_EN_I3CSLV; - case PERIPH_I2C0_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_I2C0; - case PERIPH_I2C1_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_I2C1; - case PERIPH_LCD_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_LCDCAM; case PERIPH_SARADC_MODULE: return HP_SYS_CLKRST_REG_RST_EN_ADC; case PERIPH_AES_MODULE: @@ -152,21 +115,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) { switch (periph) { - case PERIPH_MSPI_FLASH_MODULE: - case PERIPH_MSPI_PSRAM_MODULE: - return HP_SYS_CLKRST_PERI_CLK_CTRL00_REG; - case PERIPH_MIPI_DSI_MODULE: - return HP_SYS_CLKRST_PERI_CLK_CTRL03_REG; - case PERIPH_I2C0_MODULE: - case PERIPH_I2C1_MODULE: - return HP_SYS_CLKRST_SOC_CLK_CTRL2_REG; - case PERIPH_LCD_MODULE: - return HP_SYS_CLKRST_PERI_CLK_CTRL110_REG; - return HP_SYS_CLKRST_PERI_CLK_CTRL116_REG; case PERIPH_I3C_MODULE: - case PERIPH_CAM_MODULE: - return HP_SYS_CLKRST_PERI_CLK_CTRL119_REG; - case PERIPH_SYSTIMER_MODULE: case PERIPH_SARADC_MODULE: return HP_SYS_CLKRST_PERI_CLK_CTRL22_REG; case PERIPH_PVT_MODULE: @@ -193,20 +142,12 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) { switch (periph) { case PERIPH_PVT_MODULE: - case PERIPH_MSPI_FLASH_MODULE: - case PERIPH_MSPI_PSRAM_MODULE: case PERIPH_ISP_MODULE: - case PERIPH_JPEG_MODULE: case PERIPH_DMA2D_MODULE: return HP_SYS_CLKRST_HP_RST_EN0_REG; case PERIPH_PPA_MODULE: - case PERIPH_SYSTIMER_MODULE: case PERIPH_UHCI_MODULE: case PERIPH_I3C_MODULE: - case PERIPH_I2C0_MODULE: - case PERIPH_I2C1_MODULE: - return HP_SYS_CLKRST_HP_RST_EN1_REG; - case PERIPH_CAM_MODULE: case PERIPH_SARADC_MODULE: case PERIPH_AES_MODULE: case PERIPH_DS_MODULE: diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index 29a38bdfc51..a607f723bf5 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -10,8 +10,9 @@ #include "soc/soc.h" #include "soc/clk_tree_defs.h" #include "soc/rtc.h" +#include "soc/pmu_reg.h" #include "hal/regi2c_ctrl.h" -#include "soc/regi2c_bbpll.h" +#include "soc/regi2c_mpll.h" #include "hal/assert.h" #include "hal/log.h" #include "esp32p4/rom/rtc.h" @@ -82,6 +83,22 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) } +/** + * @brief Power up MPLL circuit + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void) +{ + REG_SET_BIT(PMU_RF_PWC_REG, PMU_MSPI_PHY_XPD); +} + +/** + * @brief Power down MPLL circuit + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_disable(void) +{ + REG_CLR_BIT(PMU_RF_PWC_REG, PMU_MSPI_PHY_XPD); +} + /** * @brief Enable the 32kHz crystal oscillator * @@ -272,6 +289,25 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 } +/** + * @brief Set MPLL frequency from XTAL source (Analog part - through regi2c) + * + * @param mpll_freq_mhz MPLL frequency, in MHz + * @param xtal_freq_mhz XTAL frequency, in MHz + */ +static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_t mpll_freq_mhz, uint32_t xtal_freq_mhz) +{ + HAL_ASSERT(xtal_freq_mhz == RTC_XTAL_FREQ_40M); + + // MPLL_Freq = XTAL_Freq * (div + 1) / (ref_div + 1) + uint8_t ref_div = 1; + uint8_t div = mpll_freq_mhz / 20 - 1; + + uint32_t val = REGI2C_READ(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR); + val |= ((div << 3) | ref_div); + REGI2C_WRITE(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR, val); +} + /** * @brief Select the clock source for CPU_CLK (SOC Clock Root) * diff --git a/components/hal/esp32p4/include/hal/dw_gdma_ll.h b/components/hal/esp32p4/include/hal/dw_gdma_ll.h index b710340d1a2..11400503a6b 100644 --- a/components/hal/esp32p4/include/hal/dw_gdma_ll.h +++ b/components/hal/esp32p4/include/hal/dw_gdma_ll.h @@ -8,16 +8,26 @@ #include #include -#include "hal/assert.h" +#include "esp_assert.h" +#include "hal/misc.h" +#include "hal/dw_gdma_types.h" #include "soc/dw_gdma_struct.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/reg_base.h" #define DW_GDMA_LL_GET_HW() (&DW_GDMA) +#define DW_GDMA_LL_GROUPS 1 // there's one DW-GDMA instance connected to the AXI bus +#define DW_GDMA_LL_CHANNELS_PER_GROUP 4 // there are 4 independent channels in the DW-GDMA + #define DW_GDMA_LL_MASTER_PORT_MIPI_DSI 0 // DW_GDMA master 0 can access DSI bridge #define DW_GDMA_LL_MASTER_PORT_MIPI_CSI 0 // DW_GDMA master 0 can access CSI bridge #define DW_GDMA_LL_MASTER_PORT_MEMORY 1 // DW_GDMA master 1 can only access L2MEM & ROM & MSPI Flash/PSRAM +#define DW_GDMA_LL_MAX_OUTSTANDING_REQUESTS 16 // maximum number of outstanding requests + +#define DW_GDMA_LL_LINK_LIST_ALIGNMENT 64 // link list item must be aligned to 64 bytes + // Common event bitmap #define DW_GDMA_LL_COMMON_EVENT_SLVIF_DEC_ERR (0x1 << 0) #define DW_GDMA_LL_COMMON_EVENT_SLVIF_WR2RO_ERR (0x1 << 1) @@ -58,71 +68,13 @@ #define DW_GDMA_LL_CHANNEL_EVENT_DISABLED (0x1 << 30) #define DW_GDMA_LL_CHANNEL_EVENT_ABORTED (0x1 << 31) +#define DW_GDMA_LL_CHANNEL_EVENT_MASK(chan) (1 << (chan)) +#define DW_GDMA_LL_COMMON_EVENT_MASK (1 << 16) + #ifdef __cplusplus extern "C" { #endif -/** - * @brief DW_GDMA transfer width - */ -typedef enum { - DW_GDMA_LL_TRANS_WIDTH_8, /*!< Data transfer width: 8 bits */ - DW_GDMA_LL_TRANS_WIDTH_16, /*!< Data transfer width: 16 bits */ - DW_GDMA_LL_TRANS_WIDTH_32, /*!< Data transfer width: 32 bits */ - DW_GDMA_LL_TRANS_WIDTH_64, /*!< Data transfer width: 64 bits */ - DW_GDMA_LL_TRANS_WIDTH_128, /*!< Data transfer width: 128 bits */ - DW_GDMA_LL_TRANS_WIDTH_256, /*!< Data transfer width: 256 bits */ - DW_GDMA_LL_TRANS_WIDTH_512, /*!< Data transfer width: 512 bits */ -} dw_gdma_ll_transfer_width_t; - -/** - * @brief DW_GDMA burst items - */ -typedef enum { - DW_GDMA_LL_BURST_ITEMS_1, /*!< 1 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_4, /*!< 4 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_8, /*!< 8 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_16, /*!< 16 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_32, /*!< 32 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_64, /*!< 64 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_128, /*!< 128 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_256, /*!< 256 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_512, /*!< 512 data items in the burst transaction */ - DW_GDMA_LL_BURST_ITEMS_1024, /*!< 1024 data items in the burst transaction */ -} dw_gdma_ll_burst_items_t; - -/** - * @brief Multi block transfer type - */ -typedef enum { - DW_GDMA_LL_MULTI_BLOCK_CONTIGUOUS, /*!< Contiguous */ - DW_GDMA_LL_MULTI_BLOCK_RELOAD, /*!< Reload */ - DW_GDMA_LL_MULTI_BLOCK_SHADOW_REG, /*!< Shadow register */ - DW_GDMA_LL_MULTI_BLOCK_LINK_LIST, /*!< Link list */ -} dw_gdma_ll_multi_block_type_t; - -/** - * @brief Transfer type and flow control - */ -typedef enum { - DW_GDMA_LL_FLOW_M2M_DMAC, /*!< Flow: memory to memory, controller: DMA engine */ - DW_GDMA_LL_FLOW_M2P_DMAC, /*!< Flow: memory to peripheral, controller: DMA engine */ - DW_GDMA_LL_FLOW_P2M_DMAC, /*!< Flow: peripheral to memory, controller: DMA engine */ - DW_GDMA_LL_FLOW_P2P_DMAC, /*!< Flow: peripheral to peripheral, controller: DMA engine */ - DW_GDMA_LL_FLOW_P2M_SRC, /*!< Flow: peripheral to memory, controller: source peripheral */ - DW_GDMA_LL_FLOW_P2P_SRC, /*!< Flow: peripheral to peripheral, controller: source peripheral */ - DW_GDMA_LL_FLOW_M2P_DST, /*!< Flow: memory to peripheral, controller: destination peripheral */ - DW_GDMA_LL_FLOW_P2P_DST, /*!< Flow: peripheral to peripheral, controller: destination peripheral */ -} dw_gdma_ll_trans_flow_t; - -/** - * @brief Handshake interface - */ -typedef enum { - DW_GDMA_LL_HANDSHAKE_HW, /*!< Transaction requests are initiated by hardware */ - DW_GDMA_LL_HANDSHAKE_SW, /*!< Transaction requests are initiated by software */ -} dw_gdma_ll_handshake_interface_t; - /** * @brief Handshake number for different peripherals */ @@ -132,14 +84,6 @@ typedef enum { DW_GDMA_LL_HW_HANDSHAKE_PERIPH_ISP, /*!< Handshake peripheral is ISP */ } dw_gdma_ll_hw_handshake_periph_t; -/** - * @brief Channel lock level - */ -typedef enum { - DW_GDMA_LL_LOCK_LEVEL_FULL_TRANS, /*!< Lock over complete DMA transfer */ - DW_GDMA_LL_LOCK_LEVEL_BLOCK_TRANS, /*!< Lock over DMA block transfer */ -} dw_gdma_ll_lock_level_t; - /** * @brief Enable the bus clock for the DMA module */ @@ -205,14 +149,14 @@ static inline void dw_gdma_ll_enable_intr_global(dw_gdma_dev_t *dev, bool en) } /** - * @brief Check if the common register interrupt is active + * @brief Get the address of the interrupt status register * * @param dev Pointer to the DW_GDMA registers - * @return True: common register interrupt is active, False: common register interrupt is inactive + * @return Address of the interrupt status register */ -static inline bool dw_gdma_ll_is_common_intr_active(dw_gdma_dev_t *dev) +static inline volatile void *dw_gdma_ll_get_intr_status_reg(dw_gdma_dev_t *dev) { - return dev->int_st0.commonreg_intstat; + return &dev->int_st0; } /** @@ -312,7 +256,8 @@ static inline void dw_gdma_ll_channel_enable_intr_propagation(dw_gdma_dev_t *dev * @param channel Channel number * @return Mask of the channel interrupt status */ -static inline uint32_t dw_gdma_ll_channel_get_inr_status(dw_gdma_dev_t *dev, uint8_t channel) +__attribute__((always_inline)) +static inline uint32_t dw_gdma_ll_channel_get_intr_status(dw_gdma_dev_t *dev, uint8_t channel) { return dev->ch[channel].int_st0.val; } @@ -324,6 +269,7 @@ static inline uint32_t dw_gdma_ll_channel_get_inr_status(dw_gdma_dev_t *dev, uin * @param channel Channel number * @param mask Mask of the interrupt to clear */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_clear_intr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t mask) { dev->ch[channel].int_clr0.val = mask; @@ -380,18 +326,6 @@ static inline void dw_gdma_ll_channel_abort(dw_gdma_dev_t *dev, uint8_t channel) dev->chen1.val = 0x101 << channel; } -/** - * @brief Check if the DMA channel interrupt is active - * - * @param dev Pointer to the DW_GDMA registers - * @param channel Channel number - * @return True: channel interrupt is active, False: channel interrupt is inactive - */ -static inline bool dw_gdma_ll_channel_is_interrupt_active(dw_gdma_dev_t *dev, uint8_t channel) -{ - return dev->int_st0.val & (1 << channel); -} - /** * @brief Set the source address of the DMA transfer * @@ -399,6 +333,7 @@ static inline bool dw_gdma_ll_channel_is_interrupt_active(dw_gdma_dev_t *dev, ui * @param channel Channel number * @param src_addr Source address */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_set_src_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t src_addr) { dev->ch[channel].sar0.sar0 = src_addr; @@ -411,6 +346,7 @@ static inline void dw_gdma_ll_channel_set_src_addr(dw_gdma_dev_t *dev, uint8_t c * @param channel Channel number * @param dst_addr Destination address */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_set_dst_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t dst_addr) { dev->ch[channel].dar0.dar0 = dst_addr; @@ -419,71 +355,80 @@ static inline void dw_gdma_ll_channel_set_dst_addr(dw_gdma_dev_t *dev, uint8_t c /** * @brief Set the number of data to be transferred * - * @note data_transfer_width * item_amount determins the total bytes in one block transfer. + * @note "transfer width" * "transfer block size" = the total bytes in one block transfer * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param item_numbers Number of transfer items + * @param sz Number of transfer items */ -static inline void dw_gdma_ll_channel_set_trans_amount(dw_gdma_dev_t *dev, uint8_t channel, uint32_t item_numbers) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_trans_block_size(dw_gdma_dev_t *dev, uint8_t channel, uint32_t sz) { - dev->ch[channel].block_ts0.block_ts = item_numbers - 1; + dev->ch[channel].block_ts0.block_ts = sz - 1; } /** - * @brief Set the source master port - * - * @note The choice of master port depends on the location of the source data. + * @brief Set the source master port based on the memory address * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param port Source master port + * @param mem_addr Memory address */ -static inline void dw_gdma_ll_channel_set_src_master_port(dw_gdma_dev_t *dev, uint8_t channel, uint32_t port) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_src_master_port(dw_gdma_dev_t *dev, uint8_t channel, intptr_t mem_addr) { - dev->ch[channel].ctl0.sms = port; + if (mem_addr == MIPI_CSI_MEM_BASE) { + dev->ch[channel].ctl0.sms = DW_GDMA_LL_MASTER_PORT_MIPI_CSI; + } else { + dev->ch[channel].ctl0.sms = DW_GDMA_LL_MASTER_PORT_MEMORY; + } } /** - * @brief Set the destination master port - * - * @note The choice of master port depends on the location of the destination data. + * @brief Set the destination master port based on the memory address * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param port Destination master port + * @param mem_addr Memory address */ -static inline void dw_gdma_ll_channel_set_dst_master_port(dw_gdma_dev_t *dev, uint8_t channel, uint32_t port) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_dst_master_port(dw_gdma_dev_t *dev, uint8_t channel, intptr_t mem_addr) { - dev->ch[channel].ctl0.dms = port; + if (mem_addr == MIPI_DSI_MEM_BASE) { + dev->ch[channel].ctl0.dms = DW_GDMA_LL_MASTER_PORT_MIPI_DSI; + } else { + dev->ch[channel].ctl0.dms = DW_GDMA_LL_MASTER_PORT_MEMORY; + } } /** - * @brief Enable the source address increment + * @brief Enable the source address burst mode * * @note Increase the source address by the data width after each transfer * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param en True to enable, false to disable + * @param mode Address burst mode */ -static inline void dw_gdma_ll_channel_enable_src_addr_increment(dw_gdma_dev_t *dev, uint8_t channel, bool en) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_src_burst_mode(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_burst_mode_t mode) { - dev->ch[channel].ctl0.sinc = !en; + dev->ch[channel].ctl0.sinc = mode; } /** - * @brief Enable the destination address increment + * @brief Enable the destination address burst mode * * @note Increase the destination address by the data width after each transfer * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param en True to enable, false to disable + * @param mode Address burst mode */ -static inline void dw_gdma_ll_channel_enable_dst_addr_increment(dw_gdma_dev_t *dev, uint8_t channel, bool en) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_dst_burst_mode(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_burst_mode_t mode) { - dev->ch[channel].ctl0.dinc = !en; + dev->ch[channel].ctl0.dinc = mode; } /** @@ -493,7 +438,8 @@ static inline void dw_gdma_ll_channel_enable_dst_addr_increment(dw_gdma_dev_t *d * @param channel Channel number * @param width Transfer width */ -static inline void dw_gdma_ll_channel_set_src_trans_width(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_transfer_width_t width) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_src_trans_width(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_transfer_width_t width) { dev->ch[channel].ctl0.src_tr_width = width; } @@ -505,7 +451,8 @@ static inline void dw_gdma_ll_channel_set_src_trans_width(dw_gdma_dev_t *dev, ui * @param channel Channel number * @param width Transfer width */ -static inline void dw_gdma_ll_channel_set_dst_trans_width(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_transfer_width_t width) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_dst_trans_width(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_transfer_width_t width) { dev->ch[channel].ctl0.dst_tr_width = width; } @@ -517,7 +464,8 @@ static inline void dw_gdma_ll_channel_set_dst_trans_width(dw_gdma_dev_t *dev, ui * @param channel Channel number * @param items Number of data items */ -static inline void dw_gdma_ll_channel_set_src_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_burst_items_t items) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_src_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_burst_items_t items) { dev->ch[channel].ctl0.src_msize = items; } @@ -529,7 +477,8 @@ static inline void dw_gdma_ll_channel_set_src_burst_items(dw_gdma_dev_t *dev, ui * @param channel Channel number * @param items Number of data items */ -static inline void dw_gdma_ll_channel_set_dst_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_burst_items_t items) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_dst_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_burst_items_t items) { dev->ch[channel].ctl0.dst_msize = items; } @@ -543,10 +492,11 @@ static inline void dw_gdma_ll_channel_set_dst_burst_items(dw_gdma_dev_t *dev, ui * @param channel Channel number * @param len Burst length */ -static inline void dw_gdma_ll_channel_set_src_burst_len(dw_gdma_dev_t *dev, uint8_t channel, uint32_t len) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_src_burst_len(dw_gdma_dev_t *dev, uint8_t channel, uint8_t len) { - dev->ch[channel].ctl1.arlen_en = 1; - dev->ch[channel].ctl1.arlen = len - 1; + dev->ch[channel].ctl1.arlen_en = len > 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ch[channel].ctl1, arlen, len); } /** @@ -556,86 +506,144 @@ static inline void dw_gdma_ll_channel_set_src_burst_len(dw_gdma_dev_t *dev, uint * @param channel Channel number * @param len Burst length */ -static inline void dw_gdma_ll_channel_set_dst_burst_len(dw_gdma_dev_t *dev, uint8_t channel, uint32_t len) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_dst_burst_len(dw_gdma_dev_t *dev, uint8_t channel, uint8_t len) { - dev->ch[channel].ctl1.awlen_en = 1; - dev->ch[channel].ctl1.awlen = len - 1; + dev->ch[channel].ctl1.awlen_en = len > 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ch[channel].ctl1, awlen, len); } /** - * @brief Enable to generate an interrupt when the block transfer is done + * @brief Set block markers + * + * @note This is only valid for `DW_GDMA_BLOCK_TRANSFER_SHADOW` transfer type * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param en True to enable, false to disable + * @param en_intr True to generate an interrupt when the block transfer is done, false to disable + * @param is_last True to mark the block transfer as the last one + * @param is_valid True to mark the block transfer as valid */ -static inline void dw_gdma_ll_channel_enable_intr_block_trans_done(dw_gdma_dev_t *dev, uint8_t channel, bool en) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_set_block_markers(dw_gdma_dev_t *dev, uint8_t channel, bool en_intr, bool is_last, bool is_valid) { - dev->ch[channel].ctl1.ioc_blktfr = en; + dmac_chn_ctl1_reg_t ctrl1; + ctrl1.val = dev->ch[channel].ctl1.val; + ctrl1.shadowreg_or_lli_last = is_last; + ctrl1.ioc_blktfr = en_intr; + ctrl1.shadowreg_or_lli_valid = is_valid; + dev->ch[channel].ctl1.val = ctrl1.val; } /** - * @brief Set the multi block transfer type for the source peripheral + * @brief Whether to enable the status write back for the source peripheral * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param type Multi block transfer type + * @param en True to enable write back, false to disable */ -static inline void dw_gdma_ll_channel_set_src_multi_block_type(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_multi_block_type_t type) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_enable_src_periph_status_write_back(dw_gdma_dev_t *dev, uint8_t channel, bool en) { - dev->ch[channel].cfg0.src_multblk_type = type; + dev->ch[channel].ctl1.src_stat_en = en; } /** - * @brief Set the multi block transfer type for the destination peripheral + * @brief Whether to enable the status write back for the destination peripheral * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param type Multi block transfer type + * @param en True to enable write back, false to disable */ -static inline void dw_gdma_ll_channel_set_dst_multi_block_type(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_multi_block_type_t type) +__attribute__((always_inline)) +static inline void dw_gdma_ll_channel_enable_dst_periph_status_write_back(dw_gdma_dev_t *dev, uint8_t channel, bool en) { - dev->ch[channel].cfg0.dst_multblk_type = type; + dev->ch[channel].ctl1.dst_stat_en = en; } /** - * @brief Set the unique ID for the source peripheral - * - * @note This ID is related to Out-of-order transaction + * @brief Set the multi block transfer type for the source peripheral * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param uid Unique ID + * @param type Multi block transfer type */ -static inline void dw_gdma_ll_channel_set_src_uid(dw_gdma_dev_t *dev, uint8_t channel, uint32_t uid) +static inline void dw_gdma_ll_channel_set_src_multi_block_type(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_block_transfer_type_t type) { - dev->ch[channel].cfg0.rd_uid = uid; + dev->ch[channel].cfg0.src_multblk_type = type; } /** - * @brief Set the unique ID for the destination peripheral - * - * @note This ID is related to Out-of-order transaction + * @brief Set the multi block transfer type for the destination peripheral * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param uid Unique ID + * @param type Multi block transfer type */ -static inline void dw_gdma_ll_channel_set_dst_uid(dw_gdma_dev_t *dev, uint8_t channel, uint32_t uid) +static inline void dw_gdma_ll_channel_set_dst_multi_block_type(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_block_transfer_type_t type) { - dev->ch[channel].cfg0.wr_uid = uid; + dev->ch[channel].cfg0.dst_multblk_type = type; } /** - * @brief Set transfer type and flow control + * @brief Transfer type and flow control + */ +typedef enum { + DW_GDMA_LL_FLOW_M2M_DMAC, /*!< Flow: memory to memory, controller: DMA engine */ + DW_GDMA_LL_FLOW_M2P_DMAC, /*!< Flow: memory to peripheral, controller: DMA engine */ + DW_GDMA_LL_FLOW_P2M_DMAC, /*!< Flow: peripheral to memory, controller: DMA engine */ + DW_GDMA_LL_FLOW_P2P_DMAC, /*!< Flow: peripheral to peripheral, controller: DMA engine */ + DW_GDMA_LL_FLOW_P2M_SRC, /*!< Flow: peripheral to memory, controller: source peripheral */ + DW_GDMA_LL_FLOW_P2P_SRC, /*!< Flow: peripheral to peripheral, controller: source peripheral */ + DW_GDMA_LL_FLOW_M2P_DST, /*!< Flow: memory to peripheral, controller: destination peripheral */ + DW_GDMA_LL_FLOW_P2P_DST, /*!< Flow: peripheral to peripheral, controller: destination peripheral */ +} dw_gdma_ll_trans_flow_t; + +#define _MAKE_GDMA_FLOW_CTRL_CODE(src, dst, con) ((src) << 3 | (dst) << 2 | (con)) + +/** + * @brief Set transfer flow controller * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param flow Transfer flow control + * @param src_role Source target role + * @param dst_role Destination target role + * @param controller Flow controller */ -static inline void dw_gdma_ll_channel_set_trans_flow(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_trans_flow_t flow) +static inline void dw_gdma_ll_channel_set_trans_flow(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_role_t src_role, dw_gdma_role_t dst_role, dw_gdma_flow_controller_t controller) { - dev->ch[channel].cfg1.tt_fc = flow; + bool src_is_perih = (src_role != DW_GDMA_ROLE_MEM); + bool dst_is_perih = (dst_role != DW_GDMA_ROLE_MEM); + uint32_t fc_code = _MAKE_GDMA_FLOW_CTRL_CODE(src_is_perih, dst_is_perih, controller); + switch (fc_code) { + case _MAKE_GDMA_FLOW_CTRL_CODE(0, 0, DW_GDMA_FLOW_CTRL_SELF): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_M2M_DMAC; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(0, 1, DW_GDMA_FLOW_CTRL_SELF): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_M2P_DMAC; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(1, 0, DW_GDMA_FLOW_CTRL_SELF): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_P2M_DMAC; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(1, 1, DW_GDMA_FLOW_CTRL_SELF): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_P2P_DMAC; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(1, 0, DW_GDMA_FLOW_CTRL_SRC): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_P2M_SRC; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(1, 1, DW_GDMA_FLOW_CTRL_SRC): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_P2P_SRC; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(0, 1, DW_GDMA_FLOW_CTRL_DST): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_M2P_DST; + break; + case _MAKE_GDMA_FLOW_CTRL_CODE(1, 1, DW_GDMA_FLOW_CTRL_DST): + dev->ch[channel].cfg1.tt_fc = DW_GDMA_LL_FLOW_P2P_DST; + break; + default: + abort(); + break; + } } /** @@ -647,7 +655,7 @@ static inline void dw_gdma_ll_channel_set_trans_flow(dw_gdma_dev_t *dev, uint8_t * @param channel Channel number * @param hs Handshaking interface */ -static inline void dw_gdma_ll_channel_set_src_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_handshake_interface_t hs) +static inline void dw_gdma_ll_channel_set_src_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_handshake_type_t hs) { dev->ch[channel].cfg1.hs_sel_src = hs; } @@ -661,7 +669,7 @@ static inline void dw_gdma_ll_channel_set_src_handshake_interface(dw_gdma_dev_t * @param channel Channel number * @param hs Handshaking interface */ -static inline void dw_gdma_ll_channel_set_dst_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_handshake_interface_t hs) +static inline void dw_gdma_ll_channel_set_dst_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_handshake_type_t hs) { dev->ch[channel].cfg1.hs_sel_dst = hs; } @@ -675,9 +683,22 @@ static inline void dw_gdma_ll_channel_set_dst_handshake_interface(dw_gdma_dev_t * @param channel Channel number * @param periph Peripheral ID */ -static inline void dw_gdma_ll_channel_set_src_handshake_periph(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_hw_handshake_periph_t periph) +static inline void dw_gdma_ll_channel_set_src_handshake_periph(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_role_t periph) { - dev->ch[channel].cfg1.src_per = periph; + switch (periph) { + case DW_GDMA_ROLE_PERIPH_DSI: + dev->ch[channel].cfg1.src_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_DSI; + break; + case DW_GDMA_ROLE_PERIPH_CSI: + dev->ch[channel].cfg1.src_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_CSI; + break; + case DW_GDMA_ROLE_PERIPH_ISP: + dev->ch[channel].cfg1.src_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_ISP; + break; + default: + abort(); + break; + } } /** @@ -689,9 +710,22 @@ static inline void dw_gdma_ll_channel_set_src_handshake_periph(dw_gdma_dev_t *de * @param channel Channel number * @param periph Peripheral ID */ -static inline void dw_gdma_ll_channel_set_dst_handshake_periph(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_hw_handshake_periph_t periph) +static inline void dw_gdma_ll_channel_set_dst_handshake_periph(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_role_t periph) { - dev->ch[channel].cfg1.dst_per = periph; + switch (periph) { + case DW_GDMA_ROLE_PERIPH_DSI: + dev->ch[channel].cfg1.dst_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_DSI; + break; + case DW_GDMA_ROLE_PERIPH_CSI: + dev->ch[channel].cfg1.dst_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_CSI; + break; + case DW_GDMA_ROLE_PERIPH_ISP: + dev->ch[channel].cfg1.dst_per = DW_GDMA_LL_HW_HANDSHAKE_PERIPH_ISP; + break; + default: + abort(); + break; + } } /** @@ -715,7 +749,7 @@ static inline void dw_gdma_ll_channel_set_priority(dw_gdma_dev_t *dev, uint8_t c * @param channel Channel number * @param lock_level At which level the lock is applied */ -static inline void dw_gdma_ll_channel_lock(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_lock_level_t lock_level) +static inline void dw_gdma_ll_channel_lock(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_lock_level_t lock_level) { dev->ch[channel].cfg1.lock_ch_l = lock_level; dev->ch[channel].cfg1.lock_ch = 1; @@ -764,11 +798,27 @@ static inline void dw_gdma_ll_channel_set_dst_outstanding_limit(dw_gdma_dev_t *d * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param addr Address of the first link list item, it must be aligned 64 + * @param addr Address of the first link list item, it must be aligned 64 bytes */ static inline void dw_gdma_ll_channel_set_link_list_head_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr) { dev->ch[channel].llp0.loc0 = addr >> 6; + dev->ch[channel].llp1.val = 0; +} + +/** + * @brief Get the current link list item address + * + * @note When the DMA detects an invalid block, this function can tell which link list item is invalid + * + * @param dev Pointer to the DW_GDMA registers + * @param channel Channel number + * @return Address of the current link list item + */ +__attribute__((always_inline)) +static inline intptr_t dw_gdma_ll_channel_get_current_link_list_item_addr(dw_gdma_dev_t *dev, uint8_t channel) +{ + return (intptr_t)dev->ch[channel].llp0.loc0 << 6; } /** @@ -784,20 +834,34 @@ static inline void dw_gdma_ll_channel_set_link_list_master_port(dw_gdma_dev_t *d } /** - * @brief Get the total number of data that transferred for the previous block transfer. + * @brief Get the total number of data that got transferred * - * @note for normal transfer, this value is the same as the value of `dw_gdma_ll_channel_set_trans_amount` + * @note for normal transfer, this value is the same as the value of `dw_gdma_ll_channel_set_trans_block_size` * @note if any error occurs, the transfer might be terminated early, this function returns actual data transferred without error. * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @return Total number of data that transferred for the previous block transfer + * @return Total number of data that got transferred */ static inline uint32_t dw_gdma_ll_channel_get_trans_amount(dw_gdma_dev_t *dev, uint8_t channel) { return dev->ch[channel].status0.cmpltd_blk_tfr_size; } +/** + * @brief Get the total number of data left in the channel FIFO after completing the current block transfer + * + * @note for normal transfer completion without errors, this function should always return 0 + * + * @param dev Pointer to the DW_GDMA registers + * @param channel Channel number + * @return Total number of data left in the channel FIFO + */ +static inline uint32_t dw_gdma_ll_channel_get_fifo_remain(dw_gdma_dev_t *dev, uint8_t channel) +{ + return dev->ch[channel].status1.data_left_in_fifo; +} + /** * @brief Resume the multi-block transfer * @@ -806,6 +870,7 @@ static inline uint32_t dw_gdma_ll_channel_get_trans_amount(dw_gdma_dev_t *dev, u * @param dev Pointer to the DW_GDMA registers * @param channel Channel number */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_resume_multi_block_transfer(dw_gdma_dev_t *dev, uint8_t channel) { // this register is write-only, we can't do read-modify-write @@ -813,29 +878,367 @@ static inline void dw_gdma_ll_channel_resume_multi_block_transfer(dw_gdma_dev_t } /** - * @brief Set the address to fetch the source status of the DMA channel + * @brief Set the address where to fetch the status of the source peripheral + * + * @note Status of the source peripheral can be read by `dw_gdma_ll_channel_get_src_periph_status` * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param addr Address to fetch the source status of the DMA channel + * @param addr Address to fetch the status */ -static inline void dw_gdma_ll_channel_set_src_status_fetch_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr) +static inline void dw_gdma_ll_channel_set_src_periph_status_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr) { dev->ch[channel].sstatar0.sstatar0 = addr; } /** - * @brief Set the address to fetch the destination status of the DMA channel + * @brief Set the address where to fetch the status of the destination peripheral + * + * @note Status of the destination peripheral can be read by `dw_gdma_ll_channel_get_dst_periph_status` * * @param dev Pointer to the DW_GDMA registers * @param channel Channel number - * @param addr Address to fetch the destination status of the DMA channel + * @param addr Address to fetch the status */ -static inline void dw_gdma_ll_channel_set_dst_status_fetch_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr) +static inline void dw_gdma_ll_channel_set_dst_periph_status_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr) { dev->ch[channel].dstatar0.dstatar0 = addr; } +/** + * @brief Get the status of the source peripheral + * + * @param dev Pointer to the DW_GDMA registers + * @param channel Channel number + * @return Status of the source peripheral + */ +static inline uint32_t dw_gdma_ll_channel_get_src_periph_status(dw_gdma_dev_t *dev, uint8_t channel) +{ + return dev->ch[channel].sstat0.val; +} + +/** + * @brief Get the status of the destination peripheral + * + * @param dev Pointer to the DW_GDMA registers + * @param channel Channel number + * @return Status of the destination peripheral + */ +static inline uint32_t dw_gdma_ll_channel_get_dst_periph_status(dw_gdma_dev_t *dev, uint8_t channel) +{ + return dev->ch[channel].dstat0.val; +} + +/** + * @brief Type of DW-DMA link list item + */ +typedef struct dw_gdma_link_list_item_t { + dmac_chn_sar0_reg_t sar_lo; /*!< Source address low 32 bits */ + dmac_chn_sar1_reg_t sar_hi; /*!< Source address high 32 bits */ + dmac_chn_dar0_reg_t dar_lo; /*!< Destination address low 32 bits */ + dmac_chn_dar1_reg_t dar_hi; /*!< Destination address high 32 bits */ + dmac_chn_block_ts0_reg_t block_ts_lo; /*!< Block transfer size, specify the number of data items to be transferred in a block */ + uint32_t reserved_14; + dmac_chn_llp0_reg_t llp_lo; /*!< Pointer to the next link list item low 32 bits. Set to zero to indicate the end of the list */ + dmac_chn_llp1_reg_t llp_hi; /*!< Pointer to the next link list item high 32 bits. Set to zero to indicate the end of the list */ + dmac_chn_ctl0_reg_t ctrl_lo; /*!< Control word low 32 bits */ + dmac_chn_ctl1_reg_t ctrl_hi; /*!< Control word high 32 bits */ + dmac_chn_sstat0_reg_t sstat; /*!< Status of the source peripheral */ + dmac_chn_dstat0_reg_t dstat; /*!< Status of the destination peripheral */ + dmac_chn_status0_reg_t status_lo; /*!< Channel status low 32 bits */ + dmac_chn_status1_reg_t status_hi; /*!< Channel status high 32 bits */ + uint32_t reserved_38; + uint32_t reserved_3c; +} dw_gdma_link_list_item_t __attribute__((aligned(DW_GDMA_LL_LINK_LIST_ALIGNMENT))); + +ESP_STATIC_ASSERT(sizeof(dw_gdma_link_list_item_t) == DW_GDMA_LL_LINK_LIST_ALIGNMENT, "Invalid size of dw_gdma_link_list_item_t structure"); + +/** + * @brief Set the transfer width of the source data + * + * @param lli Link list item + * @param width Transfer width + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_src_trans_width(dw_gdma_link_list_item_t *lli, dw_gdma_transfer_width_t width) +{ + lli->ctrl_lo.src_tr_width = width; +} + +/** + * @brief Set the transfer width of the destination data + * + * @param lli Link list item + * @param width Transfer width + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_dst_trans_width(dw_gdma_link_list_item_t *lli, dw_gdma_transfer_width_t width) +{ + lli->ctrl_lo.dst_tr_width = width; +} + +/** + * @brief Set the source master port based on the memory address + * + * @param lli Link list item + * @param mem_addr Memory address + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_src_master_port(dw_gdma_link_list_item_t *lli, intptr_t mem_addr) +{ + if (mem_addr == MIPI_CSI_MEM_BASE) { + lli->ctrl_lo.sms = DW_GDMA_LL_MASTER_PORT_MIPI_CSI; + } else { + lli->ctrl_lo.sms = DW_GDMA_LL_MASTER_PORT_MEMORY; + } +} + +/** + * @brief Set the destination master port based on the memory address + * + * @param lli Link list item + * @param mem_addr Memory address + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_dst_master_port(dw_gdma_link_list_item_t *lli, intptr_t mem_addr) +{ + if (mem_addr == MIPI_DSI_MEM_BASE) { + lli->ctrl_lo.dms = DW_GDMA_LL_MASTER_PORT_MIPI_DSI; + } else { + lli->ctrl_lo.dms = DW_GDMA_LL_MASTER_PORT_MEMORY; + } +} + +/** + * @brief Set the source address of the DMA transfer + * + * @param lli Link list item + * @param src_addr Source address + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_src_addr(dw_gdma_link_list_item_t *lli, uint32_t src_addr) +{ + lli->sar_lo.sar0 = src_addr; +} + +/** + * @brief Set the destination address of the DMA transfer + * + * @param lli Link list item + * @param dst_addr Destination address + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_dst_addr(dw_gdma_link_list_item_t *lli, uint32_t dst_addr) +{ + lli->dar_lo.dar0 = dst_addr; +} + +/** + * @brief Set the number of data to be transferred + * + * @note "transfer width" * "transfer size" = the total bytes in one block transfer + * + * @param lli Link list item + * @param sz Number of transfer items + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_trans_block_size(dw_gdma_link_list_item_t *lli, uint32_t sz) +{ + lli->block_ts_lo.block_ts = sz - 1; +} + +/** + * @brief Enable the source address burst mode + * + * @note Increase the source address by the data width after each transfer + * + * @param lli Link list item + * @param mode Address burst mode + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_src_burst_mode(dw_gdma_link_list_item_t *lli, dw_gdma_burst_mode_t mode) +{ + lli->ctrl_lo.sinc = mode; +} + +/** + * @brief Enable the destination address burst mode + * + * @note Increase the destination address by the data width after each transfer + * + * @param lli Link list item + * @param mode Address burst mode + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_dst_burst_mode(dw_gdma_link_list_item_t *lli, dw_gdma_burst_mode_t mode) +{ + lli->ctrl_lo.dinc = mode; +} + +/** + * @brief Set the number of data items that can be transferred in a single burst transaction for the source master port + * + * @param lli Link list item + * @param items Number of data items + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_src_burst_items(dw_gdma_link_list_item_t *lli, dw_gdma_burst_items_t items) +{ + lli->ctrl_lo.src_msize = items; +} + +/** + * @brief Set the number of data items that can be transferred in a single burst transaction for the destination master port + * + * @param lli Link list item + * @param items Number of data items + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_dst_burst_items(dw_gdma_link_list_item_t *lli, dw_gdma_burst_items_t items) +{ + lli->ctrl_lo.dst_msize = items; +} + +/** + * @brief Set the source burst length + * + * @note This controls how many times the DMA controller will ask for data from the source device in a single burst transaction. + * + * @param lli Link list item + * @param len Burst length + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_src_burst_len(dw_gdma_link_list_item_t *lli, uint8_t len) +{ + lli->ctrl_hi.arlen_en = len > 0; + lli->ctrl_hi.arlen = len; +} + +/** + * @brief Set the destination burst length + * + * @param lli Link list item + * @param len Burst length + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_dst_burst_len(dw_gdma_link_list_item_t *lli, uint8_t len) +{ + lli->ctrl_hi.awlen_en = len > 0; + lli->ctrl_hi.awlen = len; +} + +/** + * @brief Set block markers + * + * @note This is only valid for `DW_GDMA_BLOCK_TRANSFER_SHADOW` transfer type + * + * @param lli Link list item + * @param en_intr True to generate an interrupt when the block transfer is done, false to disable + * @param is_last True to mark the block transfer as the last one + * @param is_valid True to mark the block transfer as valid + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_set_block_markers(dw_gdma_link_list_item_t *lli, bool en_intr, bool is_last, bool is_valid) +{ + lli->ctrl_hi.ioc_blktfr = en_intr; + lli->ctrl_hi.shadowreg_or_lli_last = is_last; + lli->ctrl_hi.shadowreg_or_lli_valid = is_valid; +} + +/** + * @brief Whether to enable the status write back for the source peripheral + * + * @param lli Link list item + * @param en True to enable write back, false to disable + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_enable_src_periph_status_write_back(dw_gdma_link_list_item_t *lli, bool en) +{ + lli->ctrl_hi.src_stat_en = en; +} + +/** + * @brief Whether to enable the status write back for the destination peripheral + * + * @param lli Link list item + * @param en True to enable write back, false to disable + */ +__attribute__((always_inline)) +static inline void dw_gdma_ll_lli_enable_dst_periph_status_write_back(dw_gdma_link_list_item_t *lli, bool en) +{ + lli->ctrl_hi.dst_stat_en = en; +} + +/** + * @brief Get the status of the source peripheral + * + * @param lli Link list item + * @return Status of the source peripheral + */ +static inline uint32_t dw_gdma_ll_lli_get_src_periph_status(dw_gdma_link_list_item_t *lli) +{ + return lli->sstat.val; +} + +/** + * @brief Get the status of the destination peripheral + * + * @param lli Link list item + * @return Status of the destination peripheral + */ +static inline uint32_t dw_gdma_ll_lli_get_dst_periph_status(dw_gdma_link_list_item_t *lli) +{ + return lli->dstat.val; +} + +/** + * @brief Set the master port of the memory which holds the link list + * + * @param lli Link list item + * @param port Master port + */ +static inline void dw_gdma_ll_lli_set_link_list_master_port(dw_gdma_link_list_item_t *lli, uint32_t port) +{ + lli->llp_lo.lms = port; +} + +/** + * @brief Set the address of the next link list item + * + * @param lli Link list item + * @param addr Address of the next link list item, it must be aligned 64 bytes + */ +static inline void dw_gdma_ll_lli_set_next_item_addr(dw_gdma_link_list_item_t *lli, uint32_t addr) +{ + lli->llp_lo.loc0 = addr >> 6; + lli->llp_hi.val = 0; +} + +/** + * @brief Get the total number of data that got transferred + * + * @note for normal transfer, this value is the same as the value of `dw_gdma_ll_lli_set_trans_block_size` + * @note if any error occurs, the transfer might be terminated early, this function returns actual data transferred without error. + * + * @param lli Link list item + * @return Total number of data that got transferred + */ +static inline uint32_t dw_gdma_ll_lli_get_trans_amount(dw_gdma_link_list_item_t *lli) +{ + return lli->status_lo.cmpltd_blk_tfr_size; +} + +/** + * @brief Get the total number of data left in the channel FIFO after completing the current block transfer + * + * @param lli Link list item + * @return Total number of data left in the channel FIFO + */ +static inline uint32_t dw_gdma_ll_lli_get_fifo_remain(dw_gdma_link_list_item_t *lli) +{ + return lli->status_hi.data_left_in_fifo; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/ecdsa_ll.h b/components/hal/esp32p4/include/hal/ecdsa_ll.h index 1d52bd4f9f5..b30b078b410 100644 --- a/components/hal/esp32p4/include/hal/ecdsa_ll.h +++ b/components/hal/esp32p4/include/hal/ecdsa_ll.h @@ -23,7 +23,6 @@ typedef enum { ECDSA_PARAM_R, ECDSA_PARAM_S, ECDSA_PARAM_Z, - ECDSA_PARAM_K, ECDSA_PARAM_QAX, ECDSA_PARAM_QAY } ecdsa_ll_param_t; @@ -199,26 +198,6 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve) } } -/** - * @brief Set the source of `K` - * - * @param mode Mode of K generation - */ -static inline void ecdsa_ll_set_k_mode(ecdsa_k_mode_t mode) -{ - switch (mode) { - case ECDSA_K_USE_TRNG: - REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_K); - break; - case ECDSA_K_USER_PROVIDED: - REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_K); - break; - default: - HAL_ASSERT(false && "Unsupported curve"); - break; - } -} - /** * @brief Set the source of `Z` (SHA message) * @@ -344,7 +323,6 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b case ECDSA_PARAM_Z: reg = ECDSA_Z_MEM; break; - case ECDSA_PARAM_K: case ECDSA_PARAM_QAX: reg = ECDSA_QAX_MEM; break; @@ -382,7 +360,6 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin case ECDSA_PARAM_Z: reg = ECDSA_Z_MEM; break; - case ECDSA_PARAM_K: case ECDSA_PARAM_QAX: reg = ECDSA_QAX_MEM; break; diff --git a/components/hal/esp32p4/include/hal/etm_ll.h b/components/hal/esp32p4/include/hal/etm_ll.h index fa1dcae8c16..6904d170ac7 100644 --- a/components/hal/esp32p4/include/hal/etm_ll.h +++ b/components/hal/esp32p4/include/hal/etm_ll.h @@ -121,6 +121,24 @@ static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uin hw->channel[chan].task_id.task_id = task; } +/** + * @brief Get the flag that marks whether LP CPU is awakened by ETM + * + * @return Return true if lpcore is woken up by soc etm flag + */ +static inline bool etm_ll_is_lpcore_wakeup_triggered(void) +{ + return SOC_ETM.task_st5.ulp_task_wakeup_cpu_st; +} + +/** + * @brief Clear the flag that marks whether LP CPU is awakened by ETM + */ +static inline void etm_ll_clear_lpcore_wakeup_status(void) +{ + SOC_ETM.task_st5_clr.ulp_task_wakeup_cpu_st_clr = 1; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h index 9d719c87109..f7573cf1aca 100644 --- a/components/hal/esp32p4/include/hal/gdma_ll.h +++ b/components/hal/esp32p4/include/hal/gdma_ll.h @@ -13,6 +13,7 @@ #include #include #include "soc/hp_sys_clkrst_struct.h" +#include "soc/soc_etm_source.h" #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] @@ -44,6 +45,46 @@ #define GDMA_LL_AHB_MAX_CRC_BIT_WIDTH 32 // Max CRC bit width supported by AHB GDMA #define GDMA_LL_AXI_MAX_CRC_BIT_WIDTH 16 // Max CRC bit width supported by AXI GDMA +#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[2][GDMA_ETM_EVENT_MAX]){ \ + { \ + [GDMA_ETM_EVENT_EOF] = PDMA_AHB_EVT_OUT_EOF_CH0 + (chan), \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = PDMA_AXI_EVT_OUT_EOF_CH0 + (chan), \ + }, \ + }[group][event] + +#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[2][GDMA_ETM_EVENT_MAX]){ \ + { \ + [GDMA_ETM_EVENT_EOF] = PDMA_AHB_EVT_IN_SUC_EOF_CH0 + (chan), \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = PDMA_AXI_EVT_IN_SUC_EOF_CH0 + (chan), \ + }, \ + }[group][event] + +#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[2][GDMA_ETM_TASK_MAX]){ \ + { \ + [GDMA_ETM_TASK_START] = PDMA_AHB_TASK_OUT_START_CH0 + (chan), \ + }, \ + { \ + [GDMA_ETM_TASK_START] = PDMA_AXI_TASK_OUT_START_CH0 + (chan), \ + }, \ + }[group][task] + +#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[2][GDMA_ETM_TASK_MAX]){ \ + { \ + [GDMA_ETM_TASK_START] = PDMA_AHB_TASK_IN_START_CH0 + (chan), \ + }, \ + { \ + [GDMA_ETM_TASK_START] = PDMA_AXI_TASK_IN_START_CH0 + (chan), \ + }, \ + }[group][task] + #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index 986edcdacc7..f92a1b6b990 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -39,9 +39,9 @@ extern "C" { #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) #define GPIO_LL_INTR0_ENA (BIT(0)) -// #define GPIO_LL_INTR1_ENA (BIT(1)) // TODO: IDF-7995 -// #define GPIO_LL_INTR2_ENA (BIT(2)) -// #define GPIO_LL_INTR3_ENA (BIT(3)) +#define GPIO_LL_INTR1_ENA (BIT(1)) +#define GPIO_LL_INTR2_ENA (BIT(3)) +#define GPIO_LL_INTR3_ENA (BIT(4)) /** * @brief Get the configuration for an IO @@ -289,7 +289,7 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t // GPIO 16-47 HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low |= (bit_mask >> SOC_RTCIO_PIN_COUNT); } else { - // GPIO 48-56 + // GPIO 48-54 HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } @@ -312,7 +312,7 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t // GPIO 16-47 HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low &= ~(bit_mask >> SOC_RTCIO_PIN_COUNT); } else { - // GPIO 48-56 + // GPIO 48-54 HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } @@ -486,7 +486,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 16-47 HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low |= (bit_mask >> SOC_RTCIO_PIN_COUNT); } else { - // GPIO 48-56 + // GPIO 48-54 HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } @@ -511,7 +511,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 16-47 HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low &= ~(bit_mask >> SOC_RTCIO_PIN_COUNT); } else { - // GPIO 48-56 + // GPIO 48-54 HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } @@ -541,7 +541,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 16-47 return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT)); } else { - // GPIO 48-56 + // GPIO 48-54 return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT))); } } diff --git a/components/hal/esp32p4/include/hal/jpeg_ll.h b/components/hal/esp32p4/include/hal/jpeg_ll.h new file mode 100644 index 00000000000..2126d5db72e --- /dev/null +++ b/components/hal/esp32p4/include/hal/jpeg_ll.h @@ -0,0 +1,634 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/jpeg_struct.h" +#include "hal/jpeg_types.h" +#include "soc/hp_sys_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define JPEG_LL_GET_HW(num) (&JPEG) + +typedef enum { + JPEG_LL_DONE = (1 << 0), + JPEG_LL_DCT_DONE = (1 << 11), +} jpeg_ll_codec_intr_t; + +typedef enum { + JPEG_LL_INTR_CID_ERR = (1 << 2), + JPEG_LL_INTR_C_DHT_DC_ID = (1 << 3), + JPEG_LL_INTR_C_DHT_AC_ID = (1 << 4), + JPEG_LL_INTR_C_DQT_ID = (1 << 5), + JPEG_LL_INTR_RST_UXP_ERR = (1 << 6), + JPEG_LL_INTR_RST_CHECK_NON_ERR = (1 << 7), + JPEG_LL_INTR_RST_CHECK_POS_ERR = (1 << 8), + JPEG_LL_INTR_OUT_EOF = (1 << 9), + JPEG_LL_INTR_SCAN_CHECK_NONE = (1 << 13), + JPEG_LL_INTR_SCAN_POS_ERR = (1 << 14), + JPEG_LL_INTR_UXP_DET = (1 << 15), + JPEG_LL_INTR_DE_FRAME_EOF_ERR = (1 << 18), + JPEG_LL_INTR_DE_FRAME_EOF_LACK = (1 << 19), + JPEG_LL_INTR_SOS_UNMATCH_ERR = (1 << 20), + JPEG_LL_INTR_MARKER_ERR_FST = (1 << 21), + JPEG_LL_INTR_MARKER_ERR_OTHER = (1 << 22), + JPEG_LL_INTR_UNDET = (1 << 23), + JPEG_LL_INTR_DECODE_TIMEOUT = (1 << 24), +} jpeg_ll_decoder_intr_t; + +#define JPEG_LL_DECODER_EVENT_INTR (JPEG_LL_INTR_CID_ERR | \ + JPEG_LL_INTR_C_DHT_DC_ID | \ + JPEG_LL_INTR_C_DHT_AC_ID | \ + JPEG_LL_INTR_C_DQT_ID | \ + JPEG_LL_INTR_RST_UXP_ERR | \ + JPEG_LL_INTR_RST_CHECK_NON_ERR | \ + JPEG_LL_INTR_RST_CHECK_POS_ERR | \ + JPEG_LL_INTR_OUT_EOF | \ + JPEG_LL_INTR_SCAN_CHECK_NONE | \ + JPEG_LL_INTR_SCAN_POS_ERR | \ + JPEG_LL_INTR_UXP_DET | \ + JPEG_LL_INTR_DE_FRAME_EOF_ERR | \ + JPEG_LL_INTR_DE_FRAME_EOF_LACK | \ + JPEG_LL_INTR_SOS_UNMATCH_ERR | \ + JPEG_LL_INTR_MARKER_ERR_FST | \ + JPEG_LL_INTR_MARKER_ERR_OTHER | \ + JPEG_LL_INTR_UNDET | \ + JPEG_LL_INTR_DECODE_TIMEOUT) + + +typedef enum { + JPEG_LL_RLE_PARALLEL_ERR = (1 << 1), + JPEG_LL_BS_LAST_BLOCK_EOF = (1 << 12), + JPEG_LL_EN_FRAME_EOF_ERR = (1 << 16), + JPEG_LL_EN_FRAME_EOF_LACK = (1 << 16), +} jpeg_ll_encoder_intr_t; + +/** + * @brief Enable the hardware clock for JPEG module + * + * @param enable True to enable; false to disable + */ +static inline void jpeg_ll_enable_bus_clock(bool enable) +{ + HP_SYS_CLKRST.soc_clk_ctrl1.reg_jpeg_sys_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define jpeg_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; jpeg_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the JPEG module + */ +static inline void jpeg_ll_reset_module_register(void) +{ + HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_jpeg = 1; + HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_jpeg = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define jpeg_ll_reset_module_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; jpeg_ll_reset_module_register(__VA_ARGS__) + +/** + * @brief Write the numbers of 1~n codewords length sum of ac0 table and write the minimum codeword of code length + * for 1~16 of ac0 table + * + * @param hw Pointer to JPEG hardware + * @param huffman_bits_table Pointer to huffman table + * @param minimum_code_table Pointer to minimum huffman code table + */ +static inline void jpeg_ll_dht_ac0_write_codeword(jpeg_dev_t *hw, uint8_t *huffman_bits_table, uint32_t *minimum_code_table) +{ + uint32_t element_number = 0; + for (int idx = 0; idx < JEPG_HUFFMAN_BITS_LEN_TABLE_LEN; idx++) { + element_number += (uint32_t)huffman_bits_table[idx]; + hw->dht_totlen_ac0.dht_totlen_ac0 = element_number; + hw->dht_codemin_ac0.dht_codemin_ac0 = minimum_code_table[idx]; + } +} + +/** + * @brief Write the symbols corresponding to the decoded codeword for AC0 huffman table in FIFO mode + * + * @param hw Pointer to JPEG hardware. + * @param huffman_value_table Pointer to huffman value table. + */ +static inline void jpeg_ll_dht_ac0_write_value(jpeg_dev_t *hw, uint8_t *huffman_value_table) +{ + for (int idx = 0; idx < JPEG_HUFFMAN_AC_VALUE_TABLE_LEN; idx++) { + hw->dht_val_ac0.dht_val_ac0 = (uint32_t)huffman_value_table[idx]; + } +} + +/** + * @brief Write the numbers of 1~n codewords length sum of ac1 table and write the minimum codeword of code length + * for 1~16 of ac1 table + * + * @param hw Pointer to JPEG hardware + * @param huffman_bits_table Pointer to huffman table + * @param minimum_code_table Pointer to minimum huffman code table + */ +static inline void jpeg_ll_dht_ac1_write_codeword(jpeg_dev_t *hw, uint8_t *huffman_bits_table, uint32_t *minimum_code_table) +{ + uint32_t element_number = 0; + for (int idx = 0; idx < JEPG_HUFFMAN_BITS_LEN_TABLE_LEN; idx++) { + element_number += (uint32_t)huffman_bits_table[idx]; + hw->dht_totlen_ac1.dht_totlen_ac1 = element_number; + hw->dht_codemin_ac1.dht_codemin_ac1 = minimum_code_table[idx]; + } +} + +/** + * @brief Write the symbols corresponding to the decoded codeword for AC1 huffman table in FIFO mode + * + * @param hw Pointer to JPEG hardware. + * @param huffman_value_table Pointer to huffman value table. + */ +static inline void jpeg_ll_dht_ac1_write_value(jpeg_dev_t *hw, uint8_t *huffman_value_table) +{ + for (int idx = 0; idx < JPEG_HUFFMAN_AC_VALUE_TABLE_LEN; idx++) { + hw->dht_val_ac1.dht_val_ac1 = (uint32_t)huffman_value_table[idx]; + } +} + +/** + * @brief Write the numbers of 1~n codewords length sum of dc0 table and write the minimum codeword of code length + * for 1~16 of dc0 table + * + * @param hw Pointer to JPEG hardware + * @param huffman_bits_table Pointer to huffman table + * @param minimum_code_table Pointer to minimum huffman code table + */ +static inline void jpeg_ll_dht_dc0_write_codeword(jpeg_dev_t *hw, uint8_t *huffman_bits_table, uint32_t *minimum_code_table) +{ + uint32_t element_number = 0; + for (int idx = 0; idx < JEPG_HUFFMAN_BITS_LEN_TABLE_LEN; idx++) { + element_number += (uint32_t)huffman_bits_table[idx]; + hw->dht_totlen_dc0.dht_totlen_dc0 = element_number; + hw->dht_codemin_dc0.dht_codemin_dc0 = minimum_code_table[idx]; + } +} + +/** + * @brief Write the symbols corresponding to the decoded codeword for DC0 huffman table in FIFO mode + * + * @param hw Pointer to JPEG hardware + * @param huffman_value_table Pointer to huffman value table. + */ +static inline void jpeg_ll_dht_dc0_write_value(jpeg_dev_t *hw, uint8_t *huffman_value_table) +{ + for (int idx = 0; idx < JPEG_HUFFMAN_DC_VALUE_TABLE_LEN; idx++) { + hw->dht_val_dc0.dht_val_dc0 = (uint32_t)huffman_value_table[idx]; + } +} + +/** + * @brief Write the numbers of 1~n codewords length sum of dc1 table and write the minimum codeword of code length + * for 1~16 of dc1 table + * + * @param hw Pointer to JPEG hardware + * @param huffman_bits_table Pointer to huffman table + * @param minimum_code_table Pointer to minimum huffman code table + */ +static inline void jpeg_ll_dht_dc1_write_codeword(jpeg_dev_t *hw, uint8_t *huffman_bits_table, uint32_t *minimum_code_table) +{ + uint32_t element_number = 0; + for (int idx = 0; idx < JEPG_HUFFMAN_BITS_LEN_TABLE_LEN; idx++) { + element_number += (uint32_t)huffman_bits_table[idx]; + hw->dht_totlen_dc1.dht_totlen_dc1 = element_number; + hw->dht_codemin_dc1.dht_codemin_dc1 = minimum_code_table[idx]; + } +} + +/** + * @brief Write the symbols corresponding to the decoded codeword for DC1 huffman table in FIFO mode + * + * @param hw Pointer to JPEG hardware + * @param huffman_value_table Pointer to huffman value table. + */ +static inline void jpeg_ll_dht_dc1_write_value(jpeg_dev_t *hw, uint8_t *huffman_value_table) +{ + for (int idx = 0; idx < JPEG_HUFFMAN_DC_VALUE_TABLE_LEN; idx++) { + hw->dht_val_dc1.dht_val_dc1 = (uint32_t)huffman_value_table[idx]; + } +} + +/** + * @brief Configures the quantization coefficient table precision for the encoder + * + * @param hw Pointer to JPEG hardware + * @param qnr_presition precision of quantization coefficient table + */ +static inline void jpeg_ll_set_qnr_presition(jpeg_dev_t *hw, uint8_t qnr_presition) +{ + hw->config.qnr_presition = qnr_presition; +} + +/** + * @brief Configures it to write quantization coefficient for table0 in FIFO mode + * + * @param hw Pointer to JPEG hardware + * @param quantization_table Pointer to quantization table. + */ +static inline void jpeg_ll_write_quantization_coefficient_t0(jpeg_dev_t *hw, uint32_t *quantization_table) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->dqt_info, t0_dqt_info, 0); + for (int q = 0; q < JPEG_QUANTIZATION_TABLE_LEN; q++) { + hw->t0qnr.t0_qnr_val = quantization_table[q]; + } +} + +/** + * @brief Configures it to write quantization coefficient for table1 in FIFO mode + * + * @param hw Pointer to JPEG hardware + * @param quantization_table Pointer to quantization table. + */ +static inline void jpeg_ll_write_quantization_coefficient_t1(jpeg_dev_t *hw, uint32_t *quantization_table) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->dqt_info, t1_dqt_info, 1); + for (int q = 0; q < JPEG_QUANTIZATION_TABLE_LEN; q++) { + hw->t1qnr.chrominance_qnr_val = quantization_table[q]; + } +} + +/** + * @brief Configures it to write quantization coefficient for table2 in FIFO mode + * + * @param hw Pointer to JPEG hardware + * @param quantization_table Pointer to quantization table. + */ +static inline void jpeg_ll_write_quantization_coefficient_t2(jpeg_dev_t *hw, uint32_t *quantization_table) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->dqt_info, t2_dqt_info, 2); + for (int q = 0; q < JPEG_QUANTIZATION_TABLE_LEN; q++) { + hw->t2qnr.t2_qnr_val = quantization_table[q]; + } +} + +/** + * @brief Configures it to write quantization coefficient for table3 in FIFO mode + * + * @param hw Pointer to JPEG hardware + * @param quantization_table Pointer to quantization table. + */ +static inline void jpeg_ll_write_quantization_coefficient_t3(jpeg_dev_t *hw, uint32_t *quantization_table) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->dqt_info, t3_dqt_info, 3); + for (int q = 0; q < JPEG_QUANTIZATION_TABLE_LEN; q++) { + hw->t3qnr.t3_qnr_val = quantization_table[q]; + } +} + +/** + * @brief Configures image’s height + * + * @param hw Pointer to JPEG hardware + * @param height height of image. + */ +static inline void jpeg_ll_set_picture_height(jpeg_dev_t *hw, uint32_t height) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->pic_size, va, height); +} + +/** + * @brief Configures image’s width + * + * @param hw Pointer to JPEG hardware + * @param height width of image. + */ +static inline void jpeg_ll_set_picture_width(jpeg_dev_t *hw, uint32_t width) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->pic_size, ha, width); +} + +/** + * @brief Configure component0. + * + * @param hw Pointer to JPEG hardware + * @param identifier ID of component 0. + * @param horizontal_factor Configures the horizontal sampling factor of component 0. + * @param vertical_factor Configures the vertical sampling factor of component 0. + * @param qun_table_id Configures the selected quantization coefficient table ID for component 0. + */ +static inline void jpeg_ll_set_frame_info_component0(jpeg_dev_t *hw, uint8_t identifier, uint8_t horizontal_factor, uint8_t vertical_factor, uint8_t qun_table_id) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c0, c0_id, identifier); + hw->c0.c0_x_factor = horizontal_factor; + hw->c0.c0_y_factor = vertical_factor; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c0, c0_dqt_tbl_sel, qun_table_id); +} + +/** + * @brief Configure component1. + * + * @param hw Pointer to JPEG hardware + * @param identifier ID of component 1. + * @param horizontal_factor Configures the horizontal sampling factor of component 1. + * @param vertical_factor Configures the vertical sampling factor of component 1. + * @param qun_table_id Configures the selected quantization coefficient table ID for component 1. + */ +static inline void jpeg_ll_set_frame_info_component1(jpeg_dev_t *hw, uint8_t identifier, uint8_t horizontal_factor, uint8_t vertical_factor, uint8_t qun_table_id) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c1, c1_id, identifier); + hw->c1.c1_x_factor = horizontal_factor; + hw->c1.c1_y_factor = vertical_factor; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c1, c1_dqt_tbl_sel, qun_table_id); +} + +/** + * @brief Configure component2. + * + * @param hw Pointer to JPEG hardware + * @param identifier ID of component 2. + * @param horizontal_factor Configures the horizontal sampling factor of component 2. + * @param vertical_factor Configures the vertical sampling factor of component 2. + * @param qun_table_id Configures the selected quantization coefficient table ID for component 2. + */ +static inline void jpeg_ll_set_frame_info_component2(jpeg_dev_t *hw, uint8_t identifier, uint8_t horizontal_factor, uint8_t vertical_factor, uint8_t qun_table_id) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c2, c2_id, identifier); + hw->c2.c2_x_factor = horizontal_factor; + hw->c2.c2_y_factor = vertical_factor; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c2, c2_dqt_tbl_sel, qun_table_id); +} + +/** + * @brief Configure component3. + * + * @param hw Pointer to JPEG hardware + * @param identifier ID of component 3. + * @param horizontal_factor Configures the horizontal sampling factor of component 3. + * @param vertical_factor Configures the vertical sampling factor of component 3. + * @param qun_table_id Configures the selected quantization coefficient table ID for component 3. + */ +static inline void jpeg_ll_set_frame_info_component3(jpeg_dev_t *hw, uint8_t identifier, uint8_t horizontal_factor, uint8_t vertical_factor, uint8_t qun_table_id) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c3, c3_id, identifier); + hw->c3.c3_x_factor = horizontal_factor; + hw->c3.c3_y_factor = vertical_factor; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->c3, c3_dqt_tbl_sel, qun_table_id); +} + +/** + * @brief Get factor from component0 + * + * @param hw Pointer to JPEG hardware + * @param component_factor Pointer to component factor + */ +static inline void jpeg_ll_get_component0_factor(jpeg_dev_t *hw, jpeg_component_factor_t *component_factor) +{ + component_factor->horizontal = hw->c0.c0_x_factor; + component_factor->vertical = hw->c0.c0_y_factor; +} + +/** + * @brief Get factor from component1 + * + * @param hw Pointer to JPEG hardware + * @param component_factor Pointer to component factor + */ +static inline void jpeg_ll_get_component1_factor(jpeg_dev_t *hw, jpeg_component_factor_t *component_factor) +{ + component_factor->horizontal = hw->c1.c1_x_factor; + component_factor->vertical = hw->c1.c1_y_factor; +} + +/** + * @brief Configures whether or not to start compressing a new image + * + * @param hw Pointer to JPEG hardware + */ +static inline void jpeg_ll_process_start(jpeg_dev_t *hw) +{ + hw->config.jpeg_start = 1; +} + +/** + * @brief Configures whether or not pause the JPEG codec. + * + * @param hw Pointer to JPEG hardware + * @param en true: pause the jpeg codec, false: resume. + */ +static inline void jpeg_ll_codec_pause(jpeg_dev_t *hw, bool en) +{ + hw->config.pause_en = en; +} + + +/** + * @brief Apply soft reset, this will reset the hardware fsm and fifo. + * + * @param hw Pointer to JPEG hardware. + */ +static inline void jpeg_ll_soft_rst(jpeg_dev_t *hw) +{ + hw->config.soft_rst = 1; + hw->config.soft_rst = 0; +} + +/** + * @brief Configures if the JPEG codec is working as an encoder or a decoder. + * + * @param hw Pointer to JPEG hardware. + * @param mode Refer to `jpeg_codec_mode_t` + */ +static inline void jpeg_ll_set_codec_mode(jpeg_dev_t *hw, jpeg_codec_mode_t mode) +{ + uint8_t mode_val = 0; + switch (mode) { + case JPEG_CODEC_ENCODER: + mode_val = 0; + break; + case JPEG_CODEC_DECODER: + mode_val = 1; + break; + default: + HAL_ASSERT(false); + break; + } + hw->config.mode = mode_val; +} + +/** + * @brief Configures whether or not to enable FIFO mode of configuring quantization coefficient tables. + * + * @param hw Pointer to JPEG hardware. + * @param mode 0: Use non-fifo mode. 1: Use fifo mode. + */ +static inline void jpeg_ll_set_access_qnr_ram_mode(jpeg_dev_t *hw, uint8_t mode) +{ + hw->config.qnr_fifo_en = mode; +} + +/** + * @brief Configures the number of color components in image when decoding + * + * @param hw Pointer to JPEG hardware. + * @param component_num Number of color components + */ +static inline void jpeg_ll_set_decode_component_num(jpeg_dev_t *hw, uint8_t component_num) +{ + // ESP32P4 only support to decode color component not larger than 4 + HAL_ASSERT(component_num <= 3); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->decode_conf, component_num, component_num); +} + +/** + * @brief Configures the format of the image to be compressed + * + * @param hw Pointer to JPEG hardware. + * @param mode_sel Select sample mode, refer to `jpeg_sample_mode_t`. + */ +static inline void jpeg_ll_sample_mode_select(jpeg_dev_t *hw, jpeg_sample_mode_t mode_sel) +{ + uint8_t sample_sel = 0; + switch (mode_sel) { + case JPEG_SAMPLE_MODE_YUV444: + sample_sel = 0; + break; + case JPEG_SAMPLE_MODE_YUV422: + sample_sel = 1; + break; + case JPEG_SAMPLE_MODE_YUV420: + sample_sel = 0; + break; + default: + HAL_ASSERT(false); + break; + } + hw->config.sample_sel = sample_sel; +} + +/** + * @brief Configure whether or not to reverse the original image's pixel order. + * + * @param hw Pointer to JPEG hardware. + * @param reverse_en 0: not revert; 1: revert. + */ +static inline void jpeg_ll_pixel_reverse(jpeg_dev_t *hw, bool reverse_en) +{ + hw->config.pixel_rev = reverse_en; +} + +/** + * @brief Configures whether or not to add EOI of “0xffd9” at the end of bitstream + * + * @param hw Pointer to JPEG hardware. + * @param tailer_en 1: Add `0xffd9` at the end ot bitstream. + */ +static inline void jpeg_ll_add_tail(jpeg_dev_t *hw, bool tailer_en) +{ + hw->config.tailer_en = tailer_en; +} + +/** + * @brief Configures whether or not to add “00” after “ff” + * + * @param hw Pointer to JPEG hardware. + * @param ff_check_en 0: not add `00` after `ff`; 1: Add. + */ +static inline void jpeg_ll_enable_ff_check(jpeg_dev_t *hw, bool ff_check_en) +{ + hw->config.ff_check_en = ff_check_en; +} + +/** + * @brief Configures the luma quantization table ID for the encoder + * + * @param hw Pointer to JPEG hardware. + * @param lqnr_id ID of luma quantization table. + */ +static inline void jpeg_ll_luminance_qnr_table_id(jpeg_dev_t *hw, uint8_t lqnr_id) +{ + hw->config.lqnr_tbl_sel = lqnr_id; +} + +/** + * @brief Configures the chroma quantization table ID for the encoder. + * + * @param hw Pointer to JPEG hardware. + * @param cqnr_id ID of chroma quantization table. + */ +static inline void jpeg_ll_chrominance_qnr_table_id(jpeg_dev_t *hw, uint8_t cqnr_id) +{ + hw->config.cqnr_tbl_sel = cqnr_id; +} + +/** + * @brief Configures the restart interval in DRI segment when decoding + * + * @param hw Pointer to JPEG hardware. + * @param restart_interval value of restart interval. + */ +static inline void jpeg_ll_set_restart_interval(jpeg_dev_t *hw, uint16_t restart_interval) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->decode_conf, restart_interval, restart_interval); +} + +/** + * @brief Get JPEG interrupt status register address + * + * @param hw Pointer to JPEG hardware. + * @return address of interrupt status register. + */ +static inline volatile void *jpeg_ll_get_interrupt_status_reg(jpeg_dev_t *hw) +{ + return &hw->int_st; +} + +/** + * @brief Enable JPEG interrupt + * + * @param hw Pointer to JPEG hardware. + */ +static inline void jpeg_ll_enable_intr_mask(jpeg_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val |= mask; +} + +/** + * @brief Clear JPEG interrupt + * + * @param hw Pointer to JPEG hardware. + */ +static inline void jpeg_ll_clear_intr_mask(jpeg_dev_t *hw, uint32_t mask) +{ + hw->int_clr.val = mask; +} + +/** + * @brief Disable JPEG interrupt + * + * @param hw Pointer to JPEG hardware. + */ +static inline void jpeg_ll_disable_intr_mask(jpeg_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val &= (~mask); +} + +/** + * @brief Get JPEG interrupt status + * + * @param hw Pointer to JPEG hardware. + */ +static inline uint32_t jpeg_ll_get_intr_status(jpeg_dev_t *hw) +{ + return hw->int_st.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/lcd_ll.h b/components/hal/esp32p4/include/hal/lcd_ll.h new file mode 100644 index 00000000000..58bfeb34ece --- /dev/null +++ b/components/hal/esp32p4/include/hal/lcd_ll.h @@ -0,0 +1,769 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* For NULL declaration */ +#include +#include +#include "hal/misc.h" +#include "soc/lcd_cam_reg.h" +#include "soc/lcd_cam_struct.h" +#include "hal/assert.h" +#include "hal/lcd_types.h" +#include "soc/hp_sys_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LCD_LL_GET_HW(id) (((id) == 0) ? (&LCD_CAM) : NULL) + +// Interrupt event, bit mask +#define LCD_LL_EVENT_VSYNC_END (1 << 0) +#define LCD_LL_EVENT_TRANS_DONE (1 << 1) + +#define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width +#define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width +#define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width + +/** + * @brief LCD data byte swizzle mode + */ +typedef enum { + LCD_LL_SWIZZLE_AB2BA, /*!< AB -> BA */ + LCD_LL_SWIZZLE_ABC2ACB, /*!< ABC -> ACB */ + LCD_LL_SWIZZLE_ABC2BAC, /*!< ABC -> BAC */ + LCD_LL_SWIZZLE_ABC2BCA, /*!< ABC -> BCA */ + LCD_LL_SWIZZLE_ABC2CAB, /*!< ABC -> CAB */ + LCD_LL_SWIZZLE_ABC2CBA, /*!< ABC -> CBA */ +} lcd_ll_swizzle_mode_t; + +/** + * @brief Enable the bus clock for LCD module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void lcd_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.soc_clk_ctrl3.reg_lcdcam_apb_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define lcd_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the LCD module + * + * @param group_id Group ID + */ +static inline void lcd_ll_reset_register(int group_id) +{ + (void)group_id; + HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_lcdcam = 1; + HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_lcdcam = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define lcd_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_reset_register(__VA_ARGS__) + +/** + * @brief Enable clock gating + * + * @param dev LCD register base address + * @param en True to enable, False to disable + */ +static inline void lcd_ll_enable_clock(lcd_cam_dev_t *dev, bool en) +{ + HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_en = en; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define lcd_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lcd_ll_enable_clock(__VA_ARGS__) + +/** + * @brief Select clock source for LCD peripheral + * + * @param dev LCD register base address + * @param src Clock source + */ +static inline void lcd_ll_select_clk_src(lcd_cam_dev_t *dev, lcd_clock_source_t src) +{ + switch (src) { + case LCD_CLK_SRC_XTAL: + HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 0; + break; + case LCD_CLK_SRC_PLL160M: + HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 1; + break; + case LCD_CLK_SRC_APLL: + HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 2; + break; + default: + // disable the clock + HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 3; + break; + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define lcd_ll_select_clk_src(...) (void)__DECLARE_RCC_ATOMIC_ENV; lcd_ll_select_clk_src(__VA_ARGS__) + +/** + * @brief Set clock coefficient of LCD peripheral + * + * @param dev LCD register base address + * @param div_num Integer part of the divider + * @param div_a denominator of the divider + * @param div_b numerator of the divider + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_group_clock_coeff(lcd_cam_dev_t *dev, int div_num, int div_a, int div_b) +{ + // lcd_clk = module_clock_src / (div_num + div_b / div_a) + HAL_ASSERT(div_num >= 2 && div_num <= LCD_LL_CLK_FRAC_DIV_N_MAX); + // dic_num == 0 means LCD_LL_CLK_FRAC_DIV_N_MAX divider in hardware + if (div_num >= LCD_LL_CLK_FRAC_DIV_N_MAX) { + div_num = 0; + } + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl110, reg_lcd_clk_div_num, div_num); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl110, reg_lcd_clk_div_denominator, div_a); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl110, reg_lcd_clk_div_numerator, div_b); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define lcd_ll_set_group_clock_coeff(...) (void)__DECLARE_RCC_ATOMIC_ENV; lcd_ll_set_group_clock_coeff(__VA_ARGS__) + +/** + * @brief Set the PCLK clock level state when there's no transaction undergoing + * + * @param dev LCD register base address + * @param level 1 is high level, 0 is low level + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_clock_idle_level(lcd_cam_dev_t *dev, bool level) +{ + dev->lcd_clock.lcd_ck_idle_edge = level; +} + +/** + * @brief Set the PCLK sample edge + * + * @param dev LCD register base address + * @param active_on_neg True: sample on negedge, False: sample on posedge + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_pixel_clock_edge(lcd_cam_dev_t *dev, bool active_on_neg) +{ + dev->lcd_clock.lcd_ck_out_edge = active_on_neg; +} + +/** + * @brief Set PCLK prescale + * + * @param dev LCD register base address + * @param prescale Prescale value, PCLK = LCD_CLK / prescale + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_pixel_clock_prescale(lcd_cam_dev_t *dev, uint32_t prescale) +{ + HAL_ASSERT(prescale <= LCD_LL_PCLK_DIV_MAX); + // Formula: pixel_clk = lcd_clk / (1 + clkcnt_n) + // clkcnt_n can't be zero + uint32_t scale = 1; + if (prescale == 1) { + dev->lcd_clock.lcd_clk_equ_sysclk = 1; + } else { + dev->lcd_clock.lcd_clk_equ_sysclk = 0; + scale = prescale - 1; + } + dev->lcd_clock.lcd_clkcnt_n = scale; +} + +/** + * @brief Enable YUV-RGB converter + * + * @param dev LCD register base address + * @param en True to enable converter, False to disable converter + */ +static inline void lcd_ll_enable_rgb_yuv_convert(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_rgb_yuv.lcd_conv_enable = en; +} + +/** + * @brief Set convert data line width + * + * @param dev LCD register base address + * @param width data line width + */ +static inline void lcd_ll_set_convert_data_width(lcd_cam_dev_t *dev, uint32_t width) +{ + HAL_ASSERT(width == 8 || width == 16); + dev->lcd_rgb_yuv.lcd_conv_mode_8bits_on = (width == 8) ? 1 : 0; +} + +/** + * @brief Set the color range of input data + * + * @param dev LCD register base address + * @param range Color range + */ +static inline void lcd_ll_set_input_color_range(lcd_cam_dev_t *dev, lcd_color_range_t range) +{ + if (range == LCD_COLOR_RANGE_LIMIT) { + dev->lcd_rgb_yuv.lcd_conv_data_in_mode = 0; + } else if (range == LCD_COLOR_RANGE_FULL) { + dev->lcd_rgb_yuv.lcd_conv_data_in_mode = 1; + } +} + +/** + * @brief Set the color range of output data + * + * @param dev LCD register base address + * @param range Color range + */ +static inline void lcd_ll_set_output_color_range(lcd_cam_dev_t *dev, lcd_color_range_t range) +{ + if (range == LCD_COLOR_RANGE_LIMIT) { + dev->lcd_rgb_yuv.lcd_conv_data_out_mode = 0; + } else if (range == LCD_COLOR_RANGE_FULL) { + dev->lcd_rgb_yuv.lcd_conv_data_out_mode = 1; + } +} + +/** + * @brief Set YUV conversion standard + * + * @param dev LCD register base address + * @param std YUV conversion standard + */ +static inline void lcd_ll_set_yuv_convert_std(lcd_cam_dev_t *dev, lcd_yuv_conv_std_t std) +{ + if (std == LCD_YUV_CONV_STD_BT601) { + dev->lcd_rgb_yuv.lcd_conv_protocol_mode = 0; + } else if (std == LCD_YUV_CONV_STD_BT709) { + dev->lcd_rgb_yuv.lcd_conv_protocol_mode = 1; + } +} + +/** + * @brief Set the converter mode: RGB565 to YUV + * + * @param dev LCD register base address + * @param yuv_sample YUV sample mode + */ +static inline void lcd_ll_set_convert_mode_rgb_to_yuv(lcd_cam_dev_t *dev, lcd_yuv_sample_t yuv_sample) +{ + dev->lcd_rgb_yuv.lcd_conv_trans_mode = 1; + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 3; + switch (yuv_sample) { + case LCD_YUV_SAMPLE_422: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 0; + break; + case LCD_YUV_SAMPLE_420: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 1; + break; + case LCD_YUV_SAMPLE_411: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 2; + break; + default: + abort(); + } +} + +/** + * @brief Set the converter mode: YUV to RGB565 + * + * @param dev LCD register base address + * @param yuv_sample YUV sample mode + */ +static inline void lcd_ll_set_convert_mode_yuv_to_rgb(lcd_cam_dev_t *dev, lcd_yuv_sample_t yuv_sample) +{ + dev->lcd_rgb_yuv.lcd_conv_trans_mode = 0; + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 3; + switch (yuv_sample) { + case LCD_YUV_SAMPLE_422: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 0; + break; + case LCD_YUV_SAMPLE_420: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 1; + break; + case LCD_YUV_SAMPLE_411: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 2; + break; + default: + abort(); + } +} + +/** + * @brief Set the converter mode: YUV to YUV + * + * @param dev LCD register base address + * @param src_sample Source YUV sample mode + * @param dst_sample Destination YUV sample mode + */ +static inline void lcd_ll_set_convert_mode_yuv_to_yuv(lcd_cam_dev_t *dev, lcd_yuv_sample_t src_sample, lcd_yuv_sample_t dst_sample) +{ + HAL_ASSERT(src_sample != dst_sample); + dev->lcd_rgb_yuv.lcd_conv_trans_mode = 1; + switch (src_sample) { + case LCD_YUV_SAMPLE_422: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 0; + break; + case LCD_YUV_SAMPLE_420: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 1; + break; + case LCD_YUV_SAMPLE_411: + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = 2; + break; + default: + abort(); + } + switch (dst_sample) { + case LCD_YUV_SAMPLE_422: + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 0; + break; + case LCD_YUV_SAMPLE_420: + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 1; + break; + case LCD_YUV_SAMPLE_411: + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 2; + break; + default: + abort(); + } +} + +/** + * @brief Set clock cycles of each transaction phases + * + * @param dev LCD register base address + * @param cmd_cycles Clock cycles of CMD phase + * @param dummy_cycles Clock cycles of DUMMY phase + * @param data_cycles Clock cycles of DATA phase + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycles, uint32_t dummy_cycles, uint32_t data_cycles) +{ + HAL_ASSERT(cmd_cycles <= 2); + dev->lcd_user.lcd_cmd = (cmd_cycles > 0); + dev->lcd_user.lcd_dummy = (dummy_cycles > 0); + dev->lcd_user.lcd_dout = (data_cycles > 0); + dev->lcd_user.lcd_cmd_2_cycle_en = cmd_cycles > 1; + dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1; + dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1; +} + +/** + * @brief Set clock cycles of blank phases + * + * @param dev LCD register base address + * @param fk_cycles Clock cycles of front blank + * @param bk_cycles Clock cycles of back blank + */ +static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev, uint32_t fk_cycles, uint32_t bk_cycles) +{ + dev->lcd_misc.lcd_bk_en = (fk_cycles || bk_cycles); + dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1; + dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1; +} + +/** + * @brief Set data read stride, i.e., number of bytes the LCD reads from the DMA in each step + * + * @param dev LCD register base address + * @param stride data stride size, in bits + */ +static inline void lcd_ll_set_dma_read_stride(lcd_cam_dev_t *dev, uint32_t stride) +{ + switch (stride) { + case 8: + dev->lcd_user.lcd_byte_mode = 0; + break; + case 16: + dev->lcd_user.lcd_byte_mode = 1; + break; + case 24: + dev->lcd_user.lcd_byte_mode = 2; + break; + case 32: + dev->lcd_user.lcd_byte_mode = 3; + break; + default: + abort(); + } +} + +/** + * @brief Set the wire width of LCD output + * + * @param dev LCD register base address + * @param width LCD output wire width + */ +static inline void lcd_ll_set_data_wire_width(lcd_cam_dev_t *dev, uint32_t width) +{ + switch (width) { + case 8: + dev->lcd_misc.lcd_wire_mode = 0; + break; + case 16: + dev->lcd_misc.lcd_wire_mode = 1; + break; + case 24: + dev->lcd_misc.lcd_wire_mode = 2; + break; + default: + abort(); + } +} + +/** + * @brief Whether to continue the data phase when the DMA has content to send + * + * @param dev LCD register base address + * @param en True: The number of data cycles will be controller by DMA buffer size, instead of lcd_dout_cyclelen + * False: The number of data cycles will be controlled by lcd_dout_cyclelen + */ +static inline void lcd_ll_enable_output_always_on(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_user.lcd_always_out_en = en; +} + +/** + * @brief Start the LCD transaction + * + * @param dev LCD register base address + */ +__attribute__((always_inline)) +static inline void lcd_ll_start(lcd_cam_dev_t *dev) +{ + dev->lcd_user.lcd_update_reg = 1; // update parameters before start transaction + dev->lcd_user.lcd_start = 1; +} + +/** + * @brief Stop the LCD transaction + * + * @param dev LCD register base address + */ +__attribute__((always_inline)) +static inline void lcd_ll_stop(lcd_cam_dev_t *dev) +{ + dev->lcd_user.lcd_start = 0; + dev->lcd_user.lcd_update_reg = 1; // self clear +} + +/** + * @brief Reset LCD TX controller and RGB/YUV converter + * + * @param dev LCD register base address + */ +static inline void lcd_ll_reset(lcd_cam_dev_t *dev) +{ + dev->lcd_user.lcd_reset = 1; // self clear +} + +/** + * @brief Whether to reverse the data bit order + * + * @note It acts before the YUV-RGB converter + * + * @param dev LCD register base address + * @param en True to reverse, False to not reverse + */ +__attribute__((always_inline)) +static inline void lcd_ll_reverse_dma_data_bit_order(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_user.lcd_bit_order = en; +} + +/** + * @brief Whether to reverse the output data bit order + * + * @note It acts after the YUV-RGB converter + * + * @param dev LCD register base address + * @param en True to reverse, False to not reverse + */ +static inline void lcd_ll_reverse_wire_bit_order(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_user.lcd_dout_bit_order = en; +} + +/** + * @brief Whether to swap adjacent two bytes + * + * @note This acts before the YUV-RGB converter, mainly to change the data endian. + * {B1,B0},{B3,B2} => {B0,B1}{B2,B3} + * + * @param dev LCD register base address + * @param en True to swap the byte order, False to not swap + */ +__attribute__((always_inline)) +static inline void lcd_ll_swap_dma_data_byte_order(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_user.lcd_byte_order = en; +} + +/** + * @brief Enable the byte swizzle + * + * @note The swizzle module acts after the YUV-RGB converter, used to reorder the data bytes before the data output line + * + * @param dev LCD register base address + * @param en True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void lcd_ll_enable_swizzle(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_user.lcd_dout_byte_swizzle_enable = en; +} + +/** + * @brief Set data byte swizzle mode + * + * @param dev LCD register base address + * @param mode Swizzle mode + */ +static inline void lcd_ll_set_swizzle_mode(lcd_cam_dev_t *dev, lcd_ll_swizzle_mode_t mode) +{ + dev->lcd_user.lcd_dout_byte_swizzle_mode = mode; +} + +/** + * @brief Reset Async TX FIFO + * + * @param dev LCD register base address + */ +__attribute__((always_inline)) +static inline void lcd_ll_fifo_reset(lcd_cam_dev_t *dev) +{ + dev->lcd_misc.lcd_afifo_reset = 1; // self clear +} + +/** + * @brief Set the level state of DC line, on different transaction phases + * + * @param dev LCD register base address + * @param idle_phase Level state of DC line on IDLE phase + * @param cmd_phase Level state of DC line on CMD phase + * @param dummy_phase Level state of DC line on DUMMY phase + * @param data_phase Level state of DC line on DATA phase + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool cmd_phase, bool dummy_phase, bool data_phase) +{ + dev->lcd_misc.lcd_cd_idle_edge = idle_phase; + dev->lcd_misc.lcd_cd_cmd_set = (cmd_phase != idle_phase); + dev->lcd_misc.lcd_cd_dummy_set = (dummy_phase != idle_phase); + dev->lcd_misc.lcd_cd_data_set = (data_phase != idle_phase); +} + +/** + * @brief Set cycle of delay for DC line + * + * @param dev LCD register base address + * @param delay Ticks of delay + */ +static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay) +{ + dev->lcd_dly_mode_cfg1.lcd_cd_mode = delay; +} + +/** + * @brief Set the LCD command (the data at CMD phase) + * + * @param dev LCD register base address + * @param data_width Data line width + * @param command command value + */ +__attribute__((always_inline)) +static inline void lcd_ll_set_command(lcd_cam_dev_t *dev, uint32_t data_width, uint32_t command) +{ + // i80 interface only supports 8-bit or 16-bit data width + HAL_ASSERT(data_width == 8 || data_width == 16); + // if command phase has two cycles, in the first cycle we use lcd_first_cmd_val + // in the second cycle, we use lcd_latter_cmd_val + if (data_width == 8) { + dev->lcd_first_cmd_val.val = command & 0xFF; + dev->lcd_latter_cmd_val.val = (command >> 8) & 0xFF; + } else if (data_width == 16) { + dev->lcd_first_cmd_val.val = command; + } +} + +/** + * @brief Wether to enable RGB interface + * + * @param dev LCD register base address + * @param en True to enable RGB interface, False to disable RGB interface + */ +static inline void lcd_ll_enable_rgb_mode(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_ctrl.lcd_rgb_mode_en = en; +} + +/** + * @brief Whether to send the next frame automatically + * + * @param dev LCD register base address + * @param en True to enable, False to disable + */ +static inline void lcd_ll_enable_auto_next_frame(lcd_cam_dev_t *dev, bool en) +{ + // in RGB mode, enabling "next frame" means LCD controller keeps sending frame data + dev->lcd_misc.lcd_next_frame_en = en; +} + +/** + * @brief Wether to output HSYNC signal in porch resion + * + * @param dev LCD register base address + * @param en True to enable, False to disable + */ +static inline void lcd_ll_enable_output_hsync_in_porch_region(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_ctrl2.lcd_hs_blank_en = en; +} + +/** + * @brief Set HSYNC signal offset in the line + * + * @param dev LCD register base address + * @param offset_in_line Offset value + */ +static inline void lcd_ll_set_hsync_position(lcd_cam_dev_t *dev, uint32_t offset_in_line) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_ctrl2, lcd_hsync_position, offset_in_line); +} + +/** + * @brief Set RGB LCD horizontal timing + * + * @param dev LCD register base address + * @param hsw Horizontal sync width + * @param hbp Horizontal back porch + * @param active_width Horizontal active width + * @param hfp Horizontal front porch + */ +static inline void lcd_ll_set_horizontal_timing(lcd_cam_dev_t *dev, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp) +{ + dev->lcd_ctrl2.lcd_hsync_width = hsw - 1; + dev->lcd_ctrl.lcd_hb_front = hbp + hsw - 1; + dev->lcd_ctrl1.lcd_ha_width = active_width - 1; + dev->lcd_ctrl1.lcd_ht_width = hsw + hbp + active_width + hfp - 1; +} + +/** + * @brief Set RGB vertical timing + * + * @param dev LCD register base address + * @param vsw Vertical sync width + * @param vbp Vertical back porch + * @param active_height Vertical active height + * @param vfp Vertical front porch + */ +static inline void lcd_ll_set_vertical_timing(lcd_cam_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp) +{ + dev->lcd_ctrl2.lcd_vsync_width = vsw - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_ctrl1, lcd_vb_front, vbp + vsw - 1); + dev->lcd_ctrl.lcd_va_height = active_height - 1; + dev->lcd_ctrl.lcd_vt_height = vsw + vbp + active_height + vfp - 1; +} + +/** + * @brief Set level state for hsync, vsync, de at IDLE phase + * + * @param dev LCD register base address + * @param hsync_idle_level HSYNC level on IDLE phase + * @param vsync_idle_level VSYNC level on IDLE phase + * @param de_idle_level DE level on IDLE phase + */ +static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_level, bool vsync_idle_level, bool de_idle_level) +{ + dev->lcd_ctrl2.lcd_hsync_idle_pol = hsync_idle_level; + dev->lcd_ctrl2.lcd_vsync_idle_pol = vsync_idle_level; + dev->lcd_ctrl2.lcd_de_idle_pol = de_idle_level; +} + +/** + * @brief Set extra delay for HSYNC, VSYNC, and DE signals + * + * @param dev LCD register base address + * @param hsync_delay HSYNC delay + * @param vsync_delay VSYNC delay + * @param de_delay DE delay + */ +static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay) +{ + dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_delay; + dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_delay; + dev->lcd_dly_mode_cfg1.lcd_de_mode = de_delay; +} + +/** + * @brief Enable/disable interrupt by mask + * + * @param dev LCD register base address + * @param mask Interrupt mask + * @param en True to enable interrupt, False to disable interrupt + */ +static inline void lcd_ll_enable_interrupt(lcd_cam_dev_t *dev, uint32_t mask, bool en) +{ + if (en) { + dev->lc_dma_int_ena.val |= mask & 0x03; + } else { + dev->lc_dma_int_ena.val &= ~(mask & 0x03); + } +} + +/** + * @brief Get interrupt status value + * + * @param dev LCD register base address + * @return Interrupt status value + */ +__attribute__((always_inline)) +static inline uint32_t lcd_ll_get_interrupt_status(lcd_cam_dev_t *dev) +{ + return dev->lc_dma_int_st.val & 0x03; +} + +/** + * @brief Clear interrupt status by mask + * + * @param dev LCD register base address + * @param mask Interupt status mask + */ +__attribute__((always_inline)) +static inline void lcd_ll_clear_interrupt_status(lcd_cam_dev_t *dev, uint32_t mask) +{ + dev->lc_dma_int_clr.val = mask & 0x03; +} + +/** + * @brief Get address of interrupt status register address + * + * @param dev LCD register base address + * @return Interrupt status register address + */ +static inline volatile void *lcd_ll_get_interrupt_status_reg(lcd_cam_dev_t *dev) +{ + return &dev->lc_dma_int_st; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/ldo_ll.h b/components/hal/esp32p4/include/hal/ldo_ll.h new file mode 100644 index 00000000000..e3d2ce4bd0c --- /dev/null +++ b/components/hal/esp32p4/include/hal/ldo_ll.h @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include +#include "esp_bit_defs.h" +#include "hal/assert.h" +#include "soc/pmu_struct.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * LDO capabilities + */ +#define LDO_LL_UNIT_NUM 4 + +/** + * LDO LL macros, these macros are in the unit of mV + */ +#define LDO_LL_EXT_LDO_DREF_VOL_H_BASE 1000 +#define LDO_LL_EXT_LDO_DREF_VOL_H_STEP 100 +#define LDO_LL_EXT_LDO_DREF_VOL_L_BASE 500 +#define LDO_LL_EXT_LDO_DREF_VOL_L_STEP 50 +#define LDO_LL_EXT_LDO_MUL_VOL_BASE 1000 +#define LDO_LL_EXT_LDO_MUL_VOL_STEP 250 + +/** + * Trick to be adapted to the LDO register structure + * + * In pmu_ext_ldo_info_t ext_ldo[6] registers: + * - ext_ldo[0] is LDO1 + * - ext_ldo[3] is LDO2 + * - ext_ldo[1] is LDO3 + * - ext_ldo[4] is LDO4 + */ +#define LDO_ID2INDEX(id) (uint8_t[]){0,3,1,4}[id] + +/** + * LDO ID to real unit ID + */ +#define LDO_ID2UNIT(ldo_id) ((ldo_id) - 1) + +/** + * @brief Enable a LDO + * + * @param ldo_id LDO ID + * @param enable True: enable; False: disable + */ +__attribute__((always_inline)) +static inline void ldo_ll_enable(int ldo_id, bool enable) +{ + HAL_ASSERT(ldo_id < LDO_LL_UNIT_NUM); + + PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.xpd = enable; +} + +/** + * @brief Enable a LDO + * + * @param ldo_id LDO ID + * @param voltage_mv Voltage in mV + */ +__attribute__((always_inline)) +static inline void ldo_ll_set_output_voltage_mv(int ldo_id, int voltage_mv) +{ + int dref = 0, mul = 0; + + /** + * Vout = dref * mul + * + * mul reg[2:0]: + * mul = 1~2.75, step = 0.25 + + * dref reg[3:0]: + * 0~8 : dref = 0.5V ~ 0.9V, step 50mV + * 9~15 : dref = 1.0V ~ 1.6V, step 100mV + */ + if (voltage_mv <= 500) { + dref = 0; + mul = 0; + } else if (voltage_mv <= 900) { + mul = 0; + dref = (voltage_mv - LDO_LL_EXT_LDO_DREF_VOL_L_BASE) / LDO_LL_EXT_LDO_DREF_VOL_L_STEP; + } else if (voltage_mv <= 1600) { + mul = 1; + dref = 6 + (voltage_mv - LDO_LL_EXT_LDO_DREF_VOL_H_BASE) / LDO_LL_EXT_LDO_DREF_VOL_H_STEP; + } else if (voltage_mv <= 2000) { + mul = 4; + dref = (voltage_mv / 2 - LDO_LL_EXT_LDO_DREF_VOL_L_BASE) / LDO_LL_EXT_LDO_DREF_VOL_L_STEP; + } else if (voltage_mv <= 3200) { + mul = 4; + dref = 9 + (voltage_mv / 2 - LDO_LL_EXT_LDO_DREF_VOL_H_BASE) / LDO_LL_EXT_LDO_DREF_VOL_H_STEP; + } else { + mul = 7; + dref = 15; + } + if (mul > 7) { + mul = 7; + } + if (mul < 0) { + mul = 0; + } + if (dref > 15) { + dref = 15; + } + if (dref < 0) { + dref = 0; + } + /** + * tieh_sel: + * - 0: tieh; + * - 1: sdmmc0_tieh; + * - 2: 3.3V; + * - 3: sdmmc1_tieh; + * + * tieh: + * - 0: dref * mul + * - 1: 3.3V + * + * force_tieh_sel: + * - 0: efuse + * - 1: tieh_sel + */ + PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.tieh_sel = 0; + PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.tieh = 0; + PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.force_tieh_sel = 1; + PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.dref = dref; + PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.mul = mul; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/lp_core_ll.h b/components/hal/esp32p4/include/hal/lp_core_ll.h new file mode 100644 index 00000000000..73274fda12b --- /dev/null +++ b/components/hal/esp32p4/include/hal/lp_core_ll.h @@ -0,0 +1,145 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use it in application code. + ******************************************************************************/ + +#pragma once + +#include +#include "soc/lpperi_struct.h" +#include "soc/pmu_struct.h" +#include "soc/lp_system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(9) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(10) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_0 BIT(13) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_BOD BIT(14) +#define LP_CORE_LL_WAKEUP_SOURCE_ETM BIT(17) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 BIT(18) +#define LP_CORE_LL_WAKEUP_SOURCE_LP_I2S BIT(19) +#define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(22) + +/* Use lp timer 1 as the normal wakeup timer, timer 0 is used by deep sleep */ +#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 + +/** + * @brief Enable the bus clock for LP-coree + * + * @param enable true to enable, false to disable + */ +static inline void lp_core_ll_enable_bus_clock(bool enable) +{ + LPPERI.clk_en.ck_en_lp_core = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define lp_core_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the lp_core module + * + */ +static inline void lp_core_ll_reset_register(void) +{ + LPPERI.reset_en.rst_en_lp_core = 1; + LPPERI.reset_en.rst_en_lp_core = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define lp_core_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_reset_register(__VA_ARGS__) + + +/** + * @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core + * + */ +static inline void lp_core_ll_hp_wake_lp(void) +{ + PMU.hp_lp_cpu_comm.hp_trigger_lp = 1; +} + +/** + * @brief Enables the LP core debug module, allowing JTAG to connect + * + * @param enable enable if true, disable if false + */ +static inline void lp_core_ll_debug_module_enable(bool enable) +{ + LPPERI.cpu.lpcore_dbgm_unavailable = !enable; +} + +/** + * @brief Enables CPU reset at sleep + * + * @param enable enable if true, disable if false + */ +static inline void lp_core_ll_rst_at_sleep_enable(bool enable) +{ + PMU.lp_cpu_pwr0.lp_cpu_slp_reset_en = enable; +} + +/** + * @brief Stall lp core cpu at sleep request + * + * @param enable enable if true, disable if false + */ +static inline void lp_core_ll_stall_at_sleep_request(bool enable) +{ + PMU.lp_cpu_pwr0.lp_cpu_slp_stall_en = enable; +} + +/** + * @brief Set the wake-up source for the lp-core + * + * @param flags wake-up sources + */ +static inline void lp_core_ll_set_wakeup_source(uint32_t flags) +{ + PMU.lp_cpu_pwr2.lp_cpu_wakeup_en = flags; +} + +/** + * @brief Get wake-up sources for the LP-core + */ +static inline uint32_t lp_core_ll_get_wakeup_source(void) +{ + return PMU.lp_cpu_pwr2.lp_cpu_wakeup_en; +} + +/** + * @brief Set boot address for lp core + * + * @param boot_address address which the lp core will start booting from + */ +static inline void lp_core_ll_set_boot_address(intptr_t boot_address) +{ + LP_SYS.lp_core_boot_addr.lp_cpu_boot_addr = boot_address; +} + + +/** + * @brief Set address LP-ROM bootloader will jump to after initialization + * + * @param boot_address address which the LP-ROM bootloader will jump to + */ +static inline void lp_core_ll_set_app_boot_address(intptr_t boot_address) +{ + LP_SYS.boot_addr_hp_lp_reg.boot_addr_hp_lp = boot_address; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/lp_timer_ll.h b/components/hal/esp32p4/include/hal/lp_timer_ll.h new file mode 100644 index 00000000000..81aecb30d11 --- /dev/null +++ b/components/hal/esp32p4/include/hal/lp_timer_ll.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-P4 LP_Timer register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/lp_timer_struct.h" +#include "soc/lp_timer_reg.h" +#include "soc/lp_system_reg.h" +#include "hal/lp_timer_types.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value) +{ + dev->target[timer_id].hi.target_hi = (value >> 32) & 0xFFFF; + dev->target[timer_id].lo.target_lo = value & 0xFFFFFFFF; +} + +FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en) +{ + dev->target[timer_id].hi.enable = en; +} + +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id) +{ + return dev->counter[timer_id].lo.counter_lo; +} + +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id) +{ + return dev->counter[timer_id].hi.counter_hi; +} + +FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev) +{ + dev->update.main_timer_update = 1; +} + +FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev) +{ + dev->int_clr.soc_wakeup_int_clr = 1; +} + +FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev) +{ + dev->int_clr.overflow_clr = 1; +} + +FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev) +{ + dev->lp_int_clr.main_timer_lp_int_clr = 1; +} + +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev) +{ + return dev->lp_int_raw.val; +} + +FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask) +{ + dev->lp_int_clr.val = mask; +} + +FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(LP_SYSTEM_REG_LP_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h new file mode 100644 index 00000000000..19aed7fb437 --- /dev/null +++ b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h @@ -0,0 +1,270 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/mipi_dsi_bridge_struct.h" +#include "hal/mipi_dsi_types.h" +#include "hal/lcd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + MIPI_DSI_LL_FLOW_CONTROLLER_DMA, ///< DMA controller as the flow controller + MIPI_DSI_LL_FLOW_CONTROLLER_BRIDGE, ///< DSI bridge is the flow controller +} mipi_dsi_ll_flow_controller_t; + +/** + * @brief Enable the DSI bridge + * + * @param dev Pointer to the DSI bridge controller register base address + * @param en True to enable, false to disable + */ +static inline void mipi_dsi_brg_ll_enable(dsi_brg_dev_t *dev, bool en) +{ + dev->en.dsi_en = en; +} + +/** + * @brief Set the number of 64-bit words in one dma burst transfer + * + * @note valid only when dsi_bridge is the flow controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param burst_len Number of 64-bit words in one dma burst transfer + */ +static inline void mipi_dsi_brg_ll_set_burst_len(dsi_brg_dev_t *dev, uint32_t burst_len) +{ + dev->dma_req_cfg.dma_burst_len = burst_len; +} + +/** + * @brief Set the number of pixel bits in total + * + * @note valid only when dsi_bridge is the flow controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param num_pixel_bits Number of pixel bits, must be aligned to 64 + */ +static inline void mipi_dsi_brg_ll_set_num_pixel_bits(dsi_brg_dev_t *dev, uint32_t num_pixel_bits) +{ + dev->raw_num_cfg.raw_num_total = num_pixel_bits / 64; + // reload the value into internal counter + dev->raw_num_cfg.raw_num_total_set = 1; +} + +/** + * @brief Set the threshold whether the dsi_bridge FIFO can receive one more 64-bit + * + * @note valid only when dsi_bridge is the flow controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param threshold Threshold value + */ +static inline void mipi_dsi_brg_ll_credit_set_threshold(dsi_brg_dev_t *dev, uint32_t threshold) +{ + dev->raw_buf_credit_ctl.credit_thrd = threshold; +} + +/** + * @brief Set the threshold whether the dsi_bridge FIFO can receive one more DMA burst + * + * @note valid only when dsi_bridge is the flow controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param threshold Threshold value + */ +static inline void mipi_dsi_brg_ll_credit_set_burst_threshold(dsi_brg_dev_t *dev, uint32_t threshold) +{ + dev->raw_buf_credit_ctl.credit_burst_thrd = threshold; +} + +/** + * @brief Reset the credit counter of the DSI bridge + * + * @note valid only when dsi_bridge is the flow controller + * + * @param dev Pointer to the DSI bridge controller register base address + */ +static inline void mipi_dsi_brg_ll_credit_reset(dsi_brg_dev_t *dev) +{ + dev->raw_buf_credit_ctl.credit_reset = 1; +} + +/** + * @brief Set the color coding for the bridge controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param pixel_format Color coding + * @param sub_config Sub configuration + */ +static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_rgb_pixel_format_t pixel_format, uint32_t sub_config) +{ + switch (pixel_format) { + case LCD_COLOR_PIXEL_FORMAT_RGB565: + dev->pixel_type.raw_type = 2; + break; + case LCD_COLOR_PIXEL_FORMAT_RGB666: + dev->pixel_type.raw_type = 1; + break; + case LCD_COLOR_PIXEL_FORMAT_RGB888: + dev->pixel_type.raw_type = 0; + break; + default: + abort(); + } + dev->pixel_type.dpi_config = sub_config; +} + +/** + * @brief Set the color space for input color data + * + * @param dev Pointer to the DSI bridge controller register base address + * @param color_space Color space type + */ +static inline void mipi_dsi_brg_ll_set_input_color_space(dsi_brg_dev_t *dev, lcd_color_space_t color_space) +{ + switch (color_space) { + case LCD_COLOR_SPACE_RGB: + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_SPACE_YUV: + dev->pixel_type.data_in_type = 1; + break; + default: + abort(); + } +} + +/** + * @brief Set the vertical timing parameters for the bridge controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param vsw Vertical sync width + * @param vbp Vertical back porch + * @param active_height Active height + * @param vfp Vertical front porch + */ +static inline void mipi_dsi_brg_ll_set_vertical_timing(dsi_brg_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp) +{ + dev->dpi_v_cfg0.vdisp = active_height; + dev->dpi_v_cfg0.vtotal = vsw + vbp + active_height + vfp; + dev->dpi_v_cfg1.vsync = vsw; + dev->dpi_v_cfg1.vbank = vbp; +} + +/** + * @brief Set the horizontal timing parameters for the bridge controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param hsw Horizontal sync width + * @param hbp Horizontal back porch + * @param active_width Active width + * @param hfp Horizontal front porch + */ +static inline void mipi_dsi_brg_ll_set_horizontal_timing(dsi_brg_dev_t *dev, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp) +{ + dev->dpi_h_cfg0.hdisp = active_width; + dev->dpi_h_cfg0.htotal = hsw + hbp + active_width + hfp; + dev->dpi_h_cfg1.hsync = hsw; + dev->dpi_h_cfg1.hbank = hbp; +} + +/** + * @brief Set the under run discard count for the bridge controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param under_run_discard_count Under run discard count + */ +static inline void mipi_dsi_brg_ll_set_underrun_discard_count(dsi_brg_dev_t *dev, uint32_t under_run_discard_count) +{ + dev->dpi_misc_config.fifo_underrun_discard_vcnt = under_run_discard_count; +} + +/** + * @brief Enable the DPI output + * + * @param dev Pointer to the DSI bridge controller register base address + * @param en True to enable, false to disable + */ +static inline void mipi_dsi_brg_ll_enable_dpi_output(dsi_brg_dev_t *dev, bool en) +{ + dev->dpi_misc_config.dpi_en = en; +} + +/** + * @brief Update the configuration of DSI bridge + * + * @param dev Pointer to the DSI bridge controller register base address + */ +static inline void mipi_dsi_brg_ll_update_config(dsi_brg_dev_t *dev) +{ + dev->dpi_config_update.dpi_config_update = 1; +} + +/** + * @brief Enable the refclk and cfg_clk of dsi host + * + * @param dev Pointer to the DSI bridge controller register base address + * @param en True to enable, false to disable + */ +static inline void mipi_dsi_brg_ll_enable_ref_clock(dsi_brg_dev_t *dev, bool en) +{ + dev->host_ctrl.dsi_cfg_ref_clk_en = en; +} + +/** + * @brief Set the flow controller of DMA transfer + * + * @param dev Pointer to the DSI bridge controller register base address + * @param controller Flow controller + */ +static inline void mipi_dsi_brg_ll_set_flow_controller(dsi_brg_dev_t* dev, mipi_dsi_ll_flow_controller_t controller) +{ + dev->dma_flow_ctrl.dsi_dma_flow_controller = controller; +} + +/** + * @brief Set the number of blocks when multi-block transfer is enabled + * + * @note only valid when DMAC is the flow controller + * + * @param dev Pointer to the DSI bridge controller register base address + * @param number Number of blocks + */ +static inline void mipi_dsi_brg_ll_set_multi_block_number(dsi_brg_dev_t* dev, uint32_t number) +{ + dev->dma_flow_ctrl.dma_flow_multiblk_num = number; +} + +/** + * @brief Set the YUV-RGB conversion standard + * + * @param dev Pointer to the DSI bridge controller register base address + * @param std YUV-RGB conversion standard + */ +static inline void mipi_dsi_brg_ll_set_yuv_convert_std(dsi_brg_dev_t* dev, lcd_yuv_conv_std_t std) +{ + switch (std) { + case LCD_YUV_CONV_STD_BT601: + dev->yuv_cfg.protocol = 0; + break; + case LCD_YUV_CONV_STD_BT709: + dev->yuv_cfg.protocol = 1; + break; + default: + abort(); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h new file mode 100644 index 00000000000..a76bbb31340 --- /dev/null +++ b/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h @@ -0,0 +1,769 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/mipi_dsi_host_struct.h" +#include "hal/mipi_dsi_types.h" +#include "hal/lcd_types.h" + +#define MIPI_DSI_LL_MAX_DPI_CLK_DIV 256 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MIPI DSI transmission speed mode + */ +typedef enum { + MIPI_DSI_LL_TRANS_SPEED_HS, /*!< High speed transmission */ + MIPI_DSI_LL_TRANS_SPEED_LP, /*!< Low power transmission */ +} mipi_dsi_ll_trans_speed_mode_t; + +/** + * @brief Color coding type (depth and pixel configuration) + */ +typedef enum { + MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG1 = 0, // 16-bit configuration 1 + MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG2 = 1, // 16-bit configuration 2 + MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG3 = 2, // 16-bit configuration 3 + MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG1 = 3, // 18-bit configuration 1 + MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG2 = 4, // 18-bit configuration 2 + MIPI_DSI_LL_COLOR_CODE_24BIT = 5, // 24-bit +} mipi_dsi_ll_color_coding_t; + +/** + * @brief The kind of test pattern that can be generated by the DSI Host controller + */ +typedef enum { + MIPI_DSI_LL_PATTERN_BAR_VERTICAL, // Vertical bar pattern + MIPI_DSI_LL_PATTERN_BAR_HORIZONTAL, // Horizontal bar pattern + MIPI_DSI_LL_PATTERN_BER_VERTICAL, // Vertical ber pattern +} mipi_dsi_ll_pattern_type_t; + +/** + * @brief MIPI DSI Video mode burst type + */ +typedef enum { + MIPI_DSI_LL_VIDEO_NON_BURST_WITH_SYNC_PULSES, // Non-burst mode with sync pulses + MIPI_DSI_LL_VIDEO_NON_BURST_WITH_SYNC_EVENTS, // Non-burst mode with sync events + MIPI_DSI_LL_VIDEO_BURST_WITH_SYNC_PULSES, // Burst mode with sync pulses +} mipi_dsi_ll_video_burst_type_t; + +/** + * @brief Set the DSI Host controller power state + * + * @param dev Pointer to the DSI Host controller register base address + * @param True to turn on, False to turn off + */ +static inline void mipi_dsi_host_ll_power_on_off(dsi_host_dev_t *dev, bool on) +{ + dev->pwr_up.shutdownz = on; +} + +/** + * @brief Set the division factor for the Time Out clock + * + * @note The Time Out clock is the clock used as the timing unit in the configuration of HS->LP and LP->HS transition error. + * @note Time out clock source is lane byte clock + * + * @param dev Pointer to the DSI Host controller register base address + * @param div Division factor for the Time Out clock + */ +static inline void mipi_dsi_host_ll_set_timeout_clock_division(dsi_host_dev_t *dev, uint32_t div) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->clkmgr_cfg, to_clk_division, div - 1); +} + +/** + * @brief Set the division factor for the Escape clock + * + * @note TX Escape clock source is lane byte clock + * + * @param dev Pointer to the DSI Host controller register base address + * @param div Division factor for the Escape clock + */ +static inline void mipi_dsi_host_ll_set_escape_clock_division(dsi_host_dev_t *dev, uint32_t div) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->clkmgr_cfg, tx_esc_clk_division, div - 1); +} + +/** + * @brief Set the timeout counts for various operations + * + * @param dev Pointer to the DSI Host controller register base address + * @param hs_tx Timeout count for HS transmission, measured in TO_CLK_DIVISION cycles + * @param lp_rx Timeout count for LP reception, measured in TO_CLK_DIVISION cycles + * @param hs_rd Timeout count for HS read, measured in lane byte clock cycles + * @param lp_rd Timeout count for LP read, measured in lane byte clock cycles + * @param hs_wr Timeout count for HS write, measured in lane byte clock cycles + * @param lp_wr Timeout count for LP write, measured in lane byte clock cycles + * @param bta Timeout count for BTA, measured in lane byte clock cycles + */ +static inline void mipi_dsi_host_ll_set_timeout_count(dsi_host_dev_t *dev, uint32_t hs_tx, uint32_t lp_rx, uint32_t hs_rd, uint32_t lp_rd, uint32_t hs_wr, uint32_t lp_wr, uint32_t bta) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, hstx_to_cnt, hs_tx); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, lprx_to_cnt, lp_rx); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_rd_to_cnt, hs_rd_to_cnt, hs_rd); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_rd_to_cnt, lp_rd_to_cnt, lp_rd); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_wr_to_cnt, hs_wr_to_cnt, hs_wr); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_wr_to_cnt, lp_wr_to_cnt, lp_wr); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->bta_to_cnt, bta_to_cnt, bta); +} + +/** + * @brief Enable the automatic mechanism to stop providing clock in the clock lane when time allows + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_non_continuous_clock(dsi_host_dev_t *dev, bool enable) +{ + dev->lpclk_ctrl.auto_clklane_ctrl = enable; +} + +/** + * @brief Request the PHY module to start transmission of high speed clock + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_hs_clock(dsi_host_dev_t *dev, bool enable) +{ + dev->lpclk_ctrl.phy_txrequestclkhs = enable; +} + +////////////////////////////////////////////DPI Interface/////////////////////////////// + +/** + * @brief Set DPI virtual channel ID that will be indexed to the video mode packets + * + * @param dev Pointer to the DSI Host controller register base address + * @param vcid Virtual channel ID + */ +static inline void mipi_dsi_host_ll_dpi_set_vcid(dsi_host_dev_t *dev, uint32_t vcid) +{ + dev->dpi_vcid.dpi_vcid = vcid; +} + +/** + * @brief Set DPI video color coding + * + * @param dev Pointer to the DSI Host controller register base address + * @param color_coding Color coding value + * @param sub_config Sub configuration value + */ +static inline void mipi_dsi_host_ll_dpi_set_color_coding(dsi_host_dev_t *dev, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config) +{ + switch (color_coding) { + case LCD_COLOR_PIXEL_FORMAT_RGB565: + dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG1 + sub_config; + break; + case LCD_COLOR_PIXEL_FORMAT_RGB666: + dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG1 + sub_config; + break; + case LCD_COLOR_PIXEL_FORMAT_RGB888: + dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_24BIT; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Enable DPI loosely packetization video (used only when color depth = 18) + * + * @param dev Pointer to the DSI Host controller register base address + * @param en True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_loosely18_packet(dsi_host_dev_t *dev, bool en) +{ + dev->dpi_color_coding.loosely18_en = en; +} + +/** + * @brief Set DPI timing signal polarity + * + * @param dev Pointer to the DSI Host controller register base address + * @param hsync_active_low If the HSYNC signal is active low + * @param vsync_active_low If the VSYNC signal is active low + * @param de_active_low If the DE signal is active low + * @param shut_down_active_low If the SHUTDOWNZ signal is active low + * @param color_mode_active_low If the COLORM active low + */ +static inline void mipi_dsi_host_ll_dpi_set_timing_polarity(dsi_host_dev_t *dev, bool hsync_active_low, bool vsync_active_low, bool de_active_low, bool shut_down_active_low, bool color_mode_active_low) +{ + dev->dpi_cfg_pol.hsync_active_low = hsync_active_low; + dev->dpi_cfg_pol.vsync_active_low = vsync_active_low; + dev->dpi_cfg_pol.dataen_active_low = de_active_low; + dev->dpi_cfg_pol.shutd_active_low = shut_down_active_low; + dev->dpi_cfg_pol.colorm_active_low = color_mode_active_low; +} + +/** + * @brief Enable frame BTA acknowledgement + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_frame_ack(dsi_host_dev_t *dev, bool en) +{ + dev->vid_mode_cfg.frame_bta_ack_en = en; +} + +/** + * @brief Enable return to low power mode inside horizontal front/back porch periods when timing allows + * + * @param dev Pointer to the DSI Host controller register base address + * @param en_hbp True to enable, False to disable + * @param en_hfp True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_lp_horizontal_timing(dsi_host_dev_t *dev, bool en_hbp, bool en_hfp) +{ + dev->vid_mode_cfg.lp_hbp_en = en_hbp; + dev->vid_mode_cfg.lp_hfp_en = en_hfp; +} + +/** + * @brief Enable return to low power mode inside vertical timing periods (e.g. vbp) when timing allows + * + * @param dev Pointer to the DSI Host controller register base address + * @param en_vsync True to enable, False to disable + * @param en_vbp True to enable, False to disable + * @param en_vfp True to enable, False to disable + * @param en_vact True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_lp_vertical_timing(dsi_host_dev_t *dev, bool en_vsync, bool en_vbp, bool en_vfp, bool en_vact) +{ + dev->vid_mode_cfg.lp_vsa_en = en_vsync; + dev->vid_mode_cfg.lp_vbp_en = en_vbp; + dev->vid_mode_cfg.lp_vfp_en = en_vfp; + dev->vid_mode_cfg.lp_vact_en = en_vact; +} + +/** + * @brief Enable the command transmission in LP mode + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_lp_command(dsi_host_dev_t *dev, bool enable) +{ + dev->vid_mode_cfg.lp_cmd_en = enable; +} + +/** + * @brief Set MIPI DSI video burst type + * + * @param dev Pointer to the DSI Host controller register base address + * @param mode Video mode type + */ +static inline void mipi_dsi_host_ll_dpi_set_video_burst_type(dsi_host_dev_t *dev, mipi_dsi_ll_video_burst_type_t type) +{ + dev->vid_mode_cfg.vid_mode_type = type; +} + +/** + * @brief Set the kind of the pattern to be generated by the DSI Host controller + * + * @param dev Pointer to the DSI Host controller register base address + * @param type Pattern type + */ +static inline void mipi_dsi_host_ll_dpi_set_pattern_type(dsi_host_dev_t *dev, mipi_dsi_ll_pattern_type_t type) +{ + switch (type) { + case MIPI_DSI_LL_PATTERN_BAR_HORIZONTAL: + dev->vid_mode_cfg.vpg_mode = 0; + dev->vid_mode_cfg.vpg_orientation = 1; + break; + case MIPI_DSI_LL_PATTERN_BAR_VERTICAL: + dev->vid_mode_cfg.vpg_mode = 0; + dev->vid_mode_cfg.vpg_orientation = 0; + break; + case MIPI_DSI_LL_PATTERN_BER_VERTICAL: + dev->vid_mode_cfg.vpg_mode = 1; + dev->vid_mode_cfg.vpg_orientation = 0; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Enable pattern generation + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_pattern(dsi_host_dev_t *dev, bool enable) +{ + dev->vid_mode_cfg.vpg_en = enable; +} + +/** + * @brief Enable / Disable DPI video mode + * + * @note Commands can still be sent by the generic interface while in video mode + * + * @param dev Pointer to the DSI Host controller register base address + * @param en True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_dpi_enable_video_mode(dsi_host_dev_t *dev, bool en) +{ + dev->mode_cfg.cmd_video_mode = !en; +} + +/** + * @brief Set the number of bytes inside a null packet + * + * @param dev Pointer to the DSI Host controller register base address + * @param packet_size Number of bytes inside a null packet, 0 means to disable the null packet + */ +static inline void mipi_dsi_host_ll_dpi_set_null_packet_size(dsi_host_dev_t *dev, uint32_t packet_size) +{ + dev->vid_null_size.vid_null_size = packet_size; +} + +/** + * @brief Se the number of chunks to be transmitted during a Line period + * + * @note A trunk is pair of video packet and null packet + * @note The data in each chunk is set in `mipi_dsi_host_ll_dpi_set_video_packet_pixel_num` + * + * @param dev Pointer to the DSI Host controller register base address + * @param trunk_num Number of chunks. 0 - video line is transmitted in a single packet + * 1 - video line is transmitted in a single packet, followed by a null packet + * Others - Multiple chunks are used to transmit each video line + */ +static inline void mipi_dsi_host_ll_dpi_set_trunks_num(dsi_host_dev_t *dev, uint32_t trunks_num) +{ + dev->vid_num_chunks.vid_num_chunks = trunks_num; +} + +/** + * @brief Set the number of pixels in a signal video packet + * + * @note For 18-bit not loosely packed data types, the size must be a multiple of 4 + * @note For YUV data types, the size must be a multiple of 2 + * + * @param dev Pointer to the DSI Host controller register base address + * @param packet_pixels Number of pixels in a signal video packet + */ +static inline void mipi_dsi_host_ll_dpi_set_video_packet_pixel_num(dsi_host_dev_t *dev, uint32_t packet_pixels) +{ + dev->vid_pkt_size.vid_pkt_size = packet_pixels; +} + +/** + * @brief Set vertical timing parameters of video mode + * + * @param dev Pointer to the DSI Host controller register base address + * @param vsw Vertical Synchronization Width, in lines + * @param vbp Vertical Back Porch period, in lines + * @param active_height Vertical active height, in lines + * @param vfp Vertical Front Porch period, in lines + */ +static inline void mipi_dsi_host_ll_dpi_set_vertical_timing(dsi_host_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp) +{ + dev->vid_vsa_lines.vsa_lines = vsw; + dev->vid_vbp_lines.vbp_lines = vbp; + dev->vid_vactive_lines.v_active_lines = active_height; + dev->vid_vfp_lines.vfp_lines = vfp; +} + +/** + * @brief Set horizontal timing parameters of video mode + * + * @param dev Pointer to the DSI Host controller register base address + * @param hsw Horizontal Synchronization Width, in lane byte clock cycles + * @param hbp Horizontal Back Porch period, in lane byte clock cycles + * @param active_width Horizontal active width, in lane byte clock cycles + * @param hfp Horizontal Front Porch period, in lane byte clock cycles + */ +static inline void mipi_dsi_host_ll_dpi_set_horizontal_timing(dsi_host_dev_t *dev, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp) +{ + dev->vid_hsa_time.vid_hsa_time = hsw; + dev->vid_hbp_time.vid_hbp_time = hbp; + // the vid_hline_time here is the overall time for each video line + dev->vid_hline_time.vid_hline_time = active_width + hsw + hbp + hfp; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Enable the tearing effect acknowledge + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_te_ack(dsi_host_dev_t *dev, bool en) +{ + dev->cmd_mode_cfg.tear_fx_en = en; +} + +/** + * @brief Enable the acknowledge request after each packet transmission + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_cmd_ack(dsi_host_dev_t *dev, bool enable) +{ + dev->cmd_mode_cfg.ack_rqst_en = enable; +} + +/** + * @brief Set the speed mode when transmitting DCS short write commands + * + * @param dev Pointer to the DSI Host controller register base address + * @param num_of_params Number of parameters in the DCS command + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_dcs_short_wr_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed) +{ + switch (num_of_params) { + case 0: // DCS short write command with no parameter + dev->cmd_mode_cfg.dcs_sw_0p_tx = speed; + break; + case 1: // DCS short write command with one parameter + dev->cmd_mode_cfg.dcs_sw_1p_tx = speed; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Set the speed mode when transmitting DCS long write commands + * + * @param dev Pointer to the DSI Host controller register base address + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_dcs_long_wr_speed_mode(dsi_host_dev_t *dev, mipi_dsi_ll_trans_speed_mode_t speed) +{ + dev->cmd_mode_cfg.dcs_lw_tx = speed; +} + +/** + * @brief Set the speed mode when transmitting DCS read commands + * + * @param dev Pointer to the DSI Host controller register base address + * @param num_of_params Number of parameters in the DCS command + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_dcs_short_rd_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed) +{ + switch (num_of_params) { + case 0: // DCS short read with zero parameter + dev->cmd_mode_cfg.dcs_sr_0p_tx = speed; + break; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Set the speed mode when transmitting generic short write commands + * + * @param dev Pointer to the DSI Host controller register base address + * @param num_of_params Number of parameters in the generic command + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_gen_short_wr_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed) +{ + switch (num_of_params) { + case 0: // Generic short write command with no parameter + dev->cmd_mode_cfg.gen_sw_0p_tx = speed; + break; + case 1: // Generic short write command with one parameter + dev->cmd_mode_cfg.gen_sw_1p_tx = speed; + break; + case 2: // Generic short write command with two parameters + dev->cmd_mode_cfg.gen_sw_2p_tx = speed; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Set the speed mode when transmitting generic long write commands + * + * @param dev Pointer to the DSI Host controller register base address + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_gen_long_wr_speed_mode(dsi_host_dev_t *dev, mipi_dsi_ll_trans_speed_mode_t speed) +{ + dev->cmd_mode_cfg.gen_lw_tx = speed; +} + +/** + * @brief Set the speed mode when transmitting generic short read commands + * + * @param dev Pointer to the DSI Host controller register base address + * @param num_of_params Number of parameters in the generic command + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_gen_short_rd_speed_mode(dsi_host_dev_t *dev, uint8_t num_of_params, mipi_dsi_ll_trans_speed_mode_t speed) +{ + switch (num_of_params) { + case 0: // Generic short read command with zero parameter + dev->cmd_mode_cfg.gen_sr_0p_tx = speed; + break; + case 1: // Generic short read command with one parameter + dev->cmd_mode_cfg.gen_sr_1p_tx = speed; + break; + case 2: // Generic short read command with two parameters + dev->cmd_mode_cfg.gen_sr_2p_tx = speed; + break; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Set the speed mode for the "Maximum Return Packet Size" command + * + * @param dev Pointer to the DSI Host controller register base address + * @param speed Speed mode + */ +static inline void mipi_dsi_host_ll_set_mrps_speed_mode(dsi_host_dev_t *dev, mipi_dsi_ll_trans_speed_mode_t speed) +{ + dev->cmd_mode_cfg.max_rd_pkt_size = speed; +} + +/** + * @brief Enable receive EoT packet + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_rx_eotp(dsi_host_dev_t *dev, bool en) +{ + dev->pckhdl_cfg.eotp_rx_en = en; +} + +/** + * @brief Enable transmit EoT packet + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable_in_hs_mode True to enable, False to disable + * @param enable_in_lp_mode True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_tx_eotp(dsi_host_dev_t *dev, bool enable_in_hs_mode, bool enable_in_lp_mode) +{ + dev->pckhdl_cfg.eotp_tx_en = enable_in_hs_mode; + dev->pckhdl_cfg.eotp_tx_lp_en = enable_in_lp_mode; +} + +/** + * @brief Enable the CRC check for the received packets + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_rx_crc(dsi_host_dev_t *dev, bool enable) +{ + dev->pckhdl_cfg.crc_rx_en = enable; +} + +/** + * @brief Enable the ECC check for the received packets + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_rx_ecc(dsi_host_dev_t *dev, bool enable) +{ + dev->pckhdl_cfg.ecc_rx_en = enable; +} + +/** + * @brief Enable the Bus Turn Around (BTA) request + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_host_ll_enable_bta(dsi_host_dev_t *dev, bool enable) +{ + dev->pckhdl_cfg.bta_en = enable; +} + +/** + * @brief Set the timing for low power commands sent while in video mode + * + * @param dev Pointer to the DSI Host controller register base address + * @param in_vact largest packet size during VACT period, in bytes + * @param out_vact largest packet size during non-VACT period (VSA,VBP,VFP), in bytes + */ +static inline void mipi_dsi_host_ll_set_lp_largest_cmd_packet_size(dsi_host_dev_t *dev, uint32_t in_vact, uint32_t out_vact) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->dpi_lp_cmd_tim, invact_lpcmd_time, in_vact); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->dpi_lp_cmd_tim, outvact_lpcmd_time, out_vact); +} + +////////////////////////////////////////////Generic Interface/////////////////////////////// + +/** + * @brief Set the header for new packets sent using the Generic interface + * + * @param dev Pointer to the DSI Host controller register base address + * @param dt Data type + * @param vc_id Virtual channel ID + * @param ms_byte most significant byte of the word count for long packets or data1 for short packets + * @param ls_byte least significant byte of the word count for long packets or data0 for short packets + */ +static inline void mipi_dsi_host_ll_gen_set_packet_header(dsi_host_dev_t *dev, uint8_t vc_id, + mipi_dsi_data_type_t dt, uint8_t ms_byte, uint8_t ls_byte) +{ + dev->gen_hdr.val = (ms_byte << 16) | (ls_byte << 8) | ((vc_id << 6) | dt); +} + +/** + * @brief Set the payload for packets sent using the generic interface + * + * @param dev Pointer to the DSI Host controller register base address + * @param payload Payload data + */ +static inline void mipi_dsi_host_ll_gen_write_payload_fifo(dsi_host_dev_t *dev, uint32_t payload) +{ + dev->gen_pld_data.val = payload; +} + +/** + * @brief When using the generic interface, return the contents of READ responses + * + * @param dev Pointer to the DSI Host controller register base address + * @return payload data + */ +static inline uint32_t mipi_dsi_host_ll_gen_read_payload_fifo(dsi_host_dev_t *dev) +{ + return dev->gen_pld_data.val; +} + +/** + * @brief Is the read command of the generic interface busy? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if busy, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_read_cmd_busy(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_rd_cmd_busy; +} + +/** + * @brief Is the read payload FIFO of the generic interface full? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if full, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_read_fifo_full(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_pld_r_full; +} + +/** + * @brief Is the read payload FIFO of the generic interface empty? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if empty, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_read_fifo_empty(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_pld_r_empty; +} + +/** + * @brief Is the write payload FIFO of generic interface full? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if full, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_write_fifo_full(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_pld_w_full; +} + +/** + * @brief Is the write payload FIFO of generic interface empty? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if empty, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_write_fifo_empty(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_pld_w_empty; +} + +/** + * @brief Is the command FIFO of generic interface full? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if full, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_cmd_fifo_full(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_cmd_full; +} + +/** + * @brief Is the command FIFO of generic interface empty? + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if empty, False if not + */ +static inline bool mipi_dsi_host_ll_gen_is_cmd_fifo_empty(dsi_host_dev_t *dev) +{ + return dev->cmd_pkt_status.gen_cmd_empty; +} + +/** + * @brief Set the ID of the virtual channel that for generic reading back + * + * @param dev Pointer to the DSI Host controller register base address + * @param vcid Virtual channel ID + */ +static inline void mipi_dsi_host_ll_gen_set_rx_vcid(dsi_host_dev_t *dev, uint32_t vcid) +{ + dev->gen_vcid.gen_vcid_rx = vcid; +} + +/** + * @brief Set the ID of the virtual channel that for tear effect + * + * @param dev Pointer to the DSI Host controller register base address + * @param vcid Virtual channel ID + */ +static inline void mipi_dsi_host_ll_gen_set_te_vcid(dsi_host_dev_t *dev, uint32_t vcid) +{ + dev->gen_vcid.gen_vcid_tear_auto = vcid; +} + +/** + * @brief Set the ID of the virtual channel that for automatically transmitting generic packets + * + * @param dev Pointer to the DSI Host controller register base address + * @param vcid Virtual channel ID + */ +static inline void mipi_dsi_host_ll_gen_set_tx_vcid(dsi_host_dev_t *dev, uint32_t vcid) +{ + dev->gen_vcid.gen_vcid_tx_auto = vcid; +} + +#ifdef __cplusplus + +} +#endif diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h new file mode 100644 index 00000000000..9bf9b42d1cd --- /dev/null +++ b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/hp_sys_clkrst_struct.h" +#include "hal/misc.h" +#include "hal/mipi_dsi_host_ll.h" +#include "hal/mipi_dsi_brg_ll.h" +#include "hal/mipi_dsi_phy_ll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for MIPI DSI module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void mipi_dsi_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.soc_clk_ctrl1.reg_dsi_sys_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the MIPI DSI module + * + * @param group_id Group ID + */ +static inline void mipi_dsi_ll_reset_register(int group_id) +{ + (void)group_id; + HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dsi_brg = 1; + HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dsi_brg = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_reset_register(__VA_ARGS__) + +/** + * @brief Enable MIPI DSI DPI clock + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void mipi_dsi_ll_enable_dpi_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_enable_dpi_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_dpi_clock(__VA_ARGS__) + +/** + * @brief Set the clock source for the DSI DPI interface + * + * @param group_id Group ID + * @param source Clock source + */ +static inline void mipi_dsi_ll_set_dpi_clock_source(int group_id, mipi_dsi_dpi_clock_source_t source) +{ + (void)group_id; + switch (source) { + case MIPI_DSI_DPI_CLK_SRC_XTAL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 0; + break; + case MIPI_DSI_DPI_CLK_SRC_PLL_F160M: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 2; + break; + case MIPI_DSI_DPI_CLK_SRC_PLL_F240M: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1; + break; + default: + abort(); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_set_dpi_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_dpi_clock_source(__VA_ARGS__) + +/** + * @brief Set the clock division factor for the DPI clock source + * + * @param group_id Group ID + * @param div Division factor + */ +static inline void mipi_dsi_ll_set_dpi_clock_div(int group_id, uint32_t div) +{ + (void)group_id; + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl03, reg_mipi_dsi_dpiclk_div_num, div - 1); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_set_dpi_clock_div(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_dpi_clock_div(__VA_ARGS__) + +/** + * @brief Enable MIPI DSI PHY configuration clock + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void mipi_dsi_ll_enable_phy_config_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_cfg_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_enable_phy_config_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_phy_config_clock(__VA_ARGS__) + +/** + * @brief Enable MIPI DSI PHY PLL reference clock + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void mipi_dsi_ll_enable_phy_reference_clock(int group_id, bool enable) +{ + (void)group_id; + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_enable_phy_reference_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_phy_reference_clock(__VA_ARGS__) + +/** + * @brief Set the clock source for the DSI PHY interface + * + * @param group_id Group ID + * @param source Clock source + */ +static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_clock_source_t source) +{ + (void)group_id; + switch (source) { + case MIPI_DSI_PHY_CLK_SRC_PLL_F20M: + HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0; + break; + case MIPI_DSI_PHY_CLK_SRC_RC_FAST: + HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1; + break; + case MIPI_DSI_PHY_CLK_SRC_PLL_F25M: + HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2; + break; + default: + abort(); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_set_phy_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_phy_clock_source(__VA_ARGS__) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h new file mode 100644 index 00000000000..c5de472eb0e --- /dev/null +++ b/components/hal/esp32p4/include/hal/mipi_dsi_phy_ll.h @@ -0,0 +1,234 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/mipi_dsi_host_struct.h" +#include "hal/mipi_dsi_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the PHY clock lane + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_phy_ll_enable_clock_lane(dsi_host_dev_t *dev, bool enable) +{ + dev->phy_rstz.phy_enableclk = enable; +} + +/** + * @brief Reset the digital section of the PHY + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to place the PHY in the reset state, False to release the reset + */ +static inline void mipi_dsi_phy_ll_reset(dsi_host_dev_t *dev) +{ + dev->phy_rstz.phy_rstz = 0; + dev->phy_rstz.phy_rstz = 1; +} + +/** + * @brief Shutdown the PHY + * + * @param dev Pointer to the DSI Host controller register base address + * @param on_off True to power up, false to shut down + */ +static inline void mipi_dsi_phy_ll_power_on_off(dsi_host_dev_t *dev, bool on_off) +{ + dev->phy_rstz.phy_shutdownz = on_off; +} + +/** + * @brief Force the PHY to stay on while in ULPS + * + * @note To follow the programming model, use wakeup_pll function + * + * @param dev Pointer to the DSI Host controller register base address + * @param enable True to enable, False to disable + */ +static inline void mipi_dsi_phy_ll_force_pll(dsi_host_dev_t *dev, bool force) +{ + dev->phy_rstz.phy_forcepll = force; +} + +/** + * @brief Check if the PHY PLL is locked + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if the PLL is locked, False otherwise + */ +static inline bool mipi_dsi_phy_ll_is_pll_locked(dsi_host_dev_t *dev) +{ + return dev->phy_status.phy_lock; +} + +/** + * @brief Check if the Lane0 in stop state + * + * @param dev Pointer to the DSI Host controller register base address + * @return True if the Lane0 in stop state, False otherwise + */ +static inline bool mipi_dsi_phy_ll_is_lane0_stoped(dsi_host_dev_t *dev) +{ + return dev->phy_status.phy_stopstate0lane; +} + +/** + * @brief Set the number of active data lanes + * + * @param dev Pointer to the DSI Host controller register base address + * @param lane_num Number of lanes used in the DSI link + */ +static inline void mipi_dsi_phy_ll_set_data_lane_number(dsi_host_dev_t *dev, uint32_t lane_num) +{ + dev->phy_if_cfg.n_lanes = lane_num - 1; +} + +/** + * @brief Set the minimum time PHY needs to stay in Stop state before requesting an HS transmission + * + * @param dev Pointer to the DSI Host controller register base address + * @param wait_time Time in lane byte clock cycles + */ +static inline void mipi_dsi_phy_ll_set_stop_wait_time(dsi_host_dev_t *dev, uint32_t wait_time) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->phy_if_cfg, phy_stop_wait_time, wait_time); +} + +/** + * @brief Set the maximum time required to perform a read command in lane byte clock cycles + * + * @note This can only be modified when no read command is in progress + * + * @param dev Pointer to the DSI Host controller register base address + * @param max_time Maximum time required to perform a read command in lane byte clock cycles + */ +static inline void mipi_dsi_phy_ll_set_max_read_time(dsi_host_dev_t *dev, uint32_t max_time) +{ + dev->phy_tmr_rd_cfg.max_rd_time = max_time; +} + +/** + * @brief ULPS mode request on all active data lanes + * + * @param dev Pointer to the DSI Host controller register base address + */ +static inline void mipi_dsi_phy_ll_data_enter_ulps(dsi_host_dev_t *dev) +{ + dev->phy_ulps_ctrl.phy_txrequlpslan = 1; +} + +/** + * @brief ULPS mode exit on all active data lanes + * + * @param dev Pointer to the DSI Host controller register base address + */ +static inline void mipi_dsi_phy_ll_data_exit_ulps(dsi_host_dev_t *dev) +{ + dev->phy_ulps_ctrl.phy_txexitulpslan = 1; +} + +/** + * @brief ULPS mode request on clock lane + * + * @param dev Pointer to the DSI Host controller register base address + */ +static inline void mipi_dsi_phy_ll_clk_enter_ulps(dsi_host_dev_t *dev) +{ + dev->phy_ulps_ctrl.phy_txrequlpsclk = 1; +} + +/** + * @brief ULPS mode exit on clock lane + * + * @param dev Pointer to the DSI Host controller register base address + */ +static inline void mipi_dsi_phy_ll_clk_exit_ulps(dsi_host_dev_t *dev) +{ + dev->phy_ulps_ctrl.phy_txexitulpsclk = 1; +} + +/** + * @brief Control the internal interface (clock and pins) between the DSI Host and the D-PHY + * + * @param dev Pointer to the DSI Host controller register base address + * @param clock_level Level of the clock + * @param clear Whether to clear the pins of the PHY + */ +static inline void mipi_dsi_phy_ll_write_clock(dsi_host_dev_t *dev, uint32_t clock_level, bool clear) +{ + dev->phy_tst_ctrl0.val = clock_level << 1 | clear; +} + +/** + * @brief Write the PHY register via internal interface (so-called the test interface) + * + * @param dev Pointer to the DSI Host controller register base address + * @param reg_addr Address of the PHY register + */ +static inline void mipi_dsi_phy_ll_write_reg_addr(dsi_host_dev_t *dev, uint8_t reg_addr) +{ + dev->phy_tst_ctrl1.val = (1 << 16) | (reg_addr & 0xFF); +} + +/** + * @brief Write the PHY register value via internal interface (so-called the test interface) + * + * @param dev Pointer to the DSI Host controller register base address + * @param reg_val Value to write to the PHY register + */ +static inline void mipi_dsi_phy_ll_write_reg_val(dsi_host_dev_t *dev, uint8_t reg_val) +{ + dev->phy_tst_ctrl1.val = reg_val & 0xFF; +} + +/** + * @brief Send trigger transmission + * + * @note Only one bit of the trigger_request is asserted at a time + * @note Only call this function when the PHY is not in LPDT or ULPS modes + * + * @param dev Pointer to the DSI Host controller register base address + * @param trigger_request Trigger request + */ +static inline void mipi_dsi_phy_ll_escape_trigger(dsi_host_dev_t *dev, uint8_t trigger_request) +{ + dev->phy_tx_triggers.phy_tx_triggers = trigger_request; + while (dev->phy_status.phy_stopstate0lane == 0); + dev->phy_tx_triggers.phy_tx_triggers = 0; +} + +/** + * @brief Set the time to switch between HS and LP + * + * @param dev Pointer to the DSI Host controller register base address + * @param data_hs2lp Time to switch data lane from HS to LP, in lane byte clock cycles + * @param data_lp2hs Time to switch data lane from LP to HS, in lane byte clock cycles + * @param clk_hs2lp Time to switch clock lane from HS to LP, in lane byte clock cycles + * @param clk_lp2hs Time to switch clock lane from LP to HS, in lane byte clock cycles + */ +static inline void mipi_dsi_phy_ll_set_switch_time(dsi_host_dev_t *dev, uint32_t data_hs2lp, uint32_t data_lp2hs, uint32_t clk_hs2lp, uint32_t clk_lp2hs) +{ + dev->phy_tmr_cfg.phy_hs2lp_time = data_hs2lp; + dev->phy_tmr_cfg.phy_lp2hs_time = data_lp2hs; + dev->phy_tmr_lpclk_cfg.phy_clkhs2lp_time = clk_hs2lp; + dev->phy_tmr_lpclk_cfg.phy_clklp2hs_time = clk_lp2hs; +} + +#ifdef __cplusplus + +} +#endif diff --git a/components/hal/esp32p4/include/hal/pmu_ll.h b/components/hal/esp32p4/include/hal/pmu_ll.h new file mode 100644 index 00000000000..1b898aee319 --- /dev/null +++ b/components/hal/esp32p4/include/hal/pmu_ll.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C6 PMU register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/assert.h" +#include "soc/pmu_struct.h" +#include "hal/pmu_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw) +{ + return hw->lp_int_raw.val; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask) +{ + hw->lp_int_raw.val = mask; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h index e22a0258155..c4d7e26646d 100644 --- a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h @@ -10,6 +10,7 @@ #include #include "soc/soc.h" #include "soc/regi2c_defs.h" +#include "soc/hp_sys_clkrst_reg.h" #ifdef __cplusplus extern "C" { @@ -45,6 +46,32 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); } +/** + * @brief Start MPLL self-calibration + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_start(void) +{ + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); +} + +/** + * @brief Stop MPLL self-calibration + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_stop(void) +{ + SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP); +} + +/** + * @brief Check whether MPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_mpll_calibration_is_done(void) +{ + return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_END); +} + /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register */ diff --git a/components/hal/esp32p4/include/hal/sdm_ll.h b/components/hal/esp32p4/include/hal/sdm_ll.h new file mode 100644 index 00000000000..7bdad37119d --- /dev/null +++ b/components/hal/esp32p4/include/hal/sdm_ll.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/gpio_ext_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set Sigma-delta enable + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param en Sigma-delta enable value + */ +static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en) +{ + hw->misc.function_clk_en = en; +} + +/** + * @brief Set Sigma-delta channel duty. + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param channel Sigma-delta channel number + * @param density Sigma-delta quantized density of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90. + * The waveform is more like a random one in this range. + */ +__attribute__((always_inline)) +static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); +} + +/** + * @brief Set Sigma-delta channel's clock pre-scale value. + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param channel Sigma-delta channel number + * @param prescale The divider of source clock, ranges from 1 to 256 + */ +static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) +{ + HAL_ASSERT(prescale && prescale <= 256); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h index de642b56d69..fbdb8990988 100644 --- a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h @@ -24,8 +24,6 @@ extern "C" { #endif -//TODO: IDF-7545 - /// Choose type of chip you want to encrypt manully typedef enum { @@ -38,10 +36,9 @@ typedef enum */ static inline void spi_flash_encrypt_ll_enable(void) { - // REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, - // HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | - // HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); - abort(); + REG_SET_BIT(HP_SYSTEM_CRYPTO_CTRL_REG, + HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | + HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT); } /* @@ -49,9 +46,8 @@ static inline void spi_flash_encrypt_ll_enable(void) */ static inline void spi_flash_encrypt_ll_disable(void) { - // REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, - // HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); - abort(); + REG_CLR_BIT(HP_SYSTEM_CRYPTO_CTRL_REG, + HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT); } /** diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index 7bbb1aea580..f428edde56c 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -251,6 +251,24 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. This function is only used in quad flash + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + if (extra_dummy > 0) { + dev->flash_waiti_ctrl.waiti_dummy_cyclelen = extra_dummy - 1; + dev->flash_waiti_ctrl.waiti_dummy = 1; + } else { + dev->flash_waiti_ctrl.waiti_dummy = 0; + } +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32p4/include/hal/systimer_ll.h b/components/hal/esp32p4/include/hal/systimer_ll.h index 65e3d364b3f..e082de3e75b 100644 --- a/components/hal/esp32p4/include/hal/systimer_ll.h +++ b/components/hal/esp32p4/include/hal/systimer_ll.h @@ -36,12 +36,40 @@ static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t cl /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define systimer_ll_set_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; systimer_ll_set_clock_source(__VA_ARGS__) - static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) { return (HP_SYS_CLKRST.peri_clk_ctrl21.reg_systimer_clk_src_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + HP_SYS_CLKRST.soc_clk_ctrl2.reg_systimer_apb_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_stimer = 1; + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_stimer = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /********************** ETM *****************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en) diff --git a/components/hal/esp32p4/include/hal/touch_sensor_ll.h b/components/hal/esp32p4/include/hal/touch_sensor_ll.h new file mode 100644 index 00000000000..117ff8d2e1d --- /dev/null +++ b/components/hal/esp32p4/include/hal/touch_sensor_ll.h @@ -0,0 +1,948 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/touch_sensor_periph.h" +#include "soc/lp_analog_peri_struct.h" +#include "soc/touch_struct.h" +#include "soc/pmu_struct.h" +#include "soc/soc_caps.h" +#include "hal/touch_sensor_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define TOUCH_LL_READ_RAW 0x0 +#define TOUCH_LL_READ_BENCHMARK 0x2 +#define TOUCH_LL_READ_SMOOTH 0x3 + +#define TOUCH_LL_TIMER_FORCE_DONE_BY_SW 0x1 +#define TOUCH_LL_TIMER_DONE_BY_FSM 0x0 + +// Interrupt mask +#define TOUCH_LL_INTR_MASK_SCAN_DONE BIT(1) +#define TOUCH_LL_INTR_MASK_DONE BIT(2) +#define TOUCH_LL_INTR_MASK_ACTIVE BIT(3) +#define TOUCH_LL_INTR_MASK_INACTIVE BIT(4) +#define TOUCH_LL_INTR_MASK_TIMEOUT BIT(5) +#define TOUCH_LL_INTR_MASK_APPROACH_DONE BIT(6) +#define TOUCH_LL_INTR_MASK_ALL (0x3F) + +#define TOUCH_LL_FULL_CHANNEL_MASK ((uint16_t)((1U << SOC_TOUCH_SENSOR_NUM) - 1)) +#define TOUCH_LL_NULL_CHANNEL (15) // Null Channel id. Used for disabling some functions like sleep/approach/waterproof + +#define TOUCH_LL_PAD_MEASURE_WAIT_MAX (0x7FFF) // The timer frequency is 8Mhz, the max value is 0xff + +/** + * Enable/disable clock gate of touch sensor. + * + * @param enable true/false. + */ +static inline void touch_ll_enable_clock(bool enable) +{ + LP_ANA_PERI.date.clk_en = enable; +} + +/** + * Set the power on wait cycle + * + * @param wait_cycles + */ +static inline void touch_ll_set_power_on_wait_cycle(uint32_t wait_cycles) +{ + LP_ANA_PERI.touch_scan_ctrl1.touch_xpd_wait = wait_cycles; +} + +/** + * Set touch sensor touch sensor charge and discharge times of every measurement on a pad. + * + * @param sampler_id The sampler index + * @param charge_times The times of charge and discharge in each measure process of touch channels. + * The timer frequency is 8Mhz. Range: 0 ~ 0xffff. + */ +static inline void touch_ll_set_charge_times(uint8_t sampler_id, uint16_t charge_times) +{ + //The times of charge and discharge in each measure process of touch channels. + switch (sampler_id) { + case 0: + LP_ANA_PERI.touch_work_meas_num.touch_meas_num0 = charge_times; + break; + case 1: + LP_ANA_PERI.touch_work_meas_num.touch_meas_num1 = charge_times; + break; + case 2: + LP_ANA_PERI.touch_work_meas_num.touch_meas_num2 = charge_times; + break; + default: + abort(); + } +} + +/** + * Get touch sensor times of charge and discharge. + * + * @param meas_times Pointer to accept times count of charge and discharge. + */ +static inline void touch_ll_get_charge_times(uint8_t sampler_id, uint16_t *charge_times) +{ + switch (sampler_id) { + case 0: + *charge_times = LP_ANA_PERI.touch_work_meas_num.touch_meas_num0; + break; + case 1: + *charge_times = LP_ANA_PERI.touch_work_meas_num.touch_meas_num1; + break; + case 2: + *charge_times = LP_ANA_PERI.touch_work_meas_num.touch_meas_num2; + break; + default: + abort(); + } +} + +/** + * Set touch sensor sleep time. + * + * @param interval_ticks The touch sensor will sleep for some cycles after each measurement. + * interval_ticks decide the interval between each measurement. + * t_sleep = interval_ticks / (RTC_SLOW_CLK frequency). + * The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function. + */ +static inline void touch_ll_set_measure_interval_ticks(uint16_t interval_ticks) +{ + // touch sensor sleep cycle Time = interval_ticks / RTC_SLOW_CLK + HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.touch_pwr_cntl, touch_sleep_cycles, interval_ticks); +} + +/** + * Get touch sensor sleep time. + * + * @param interval_ticks Pointer to accept measurement interval (sleep) cycle number. + */ +static inline void touch_ll_get_measure_interval_ticks(uint16_t *interval_ticks) +{ + *interval_ticks = HAL_FORCE_READ_U32_REG_FIELD(PMU.touch_pwr_cntl, touch_sleep_cycles); +} + +/** + * Set touch sensor FSM mode. + * The measurement action can be triggered by the hardware timer, as well as by the software instruction. + * + * @param mode FSM mode. + * TOUCH_FSM_MODE_TIMER: the FSM will trigger scanning repeatedly under the control of the hardware timer + * TOUCH_FSM_MODE_SW: the FSM will trigger scanning once under the control of the software + */ +static inline void touch_ll_set_fsm_mode(touch_fsm_mode_t mode) +{ + // FSM controlled by timer or software + LP_ANA_PERI.touch_mux0.touch_fsm_en = mode; + // Start by timer or software + LP_ANA_PERI.touch_mux0.touch_start_force = mode; + // Stop by timer or software + LP_ANA_PERI.touch_mux0.touch_done_force = mode; +} + +/** + * Get touch sensor FSM mode. + * The measurement action can be triggered by the hardware timer, as well as by the software instruction. + * + * @param mode FSM mode. + */ +static inline void touch_ll_get_fsm_mode(touch_fsm_mode_t *mode) +{ + *mode = (touch_fsm_mode_t)LP_ANA_PERI.touch_mux0.touch_fsm_en; +} + +/** + * Is touch sensor FSM using hardware timer to trigger scanning. + * The measurement action can be triggered by the hardware timer, as well as by the software instruction. + * + * @return Whether FSM timer enabled. + */ +static inline bool touch_ll_is_fsm_using_timer(void) +{ + return !LP_ANA_PERI.touch_mux0.touch_start_force; +} + +/** + * Touch timer trigger measurement and always wait measurement done. + * Force done for touch timer ensures that the timer always can get the measurement done signal. + */ +static inline void touch_ll_force_done_curr_measurement(void) +{ + if (touch_ll_is_fsm_using_timer()) { + LP_ANA_PERI.touch_mux0.touch_done_force = TOUCH_LL_TIMER_FORCE_DONE_BY_SW; + LP_ANA_PERI.touch_mux0.touch_done_en = 1; + LP_ANA_PERI.touch_mux0.touch_done_en = 0; + LP_ANA_PERI.touch_mux0.touch_done_force = TOUCH_LL_TIMER_DONE_BY_FSM; + } else { + LP_ANA_PERI.touch_mux0.touch_done_en = 1; + LP_ANA_PERI.touch_mux0.touch_done_en = 0; + } +} + +/** + * Start touch sensor FSM timer to run FSM repeatedly + * The measurement action can be triggered by the hardware timer, as well as by the software instruction. + * @note + * The timer should be triggered + * @param is_sleep Whether in sleep state + */ +static inline void touch_ll_start_fsm_repeated_timer(bool is_sleep) +{ + /** + * Touch timer trigger measurement and always wait measurement done. + * Force done for touch timer ensures that the timer always can get the measurement done signal. + */ + touch_ll_force_done_curr_measurement(); + if (is_sleep) { + PMU.touch_pwr_cntl.touch_sleep_timer_en = 1; + } else { + LP_ANA_PERI.touch_mux0.touch_start_en = 1; + } +} + +/** + * Stop touch sensor FSM timer. + * The measurement action can be triggered by the hardware timer, as well as by the software instruction. + * @param is_sleep Whether in sleep state + */ +static inline void touch_ll_stop_fsm_repeated_timer(bool is_sleep) +{ + if (is_sleep) { + PMU.touch_pwr_cntl.touch_sleep_timer_en = 0; + } else { + LP_ANA_PERI.touch_mux0.touch_start_en = 0; + } + touch_ll_force_done_curr_measurement(); +} + +/** + * Start touch sensor FSM once by software + * @note Every trigger means measuring one channel, not scanning all enabled channels + */ +static inline void touch_ll_start_fsm_once(void) +{ + /* Trigger once measurement */ + LP_ANA_PERI.touch_mux0.touch_start_en = 1; + LP_ANA_PERI.touch_mux0.touch_start_en = 0; +} + +static inline void touch_ll_measure_channel_once(uint16_t chan_mask) +{ + LP_ANA_PERI.touch_mux1.touch_start = chan_mask; +} + +/** + * Set touch sensor threshold of charge cycles that triggers pad active state. + * The threshold determines the sensitivity of the touch sensor. + * The threshold is the original value of the trigger state minus the benchmark value. + * + * @note If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered. + * @param touch_num The touch pad id + * @param sampler_id The sampler index + * @param thresh The threshold of charge cycles + */ +static inline void touch_ll_set_chan_active_threshold(uint32_t touch_num, uint8_t sampler_id, uint32_t thresh) +{ + HAL_ASSERT(sampler_id < SOC_TOUCH_SAMPLER_NUM); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_padx_thn[touch_num].thn[sampler_id], threshold, thresh); +} + +/** + * Enable touch sensor channel. Register touch channel into touch sensor measurement group. + * The working mode of the touch sensor is simultaneous measurement. + * This function will set the measure bits according to the given bitmask. + * + * @note If set this mask, the FSM timer should be stop firstly. + * @note The touch sensor that in scan map, should be deinit GPIO function firstly. + * @param enable_mask bitmask of touch sensor scan group. + * e.g. TOUCH_PAD_NUM1 -> BIT(1) + * @return + * - ESP_OK on success + */ +static inline void touch_ll_set_channel_mask(uint16_t enable_mask) +{ + uint16_t mask = enable_mask & TOUCH_PAD_BIT_MASK_ALL; + LP_ANA_PERI.touch_scan_ctrl1.touch_scan_pad_map = mask; + LP_ANA_PERI.touch_filter2.touch_outen = mask; +} + +/** + * @brief Power on the channel by mask + * + * @param chan_mask The channel mask that needs to power on + */ +static inline void touch_ll_channel_power_on(uint16_t chan_mask) +{ + uint32_t curr_mask = LP_ANA_PERI.touch_mux1.touch_xpd; + LP_ANA_PERI.touch_mux1.touch_xpd = chan_mask | curr_mask; +} + +/** + * @brief Power off the channel by mask + * + * @param chan_mask The channel mask that needs to power off + */ +static inline void touch_ll_channel_power_off(uint16_t chan_mask) +{ + uint32_t curr_mask = LP_ANA_PERI.touch_mux1.touch_xpd; + LP_ANA_PERI.touch_mux1.touch_xpd = (~chan_mask) & curr_mask; +} + +/** + * @brief Start channel by mask + * @note Only start the specified channels + * + * @param chan_mask The channel mask that needs to start + */ +static inline void touch_ll_channel_start(uint16_t chan_mask) +{ + uint32_t curr_mask = LP_ANA_PERI.touch_mux1.touch_start; + LP_ANA_PERI.touch_mux1.touch_start = chan_mask | curr_mask; + LP_ANA_PERI.touch_mux1.touch_start = (~chan_mask) & curr_mask; +} + +/** + * Get the touch sensor active channel mask, usually used in ISR to decide which channels are 'touched'. + * + * @param active_mask The touch channel status. e.g. Touch1 trigger status is `status_mask & (BIT1)`. + */ +static inline void touch_ll_get_active_channel_mask(uint32_t *active_mask) +{ + *active_mask = LP_TOUCH.chn_status.pad_active; +} + +/** + * Clear all touch sensor channels active status. + * + * @note Generally no manual removal is required. + */ +static inline void touch_ll_clear_active_channel_status(void) +{ + LP_ANA_PERI.touch_clr.touch_status_clr = 1; +} + +/** + * Get the data of the touch channel according to the types + * + * @param touch_num touch pad index + * @param sampler_id The sampler index + * @param type data type + * 0/1: TOUCH_LL_READ_RAW, the raw data of the touch channel + * 2: TOUCH_LL_READ_BENCHMARK, benchmark value of touch channel, + * the benchmark value is the maximum during the first measurement period + * 3: TOUCH_LL_READ_SMOOTH, the smoothed data that obtained by filtering the raw data. + * @param data pointer to the data + */ +__attribute__((always_inline)) +static inline void touch_ll_read_chan_data(uint32_t touch_num, uint8_t sampler_id, uint8_t type, uint32_t *data) +{ + HAL_ASSERT(sampler_id < SOC_TOUCH_SAMPLER_NUM); + HAL_ASSERT(type <= TOUCH_LL_READ_SMOOTH); + LP_ANA_PERI.touch_mux0.touch_freq_sel = sampler_id + 1; + LP_ANA_PERI.touch_mux0.touch_data_sel = type; + *data = LP_TOUCH.chn_data[touch_num - 1].pad_data; +} + +/** + * Get touch sensor measure status. No block. + * + * @return + * - If touch sensors measure done. + */ +static inline bool touch_ll_is_measure_done(uint32_t *touch_num) +{ + *touch_num = (uint32_t)(LP_TOUCH.chn_status.scan_curr); + return (bool)LP_TOUCH.chn_status.meas_done; +} + +/** + * Select the counting mode of the binarized touch out wave + * + * @param mode 0: as data, the value will be smaller than actual value but more sensitive when the frequency of touch_out is close to the source clock + * 1: as clock, the value is accurate but less sensitive when the frequency of touch_out is close to the source clock + * No big difference when the frequency of touch_out is far more lower than the source clock + */ +static inline void touch_ll_set_out_mode(touch_out_mode_t mode) +{ + LP_ANA_PERI.touch_work.touch_out_sel = mode; +} + +/** + * @brief Set the clock division of the sampling frequency + * + * @param sampler_id The sampler index + * @param div_num Division number + */ +static inline void touch_ll_set_clock_div(uint8_t sampler_id, uint32_t div_num) +{ + switch (sampler_id) { + case 0: + LP_ANA_PERI.touch_work.div_num0 = div_num; + break; + case 1: + LP_ANA_PERI.touch_work.div_num1 = div_num; + break; + case 2: + LP_ANA_PERI.touch_work.div_num2 = div_num; + break; + default: + // invalid sampler_id + abort(); + } +} + +/** + * Set connection type of touch channel in idle status. + * When a channel is in measurement mode, other initialized channels are in idle mode. + * The touch channel is generally adjacent to the trace, so the connection state of the idle channel + * affects the stability and sensitivity of the test channel. + * The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels. + * The `CONN_GND`(grounding) setting increases the stability of touch channels. + * @note This option does not take effect, it is default to HIGH Z + * Only remained here to be compatible to other version + * + * @param type Select idle channel connect to high resistance state or ground. (No effect) + */ +static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type) +{ + (void)type; +} + +/** + * Get the current channel that under measuring. + * + * @return + * - touch channel number + */ +__attribute__((always_inline)) +static inline uint32_t touch_ll_get_current_meas_channel(void) +{ + return (uint32_t)(LP_TOUCH.chn_status.scan_curr); +} + +/** + * Enable touch sensor interrupt by bitmask. + * + * @param int_mask interrupt mask + */ +static inline void touch_ll_intr_enable(uint32_t int_mask) +{ + uint32_t mask = LP_TOUCH.int_ena.val; + mask |= (int_mask & TOUCH_LL_INTR_MASK_ALL); + LP_TOUCH.int_ena.val = mask; +} + +/** + * Disable touch sensor interrupt by bitmask. + * + * @param int_mask interrupt mask + */ +static inline void touch_ll_intr_disable(uint32_t int_mask) +{ + uint32_t mask = LP_TOUCH.int_ena.val; + mask &= ~(int_mask & TOUCH_LL_INTR_MASK_ALL); + LP_TOUCH.int_ena.val = mask; +} + +/** + * Clear touch sensor interrupt by bitmask. + * + * @param int_mask Pad mask to clear interrupts + */ +static inline void touch_ll_intr_clear_all(void) +{ + LP_TOUCH.int_clr.val = TOUCH_LL_INTR_MASK_ALL; +} + +/** + * Get the bitmask of touch sensor interrupt status. + * + * @return type interrupt type + */ +static inline uint32_t touch_ll_get_intr_status_mask(void) +{ + uint32_t intr_st = LP_TOUCH.int_st.val; + return (intr_st & TOUCH_LL_INTR_MASK_ALL); +} + +/** + * Enable the timeout check for all touch sensor channels measurements. + * When the touch reading of a touch channel exceeds the measurement threshold, + * If enable: a timeout interrupt will be generated and it will go to the next channel measurement. + * If disable: the FSM is always on the channel, until the measurement of this channel is over. + * + * @param timeout_cycles The maximum time cycles of the measurement on one channel. + */ +static inline void touch_ll_timeout_enable(uint32_t timeout_cycles) +{ + LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_num = timeout_cycles; + LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_en = 1; +} + +/** + * Disable the timeout check for all touch sensor channels measurements. + * When the touch reading of a touch channel exceeds the measurement threshold, + * If enable: a timeout interrupt will be generated and it will go to the next channel measurement. + * If disable: the FSM is always on the channel, until the measurement of this channel is over. + */ +static inline void touch_ll_timeout_disable(void) +{ + LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_en = 0; +} + +/** + * Set the engaged sampler number + * + * @param sampler_num The enabled sampler number, range 0~3. + * 0/1 means only one sampler enabled, which can not support frequency hopping + */ +static inline void touch_ll_sampler_set_engaged_num(uint8_t sampler_num) +{ + HAL_ASSERT(sampler_num < SOC_TOUCH_SAMPLER_NUM); + LP_ANA_PERI.touch_scan_ctrl2.freq_scan_en = !!sampler_num; + LP_ANA_PERI.touch_scan_ctrl2.freq_scan_cnt_limit = sampler_num ? sampler_num : 1; +} + +/** + * Set capacitance and resistance of the RC filter of the sampling frequency. + * + * @param sampler_id The sampler index + * @param cap Capacitance of the RC filter. + * @param res Resistance of the RC filter. + */ +static inline void touch_ll_sampler_set_rc_filter(uint8_t sampler_id, uint32_t cap, uint32_t res) +{ + HAL_ASSERT(sampler_id < SOC_TOUCH_SAMPLER_NUM); + LP_ANA_PERI.touch_freq_scan_para[sampler_id].touch_freq_dcap_lpf = cap; + LP_ANA_PERI.touch_freq_scan_para[sampler_id].touch_freq_dres_lpf = res; +} + +/** + * @brief Set the driver of the sampling frequency + * + * @param sampler_id The sampler index + * @param ls_drv Low speed touch driver + * @param hs_drv High speed touch driver + */ +static inline void touch_ll_sampler_set_driver(uint8_t sampler_id, uint32_t ls_drv, uint32_t hs_drv) +{ + HAL_ASSERT(sampler_id < SOC_TOUCH_SAMPLER_NUM); + LP_ANA_PERI.touch_freq_scan_para[sampler_id].touch_freq_drv_ls = ls_drv; + LP_ANA_PERI.touch_freq_scan_para[sampler_id].touch_freq_drv_hs = hs_drv; +} + +/** + * Set the touch internal LDO bias voltage of the sampling frequency + * + * @param sampler_id The sampler index + * @param bias_volt LDO bias voltage + */ +static inline void touch_ll_sampler_set_bias_voltage(uint8_t sampler_id, uint32_t bias_volt) +{ + HAL_ASSERT(sampler_id < SOC_TOUCH_SAMPLER_NUM); + LP_ANA_PERI.touch_freq_scan_para[sampler_id].touch_freq_dbias = bias_volt; +} + +/** + * @brief Set the internal loop capacitance + * Can simulate the touch signal via the internal capacitance + * Need to turn off touch pad + * @param cap The internal capacitance + */ +static inline void touch_ll_set_internal_loop_capacitance(int cap) +{ + bool enable = cap > 0; + LP_ANA_PERI.touch_ana_para.touch_touch_en_cal = enable; + LP_ANA_PERI.touch_ana_para.touch_touch_dcap_cal = enable ? cap : 0; +} + +/************************ Filter register setting ************************/ + +/** + * Force reset benchmark to raw data of touch sensor. + * + * @note If call this API, make sure enable clock gate(`touch_ll_clkgate`) first. + * @param chan_mask touch channel mask + */ +static inline void touch_ll_reset_chan_benchmark(uint32_t chan_mask) +{ + LP_ANA_PERI.touch_clr.touch_channel_clr = chan_mask; +} + +/** + * Set filter mode. The input of the filter is the raw value of touch reading, + * and the output of the filter is involved in the judgment of the touch state. + * + * @param mode Filter mode type. Refer to ``touch_filter_mode_t``. + */ +static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode) +{ + LP_ANA_PERI.touch_filter1.touch_filter_mode = mode; +} + +/** + * Set filter mode. The input to the filter is raw data and the output is the smooth data. + * The smooth data is used to determine the touch status. + * + * @param mode Filter mode type. Refer to ``touch_smooth_mode_t``. + */ +static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode) +{ + LP_ANA_PERI.touch_filter1.touch_smooth_lvl = mode; +} + +/** + * Set debounce count, such as `n`. If the measured values continue to exceed + * the threshold for `n+1` times, it is determined that the touch sensor state changes. + * + * @param dbc_cnt Debounce count value. + */ +static inline void touch_ll_filter_set_debounce(uint32_t dbc_cnt) +{ + LP_ANA_PERI.touch_filter1.touch_debounce_limit = dbc_cnt; +} + +/** + * Set the positive noise threshold coefficient. Higher = More noise resistance. + * The benchmark will update to the new value if the touch data is within (benchmark + active_threshold * pos_coeff) + * + * + * @param pos_noise_thresh Range [-1 ~ 3]. The coefficient is -1: always; 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; + * -1: the benchmark will always update to the new touch data without considering the positive noise threshold + */ +static inline void touch_ll_filter_set_pos_noise_thresh(int pos_noise_thresh) +{ + bool always_update = pos_noise_thresh < 0; + LP_ANA_PERI.touch_filter2.touch_bypass_noise_thres = always_update; + LP_ANA_PERI.touch_filter1.touch_noise_thres = always_update ? 0 : pos_noise_thresh; +} + +/** + * Set the negative noise threshold coefficient. Higher = More noise resistance. + * The benchmark will update to the new value if the touch data is greater than (benchmark - active_threshold * neg_coeff) + * + * @param neg_noise_thresh Range [-2 ~ 3]. The coefficient is -2: never; -1: always; 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; + * -1: the benchmark will always update to the new touch data without considering the negative noise threshold + * -2: the benchmark will never update to the new touch data with negative growth + * @param neg_noise_limit Only when neg_noise_thresh >= 0, if the touch data keep blow the negative threshold for mare than neg_noise_limit ticks, + * the benchmark will still update to the new value. + * It is normally used for updating the benchmark at the first scanning + */ +static inline void touch_ll_filter_set_neg_noise_thresh(int neg_noise_thresh, uint8_t neg_noise_limit) +{ + bool always_update = neg_noise_thresh == -1; + bool stop_update = neg_noise_thresh == -2; + LP_ANA_PERI.touch_filter2.touch_bypass_neg_noise_thres = always_update; + LP_ANA_PERI.touch_filter1.touch_neg_noise_disupdate_baseline_en = stop_update; + LP_ANA_PERI.touch_filter1.touch_neg_noise_thres = always_update || stop_update ? 0 : neg_noise_thresh; + LP_ANA_PERI.touch_filter1.touch_neg_noise_limit = always_update || stop_update ? 5 : neg_noise_limit; // 5 is the default value +} + +/** + * Set the hysteresis value of the active threshold + * While the touch data is greater than active_threshold + hysteresis and last for several ticks, the channel is activated, + * and while the touch data is smaller than active_threshold - hysteresis and last for several ticks, the channel is inactivated + * + * @param hysteresis The hysteresis value of active threshold + */ +static inline void touch_ll_filter_set_active_hysteresis(uint32_t hysteresis) +{ + LP_ANA_PERI.touch_filter1.touch_hysteresis = hysteresis; +} + +/** + * Set jitter filter step size. + * If filter mode is jitter, should set filter step for jitter. + * Range: 0 ~ 15 + * + * @param step The step size of the data change. + */ +static inline void touch_ll_filter_set_jitter_step(uint32_t step) +{ + LP_ANA_PERI.touch_filter1.touch_jitter_step = step; +} + +/** + * Enable or disable touch sensor filter and detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + */ +static inline void touch_ll_filter_enable(bool enable) +{ + LP_ANA_PERI.touch_filter1.touch_filter_en = enable; +} + +/** + * Force the update the benchmark by software + * @note This benchmark will be applied to all enabled channel and all sampling frequency + * + * @param benchmark The benchmark specified by software + */ +static inline void touch_ll_force_update_benchmark(uint32_t benchmark) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_filter3, touch_baseline_sw, benchmark); + LP_ANA_PERI.touch_filter3.touch_update_baseline_sw = 1; + // waiting for update + while (LP_ANA_PERI.touch_filter3.touch_update_baseline_sw); +} + +/************************ Waterproof register setting ************************/ + +/** + * Set touch channel use for guard pad. + * + * @param pad_num Touch sensor channel number. + */ +static inline void touch_ll_waterproof_set_guard_chan(uint32_t pad_num) +{ + LP_ANA_PERI.touch_scan_ctrl2.touch_out_ring = pad_num; +} + +/** + * Enable or disable parameter of waterproof function. + * + * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. + * Guard pad is used to detect the large area of water covering the touch panel. + * Shield pad is used to shield the influence of water droplets covering the touch panel. + * It is generally designed as a grid and is placed around the touch buttons. + */ +static inline void touch_ll_waterproof_enable(bool enable) +{ + LP_ANA_PERI.touch_scan_ctrl1.touch_shield_pad_en = enable; +} + +/** + * Set the shield channel mask + * + * @param mask The channels that set in the mask will be used as shield channel + */ +static inline void touch_ll_waterproof_set_shield_chan_mask(uint32_t mask) +{ + LP_ANA_PERI.touch_mux0.touch_bufsel = (mask & TOUCH_LL_FULL_CHANNEL_MASK); +} + +/** + * Set the touch buff driver for the shield channel. + * + * @param driver_level The driver level of the touch buff + */ +static inline void touch_ll_waterproof_set_shield_driver(touch_pad_shield_driver_t driver_level) +{ + LP_ANA_PERI.touch_ana_para.touch_touch_buf_drv = driver_level; +} + +/************************ Approach register setting ************************/ + +/** + * Set the approach channel to the specific touch channel + * To disable the approach channel, point this pad to `TOUCH_LL_NULL_CHANNEL` + * + * @param aprch_chan approach channel. + * @param touch_num The touch channel that supposed to be used as approach channel + */ +static inline void touch_ll_set_approach_channel(uint8_t aprch_chan, uint32_t touch_num) +{ + switch (aprch_chan) { + case 0: + LP_ANA_PERI.touch_approach.touch_approach_pad0 = touch_num; + break; + case 1: + LP_ANA_PERI.touch_approach.touch_approach_pad1 = touch_num; + break; + case 2: + LP_ANA_PERI.touch_approach.touch_approach_pad2 = touch_num; + break; + default: + // invalid approach channel + abort(); + } +} + +/** + * Set cumulative measurement times for approach channel. + * + * @param sampler_id The sampler index + * @param times The cumulative number of measurement cycles. + */ +static inline void touch_ll_approach_set_measure_times(uint8_t sampler_id, uint32_t times) +{ + switch (sampler_id) { + case 0: + LP_ANA_PERI.touch_approach_work_meas_num.touch_approach_meas_num0 = times; + break; + case 1: + LP_ANA_PERI.touch_approach_work_meas_num.touch_approach_meas_num1 = times; + break; + case 2: + LP_ANA_PERI.touch_approach_work_meas_num.touch_approach_meas_num2 = times; + break; + default: + // invalid sampler_id + abort(); + } +} + +/** + * Read current cumulative measurement times for approach channel. + * + * @param aprch_chan approach channel. + * @param cnt The cumulative number of measurement cycles. + */ +static inline void touch_ll_approach_read_measure_cnt(uint8_t aprch_chan, uint32_t *cnt) +{ + switch (aprch_chan) { + case 0: + *cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, approach_pad0_cnt); + break; + case 1: + *cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, approach_pad1_cnt); + break; + case 2: + *cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, approach_pad2_cnt); + break; + default: // sleep channel + *cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, slp_approach_cnt); + break; + } +} + +/** + * Check if the touch sensor channel is the approach channel. + * + * @param touch_num The touch sensor channel number. + */ +static inline bool touch_ll_is_approach_channel(uint32_t touch_num) +{ + if ((LP_ANA_PERI.touch_approach.touch_approach_pad0 != touch_num) + && (LP_ANA_PERI.touch_approach.touch_approach_pad1 != touch_num) + && (LP_ANA_PERI.touch_approach.touch_approach_pad2 != touch_num)) { + return false; + } else { + return true; + } +} + +/************** sleep channel setting ***********************/ + +/** + * Set touch channel number for sleep channel. + * + * @note Only one touch sensor channel is supported in deep sleep mode. + * @param touch_num Touch sensor channel number. + */ +static inline void touch_ll_sleep_set_channel_num(uint32_t touch_num) +{ + LP_ANA_PERI.touch_slp0.touch_slp_pad = touch_num; +} + +/** + * Get touch channel number for sleep pad. + * + * @note Only one touch sensor channel is supported in deep sleep mode. + * @param touch_num Touch sensor channel number. + */ +static inline void touch_ll_sleep_get_channel_num(uint32_t *touch_num) +{ + *touch_num = (uint32_t)(LP_ANA_PERI.touch_slp0.touch_slp_pad); +} + +/** + * Set the trigger threshold of touch sensor in deep sleep. + * The threshold determines the sensitivity of the touch sensor. + * The threshold is the original value of the trigger state minus the benchmark value. + * + * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep. + */ +static inline void touch_ll_sleep_set_threshold(uint8_t sampler_id, uint32_t touch_thresh) +{ + switch (sampler_id) { + case 0: + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_slp0, touch_slp_th0, touch_thresh); + break; + case 1: + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_slp1, touch_slp_th1, touch_thresh); + break; + case 2: + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_slp1, touch_slp_th2, touch_thresh); + break; + default: + // invalid sampler_id + abort(); + } +} + +/** + * Enable approach function for sleep channel. + */ +static inline void touch_ll_sleep_enable_approach(bool enable) +{ + LP_ANA_PERI.touch_approach.touch_slp_approach_en = enable; +} + +/** + * Get the data of the touch channel according to the types + * + * @param sampler_id The sampler index + * @param type data type + * 0/1: TOUCH_LL_READ_RAW, the raw data of the touch channel + * 2: TOUCH_LL_READ_BENCHMARK, benchmark value of touch channel, + * the benchmark value is the maximum during the first measurement period + * 3: TOUCH_LL_READ_SMOOTH, the smoothed data that obtained by filtering the raw data. + * @param smooth_data pointer to smoothed data + */ +__attribute__((always_inline)) +static inline void touch_ll_sleep_read_chan_data(uint8_t type, uint8_t sampler_id, uint32_t *data) +{ + HAL_ASSERT(type <= TOUCH_LL_READ_SMOOTH); + LP_ANA_PERI.touch_mux0.touch_freq_sel = sampler_id + 1; + LP_ANA_PERI.touch_mux0.touch_data_sel = type; + *data = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.slp_ch_data, slp_data); +} + +/** + * @brief Reset the benchmark of the sleep channel + * + */ +static inline void touch_ll_sleep_reset_benchmark(void) +{ + LP_ANA_PERI.touch_slp0.touch_slp_channel_clr = 1; +} + +/** + * Read debounce of touch sensor for sleep channel. + * + * @param debounce Pointer to accept touch sensor debounce value. + */ +static inline void touch_ll_sleep_read_debounce(uint32_t *debounce) +{ + *debounce = LP_TOUCH.slp_ch_data.slp_debounce_cnt; +} + +/** + * Read approach count of touch sensor for sleep channel. + * @param approach_cnt Pointer to accept touch sensor approach count value. + */ +static inline void touch_ll_sleep_read_approach_cnt(uint32_t *approach_cnt) +{ + *approach_cnt = HAL_FORCE_READ_U32_REG_FIELD(LP_TOUCH.aprch_ch_data, slp_approach_cnt); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 6efd8531f63..e56a330063d 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -315,34 +315,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // HP_SYS_CLKRST.hp_rst_en1 is a shared register, so this function must be used in an atomic way #define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__) -/** - * @brief Configure the UART core reset. - * - * @param hw Beginning address of the peripheral registers. - * @param core_rst_en True to enable the core reset, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) -{ - if ((hw) == &UART0) { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_core = core_rst_en; - } else if ((hw) == &UART1) { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart1_core = core_rst_en; - } else if ((hw) == &UART2) { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_core = core_rst_en; - } else if ((hw) == &UART3) { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart3_core = core_rst_en; - } else if ((hw) == &UART4) { - HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_core = core_rst_en; - } else { - // Not going to implement LP_UART reset in this function, it will have its own LL function - abort(); - } -} -// HP_SYS_CLKRST.hp_rst_en1 is a shared register, so this function must be used in an atomic way -#define uart_ll_set_reset_core(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_reset_core(__VA_ARGS__) - /** * @brief Enable the UART clock. * diff --git a/components/hal/esp32s2/include/hal/brownout_ll.h b/components/hal/esp32s2/include/hal/brownout_ll.h index 6a8b7cfe579..fc13a382e9e 100644 --- a/components/hal/esp32s2/include/hal/brownout_ll.h +++ b/components/hal/esp32s2/include/hal/brownout_ll.h @@ -116,6 +116,16 @@ static inline void brownout_ll_intr_clear(void) RTCCNTL.int_clr.rtc_brown_out = 1; } +/** + * @brief Clear BOD internal count. + */ +static inline void brownout_ll_clear_count(void) +{ + RTCCNTL.brown_out.cnt_clr = 1; + RTCCNTL.brown_out.cnt_clr = 0; +} + + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/clk_gate_ll.h b/components/hal/esp32s2/include/hal/clk_gate_ll.h index 32ee2c457b7..82725b9c591 100644 --- a/components/hal/esp32s2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s2/include/hal/clk_gate_ll.h @@ -243,16 +243,14 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk(void) { DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk(void) { DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); } static inline void periph_ll_reset(periph_module_t periph) diff --git a/components/hal/esp32s2/include/hal/spimem_flash_ll.h b/components/hal/esp32s2/include/hal/spimem_flash_ll.h index 196079e7971..ea0ca5da4c3 100644 --- a/components/hal/esp32s2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s2/include/hal/spimem_flash_ll.h @@ -217,6 +217,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_waiti_ctrl.waiti_en = auto_waiti; // enable auto wait-idle function. } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + // Not supported on this chip. +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32s2/include/hal/systimer_ll.h b/components/hal/esp32s2/include/hal/systimer_ll.h index 755d349bb6d..dd35801bc56 100644 --- a/components/hal/esp32s2/include/hal/systimer_ll.h +++ b/components/hal/esp32s2/include/hal/systimer_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "soc/systimer_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/system_reg.h" #include "hal/assert.h" #ifdef __cplusplus @@ -35,6 +36,38 @@ static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) return SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + uint32_t reg_val = READ_PERI_REG(DPORT_PERIP_CLK_EN0_REG); + reg_val &= ~DPORT_SYSTIMER_CLK_EN_M; + reg_val |= enable << DPORT_SYSTIMER_CLK_EN_S; + WRITE_PERI_REG(DPORT_PERIP_CLK_EN0_REG, reg_val); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, DPORT_SYSTIMER_RST_M); + WRITE_PERI_REG(DPORT_PERIP_RST_EN0_REG, 0); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /******************* Counter *************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) diff --git a/components/hal/esp32s2/include/hal/temperature_sensor_ll.h b/components/hal/esp32s2/include/hal/temperature_sensor_ll.h index 86dcd5dbefb..ca444f528b5 100644 --- a/components/hal/esp32s2/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32s2/include/hal/temperature_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,6 +21,7 @@ #include "soc/rtc_cntl_reg.h" #include "soc/sens_struct.h" #include "hal/temperature_sensor_types.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -82,7 +83,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) while (!SENS.sar_tctrl.tsens_ready) { } SENS.sar_tctrl.tsens_dump_out = 0; - return SENS.sar_tctrl.tsens_out; + return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_tctrl, tsens_out); } /** @@ -106,7 +107,7 @@ static inline uint32_t temperature_sensor_ll_get_offset(void) */ static inline uint32_t temperature_sensor_ll_get_clk_div(void) { - return SENS.sar_tctrl.tsens_clk_div; + return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_tctrl, tsens_clk_div); } /** @@ -119,7 +120,7 @@ static inline uint32_t temperature_sensor_ll_get_clk_div(void) */ static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) { - SENS.sar_tctrl.tsens_clk_div = clk_div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_clk_div, clk_div); } #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/touch_sensor_ll.h b/components/hal/esp32s2/include/hal/touch_sensor_ll.h index 62072a5856b..656b79099f3 100644 --- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,6 +34,8 @@ extern "C" { #define TOUCH_LL_TIMER_FORCE_DONE 0x3 #define TOUCH_LL_TIMER_DONE 0x0 +#define TOUCH_LL_PAD_MEASURE_WAIT_MAX (0xFF) /*! +#include "esp_attr.h" #include "soc/soc.h" #include "soc/system_reg.h" #include "soc/usb_wrap_struct.h" @@ -22,8 +23,6 @@ extern "C" { */ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw) { - //Enable internal PHY - hw->otg_conf.pad_enable = 1; hw->otg_conf.phy_sel = 0; } @@ -59,6 +58,16 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool hw->otg_conf.val = conf.val; } +/** + * @brief Enable the internal PHY control to D+/D- pad + * @param hw Start address of the USB Wrap registers + * @param pad_en Enable the PHY control to D+/D- pad + */ +static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en) +{ + hw->otg_conf.pad_enable = pad_en; +} + /** * @brief Enable the internal PHY's test mode * @@ -79,6 +88,30 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en) } } +/** + * Enable the bus clock for USB Wrap module + * @param clk_en True if enable the clock of USB Wrap module + */ +FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en) +{ + REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en); +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the USB Wrap module + */ +FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void) +{ + REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1); + REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0); +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_reset_register(__VA_ARGS__) + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/touch_sensor_hal.c b/components/hal/esp32s2/touch_sensor_hal.c index 520a5cb89ef..04deb1c9252 100644 --- a/components/hal/esp32s2/touch_sensor_hal.c +++ b/components/hal/esp32s2/touch_sensor_hal.c @@ -142,7 +142,7 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable) { if (enable) { touch_ll_sleep_set_channel_num(pad_num); - touch_ll_sleep_set_threshold(SOC_TOUCH_PAD_THRESHOLD_MAX); + touch_ll_sleep_set_threshold(TOUCH_PAD_THRESHOLD_MAX); touch_ll_sleep_reset_benchmark(); } else { touch_ll_sleep_set_channel_num(TOUCH_PAD_NUM0); diff --git a/components/hal/esp32s3/include/hal/brownout_ll.h b/components/hal/esp32s3/include/hal/brownout_ll.h index 37a2020c12f..4cc8d95f670 100644 --- a/components/hal/esp32s3/include/hal/brownout_ll.h +++ b/components/hal/esp32s3/include/hal/brownout_ll.h @@ -115,6 +115,15 @@ static inline void brownout_ll_intr_clear(void) RTCCNTL.int_clr.rtc_brown_out = 1; } +/** + * @brief Clear BOD internal count. + */ +static inline void brownout_ll_clear_count(void) +{ + RTCCNTL.brown_out.cnt_clr = 1; + RTCCNTL.brown_out.cnt_clr = 0; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/clk_gate_ll.h b/components/hal/esp32s3/include/hal/clk_gate_ll.h index dfc15c868be..0d43fd4bb85 100644 --- a/components/hal/esp32s3/include/hal/clk_gate_ll.h +++ b/components/hal/esp32s3/include/hal/clk_gate_ll.h @@ -264,16 +264,14 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk(void) { DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk(void) { DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); } static inline void periph_ll_reset(periph_module_t periph) diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index ff923dd82fb..558939e88bb 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -102,9 +102,13 @@ static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable) * @brief Get DMA RX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->channel[channel].in.int_st.val; + if (raw) { + return dev->channel[channel].in.int_raw.val; + } else { + return dev->channel[channel].in.int_st.val; + } } /** @@ -366,9 +370,13 @@ static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t c * @brief Get DMA TX channel interrupt status word */ __attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) { - return dev->channel[channel].out.int_st.val; + if (raw) { + return dev->channel[channel].out.int_raw.val; + } else { + return dev->channel[channel].out.int_st.val; + } } /** diff --git a/components/hal/esp32s3/include/hal/lcd_ll.h b/components/hal/esp32s3/include/hal/lcd_ll.h index 1be0b4d5099..284d9c32586 100644 --- a/components/hal/esp32s3/include/hal/lcd_ll.h +++ b/components/hal/esp32s3/include/hal/lcd_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,6 +29,45 @@ extern "C" { #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width #define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width +/** + * @brief LCD data byte swizzle mode + */ +typedef enum { + LCD_LL_SWIZZLE_AB2BA, /*!< AB -> BA */ +} lcd_ll_swizzle_mode_t; + +/** + * @brief Enable the bus clock for LCD module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void lcd_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + SYSTEM.perip_clk_en1.lcd_cam_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define lcd_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the LCD module + * + * @param group_id Group ID + */ +static inline void lcd_ll_reset_register(int group_id) +{ + (void)group_id; + SYSTEM.perip_rst_en1.lcd_cam_rst = 0x01; + SYSTEM.perip_rst_en1.lcd_cam_rst = 0x00; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define lcd_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_reset_register(__VA_ARGS__) + /** * @brief Enable clock gating * @@ -326,15 +365,35 @@ static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev, uint32_t fk_cycle } /** - * @brief Set data line width + * @brief Set data read stride, i.e., number of bytes the LCD reads from the DMA in each step * * @param dev LCD register base address - * @param width data line width (8 or 16) + * @param stride data stride size */ -static inline void lcd_ll_set_data_width(lcd_cam_dev_t *dev, uint32_t width) +static inline void lcd_ll_set_dma_read_stride(lcd_cam_dev_t *dev, uint32_t stride) { - HAL_ASSERT(width == 8 || width == 16); - dev->lcd_user.lcd_2byte_en = (width == 16); + switch (stride) { + case 8: + dev->lcd_user.lcd_2byte_en = 0; + break; + case 16: + dev->lcd_user.lcd_2byte_en = 1; + break; + default: + abort(); + break; + } +} + +/** + * @brief Set the wire width of LCD output + * + * @param dev LCD register base address + * @param width LCD output wire width + */ +static inline void lcd_ll_set_data_wire_width(lcd_cam_dev_t *dev, uint32_t width) +{ + // data line width is same as data stride that set in `lcd_ll_set_dma_read_stride` } /** @@ -386,36 +445,69 @@ static inline void lcd_ll_reset(lcd_cam_dev_t *dev) /** * @brief Whether to reverse the data bit order * + * @note It acts before the YUV-RGB converter + * * @param dev LCD register base address * @param en True to reverse, False to not reverse */ __attribute__((always_inline)) -static inline void lcd_ll_reverse_bit_order(lcd_cam_dev_t *dev, bool en) +static inline void lcd_ll_reverse_dma_data_bit_order(lcd_cam_dev_t *dev, bool en) { - // whether to change LCD_DATA_out[N:0] to LCD_DATA_out[0:N] dev->lcd_user.lcd_bit_order = en; } +/** + * @brief Whether to reverse the output data bit order + * + * @note ESP32S3 doesn't support to reverse the data bit after the YUV-RGB converter + * + * @param dev LCD register base address + * @param en True to reverse, False to not reverse + */ +static inline void lcd_ll_reverse_wire_bit_order(lcd_cam_dev_t *dev, bool en) +{ + (void)dev; + (void)en; +} + /** * @brief Whether to swap adjacent two bytes * + * @note This acts before the YUV-RGB converter, mainly to change the data endian. + * {B1,B0},{B3,B2} => {B0,B1}{B2,B3} + * * @param dev LCD register base address - * @param width Bus width * @param en True to swap the byte order, False to not swap */ __attribute__((always_inline)) -static inline void lcd_ll_swap_byte_order(lcd_cam_dev_t *dev, uint32_t width, bool en) +static inline void lcd_ll_swap_dma_data_byte_order(lcd_cam_dev_t *dev, bool en) { - HAL_ASSERT(width == 8 || width == 16); - if (width == 8) { - // {B0}{B1}{B2}{B3} => {B1}{B0}{B3}{B2} - dev->lcd_user.lcd_8bits_order = en; - dev->lcd_user.lcd_byte_order = 0; - } else if (width == 16) { - // {B1,B0},{B3,B2} => {B0,B1}{B2,B3} - dev->lcd_user.lcd_byte_order = en; - dev->lcd_user.lcd_8bits_order = 0; - } + dev->lcd_user.lcd_byte_order = en; +} + +/** + * @brief Enable the byte swizzle + * + * @note The swizzle module acts after the YUV-RGB converter, used to reorder the data bytes before the data wire + * + * @param dev LCD register base address + * @param en True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void lcd_ll_enable_swizzle(lcd_cam_dev_t *dev, bool en) +{ + dev->lcd_user.lcd_8bits_order = en; +} + +/** + * @brief Set data byte swizzle mode + * + * @param dev LCD register base address + * @param mode Swizzle mode + */ +static inline void lcd_ll_set_swizzle_mode(lcd_cam_dev_t *dev, lcd_ll_swizzle_mode_t mode) +{ + HAL_ASSERT(mode == LCD_LL_SWIZZLE_AB2BA); } /** @@ -652,35 +744,6 @@ static inline volatile void *lcd_ll_get_interrupt_status_reg(lcd_cam_dev_t *dev) return &dev->lc_dma_int_st; } -/** - * @brief Enable or disable the bus clock for the LCD module - * - * @param set_bit True to set bit, false to clear bit - */ -static inline void lcd_ll_enable_bus_clock(int group_id, bool enable) -{ - (void)group_id; - SYSTEM.perip_clk_en1.lcd_cam_clk_en = enable; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define lcd_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_enable_bus_clock(__VA_ARGS__) - -/** - * @brief Reset the LCD module - */ -static inline void lcd_ll_reset_register(int group_id) -{ - (void)group_id; - SYSTEM.perip_rst_en1.lcd_cam_rst = 0x01; - SYSTEM.perip_rst_en1.lcd_cam_rst = 0x00; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance -#define lcd_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; lcd_ll_reset_register(__VA_ARGS__) - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/spimem_flash_ll.h b/components/hal/esp32s3/include/hal/spimem_flash_ll.h index 70c809e1a3e..eee9d0851db 100644 --- a/components/hal/esp32s3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s3/include/hal/spimem_flash_ll.h @@ -274,6 +274,24 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool dev->flash_sus_cmd.flash_pes_wait_en = 1; } +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. This function is only used in quad flash + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + if (extra_dummy > 0) { + dev->flash_waiti_ctrl.waiti_dummy_cyclelen = extra_dummy - 1; + dev->flash_waiti_ctrl.waiti_dummy = 1; + } else { + dev->flash_waiti_ctrl.waiti_dummy = 0; + } +} + /** * Return the suspend status of erase or program operations. * diff --git a/components/hal/esp32s3/include/hal/systimer_ll.h b/components/hal/esp32s3/include/hal/systimer_ll.h index 676ff1d9f9c..36fe0fa1175 100644 --- a/components/hal/esp32s3/include/hal/systimer_ll.h +++ b/components/hal/esp32s3/include/hal/systimer_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "soc/systimer_struct.h" #include "soc/clk_tree_defs.h" +#include "soc/system_struct.h" #include "hal/assert.h" #ifdef __cplusplus @@ -35,6 +36,35 @@ static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) return SYSTIMER_CLK_SRC_XTAL; } +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + SYSTEM.perip_clk_en0.systimer_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + SYSTEM.perip_rst_en0.systimer_rst = 1; + SYSTEM.perip_rst_en0.systimer_rst = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + /******************* Counter *************************/ __attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) diff --git a/components/hal/esp32s3/include/hal/temperature_sensor_ll.h b/components/hal/esp32s3/include/hal/temperature_sensor_ll.h index cc14ce96e5e..98baca81bba 100644 --- a/components/hal/esp32s3/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32s3/include/hal/temperature_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,6 +21,7 @@ #include "soc/rtc_cntl_reg.h" #include "soc/sens_struct.h" #include "hal/temperature_sensor_types.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -82,7 +83,7 @@ static inline uint32_t temperature_sensor_ll_get_raw_value(void) while (!SENS.sar_tctrl.tsens_ready) { } SENS.sar_tctrl.tsens_dump_out = 0; - return SENS.sar_tctrl.tsens_out; + return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_tctrl, tsens_out); } /** @@ -106,7 +107,7 @@ static inline uint32_t temperature_sensor_ll_get_offset(void) */ static inline uint32_t temperature_sensor_ll_get_clk_div(void) { - return SENS.sar_tctrl.tsens_clk_div; + return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_tctrl, tsens_clk_div); } /** @@ -119,7 +120,7 @@ static inline uint32_t temperature_sensor_ll_get_clk_div(void) */ static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) { - SENS.sar_tctrl.tsens_clk_div = clk_div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_clk_div, clk_div); } #ifdef __cplusplus diff --git a/components/hal/esp32s3/include/hal/touch_sensor_ll.h b/components/hal/esp32s3/include/hal/touch_sensor_ll.h index 5803b0a2c9e..0cb69edc541 100644 --- a/components/hal/esp32s3/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32s3/include/hal/touch_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,6 +34,8 @@ extern "C" { #define TOUCH_LL_TIMER_FORCE_DONE 0x3 #define TOUCH_LL_TIMER_DONE 0x0 +#define TOUCH_LL_PAD_MEASURE_WAIT_MAX (0xFF) /*!clk_conf.rst_core = core_rst_en; -} - /** * @brief Set the UART source clock. * diff --git a/components/hal/esp32s3/include/hal/usb_phy_ll.h b/components/hal/esp32s3/include/hal/usb_phy_ll.h index f9685ea36ac..0045bc13a44 100644 --- a/components/hal/esp32s3/include/hal/usb_phy_ll.h +++ b/components/hal/esp32s3/include/hal/usb_phy_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,8 +7,9 @@ #pragma once #include +#include "esp_attr.h" #include "soc/soc.h" -#include "soc/system_reg.h" +#include "soc/system_struct.h" #include "soc/usb_wrap_struct.h" #include "soc/rtc_cntl_struct.h" #include "soc/usb_serial_jtag_struct.h" @@ -24,7 +25,6 @@ extern "C" { */ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw) { - hw->otg_conf.pad_enable = 1; // USB_OTG use internal PHY hw->otg_conf.phy_sel = 0; // phy_sel is controlled by the following register value @@ -107,6 +107,16 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool hw->otg_conf.val = conf.val; } +/** + * @brief Enable the internal PHY control to D+/D- pad + * @param hw Start address of the USB Wrap registers + * @param pad_en Enable the PHY control to D+/D- pad + */ +static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en) +{ + hw->otg_conf.pad_enable = pad_en; +} + /** * @brief Enable the internal PHY's test mode * @@ -127,6 +137,30 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en) } } +/** + * Enable the bus clock for USB Wrap module + * @param clk_en True if enable the clock of USB Wrap module + */ +FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en) +{ + SYSTEM.perip_clk_en0.usb_clk_en = clk_en; +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the USB Wrap module + */ +FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void) +{ + SYSTEM.perip_rst_en0.usb_rst = 1; + SYSTEM.perip_rst_en0.usb_rst = 0; +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_reset_register(__VA_ARGS__) + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h index 3c0053385c8..ac7c8491208 100644 --- a/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,9 @@ // The LL layer of the USB-serial-jtag controller #pragma once +#include +#include "esp_attr.h" +#include "soc/system_struct.h" #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" @@ -158,6 +161,15 @@ static inline int usb_serial_jtag_ll_txfifo_writable(void) * @brief Flushes the TX buffer, that is, make it available for the * host to pick up. * + * @note When fifo is full (with 64 byte), HW will flush the buffer automatically, + * if this function is called directly after, this effectively turns into a + * no-op. Because a 64-byte packet will be interpreted as a not-complete USB + * transaction, you need to transfer either more data or a zero-length packet + * for the data to actually end up at the program listening to the CDC-ACM + * serial port. To send a zero-length packet, call + * usb_serial_jtag_ll_txfifo_flush() again when + * usb_serial_jtag_ll_txfifo_writable() returns true. + * * @return na */ static inline void usb_serial_jtag_ll_txfifo_flush(void) @@ -165,6 +177,64 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void) USB_SERIAL_JTAG.ep1_conf.wr_done=1; } +/** + * @brief Disable usb serial jtag pad during light sleep to avoid current leakage + * + * @return Initial configuration of usb serial jtag pad enable before light sleep + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void) +{ + bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable; + + // Disable USB pad function + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + + return pad_enabled; +} + +/** + * @brief Enable the internal USJ PHY control to D+/D- pad + * + * @param enable_pad Enable the USJ PHY control to D+/D- pad + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad) +{ + USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad; +} + +/** + * @brief Enable the bus clock for USB Serial_JTAG module + * @param clk_en True if enable the clock of USB Serial_JTAG module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) +{ + SYSTEM.perip_clk_en1.usb_device_clk_en = clk_en; +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the usb serial jtag module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void) +{ + SYSTEM.perip_rst_en1.usb_device_rst = 1; + SYSTEM.perip_rst_en1.usb_device_rst = 0; +} + +// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way +#define usb_serial_jtag_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_reset_register(__VA_ARGS__) + +/** + * Get the enable status USB Serial_JTAG module + * + * @return Return true if USB Serial_JTAG module is enabled + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void) +{ + return (SYSTEM.perip_clk_en1.usb_device_clk_en && !SYSTEM.perip_rst_en1.usb_device_rst); +} #ifdef __cplusplus } diff --git a/components/hal/esp32s3/rtc_cntl_hal.c b/components/hal/esp32s3/rtc_cntl_hal.c index 27d3c605bec..94c74908b7c 100644 --- a/components/hal/esp32s3/rtc_cntl_hal.c +++ b/components/hal/esp32s3/rtc_cntl_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,6 +68,14 @@ void rtc_cntl_hal_enable_cpu_retention(void *addr) ); rtc_cntl_ll_enable_cpu_retention_clock(); rtc_cntl_ll_enable_cpu_retention(); +#if SOC_PM_SUPPORT_TAGMEM_PD + if (!retent->tagmem.dcache.enable) { + // Here we only need to care for the safety of the PSRAM data in the DCache. + // Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be + // modified in the sleep process code after now, so it is safe to writeback here. + Cache_WriteBack_All(); + } +#endif } } } diff --git a/components/hal/esp32s3/touch_sensor_hal.c b/components/hal/esp32s3/touch_sensor_hal.c index 6ec7fc73083..9b92bd2bc36 100644 --- a/components/hal/esp32s3/touch_sensor_hal.c +++ b/components/hal/esp32s3/touch_sensor_hal.c @@ -142,7 +142,7 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable) { if (enable) { touch_ll_sleep_set_channel_num(pad_num); - touch_ll_sleep_set_threshold(SOC_TOUCH_PAD_THRESHOLD_MAX); + touch_ll_sleep_set_threshold(TOUCH_PAD_THRESHOLD_MAX); touch_ll_sleep_reset_benchmark(); } else { touch_ll_sleep_set_channel_num(TOUCH_PAD_NUM0); diff --git a/components/hal/gdma_hal_ahb_v1.c b/components/hal/gdma_hal_ahb_v1.c index 4c8cf98b6a9..6964b987905 100644 --- a/components/hal/gdma_hal_ahb_v1.c +++ b/components/hal/gdma_hal_ahb_v1.c @@ -131,12 +131,12 @@ void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_ } } -uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir) +uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw) { if (dir == GDMA_CHANNEL_DIRECTION_RX) { - return gdma_ll_rx_get_interrupt_status(hal->dev, chan_id); + return gdma_ll_rx_get_interrupt_status(hal->dev, chan_id, raw); } else { - return gdma_ll_tx_get_interrupt_status(hal->dev, chan_id); + return gdma_ll_tx_get_interrupt_status(hal->dev, chan_id, raw); } } @@ -162,6 +162,17 @@ uint32_t gdma_ahb_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd } } +#if SOC_GDMA_SUPPORT_ETM +void gdma_ahb_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis) +{ + if (dir == GDMA_CHANNEL_DIRECTION_RX) { + gdma_ll_rx_enable_etm_task(hal->dev, chan_id, en_or_dis); + } else { + gdma_ll_tx_enable_etm_task(hal->dev, chan_id, en_or_dis); + } +} +#endif // SOC_GDMA_SUPPORT_ETM + void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config) { hal->dev = GDMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID); @@ -179,6 +190,9 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config) hal->read_intr_status = gdma_ahb_hal_read_intr_status; hal->get_intr_status_reg = gdma_ahb_hal_get_intr_status_reg; hal->get_eof_desc_addr = gdma_ahb_hal_get_eof_desc_addr; +#if SOC_GDMA_SUPPORT_ETM + hal->enable_etm_task = gdma_ahb_hal_enable_etm_task; +#endif #if SOC_AHB_GDMA_SUPPORT_PSRAM hal->set_ext_mem_align = gdma_ahb_hal_set_ext_mem_align; #endif // SOC_AHB_GDMA_SUPPORT_PSRAM diff --git a/components/hal/gdma_hal_ahb_v2.c b/components/hal/gdma_hal_ahb_v2.c index 5ba655d9633..2b4f7a9e90f 100644 --- a/components/hal/gdma_hal_ahb_v2.c +++ b/components/hal/gdma_hal_ahb_v2.c @@ -120,12 +120,12 @@ void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_ } } -uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir) +uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw) { if (dir == GDMA_CHANNEL_DIRECTION_RX) { - return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id); + return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id, raw); } else { - return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id); + return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id, raw); } } @@ -207,6 +207,17 @@ uint32_t gdma_ahb_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_ } #endif // SOC_GDMA_SUPPORT_CRC +#if SOC_GDMA_SUPPORT_ETM +void gdma_ahb_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis) +{ + if (dir == GDMA_CHANNEL_DIRECTION_RX) { + ahb_dma_ll_rx_enable_etm_task(hal->ahb_dma_dev, chan_id, en_or_dis); + } else { + ahb_dma_ll_tx_enable_etm_task(hal->ahb_dma_dev, chan_id, en_or_dis); + } +} +#endif // SOC_GDMA_SUPPORT_ETM + void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config) { hal->ahb_dma_dev = AHB_DMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID); @@ -230,4 +241,7 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config) hal->set_crc_poly = gdma_ahb_hal_set_crc_poly; hal->get_crc_result = gdma_ahb_hal_get_crc_result; #endif // SOC_GDMA_SUPPORT_CRC +#if SOC_GDMA_SUPPORT_ETM + hal->enable_etm_task = gdma_ahb_hal_enable_etm_task; +#endif // SOC_GDMA_SUPPORT_ETM } diff --git a/components/hal/gdma_hal_axi.c b/components/hal/gdma_hal_axi.c index ce22fb2f010..67e3aeae404 100644 --- a/components/hal/gdma_hal_axi.c +++ b/components/hal/gdma_hal_axi.c @@ -120,12 +120,12 @@ void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_ } } -uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir) +uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw) { if (dir == GDMA_CHANNEL_DIRECTION_RX) { - return axi_dma_ll_rx_get_interrupt_status(hal->axi_dma_dev, chan_id); + return axi_dma_ll_rx_get_interrupt_status(hal->axi_dma_dev, chan_id, raw); } else { - return axi_dma_ll_tx_get_interrupt_status(hal->axi_dma_dev, chan_id); + return axi_dma_ll_tx_get_interrupt_status(hal->axi_dma_dev, chan_id, raw); } } @@ -207,6 +207,17 @@ uint32_t gdma_axi_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_ } #endif // SOC_GDMA_SUPPORT_CRC +#if SOC_GDMA_SUPPORT_ETM +void gdma_axi_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis) +{ + if (dir == GDMA_CHANNEL_DIRECTION_RX) { + axi_dma_ll_rx_enable_etm_task(hal->axi_dma_dev, chan_id, en_or_dis); + } else { + axi_dma_ll_tx_enable_etm_task(hal->axi_dma_dev, chan_id, en_or_dis); + } +} +#endif // SOC_GDMA_SUPPORT_ETM + void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config) { hal->axi_dma_dev = AXI_DMA_LL_GET_HW(config->group_id - GDMA_LL_AXI_GROUP_START_ID); @@ -230,4 +241,7 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config) hal->set_crc_poly = gdma_axi_hal_set_crc_poly; hal->get_crc_result = gdma_axi_hal_get_crc_result; #endif // SOC_GDMA_SUPPORT_CRC +#if SOC_GDMA_SUPPORT_ETM + hal->enable_etm_task = gdma_axi_hal_enable_etm_task; +#endif // SOC_GDMA_SUPPORT_ETM } diff --git a/components/hal/gdma_hal_top.c b/components/hal/gdma_hal_top.c index 2e01d3e9ed3..e3c882b2a23 100644 --- a/components/hal/gdma_hal_top.c +++ b/components/hal/gdma_hal_top.c @@ -75,9 +75,9 @@ void gdma_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_dire hal->clear_intr(hal, chan_id, dir, intr_event_mask); } -uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir) +uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw) { - return hal->read_intr_status(hal, chan_id, dir); + return hal->read_intr_status(hal, chan_id, dir, raw); } uint32_t gdma_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir) @@ -106,3 +106,10 @@ uint32_t gdma_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_chan return hal->get_crc_result(hal, chan_id, dir); } #endif // SOC_GDMA_SUPPORT_CRC + +#if SOC_GDMA_SUPPORT_ETM +void gdma_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis) +{ + hal->enable_etm_task(hal, chan_id, dir, en_or_dis); +} +#endif // SOC_GDMA_SUPPORT_ETM diff --git a/components/hal/i2c_hal.c b/components/hal/i2c_hal.c index 2b1248f622a..92d64091c54 100644 --- a/components/hal/i2c_hal.c +++ b/components/hal/i2c_hal.c @@ -75,3 +75,9 @@ void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t * i2c_ll_set_sda_timing(hal->dev, timing_config->sda_sample, timing_config->sda_hold); i2c_ll_set_tout(hal->dev, timing_config->timeout); } + +void i2c_hal_master_trans_start(i2c_hal_context_t *hal) +{ + i2c_ll_update(hal->dev); + i2c_ll_master_trans_start(hal->dev); +} diff --git a/components/hal/i2c_hal_iram.c b/components/hal/i2c_hal_iram.c index f495de55952..f7128a64b57 100644 --- a/components/hal/i2c_hal_iram.c +++ b/components/hal/i2c_hal_iram.c @@ -1,17 +1,11 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/i2c_hal.h" -void i2c_hal_master_trans_start(i2c_hal_context_t *hal) -{ - i2c_ll_update(hal->dev); - i2c_ll_master_trans_start(hal->dev); -} - //////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// /////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h index 5ccd6b4ad3d..36f43238499 100644 --- a/components/hal/include/hal/color_types.h +++ b/components/hal/include/hal/color_types.h @@ -42,6 +42,7 @@ typedef enum { */ typedef enum { COLOR_PIXEL_RGB888, ///< 24 bits, 8 bits per R/G/B value + COLOR_PIXEL_RGB666, ///< 18 bits, 6 bits per R/G/B value COLOR_PIXEL_RGB565, ///< 16 bits, 5 bits per R/B value, 6 bits for G value } color_pixel_rgb_format_t; @@ -92,7 +93,7 @@ typedef union { Color Conversion ---------------------------------------------------------------*/ /** - * @brief LCD color range + * @brief Color range * @note The difference between a full range color and a limited range color is * the amount of shades of black and white that they can display. */ diff --git a/components/hal/include/hal/dw_gdma_hal.h b/components/hal/include/hal/dw_gdma_hal.h index fa030c46eaf..71c44d825bd 100644 --- a/components/hal/include/hal/dw_gdma_hal.h +++ b/components/hal/include/hal/dw_gdma_hal.h @@ -41,6 +41,13 @@ typedef struct { */ void dw_gdma_hal_init(dw_gdma_hal_context_t *hal, const dw_gdma_hal_config_t *config); +/** + * @brief DW_GDMA HAL driver deinitialization + * + * @param hal Pointer to the HAL driver context + */ +void dw_gdma_hal_deinit(dw_gdma_hal_context_t *hal); + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/dw_gdma_types.h b/components/hal/include/hal/dw_gdma_types.h new file mode 100644 index 00000000000..1a1bea8a58b --- /dev/null +++ b/components/hal/include/hal/dw_gdma_types.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief DMA block transfer type + */ +typedef enum { + DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS, /*!< Contiguous buffer address */ + DW_GDMA_BLOCK_TRANSFER_RELOAD, /*!< Reload transfer configuration automatically */ + DW_GDMA_BLOCK_TRANSFER_SHADOW, /*!< Shadow register */ + DW_GDMA_BLOCK_TRANSFER_LIST, /*!< Link list */ +} dw_gdma_block_transfer_type_t; + +/** + * @brief Flow control type + */ +typedef enum { + DW_GDMA_FLOW_CTRL_SELF, /*!< Flow controller is the DMA engine itself */ + DW_GDMA_FLOW_CTRL_SRC, /*!< Flow controller is the source peripheral */ + DW_GDMA_FLOW_CTRL_DST, /*!< Flow controller is the destination peripheral */ +} dw_gdma_flow_controller_t; + +/** + * @brief Handshake interface type + */ +typedef enum { + DW_GDMA_HANDSHAKE_HW, /*!< Transaction requests are initiated by hardware */ + DW_GDMA_HANDSHAKE_SW, /*!< Transaction requests are initiated by software */ +} dw_gdma_handshake_type_t; + +/** + * @brief Role of the DMA source/destination + */ +typedef enum { + DW_GDMA_ROLE_MEM, /*!< Target is a plain memory which is accessible by the DMA */ + DW_GDMA_ROLE_PERIPH_DSI, /*!< Target is FIFO memory of peripheral: DSI */ + DW_GDMA_ROLE_PERIPH_CSI, /*!< Target is FIFO memory of peripheral: CSI */ + DW_GDMA_ROLE_PERIPH_ISP, /*!< Target is FIFO memory of peripheral: ISP */ +} dw_gdma_role_t; + +/** + * @brief Channel lock level + */ +typedef enum { + DW_GDMA_LOCK_LEVEL_FULL_TRANS, /*!< Lock over complete DMA transfer */ + DW_GDMA_LOCK_LEVEL_BLOCK_TRANS, /*!< Lock over DMA block transfer */ +} dw_gdma_lock_level_t; + +/** + * @brief DW_GDMA transfer width + */ +typedef enum { + DW_GDMA_TRANS_WIDTH_8, /*!< Data transfer width: 8 bits */ + DW_GDMA_TRANS_WIDTH_16, /*!< Data transfer width: 16 bits */ + DW_GDMA_TRANS_WIDTH_32, /*!< Data transfer width: 32 bits */ + DW_GDMA_TRANS_WIDTH_64, /*!< Data transfer width: 64 bits */ + DW_GDMA_TRANS_WIDTH_128, /*!< Data transfer width: 128 bits */ + DW_GDMA_TRANS_WIDTH_256, /*!< Data transfer width: 256 bits */ + DW_GDMA_TRANS_WIDTH_512, /*!< Data transfer width: 512 bits */ +} dw_gdma_transfer_width_t; + +/** + * @brief DW_GDMA burst mode + */ +typedef enum { + DW_GDMA_BURST_MODE_INCREMENT, /*!< The address is increased after each transfer */ + DW_GDMA_BURST_MODE_FIXED, /*!< The address remains the same after each transfer */ +} dw_gdma_burst_mode_t; + +/** + * @brief Number of data items that are contained in one burst transaction + * + * @note One item's bit width is set by `dw_gdma_transfer_width_t` + */ +typedef enum { + DW_GDMA_BURST_ITEMS_1, /*!< 1 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_4, /*!< 4 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_8, /*!< 8 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_16, /*!< 16 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_32, /*!< 32 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_64, /*!< 64 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_128, /*!< 128 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_256, /*!< 256 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_512, /*!< 512 data items in a burst transaction */ + DW_GDMA_BURST_ITEMS_1024, /*!< 1024 data items in a burst transaction */ +} dw_gdma_burst_items_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/ecdsa_hal.h b/components/hal/include/hal/ecdsa_hal.h index 9ce048f9e3f..97981600196 100644 --- a/components/hal/include/hal/ecdsa_hal.h +++ b/components/hal/include/hal/ecdsa_hal.h @@ -27,7 +27,6 @@ extern "C" { typedef struct { ecdsa_mode_t mode; /* Mode of operation */ ecdsa_curve_t curve; /* Curve to use for operation */ - ecdsa_k_mode_t k_mode; /* Source of K */ ecdsa_sha_mode_t sha_mode; /* Source of SHA that needs to be signed */ int efuse_key_blk; /* Efuse block to use as ECDSA key (The purpose of the efuse block must be ECDSA_KEY) */ bool use_km_key; /* Use an ECDSA key from the Key Manager peripheral */ @@ -37,13 +36,12 @@ typedef struct { * @brief Generate ECDSA signature * * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` - * @param k Value of K used internally. Set this to NULL if K is generated by hardware * @param hash Hash that is to be signed * @param r_out Buffer that will contain `R` component of ECDSA signature * @param s_out Buffer that will contain `S` component of ECDSA signature * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1) */ -void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *k, const uint8_t *hash, +void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, uint8_t *r_out, uint8_t *s_out, uint16_t len); /** diff --git a/components/hal/include/hal/ecdsa_types.h b/components/hal/include/hal/ecdsa_types.h index fa96fbdee70..8ef5636b49e 100644 --- a/components/hal/include/hal/ecdsa_types.h +++ b/components/hal/include/hal/ecdsa_types.h @@ -26,14 +26,6 @@ typedef enum { ECDSA_CURVE_SECP256R1, } ecdsa_curve_t; -/** - * @brief Source of 'K' used internally for generating signature - */ -typedef enum { - ECDSA_K_USE_TRNG, - ECDSA_K_USER_PROVIDED, -} ecdsa_k_mode_t; - /** * @brief Source of SHA message that is to be signed/verified */ diff --git a/components/hal/include/hal/gdma_hal.h b/components/hal/include/hal/gdma_hal.h index f43792d0d94..1eca5ebf3c6 100644 --- a/components/hal/include/hal/gdma_hal.h +++ b/components/hal/include/hal/gdma_hal.h @@ -85,13 +85,16 @@ struct gdma_hal_context_t { uint32_t (*get_intr_status_reg)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); // Get the interrupt status register address void (*enable_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis); /// Enable the channel interrupt void (*clear_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); /// Clear the channel interrupt - uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Read the channel interrupt status + uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); /// Read the channel interrupt status uint32_t (*get_eof_desc_addr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); /// Get the address of the descriptor with success/error EOF flag set #if SOC_GDMA_SUPPORT_CRC void (*clear_crc)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Clear the CRC interim results void (*set_crc_poly)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config); /// Set the CRC polynomial uint32_t (*get_crc_result)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Get the CRC result #endif // SOC_GDMA_SUPPORT_CRC +#if SOC_GDMA_SUPPORT_ETM + void (*enable_etm_task)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis); /// Enable the ETM task +#endif // SOC_GDMA_SUPPORT_ETM }; void gdma_hal_deinit(gdma_hal_context_t *hal); @@ -122,7 +125,7 @@ void gdma_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_dire uint32_t gdma_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); -uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); +uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); @@ -141,6 +144,10 @@ void gdma_hal_set_crc_poly(gdma_hal_context_t *hal, int chan_id, gdma_channel_di uint32_t gdma_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); #endif // SOC_GDMA_SUPPORT_CRC +#if SOC_GDMA_SUPPORT_ETM +void gdma_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis); +#endif + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/gdma_hal_ahb.h b/components/hal/include/hal/gdma_hal_ahb.h index 382f49ff5bf..e2de69b9e99 100644 --- a/components/hal/include/hal/gdma_hal_ahb.h +++ b/components/hal/include/hal/gdma_hal_ahb.h @@ -36,7 +36,7 @@ void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); -uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); +uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); uint32_t gdma_ahb_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); diff --git a/components/hal/include/hal/gdma_hal_axi.h b/components/hal/include/hal/gdma_hal_axi.h index 918e1926a2d..e9cb68b708c 100644 --- a/components/hal/include/hal/gdma_hal_axi.h +++ b/components/hal/include/hal/gdma_hal_axi.h @@ -36,7 +36,7 @@ void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); -uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); +uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index 1f613e4bdbe..d785ec491a5 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -74,8 +74,6 @@ typedef enum { #define GPIO_PIN_REG_52 IO_MUX_GPIO52_REG #define GPIO_PIN_REG_53 IO_MUX_GPIO53_REG #define GPIO_PIN_REG_54 IO_MUX_GPIO54_REG -#define GPIO_PIN_REG_55 IO_MUX_GPIO55_REG -#define GPIO_PIN_REG_56 IO_MUX_GPIO56_REG typedef enum { GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ diff --git a/components/hal/include/hal/ieee802154_common_ll.h b/components/hal/include/hal/ieee802154_common_ll.h index 86b8b9b996c..7520761b775 100644 --- a/components/hal/include/hal/ieee802154_common_ll.h +++ b/components/hal/include/hal/ieee802154_common_ll.h @@ -455,6 +455,85 @@ static inline void ieee802154_ll_disable_coex(void) IEEE802154.pti.hw_ack_pti = 1; } +static inline void ieee802154_ll_clear_debug_cnt(uint32_t clear_bits) +{ + IEEE802154.debug_cnt_clr.val = clear_bits; +} + +static inline uint32_t ieee802154_ll_get_sfd_timeout_cnt(void) +{ + return IEEE802154.debug_sfd_timeout_cnt; +} + +static inline uint32_t ieee802154_ll_get_crc_error_cnt(void) +{ + return IEEE802154.debug_crc_error_cnt; +} + +static inline uint32_t ieee802154_ll_get_ed_abort_cnt(void) +{ + return IEEE802154.debug_ed_abort_cnt; +} + +static inline uint32_t ieee802154_ll_get_cca_fail_cnt(void) +{ + return IEEE802154.debug_cca_fail_cnt; +} + +static inline uint32_t ieee802154_ll_get_rx_fliter_fail_cnt(void) +{ + return IEEE802154.debug_rx_filter_fail_cnt; +} + +static inline uint32_t ieee802154_ll_get_no_rss_detect_cnt(void) +{ + return IEEE802154.debug_no_rss_detect_cnt; +} + +static inline uint32_t ieee802154_ll_get_rx_abort_coex_cnt(void) +{ + return IEEE802154.debug_rx_abort_coex_cnt; +} + +static inline uint32_t ieee802154_ll_get_rx_restart_cnt(void) +{ + return IEEE802154.debug_rx_restart_cnt; +} + +static inline uint32_t ieee802154_ll_get_tx_ack_abort_coex_cnt(void) +{ + return IEEE802154.debug_tx_ack_abort_coex_cnt; +} + +static inline uint32_t ieee802154_ll_get_ed_scan_coex_cnt(void) +{ + return IEEE802154.debug_ed_scan_break_coex_cnt; +} + +static inline uint32_t ieee802154_ll_get_rx_ack_abort_coex_cnt(void) +{ + return IEEE802154.debug_rx_ack_abort_coex_cnt; +} + +static inline uint32_t ieee802154_ll_get_rx_ack_timeout_cnt(void) +{ + return IEEE802154.debug_rx_ack_timeout_cnt; +} + +static inline uint32_t ieee802154_ll_get_tx_break_coex_cnt(void) +{ + return IEEE802154.debug_tx_break_coex_cnt; +} + +static inline uint32_t ieee802154_ll_get_tx_security_error_cnt(void) +{ + return IEEE802154.debug_tx_security_error_cnt; +} + +static inline uint32_t ieee802154_ll_get_cca_busy_cnt(void) +{ + return IEEE802154.debug_cca_busy_cnt; +} #endif #ifdef __cplusplus diff --git a/components/hal/include/hal/jpeg_hal.h b/components/hal/include/hal/jpeg_hal.h new file mode 100644 index 00000000000..137ab119f3c --- /dev/null +++ b/components/hal/include/hal/jpeg_hal.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct jpeg_dev_t *jpeg_soc_handle_t; // JPEG SOC layer handle + +/** + * Context that should be maintained by both the driver and the HAL + */ +typedef struct { + jpeg_soc_handle_t dev; // JPEG SOC layer handle (i.e. register base address) +} jpeg_hal_context_t; + +/** + * @brief Initialize the JPEG codec HAL driver + * + * @param hal: JPEG codec HAL context + */ +void jpeg_hal_init(jpeg_hal_context_t *hal); + +/** + * @brief Deinitialize the JPEG codec HAL driver + * + * @param hal: JPEG codec HAL context + */ +void jpeg_hal_deinit(jpeg_hal_context_t *hal); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/jpeg_types.h b/components/hal/include/hal/jpeg_types.h new file mode 100644 index 00000000000..0d0b879d3d1 --- /dev/null +++ b/components/hal/include/hal/jpeg_types.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/color_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define JEPG_HUFFMAN_BITS_LEN_TABLE_LEN (16) +#define JPEG_HUFFMAN_AC_VALUE_TABLE_LEN (256) +#define JPEG_HUFFMAN_DC_VALUE_TABLE_LEN (16) +#define JPEG_QUANTIZATION_TABLE_LEN (64) + +/** + * @brief Enum for JPEG codec working mode. + */ +typedef enum { + JPEG_CODEC_ENCODER, ///< Encode mode + JPEG_CODEC_DECODER, ///< Decode mode +} jpeg_codec_mode_t; + +/** + * @brief Structure for recording factor of component. + */ +typedef struct { + uint32_t horizontal; ///< horizontal factor + uint32_t vertical; ///< vertical factor +} jpeg_component_factor_t; + +/** + * @brief Enum for JEPG sampling mode. + */ +typedef enum { + JPEG_SAMPLE_MODE_YUV444 = COLOR_PIXEL_YUV444, ///< sample in YUV444 + JPEG_SAMPLE_MODE_YUV422 = COLOR_PIXEL_YUV422, ///< sample in YUV422 + JPEG_SAMPLE_MODE_YUV420 = COLOR_PIXEL_YUV420, ///< sample in YUV420 +} jpeg_sample_mode_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/lcd_hal.h b/components/hal/include/hal/lcd_hal.h index 1312b5135e5..00b75493761 100644 --- a/components/hal/include/hal/lcd_hal.h +++ b/components/hal/include/hal/lcd_hal.h @@ -8,6 +8,7 @@ #include #include +#include "hal/hal_utils.h" #ifdef __cplusplus extern "C" { @@ -43,9 +44,10 @@ void lcd_hal_init(lcd_hal_context_t *hal, int id); * @param src_freq_hz LCD source clock frequency in Hz * @param expect_pclk_freq_hz Expected LCD PCLK frequency in Hz * @param lcd_clk_flags Extra flags to control LCD PCLK clock calculation, supported flags are prefixed with LCD_HAL_PCLK_FLAG_ + * @param lcd_clk_div Returned LCD clock divider parameter * @return Actual LCD PCLK frequency in Hz */ -uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uint32_t expect_pclk_freq_hz, int lcd_clk_flags); +uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uint32_t expect_pclk_freq_hz, int lcd_clk_flags, hal_utils_clk_div_t* lcd_clk_div); #ifdef __cplusplus } diff --git a/components/hal/include/hal/lcd_types.h b/components/hal/include/hal/lcd_types.h index ebb112b8035..e25ff40ac5d 100644 --- a/components/hal/include/hal/lcd_types.h +++ b/components/hal/include/hal/lcd_types.h @@ -19,7 +19,9 @@ extern "C" { * @brief LCD clock source */ typedef soc_periph_lcd_clk_src_t lcd_clock_source_t; -#endif +#else +typedef int lcd_clock_source_t; +#endif // SOC_LCD_I80_SUPPORTED || SOC_LCD_RGB_SUPPORTED /** * @brief RGB data endian @@ -37,6 +39,15 @@ typedef enum { LCD_COLOR_SPACE_YUV = COLOR_SPACE_YUV, /*!< Color space: YUV */ } lcd_color_space_t; +/** + * @brief LCD color pixel format in RGB color space + */ +typedef enum { + LCD_COLOR_PIXEL_FORMAT_RGB565 = COLOR_PIXEL_RGB565, /*!< 16 bits, 5 bits per R/B value, 6 bits for G value */ + LCD_COLOR_PIXEL_FORMAT_RGB666 = COLOR_PIXEL_RGB666, /*!< 18 bits, 6 bits per R/G/B value */ + LCD_COLOR_PIXEL_FORMAT_RGB888 = COLOR_PIXEL_RGB888, /*!< 24 bits, 8 bits per R/G/B value */ +} lcd_color_rgb_pixel_format_t; + /** * @brief LCD color range */ diff --git a/components/hal/include/hal/mipi_dsi_hal.h b/components/hal/include/hal/mipi_dsi_hal.h new file mode 100644 index 00000000000..41005971ab1 --- /dev/null +++ b/components/hal/include/hal/mipi_dsi_hal.h @@ -0,0 +1,158 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/lcd_types.h" +#include "hal/mipi_dsi_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MIPI DSI SOC layer representation of the host controller + */ +typedef struct dsi_host_dev_t *mipi_dsi_host_soc_handle_t; + +/** + * @brief MIPI DSI SOC layer representation of the bridge controller + */ +typedef struct dsi_brg_dev_t *mipi_dsi_bridge_soc_handle_t; + +/** + * @brief MIPI DSI HAL driver context + */ +typedef struct { + mipi_dsi_host_soc_handle_t host; /*!< Pointer to the host controller registers */ + mipi_dsi_bridge_soc_handle_t bridge; /*!< Pointer to the bridge controller registers */ + float dpi2lane_clk_ratio; /*!< Ratio between DPI clock and lane byte clock */ +} mipi_dsi_hal_context_t; + +/** + * @brief MIPI DSI HAL driver configuration + */ +typedef struct { + uint32_t lane_byte_clk_hz; /*!< Lane byte clock frequency */ + uint32_t dpi_clk_hz; /*!< DPI clock frequency */ +} mipi_dsi_hal_config_t; + +/** + * @brief Initialize MIPI DSI Hal driver context + * + * @note Caller should malloc the memory for the hal context + * + * @param hal Pointer to the HAL driver context + * @param config Pointer to the HAL driver configuration + */ +void mipi_dsi_hal_init(mipi_dsi_hal_context_t *hal, const mipi_dsi_hal_config_t *config); + +/** + * @brief Write a value to a PHY register via internal bus (so-called test interface) + * + * @param hal Pointer to the HAL driver context + * @param reg_addr Address of the PHY register + * @param reg_val Value to be written to the PHY register + */ +void mipi_dsi_hal_phy_write_register(mipi_dsi_hal_context_t *hal, uint8_t reg_addr, uint8_t reg_val); + +/** + * @brief Send a DCS command with parameters via the generic interface + * + * @note The command itself and the parameters are sent in one packet. For simplicity, we use the same + * DCS_LONG_WRITE type to send all different commands. + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param command DCS command + * @param command_bytes Number of bytes of the command + * @param param Pointer to the parameters + * @param param_size Number of bytes of the parameters + */ +void mipi_dsi_hal_host_gen_write_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc, + uint32_t command, uint32_t command_bytes, const void *param, uint16_t param_size); + +/** + * @brief Send a DCS command and return the associated parameters via the generic interface + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param command DCS command + * @param command_bytes Number of bytes of the command + * @param ret_param Pointer to the buffer to store the returned parameters + * @param param_buf_size Size of the buffer to store the returned parameters + */ +void mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc, uint32_t command, uint32_t command_bytes, void *ret_param, uint16_t param_buf_size); + +/** + * @brief Send a long packet via the generic interface + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param dt Data type + * @param buffer Pointer to the buffer + * @param buffer_size Number of bytes to be sent + */ +void mipi_dsi_hal_host_gen_write_long_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, const void *buffer, uint16_t buffer_size); + +/** + * @brief Send a short packet via the generic interface + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param dt Data type + * @param header_data Data to be sent, filled into the DSI packet header + */ +void mipi_dsi_hal_host_gen_write_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data); + +/** + * @brief Send a short packet via the generic interface and return the associated data + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param dt Data type + * @param header_data Data to be filled into the DSI packet header + * @param ret_buffer Pointer to the buffer to store the returned data + * @param buffer_size Size of the buffer to store the returned data + */ +void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size); + +/** + * @brief Set DPI color coding + * + * @param hal Pointer to the HAL driver context + * @param color_coding Color coding + * @param sub_config Sub configuration + */ +void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config); + +/** + * @brief Set horizontal timing parameters for DPI + * + * @param hal Pointer to the HAL driver context + * @param hsw Horizontal Synchronization Width + * @param hbp Horizontal Back Porch + * @param active_width Active Width + * @param hfp Horizontal Front Porch + */ +void mipi_dsi_hal_host_dpi_set_horizontal_timing(mipi_dsi_hal_context_t *hal, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp); + +/** + * @brief Set vertical timing parameters for DPI + * + * @param hal Pointer to the HAL driver context + * @param vsw Vertical Synchronization Width + * @param vbp Vertical Back Porch + * @param active_height Active Height + * @param vfp Vertical Front Porch + */ +void mipi_dsi_hal_host_dpi_set_vertical_timing(mipi_dsi_hal_context_t *hal, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp); + +#ifdef __cplusplus + +} +#endif diff --git a/components/hal/include/hal/mipi_dsi_types.h b/components/hal/include/hal/mipi_dsi_types.h new file mode 100644 index 00000000000..68c666ad21a --- /dev/null +++ b/components/hal/include/hal/mipi_dsi_types.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "esp_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MIPI DSI Data Type (DT) + */ +typedef enum { + MIPI_DSI_DT_VSYNC_START = 0x01, /*!< V Sync Start */ + MIPI_DSI_DT_VSYNC_END = 0x11, /*!< V Sync End */ + MIPI_DSI_DT_HSYNC_START = 0x21, /*!< H Sync Start */ + MIPI_DSI_DT_HSYNC_END = 0x31, /*!< H Sync End */ + MIPI_DSI_DT_EOT_PACKET = 0x08, /*!< End of Transmission */ + MIPI_DSI_DT_COLOR_MODE_OFF = 0x02, /*!< Color Mode Off */ + MIPI_DSI_DT_COLOR_MODE_ON = 0x12, /*!< Color Mode On */ + MIPI_DSI_DT_SHUTDOWN_PERIPHERAL = 0x22, /*!< Shutdown Peripheral */ + MIPI_DSI_DT_TURN_ON_PERIPHERAL = 0x32, /*!< Turn On Peripheral */ + MIPI_DSI_DT_GENERIC_SHORT_WRITE_0 = 0x03, /*!< Generic Short Write, with no parameter */ + MIPI_DSI_DT_GENERIC_SHORT_WRITE_1 = 0x13, /*!< Generic Short Write, with 1 byte parameter */ + MIPI_DSI_DT_GENERIC_SHORT_WRITE_2 = 0x23, /*!< Generic Short Write, with 2 byte parameter */ + MIPI_DSI_DT_GENERIC_READ_REQUEST_0 = 0x04, /*!< Generic Read Request, with no parameter */ + MIPI_DSI_DT_GENERIC_READ_REQUEST_1 = 0x14, /*!< Generic Read Request, with 1 byte parameter */ + MIPI_DSI_DT_GENERIC_READ_REQUEST_2 = 0x24, /*!< Generic Read Request, with 2 byte parameter */ + MIPI_DSI_DT_DCS_SHORT_WRITE_0 = 0x05, /*!< DCS Short Write, with no parameter */ + MIPI_DSI_DT_DCS_SHORT_WRITE_1 = 0x15, /*!< DCS Short Write, with 1 byte parameter */ + MIPI_DSI_DT_DCS_READ_0 = 0x06, /*!< DCS Read, with no parameter */ + MIPI_DSI_DT_SET_MAXIMUM_RETURN_PKT = 0x37, /*!< Set Maximum Return Packet Size */ + MIPI_DSI_DT_NULL_PACKET = 0x09, /*!< Null Packet, no data */ + MIPI_DSI_DT_BLANKING_PACKET = 0x19, /*!< Blanking Packet, no data */ + MIPI_DSI_DT_GENERIC_LONG_WRITE = 0x29, /*!< Generic Long Write */ + MIPI_DSI_DT_DCS_LONG_WRITE = 0x39, /*!< DCS Long Write */ + MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_16 = 0x0E, /*!< Packed Pixel Stream, RGB565 */ + MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_18 = 0x1E, /*!< Packed Pixel Stream, RGB666 */ + MIPI_DSI_DT_LOOSELY_PIXEL_STREAM_RGB_18 = 0x2E, /*!< Loosely Pixel Stream, RGB666 */ + MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_24 = 0x3E, /*!< Packed Pixel Stream, RGB888 */ +} __attribute__((packed)) mipi_dsi_data_type_t; + +/** + * @brief MIPI DSI packet + */ +typedef struct { + mipi_dsi_data_type_t dt: 6; /*!< Data Type */ + uint8_t vc: 2; /*!< Virtual Channel */ + union { + uint16_t word_count; /*!< Word count, in bytes */ + uint8_t data[2]; /*!< Data of short packet */ + }; + uint8_t ecc; /*!< ECC */ + uint8_t payload[0]; /*!< Payload of long packet */ +} __attribute__((packed)) mipi_dsi_packet_t; + +ESP_STATIC_ASSERT(sizeof(mipi_dsi_packet_t) == 4, "Invalid size of mipi_dsi_packet_t structure"); + +#if SOC_MIPI_DSI_SUPPORTED +/** + * @brief MIPI DSI PHY clock source + */ +typedef soc_periph_mipi_dsi_phy_clk_src_t mipi_dsi_phy_clock_source_t; + +/** + * @brief MIPI DSI DPI clock source + */ +typedef soc_periph_mipi_dsi_dpi_clk_src_t mipi_dsi_dpi_clock_source_t; +#else +typedef int mipi_dsi_phy_clock_source_t; +typedef int mipi_dsi_dpi_clock_source_t; +#endif // SOC_MIPI_DSI_SUPPORTED + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/modem_clock_types.h b/components/hal/include/hal/modem_clock_types.h index e430a0610ff..bb972f7a7f4 100644 --- a/components/hal/include/hal/modem_clock_types.h +++ b/components/hal/include/hal/modem_clock_types.h @@ -15,8 +15,7 @@ typedef enum { MODEM_CLOCK_DOMAIN_MODEM_PERIPH, MODEM_CLOCK_DOMAIN_WIFI, MODEM_CLOCK_DOMAIN_BT, - MODEM_CLOCK_DOMAIN_MODEM_ADC_COMMON_FE, - MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE, + MODEM_CLOCK_DOMAIN_MODEM_FE, MODEM_CLOCK_DOMAIN_IEEE802154, MODEM_CLOCK_DOMAIN_LP_APB, MODEM_CLOCK_DOMAIN_I2C_MASTER, diff --git a/components/hal/include/hal/pau_hal.h b/components/hal/include/hal/pau_hal.h index 197fd635724..4853cfa304e 100644 --- a/components/hal/include/hal/pau_hal.h +++ b/components/hal/include/hal/pau_hal.h @@ -55,7 +55,7 @@ void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_rest void pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal); #endif -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA /** * @brief Set regdma system link address * @@ -102,7 +102,7 @@ void pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_rest */ void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal); -#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA /** * @brief Enable or disable PAU module clock * diff --git a/components/hal/include/hal/rtc_io_hal.h b/components/hal/include/hal/rtc_io_hal.h index 2e6d50ca81a..67b2201bcaa 100644 --- a/components/hal/include/hal/rtc_io_hal.h +++ b/components/hal/include/hal/rtc_io_hal.h @@ -259,7 +259,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode); #define rtcio_hal_wakeup_disable(rtcio_num) rtcio_ll_wakeup_disable(rtcio_num) /** - * Set specific logic level on an RTC IO pin as a wakeup trigger. + * Set specific logic level on an RTC IO pin as a ext0 wakeup trigger. * * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT. * @param level Logic level (0) diff --git a/components/hal/include/hal/systimer_hal.h b/components/hal/include/hal/systimer_hal.h index ac6e338e455..b03b927fcf2 100644 --- a/components/hal/include/hal/systimer_hal.h +++ b/components/hal/include/hal/systimer_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -126,14 +126,6 @@ void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps); #endif -/** - * @brief Set Systimer clock source - * - * Use this function as - PERIPH_RCC_ATOMIC(){ systimer_hal_set_clock_source(hal, clk_src); } - * due to Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section - */ -void systimer_hal_set_clock_source(systimer_hal_context_t *hal, systimer_clock_source_t clk_src); - /** * @brief Get Systimer clock source */ diff --git a/components/hal/include/hal/touch_sensor_types.h b/components/hal/include/hal/touch_sensor_types.h index 46e0d967ca4..55291090cb6 100644 --- a/components/hal/include/hal/touch_sensor_types.h +++ b/components/hal/include/hal/touch_sensor_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -119,7 +119,13 @@ typedef enum { #define TOUCH_PAD_LOW_VOLTAGE_THRESHOLD (TOUCH_LVOLT_0V5) #define TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD (TOUCH_HVOLT_ATTEN_0V5) #define TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT (TOUCH_PAD_CONN_GND) -#define TOUCH_PAD_THRESHOLD_MAX (SOC_TOUCH_PAD_THRESHOLD_MAX) /*!dev) -/** - * @brief Configure the UART core reset - * - * @param hal Context of the HAL layer - * @param core_rst_en true to enable the core reset, otherwise set it false - * - * @return None - */ -#define uart_hal_set_reset_core(hal, core_rst_en) uart_ll_set_reset_core((hal)->dev, core_rst_en) - /** * @brief Read data from the UART rxfifo * diff --git a/components/hal/include/hal/usb_dwc_hal.h b/components/hal/include/hal/usb_dwc_hal.h index 3648b259e0e..38fd1fe3410 100644 --- a/components/hal/include/hal/usb_dwc_hal.h +++ b/components/hal/include/hal/usb_dwc_hal.h @@ -1,39 +1,57 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#ifdef __cplusplus -extern "C" { -#endif - +#include "soc/soc_caps.h" /* -NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL - functions must be called from critical sections unless specified otherwise +This header is shared across all targets. Resolve to an empty header for targets +that don't support USB OTG. */ - -#include -#include -#include "soc/soc_caps.h" #if SOC_USB_OTG_SUPPORTED -#include "soc/usb_dwc_struct.h" +#include +#include #include "hal/usb_dwc_ll.h" -#endif -#include "hal/usb_types_private.h" +#include "hal/usb_dwc_types.h" #include "hal/assert.h" +#endif // SOC_USB_OTG_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif -// ------------------------------------------------ Macros and Types --------------------------------------------------- #if SOC_USB_OTG_SUPPORTED -// ------------------ Constants/Configs -------------------- -#define USB_DWC_HAL_DMA_MEM_ALIGN 512 -#define USB_DWC_HAL_FRAME_LIST_MEM_ALIGN 512 //The frame list needs to be 512 bytes aligned (contrary to the databook) -#define USB_DWC_HAL_NUM_CHAN 8 -#define USB_DWC_HAL_XFER_DESC_SIZE (sizeof(usb_dwc_ll_dma_qtd_t)) -#define USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES 200 //Although we have a 256 lines, only 200 lines are usuable due to EPINFO_CTL +// ------------------------------------------------ Macros and Types --------------------------------------------------- + +// ----------------------- Configs ------------------------- + +/** + * @brief Possible FIFO biases + */ +typedef enum { + USB_HAL_FIFO_BIAS_DEFAULT, /**< Default (balanced) FIFO sizes */ + USB_HAL_FIFO_BIAS_RX, /**< Bigger RX FIFO for IN transfers */ + USB_HAL_FIFO_BIAS_PTX, /**< Bigger periodic TX FIFO for ISOC OUT transfers */ +} usb_hal_fifo_bias_t; + +/** + * @brief MPS limits based on FIFO configuration + * + * In bytes + * + * The resulting values depend on + * 1. FIFO total size (chip specific) + * 2. Set FIFO bias + */ +typedef struct { + unsigned int in_mps; /**< Maximum packet size of IN packet */ + unsigned int non_periodic_out_mps; /**< Maximum packet size of BULK and CTRL OUT packets */ + unsigned int periodic_out_mps; /**< Maximum packet size of INTR and ISOC OUT packets */ +} usb_hal_fifo_mps_limits_t; /** * @brief FIFO size configuration structure @@ -111,7 +129,7 @@ typedef enum { typedef struct { union { struct { - usb_priv_xfer_type_t type: 2; /**< The type of endpoint */ + usb_dwc_xfer_type_t type: 2; /**< The type of endpoint */ uint32_t bEndpointAddress: 8; /**< Endpoint address (containing endpoint number and direction) */ uint32_t mps: 11; /**< Maximum Packet Size */ uint32_t dev_addr: 8; /**< Device Address */ @@ -122,7 +140,7 @@ typedef struct { uint32_t val; }; struct { - usb_hal_interval_t interval; /**< The interval of the endpoint */ + unsigned int interval; /**< The interval of the endpoint in frames (FS) or microframes (HS) */ uint32_t phase_offset_frames; /**< Phase offset in number of frames */ } periodic; /**< Characteristic for periodic (interrupt/isochronous) endpoints only */ } usb_dwc_hal_ep_char_t; @@ -142,9 +160,9 @@ typedef struct { }; uint32_t val; } flags; /**< Flags regarding channel's status and information */ - usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */ - usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */ - usb_priv_xfer_type_t type; /**< The transfer type of the channel */ + usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */ + usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */ + usb_dwc_xfer_type_t type; /**< The transfer type of the channel */ void *chan_ctx; /**< Context variable for the owner of the channel */ } usb_dwc_hal_chan_t; @@ -155,8 +173,10 @@ typedef struct { //Context usb_dwc_dev_t *dev; /**< Pointer to base address of DWC_OTG registers */ //Host Port related - uint32_t *periodic_frame_list; /**< Pointer to scheduling frame list */ - usb_hal_frame_list_len_t frame_list_len; /**< Length of the periodic scheduling frame list */ + uint32_t *periodic_frame_list; /**< Pointer to scheduling frame list */ + usb_hal_frame_list_len_t frame_list_len; /**< Length of the periodic scheduling frame list */ + //FIFO related + const usb_dwc_hal_fifo_config_t *fifo_config; /**< FIFO sizes configuration */ union { struct { uint32_t dbnc_lock_enabled: 1; /**< Debounce lock enabled */ @@ -171,7 +191,7 @@ typedef struct { struct { int num_allocd; /**< Number of channels currently allocated */ uint32_t chan_pend_intrs_msk; /**< Bit mask of channels with pending interrupts */ - usb_dwc_hal_chan_t *hdls[USB_DWC_HAL_NUM_CHAN]; /**< Handles of each channel. Set to NULL if channel has not been allocated */ + usb_dwc_hal_chan_t *hdls[OTG_NUM_HOST_CHAN]; /**< Handles of each channel. Set to NULL if channel has not been allocated */ } channels; } usb_dwc_hal_context_t; @@ -225,21 +245,28 @@ void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal); void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal); /** - * @brief Set FIFO sizes + * @brief Set FIFO bias * * This function will set the sizes of each of the FIFOs (RX FIFO, Non-periodic TX FIFO, Periodic TX FIFO) and must be - * called at least once before allocating the channel. Based on the type of endpoints (and the endpionts' MPS), there + * called at least once before allocating the channel. Based on the type of endpoints (and the endpoints' MPS), there * may be situations where this function may need to be called again to resize the FIFOs. If resizing FIFOs dynamically, * it is the user's responsibility to ensure there are no active channels when this function is called. * - * @note The totol size of all the FIFOs must be less than or equal to USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES * @note After a port reset, the FIFO size registers will reset to their default values, so this function must be called * again post reset. * - * @param hal Context of the HAL layer - * @param fifo_config FIFO configuration + * @param[in] hal Context of the HAL layer + * @param[in] fifo_bias FIFO bias configuration */ -void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *fifo_config); +void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bias_t fifo_bias); + +/** + * @brief Get MPS limits + * + * @param[in] hal Context of the HAL layer + * @param[out] mps_limits MPS limits + */ +void usb_dwc_hal_get_mps_limits(usb_dwc_hal_context_t *hal, usb_hal_fifo_mps_limits_t *mps_limits); // ---------------------------------------------------- Host Port ------------------------------------------------------ @@ -472,14 +499,14 @@ static inline bool usb_dwc_hal_port_check_if_connected(usb_dwc_hal_context_t *ha } /** - * @brief Check the speed (LS/FS) of the device connected to the host port + * @brief Check the speed of the device connected to the host port * * @note This function should only be called after confirming that a device is connected to the host port * * @param hal Context of the HAL layer - * @return usb_priv_speed_t Speed of the connected device (FS or LS only on the esp32-s2 and esp32-s3) + * @return usb_dwc_speed_t Speed of the connected device */ -static inline usb_priv_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal) +static inline usb_dwc_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal) { return usb_dwc_ll_hprt_get_speed(hal->dev); } @@ -788,7 +815,7 @@ usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal */ usb_dwc_hal_chan_event_t usb_dwc_hal_chan_decode_intr(usb_dwc_hal_chan_t *chan_obj); -#endif +#endif // SOC_USB_OTG_SUPPORTED #ifdef __cplusplus } diff --git a/components/hal/include/hal/usb_dwc_ll.h b/components/hal/include/hal/usb_dwc_ll.h index eb7231d2f7c..7d0b021f471 100644 --- a/components/hal/include/hal/usb_dwc_ll.h +++ b/components/hal/include/hal/usb_dwc_ll.h @@ -1,24 +1,106 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/soc_caps.h" +/* +This header is shared across all targets. Resolve to an empty header for targets +that don't support USB OTG. +*/ +#if SOC_USB_OTG_SUPPORTED +#include +#include +#include "soc/usb_dwc_struct.h" +#include "soc/usb_dwc_cfg.h" +#include "hal/usb_dwc_types.h" +#include "hal/misc.h" +#endif // SOC_USB_OTG_SUPPORTED + #ifdef __cplusplus extern "C" { #endif -#include -#include -#include "soc/soc_caps.h" #if SOC_USB_OTG_SUPPORTED -#include "soc/usb_dwc_struct.h" -#endif -#include "hal/usb_types_private.h" -#include "hal/misc.h" +/* ----------------------------------------------------------------------------- +--------------------------------- DWC Constants -------------------------------- +----------------------------------------------------------------------------- */ + +#define USB_DWC_QTD_LIST_MEM_ALIGN 512 +#define USB_DWC_FRAME_LIST_MEM_ALIGN 512 // The frame list needs to be 512 bytes aligned (contrary to the databook) +/* +Although we have a 256 lines, only 200 lines are useable due to EPINFO_CTL. +Todo: Check sizes again and express this macro in terms of DWC config options (IDF-7384) +*/ +#define USB_DWC_FIFO_TOTAL_USABLE_LINES 200 + +/* ----------------------------------------------------------------------------- +------------------------------ DWC Configuration ------------------------------- +----------------------------------------------------------------------------- */ + +/** + * @brief Default FIFO sizes (see 2.1.2.4 for programming guide) + * + * RXFIFO + * - Recommended: ((LPS/4) * 2) + 2 + * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104 + * - Worst case can accommodate two packets of 204 bytes, or one packet of 408 + * NPTXFIFO + * - Recommended: (LPS/4) * 2 + * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48 + * - Worst case can accommodate three packets of 64 bytes or one packet of 192 + * PTXFIFO + * - Recommended: (LPS/4) * 2 + * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48 + * - Worst case can accommodate three packets of 64 bytes or one packet of 192 + */ +#define USB_DWC_FIFO_RX_LINES_DEFAULT 104 +#define USB_DWC_FIFO_NPTX_LINES_DEFAULT 48 +#define USB_DWC_FIFO_PTX_LINES_DEFAULT 48 + +/** + * @brief FIFO sizes that bias to giving RX FIFO more capacity + * + * RXFIFO + * - Recommended: ((LPS/4) * 2) + 2 + * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152 + * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes + * NPTXFIFO + * - Recommended: (LPS/4) * 2 + * - Actual: Assume LPS is 64, and 1 packets: (64/4) * 1 = 16 + * - Worst case can accommodate one packet of 64 bytes + * PTXFIFO + * - Recommended: (LPS/4) * 2 + * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 2 = 32 + * - Worst case can accommodate two packets of 64 bytes or one packet of 128 + */ +#define USB_DWC_FIFO_RX_LINES_BIASRX 152 +#define USB_DWC_FIFO_NPTX_LINES_BIASRX 16 +#define USB_DWC_FIFO_PTX_LINES_BIASRX 32 + +/** + * @brief FIFO sizes that bias to giving Periodic TX FIFO more capacity (i.e., ISOC OUT) + * + * RXFIFO + * - Recommended: ((LPS/4) * 2) + 2 + * - Actual: Assume LPS is 64, and 2 packets: ((64/4) * 2) + 2 = 34 + * - Worst case can accommodate two packets of 64 bytes or one packet of 128 + * NPTXFIFO + * - Recommended: (LPS/4) * 2 + * - Actual: Assume LPS is 64, and 1 packets: (64/4) * 1 = 16 + * - Worst case can accommodate one packet of 64 bytes + * PTXFIFO + * - Recommended: (LPS/4) * 2 + * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150 + * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes + */ +#define USB_DWC_FIFO_RX_LINES_BIASTX 34 +#define USB_DWC_FIFO_NPTX_LINES_BIASTX 16 +#define USB_DWC_FIFO_PTX_LINES_BIASTX 150 /* ----------------------------------------------------------------------------- ------------------------------- Global Registers ------------------------------- @@ -98,7 +180,6 @@ extern "C" { #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) -#if SOC_USB_OTG_SUPPORTED /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * Each QTD describes one transfer. Scatter gather mode will automatically split @@ -422,7 +503,7 @@ static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw) * @param hw Start address of the DWC_OTG registers * @param speed Speed to initialize the host port at */ -static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed) +static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed) { hw->hcfg_reg.descdma = 1; //Enable scatt/gatt hw->hcfg_reg.fslssupp = 1; //FS/LS support only @@ -431,13 +512,13 @@ static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_spee Note: It seems like our PHY has an implicit 8 divider applied when in LS mode, so the values of FSLSPclkSel and FrInt have to be adjusted accordingly. */ - hw->hcfg_reg.fslspclksel = (speed == USB_PRIV_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only + hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only hw->hcfg_reg.perschedena = 0; //Disable perio sched } // ----------------------------- HFIR Register --------------------------------- -static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed) +static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed) { usb_dwc_hfir_reg_t hfir; hfir.val = hw->hfir_reg.val; @@ -447,7 +528,7 @@ static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_spee Note: It seems like our PHY has an implicit 8 divider applied when in LS mode, so the values of FSLSPclkSel and FrInt have to be adjusted accordingly. */ - hfir.frint = (speed == USB_PRIV_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS + hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS hw->hfir_reg.val = hfir.val; } @@ -530,19 +611,9 @@ static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw) // ----------------------------- HPRT Register --------------------------------- -static inline usb_priv_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw) +static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw) { - usb_priv_speed_t speed; - //esp32-s2 and esp32-s3 only support FS or LS - switch (hw->hprt_reg.prtspd) { - case 1: - speed = USB_PRIV_SPEED_FULL; - break; - default: - speed = USB_PRIV_SPEED_LOW; - break; - } - return speed; + return (usb_dwc_speed_t)hw->hprt_reg.prtspd; } static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw) @@ -701,24 +772,9 @@ static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_reg chan->hcchar_reg.devaddr = addr; } -static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_priv_xfer_type_t type) +static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type) { - uint32_t ep_type; - switch (type) { - case USB_PRIV_XFER_TYPE_CTRL: - ep_type = 0; - break; - case USB_PRIV_XFER_TYPE_ISOCHRONOUS: - ep_type = 1; - break; - case USB_PRIV_XFER_TYPE_BULK: - ep_type = 2; - break; - default: //USB_PRIV_XFER_TYPE_INTR - ep_type = 3; - break; - } - chan->hcchar_reg.eptype = ep_type; + chan->hcchar_reg.eptype = (uint32_t)type; } //Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause @@ -743,7 +799,7 @@ static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t * chan->hcchar_reg.mps = mps; } -static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_priv_xfer_type_t type, bool is_in, bool is_ls) +static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls) { //Sets all persistent fields of the channel over its lifetimez usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr); @@ -793,28 +849,48 @@ static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len) { - HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, ntd, qtd_list_len - 1); //Set the length of the descriptor list + usb_dwc_hctsiz_reg_t hctsiz; + hctsiz.val = chan->hctsiz_reg.val; + //Set the length of the descriptor list. NTD occupies xfersize[15:8] + hctsiz.xfersize &= ~(0xFF << 8); + hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8; + chan->hctsiz_reg.val = hctsiz.val; } static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan) { - chan->hctsiz_reg.dopng = 0; //Don't do ping - HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, sched_info, 0xFF); //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels + usb_dwc_hctsiz_reg_t hctsiz; + hctsiz.val = chan->hctsiz_reg.val; + hctsiz.dopng = 0; //Don't do ping + /* + Set SCHED_INFO which occupies xfersize[7:0] + It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels + */ + hctsiz.xfersize |= 0xFF; + chan->hctsiz_reg.val = hctsiz.val; } // ---------------------------- HCDMAi Register -------------------------------- static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx) { - //Set HCDMAi - chan->hcdma_reg.val = 0; - chan->hcdma_reg.non_iso.dmaaddr = (((uint32_t)dmaaddr) >> 9) & 0x7FFFFF; //MSB of 512 byte aligned address - chan->hcdma_reg.non_iso.ctd = qtd_idx; + usb_dwc_hcdma_reg_t hcdma; + /* + Set the base address portion of the field which is dmaaddr[31:9]. This is + the based address of the QTD list and must be 512 bytes aligned + */ + hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00; + //Set the current QTD index in the QTD list which is dmaaddr[8:3] + hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3; + //dmaaddr[2:0] is reserved thus doesn't not need to be set + + chan->hcdma_reg.val = hcdma.val; } static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan) { - return chan->hcdma_reg.non_iso.ctd; + //The current QTD index is dmaaddr[8:3] + return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F; } // ---------------------------- HCDMABi Register ------------------------------- @@ -934,7 +1010,7 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem qtd->buffer_status_val = 0; } -#endif +#endif // SOC_USB_OTG_SUPPORTED #ifdef __cplusplus } diff --git a/components/hal/include/hal/usb_types_private.h b/components/hal/include/hal/usb_dwc_types.h similarity index 66% rename from components/hal/include/hal/usb_types_private.h rename to components/hal/include/hal/usb_dwc_types.h index d3d358688d8..22018953bc7 100644 --- a/components/hal/include/hal/usb_types_private.h +++ b/components/hal/include/hal/usb_dwc_types.h @@ -20,21 +20,26 @@ extern "C" /** * @brief USB speeds supported by the DWC OTG controller + * + * @note usb_dwc_speed_t enum values must match the values of the DWC_OTG prtspd register field */ typedef enum { - USB_PRIV_SPEED_FULL, - USB_PRIV_SPEED_LOW, -} usb_priv_speed_t; + USB_DWC_SPEED_HIGH = 0, + USB_DWC_SPEED_FULL = 1, + USB_DWC_SPEED_LOW = 2, +} usb_dwc_speed_t; /** * @brief USB transfer types supported by the DWC OTG controller + * + * @note usb_dwc_xfer_type_t enum values must match the values of the DWC_OTG hcchar register field */ typedef enum { - USB_PRIV_XFER_TYPE_CTRL, - USB_PRIV_XFER_TYPE_ISOCHRONOUS, - USB_PRIV_XFER_TYPE_BULK, - USB_PRIV_XFER_TYPE_INTR, -} usb_priv_xfer_type_t; + USB_DWC_XFER_TYPE_CTRL = 0, + USB_DWC_XFER_TYPE_ISOCHRONOUS = 1, + USB_DWC_XFER_TYPE_BULK = 2, + USB_DWC_XFER_TYPE_INTR = 3, +} usb_dwc_xfer_type_t; /** * @brief Enumeration of different possible lengths of the periodic frame list @@ -46,19 +51,6 @@ typedef enum { USB_HAL_FRAME_LIST_LEN_64 = 64, } usb_hal_frame_list_len_t; -/** - * @brief Support intervals in number of USB frames (i.e., 1ms) - */ -typedef enum { - USB_HAL_INTERVAL_1 = 1, - USB_HAL_INTERVAL_2 = 2, - USB_HAL_INTERVAL_4 = 4, - USB_HAL_INTERVAL_8 = 8, - USB_HAL_INTERVAL_16 = 16, - USB_HAL_INTERVAL_32 = 32, - USB_HAL_INTERVAL_64 = 64, -} usb_hal_interval_t; - #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/usb_phy_hal.h b/components/hal/include/hal/usb_phy_hal.h index f8d5a2688b6..6312744bff5 100644 --- a/components/hal/include/hal/usb_phy_hal.h +++ b/components/hal/include/hal/usb_phy_hal.h @@ -7,7 +7,7 @@ #pragma once #include -#include "usb_types_private.h" +#include "usb_dwc_types.h" #include "usb_phy_types.h" #include "soc/soc_caps.h" #if SOC_USB_OTG_SUPPORTED @@ -72,7 +72,7 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal); * @param hal Context of the HAL layer * @param speed USB speed */ -void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_priv_speed_t speed); +void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed); /** * @brief Enable/Disable test mode for internal PHY to mimick host-device disconnection diff --git a/components/hal/include/hal/usb_phy_types.h b/components/hal/include/hal/usb_phy_types.h index 1f5ac431efa..50636a64ddf 100644 --- a/components/hal/include/hal/usb_phy_types.h +++ b/components/hal/include/hal/usb_phy_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -55,6 +55,7 @@ typedef enum { USB_PHY_SPEED_UNDEFINED, USB_PHY_SPEED_LOW, /**< USB Low Speed (1.5 Mbit/s) */ USB_PHY_SPEED_FULL, /**< USB Full Speed (12 Mbit/s) */ + USB_PHY_SPEED_HIGH, /**< USB High Speed (480 Mbit/s) */ USB_PHY_SPEED_MAX, } usb_phy_speed_t; diff --git a/components/hal/jpeg_hal.c b/components/hal/jpeg_hal.c new file mode 100644 index 00000000000..9ac73fda6f6 --- /dev/null +++ b/components/hal/jpeg_hal.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "hal/jpeg_hal.h" +#include "hal/jpeg_ll.h" + +void jpeg_hal_init(jpeg_hal_context_t *hal) +{ + hal->dev = JPEG_LL_GET_HW(); +} + +void jpeg_hal_deinit(jpeg_hal_context_t *hal) +{ + hal->dev = NULL; +} diff --git a/components/hal/lcd_hal.c b/components/hal/lcd_hal.c index 706f5787dce..22572e8b094 100644 --- a/components/hal/lcd_hal.c +++ b/components/hal/lcd_hal.c @@ -7,14 +7,13 @@ #include "hal/lcd_hal.h" #include "hal/lcd_ll.h" #include "hal/log.h" -#include "hal/hal_utils.h" void lcd_hal_init(lcd_hal_context_t *hal, int id) { hal->dev = LCD_LL_GET_HW(id); } -uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uint32_t expect_pclk_freq_hz, int lcd_clk_flags) +uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uint32_t expect_pclk_freq_hz, int lcd_clk_flags, hal_utils_clk_div_t* lcd_clk_div) { // lcd_clk = module_clock_src / (n + b / a) // pixel_clk = lcd_clk / mo @@ -29,12 +28,9 @@ uint32_t lcd_hal_cal_pclk_freq(lcd_hal_context_t *hal, uint32_t src_freq_hz, uin .min_integ = 2, .max_fract = LCD_LL_CLK_FRAC_DIV_AB_MAX, }; - hal_utils_clk_div_t lcd_clk_div = {}; - uint32_t real_freq = hal_utils_calc_clk_div_frac_fast(&lcd_clk_info, &lcd_clk_div); - HAL_EARLY_LOGD("lcd_hal", "n=%"PRIu32",a=%"PRIu32",b=%"PRIu32",mo=%"PRIu32, lcd_clk_div.integer, lcd_clk_div.denominator, lcd_clk_div.numerator, mo); + uint32_t real_freq = hal_utils_calc_clk_div_frac_fast(&lcd_clk_info, lcd_clk_div); + HAL_EARLY_LOGD("lcd_hal", "n=%"PRIu32",a=%"PRIu32",b=%"PRIu32",mo=%"PRIu32, lcd_clk_div->integer, lcd_clk_div->denominator, lcd_clk_div->numerator, mo); - lcd_ll_set_group_clock_coeff(hal->dev, lcd_clk_div.integer, lcd_clk_div.denominator, lcd_clk_div.numerator); lcd_ll_set_pixel_clock_prescale(hal->dev, mo); - return real_freq / mo; } diff --git a/components/hal/mipi_dsi_hal.c b/components/hal/mipi_dsi_hal.c new file mode 100644 index 00000000000..74a677f4b31 --- /dev/null +++ b/components/hal/mipi_dsi_hal.c @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "hal/mipi_dsi_hal.h" +#include "hal/mipi_dsi_ll.h" + +void mipi_dsi_hal_init(mipi_dsi_hal_context_t *hal, const mipi_dsi_hal_config_t *config) +{ + hal->host = &MIPI_DSI_HOST; + hal->bridge = &MIPI_DSI_BRIDGE; + hal->dpi2lane_clk_ratio = ((float)config->lane_byte_clk_hz) / config->dpi_clk_hz; +} + +void mipi_dsi_hal_phy_write_register(mipi_dsi_hal_context_t *hal, uint8_t reg_addr, uint8_t reg_val) +{ + // disable the test clear pin, enable the interface to write values to the PHY internal registers + mipi_dsi_phy_ll_write_clock(hal->host, 0, false); + // load PHY register address + mipi_dsi_phy_ll_write_reg_addr(hal->host, reg_addr); + // the address write operation is set on the falling edge of the test clock + mipi_dsi_phy_ll_write_clock(hal->host, 1, false); + mipi_dsi_phy_ll_write_clock(hal->host, 0, false); + // load PHY register value + mipi_dsi_phy_ll_write_reg_val(hal->host, reg_val); + // the data write operation is set on the rising edge of the test clock + mipi_dsi_phy_ll_write_clock(hal->host, 1, false); + mipi_dsi_phy_ll_write_clock(hal->host, 0, false); +} + +void mipi_dsi_hal_host_gen_write_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc, + uint32_t command, uint32_t command_bytes, const void *param, uint16_t param_size) +{ + const uint8_t *payload = param; + // the payload size is the command size plus the parameter size + uint32_t payload_size = command_bytes + param_size; + + // merge the command and some bytes of parameters into one 32-bit word + uint32_t temp = command & ((1 << (8 * command_bytes)) - 1); + uint16_t merged_size = MIN(4 - command_bytes, param_size); + for (int i = 0; i < merged_size; i++) { + temp |= payload[i] << (8 * (i + command_bytes)); + } + while (mipi_dsi_host_ll_gen_is_write_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_write_payload_fifo(hal->host, temp); + + // write the remaining parameters into FIFO + payload += merged_size; + uint32_t remain_size = param_size - merged_size; + while (remain_size >= 4) { + temp = *(uint32_t *)payload; + while (mipi_dsi_host_ll_gen_is_write_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_write_payload_fifo(hal->host, temp); + payload += 4; + remain_size -= 4; + } + if (remain_size) { + temp = *(uint32_t *)payload; + temp &= (1 << (8 * remain_size)) - 1; + while (mipi_dsi_host_ll_gen_is_write_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_write_payload_fifo(hal->host, temp); + } + + uint8_t wc_msb = (payload_size >> 8) & 0xFF; + uint8_t wc_lsb = payload_size & 0xFF; + while (mipi_dsi_host_ll_gen_is_cmd_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_set_packet_header(hal->host, vc, MIPI_DSI_DT_DCS_LONG_WRITE, wc_msb, wc_lsb); +} + +void mipi_dsi_hal_host_gen_write_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data) +{ + uint8_t msb = (header_data >> 8) & 0xFF; + uint8_t lsb = header_data & 0xFF; + while (mipi_dsi_host_ll_gen_is_cmd_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_set_packet_header(hal->host, vc, dt, msb, lsb); +} + +void mipi_dsi_hal_host_gen_write_long_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, const void *buffer, uint16_t buffer_size) +{ + const uint8_t *payload = buffer; + uint32_t remain_size = buffer_size; + uint32_t temp = 0; + while (remain_size >= 4) { + temp = *(uint32_t *)payload; + while (mipi_dsi_host_ll_gen_is_write_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_write_payload_fifo(hal->host, temp); + payload += 4; + remain_size -= 4; + } + if (remain_size) { + temp = *(uint32_t *)payload; + temp &= (1 << (8 * remain_size)) - 1; + while (mipi_dsi_host_ll_gen_is_write_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_write_payload_fifo(hal->host, temp); + } + + uint8_t wc_msb = (buffer_size >> 8) & 0xFF; + uint8_t wc_lsb = buffer_size & 0xFF; + while (mipi_dsi_host_ll_gen_is_cmd_fifo_full(hal->host)); + mipi_dsi_host_ll_gen_set_packet_header(hal->host, vc, dt, wc_msb, wc_lsb); +} + +void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size) +{ + uint8_t *receive_buffer = (uint8_t *)ret_buffer; + // set the maximum returned data size, it should equal to the parameter size of the read command + mipi_dsi_hal_host_gen_write_short_packet(hal, vc, MIPI_DSI_DT_SET_MAXIMUM_RETURN_PKT, buffer_size); + // make sure command mode is on + mipi_dsi_host_ll_dpi_enable_video_mode(hal->host, false); + // make sure receiving is enabled + mipi_dsi_host_ll_enable_bta(hal->host, true); + // listen to the same virtual channel as the one sent to + mipi_dsi_host_ll_gen_set_rx_vcid(hal->host, vc); + mipi_dsi_hal_host_gen_write_short_packet(hal, vc, dt, header_data); + while (mipi_dsi_host_ll_gen_is_read_cmd_busy(hal->host)); + // wait data to come into the fifo + while (mipi_dsi_host_ll_gen_is_read_fifo_empty(hal->host)); + uint32_t temp = 0; + uint32_t counter = 0; + while (!mipi_dsi_host_ll_gen_is_read_fifo_empty(hal->host)) { + temp = mipi_dsi_host_ll_gen_read_payload_fifo(hal->host); + for (int i = 0; i < 4; i++) { + if ((counter + i) < buffer_size) { + receive_buffer[counter + i] = (temp >> (8 * i)) & 0xFF; + } + counter++; + } + } +} + +void mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t vc, uint32_t command, uint32_t command_bytes, void *ret_param, uint16_t param_buf_size) +{ + uint16_t header_data = command & ((1 << (8 * command_bytes)) - 1); + mipi_dsi_hal_host_gen_read_short_packet(hal, vc, MIPI_DSI_DT_DCS_READ_0, header_data, ret_param, param_buf_size); +} + +void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config) +{ + mipi_dsi_host_ll_dpi_set_color_coding(hal->host, color_coding, sub_config); + mipi_dsi_brg_ll_set_pixel_format(hal->bridge, color_coding, sub_config); + // please note, we need to call bridge_update to make the new configuration take effect +} + +void mipi_dsi_hal_host_dpi_set_horizontal_timing(mipi_dsi_hal_context_t *hal, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp) +{ + mipi_dsi_host_ll_dpi_set_horizontal_timing(hal->host, + hsw * hal->dpi2lane_clk_ratio, + hbp * hal->dpi2lane_clk_ratio, + active_width * hal->dpi2lane_clk_ratio, + hfp * hal->dpi2lane_clk_ratio); + mipi_dsi_brg_ll_set_horizontal_timing(hal->bridge, hsw, hbp, active_width, hfp); + // please note, we need to call bridge_update to make the new configuration take effect +} + +void mipi_dsi_hal_host_dpi_set_vertical_timing(mipi_dsi_hal_context_t *hal, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp) +{ + mipi_dsi_host_ll_dpi_set_vertical_timing(hal->host, vsw, vbp, active_height, vfp); + mipi_dsi_brg_ll_set_vertical_timing(hal->bridge, vsw, vbp, active_height, vfp); + // please note, we need to call bridge_update to make the new configuration take effect +} diff --git a/components/hal/mmu_hal.c b/components/hal/mmu_hal.c index b60fae6483f..b3ee4918154 100644 --- a/components/hal/mmu_hal.c +++ b/components/hal/mmu_hal.c @@ -31,7 +31,7 @@ void mmu_hal_unmap_all(void) mmu_ll_unmap_all(MMU_LL_PSRAM_MMU_ID); #else mmu_ll_unmap_all(0); -#if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE mmu_ll_unmap_all(1); #endif #endif diff --git a/components/hal/spi_flash_hal_iram.c b/components/hal/spi_flash_hal_iram.c index edcbe9e7ad7..e73ead6ad92 100644 --- a/components/hal/spi_flash_hal_iram.c +++ b/components/hal/spi_flash_hal_iram.c @@ -146,6 +146,9 @@ void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host) spi_mem_dev_t *dev = (spi_mem_dev_t*)spi_flash_ll_get_hw(SPI1_HOST); spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host; spimem_flash_ll_auto_wait_idle_init(dev, true); + if (ctx->freq_mhz == 120) { + spimem_flash_ll_set_wait_idle_dummy_phase(dev, ctx->extra_dummy); + } spimem_flash_ll_auto_suspend_init(dev, true); // tsus = ceil(ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles); uint32_t tsus = (ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->tsus_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index 25b77b8ef6b..ee58edae031 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -12,29 +12,6 @@ #include "soc/soc_caps.h" #include "soc/clk_tree_defs.h" -//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros. -#if SOC_GDMA_SUPPORTED -#if (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AHB) && (SOC_AHB_GDMA_VERSION == 1) -#include "soc/gdma_struct.h" -#include "hal/gdma_ll.h" -#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, chan, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, chan, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable); -#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable); - -#elif (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI) //TODO: IDF-6152, refactor spi hal layer -#include "hal/axi_dma_ll.h" -#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) axi_dma_ll_rx_enable_data_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) axi_dma_ll_tx_enable_data_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) axi_dma_ll_rx_enable_descriptor_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) axi_dma_ll_tx_enable_descriptor_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) axi_dma_ll_tx_enable_auto_write_back(&AXI_DMA, chan, enable); -#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) axi_dma_ll_tx_set_eof_mode(&AXI_DMA, chan, enable); -#endif -#endif //SOC_GDMA_SUPPORTED - /* The tag may be unused if log level is set to NONE */ static const __attribute__((unused)) char SPI_HAL_TAG[] = "spi_hal"; @@ -44,14 +21,6 @@ static const __attribute__((unused)) char SPI_HAL_TAG[] = "spi_hal"; return (ret_val); \ } -static void s_spi_hal_dma_init_config(const spi_hal_context_t *hal) -{ - spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); - spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); - spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); - spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1); -} - void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *config) { memset(hal, 0, sizeof(spi_hal_context_t)); @@ -71,9 +40,6 @@ void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config spi_ll_set_mosi_free_level(hw, 0); #endif spi_ll_master_init(hw); - if (config->dma_enabled) { - s_spi_hal_dma_init_config(hal); - } //Force a transaction done interrupt. This interrupt won't fire yet because //we initialized the SPI interrupt as disabled. This way, we can just diff --git a/components/hal/spi_slave_hal.c b/components/hal/spi_slave_hal.c index c53bd600cad..5d0f570b544 100644 --- a/components/hal/spi_slave_hal.c +++ b/components/hal/spi_slave_hal.c @@ -2,37 +2,6 @@ #include "hal/spi_ll.h" #include "soc/soc_caps.h" -//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros. -#if SOC_GDMA_SUPPORTED -#if (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AHB) && (SOC_AHB_GDMA_VERSION == 1) -#include "soc/gdma_struct.h" -#include "hal/gdma_ll.h" -#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, chan, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, chan, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable); -#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable); - -#elif (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI) //TODO: IDF-6152, refactor spi hal layer -#include "hal/axi_dma_ll.h" -#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) axi_dma_ll_rx_enable_data_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) axi_dma_ll_tx_enable_data_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) axi_dma_ll_rx_enable_descriptor_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) axi_dma_ll_tx_enable_descriptor_burst(&AXI_DMA, chan, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) axi_dma_ll_tx_enable_auto_write_back(&AXI_DMA, chan, enable); -#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) axi_dma_ll_tx_set_eof_mode(&AXI_DMA, chan, enable); -#endif -#endif //SOC_GDMA_SUPPORTED - -static void s_spi_slave_hal_dma_init_config(const spi_slave_hal_context_t *hal) -{ - spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); - spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); - spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); - spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1); -} - void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config) { spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id); @@ -40,9 +9,6 @@ void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config hal->dma_in = hal_config->dma_in; hal->dma_out = hal_config->dma_out; - if (hal->use_dma) { - s_spi_slave_hal_dma_init_config(hal); - } spi_ll_slave_init(hal->hw); //Force a transaction done interrupt. This interrupt won't fire yet because we initialized the SPI interrupt as diff --git a/components/hal/spi_slave_hd_hal.c b/components/hal/spi_slave_hd_hal.c index ff7d48abb2d..a62a5172698 100644 --- a/components/hal/spi_slave_hd_hal.c +++ b/components/hal/spi_slave_hd_hal.c @@ -27,10 +27,6 @@ #define spi_dma_ll_rx_restart(dev, chan) gdma_ll_rx_restart(&GDMA, chan) #define spi_dma_ll_rx_reset(dev, chan) gdma_ll_rx_reset_channel(&GDMA, chan) #define spi_dma_ll_tx_reset(dev, chan) gdma_ll_tx_reset_channel(&GDMA, chan) -#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable) -#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, chan, enable) -#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, chan, enable) -#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, chan, enable) #define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable) #define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable) #define spi_dma_ll_get_out_eof_desc_addr(dev, chan) gdma_ll_tx_get_eof_desc_addr(&GDMA, chan) @@ -50,10 +46,6 @@ #define spi_dma_ll_rx_restart(dev, chan) axi_dma_ll_rx_restart(&AXI_DMA, chan) #define spi_dma_ll_rx_reset(dev, chan) axi_dma_ll_rx_reset_channel(&AXI_DMA, chan) #define spi_dma_ll_tx_reset(dev, chan) axi_dma_ll_tx_reset_channel(&AXI_DMA, chan) -#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) axi_dma_ll_rx_enable_data_burst(&AXI_DMA, chan, enable) -#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) axi_dma_ll_tx_enable_data_burst(&AXI_DMA, chan, enable) -#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) axi_dma_ll_rx_enable_descriptor_burst(&AXI_DMA, chan, enable) -#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) axi_dma_ll_tx_enable_descriptor_burst(&AXI_DMA, chan, enable) #define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) axi_dma_ll_tx_enable_auto_write_back(&AXI_DMA, chan, enable) #define spi_dma_ll_set_out_eof_generation(dev, chan, enable) axi_dma_ll_tx_set_eof_mode(&AXI_DMA, chan, enable) #define spi_dma_ll_get_out_eof_desc_addr(dev, chan) axi_dma_ll_tx_get_eof_desc_addr(&AXI_DMA, chan) @@ -71,10 +63,6 @@ static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal) { - spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); - spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); - spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); - spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1); spi_dma_ll_enable_out_auto_wrback(hal->dma_out, hal->tx_dma_chan, 1); spi_dma_ll_set_out_eof_generation(hal->dma_out, hal->tx_dma_chan, 1); } diff --git a/components/hal/systimer_hal.c b/components/hal/systimer_hal.c index 728534b7bb9..658bfaad47d 100644 --- a/components/hal/systimer_hal.c +++ b/components/hal/systimer_hal.c @@ -31,12 +31,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal) hal->dev = NULL; } -void systimer_hal_set_clock_source(systimer_hal_context_t *hal, systimer_clock_source_t clk_src) -{ - (void)hal; - systimer_ll_set_clock_source(clk_src); -} - systimer_clock_source_t systimer_hal_get_clock_source(systimer_hal_context_t *hal) { (void)hal; diff --git a/components/hal/test_apps/crypto/README.md b/components/hal/test_apps/crypto/README.md index 6c4d3af205c..f9ee480507d 100644 --- a/components/hal/test_apps/crypto/README.md +++ b/components/hal/test_apps/crypto/README.md @@ -76,34 +76,36 @@ espefuse.py -p $ESPPORT burn_key BLOCK_KEY4 main/hmac/hmac_key.bin HMAC_UP # Burning the HMAC keys for Digital Signature tests -The tests needs some HMAC keys to be burned in the `BLOCK_KEY1`, `BLOCK_KEY2` and `BLOCK_KEY3` of the efuses. As this verification application is independent of the efuse component, the user needs to manually burn the keys and their key purposes using `espefuse.py`. +The tests needs some HMAC keys to be burned in the `BLOCK_KEY0`, `BLOCK_KEY1` and `BLOCK_KEY2` of the efuses. As this verification application is independent of the efuse component, the user needs to manually burn the keys and their key purposes using `espefuse.py`. If SOC_DS_SIGNATURE_MAX_BIT_LEN == 3072: ```bash -espefuse.py -p $ESPPORT burn_key BLOCK_KEY1 main/ds/keys/3072/ds_key1.bin HMAC_DOWN_DIGITAL_SIGNATURE +espefuse.py -p $ESPPORT burn_key BLOCK_KEY0 main/ds/keys/3072/ds_key1.bin HMAC_DOWN_DIGITAL_SIGNATURE -espefuse.py -p $ESPPORT burn_key BLOCK_KEY2 main/ds/keys/3072/ds_key2.bin HMAC_DOWN_DIGITAL_SIGNATURE +espefuse.py -p $ESPPORT burn_key BLOCK_KEY1 main/ds/keys/3072/ds_key2.bin HMAC_DOWN_DIGITAL_SIGNATURE -espefuse.py -p $ESPPORT burn_key BLOCK_KEY3 main/ds/keys/3072/ds_key3.bin HMAC_DOWN_DIGITAL_SIGNATURE +espefuse.py -p $ESPPORT burn_key BLOCK_KEY2 main/ds/keys/3072/ds_key3.bin HMAC_DOWN_DIGITAL_SIGNATURE ``` If SOC_DS_SIGNATURE_MAX_BIT_LEN == 4096: ```bash -espefuse.py -p $ESPPORT burn_key BLOCK_KEY1 main/ds/keys/4096/ds_key1.bin HMAC_DOWN_DIGITAL_SIGNATURE +espefuse.py -p $ESPPORT burn_key BLOCK_KEY0 main/ds/keys/4096/ds_key1.bin HMAC_DOWN_DIGITAL_SIGNATURE -espefuse.py -p $ESPPORT burn_key BLOCK_KEY2 main/ds/keys/4096/ds_key2.bin HMAC_DOWN_DIGITAL_SIGNATURE +espefuse.py -p $ESPPORT burn_key BLOCK_KEY1 main/ds/keys/4096/ds_key2.bin HMAC_DOWN_DIGITAL_SIGNATURE -espefuse.py -p $ESPPORT burn_key BLOCK_KEY3 main/ds/keys/4096/ds_key3.bin HMAC_DOWN_DIGITAL_SIGNATURE +espefuse.py -p $ESPPORT burn_key BLOCK_KEY2 main/ds/keys/4096/ds_key3.bin HMAC_DOWN_DIGITAL_SIGNATURE ``` # Burning the ECDSA keys -The ECDSA tests need some ECDSA keys to be burned in the `BLOCK_KEY1` and `BLOCK_KEY2` of the efuses. As this verification application is independent of the efuse component, the user needs to manually burn the keys and their key purposes using `espefuse.py`. +By default, ECDSA tests are disabled. You can enable it after disabling HMAC tests using `idf.py menuconfig -> Test App Configuration -> Enable ECDSA Peripheral test cases` + +The ECDSA tests need some ECDSA keys to be burned in the `BLOCK_KEY4` and `BLOCK_KEY5` of the efuses. As this verification application is independent of the efuse component, the user needs to manually burn the keys and their key purposes using `espefuse.py`. ```bash -espefuse.py -p $ESPPORT burn_key BLOCK_KEY1 main/ecdsa/ecdsa192_priv_key.pem ECDSA_KEY +espefuse.py -p $ESPPORT burn_key BLOCK_KEY4 main/ecdsa/ecdsa192_priv_key.pem ECDSA_KEY -espefuse.py -p $ESPPORT burn_key BLOCK_KEY2 main/ecdsa/ecdsa256_priv_key.pem ECDSA_KEY +espefuse.py -p $ESPPORT burn_key BLOCK_KEY5 main/ecdsa/ecdsa256_priv_key.pem ECDSA_KEY ``` # Building diff --git a/components/hal/test_apps/crypto/main/CMakeLists.txt b/components/hal/test_apps/crypto/main/CMakeLists.txt index add281587e8..d782ffb32e7 100644 --- a/components/hal/test_apps/crypto/main/CMakeLists.txt +++ b/components/hal/test_apps/crypto/main/CMakeLists.txt @@ -33,5 +33,7 @@ if(CONFIG_SOC_SHA_SUPPORTED) endif() idf_component_register(SRCS ${srcs} + PRIV_REQUIRES efuse REQUIRES test_utils unity - WHOLE_ARCHIVE) + WHOLE_ARCHIVE + PRIV_INCLUDE_DIRS ".") diff --git a/components/hal/test_apps/crypto/main/Kconfig.projbuild b/components/hal/test_apps/crypto/main/Kconfig.projbuild new file mode 100644 index 00000000000..41adba48b04 --- /dev/null +++ b/components/hal/test_apps/crypto/main/Kconfig.projbuild @@ -0,0 +1,22 @@ +menu "Test App Configuration" + + config CRYPTO_TEST_APP_ENABLE_DS_TESTS + bool "Enable DS Peripheral test cases" + default y + help + Enabling this option includes DS Peripheral related test cases in the build for supported targets. + + config CRYPTO_TEST_APP_ENABLE_HMAC_TESTS + bool "Enable HMAC Peripheral test cases" + default y + help + Enabling this option includes HMAC Peripheral related test cases in the build for supported targets. + + config CRYPTO_TEST_APP_ENABLE_ECDSA_TESTS + depends on !CRYPTO_TEST_APP_ENABLE_HMAC_TESTS + bool "Enable ECDSA Peripheral test cases" + default n + help + Enabling this option includes ECDSA Peripheral related test cases in the build for supported targets. + +endmenu diff --git a/components/hal/test_apps/crypto/main/app_main.c b/components/hal/test_apps/crypto/main/app_main.c index f33712ac24e..6708b7a7685 100644 --- a/components/hal/test_apps/crypto/main/app_main.c +++ b/components/hal/test_apps/crypto/main/app_main.c @@ -32,15 +32,15 @@ static void run_all_tests(void) #if CONFIG_IDF_ENV_FPGA -#if CONFIG_SOC_HMAC_SUPPORTED +#if CONFIG_SOC_HMAC_SUPPORTED && CONFIG_CRYPTO_TEST_APP_ENABLE_HMAC_TESTS RUN_TEST_GROUP(hmac); #endif -#if CONFIG_SOC_DIG_SIGN_SUPPORTED +#if CONFIG_SOC_DIG_SIGN_SUPPORTED && CONFIG_CRYPTO_TEST_APP_ENABLE_DS_TESTS RUN_TEST_GROUP(ds); #endif -#if CONFIG_SOC_ECDSA_SUPPORTED +#if CONFIG_SOC_ECDSA_SUPPORTED && CONFIG_CRYPTO_TEST_APP_ENABLE_ECDSA_TESTS RUN_TEST_GROUP(ecdsa) #endif diff --git a/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_3072.h b/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_3072.h index 8d277847ceb..70fe3c48c79 100644 --- a/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_3072.h +++ b/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_3072.h @@ -5,6 +5,9 @@ * * File generated by gen_digital_signature_tests.py */ + +#include "hal_crypto_common.h" + #define NUM_HMAC_KEYS 3 static const uint8_t test_hmac_keys[NUM_HMAC_KEYS][32] = { @@ -38,8 +41,6 @@ static const uint32_t test_messages[NUM_MESSAGES][3072/32] = { { 0x08b2bdd7, 0xb9e4f5e9, 0x2298b215, 0xed9042e0, 0xd93a60dd, 0x14f08d95, 0xe9f669fe, 0x196b10fb, 0xceb6f5a5, 0xe19255c5, 0x1ebb83b2, 0xb4655473, 0xa6b79c9d, 0x88fe4dd9, 0x3546e18a, 0x6dc61f68, 0xc45d3b39, 0x061ee6ff, 0x9c85aaa3, 0x5ad24b87, 0x8ee06618, 0xc5292e42, 0x92bf8b73, 0x23124856, 0x85272862, 0xb284fbed, 0x6212d764, 0x7ee3f935, 0x3b386c35, 0xc694dd1f, 0xa6e068c2, 0xc8cad857, 0x5efd0a73, 0xceec5084, 0xfbb88a02, 0xb09d042d, 0x4e45d49f, 0xb430b6e7, 0xc63934a8, 0x212701f8, 0x6220074a, 0xd88103c3, 0x3312698b, 0x4e0bd933, 0x37b85cbd, 0x2cd97e09, 0x5014b36e, 0x57c8399f, 0xa6427d45, 0x57381c5d, 0x689adc4b, 0x48f893c3, 0x40b902a1, 0x130048cd, 0xa158e363, 0xf3a58a8a, 0x6b3ea545, 0xd6b51dc4, 0xe65db148, 0x5bf8ad29, 0x44257142, 0x92e0deb9, 0xb9cfbe30, 0x83b5cc31, 0x401feebc, 0x70d8ed1a, 0x6a77f25b, 0xed4bb4ba, 0x6a69e8a3, 0xe72c1f3a, 0xf9f67b2d, 0x64a13cdd, 0xc3268e68, 0xa5a33132, 0x6b10626a, 0xb48a00a3, 0xffc1ab2e, 0x4ae98114, 0xf571d6d5, 0x1c068302, 0xca5fe2a9, 0xc7f43921, 0x5b82d397, 0x43a210b2, 0x7b58af9e, 0x6232c22a, 0xc51f2306, 0xfcd5d566, 0x76c5e2e7, 0x8b77942e, 0xd9323119, 0xe3eb7011, 0xe8a1bc8e, 0xc02bf571, 0x90799da8, 0x76f308ea }, }; - - #define NUM_CASES 6 static const encrypt_testcase_t test_cases[NUM_CASES] = { @@ -53,7 +54,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 95, // 3072 bit }, .expected_c = { 0xa7, 0x3e, 0x23, 0x1f, 0x22, 0x91, 0xfa, 0xfe, 0x59, 0x13, 0x9d, 0x3d, 0x2b, 0x40, 0xdc, 0xa8, 0xe6, 0x7d, 0xf2, 0x4d, 0x03, 0x4c, 0x80, 0x87, 0x7d, 0x05, 0x71, 0x8b, 0x04, 0xee, 0xd6, 0x95, 0x8d, 0x87, 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0x0f, 0x18, 0xd8, 0x7f }, - .hmac_key_idx = 0, + .hmac_key_idx = DS_KEY_BLOCK_1, // results of message array encrypted with these keys .expected_results = { // Message 0 @@ -78,7 +79,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 63, // 2048 bit }, .expected_c = { 0x42, 0x29, 0xab, 0xdc, 0x8a, 0x08, 0x04, 0x91, 0x78, 0x2a, 0xa5, 0x6b, 0x3f, 0x2a, 0x1c, 0xf1, 0xd6, 0xda, 0x35, 0x54, 0x4a, 0xa1, 0x78, 0xc3, 0x6d, 0x95, 0xda, 0x0d, 0xe3, 0xd4, 0xfc, 0x36, 0xcd, 0x65, 0x7c, 0x86, 0xdf, 0x5b, 0x19, 0xe7, 0x90, 0x2a, 0x7a, 0xa9, 0x23, 0x38, 0xb5, 0xa1, 0x95, 0x55, 0xb7, 0xa0, 0x27, 0xb1, 0xa1, 0x32, 0xd3, 0xad, 0x42, 0xd5, 0x73, 0x51, 0xbe, 0x6f, 0x6e, 0x3a, 0x37, 0x1e, 0x71, 0x56, 0xa2, 0x2f, 0x7b, 0xf3, 0xa7, 0x42, 0xc7, 0x98, 0xfd, 0x33, 0xcc, 0x55, 0x8d, 0x56, 0x5b, 0xfb, 0x4b, 0x6b, 0x18, 0x28, 0xad, 0xf9, 0x14, 0x16, 0x49, 0xd5, 0x75, 0x6b, 0xef, 0xc3, 0x51, 0x89, 0x2c, 0x53, 0xfa, 0x91, 0x09, 0xc2, 0x18, 0x99, 0xcc, 0x1e, 0x31, 0xb1, 0x5d, 0xcf, 0x6b, 0x94, 0xbe, 0x5c, 0xa4, 0x45, 0xae, 0x82, 0x7f, 0xd3, 0x9c, 0xf7, 0xb9, 0xee, 0xb8, 0x52, 0xb0, 0x2f, 0xce, 0xd6, 0x34, 0x22, 0xdd, 0x69, 0x72, 0x3a, 0x51, 0xe9, 0x2e, 0x70, 0x2c, 0x00, 0x3f, 0x71, 0x11, 0x56, 0xc5, 0x83, 0x12, 0x64, 0xf5, 0x1a, 0xb4, 0x0f, 0xcb, 0x79, 0xb7, 0x8a, 0xf8, 0x07, 0xc5, 0x96, 0x1a, 0xbc, 0xd1, 0xd9, 0xad, 0x83, 0x6c, 0x37, 0xac, 0xa9, 0xc4, 0x1c, 0xcd, 0x7a, 0xfc, 0x39, 0xee, 0xf4, 0xfd, 0xee, 0x18, 0x02, 0x69, 0x9a, 0xdf, 0x2d, 0x2b, 0xbe, 0x87, 0xc6, 0xec, 0xd3, 0xd3, 0xf5, 0xc4, 0x4c, 0x84, 0xe2, 0xf3, 0xcc, 0xc5, 0xe8, 0x9b, 0x3e, 0x9b, 0x16, 0x45, 0xd8, 0xcd, 0x90, 0xf1, 0x92, 0xf1, 0x35, 0x30, 0xcf, 0x5a, 0xf8, 0xb9, 0x52, 0x00, 0xb8, 0x36, 0xde, 0x3c, 0x85, 0x8d, 0xcc, 0x62, 0x2c, 0x04, 0x56, 0x41, 0x29, 0x96, 0x66, 0xdf, 0xbe, 0xb3, 0x95, 0x49, 0xda, 0xed, 0x6c, 0x28, 0x6a, 0x71, 0xf4, 0x2a, 0x8f, 0xc5, 0x22, 0x58, 0xc9, 0x2c, 0x8a, 0x4c, 0xc3, 0xe8, 0xc5, 0x90, 0x78, 0xea, 0x1b, 0x6e, 0xf6, 0x97, 0xa7, 0x9b, 0x72, 0x07, 0xec, 0xbf, 0xbb, 0x48, 0x2a, 0x85, 0xdb, 0xf9, 0x58, 0x51, 0xcc, 0x23, 0x7c, 0x32, 0x24, 0xb6, 0xdd, 0xa8, 0xbd, 0xfb, 0x27, 0x8f, 0xf0, 0x74, 0xec, 0x6b, 0xed, 0x36, 0x68, 0x30, 0xec, 0x6d, 0x0f, 0x6d, 0xe4, 0x9c, 0x31, 0x80, 0x32, 0x66, 0x80, 0x89, 0x5f, 0x3e, 0x3d, 0xba, 0x3b, 0xba, 0xec, 0x56, 0xbe, 0x60, 0xdb, 0x2e, 0xad, 0xd4, 0xb7, 0xf7, 0xf6, 0x48, 0x54, 0x47, 0xc3, 0x69, 0x72, 0xf0, 0x40, 0x93, 0xb6, 0x7e, 0x91, 0x76, 0x68, 0x32, 0xcb, 0xcb, 0x70, 0x10, 0x26, 0xa9, 0xfa, 0x44, 0x1b, 0x03, 0x3c, 0x24, 0x0f, 0xa2, 0xa2, 0xb1, 0x0c, 0xf5, 0x6c, 0x1d, 0x14, 0xd1, 0x10, 0x44, 0x27, 0x4f, 0x5b, 0xa9, 0x2d, 0xd8, 0x82, 0x6b, 0xce, 0xc7, 0xdf, 0x7a, 0x55, 0x68, 0x57, 0xb7, 0xc9, 0xf0, 0x7a, 0x35, 0xd8, 0x34, 0x3d, 0x2e, 0xf8, 0x9e, 0x1d, 0x27, 0x0c, 0xdc, 0xa0, 0x9e, 0x40, 0xa3, 0x01, 0x7e, 0xef, 0x94, 0x08, 0x4a, 0xa1, 0x22, 0xe1, 0xe7, 0x89, 0x9d, 0x18, 0x60, 0x92, 0xf7, 0xfc, 0x95, 0x96, 0xd8, 0x9e, 0x59, 0x6c, 0xcd, 0xd6, 0xec, 0xde, 0xe8, 0xf3, 0x0e, 0xb5, 0x24, 0x85, 0x6a, 0xb7, 0x2b, 0x82, 0xdb, 0x09, 0x5d, 0xd9, 0x4e, 0xd5, 0x09, 0xd6, 0x15, 0x18, 0x62, 0x01, 0x34, 0x7f, 0x65, 0x5f, 0x44, 0xc4, 0x47, 0xa2, 0x0f, 0x7d, 0xf4, 0xa8, 0xa8, 0x87, 0xef, 0x11, 0x2a, 0x48, 0xef, 0x10, 0xad, 0x62, 0xf6, 0x9d, 0x15, 0x9f, 0x41, 0x3d, 0xac, 0x15, 0x29, 0xa5, 0x91, 0x5c, 0x10, 0xa6, 0x77, 0xe8, 0x6c, 0x0a, 0xa2, 0x79, 0xf1, 0x0c, 0x48, 0x04, 0x4a, 0xb3, 0x6b, 0xf3, 0x5c, 0xa6, 0x33, 0x84, 0x28, 0xde, 0xc6, 0x0a, 0x6c, 0x97, 0xbf, 0x09, 0xc8, 0xd1, 0x6a, 0x68, 0x70, 0x24, 0x89, 0xd7, 0xbb, 0x01, 0x34, 0xe1, 0xed, 0x10, 0x71, 0xac, 0xf3, 0xfd, 0x76, 0xeb, 0x56, 0x8a, 0xe0, 0x5e, 0x48, 0xee, 0xc9, 0xe8, 0x9c, 0x06, 0x26, 0xcc, 0x94, 0x70, 0x5c, 0x7c, 0x36, 0xc0, 0xf5, 0x29, 0xb3, 0xbb, 0x6a, 0x58, 0x31, 0x8d, 0x6f, 0xd1, 0x45, 0xc5, 0x11, 0xae, 0x4e, 0x2b, 0xf1, 0x29, 0xbf, 0x38, 0xc4, 0x48, 0x5c, 0x8b, 0x01, 0xe7, 0xce, 0x4c, 0xf7, 0x78, 0xfb, 0x98, 0x6f, 0x64, 0x3e, 0x96, 0x82, 0x0c, 0xc8, 0xc7, 0x64, 0x7e, 0x31, 0x5b, 0xdc, 0x43, 0x83, 0xfd, 0x97, 0xd7, 0x25, 0x43, 0x23, 0x72, 0x1e, 0x61, 0xa6, 0x51, 0x77, 0x44, 0x02, 0x3f, 0xee, 0x26, 0xf1, 0xa9, 0xc6, 0x6b, 0x97, 0x2e, 0x25, 0x4b, 0xc8, 0xff, 0x35, 0x15, 0x6b, 0x6f, 0xbd, 0x5e, 0x19, 0x58, 0xa0, 0x23, 0xee, 0x80, 0xd4, 0xd9, 0xbc, 0x52, 0xc8, 0xfc, 0xb5, 0x8c, 0x8e, 0xaf, 0x36, 0x81, 0x36, 0x96, 0xca, 0x5e, 0xdf, 0xe1, 0xa2, 0xda, 0x17, 0x90, 0x40, 0xe5, 0x7f, 0x0b, 0x2b, 0x02, 0xea, 0x79, 0x4c, 0xad, 0x74, 0x3b, 0x82, 0x93, 0x74, 0xec, 0x1b, 0xa1, 0xcd, 0xcd, 0x1a, 0xe3, 0x2e, 0xdd, 0x80, 0xf3, 0x32, 0x76, 0x9b, 0xf4, 0x1d, 0xa4, 0xf1, 0xe2, 0x0e, 0xc3, 0x7f, 0xdc, 0xdf, 0x06, 0xcd, 0x79, 0xfc, 0xde, 0x0b, 0xfd, 0x65, 0x7a, 0xdf, 0x39, 0xe3, 0x68, 0x02, 0x8e, 0x2a, 0x5d, 0xe2, 0x0f, 0x15, 0x7b, 0x2f, 0x9e, 0xc7, 0xa7, 0x95, 0xac, 0x4d, 0xb6, 0xad, 0x15, 0xff, 0x6a, 0x9e, 0x5d, 0xe3, 0xca, 0x33, 0xb3, 0x9f, 0x38, 0x1c, 0x6b, 0x32, 0xfc, 0x7c, 0xdb, 0x88, 0xf2, 0xfe, 0xe8, 0x5b, 0x82, 0x67, 0x60, 0x5a, 0x0e, 0xdc, 0xb8, 0xc6, 0x5d, 0x4e, 0x39, 0x19, 0xea, 0x85, 0x33, 0xd2, 0xf1, 0xc1, 0xc9, 0xee, 0x07, 0xae, 0xc2, 0xfe, 0x1d, 0xa4, 0x78, 0xef, 0x68, 0xf8, 0x86, 0xd3, 0xe4, 0xa7, 0x13, 0x21, 0x95, 0x9d, 0xfb, 0xc7, 0x70, 0x7d, 0xd2, 0xba, 0xb2, 0x0f, 0x83, 0x64, 0xc1, 0x0b, 0xbc, 0xca, 0xc2, 0x97, 0x1b, 0x5a, 0x8e, 0x97, 0xa7, 0x75, 0x2f, 0x9f, 0xb1, 0x48, 0xc7, 0x47, 0x77, 0xff, 0x69, 0x2a, 0xc5, 0x7d, 0x1f, 0x30, 0x27, 0x57, 0x55, 0x6c, 0xea, 0x60, 0x48, 0xeb, 0x57, 0x48, 0x4e, 0xb9, 0xa5, 0x96, 0x00, 0xe2, 0x37, 0x31, 0x21, 0xc5, 0x3e, 0x51, 0x0d, 0x16, 0xa4, 0x3e, 0x9a, 0x10, 0xf9, 0xe3, 0xa8, 0x55, 0xb8, 0x76, 0x66, 0x27, 0xce, 0x83, 0x06, 0x9d, 0xd2, 0xd2, 0x6f, 0x47, 0x6b, 0x16, 0x39, 0xb9, 0xf4, 0x0d, 0xa0, 0x50, 0x53, 0x46, 0x44, 0xec, 0xa3, 0xf9, 0xb0, 0x4e, 0x47, 0x39, 0xd6, 0x4b, 0xe6, 0xe6, 0x48, 0x7f, 0x90, 0xa6, 0x31, 0x20, 0xd7, 0x21, 0x39, 0x7a, 0x9b, 0x60, 0x87, 0xa3, 0xf8, 0x26, 0xda, 0xb0, 0xc1, 0xa8, 0x42, 0x6b, 0xba, 0xdb, 0xc9, 0xd4, 0x84, 0x23, 0x7f, 0x10, 0xcb, 0x84, 0xfa, 0x88, 0xa9, 0x41, 0xa2, 0x69, 0x94, 0x8c, 0x9c, 0xdf, 0xc6, 0x68, 0x2a, 0x89, 0x8e, 0x7a, 0x9f, 0x85, 0x9c, 0xe4, 0x7a, 0xac, 0x76, 0x87, 0x47, 0x4d, 0x45, 0x2d, 0x05, 0x4f, 0x23, 0x9d, 0x3a, 0x42, 0x83, 0xdb, 0x5c, 0xef, 0xaa, 0xfd, 0xc9, 0x26, 0x35, 0xa9, 0x03, 0x5f, 0xc4, 0x67, 0xc0, 0xb6, 0x97, 0x06, 0xf6, 0x90, 0xbe, 0xc7, 0x68, 0x53, 0xc6, 0xf0, 0x42, 0x5f, 0x1b, 0x4f, 0x2e, 0x13, 0x63, 0xc6, 0x3d, 0x01, 0xbd, 0x42, 0x43, 0xe3, 0x9b, 0xc9, 0x2f, 0x59, 0xf3, 0x84, 0xd6, 0xaa, 0x76, 0x06, 0xb3, 0x89, 0x4f, 0x9a, 0xdd, 0xf6, 0xb0, 0x05, 0xf8, 0x82, 0xfe, 0x2a, 0x29, 0x19, 0x29, 0xf7, 0x1a, 0x07, 0x2f, 0xba, 0x9f, 0xee, 0xdb, 0x7d, 0x20, 0x43, 0x00, 0x94, 0xac, 0xe1, 0x5d, 0x78, 0x07, 0x55, 0x65, 0xb4, 0x95, 0x70, 0x5e, 0xc5, 0x51, 0x78, 0xde, 0x4b, 0x6d, 0x28, 0x6f, 0x97, 0xa8, 0x31, 0x39, 0xbf, 0x2c, 0x7a, 0xbd, 0x2c, 0x98, 0x67, 0xf8, 0xcb, 0x5d, 0x4b, 0xbd, 0x20, 0x44, 0x07, 0x3b, 0x94, 0x1a, 0x1d, 0x7e, 0x63, 0xf6, 0xa8, 0xf7, 0x0a, 0x5b, 0x08, 0xe8, 0xd1, 0xa3, 0x0c, 0x37, 0xd2, 0x32, 0xe5, 0x36, 0x26, 0x24, 0x56, 0xe6, 0xb2, 0x3a, 0xae, 0x87, 0x16, 0xd9, 0xd5, 0x66, 0x3c, 0x06, 0x3a, 0x24, 0x9f, 0x8b, 0x7a, 0xe3, 0x35, 0xe1, 0xb0, 0x77, 0x69, 0xd9, 0x37, 0x42, 0x7f, 0xb0, 0xd6, 0x10, 0x18, 0xee, 0x27, 0x2b, 0xe2, 0x5b, 0xe7, 0xcc, 0x1f, 0x8f, 0x78, 0x8a, 0x28, 0x5d, 0x1c, 0xc5, 0xca, 0xf5, 0xf8, 0x10, 0x3d, 0xf4, 0x71, 0xc9, 0x40, 0xe3, 0x13, 0xaa, 0x0e, 0x2a, 0x1f, 0xe5, 0x8e, 0x9e, 0x8a, 0x1b, 0xbb, 0x6c, 0x7f, 0x1b, 0x97, 0x2e, 0xa9, 0xc0, 0x8d, 0x03, 0x8f, 0x41, 0x55, 0xc2, 0xa2, 0x46, 0xd3, 0x89, 0xad, 0xe4, 0xf4, 0xbf, 0x1c, 0xc4, 0xd7, 0x7e, 0x77, 0xce, 0x48, 0x00 }, - .hmac_key_idx = 0, + .hmac_key_idx = DS_KEY_BLOCK_1, // results of message array encrypted with these keys .expected_results = { // Message 0 @@ -103,7 +104,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 31, // 1024 bit }, .expected_c = { 0xe0, 0x77, 0x7a, 0xd4, 0xf2, 0xdc, 0x37, 0x20, 0xd9, 0xc7, 0x46, 0x3a, 0xf8, 0x36, 0x1f, 0x17, 0x1c, 0x28, 0x5e, 0xa3, 0x12, 0x8e, 0x60, 0x15, 0xdd, 0x11, 0xd9, 0xdb, 0x1c, 0xf1, 0x02, 0x32, 0x82, 0xff, 0xe0, 0x29, 0x30, 0x7d, 0x1a, 0x68, 0x98, 0x3a, 0x7b, 0x18, 0xd2, 0x37, 0x55, 0x1f, 0x4c, 0xf3, 0x8a, 0x9e, 0xe8, 0xed, 0x40, 0xf4, 0x95, 0xce, 0xc3, 0xa8, 0x9d, 0xfe, 0x39, 0x41, 0x39, 0x96, 0x43, 0xcd, 0x45, 0x06, 0x53, 0xac, 0x9e, 0x5e, 0x9d, 0x75, 0x34, 0x19, 0xec, 0x19, 0x79, 0xd8, 0x39, 0x9d, 0x98, 0x67, 0x83, 0x77, 0x70, 0xc9, 0x38, 0x22, 0x5f, 0x3e, 0x40, 0xfe, 0x53, 0x3e, 0xf8, 0x97, 0xd3, 0x1c, 0xe1, 0xeb, 0x04, 0x59, 0xf5, 0xd6, 0x10, 0xdf, 0x6d, 0xd4, 0x52, 0xae, 0x13, 0x32, 0x63, 0x0b, 0xdf, 0x0a, 0xfa, 0x5f, 0xa2, 0x87, 0x17, 0xb9, 0xe4, 0x37, 0xed, 0xa7, 0xf7, 0x8b, 0x42, 0xf7, 0x94, 0x13, 0x7e, 0x0f, 0x6a, 0x1a, 0x56, 0x1d, 0x52, 0x09, 0x1d, 0x07, 0x25, 0x90, 0xa8, 0xd7, 0x4f, 0xf6, 0xe8, 0xa2, 0x5a, 0x28, 0xb3, 0xac, 0x5f, 0x8b, 0xe1, 0x01, 0xeb, 0x30, 0x3e, 0x41, 0xd9, 0x99, 0x8a, 0x40, 0x88, 0x1e, 0xd2, 0x58, 0x82, 0x74, 0x66, 0x85, 0x10, 0x90, 0x70, 0x70, 0x3c, 0x98, 0x44, 0xa8, 0xa6, 0x5b, 0x92, 0x89, 0x81, 0x08, 0x69, 0x3c, 0xe4, 0x5e, 0xf4, 0x2b, 0xec, 0xf5, 0x46, 0x28, 0xba, 0x52, 0xce, 0xac, 0xe7, 0x1b, 0xa5, 0x85, 0x47, 0xd2, 0x6f, 0x20, 0xe0, 0x13, 0xf5, 0xa5, 0xe9, 0x91, 0x3c, 0x3b, 0xe5, 0xaa, 0x1f, 0xeb, 0x31, 0xf7, 0x00, 0x57, 0xbb, 0x07, 0x97, 0x4f, 0xdf, 0x60, 0xfb, 0xdc, 0x83, 0xf3, 0xb0, 0xc9, 0xe9, 0x6c, 0x86, 0x91, 0x1f, 0xa5, 0xd3, 0xd5, 0x23, 0x93, 0x95, 0x0d, 0x0f, 0x45, 0x2c, 0x94, 0x1e, 0x29, 0x54, 0xa3, 0xee, 0x67, 0xf0, 0xca, 0x28, 0xcc, 0x69, 0xc6, 0x10, 0xd6, 0xe9, 0x92, 0x4b, 0xfa, 0xaa, 0xae, 0xd2, 0x21, 0x32, 0x7a, 0xf2, 0x28, 0xdb, 0x30, 0xff, 0x06, 0x23, 0x2b, 0xad, 0xa6, 0xb7, 0xd1, 0x24, 0x83, 0x5e, 0x19, 0x56, 0xb8, 0x73, 0xf6, 0x34, 0x08, 0xef, 0x1f, 0x46, 0xd6, 0x3b, 0xb0, 0xfc, 0x43, 0x87, 0xd6, 0xf3, 0x91, 0x97, 0x1d, 0xcd, 0xa0, 0x04, 0x9f, 0xcf, 0xe9, 0xa3, 0x60, 0x68, 0x32, 0x06, 0xe1, 0x33, 0xeb, 0xf1, 0x63, 0x4f, 0x9a, 0xc9, 0xc3, 0xcd, 0x34, 0x07, 0x6d, 0x3b, 0x9e, 0xc3, 0xd5, 0xb1, 0x9c, 0xb1, 0x46, 0x32, 0xe5, 0x8d, 0x96, 0xb5, 0xdc, 0x64, 0x04, 0xd0, 0x89, 0x8e, 0xd7, 0xc7, 0x82, 0x4e, 0x30, 0x8f, 0xde, 0xce, 0x9f, 0xac, 0x17, 0xf3, 0xc0, 0x31, 0x9f, 0x72, 0xd3, 0x27, 0x42, 0xcb, 0x7f, 0x76, 0x75, 0xec, 0x75, 0xe2, 0x33, 0x1b, 0xca, 0xb2, 0x16, 0x18, 0xe5, 0x41, 0xcc, 0x7b, 0x2b, 0x5d, 0x04, 0x43, 0x77, 0x9d, 0x72, 0x53, 0xfb, 0x56, 0xb2, 0xf7, 0x4b, 0x03, 0x08, 0xf6, 0xa7, 0x23, 0x39, 0x17, 0x44, 0x91, 0xc9, 0x8b, 0xab, 0x8b, 0x40, 0xf3, 0x43, 0xb5, 0x04, 0x69, 0xca, 0x11, 0x3f, 0xca, 0x39, 0xa2, 0xbd, 0xea, 0x84, 0x15, 0xe0, 0x2e, 0x1c, 0x6e, 0xe4, 0x7c, 0x23, 0x1e, 0xd9, 0xb9, 0x91, 0xe3, 0x26, 0x49, 0xdb, 0x53, 0x66, 0xbc, 0xe7, 0x3e, 0xb9, 0xa8, 0xa7, 0x7c, 0xed, 0xe1, 0xf5, 0xaf, 0x7a, 0xd2, 0x53, 0x88, 0x4e, 0x2b, 0x98, 0x81, 0x56, 0xbe, 0xae, 0xcc, 0x96, 0x4d, 0x50, 0x22, 0x8d, 0xdc, 0x04, 0x31, 0xf3, 0xf7, 0x7d, 0x2a, 0xfa, 0xbb, 0x9d, 0x23, 0x4e, 0xc1, 0xb7, 0x3a, 0xfb, 0xae, 0x4f, 0x3f, 0xf0, 0x1b, 0xd3, 0xe1, 0x50, 0x41, 0xf4, 0x91, 0x58, 0xcb, 0x01, 0x43, 0xaa, 0xff, 0xde, 0x71, 0xaf, 0x49, 0x59, 0x9e, 0x9b, 0xc4, 0x48, 0xb1, 0xfa, 0x82, 0xd0, 0xe2, 0x96, 0xee, 0x88, 0xf3, 0x63, 0xdc, 0x52, 0x9c, 0x49, 0x08, 0xb0, 0x17, 0xa6, 0xcc, 0x7c, 0xbd, 0xc4, 0x8d, 0x5e, 0x40, 0x81, 0x2a, 0x04, 0xf5, 0x22, 0x7c, 0x87, 0xab, 0xa4, 0xfb, 0x0f, 0x0b, 0xed, 0xe3, 0xd7, 0x09, 0x69, 0xab, 0x28, 0xa0, 0x76, 0x01, 0xdc, 0xb3, 0xb4, 0x89, 0x0b, 0x37, 0x86, 0xb9, 0x45, 0x6d, 0x35, 0xe2, 0x82, 0x45, 0xf3, 0x6f, 0xab, 0xdb, 0xd6, 0xdb, 0xd2, 0x68, 0x10, 0xf0, 0x7e, 0xba, 0x77, 0x2b, 0x31, 0x9b, 0x7d, 0x9f, 0xb0, 0xf7, 0xad, 0x88, 0x72, 0x37, 0x45, 0x99, 0xff, 0xe6, 0xdd, 0x98, 0x1b, 0xf7, 0x08, 0x2d, 0x85, 0xa6, 0x05, 0x61, 0xa7, 0x44, 0x5e, 0xce, 0x47, 0x9a, 0xba, 0x7a, 0xc6, 0xb0, 0x94, 0xd2, 0x95, 0x3f, 0x77, 0x73, 0xcd, 0x81, 0xa7, 0x5b, 0xcc, 0xf0, 0x85, 0xae, 0xd8, 0x72, 0xfa, 0xdf, 0x12, 0x64, 0xec, 0x0a, 0xec, 0xcc, 0xce, 0x7b, 0xd7, 0x6f, 0x0b, 0x40, 0x49, 0xef, 0x0c, 0x20, 0x4a, 0x68, 0x7b, 0x92, 0xf7, 0xd0, 0x30, 0x5c, 0x5c, 0xe5, 0x8c, 0xcc, 0x7a, 0x9d, 0xad, 0x6d, 0xf8, 0xcb, 0xdd, 0xfd, 0x84, 0x0f, 0x65, 0x86, 0x54, 0xb8, 0x75, 0xf1, 0x9c, 0x3c, 0xb3, 0xd0, 0x43, 0x65, 0x88, 0x2e, 0xcb, 0xd4, 0x4c, 0x82, 0x54, 0x81, 0x44, 0x5c, 0x44, 0x16, 0xf9, 0x64, 0xa0, 0x8e, 0xf5, 0x47, 0xba, 0x25, 0x52, 0xb0, 0x5a, 0xa1, 0xaf, 0x0c, 0xfc, 0x8f, 0x8b, 0x9b, 0x4a, 0x7e, 0x4e, 0xdd, 0x5b, 0x55, 0xb0, 0x01, 0x5f, 0xe9, 0xfd, 0x4e, 0x01, 0xe9, 0x9c, 0x71, 0x3f, 0x58, 0xad, 0x21, 0x5e, 0xb5, 0x5e, 0xf9, 0x4b, 0xd2, 0x61, 0x48, 0x1f, 0xa9, 0x77, 0xbb, 0x85, 0x9b, 0x09, 0x84, 0xda, 0xb5, 0x57, 0x27, 0x73, 0xd5, 0xa3, 0xa5, 0xf1, 0x2c, 0xbb, 0x53, 0x01, 0x6a, 0x97, 0x26, 0xe8, 0x97, 0xa3, 0x62, 0xea, 0xf8, 0x9f, 0x30, 0xfd, 0xe9, 0xa8, 0x35, 0x67, 0x54, 0xff, 0x6b, 0x2d, 0x79, 0x12, 0xad, 0x3c, 0x14, 0x6d, 0x9a, 0x62, 0xe1, 0x60, 0x3c, 0x73, 0xa0, 0x73, 0xa7, 0xe4, 0xb6, 0x37, 0x90, 0x2b, 0xec, 0xba, 0xa2, 0x59, 0xbc, 0xfa, 0x45, 0x78, 0x05, 0x45, 0xfb, 0x25, 0xac, 0xa1, 0x78, 0xbf, 0xa2, 0xe7, 0xa3, 0xb7, 0x94, 0x00, 0x65, 0xf3, 0xb6, 0x44, 0xc6, 0x51, 0xc0, 0x50, 0xe5, 0x58, 0xf5, 0x5b, 0x0d, 0xb2, 0xa7, 0x00, 0xa8, 0xa7, 0x21, 0x6a, 0x6e, 0x9f, 0x11, 0xbc, 0x48, 0x01, 0x78, 0x86, 0x4f, 0x64, 0x27, 0xd6, 0x8c, 0xa4, 0xc0, 0xfb, 0x80, 0x50, 0x32, 0x21, 0xc8, 0xce, 0xd3, 0xe7, 0x79, 0x8e, 0xe8, 0x10, 0x3f, 0x3a, 0x36, 0x92, 0x1e, 0x18, 0x08, 0x70, 0x8d, 0x62, 0xcf, 0x67, 0x0f, 0xdc, 0xd1, 0xcb, 0xeb, 0x18, 0x53, 0xb7, 0xfe, 0x1a, 0xbf, 0xbc, 0x4f, 0x04, 0xc1, 0xb1, 0x7b, 0x02, 0x0f, 0x3f, 0xd7, 0xe4, 0xb6, 0x0e, 0x7e, 0x64, 0x8f, 0x53, 0x4a, 0x47, 0x96, 0x18, 0x8b, 0x10, 0x61, 0x60, 0xb1, 0xaa, 0xfb, 0xfb, 0x79, 0x8e, 0x15, 0xe5, 0xb9, 0xc0, 0x95, 0xf5, 0xeb, 0x8a, 0xff, 0x5d, 0xde, 0xea, 0x50, 0xe9, 0x61, 0xf0, 0x19, 0x9e, 0x51, 0xd5, 0x1c, 0xba, 0x5c, 0x18, 0x24, 0x6d, 0x0e, 0x16, 0x73, 0x65, 0xc2, 0x33, 0x1b, 0x17, 0xa2, 0xe1, 0xb2, 0x8b, 0xd0, 0x8f, 0x79, 0x35, 0x75, 0xd5, 0xfe, 0x80, 0xfc, 0xf0, 0x83, 0xc0, 0xff, 0xfd, 0x64, 0x54, 0x77, 0xb3, 0x68, 0xc1, 0xc5, 0x9d, 0x17, 0xd4, 0x7d, 0xd0, 0xdb, 0x51, 0x29, 0xaa, 0xe8, 0x23, 0x21, 0x9c, 0xa8, 0x86, 0x9e, 0xd5, 0xd7, 0x5d, 0x70, 0xfb, 0xeb, 0x57, 0x03, 0x5b, 0x46, 0x95, 0x1e, 0x5c, 0xb6, 0xdd, 0x87, 0x1d, 0x3a, 0x82, 0x0c, 0x4f, 0x2b, 0x7b, 0x23, 0x09, 0x61, 0xf1, 0xd3, 0x3f, 0xcb, 0xf1, 0x19, 0xf2, 0x9d, 0x8e, 0xcb, 0x17, 0x51, 0x56, 0x03, 0x36, 0xf7, 0x66, 0x43, 0x4f, 0x02, 0xe3, 0xde, 0xf7, 0xab, 0xbd, 0x60, 0xb0, 0x07, 0x97, 0x26, 0xf0, 0x0e, 0xe6, 0x26, 0x31, 0x0c, 0x67, 0x49, 0x10, 0xe8, 0x78, 0x6c, 0x38, 0x2e, 0xbe, 0x1b, 0x6c, 0xd2, 0x61, 0x57, 0x62, 0x15, 0x28, 0xae, 0x61, 0x34, 0xef, 0x50, 0x4e, 0x43, 0x09, 0x38, 0xf8, 0xaa, 0x85, 0xd0, 0xae, 0x3f, 0xc0, 0x4c, 0xb5, 0x0a, 0xff, 0x90, 0x7b, 0x82, 0xf6, 0x2e, 0xa2, 0x44, 0x13, 0x08, 0x02, 0x13, 0x3a, 0xe8, 0xf4, 0x0d, 0x81, 0x62, 0x65, 0x4b, 0xb9, 0xb5, 0x73, 0x3c, 0x4c, 0xf1, 0x93, 0x7d, 0x84, 0xaa, 0x84, 0x66, 0x44, 0x38, 0x0b, 0xb4, 0xdb, 0x08, 0xfa, 0x24, 0x73, 0xbf, 0xfe, 0xfc, 0x1a, 0x4e, 0x7d, 0x72, 0x5e, 0x1b, 0xd4, 0x2d, 0xf2, 0x45, 0x27, 0x52, 0x9a, 0x22, 0x7a, 0xc0, 0xba, 0x92, 0x4b, 0xad, 0x39, 0x20, 0x85, 0x49, 0x88, 0x60, 0x09, 0x1f, 0x40, 0x23, 0xe7, 0xcc, 0xca, 0x3d, 0xe1, 0xe6, 0x4e }, - .hmac_key_idx = 0, + .hmac_key_idx = DS_KEY_BLOCK_1, // results of message array encrypted with these keys .expected_results = { // Message 0 @@ -128,7 +129,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 95, // 3072 bit }, .expected_c = { 0x74, 0x3a, 0x44, 0x62, 0xa7, 0x7a, 0x9a, 0x00, 0xe6, 0x18, 0xdd, 0x5e, 0xaf, 0x37, 0x77, 0x31, 0x1b, 0x19, 0x6b, 0xc1, 0x67, 0x2c, 0x19, 0x23, 0xed, 0xa8, 0x49, 0x08, 0xf7, 0x98, 0x24, 0x8f, 0x24, 0x5b, 0xfb, 0x11, 0x35, 0x1a, 0x19, 0x72, 0x3b, 0x72, 0x77, 0x3f, 0xcf, 0x93, 0x9a, 0xc0, 0xc8, 0x81, 0xc9, 0xab, 0x5f, 0xe2, 0x7d, 0xe7, 0xec, 0x6d, 0x63, 0xb7, 0x01, 0xe7, 0x86, 0x1f, 0x3e, 0x5e, 0x72, 0x67, 0x0e, 0xc8, 0x81, 0x98, 0xf3, 0x52, 0x14, 0xb4, 0xf9, 0x8a, 0xd2, 0x92, 0x63, 0xf2, 0xa9, 0xc5, 0x60, 0xd9, 0x27, 0xc8, 0x97, 0x13, 0x75, 0x7e, 0x58, 0x60, 0x41, 0x13, 0xe0, 0xf6, 0xb5, 0x04, 0x65, 0xaa, 0x05, 0x5b, 0xea, 0xb7, 0x2b, 0xef, 0x17, 0xf1, 0x81, 0x72, 0x6d, 0x32, 0x91, 0x25, 0xb4, 0x84, 0x71, 0x7a, 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.hmac_key_idx = 0, + .hmac_key_idx = DS_KEY_BLOCK_1, // results of message array encrypted with these keys .expected_results = { // Message 0 @@ -178,7 +179,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 31, // 1024 bit }, .expected_c = { 0xf8, 0x04, 0xa8, 0xfb, 0x42, 0x1d, 0x28, 0x97, 0x84, 0xb7, 0x31, 0xe4, 0x0d, 0xdd, 0xe5, 0xd3, 0xf8, 0x25, 0x0d, 0x3b, 0x50, 0x3b, 0xa5, 0x3f, 0xdc, 0xbc, 0x01, 0xf5, 0xd4, 0x5f, 0x10, 0x7e, 0xb9, 0xe4, 0xaf, 0x7b, 0x2a, 0xd4, 0x4a, 0x71, 0xed, 0xbb, 0x8f, 0x47, 0x07, 0x1c, 0xdc, 0x0e, 0x1b, 0xdc, 0x35, 0xce, 0x30, 0x8b, 0x79, 0x74, 0x27, 0x85, 0x44, 0xc3, 0x19, 0xdf, 0x47, 0x2d, 0x3f, 0xe9, 0x45, 0x9a, 0xa4, 0x07, 0xc2, 0xf1, 0x6a, 0x78, 0x6f, 0xed, 0x79, 0x54, 0x1a, 0xdd, 0x2d, 0xa4, 0x2c, 0x0c, 0x9a, 0xb2, 0xb1, 0x24, 0x4a, 0xdf, 0x1c, 0xfc, 0xa9, 0x4d, 0x6b, 0xc0, 0x09, 0x01, 0x07, 0x14, 0x8c, 0x51, 0xd5, 0x0f, 0xcc, 0xd3, 0x27, 0x05, 0x6b, 0x47, 0xbf, 0xe2, 0xe5, 0x2e, 0xa1, 0x63, 0x80, 0xdd, 0x5d, 0x9f, 0x38, 0x71, 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0x30, 0xc3, 0xf9, 0x1d, 0xef, 0x93, 0x0c, 0xfe, 0x30, 0xc8, 0xdd, 0xe0, 0xee, 0x68, 0xf1, 0x65, 0x56, 0x15, 0x38, 0xb1, 0x55, 0x2f, 0x51, 0x21, 0x11, 0x0f, 0x43, 0x18, 0x2f, 0x01, 0x9f, 0x17, 0x57, 0x0f, 0xfa, 0xd3, 0x05, 0xea, 0x17, 0xbc, 0x5a, 0x80, 0x5b, 0xb0, 0x63, 0x61, 0x78, 0xd0, 0x18, 0xa7, 0xd8, 0x8a, 0xff, 0x83, 0x35, 0xaa, 0x56, 0xc2, 0x8b, 0x70, 0x0a, 0x2a, 0xd8, 0x5b, 0x67, 0xf5, 0xa4, 0x77, 0x49, 0xf4, 0x96, 0x63, 0xd2, 0x0e, 0x85, 0x5a, 0xa9, 0xaf, 0x49, 0xa7, 0x45, 0x60 }, - .hmac_key_idx = 2, + .hmac_key_idx = DS_KEY_BLOCK_3, // results of message array encrypted with these keys .expected_results = { // Message 0 diff --git a/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_4096.h b/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_4096.h index 8afae330574..2a456a585b7 100644 --- a/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_4096.h +++ b/components/hal/test_apps/crypto/main/ds/digital_signature_test_cases_4096.h @@ -5,6 +5,9 @@ * * File generated by gen_digital_signature_tests.py */ + +#include "hal_crypto_common.h" + #define NUM_HMAC_KEYS 3 static const uint8_t test_hmac_keys[NUM_HMAC_KEYS][32] = { @@ -53,7 +56,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 127, // 4096 bit }, .expected_c = { 0xe9, 0xb0, 0x95, 0xe3, 0x03, 0xf1, 0x78, 0xf2, 0x79, 0x24, 0x73, 0x10, 0x4f, 0x9f, 0xc4, 0x45, 0x67, 0xf6, 0xf7, 0xba, 0xfb, 0xa4, 0xcd, 0xda, 0x0e, 0x14, 0x48, 0x5d, 0x71, 0xc7, 0x2e, 0x80, 0x49, 0x44, 0xc0, 0x2d, 0xcb, 0x8a, 0x6a, 0x70, 0x33, 0xfe, 0x10, 0x0a, 0xf4, 0xa0, 0x15, 0xa0, 0xdb, 0xc0, 0x8f, 0xad, 0xe3, 0xfe, 0x0b, 0x69, 0x95, 0xd1, 0xd3, 0x09, 0x67, 0x69, 0x5a, 0x99, 0xa0, 0xc1, 0x98, 0xb1, 0x2e, 0x77, 0xbd, 0x35, 0xfc, 0x96, 0x5d, 0xb9, 0xf4, 0x9c, 0x99, 0x61, 0x44, 0x77, 0x8e, 0xa1, 0x73, 0x25, 0x2c, 0x7b, 0x95, 0xd8, 0xa7, 0xf3, 0xe3, 0x08, 0xeb, 0x48, 0xc8, 0x44, 0x69, 0x19, 0xe6, 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message array encrypted with these keys .expected_results = { // Message 0 @@ -78,7 +81,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 95, // 3072 bit }, .expected_c = { 0x81, 0xa5, 0xd8, 0x77, 0x3c, 0x8b, 0x6c, 0x26, 0x46, 0x72, 0x8a, 0x5c, 0x3e, 0x19, 0xcf, 0x2a, 0x72, 0xde, 0x38, 0x6d, 0x5d, 0x8d, 0x74, 0x6d, 0x89, 0xdc, 0xc6, 0xf7, 0xed, 0x1b, 0x7a, 0x1a, 0x44, 0x04, 0xe7, 0xfd, 0xb2, 0xce, 0x26, 0x51, 0x01, 0x18, 0xf2, 0x45, 0x81, 0x4c, 0x77, 0xb6, 0x95, 0x1c, 0x5d, 0x66, 0xa3, 0x21, 0xf7, 0xef, 0x5b, 0xf1, 0x5c, 0xbc, 0x7c, 0xda, 0x5d, 0x82, 0xcf, 0x94, 0xae, 0x34, 0xbf, 0x98, 0x1b, 0x6e, 0x8d, 0x14, 0xc5, 0xbb, 0xed, 0x9e, 0xf3, 0xdc, 0x63, 0xa3, 0xd8, 0x0d, 0xc0, 0xcf, 0xdc, 0x4f, 0xd5, 0x0f, 0x13, 0xb8, 0x8d, 0x12, 0x92, 0xf1, 0xdd, 0xc5, 0x6f, 0xd3, 0x69, 0xef, 0x94, 0x77, 0x87, 0x7a, 0xeb, 0x97, 0xf5, 0x02, 0x40, 0x8b, 0x5a, 0xd5, 0x9a, 0x1b, 0xb7, 0x89, 0x04, 0xb4, 0xb9, 0xf2, 0xaa, 0xb7, 0xd1, 0xe4, 0xb5, 0xb1, 0x76, 0x4c, 0x8d, 0xd1, 0x10, 0xf3, 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0xea, 0xa0, 0x4a, 0x44, 0x75, 0x93, 0xad, 0xdd, 0x89, 0x0c, 0xd3, 0xb0, 0x0b, 0x4e, 0xab, 0x96, 0x79, 0x52, 0x24, 0x84, 0x1f, 0xc6, 0xc3, 0xb7, 0x6c, 0xf5, 0x03, 0x55, 0x33, 0x67, 0xa0, 0xc6, 0xf4, 0x08, 0xd1, 0x10, 0x79, 0x82, 0x64, 0xbe, 0x36, 0x6e, 0xb5, 0xd5, 0xcd, 0x72, 0xf1, 0x19, 0xf9, 0x30, 0x7f, 0x79, 0x09, 0x61, 0x24, 0x15, 0xfd, 0x1a, 0x3e, 0x49, 0xa0, 0xb9, 0x58, 0x97, 0xb2, 0x5f, 0xdf, 0x7a, 0xf4, 0x31, 0xcb, 0xb0, 0x8c, 0x33, 0x2c, 0x13, 0x3d, 0x8c, 0xe3, 0x79, 0x08, 0x66, 0xa0, 0x2d, 0xad, 0x3d, 0xeb, 0x82, 0xaf, 0x9c }, - .hmac_key_idx = 0, + .hmac_key_idx = DS_KEY_BLOCK_1, // results of message array encrypted with these keys .expected_results = { // Message 0 @@ -128,7 +131,7 @@ static const encrypt_testcase_t test_cases[NUM_CASES] = { .length = 31, // 1024 bit }, .expected_c = { 0x5a, 0x60, 0x69, 0x68, 0x29, 0x96, 0x85, 0xb3, 0xba, 0x39, 0x9d, 0x2d, 0x82, 0x39, 0xac, 0x5e, 0x41, 0x70, 0xcc, 0xb7, 0x80, 0x57, 0x4f, 0x9c, 0x32, 0xb6, 0xdf, 0x76, 0xe0, 0x55, 0xa2, 0xaf, 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.hmac_key_idx = DS_KEY_BLOCK_1, // results of message array encrypted with these keys .expected_results = { // Message 0 diff --git a/components/hal/test_apps/crypto/main/ds/test_ds.c b/components/hal/test_apps/crypto/main/ds/test_ds.c index c9542601044..631f67947f8 100644 --- a/components/hal/test_apps/crypto/main/ds/test_ds.c +++ b/components/hal/test_apps/crypto/main/ds/test_ds.c @@ -12,15 +12,9 @@ #include "unity_fixture.h" #include "soc/soc_caps.h" -typedef enum { - HMAC_KEY0 = 0, - HMAC_KEY1, - HMAC_KEY2, - HMAC_KEY3, - HMAC_KEY4, - HMAC_KEY5, - HMAC_KEY_MAX -} hmac_key_id_t; +#include "esp_log.h" + +const static char *TAG = "test_ds"; #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/efuse.h" @@ -164,7 +158,7 @@ static void ds_disable_release(void) } -static esp_err_t esp_ds_start_sign(const void *message, const esp_ds_data_t *data, hmac_key_id_t key_id) +static esp_err_t esp_ds_start_sign(const void *message, const esp_ds_data_t *data, uint32_t key_id) { ds_acquire_enable(); @@ -215,7 +209,7 @@ static esp_err_t esp_ds_finish_sign(void *signature, const esp_ds_data_t *data) static esp_err_t esp_ds_sign(const void *message, const esp_ds_data_t *data, - hmac_key_id_t key_id, + uint32_t key_id, void *signature) { esp_err_t result = esp_ds_start_sign(message, data, key_id); @@ -272,7 +266,7 @@ static void ds_disable_release(void) static esp_err_t esp_ds_start_sign(const void *message, const esp_ds_data_t *data, - hmac_key_id_t key_id) + uint32_t key_id) { ds_acquire_enable(); @@ -325,7 +319,7 @@ esp_err_t esp_ds_finish_sign(void *signature, const esp_ds_data_t *data) static esp_err_t esp_ds_sign(const void *message, const esp_ds_data_t *data, - hmac_key_id_t key_id, + uint32_t key_id, void *signature) { esp_err_t result = esp_ds_start_sign(message, data, key_id); @@ -384,7 +378,7 @@ TEST_TEAR_DOWN(ds) TEST(ds, digital_signature_parameter_encryption) { for (int i = 0; i < NUM_CASES; i++) { - printf("Encrypting test case %d...\n", i); + ESP_LOGI(TAG, "Encrypting test case %d.", i); const encrypt_testcase_t *t = &test_cases[i]; esp_ds_data_t result = { }; esp_ds_p_data_t p_data; @@ -397,7 +391,7 @@ TEST(ds, digital_signature_parameter_encryption) esp_err_t r = esp_ds_encrypt_params(&result, t->iv, &p_data, test_hmac_keys[t->hmac_key_idx]); - printf("Encrypting test case %d done\n", i); + ESP_LOGI(TAG, "Encrypting test case %d done", i); TEST_ASSERT_EQUAL(ESP_OK, r); TEST_ASSERT_EQUAL(t->p_data.length, result.rsa_length); TEST_ASSERT_EQUAL_HEX8_ARRAY(t->iv, result.iv, ETS_DS_IV_LEN); @@ -405,8 +399,8 @@ TEST(ds, digital_signature_parameter_encryption) } } -// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). -// HMAC_KEY0 is usually used for HMAC upstream (user access) tests. +// This test uses the HMAC_KEY_BLOCK_1 eFuse key which hasn't been burned by burn_hmac_keys(). +// HMAC_KEY_BLOCK_1 is usually used for HMAC upstream (user access) tests. TEST(ds, digital_signature_wrong_hmac_key_purpose) { esp_ds_data_t ds_data = {}; @@ -414,11 +408,11 @@ TEST(ds, digital_signature_wrong_hmac_key_purpose) const char *message = "test"; // HMAC fails in that case because it checks for the correct purpose - TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0)); + TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY_BLOCK_1)); } -// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). -// HMAC_KEY0 is usually used for HMAC upstream (user access) tests. +// This test uses the HMAC_KEY_BLOCK_1 eFuse key which hasn't been burned by burn_hmac_keys(). +// HMAC_KEY_BLOCK_1 is usually used for HMAC upstream (user access) tests. TEST(ds, digital_signature_blocking_wrong_hmac_key_purpose) { esp_ds_data_t ds_data = {}; @@ -427,13 +421,13 @@ TEST(ds, digital_signature_blocking_wrong_hmac_key_purpose) uint8_t signature_data [128 * 4]; // HMAC fails in that case because it checks for the correct purpose - TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data)); + TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY_BLOCK_1, signature_data)); } TEST(ds, digital_signature_operation) { for (int i = 0; i < NUM_CASES; i++) { - printf("Running test case %d...\n", i); + ESP_LOGI(TAG, "Running test case %d.", i); const encrypt_testcase_t *t = &test_cases[i]; // copy encrypt parameter test case into ds_data structure @@ -444,11 +438,11 @@ TEST(ds, digital_signature_operation) for (int j = 0; j < NUM_MESSAGES; j++) { uint8_t signature[DS_MAX_BITS / 8] = { 0 }; - printf(" ... message %d\n", j); + ESP_LOGD(TAG, " ... message %d", j); esp_err_t ds_r = esp_ds_start_sign(test_messages[j], &ds_data, - t->hmac_key_idx + 1); + t->hmac_key_idx); TEST_ASSERT_EQUAL(ESP_OK, ds_r); ds_r = esp_ds_finish_sign(signature, &ds_data); @@ -465,7 +459,7 @@ TEST(ds, digital_signature_operation) TEST(ds, digital_signature_blocking_operation) { for (int i = 0; i < NUM_CASES; i++) { - printf("Running test case %d...\n", i); + ESP_LOGI(TAG, "Running test case %d.", i); const encrypt_testcase_t *t = &test_cases[i]; // copy encrypt parameter test case into ds_data structure @@ -479,7 +473,7 @@ TEST(ds, digital_signature_blocking_operation) esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, - t->hmac_key_idx + 1); + t->hmac_key_idx); TEST_ASSERT_EQUAL(ESP_OK, ds_r); ds_r = esp_ds_finish_sign(signature, &ds_data); @@ -487,7 +481,7 @@ TEST(ds, digital_signature_blocking_operation) #else esp_err_t ds_r = esp_ds_sign(test_messages[0], &ds_data, - t->hmac_key_idx + 1, + t->hmac_key_idx, signature); TEST_ASSERT_EQUAL(ESP_OK, ds_r); #endif @@ -510,10 +504,10 @@ TEST(ds, digital_signature_invalid_data) // Corrupt the IV one bit at a time, rerun and expect failure for (int bit = 0; bit < 128; bit++) { - printf("Corrupting IV bit %d...\n", bit); + ESP_LOGD(TAG, "Corrupting IV bit %d.", bit); ds_data.iv[bit / 8] ^= 1 << (bit % 8); - esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1); + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx); TEST_ASSERT_EQUAL(ESP_OK, ds_r); ds_r = esp_ds_finish_sign(signature, &ds_data); @@ -524,12 +518,12 @@ TEST(ds, digital_signature_invalid_data) } // Corrupt encrypted key data one bit at a time, rerun and expect failure - printf("Corrupting C...\n"); + ESP_LOGD(TAG, "Corrupting C."); for (int bit = 0; bit < ETS_DS_C_LEN * 8; bit++) { - printf("Corrupting C bit %d...\n", bit); + ESP_LOGD(TAG, "Corrupting C bit %d.", bit); ds_data.c[bit / 8] ^= 1 << (bit % 8); - esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1); + esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx); TEST_ASSERT_EQUAL(ESP_OK, ds_r); ds_r = esp_ds_finish_sign(signature, &ds_data); diff --git a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c index 6b9c80c8a56..64c4c2aa0de 100644 --- a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c +++ b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c @@ -8,6 +8,7 @@ #include #include +#include "esp_efuse_chip.h" #include "esp_private/esp_crypto_lock_internal.h" #include "esp_random.h" #include "hal/clk_gate_ll.h" @@ -19,6 +20,7 @@ #include "unity_fixture.h" #include "ecdsa_params.h" +#include "hal_crypto_common.h" static void ecdsa_enable_and_reset(void) { @@ -50,7 +52,6 @@ static int test_ecdsa_verify(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* ecdsa_hal_config_t conf = { .mode = ECDSA_MODE_SIGN_VERIFY, - .k_mode = ECDSA_K_USE_TRNG, .sha_mode = ECDSA_Z_USER_PROVIDED, }; @@ -119,7 +120,6 @@ static void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* ecdsa_hal_config_t conf = { .mode = ECDSA_MODE_SIGN_GEN, - .k_mode = ECDSA_K_USE_TRNG, .sha_mode = ECDSA_Z_USER_PROVIDED, .use_km_key = use_km_key, }; @@ -127,13 +127,13 @@ static void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* if (is_p256) { conf.curve = ECDSA_CURVE_SECP256R1; if (use_km_key == 0) { - conf.efuse_key_blk = 6; + conf.efuse_key_blk = EFUSE_BLK_KEY0 + ECDSA_KEY_BLOCK_2; } len = 32; } else { conf.curve = ECDSA_CURVE_SECP192R1; if (use_km_key == 0) { - conf.efuse_key_blk = 5; + conf.efuse_key_blk = EFUSE_BLK_KEY0 + ECDSA_KEY_BLOCK_1; } len = 24; } @@ -144,7 +144,7 @@ static void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* ecdsa_enable_and_reset(); do { - ecdsa_hal_gen_signature(&conf, NULL, sha_le, r_le, s_le, len); + ecdsa_hal_gen_signature(&conf, sha_le, r_le, s_le, len); } while(!memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len)); ecdsa_disable(); @@ -174,13 +174,13 @@ static void test_ecdsa_export_pubkey(bool is_p256, bool use_km_key) if (is_p256) { conf.curve = ECDSA_CURVE_SECP256R1; if (use_km_key == 0) { - conf.efuse_key_blk = 6; + conf.efuse_key_blk = EFUSE_BLK_KEY0 + ECDSA_KEY_BLOCK_2; } len = 32; } else { conf.curve = ECDSA_CURVE_SECP192R1; if (use_km_key == 0) { - conf.efuse_key_blk = 5; + conf.efuse_key_blk = EFUSE_BLK_KEY0 + ECDSA_KEY_BLOCK_1; } len = 24; } diff --git a/components/hal/test_apps/crypto/main/hal_crypto_common.h b/components/hal/test_apps/crypto/main/hal_crypto_common.h new file mode 100644 index 00000000000..e47e8f8823e --- /dev/null +++ b/components/hal/test_apps/crypto/main/hal_crypto_common.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +// efuse key blocks for DS +#define DS_KEY_BLOCK_1 0 +#define DS_KEY_BLOCK_2 1 +#define DS_KEY_BLOCK_3 2 + +/* + * HMAC and ECDSA testcases cannot run together as block used for burning keys are overlapped + */ + +// efuse key blocks for HMAC +#define HMAC_KEY_BLOCK_1 3 +#define HMAC_KEY_BLOCK_2 4 + +// efuse key blocks for ECDSA +#define ECDSA_KEY_BLOCK_1 4 +#define ECDSA_KEY_BLOCK_2 5 diff --git a/components/hal/test_apps/crypto/main/hmac/test_hmac.c b/components/hal/test_apps/crypto/main/hmac/test_hmac.c index 27478062abb..8cbcfd2fb88 100644 --- a/components/hal/test_apps/crypto/main/hmac/test_hmac.c +++ b/components/hal/test_apps/crypto/main/hmac/test_hmac.c @@ -16,18 +16,9 @@ #include "soc/hwcrypto_reg.h" #include "soc/system_reg.h" #include "hmac_params.h" +#include "hal_crypto_common.h" -typedef enum { - HMAC_KEY0 = 0, - HMAC_KEY1, - HMAC_KEY2, - HMAC_KEY3, - HMAC_KEY4, - HMAC_KEY5, - HMAC_KEY_MAX -} hmac_key_id_t; - -static ets_efuse_block_t convert_key_type(hmac_key_id_t key_id) { +static ets_efuse_block_t convert_key_type(uint32_t key_id) { return ETS_EFUSE_BLOCK_KEY0 + (ets_efuse_block_t) key_id; } @@ -48,7 +39,7 @@ static esp_err_t hmac_jtag_disable(void) #define SHA256_PAD_SZ 8 -static esp_err_t hmac_jtag_enable(hmac_key_id_t key_id, const uint8_t *token) +static esp_err_t hmac_jtag_enable(uint32_t key_id, const uint8_t *token) { int ets_status; esp_err_t err = ESP_OK; @@ -69,7 +60,7 @@ static void write_and_padd(uint8_t *block, const uint8_t *data, uint16_t data_le bzero(block + data_len + 1, SHA256_BLOCK_SZ - data_len - 1); } -static esp_err_t hmac_calculate(hmac_key_id_t key_id, const void *message, size_t message_len, uint8_t *hmac) +static esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t message_len, uint8_t *hmac) { const uint8_t *message_bytes = (const uint8_t *)message; @@ -151,7 +142,7 @@ static esp_err_t hmac_calculate(hmac_key_id_t key_id, const void *message, size_ #else /* !CONFIG_IDF_TARGET_ESP32S2 */ -static esp_err_t hmac_calculate(hmac_key_id_t key_id, +static esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t message_len, uint8_t *hmac) @@ -168,7 +159,7 @@ static esp_err_t hmac_calculate(hmac_key_id_t key_id, } } -static esp_err_t hmac_jtag_enable(hmac_key_id_t key_id, const uint8_t *token) +static esp_err_t hmac_jtag_enable(uint32_t key_id, const uint8_t *token) { int ets_status; esp_err_t err = ESP_OK; @@ -210,7 +201,7 @@ TEST_TEAR_DOWN(hmac) TEST(hmac, hmac_downstream_jtag_enable_mode) { - TEST_ASSERT_EQUAL_HEX32_MESSAGE(ESP_OK, hmac_jtag_enable(HMAC_KEY3, jtag_enable_token_data), + TEST_ASSERT_EQUAL_HEX32_MESSAGE(ESP_OK, hmac_jtag_enable(HMAC_KEY_BLOCK_1, jtag_enable_token_data), "JTAG should be re-enabled now, please manually verify"); } @@ -227,7 +218,7 @@ TEST(hmac, hmac_upstream_mac_generation_with_zeroes) const size_t num_zero_results = sizeof(zero_results) / sizeof(hmac_result); for (int i = 0; i < num_zero_results; i++) { - TEST_ESP_OK(hmac_calculate(HMAC_KEY4, zeroes, zero_results[i].msglen, hmac)); + TEST_ESP_OK(hmac_calculate(HMAC_KEY_BLOCK_2, zeroes, zero_results[i].msglen, hmac)); TEST_ASSERT_EQUAL_HEX8_ARRAY(zero_results[i].result, hmac, sizeof(hmac)); } } @@ -238,7 +229,7 @@ TEST(hmac, hmac_upstream_MAC_generation_from_data) uint8_t hmac[32]; for (int i = 0; i < sizeof(results)/sizeof(hmac_result); i++) { - TEST_ESP_OK(hmac_calculate(HMAC_KEY4, message, results[i].msglen, hmac)); + TEST_ESP_OK(hmac_calculate(HMAC_KEY_BLOCK_2, message, results[i].msglen, hmac)); TEST_ASSERT_EQUAL_HEX8_ARRAY(results[i].result, hmac, sizeof(hmac)); } } diff --git a/components/hal/touch_sensor_hal.c b/components/hal/touch_sensor_hal.c index c145b479fc8..f69f0163bcb 100644 --- a/components/hal/touch_sensor_hal.c +++ b/components/hal/touch_sensor_hal.c @@ -12,7 +12,7 @@ void touch_hal_config(touch_pad_t touch_num) { - touch_ll_set_threshold(touch_num, SOC_TOUCH_PAD_THRESHOLD_MAX); + touch_ll_set_threshold(touch_num, TOUCH_PAD_THRESHOLD_MAX); touch_ll_set_slope(touch_num, TOUCH_PAD_SLOPE_DEFAULT); touch_ll_set_tie_option(touch_num, TOUCH_PAD_TIE_OPT_DEFAULT); } diff --git a/components/hal/usb_dwc_hal.c b/components/hal/usb_dwc_hal.c index 58fc66f4430..5875d9e6fee 100644 --- a/components/hal/usb_dwc_hal.c +++ b/components/hal/usb_dwc_hal.c @@ -9,9 +9,9 @@ #include #include "sdkconfig.h" #include "soc/chip_revision.h" -#include "hal/efuse_hal.h" #include "hal/usb_dwc_hal.h" #include "hal/usb_dwc_ll.h" +#include "hal/efuse_hal.h" #include "hal/assert.h" // ------------------------------------------------ Macros and Types --------------------------------------------------- @@ -27,6 +27,35 @@ #define CORE_REG_GHWCFG3 0x00C804B5 #define CORE_REG_GHWCFG4 0xD3F0A030 +// ----------------------- Configs ------------------------- + +/** + * @brief Default FIFO sizes (see 2.1.2.4 for programming guide) + */ +const usb_dwc_hal_fifo_config_t fifo_config_default = { + .rx_fifo_lines = USB_DWC_FIFO_RX_LINES_DEFAULT, + .nptx_fifo_lines = USB_DWC_FIFO_NPTX_LINES_DEFAULT, + .ptx_fifo_lines = USB_DWC_FIFO_PTX_LINES_DEFAULT, +}; + +/** + * @brief FIFO sizes that bias to giving RX FIFO more capacity + */ +const usb_dwc_hal_fifo_config_t fifo_config_bias_rx = { + .rx_fifo_lines = USB_DWC_FIFO_RX_LINES_BIASRX, + .nptx_fifo_lines = USB_DWC_FIFO_NPTX_LINES_BIASRX, + .ptx_fifo_lines = USB_DWC_FIFO_PTX_LINES_BIASRX, +}; + +/** + * @brief FIFO sizes that bias to giving Periodic TX FIFO more capacity (i.e., ISOC OUT) + */ +const usb_dwc_hal_fifo_config_t fifo_config_bias_ptx = { + .rx_fifo_lines = USB_DWC_FIFO_RX_LINES_BIASTX, + .nptx_fifo_lines = USB_DWC_FIFO_NPTX_LINES_BIASTX, + .ptx_fifo_lines = USB_DWC_FIFO_PTX_LINES_BIASTX, +}; + // -------------------- Configurable ----------------------- /** @@ -159,14 +188,29 @@ void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal) hal->flags.val = 0; hal->channels.num_allocd = 0; hal->channels.chan_pend_intrs_msk = 0; - memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_HAL_NUM_CHAN); + memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * OTG_NUM_HOST_CHAN); } -void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *fifo_config) +void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bias_t fifo_bias) { - HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES); + const usb_dwc_hal_fifo_config_t *fifo_config; + switch (fifo_bias) { + case USB_HAL_FIFO_BIAS_DEFAULT: + fifo_config = &fifo_config_default; + break; + case USB_HAL_FIFO_BIAS_RX: + fifo_config = &fifo_config_bias_rx; + break; + case USB_HAL_FIFO_BIAS_PTX: + fifo_config = &fifo_config_bias_ptx; + break; + default: + abort(); + } + + HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_FIFO_TOTAL_USABLE_LINES); //Check that none of the channels are active - for (int i = 0; i < USB_DWC_HAL_NUM_CHAN; i++) { + for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) { if (hal->channels.hdls[i] != NULL) { HAL_ASSERT(!hal->channels.hdls[i]->flags.active); } @@ -179,9 +223,21 @@ void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fif usb_dwc_ll_grstctl_flush_nptx_fifo(hal->dev); usb_dwc_ll_grstctl_flush_ptx_fifo(hal->dev); usb_dwc_ll_grstctl_flush_rx_fifo(hal->dev); + hal->fifo_config = fifo_config; hal->flags.fifo_sizes_set = 1; } +void usb_dwc_hal_get_mps_limits(usb_dwc_hal_context_t *hal, usb_hal_fifo_mps_limits_t *mps_limits) +{ + HAL_ASSERT(hal && mps_limits); + HAL_ASSERT(hal->flags.fifo_sizes_set); + + const usb_dwc_hal_fifo_config_t *fifo_config = hal->fifo_config; + mps_limits->in_mps = (fifo_config->rx_fifo_lines - 2) * 4; // Two lines are reserved for status quadlets internally by USB_DWC + mps_limits->non_periodic_out_mps = fifo_config->nptx_fifo_lines * 4; + mps_limits->periodic_out_mps = fifo_config->ptx_fifo_lines * 4; +} + // ---------------------------------------------------- Host Port ------------------------------------------------------ static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal) @@ -193,7 +249,7 @@ static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal) void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal) { - usb_priv_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev); + usb_dwc_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev); //Host Configuration usb_dwc_ll_hcfg_set_defaults(hal->dev, speed); //Configure HFIR @@ -208,11 +264,11 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan { HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a channel //Attempt to allocate channel - if (hal->channels.num_allocd == USB_DWC_HAL_NUM_CHAN) { + if (hal->channels.num_allocd == OTG_NUM_HOST_CHAN) { return false; //Out of free channels } int chan_idx = -1; - for (int i = 0; i < USB_DWC_HAL_NUM_CHAN; i++) { + for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) { if (hal->channels.hdls[i] == NULL) { hal->channels.hdls[i] = chan_obj; chan_idx = i; @@ -238,7 +294,7 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj) { - if (chan_obj->type == USB_PRIV_XFER_TYPE_INTR || chan_obj->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS) { + if (chan_obj->type == USB_DWC_XFER_TYPE_INTR || chan_obj->type == USB_DWC_XFER_TYPE_ISOCHRONOUS) { //Unschedule this channel for (int i = 0; i < hal->frame_list_len; i++) { hal->periodic_frame_list[i] &= ~(1 << chan_obj->flags.chan_idx); @@ -271,7 +327,7 @@ void usb_dwc_hal_chan_set_ep_char(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t //Save channel type chan_obj->type = ep_char->type; //If this is a periodic endpoint/channel, set its schedule in the frame list - if (ep_char->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_PRIV_XFER_TYPE_INTR) { + if (ep_char->type == USB_DWC_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_DWC_XFER_TYPE_INTR) { HAL_ASSERT((int)ep_char->periodic.interval <= (int)hal->frame_list_len); //Interval cannot exceed the length of the frame list //Find the effective offset in the frame list (in case the phase_offset_frames > interval) int offset = ep_char->periodic.phase_offset_frames % ep_char->periodic.interval; diff --git a/components/hal/usb_phy_hal.c b/components/hal/usb_phy_hal.c index 16a8f60d818..5a0f83bf7a6 100644 --- a/components/hal/usb_phy_hal.c +++ b/components/hal/usb_phy_hal.c @@ -20,6 +20,7 @@ void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targe if (phy_target == USB_PHY_TARGET_EXT) { usb_phy_ll_ext_otg_enable(hal->wrap_dev); } else if (phy_target == USB_PHY_TARGET_INT) { + usb_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true); usb_phy_ll_int_otg_enable(hal->wrap_dev); } } @@ -41,10 +42,10 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal) usb_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true); } -void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_priv_speed_t speed) +void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed) { // DEVICE - downstream - if (speed == USB_PRIV_SPEED_LOW) { + if (speed == USB_PHY_SPEED_LOW) { // LS: dm_pu = 1 usb_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false); } else { diff --git a/components/heap/heap_caps.c b/components/heap/heap_caps.c index 73ac52d85c4..ca5ec1338f7 100644 --- a/components/heap/heap_caps.c +++ b/components/heap/heap_caps.c @@ -122,7 +122,9 @@ HEAP_IRAM_ATTR static void *heap_caps_malloc_base( size_t size, uint32_t caps) { void *ret = NULL; - if (size == 0 || MULTI_HEAP_ADD_BLOCK_OWNER_SIZE(size) > HEAP_SIZE_MAX ) { + // remove block owner size to HEAP_SIZE_MAX rather than adding the block owner size + // to size to prevent overflows. + if (size == 0 || size > MULTI_HEAP_REMOVE_BLOCK_OWNER_SIZE(HEAP_SIZE_MAX) ) { // Avoids int overflow when adding small numbers to size, or // calculating 'end' from start+size, by limiting 'size' to the possible range return NULL; @@ -412,7 +414,9 @@ HEAP_IRAM_ATTR static void *heap_caps_realloc_base( void *ptr, size_t size, uint return NULL; } - if (MULTI_HEAP_ADD_BLOCK_OWNER_SIZE(size) > HEAP_SIZE_MAX) { + // remove block owner size to HEAP_SIZE_MAX rather than adding the block owner size + // to size to prevent overflows. + if (size > MULTI_HEAP_REMOVE_BLOCK_OWNER_SIZE(HEAP_SIZE_MAX)) { return NULL; } @@ -421,6 +425,7 @@ HEAP_IRAM_ATTR static void *heap_caps_realloc_base( void *ptr, size_t size, uint if(esp_ptr_in_diram_iram((void *)ptr)) { uint32_t *dram_addr = (uint32_t *)ptr; dram_ptr = (void *)dram_addr[-1]; + dram_ptr = MULTI_HEAP_REMOVE_BLOCK_OWNER_OFFSET(dram_ptr); heap = find_containing_heap(dram_ptr); assert(heap != NULL && "realloc() pointer is outside heap areas"); @@ -435,6 +440,12 @@ HEAP_IRAM_ATTR static void *heap_caps_realloc_base( void *ptr, size_t size, uint assert(heap != NULL && "realloc() pointer is outside heap areas"); } + // shift ptr by block owner offset. Since the ptr returned to the user + // does not include the block owner bytes (that are located at the + // beginning of the allocated memory) we have to add them back before + // processing the realloc. + ptr = MULTI_HEAP_REMOVE_BLOCK_OWNER_OFFSET(ptr); + // are the existing heap's capabilities compatible with the // requested ones? bool compatible_caps = (caps & get_all_caps(heap)) == caps; @@ -466,8 +477,10 @@ HEAP_IRAM_ATTR static void *heap_caps_realloc_base( void *ptr, size_t size, uint } assert(old_size > 0); - memcpy(new_p, ptr, MIN(size, old_size)); - heap_caps_free(ptr); + // do not copy the block owner bytes + memcpy(new_p, MULTI_HEAP_ADD_BLOCK_OWNER_OFFSET(ptr), MIN(size, old_size)); + // add the block owner bytes to ptr since they are removed in heap_caps_free + heap_caps_free(MULTI_HEAP_ADD_BLOCK_OWNER_OFFSET(ptr)); return new_p; } @@ -561,6 +574,65 @@ size_t heap_caps_get_largest_free_block( uint32_t caps ) return info.largest_free_block; } +static struct { + size_t *values; // Array of minimum_free_bytes used to keep the different values when starting monitoring + size_t counter; // Keep count of registered heap when monitoring to prevent any added heap to create an out of bound access on values + multi_heap_lock_t mux; // protect access to min_free_bytes_monitoring fields in start/stop monitoring functions +} min_free_bytes_monitoring = {NULL, 0, MULTI_HEAP_LOCK_STATIC_INITIALIZER}; + +esp_err_t heap_caps_monitor_local_minimum_free_size_start(void) +{ + // update minimum_free_bytes on all affected heap, and store the "old value" + // as a snapshot of the heaps minimum_free_bytes state. + heap_t *heap = NULL; + MULTI_HEAP_LOCK(&min_free_bytes_monitoring.mux); + if (min_free_bytes_monitoring.values == NULL) { + SLIST_FOREACH(heap, ®istered_heaps, next) { + min_free_bytes_monitoring.counter++; + } + min_free_bytes_monitoring.values = heap_caps_malloc(sizeof(size_t) * min_free_bytes_monitoring.counter, MALLOC_CAP_DEFAULT); + assert(min_free_bytes_monitoring.values != NULL && "not enough memory to store min_free_bytes value"); + memset(min_free_bytes_monitoring.values, 0xFF, sizeof(size_t) * min_free_bytes_monitoring.counter); + } + + heap = SLIST_FIRST(®istered_heaps); + for (size_t counter = 0; counter < min_free_bytes_monitoring.counter; counter++) { + size_t old_minimum = multi_heap_reset_minimum_free_bytes(heap->heap); + + if (min_free_bytes_monitoring.values[counter] > old_minimum) { + min_free_bytes_monitoring.values[counter] = old_minimum; + } + + heap = SLIST_NEXT(heap, next); + } + MULTI_HEAP_UNLOCK(&min_free_bytes_monitoring.mux); + + return ESP_OK; +} + +esp_err_t heap_caps_monitor_local_minimum_free_size_stop(void) +{ + if (min_free_bytes_monitoring.values == NULL) { + return ESP_FAIL; + } + + MULTI_HEAP_LOCK(&min_free_bytes_monitoring.mux); + heap_t *heap = SLIST_FIRST(®istered_heaps); + for (size_t counter = 0; counter < min_free_bytes_monitoring.counter; counter++) { + multi_heap_restore_minimum_free_bytes(heap->heap, min_free_bytes_monitoring.values[counter]); + + heap = SLIST_NEXT(heap, next); + } + + heap_caps_free(min_free_bytes_monitoring.values); + min_free_bytes_monitoring.values = NULL; + min_free_bytes_monitoring.counter = 0; + MULTI_HEAP_UNLOCK(&min_free_bytes_monitoring.mux); + + return ESP_OK; +} + + void heap_caps_get_info( multi_heap_info_t *info, uint32_t caps ) { memset(info, 0, sizeof(multi_heap_info_t)); @@ -571,11 +643,13 @@ void heap_caps_get_info( multi_heap_info_t *info, uint32_t caps ) multi_heap_info_t hinfo; multi_heap_get_info(heap->heap, &hinfo); - info->total_free_bytes += hinfo.total_free_bytes; - info->total_allocated_bytes += hinfo.total_allocated_bytes; + info->total_free_bytes += hinfo.total_free_bytes - MULTI_HEAP_BLOCK_OWNER_SIZE(); + info->total_allocated_bytes += (hinfo.total_allocated_bytes - + hinfo.allocated_blocks * MULTI_HEAP_BLOCK_OWNER_SIZE()); info->largest_free_block = MAX(info->largest_free_block, hinfo.largest_free_block); - info->minimum_free_bytes += hinfo.minimum_free_bytes; + info->largest_free_block -= info->largest_free_block ? MULTI_HEAP_BLOCK_OWNER_SIZE() : 0; + info->minimum_free_bytes += hinfo.minimum_free_bytes - MULTI_HEAP_BLOCK_OWNER_SIZE(); info->allocated_blocks += hinfo.allocated_blocks; info->free_blocks += hinfo.free_blocks; info->total_blocks += hinfo.total_blocks; @@ -654,6 +728,9 @@ void heap_caps_dump_all(void) size_t heap_caps_get_allocated_size( void *ptr ) { + // add the block owner bytes back to ptr before handing over + // to multi heap layer. + ptr = MULTI_HEAP_REMOVE_BLOCK_OWNER_OFFSET(ptr); heap_t *heap = find_containing_heap(ptr); assert(heap); size_t size = multi_heap_get_allocated_size(heap->heap, ptr); @@ -673,8 +750,9 @@ static HEAP_IRAM_ATTR void *heap_caps_aligned_alloc_base(size_t alignment, size_ //Heap has at least one of the caps requested. If caps has other bits set that this prio //doesn't cover, see if they're available in other prios. if ((get_all_caps(heap) & caps) == caps) { - //Just try to alloc, nothing special. - void *ret = multi_heap_aligned_alloc(heap->heap, MULTI_HEAP_ADD_BLOCK_OWNER_SIZE(size), alignment); + // Just try to alloc, nothing special. Provide the size of the block owner + // as an offset to prevent a miscalculation of the alignment. + void *ret = multi_heap_aligned_alloc_offs(heap->heap, MULTI_HEAP_ADD_BLOCK_OWNER_SIZE(size), alignment, MULTI_HEAP_BLOCK_OWNER_SIZE()); if (ret != NULL) { MULTI_HEAP_SET_BLOCK_OWNER(ret); ret = MULTI_HEAP_ADD_BLOCK_OWNER_OFFSET(ret); diff --git a/components/heap/heap_trace_standalone.c b/components/heap/heap_trace_standalone.c index 3a62d24cf75..3a292a13ed2 100644 --- a/components/heap/heap_trace_standalone.c +++ b/components/heap/heap_trace_standalone.c @@ -134,12 +134,18 @@ static HEAP_IRAM_ATTR heap_trace_record_t* map_find_and_remove(void *p) { size_t idx = hash_idx(p); heap_trace_record_t *r_cur = NULL; + heap_trace_record_t *r_prev = NULL; SLIST_FOREACH(r_cur, &hash_map[idx], slist_hashmap) { if (r_cur->address == p) { total_hashmap_hits++; - SLIST_REMOVE(&hash_map[idx], r_cur, heap_trace_record_t, slist_hashmap); + if (r_prev) { + SLIST_REMOVE_AFTER(r_prev, slist_hashmap); + } else { + SLIST_REMOVE_HEAD(&hash_map[idx], slist_hashmap); + } return r_cur; } + r_prev = r_cur; } total_hashmap_miss++; return NULL; diff --git a/components/heap/include/esp_heap_caps.h b/components/heap/include/esp_heap_caps.h index 97f2ff7143a..ec202359a33 100644 --- a/components/heap/include/esp_heap_caps.h +++ b/components/heap/include/esp_heap_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -241,6 +241,27 @@ size_t heap_caps_get_minimum_free_size( uint32_t caps ); */ size_t heap_caps_get_largest_free_block( uint32_t caps ); +/** + * @brief Start monitoring the value of minimum_free_bytes from the moment this + * function is called instead of from startup. + * + * @note This allows to detect local lows of the minimum_free_bytes value + * that wouldn't be detected otherwise. + * + * @return esp_err_t ESP_OK if the function executed properly + * ESP_FAIL if called when monitoring already active + */ +esp_err_t heap_caps_monitor_local_minimum_free_size_start(void); + +/** + * @brief Stop monitoring the value of minimum_free_bytes. After this call + * the minimum_free_bytes value calculated from startup will be returned in + * heap_caps_get_info and heap_caps_get_minimum_free_size. + * + * @return esp_err_t ESP_OK if the function executed properly + * ESP_FAIL if called when monitoring not active + */ +esp_err_t heap_caps_monitor_local_minimum_free_size_stop(void); /** * @brief Get heap info for all regions with the given capabilities. diff --git a/components/heap/include/heap_trace.inc b/components/heap/include/heap_trace.inc index 9a8923dee21..a4b97360f22 100644 --- a/components/heap/include/heap_trace.inc +++ b/components/heap/include/heap_trace.inc @@ -22,7 +22,7 @@ inline static uint32_t get_ccount(void) { uint32_t ccount = esp_cpu_get_cycle_count() & ~3; -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE ccount |= xPortGetCoreID(); #endif return ccount; diff --git a/components/heap/include/multi_heap.h b/components/heap/include/multi_heap.h index e2aa6672d74..9fa1e090a27 100644 --- a/components/heap/include/multi_heap.h +++ b/components/heap/include/multi_heap.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -179,6 +179,34 @@ typedef struct { */ void multi_heap_get_info(multi_heap_handle_t heap, multi_heap_info_t *info); +/** + * @brief Perform an aligned allocation from the provided offset + * + * @param heap The heap in which to perform the allocation + * @param size The size of the allocation + * @param alignment How the memory must be aligned + * @param offset The offset at which the alignment should start + * @return void* The ptr to the allocated memory + */ +void *multi_heap_aligned_alloc_offs(multi_heap_handle_t heap, size_t size, size_t alignment, size_t offset); + +/** + * @brief Reset the minimum_free_bytes value (setting it to free_bytes) and return the former value + * + * @param heap The heap in which the reset is taking place + * @return size_t the value of minimum_free_bytes before it is reset + */ +size_t multi_heap_reset_minimum_free_bytes(multi_heap_handle_t heap); + +/** + * @brief Set the value of minimum_free_bytes to new_minimum_free_bytes_value or keep + * the current value of minimum_free_bytes if it is smaller than new_minimum_free_bytes_value + * + * @param heap The heap in which the restore is taking place + * @param new_minimum_free_bytes_value The value to restore the minimum_free_bytes to + */ +void multi_heap_restore_minimum_free_bytes(multi_heap_handle_t heap, const size_t new_minimum_free_bytes_value); + #ifdef __cplusplus } #endif diff --git a/components/heap/linker.lf b/components/heap/linker.lf index 7109ae3814a..b40ea44cce5 100644 --- a/components/heap/linker.lf +++ b/components/heap/linker.lf @@ -48,6 +48,9 @@ entries: multi_heap_poisoning:multi_heap_get_allocated_size (noflash) multi_heap_poisoning:multi_heap_internal_check_block_poisoning (noflash) multi_heap_poisoning:multi_heap_internal_poison_fill_region (noflash) + multi_heap_poisoning:multi_heap_aligned_alloc_offs (noflash) + else: + multi_heap:multi_heap_aligned_alloc_offs (noflash) if HEAP_POISONING_COMPREHENSIVE = y: multi_heap_poisoning:verify_fill_pattern (noflash) diff --git a/components/heap/multi_heap.c b/components/heap/multi_heap.c index e6e95c966c7..151113ac056 100644 --- a/components/heap/multi_heap.c +++ b/components/heap/multi_heap.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "multi_heap.h" #include "multi_heap_internal.h" @@ -26,7 +27,14 @@ /* Defines compile-time configuration macros */ #include "multi_heap_config.h" -#if (!defined MULTI_HEAP_POISONING) && (!defined CONFIG_HEAP_TLSF_USE_ROM_IMPL) +#if (!defined MULTI_HEAP_POISONING) + +void *multi_heap_aligned_alloc_offs(multi_heap_handle_t heap, size_t size, size_t alignment, size_t offset) +{ + return multi_heap_aligned_alloc_impl_offs(heap, size, alignment, offset); +} + +#if (!defined CONFIG_HEAP_TLSF_USE_ROM_IMPL) /* if no heap poisoning, public API aliases directly to these implementations */ void *multi_heap_malloc(multi_heap_handle_t heap, size_t size) __attribute__((alias("multi_heap_malloc_impl"))); @@ -60,7 +68,9 @@ size_t multi_heap_minimum_free_size(multi_heap_handle_t heap) void *multi_heap_get_block_address(multi_heap_block_handle_t block) __attribute__((alias("multi_heap_get_block_address_impl"))); -#endif + +#endif // !CONFIG_HEAP_TLSF_USE_ROM_IMPL +#endif // !MULTI_HEAP_POISONING #define ALIGN(X) ((X) & ~(sizeof(void *)-1)) #define ALIGN_UP(X) ALIGN((X)+sizeof(void *)-1) @@ -420,4 +430,22 @@ void multi_heap_get_info_impl(multi_heap_handle_t heap, multi_heap_info_t *info) info->largest_free_block = tlsf_fit_size(heap->heap_data, info->largest_free_block); multi_heap_internal_unlock(heap); } -#endif + +#endif // CONFIG_HEAP_TLSF_USE_ROM_IMPL + +size_t multi_heap_reset_minimum_free_bytes(multi_heap_handle_t heap) +{ + multi_heap_internal_lock(heap); + const size_t old_minimum = heap->minimum_free_bytes; + heap->minimum_free_bytes = heap->free_bytes; + multi_heap_internal_unlock(heap); + return old_minimum; +} + +void multi_heap_restore_minimum_free_bytes(multi_heap_handle_t heap, const size_t new_minimum_free_bytes_value) +{ + multi_heap_internal_lock(heap); + // keep the value of minimum_free_bytes if it is lower than the value passed as parameter + heap->minimum_free_bytes = MIN(heap->minimum_free_bytes, new_minimum_free_bytes_value); + multi_heap_internal_unlock(heap); +} diff --git a/components/heap/multi_heap_internal.h b/components/heap/multi_heap_internal.h index 2fd09a9ad06..3fcbb50a76d 100644 --- a/components/heap/multi_heap_internal.h +++ b/components/heap/multi_heap_internal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/heap/multi_heap_platform.h b/components/heap/multi_heap_platform.h index a5ce50208a5..f2d1516b25d 100644 --- a/components/heap/multi_heap_platform.h +++ b/components/heap/multi_heap_platform.h @@ -72,6 +72,7 @@ inline static void multi_heap_assert(bool condition, const char *format, int lin #define MULTI_HEAP_REMOVE_BLOCK_OWNER_OFFSET(HEAD) ((TaskHandle_t*)(HEAD) - 1) #define MULTI_HEAP_ADD_BLOCK_OWNER_SIZE(SIZE) ((SIZE) + sizeof(TaskHandle_t)) #define MULTI_HEAP_REMOVE_BLOCK_OWNER_SIZE(SIZE) ((SIZE) - sizeof(TaskHandle_t)) +#define MULTI_HEAP_BLOCK_OWNER_SIZE() sizeof(TaskHandle_t) #else #define MULTI_HEAP_SET_BLOCK_OWNER(HEAD) #define MULTI_HEAP_GET_BLOCK_OWNER(HEAD) (NULL) @@ -79,6 +80,7 @@ inline static void multi_heap_assert(bool condition, const char *format, int lin #define MULTI_HEAP_REMOVE_BLOCK_OWNER_OFFSET(HEAD) (HEAD) #define MULTI_HEAP_ADD_BLOCK_OWNER_SIZE(SIZE) (SIZE) #define MULTI_HEAP_REMOVE_BLOCK_OWNER_SIZE(SIZE) (SIZE) +#define MULTI_HEAP_BLOCK_OWNER_SIZE() 0 #endif // CONFIG_HEAP_TASK_TRACKING #else // MULTI_HEAP_FREERTOS diff --git a/components/heap/multi_heap_poisoning.c b/components/heap/multi_heap_poisoning.c index 6a1db4d70f0..faa8567986e 100644 --- a/components/heap/multi_heap_poisoning.c +++ b/components/heap/multi_heap_poisoning.c @@ -205,6 +205,11 @@ void block_absorb_post_hook(void *start, size_t size, bool is_free) #endif void *multi_heap_aligned_alloc(multi_heap_handle_t heap, size_t size, size_t alignment) +{ + return multi_heap_aligned_alloc_offs(heap, size, alignment, 0); +} + +void *multi_heap_aligned_alloc_offs(multi_heap_handle_t heap, size_t size, size_t alignment, size_t offset) { if (!size) { return NULL; @@ -216,7 +221,7 @@ void *multi_heap_aligned_alloc(multi_heap_handle_t heap, size_t size, size_t ali multi_heap_internal_lock(heap); poison_head_t *head = multi_heap_aligned_alloc_impl_offs(heap, size + POISON_OVERHEAD, - alignment, sizeof(poison_head_t)); + alignment, offset + sizeof(poison_head_t)); uint8_t *data = NULL; if (head != NULL) { data = poison_allocated_region(head, size); diff --git a/components/heap/port/esp32/memory_layout.c b/components/heap/port/esp32/memory_layout.c index 46106a829d5..b35d8c1b3ee 100644 --- a/components/heap/port/esp32/memory_layout.c +++ b/components/heap/port/esp32/memory_layout.c @@ -126,7 +126,7 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_mem These are removed from the soc_memory_regions array when heaps are created. */ SOC_RESERVE_MEMORY_REGION(SOC_CACHE_PRO_LOW, SOC_CACHE_PRO_HIGH, cpu0_cache); -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache); #endif @@ -147,7 +147,7 @@ SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache); */ SOC_RESERVE_MEMORY_REGION(0x3ffe0000, 0x3ffe0440, rom_pro_data); //Reserve ROM PRO data region -#ifndef CONFIG_FREERTOS_UNICORE +#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE SOC_RESERVE_MEMORY_REGION(0x3ffe3f20, 0x3ffe4350, rom_app_data); //Reserve ROM APP data region #endif diff --git a/components/heap/port/esp32c5/memory_layout.c b/components/heap/port/esp32c5/memory_layout.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/heap/port/esp32p4/memory_layout.c b/components/heap/port/esp32p4/memory_layout.c index eb29b5fb22a..dc5afa7496f 100644 --- a/components/heap/port/esp32p4/memory_layout.c +++ b/components/heap/port/esp32p4/memory_layout.c @@ -71,26 +71,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor /** * Register the shared buffer area of the last memory block into the heap during heap initialization */ -#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#define APP_USABLE_DIRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0 +#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040 const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM - { SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available -#endif - // base 192k is always avaible, even if we config l2 cache size to 512k - { 0x4ff00000, 0x30000, SOC_MEMORY_TYPE_L2MEM, 0x4ff00000, false}, - // 64k for rom startup stack - { 0x4ff30000, 0x10000, SOC_MEMORY_TYPE_L2MEM, 0x4ff30000, true}, -#if CONFIG_ESP32P4_L2_CACHE_256KB // 768-256 = 512k avaible for l2 memory, add extra 256k - { 0x4ff40000, 0x40000, SOC_MEMORY_TYPE_L2MEM, 0x4ff40000, false}, -#endif -#if CONFIG_ESP32P4_L2_CACHE_128KB // 768 - 128 = 640k avaible for l2 memory, add extra 384k - { 0x4ff40000, 0x60000, SOC_MEMORY_TYPE_L2MEM, 0x4ff40000, false}, + { SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available #endif + { SOC_DRAM_LOW, APP_USABLE_DIRAM_END - SOC_DRAM_LOW, SOC_MEMORY_TYPE_L2MEM, SOC_IRAM_LOW, false}, + { APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE, SOC_MEMORY_TYPE_L2MEM, APP_USABLE_DIRAM_END, true}, #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50108000, 0x8000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM + { 0x50108000, 0x8000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM #endif - { 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false}, + { 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false}, }; const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); @@ -98,6 +91,7 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_m extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; extern int _tcm_text_start, _tcm_data_end; +extern int _rtc_reserved_start, _rtc_reserved_end; /** * Reserved memory regions. @@ -118,6 +112,7 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region); #endif #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP -// TODO: IDF-6019 check reserved lp mem region SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); #endif + +SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c index ee875fb6cea..af4cb5bfb7e 100644 --- a/components/heap/port/memory_layout_utils.c +++ b/components/heap/port/memory_layout_utils.c @@ -71,8 +71,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c /* Get the ROM layout to find which part of DRAM is reserved */ const ets_rom_layout_t *layout = ets_rom_layout_p; reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start; -#if CONFIG_IDF_TARGET_ESP32P4 - //TODO: IDF-7921 +#ifdef SOC_DIRAM_ROM_RESERVE_HIGH reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH; #else reserved[0].end = SOC_DIRAM_DRAM_HIGH; diff --git a/components/heap/test_apps/heap_tests/main/CMakeLists.txt b/components/heap/test_apps/heap_tests/main/CMakeLists.txt index 9e9d865371b..0ed19610cea 100644 --- a/components/heap/test_apps/heap_tests/main/CMakeLists.txt +++ b/components/heap/test_apps/heap_tests/main/CMakeLists.txt @@ -7,7 +7,8 @@ set(src_test "test_heap_main.c" "test_malloc_caps.c" "test_malloc.c" "test_realloc.c" - "test_runtime_heap_reg.c") + "test_runtime_heap_reg.c" + "test_task_tracking.c") idf_component_register(SRCS ${src_test} INCLUDE_DIRS "." diff --git a/components/heap/test_apps/heap_tests/main/test_malloc_caps.c b/components/heap/test_apps/heap_tests/main/test_malloc_caps.c index 255a4fa5b6a..37441873eaf 100644 --- a/components/heap/test_apps/heap_tests/main/test_malloc_caps.c +++ b/components/heap/test_apps/heap_tests/main/test_malloc_caps.c @@ -171,6 +171,62 @@ TEST_CASE("heap_caps metadata test", "[heap]") TEST_ASSERT(after.minimum_free_bytes < original.total_free_bytes); } +TEST_CASE("heap caps minimum free bytes monitoring", "[heap]") +{ + printf("heap caps minimum free bytes monitoring local minimum\n"); + + uint32_t caps = MALLOC_CAP_DEFAULT; + size_t minimum_free_size_reference = heap_caps_get_minimum_free_size(caps); + + // start monitoring the value of minimum free bytes + esp_err_t ret_val = heap_caps_monitor_local_minimum_free_size_start(); + TEST_ASSERT_EQUAL(ret_val, ESP_OK); + + // get the heap info and check that the value of minimum free bytes return + // is different from the previous one (before monitoring) + size_t local_minimum_free_size = heap_caps_get_minimum_free_size(caps); + TEST_ASSERT(local_minimum_free_size >= minimum_free_size_reference); + + // allocate and free 400 bytes of memory. + size_t alloc_size = 400; + void *ptr = heap_caps_malloc(400, caps); + TEST_ASSERT(ptr != NULL); + heap_caps_free(ptr); + // Check the new value of minimum free bytes to make sure + // it is now lower than the previous one. + TEST_ASSERT(heap_caps_get_minimum_free_size(caps) <= local_minimum_free_size - alloc_size); + + // stop monitoring + ret_val = heap_caps_monitor_local_minimum_free_size_stop(); + TEST_ASSERT_EQUAL(ret_val, ESP_OK); + + // get the heap info and check that the value of minimum free bytes is lower than + // the local minimum (since the local minimum didn't create a new all time minimum) + size_t free_size = heap_caps_get_minimum_free_size(caps); + TEST_ASSERT(local_minimum_free_size >= free_size); +} + +TEST_CASE("heap caps minimum free bytes fault cases", "[heap]") +{ + printf("heap caps minimum free bytes fault cases\n"); + + // start monitoring the value of minimum free bytes + esp_err_t ret_val = heap_caps_monitor_local_minimum_free_size_start(); + TEST_ASSERT_EQUAL(ret_val, ESP_OK); + + // calling start again should be allowed + ret_val = heap_caps_monitor_local_minimum_free_size_start(); + TEST_ASSERT_EQUAL(ret_val, ESP_OK); + + // stop the monitoring + ret_val = heap_caps_monitor_local_minimum_free_size_stop(); + TEST_ASSERT_EQUAL(ret_val, ESP_OK); + + // calling stop monitoring when monitoring is not active should fail + ret_val = heap_caps_monitor_local_minimum_free_size_stop(); + TEST_ASSERT_NOT_EQUAL(ret_val, ESP_OK); +} + /* Small function runs from IRAM to check that malloc/free/realloc all work OK when cache is disabled... */ diff --git a/components/heap/test_apps/heap_tests/main/test_task_tracking.c b/components/heap/test_apps/heap_tests/main/test_task_tracking.c new file mode 100644 index 00000000000..99215969dc1 --- /dev/null +++ b/components/heap/test_apps/heap_tests/main/test_task_tracking.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "unity.h" +#include "stdio.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_heap_caps.h" +#include "esp_heap_task_info.h" + +// This test only apply when task tracking is enabled +#if defined(CONFIG_HEAP_TASK_TRACKING) + +#define MAX_TASK_NUM 10 // Max number of per tasks info that it can store +#define MAX_BLOCK_NUM 10 // Max number of per block info that it can store +#define ALLOC_BYTES 36 + +static void check_heap_task_info(TaskHandle_t taskHdl) +{ + size_t num_totals = 0; + heap_task_totals_t s_totals_arr[MAX_TASK_NUM]; + heap_task_block_t s_block_arr[MAX_BLOCK_NUM]; + + heap_task_info_params_t heap_info = {0}; + heap_info.caps[0] = MALLOC_CAP_32BIT; // Gets heap info with CAP_32BIT capabilities + heap_info.mask[0] = MALLOC_CAP_32BIT; + heap_info.tasks = NULL; // Passing NULL captures heap info for all tasks + heap_info.num_tasks = 0; + heap_info.totals = s_totals_arr; // Gets task wise allocation details + heap_info.num_totals = &num_totals; + heap_info.max_totals = MAX_TASK_NUM; // Maximum length of "s_totals_arr" + heap_info.blocks = s_block_arr; // Gets block wise allocation details. For each block, gets owner task, address and size + heap_info.max_blocks = MAX_BLOCK_NUM; // Maximum length of "s_block_arr" + + heap_caps_get_per_task_info(&heap_info); + + bool task_found = false; + for (int i = 0 ; i < *heap_info.num_totals; i++) { + // the prescheduler allocs and free are stored as a + // task with a handle set to 0, avoid calling pcTaskGetName + // in that case. + if (heap_info.totals[i].task != 0 && (uint32_t*)(heap_info.totals[i].task) == (uint32_t*)taskHdl) { + task_found = true; + // check the number of byte allocated according to the task tracking feature + // and make sure it matches the expected value. The size returned by the + // heap_caps_get_per_task_info includes the size of the block owner (4 bytes) + TEST_ASSERT(heap_info.totals[i].size[0] == ALLOC_BYTES + 4); + } + } + TEST_ASSERT_TRUE(task_found); +} + +static void test_task(void *args) +{ + void *ptr = heap_caps_malloc(ALLOC_BYTES, MALLOC_CAP_32BIT); + if (ptr == NULL) { + abort(); + } + + // unlock main too check task tracking feature + xTaskNotifyGive((TaskHandle_t)args); + + // wait for main to delete this task + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); +} + +/* This test will create a task, wait for the task to allocate / free memory + * so it is added to the task tracking info in the heap component and then + * call heap_caps_get_per_task_info() and make sure a task with the name test_task + * is in the list, and that the right ALLOC_BYTES are shown. + * + * Note: The memory allocated in the task is not freed for the sake of the test + * so it is normal that memory leak will be reported by the test environment. It + * shouldn't be more than the byte allocated by the task + associated metadata + */ +TEST_CASE("heap task tracking reports created task", "[heap]") +{ + TaskHandle_t test_task_handle; + + xTaskCreate(&test_task, "test_task", 3072, (void *)xTaskGetCurrentTaskHandle(), 5, &test_task_handle); + + // wait for task to allocate memory and give the hand back to the test + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + + // check that the task is referenced in the list of task + // by the task tracking feature. Check the number of bytes + // the task has allocated and make sure it is matching the + // expected value. + check_heap_task_info(test_task_handle); + + // delete the task. + vTaskDelete(test_task_handle); +} + +#endif // CONFIG_HEAP_TASK_TRACKING diff --git a/components/heap/test_apps/heap_tests/pytest_heap.py b/components/heap/test_apps/heap_tests/pytest_heap.py index c3684eff2d8..4bed368abab 100644 --- a/components/heap/test_apps/heap_tests/pytest_heap.py +++ b/components/heap/test_apps/heap_tests/pytest_heap.py @@ -13,7 +13,7 @@ [ 'no_poisoning', 'light_poisoning', - 'comprehensive_poisoning' + 'comprehensive_poisoning', ] ) def test_heap_poisoning(dut: Dut) -> None: diff --git a/components/heap/test_apps/heap_tests/sdkconfig.ci.no_poisoning b/components/heap/test_apps/heap_tests/sdkconfig.ci.no_poisoning index 657a7609284..58c6da62c40 100644 --- a/components/heap/test_apps/heap_tests/sdkconfig.ci.no_poisoning +++ b/components/heap/test_apps/heap_tests/sdkconfig.ci.no_poisoning @@ -1,3 +1,5 @@ CONFIG_HEAP_POISONING_DISABLED=y CONFIG_HEAP_POISONING_LIGHT=n CONFIG_HEAP_POISONING_COMPREHENSIVE=n + +CONFIG_HEAP_TASK_TRACKING=y # to make sure the config doesn't induce unexpected behavior diff --git a/components/idf_test/include/esp32/idf_performance_target.h b/components/idf_test/include/esp32/idf_performance_target.h index b2702fc9303..9d53efd10c8 100644 --- a/components/idf_test/include/esp32/idf_performance_target.h +++ b/components/idf_test/include/esp32/idf_performance_target.h @@ -45,3 +45,31 @@ #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 3 #define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3 3 + +//SDIO +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT 12200 +#endif + +#if !CONFIG_FREERTOS_SMP // IDF-5224 +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 11000 // TODO: IDF-5490 +#endif +#else +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 12200 +#endif +#endif + +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT 4000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT 4000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI 1000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI 1000 +#endif diff --git a/components/idf_test/include/esp32c5/.gitkeep b/components/idf_test/include/esp32c5/.gitkeep new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/idf_test/include/esp32c6/idf_performance_target.h b/components/idf_test/include/esp32c6/idf_performance_target.h index ee92a631f71..7fa8f6cd94f 100644 --- a/components/idf_test/include/esp32c6/idf_performance_target.h +++ b/components/idf_test/include/esp32c6/idf_performance_target.h @@ -30,3 +30,23 @@ #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 10 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 10 #define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3 10 + +//SDIO +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT 9000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 10000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT 4000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT 4000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI 1000 +#endif +#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI +#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI 1000 +#endif diff --git a/components/idf_test/include/idf_performance.h b/components/idf_test/include/idf_performance.h index 86f08dee68b..0a40dc14e19 100644 --- a/components/idf_test/include/idf_performance.h +++ b/components/idf_test/include/idf_performance.h @@ -95,33 +95,6 @@ #define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES 565 #endif -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_4BIT 12200 -#endif - -#if !CONFIG_FREERTOS_SMP // IDF-5224 -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 11000 // TODO: IDF-5490 -#endif -#else -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_4BIT 12200 -#endif -#endif - -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_1BIT 4000 -#endif -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_1BIT 4000 -#endif -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_TOHOST_SPI 1000 -#endif -#ifndef IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI -#define IDF_PERFORMANCE_MIN_SDIO_THROUGHPUT_KBSEC_FRHOST_SPI 1000 -#endif - //time to perform the task selection plus context switch (from task) #ifndef IDF_PERFORMANCE_MAX_SCHEDULING_TIME #define IDF_PERFORMANCE_MAX_SCHEDULING_TIME 2000 diff --git a/components/ieee802154/Kconfig b/components/ieee802154/Kconfig index aac79087012..9c5d18e2375 100644 --- a/components/ieee802154/Kconfig +++ b/components/ieee802154/Kconfig @@ -2,7 +2,7 @@ menu "IEEE 802.15.4" visible if SOC_IEEE802154_SUPPORTED config IEEE802154_ENABLED - bool + bool "IEEE802154 Enable" default "y" if SOC_IEEE802154_SUPPORTED config IEEE802154_RX_BUFFER_SIZE @@ -14,6 +14,7 @@ menu "IEEE 802.15.4" The number of 802.15.4 receive buffers choice IEEE802154_CCA_MODE + depends on IEEE802154_ENABLED prompt "Clear Channel Assessment (CCA) mode" default IEEE802154_CCA_ED help @@ -41,6 +42,7 @@ menu "IEEE 802.15.4" endchoice config IEEE802154_CCA_MODE + depends on IEEE802154_ENABLED int default 0 if IEEE802154_CCA_CARRIER default 1 if IEEE802154_CCA_ED @@ -49,6 +51,7 @@ menu "IEEE 802.15.4" config IEEE802154_CCA_THRESHOLD int "CCA detection threshold" + depends on IEEE802154_ENABLED range -120 0 default -60 help @@ -56,6 +59,7 @@ menu "IEEE 802.15.4" config IEEE802154_PENDING_TABLE_SIZE int "Pending table size" + depends on IEEE802154_ENABLED range 1 100 default 20 help @@ -63,12 +67,14 @@ menu "IEEE 802.15.4" config IEEE802154_MULTI_PAN_ENABLE bool "Enable multi-pan feature for frame filter" + depends on IEEE802154_ENABLED default n help Enable IEEE802154 multi-pan config IEEE802154_TIMING_OPTIMIZATION bool "Enable throughput optimization" + depends on IEEE802154_ENABLED default n help Enabling this option increases throughput by ~5% at the expense of ~2.1k @@ -77,7 +83,7 @@ menu "IEEE 802.15.4" config IEEE802154_SLEEP_ENABLE # Todo: Remove when support safe power-down of the power domain (IDF-7317) bool "Enable IEEE802154 light sleep" - depends on PM_ENABLE && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP + depends on PM_ENABLE && IEEE802154_ENABLED default n help Enabling this option allows the IEEE802.15.4 module to be powered down during automatic light sleep, @@ -85,6 +91,7 @@ menu "IEEE 802.15.4" menuconfig IEEE802154_DEBUG bool "Enable IEEE802154 Debug" + depends on IEEE802154_ENABLED default n help Enabling this option allows different kinds of IEEE802154 debug output. @@ -159,4 +166,11 @@ menu "IEEE 802.15.4" default 10 help set the record abort table size + + config IEEE802154_TXRX_STATISTIC + bool "Enable record tx/rx packets information for debugging" + depends on IEEE802154_DEBUG + default n + help + Enabling this option to record the tx and rx endmenu # IEEE 802.15.4 diff --git a/components/ieee802154/driver/esp_ieee802154_debug.c b/components/ieee802154/driver/esp_ieee802154_debug.c index 6398a05dd64..2b172ad9521 100644 --- a/components/ieee802154/driver/esp_ieee802154_debug.c +++ b/components/ieee802154/driver/esp_ieee802154_debug.c @@ -5,6 +5,7 @@ */ #include +#include #include "hal/ieee802154_ll.h" #include "esp_ieee802154_util.h" #include "esp_log.h" @@ -237,4 +238,122 @@ void ieee802154_assert_print(void) } #endif // CONFIG_IEEE802154_ASSERT +#if CONFIG_IEEE802154_TXRX_STATISTIC +static ieee802154_txrx_statistic_t s_ieee802154_txrx_statistic; + +void ieee802154_txrx_statistic_clear(void) +{ + memset(&s_ieee802154_txrx_statistic, 0, sizeof(ieee802154_txrx_statistic_t)); +} + +void ieee802154_txrx_statistic(ieee802154_ll_events events) +{ + if (events == IEEE802154_EVENT_TX_DONE) { + s_ieee802154_txrx_statistic.tx.done_nums++; + } else if (events == IEEE802154_EVENT_RX_DONE) { + s_ieee802154_txrx_statistic.rx.done_nums++; + } + s_ieee802154_txrx_statistic.tx.abort.cca_busy_nums += ieee802154_ll_get_cca_busy_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_CCA_BUSY_CNT_CLEAR); + s_ieee802154_txrx_statistic.tx.abort.tx_security_error_nums += ieee802154_ll_get_tx_security_error_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR); + + // Do not record TX_BREAK_COEX_ERR due to ZB-105. + + s_ieee802154_txrx_statistic.tx.abort.rx_ack_timeout_nums += ieee802154_ll_get_rx_ack_timeout_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR); + s_ieee802154_txrx_statistic.tx.abort.rx_ack_coex_break_nums += ieee802154_ll_get_rx_ack_abort_coex_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR); + s_ieee802154_txrx_statistic.tx.abort.cca_failed_nums += ieee802154_ll_get_cca_fail_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_CCA_FAIL_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.tx_ack_coex_break_nums += ieee802154_ll_get_tx_ack_abort_coex_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.rx_restart_nums += ieee802154_ll_get_rx_restart_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_RX_RESTART_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.rx_coex_break_nums += ieee802154_ll_get_rx_abort_coex_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_RX_ABORT_COEX_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.no_rss_nums += ieee802154_ll_get_no_rss_detect_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_NO_RSS_DETECT_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.filter_fail_nums += ieee802154_ll_get_rx_fliter_fail_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_RX_FILTER_FAIL_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.ed_abort_nums += ieee802154_ll_get_ed_abort_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_ED_ABORT_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.crc_error_nums += ieee802154_ll_get_crc_error_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_CRC_ERROR_CNT_CLEAR); + s_ieee802154_txrx_statistic.rx.abort.sfd_timeout_nums += ieee802154_ll_get_sfd_timeout_cnt(); + ieee802154_ll_clear_debug_cnt(IEEE802154_SFD_TIMEOUT_CNT_CLEAR); +} + +void ieee802154_tx_nums_update(void) +{ + s_ieee802154_txrx_statistic.tx.nums++; +} + +void ieee802154_tx_break_coex_nums_update(void) +{ + s_ieee802154_txrx_statistic.tx.abort.tx_coex_break_nums++; +} + +void ieee802154_txrx_statistic_print(void) +{ + uint64_t tx_success_nums = s_ieee802154_txrx_statistic.tx.done_nums - s_ieee802154_txrx_statistic.tx.abort.rx_ack_coex_break_nums - s_ieee802154_txrx_statistic.tx.abort.rx_ack_timeout_nums; + uint64_t tx_abort_nums = s_ieee802154_txrx_statistic.tx.abort.rx_ack_coex_break_nums + s_ieee802154_txrx_statistic.tx.abort.rx_ack_timeout_nums + + s_ieee802154_txrx_statistic.tx.abort.tx_coex_break_nums + s_ieee802154_txrx_statistic.tx.abort.tx_security_error_nums + + s_ieee802154_txrx_statistic.tx.abort.cca_failed_nums + s_ieee802154_txrx_statistic.tx.abort.cca_busy_nums; + + uint64_t tx_nums = s_ieee802154_txrx_statistic.tx.nums; + float tx_success_ratio = (tx_nums > 0 ? ((float)tx_success_nums / tx_nums) : 0); + float tx_done_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.done_nums / tx_nums) : 0); + float tx_abort_ratio = (tx_nums > 0 ? ((float)tx_abort_nums / tx_nums) : 0); + float tx_abort_rx_ack_coex_break_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.abort.rx_ack_coex_break_nums / tx_nums) : 0); + float tx_abort_rx_ack_timeout_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.abort.rx_ack_timeout_nums / tx_nums) : 0); + float tx_abort_tx_coex_break_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.abort.tx_coex_break_nums / tx_nums) : 0); + float tx_abort_tx_security_error_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.abort.tx_security_error_nums / tx_nums) : 0); + float tx_abort_cca_failed_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.abort.cca_failed_nums / tx_nums) : 0); + float tx_abort_cca_busy_ratio = (tx_nums > 0 ? ((float)s_ieee802154_txrx_statistic.tx.abort.cca_busy_nums / tx_nums) : 0); + + uint64_t rx_abort_nums = s_ieee802154_txrx_statistic.rx.abort.tx_ack_coex_break_nums + s_ieee802154_txrx_statistic.rx.abort.sfd_timeout_nums + + s_ieee802154_txrx_statistic.rx.abort.crc_error_nums + s_ieee802154_txrx_statistic.rx.abort.filter_fail_nums + + s_ieee802154_txrx_statistic.rx.abort.no_rss_nums + s_ieee802154_txrx_statistic.rx.abort.rx_coex_break_nums + + s_ieee802154_txrx_statistic.rx.abort.rx_restart_nums + s_ieee802154_txrx_statistic.rx.abort.ed_abort_nums; + uint64_t rx_success_nums = s_ieee802154_txrx_statistic.rx.done_nums - s_ieee802154_txrx_statistic.rx.abort.tx_ack_coex_break_nums; + + + ESP_LOGW(TAG, "+--------------------+-----------------------------------+--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-10s%-15llu%9.2f%%|%-25s%-15llu%9.2f%%|", "", "Done:", s_ieee802154_txrx_statistic.tx.done_nums, tx_done_ratio*100, "Success:", tx_success_nums, tx_success_ratio*100); + ESP_LOGW(TAG, "+ +-----------------------------------+--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-15llu%9.2f%%|", "", "", "rx_ack_coex_break:", s_ieee802154_txrx_statistic.tx.abort.rx_ack_coex_break_nums, tx_abort_rx_ack_coex_break_ratio*100); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-15llu%9.2f%%|", "", "", "rx_ack_timeout:", s_ieee802154_txrx_statistic.tx.abort.rx_ack_timeout_nums, tx_abort_rx_ack_timeout_ratio*100); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-5s%-15llu|%-10s%-15llu%9.2f%%|%-25s%-15llu%9.2f%%|", "TX:", s_ieee802154_txrx_statistic.tx.nums, "Abort", tx_abort_nums, tx_abort_ratio*100, "tx_coex_break:", s_ieee802154_txrx_statistic.tx.abort.tx_coex_break_nums, tx_abort_tx_coex_break_ratio*100); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-15llu%9.2f%%|", "", "", "tx_security_error:", s_ieee802154_txrx_statistic.tx.abort.tx_security_error_nums, tx_abort_tx_security_error_ratio*100); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-15llu%9.2f%%|", "", "", "cca_failed:", s_ieee802154_txrx_statistic.tx.abort.cca_failed_nums, tx_abort_cca_failed_ratio*100); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-15llu%9.2f%%|", "", "", "cca_busy:", s_ieee802154_txrx_statistic.tx.abort.cca_busy_nums, tx_abort_cca_busy_ratio*100); + ESP_LOGW(TAG, "+--------------------+-----------------------------------+--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-10s%-25llu|%-25s%-25llu|", "", "Done:", s_ieee802154_txrx_statistic.rx.done_nums, "Success:", rx_success_nums); + ESP_LOGW(TAG, "+ +-----------------------------------+--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "tx_ack_coex_break:", s_ieee802154_txrx_statistic.rx.abort.tx_ack_coex_break_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "sfd_timeout:", s_ieee802154_txrx_statistic.rx.abort.sfd_timeout_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "crc_error:", s_ieee802154_txrx_statistic.rx.abort.crc_error_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-10s%-25llu|%-25s%-25llu|", "RX", "Abort", rx_abort_nums, "filter_fail:", s_ieee802154_txrx_statistic.rx.abort.filter_fail_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "no_rss:", s_ieee802154_txrx_statistic.rx.abort.no_rss_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "rx_coex_break:", s_ieee802154_txrx_statistic.rx.abort.rx_coex_break_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "rx_restart:", s_ieee802154_txrx_statistic.rx.abort.rx_restart_nums); + ESP_LOGW(TAG, "+ + +--------------------------------------------------+"); + ESP_LOGW(TAG, "|%-20s|%-35s|%-25s%-25llu|", "", "", "ed_abort:", s_ieee802154_txrx_statistic.rx.abort.ed_abort_nums); + ESP_LOGW(TAG, "+--------------------+-----------------------------------+--------------------------------------------------+"); +} + +#endif // CONFIG_IEEE802154_TXRX_STATISTIC + #endif // CONFIG_IEEE802154_DEBUG diff --git a/components/ieee802154/driver/esp_ieee802154_dev.c b/components/ieee802154/driver/esp_ieee802154_dev.c index f0db360374d..67074f56cde 100644 --- a/components/ieee802154/driver/esp_ieee802154_dev.c +++ b/components/ieee802154/driver/esp_ieee802154_dev.c @@ -26,18 +26,19 @@ #include "esp_attr.h" #include "esp_phy_init.h" -#if CONFIG_FREERTOS_USE_TICKLESS_IDLE +#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE #include "esp_pm.h" #include "esp_private/esp_clk.h" #include "esp_private/sleep_retention.h" -static bool s_rf_closed = false; +#include "esp_private/sleep_modem.h" #if SOC_PM_RETENTION_HAS_CLOCK_BUG #define IEEE802154_LINK_OWNER ENTRY(3) #else #define IEEE802154_LINK_OWNER ENTRY(0) | ENTRY(2) #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG -#endif +#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE +static bool s_rf_closed = true; #define CCA_DETECTION_TIME 8 extern void bt_bb_set_zb_tx_on_delay(uint16_t time); @@ -50,9 +51,9 @@ static uint8_t s_rx_index = 0; static uint8_t s_enh_ack_frame[128]; static uint8_t s_recent_rx_frame_info_index; static portMUX_TYPE s_ieee802154_spinlock = portMUX_INITIALIZER_UNLOCKED; +static intr_handle_t s_ieee802154_isr_handle = NULL; static esp_err_t ieee802154_sleep_init(void); -static void ieee802154_rf_enable(void); static IRAM_ATTR void event_end_process(void) { @@ -454,7 +455,11 @@ static IRAM_ATTR void isr_handle_tx_abort(void) next_operation(); break; case IEEE802154_TX_ABORT_BY_TX_COEX_BREAK: +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + esp_coex_ieee802154_coex_break_notify(); +#endif IEEE802154_ASSERT(s_ieee802154_state == IEEE802154_STATE_TX || s_ieee802154_state == IEEE802154_STATE_TX_CCA); + IEEE802154_TX_BREAK_COEX_NUMS_UPDATE(); esp_ieee802154_transmit_failed(s_tx_frame, ESP_IEEE802154_TX_ERR_COEXIST); next_operation(); break; @@ -613,6 +618,12 @@ void ieee802154_enable(void) void ieee802154_disable(void) { modem_clock_module_disable(ieee802154_periph.module); +#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare, + sleep_modem_mac_bb_power_up_prepare); +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD +#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE ieee802154_set_state(IEEE802154_STATE_DISABLE); } @@ -621,6 +632,7 @@ esp_err_t ieee802154_mac_init(void) esp_err_t ret = ESP_OK; modem_clock_module_mac_reset(PERIPH_IEEE802154_MODULE); // reset ieee802154 MAC ieee802154_pib_init(); + IEEE802154_TXRX_STATISTIC_CLEAR(); ieee802154_ll_enable_events(IEEE802154_EVENT_MASK); #if !CONFIG_IEEE802154_TEST @@ -648,7 +660,7 @@ esp_err_t ieee802154_mac_init(void) ieee802154_set_state(IEEE802154_STATE_IDLE); // TODO: Add flags for IEEE802154 ISR allocating. TZ-102 - ret = esp_intr_alloc(ieee802154_periph.irq_id, 0, ieee802154_isr, NULL, NULL); + ret = esp_intr_alloc(ieee802154_periph.irq_id, 0, ieee802154_isr, NULL, &s_ieee802154_isr_handle); ESP_RETURN_ON_FALSE(ret == ESP_OK, ESP_FAIL, IEEE802154_TAG, "IEEE802154 MAC init failed"); ESP_RETURN_ON_FALSE(ieee802154_sleep_init() == ESP_OK, ESP_FAIL, IEEE802154_TAG, "IEEE802154 MAC sleep init failed"); @@ -656,6 +668,16 @@ esp_err_t ieee802154_mac_init(void) return ret; } +esp_err_t ieee802154_mac_deinit(void) +{ + esp_err_t ret = ESP_OK; + if (s_ieee802154_isr_handle) { + ret = esp_intr_free(s_ieee802154_isr_handle); + s_ieee802154_isr_handle = NULL; + } + return ret; +} + IEEE802154_STATIC void start_ed(uint32_t duration) { ieee802154_ll_enable_events(IEEE802154_EVENT_ED_DONE); @@ -665,6 +687,7 @@ IEEE802154_STATIC void start_ed(uint32_t duration) IEEE802154_STATIC void tx_init(const uint8_t *frame) { + IEEE802154_TX_NUMS_UPDATE(); s_tx_frame = (uint8_t *)frame; stop_current_operation(); ieee802154_pib_update(); @@ -680,7 +703,7 @@ IEEE802154_STATIC void tx_init(const uint8_t *frame) esp_err_t ieee802154_transmit(const uint8_t *frame, bool cca) { - ieee802154_rf_enable(); + IEEE802154_RF_ENABLE(); ieee802154_enter_critical(); tx_init(frame); @@ -708,7 +731,7 @@ esp_err_t ieee802154_transmit_at(const uint8_t *frame, bool cca, uint32_t time) { uint32_t tx_target_time; uint32_t current_time; - ieee802154_rf_enable(); + IEEE802154_RF_ENABLE(); tx_init(frame); IEEE802154_SET_TXRX_PTI(IEEE802154_SCENE_TX_AT); if (cca) { @@ -750,7 +773,7 @@ esp_err_t ieee802154_receive(void) // already in rx state, don't abort current rx operation return ESP_OK; } - ieee802154_rf_enable(); + IEEE802154_RF_ENABLE(); ieee802154_enter_critical(); rx_init(); @@ -763,7 +786,7 @@ esp_err_t ieee802154_receive_at(uint32_t time) { uint32_t rx_target_time = time - IEEE802154_RX_RAMPUP_TIME_US; uint32_t current_time; - ieee802154_rf_enable(); + IEEE802154_RF_ENABLE(); rx_init(); IEEE802154_SET_TXRX_PTI(IEEE802154_SCENE_RX_AT); set_next_rx_buffer(); @@ -788,28 +811,29 @@ static esp_err_t ieee802154_sleep_init(void) err = sleep_retention_entries_create(ieee802154_mac_regs_retention, ARRAY_SIZE(ieee802154_mac_regs_retention), REGDMA_LINK_PRI_7, SLEEP_RETENTION_MODULE_802154_MAC); ESP_RETURN_ON_ERROR(err, IEEE802154_TAG, "failed to allocate memory for ieee802154 mac retention"); ESP_LOGI(IEEE802154_TAG, "ieee802154 mac sleep retention initialization"); -#endif + +#if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD + sleep_modem_register_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare, + sleep_modem_mac_bb_power_up_prepare); +#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD +#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE return err; } -IRAM_ATTR static void ieee802154_rf_disable(void) +IRAM_ATTR void ieee802154_rf_disable(void) { -#if CONFIG_FREERTOS_USE_TICKLESS_IDLE if (s_rf_closed == false) { esp_phy_disable(PHY_MODEM_IEEE802154); s_rf_closed = true; } -#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE } -IRAM_ATTR static void ieee802154_rf_enable(void) +IRAM_ATTR void ieee802154_rf_enable(void) { -#if CONFIG_FREERTOS_USE_TICKLESS_IDLE if (s_rf_closed) { esp_phy_enable(PHY_MODEM_IEEE802154); s_rf_closed = false; } -#endif //CONFIG_FREERTOS_USE_TICKLESS_IDLE } esp_err_t ieee802154_sleep(void) @@ -819,14 +843,14 @@ esp_err_t ieee802154_sleep(void) stop_current_operation(); ieee802154_set_state(IEEE802154_STATE_SLEEP); ieee802154_exit_critical(); - ieee802154_rf_disable(); // colse rf + IEEE802154_RF_DISABLE(); } return ESP_OK; } esp_err_t ieee802154_energy_detect(uint32_t duration) { - ieee802154_rf_enable(); + IEEE802154_RF_ENABLE(); ieee802154_enter_critical(); stop_current_operation(); @@ -842,7 +866,7 @@ esp_err_t ieee802154_energy_detect(uint32_t duration) esp_err_t ieee802154_cca(void) { - ieee802154_rf_enable(); + IEEE802154_RF_ENABLE(); ieee802154_enter_critical(); stop_current_operation(); diff --git a/components/ieee802154/esp_ieee802154.c b/components/ieee802154/esp_ieee802154.c index 83900d2b02b..c97c32f582d 100644 --- a/components/ieee802154/esp_ieee802154.c +++ b/components/ieee802154/esp_ieee802154.c @@ -22,15 +22,17 @@ esp_err_t esp_ieee802154_enable(void) { ieee802154_enable(); - esp_phy_enable(PHY_MODEM_IEEE802154); + ieee802154_rf_enable(); esp_btbb_enable(); return ieee802154_mac_init(); } esp_err_t esp_ieee802154_disable(void) { + esp_btbb_disable(); + ieee802154_rf_disable(); ieee802154_disable(); - return ESP_OK; + return ieee802154_mac_deinit(); } uint8_t esp_ieee802154_get_channel(void) @@ -393,3 +395,15 @@ __attribute__((weak)) void esp_ieee802154_timer1_done(void) { } + +#if CONFIG_IEEE802154_TXRX_STATISTIC +void esp_ieee802154_txrx_statistic_clear(void) +{ + ieee802154_txrx_statistic_clear(); +} + +void esp_ieee802154_txrx_statistic_print(void) +{ + ieee802154_txrx_statistic_print(); +} +#endif // CONFIG_IEEE802154_TXRX_STATISTIC diff --git a/components/ieee802154/include/esp_ieee802154.h b/components/ieee802154/include/esp_ieee802154.h index 96de1a07758..0cb1cb272df 100644 --- a/components/ieee802154/include/esp_ieee802154.h +++ b/components/ieee802154/include/esp_ieee802154.h @@ -586,6 +586,24 @@ esp_err_t esp_ieee802154_set_transmit_security(uint8_t *frame, uint8_t *key, uin */ esp_err_t esp_ieee802154_enh_ack_generator(uint8_t *frame, esp_ieee802154_frame_info_t *frame_info, uint8_t* enhack_frame); +/** + * The configurable definitions via Kconfig + */ +#if CONFIG_IEEE802154_TXRX_STATISTIC + +/** + * @brief Clear the current IEEE802.15.4 statistic. + * + */ +void esp_ieee802154_txrx_statistic_clear(void); + +/** + * @brief Print the current IEEE802.15.4 statistic. + * + */ +void esp_ieee802154_txrx_statistic_print(void); +#endif // CONFIG_IEEE802154_TXRX_STATISTIC + #ifdef __cplusplus } #endif diff --git a/components/ieee802154/private_include/esp_ieee802154_dev.h b/components/ieee802154/private_include/esp_ieee802154_dev.h index 7fc5756134d..847c8a47a8e 100644 --- a/components/ieee802154/private_include/esp_ieee802154_dev.h +++ b/components/ieee802154/private_include/esp_ieee802154_dev.h @@ -55,6 +55,17 @@ void ieee802154_enable(void); */ void ieee802154_disable(void); +/** + * @brief Enable the RF. + * + */ +void ieee802154_rf_enable(void); + +/** + * @brief Disable the RF. + * + */ +void ieee802154_rf_disable(void); /** * @brief Initialize the IEEE 802.15.4 MAC. * @@ -65,6 +76,16 @@ void ieee802154_disable(void); */ esp_err_t ieee802154_mac_init(void); +/** + * @brief Deinitialize the IEEE 802.15.4 MAC. + * + * @return + * - ESP_OK on success. + * - ESP_FAIL on failure. + * + */ +esp_err_t ieee802154_mac_deinit(void); + /** * @brief Transmit the given frame. * diff --git a/components/ieee802154/private_include/esp_ieee802154_util.h b/components/ieee802154/private_include/esp_ieee802154_util.h index ccf8eb927e5..3288ac9e800 100644 --- a/components/ieee802154/private_include/esp_ieee802154_util.h +++ b/components/ieee802154/private_include/esp_ieee802154_util.h @@ -15,9 +15,17 @@ extern "C" { #endif +#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE +#define IEEE802154_RF_ENABLE() ieee802154_rf_enable() +#define IEEE802154_RF_DISABLE() ieee802154_rf_disable() +#else +#define IEEE802154_RF_ENABLE() +#define IEEE802154_RF_DISABLE() +#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE #define IEEE802154_PROBE(a) do { \ IEEE802154_RECORD_EVENT(a); \ ieee802154_record_abort(a); \ + IEEE802154_TXRX_STATISTIC(a); \ } while(0) #if CONFIG_IEEE802154_RECORD_EVENT @@ -173,6 +181,62 @@ void ieee802154_assert_print(void); #define IEEE802154_ASSERT(a) assert(a) #endif // CONFIG_IEEE802154_ASSERT +#if CONFIG_IEEE802154_TXRX_STATISTIC +typedef struct ieee802154_txrx_statistic{ + struct { + uint64_t nums; + uint64_t done_nums; + struct { + uint64_t rx_ack_coex_break_nums; // IEEE802154_RX_ACK_ABORT_COEX_CNT_REG + uint64_t rx_ack_timeout_nums; // IEEE802154_RX_ACK_TIMEOUT_CNT_REG + uint64_t tx_coex_break_nums; // IEEE802154_TX_BREAK_COEX_CNT_REG + uint64_t tx_security_error_nums; // IEEE802154_TX_SECURITY_ERROR_CNT_REG + uint64_t cca_failed_nums; // IEEE802154_CCA_FAIL_CNT_REG + uint64_t cca_busy_nums; // IEEE802154_CCA_BUSY_CNT_REG + } abort; + } tx; + struct { + uint64_t done_nums; + struct { + uint64_t sfd_timeout_nums; // IEEE802154_SFD_TIMEOUT_CNT_REG + uint64_t crc_error_nums; // IEEE802154_CRC_ERROR_CNT_REG + uint64_t filter_fail_nums; // IEEE802154_RX_FILTER_FAIL_CNT_REG + uint64_t no_rss_nums; // IEEE802154_NO_RSS_DETECT_CNT_REG + uint64_t rx_coex_break_nums; // IEEE802154_RX_ABORT_COEX_CNT_REG + uint64_t rx_restart_nums; // IEEE802154_RX_RESTART_CNT_REG + uint64_t tx_ack_coex_break_nums; // IEEE802154_TX_ACK_ABORT_COEX_CNT_REG + uint64_t ed_abort_nums; // IEEE802154_ED_ABORT_CNT_REG + } abort; + } rx; +} ieee802154_txrx_statistic_t; + +#define IEEE802154_TXRX_STATISTIC_CLEAR() do { \ + ieee802154_txrx_statistic_clear();\ + } while(0) + +#define IEEE802154_TXRX_STATISTIC(a) do { \ + ieee802154_txrx_statistic(a);\ + } while(0) + +#define IEEE802154_TX_NUMS_UPDATE() do { \ + ieee802154_tx_nums_update();\ + } while(0) + +#define IEEE802154_TX_BREAK_COEX_NUMS_UPDATE() do { \ + ieee802154_tx_break_coex_nums_update();\ + } while(0) + +void ieee802154_txrx_statistic_clear(void); +void ieee802154_txrx_statistic_print(void); +void ieee802154_txrx_statistic(ieee802154_ll_events events); +void ieee802154_tx_nums_update(void); +void ieee802154_tx_break_coex_nums_update(void); +#else +#define IEEE802154_TXRX_STATISTIC(a) +#define IEEE802154_TX_NUMS_UPDATE() +#define IEEE802154_TXRX_STATISTIC_CLEAR() +#define IEEE802154_TX_BREAK_COEX_NUMS_UPDATE() +#endif // CONFIG_IEEE802154_TXRX_STATISTIC // TODO: replace etm code using common interface diff --git a/components/linux/CMakeLists.txt b/components/linux/CMakeLists.txt index b7d2bd46a70..c3b72b56bc5 100644 --- a/components/linux/CMakeLists.txt +++ b/components/linux/CMakeLists.txt @@ -3,5 +3,10 @@ if(NOT "${target}" STREQUAL "linux") return() endif() +if(CMAKE_HOST_SYSTEM_NAME STREQUAL "Darwin") + list(APPEND srcs getrandom.c assert_func.c) +endif() + idf_component_register(INCLUDE_DIRS include - REQUIRED_IDF_TARGETS linux) + REQUIRED_IDF_TARGETS linux + SRCS ${srcs}) diff --git a/components/linux/assert_func.c b/components/linux/assert_func.c new file mode 100644 index 00000000000..6d2312b4874 --- /dev/null +++ b/components/linux/assert_func.c @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "hal/assert.h" + +// Implementation of __assert_func for macOS. +void __assert_func(const char *file, int line, const char *func, const char *expr) +{ + fprintf(stderr, "assert failed at %s:%d (%s): %s\n", file, line, func, expr); + abort(); +} + +// Defining this symbol as well, since `hal` component will add "-U __assert_func" linker option, +// and symbols are prefixed with an additional underscore on macOS. +// (Can't use __attribute__((alias)) because aliases are not supported on macOS.) +void _assert_func(const char *file, int line, const char *func, const char *expr) +{ + __assert_func(file, line, func, expr); +} diff --git a/components/linux/getrandom.c b/components/linux/getrandom.c new file mode 100644 index 00000000000..5f068ee3fdd --- /dev/null +++ b/components/linux/getrandom.c @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sys/random.h" +#include +#include +#include +#include + + +// getrandom() is not available on macOS, so we read from /dev/urandom instead. + +int getrandom(void *buf, size_t buflen, unsigned int flags) +{ + int fd = open("/dev/urandom", O_RDONLY); + if (fd < 0) { + return -1; + } + ssize_t ret = read(fd, buf, buflen); + close(fd); + if (ret < 0) { + return -1; + } + return 0; +} diff --git a/components/tcp_transport/host_test/main/catch_main.cpp b/components/linux/include/machine/endian.h similarity index 55% rename from components/tcp_transport/host_test/main/catch_main.cpp rename to components/linux/include/machine/endian.h index eda0c3afe68..8f6fe5d4586 100644 --- a/components/tcp_transport/host_test/main/catch_main.cpp +++ b/components/linux/include/machine/endian.h @@ -3,5 +3,9 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#define CATCH_CONFIG_MAIN -#include "catch/catch.hpp" +#pragma once +#if __APPLE__ +#include_next +#else +#include +#endif diff --git a/components/linux/include/sys/random.h b/components/linux/include/sys/random.h new file mode 100644 index 00000000000..b495f327bc7 --- /dev/null +++ b/components/linux/include/sys/random.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include_next "sys/random.h" + +#if __APPLE__ +#include + +int getrandom(void *buf, size_t buflen, unsigned int flags); + +#endif // __APPLE__ diff --git a/components/log/README.rst b/components/log/README.rst index afc29dd7d55..7129e898119 100644 --- a/components/log/README.rst +++ b/components/log/README.rst @@ -1,120 +1 @@ -Logging library -=============== - -Overview --------- - -The logging library provides three ways for setting log verbosity: - -- **At compile time**: in menuconfig, set the verbosity level using the option :ref:`CONFIG_LOG_DEFAULT_LEVEL`. -- Optionally, also in menuconfig, set the maximum verbosity level using the option :ref:`CONFIG_LOG_MAXIMUM_LEVEL`. By default, this is the same as the default level, but it can be set higher in order to compile more optional logs into the firmware. -- **At runtime**: all logs for verbosity levels lower than :ref:`CONFIG_LOG_DEFAULT_LEVEL` are enabled by default. The function :cpp:func:`esp_log_level_set` can be used to set a logging level on a per-module basis. Modules are identified by their tags, which are human-readable ASCII zero-terminated strings. -- **At runtime**: if :ref:`CONFIG_LOG_MASTER_LEVEL` is enabled then a ``Master logging level`` can be set using :cpp:func:`esp_log_set_level_master`. This option adds an additional logging level check for all compiled logs. Note that this will increase application size. This feature is useful if you want to compile in a lot of logs that are selectable at runtime, but also want to avoid the performance hit from looking up the tags and their log level when you don't want log output. - -There are the following verbosity levels: - -- Error (lowest) -- Warning -- Info -- Debug -- Verbose (highest) - -.. note:: - - The function :cpp:func:`esp_log_level_set` cannot set logging levels higher than specified by :ref:`CONFIG_LOG_MAXIMUM_LEVEL`. To increase log level for a specific file above this maximum at compile time, use the macro `LOG_LOCAL_LEVEL` (see the details below). - - -How to use this library ------------------------ - -In each C file that uses logging functionality, define the TAG variable as shown below: - -.. code-block:: c - - static const char* TAG = "MyModule"; - -Then use one of logging macros to produce output, e.g: - -.. code-block:: c - - ESP_LOGW(TAG, "Baud rate error %.1f%%. Requested: %d baud, actual: %d baud", error * 100, baud_req, baud_real); - -Several macros are available for different verbosity levels: - -* ``ESP_LOGE`` - error (lowest) -* ``ESP_LOGW`` - warning -* ``ESP_LOGI`` - info -* ``ESP_LOGD`` - debug -* ``ESP_LOGV`` - verbose (highest) - -Additionally, there are ``ESP_EARLY_LOGx`` versions for each of these macros, e.g. :c:macro:`ESP_EARLY_LOGE`. These versions have to be used explicitly in the early startup code only, before heap allocator and syscalls have been initialized. Normal ``ESP_LOGx`` macros can also be used while compiling the bootloader, but they will fall back to the same implementation as ``ESP_EARLY_LOGx`` macros. - -There are also ``ESP_DRAM_LOGx`` versions for each of these macros, e.g. :c:macro:`ESP_DRAM_LOGE`. These versions are used in some places where logging may occur with interrupts disabled or with flash cache inaccessible. Use of this macros should be as sparing as possible, as logging in these types of code should be avoided for performance reasons. - -.. note:: - - Inside critical sections interrupts are disabled so it's only possible to use ``ESP_DRAM_LOGx`` (preferred) or ``ESP_EARLY_LOGx``. Even though it's possible to log in these situations, it's better if your program can be structured not to require it. - -To override default verbosity level at file or component scope, define the ``LOG_LOCAL_LEVEL`` macro. - -At file scope, define it before including ``esp_log.h``, e.g.: - -.. code-block:: c - - #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE - #include "esp_log.h" - -At component scope, define it in the component CMakeLists: - -.. code-block:: cmake - - target_compile_definitions(${COMPONENT_LIB} PUBLIC "-DLOG_LOCAL_LEVEL=ESP_LOG_VERBOSE") - -To configure logging output per module at runtime, add calls to the function :cpp:func:`esp_log_level_set` as follows: - -.. code-block:: c - - esp_log_level_set("*", ESP_LOG_ERROR); // set all components to ERROR level - esp_log_level_set("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack - esp_log_level_set("dhcpc", ESP_LOG_INFO); // enable INFO logs from DHCP client - -.. note:: - - The "DRAM" and "EARLY" log macro variants documented above do not support per module setting of log verbosity. These macros will always log at the "default" verbosity level, which can only be changed at runtime by calling ``esp_log_level("*", level)``. - -Even when logs are disabled by using a tag name they will still require a processing time of around 10.9 microseconds per entry. - -Master Logging Level -^^^^^^^^^^^^^^^^^^^^ - -To enable the Master logging level feature, the :ref:`CONFIG_LOG_MASTER_LEVEL` option must be enabled. It adds an additional level check for ``ESP_LOGx`` macros before calling :cpp:func:`esp_log_write`. This allows to set a higher :ref:`CONFIG_LOG_MAXIMUM_LEVEL`, but not inflict a performance hit during normal operation (only when directed). An application may set the master logging level (:cpp:func:`esp_log_set_level_master`) globally to enforce a maximum log level. ``ESP_LOGx`` macros above this level will be skipped immediately, rather than calling :cpp:func:`esp_log_write` and doing a tag lookup. It is recommended to only use this in an top-level application and not in shared components as this would override the global log level for any user using the component. By default, at startup, the Master logging level is :ref:`CONFIG_LOG_DEFAULT_LEVEL`. - -Note that this feature increases application size because the additional check is added into all ``ESP_LOGx`` macros. - -The snippet below shows how it works. Setting the Master logging level to ``ESP_LOG_NONE`` disables all logging globally. :cpp:func:`esp_log_level_set` does not currently affect logging. But after the Master logging level is released, the logs will be printed as set by :cpp:func:`esp_log_level_set`. - -.. code-block:: c - - // Master logging level is CONFIG_LOG_DEFAULT_LEVEL at start up and = ESP_LOG_INFO - ESP_LOGI("lib_name", "Message for print"); // prints a INFO message - esp_log_level_set("lib_name", ESP_LOG_WARN); // enables WARN logs from lib_name - - esp_log_set_level_master(ESP_LOG_NONE); // disables all logs globally. esp_log_level_set has no effect at the moment. - - ESP_LOGW("lib_name", "Message for print"); // no print, Master logging level blocks it - esp_log_level_set("lib_name", ESP_LOG_INFO); // enable INFO logs from lib_name - ESP_LOGI("lib_name", "Message for print"); // no print, Master logging level blocks it - - esp_log_set_level_master(ESP_LOG_INFO); // enables all INFO logs globally. - - ESP_LOGI("lib_name", "Message for print"); // prints a INFO message - -Logging to Host via JTAG -^^^^^^^^^^^^^^^^^^^^^^^^ - -By default, the logging library uses the vprintf-like function to write formatted output to the dedicated UART. By calling a simple API, all log output may be routed to JTAG instead, making logging several times faster. For details, please refer to Section :ref:`app_trace-logging-to-host`. - -Thread Safety -^^^^^^^^^^^^^ - -The log string is first written into a memory buffer and then sent to the UART for printing. Log calls are thread-safe, i.e., logs of different threads do not conflict with each other. +Please see :doc:`docs/en/api-reference/system/log.rst` for more details. \ No newline at end of file diff --git a/components/log/host_test/log_test/main/CMakeLists.txt b/components/log/host_test/log_test/main/CMakeLists.txt index e1f4369f208..20b0d424352 100644 --- a/components/log/host_test/log_test/main/CMakeLists.txt +++ b/components/log/host_test/log_test/main/CMakeLists.txt @@ -1,5 +1,8 @@ idf_component_register(SRCS "log_test.cpp" - INCLUDE_DIRS - "." - $ENV{IDF_PATH}/tools/catch - REQUIRES log) + INCLUDE_DIRS "." + REQUIRES log + WHOLE_ARCHIVE) + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/log/host_test/log_test/main/idf_component.yml b/components/log/host_test/log_test/main/idf_component.yml new file mode 100644 index 00000000000..f7982136b97 --- /dev/null +++ b/components/log/host_test/log_test/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/catch2: "^3.4.0" diff --git a/components/log/host_test/log_test/main/log_test.cpp b/components/log/host_test/log_test/main/log_test.cpp index a4befc9a24f..40da7d37630 100644 --- a/components/log/host_test/log_test/main/log_test.cpp +++ b/components/log/host_test/log_test/main/log_test.cpp @@ -6,13 +6,12 @@ software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */ -#define CATCH_CONFIG_MAIN #include #include #include #include "esp_log.h" -#include "catch.hpp" +#include using namespace std; diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig index 6fadf80b25b..6204816fd42 100644 --- a/components/lwip/Kconfig +++ b/components/lwip/Kconfig @@ -124,6 +124,14 @@ menu "LWIP" This option is used to disable the Network Discovery Protocol (NDP) if it is not required. Please use this option with caution, as the NDP is essential for IPv6 functionality within a local network. + config LWIP_FORCE_ROUTER_FORWARDING + bool "LWIP Force Router Forwarding Enable/Disable" + default n + depends on LWIP_ND6 + help + This option is used to set the the router flag for the NA packets. + When enabled, the router flag in NA packet will always set to 1, otherwise, never set router flag for NA packets. + config LWIP_MAX_SOCKETS int "Max number of open sockets" range 1 16 @@ -678,7 +686,8 @@ menu "LWIP" int "The maximum number of pbufs queued on OOSEQ per pcb" depends on LWIP_TCP_QUEUE_OOSEQ range 0 12 - default 4 + default 4 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP + default 0 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP help If LWIP_TCP_OOSEQ_MAX_PBUFS = 0, TCP will not control the number of OOSEQ pbufs. diff --git a/components/lwip/lwip b/components/lwip/lwip index 4a8286ab8bc..f5c43549e5d 160000 --- a/components/lwip/lwip +++ b/components/lwip/lwip @@ -1 +1 @@ -Subproject commit 4a8286ab8bcf983f22421e3d4be650837b5eb277 +Subproject commit f5c43549e5d12ec2105a43c27986416124143e6e diff --git a/components/lwip/port/hooks/lwip_default_hooks.c b/components/lwip/port/hooks/lwip_default_hooks.c index 251aae0f485..ede43bdfc54 100644 --- a/components/lwip/port/hooks/lwip_default_hooks.c +++ b/components/lwip/port/hooks/lwip_default_hooks.c @@ -124,11 +124,11 @@ ip4_route_src_hook(const ip4_addr_t *src,const ip4_addr_t *dest) #if LWIP_DHCP_ENABLE_VENDOR_SPEC_IDS #define DHCP_OPTION_VSI 43 #define DHCP_OPTION_VCI 60 -#define DHCP_OPTION_VSI_MAX 16 +#define DHCP_OPTION_VSI_MAX 64 static u8_t vendor_class_len = 0; static char *vendor_class_buf = NULL; -static u32_t dhcp_option_vsi[DHCP_OPTION_VSI_MAX] = {0}; +static u8_t dhcp_option_vsi[DHCP_OPTION_VSI_MAX]; void dhcp_free_vendor_class_identifier(void) { @@ -209,16 +209,10 @@ void dhcp_parse_extra_opts(struct dhcp *dhcp, uint8_t state, uint8_t option, uin if ((option == DHCP_OPTION_VSI) && (state == DHCP_STATE_REBOOTING || state == DHCP_STATE_REBINDING || state == DHCP_STATE_RENEWING || state == DHCP_STATE_REQUESTING || state == DHCP_STATE_SELECTING)) { - u8_t n; - u32_t value; u16_t copy_len; - for (n = 0; n < DHCP_OPTION_VSI_MAX && len > 0; n++) { - copy_len = LWIP_MIN(len, 4); - LWIP_ERROR("dhcp_parse_extra_opts(): extracting VSI option failed", - pbuf_copy_partial(p, &value, copy_len, offset) == copy_len, return;); - dhcp_option_vsi[n] = lwip_htonl(value); - len -= copy_len; - } + copy_len = LWIP_MIN(len, sizeof(dhcp_option_vsi)); + LWIP_ERROR("dhcp_parse_extra_opts(): extracting VSI option failed", + pbuf_copy_partial(p, &dhcp_option_vsi, copy_len, offset) == copy_len, return;); } /* DHCP_OPTION_VSI */ #endif /* LWIP_DHCP_ENABLE_VENDOR_SPEC_IDS */ } diff --git a/components/lwip/port/include/lwipopts.h b/components/lwip/port/include/lwipopts.h index 1c981f8fc43..55ce6558f82 100644 --- a/components/lwip/port/include/lwipopts.h +++ b/components/lwip/port/include/lwipopts.h @@ -1169,6 +1169,16 @@ static inline uint32_t timeout_from_offered(uint32_t lease, uint32_t min) #define LWIP_ND6 0 #endif +/** + * LWIP_FORCE_ROUTER_FORWARDING==1: the router flag in NA packet will always set to 1, + * otherwise, never set router flag for NA packets. + */ +#ifdef CONFIG_LWIP_FORCE_ROUTER_FORWARDING +#define LWIP_FORCE_ROUTER_FORWARDING 1 +#else +#define LWIP_FORCE_ROUTER_FORWARDING 0 +#endif + /** * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif. */ diff --git a/components/lwip/test_apps/sdkconfig.ci.lwip_debug b/components/lwip/test_apps/sdkconfig.ci.lwip_debug new file mode 100644 index 00000000000..a351db0a709 --- /dev/null +++ b/components/lwip/test_apps/sdkconfig.ci.lwip_debug @@ -0,0 +1,25 @@ +# Included for build test with LWIP debug enabled. + +CONFIG_LWIP_IP_FORWARD=y +CONFIG_LWIP_IPV4_NAPT=y +CONFIG_LWIP_DEBUG=y +CONFIG_LWIP_DEBUG_ESP_LOG=y +CONFIG_LWIP_NETIF_DEBUG=y +CONFIG_LWIP_PBUF_DEBUG=y +CONFIG_LWIP_ETHARP_DEBUG=y +CONFIG_LWIP_API_LIB_DEBUG=y +CONFIG_LWIP_SOCKETS_DEBUG=y +CONFIG_LWIP_IP_DEBUG=y +CONFIG_LWIP_ICMP_DEBUG=y +CONFIG_LWIP_DHCP_STATE_DEBUG=y +CONFIG_LWIP_DHCP_DEBUG=y +CONFIG_LWIP_IP6_DEBUG=y +CONFIG_LWIP_ICMP6_DEBUG=y +CONFIG_LWIP_TCP_DEBUG=y +CONFIG_LWIP_UDP_DEBUG=y +CONFIG_LWIP_SNTP_DEBUG=y +CONFIG_LWIP_DNS_DEBUG=y +CONFIG_LWIP_NAPT_DEBUG=y +CONFIG_LWIP_BRIDGEIF_DEBUG=y +CONFIG_LWIP_BRIDGEIF_FDB_DEBUG=y +CONFIG_LWIP_BRIDGEIF_FW_DEBUG=y diff --git a/components/mbedtls/Kconfig b/components/mbedtls/Kconfig index 8fc0f0eb2b7..d10b33f7ee4 100644 --- a/components/mbedtls/Kconfig +++ b/components/mbedtls/Kconfig @@ -239,7 +239,6 @@ menu "mbedTLS" config MBEDTLS_SSL_KEEP_PEER_CERTIFICATE bool "Keep peer certificate after handshake completion" default y - depends on !MBEDTLS_DYNAMIC_FREE_PEER_CERT help Keep the peer's certificate after completion of the handshake. Disabling this option will save about 4kB of heap and some code size. @@ -528,14 +527,14 @@ menu "mbedTLS" default n help This option enables hardware acceleration for ECDSA sign function, only - when using ATECC608A cryptoauth chip (integrated with ESP32-WROOM-32SE) + when using ATECC608A cryptoauth chip. config MBEDTLS_ATCA_HW_ECDSA_VERIFY bool "Enable hardware ECDSA verify acceleration when using ATECC608A" default n help This option enables hardware acceleration for ECDSA sign function, only - when using ATECC608A cryptoauth chip (integrated with ESP32-WROOM-32SE) + when using ATECC608A cryptoauth chip. config MBEDTLS_HAVE_TIME bool "Enable mbedtls time support" diff --git a/components/mbedtls/esp_crt_bundle/cacrt_all.pem b/components/mbedtls/esp_crt_bundle/cacrt_all.pem index 9551dfd830b..d8fda7d1ae6 100644 --- a/components/mbedtls/esp_crt_bundle/cacrt_all.pem +++ b/components/mbedtls/esp_crt_bundle/cacrt_all.pem @@ -1,7 +1,7 @@ ## ## Bundle of CA Root Certificates ## -## Certificate data from Mozilla as of: Tue Aug 22 03:12:04 2023 GMT +## Certificate data from Mozilla as of: Tue Dec 12 04:12:04 2023 GMT ## ## This is a bundle of X.509 certificates of public Certificate Authorities ## (CA). These were automatically extracted from Mozilla's root certificates @@ -14,7 +14,7 @@ ## Just configure this file as the SSLCACertificateFile. ## ## Conversion done with mk-ca-bundle.pl version 1.29. -## SHA256: 0ff137babc6a5561a9cfbe9f29558972e5b528202681b7d3803d03a3e82922bd +## SHA256: 1970dd65858925d68498d2356aea6d03f764422523c5887deca8ce3ba9e1f845 ## @@ -200,27 +200,6 @@ vGJHvOB0K7Lrfb5BG7XARsWhIstfTsEokt4YutUqKLsRixeTmJlglFwjz1onl14LBQaTNx47aTbr qZ5hHY8y2o4M1nQ+ewkk2gF3R8Q7zTSMmfXK4SVhM7JZG+Ju1zdXtg2pEto= -----END CERTIFICATE----- -Security Communication Root CA -============================== ------BEGIN CERTIFICATE----- -MIIDWjCCAkKgAwIBAgIBADANBgkqhkiG9w0BAQUFADBQMQswCQYDVQQGEwJKUDEYMBYGA1UEChMP -U0VDT00gVHJ1c3QubmV0MScwJQYDVQQLEx5TZWN1cml0eSBDb21tdW5pY2F0aW9uIFJvb3RDQTEw -HhcNMDMwOTMwMDQyMDQ5WhcNMjMwOTMwMDQyMDQ5WjBQMQswCQYDVQQGEwJKUDEYMBYGA1UEChMP -U0VDT00gVHJ1c3QubmV0MScwJQYDVQQLEx5TZWN1cml0eSBDb21tdW5pY2F0aW9uIFJvb3RDQTEw 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diff --git a/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem b/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem index f5ec79d41ed..26d9e4b656e 100644 --- a/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem +++ b/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem @@ -7,7 +7,7 @@ ## These certificates might be removed from ESP-IDF during every major release. -## The current deprecated certificate bundle is up-to-date with the Mozilla cert bundle (cacrt_all.pem) dated Tue Aug 22 03:12:04 2023 GMT +## The current deprecated certificate bundle is up-to-date with the Mozilla cert bundle (cacrt_all.pem) dated Tue Dec 12 04:12:04 2023 GMT Hongkong Post Root CA 1 @@ -112,3 +112,57 @@ zPUwHQYDVR0OBBYEFP+CMXI++cRmbK04ntGwUYilkMz1MA4GA1UdDwEB/wQEAwIBBjAKBggqhkjO PQQDAwNpADBmAjEA5gVYaWHlLcoNy/EZCL3W/VGSGn5jVASQkZo1kTmZ+gepZpO6yGjUij/67W4W Aie3AjEA3VoXK3YdZUKWpqxdinlW2Iob35reX8dQj7FbcQwm32pAAOwzkSFxvmjkI6TZraE3 -----END CERTIFICATE----- + +Security Communication Root CA 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+51tkljYyGOylMnfX40S2wBEqgLk9am58m9Ot/MPWo+ZkKXzR4Tgegiv/J2Wv+xYVxC5xhOW1//qk +R71kMrv2JYSiJ0L1ILDCExARzRAVukKQKtJE4ZYm6zFIEv0q2skGz3QeqUvVhyj5eTSSPi5E6PaP +T481PyWzOdxjKpBrIF/EUhJOlywqrJ2X3kjyo2bbwtKDlaZmp54lD+kLM5FlClrD2VQS3a/DTg4f +Jl4N3LON7NWBcN7STyQF82xO9UxJZo3R/9ILJUFI/lGExkKvgATP0H5kSeTy36LssUzAKh3ntLFl +osS88Zj0qnAHY7S42jtM+kAiMFsRpvAFDsYCA0irhpuF3dvd6qJ2gHN99ZwExEWN57kci57q13XR +crHedUTnQn3iV2t93Jm8PYMo6oCTjcVMZcFwgbg4/EMxsvYDNEeyrPsiBsse3RdHHF9mudMaotoR +saS8I8nkvof/uZS2+F0gStRf571oe2XyFR7SOqkt6dhrJKyXWERHrVkY8SFlcN7ONGCoQPHzPKTD +KCOM/iczQ0CgFzzr6juwcqajuUpLXhZI9LK8yIySxZ2frHI2vDSANGupi5LAuBft7HZT9SQBjLMi +6Et8Vcad+qMUu2WFbm5PEn4KPJ2V +-----END CERTIFICATE----- diff --git a/components/mbedtls/port/aes/dma/esp_aes.c b/components/mbedtls/port/aes/dma/esp_aes.c index 2b0e8b3fda7..693586813b7 100644 --- a/components/mbedtls/port/aes/dma/esp_aes.c +++ b/components/mbedtls/port/aes/dma/esp_aes.c @@ -177,24 +177,31 @@ static IRAM_ATTR void esp_aes_complete_isr(void *arg) } } -static esp_err_t esp_aes_isr_initialise( void ) +void esp_aes_intr_alloc(void) { - aes_hal_interrupt_clear(); - aes_hal_interrupt_enable(true); if (op_complete_sem == NULL) { - op_complete_sem = xSemaphoreCreateBinary(); - - if (op_complete_sem == NULL) { - ESP_LOGE(TAG, "Failed to create intr semaphore"); - return ESP_FAIL; - } const int isr_flags = esp_intr_level_to_flags(CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL); esp_err_t ret = esp_intr_alloc(ETS_AES_INTR_SOURCE, isr_flags, esp_aes_complete_isr, NULL, NULL); if (ret != ESP_OK) { - return ret; + ESP_LOGE(TAG, "Failed to allocate AES interrupt %d", ret); + // This should be treated as fatal error as this API would mostly + // be invoked within mbedTLS interface. There is no way for the system + // to proceed if the AES interrupt allocation fails here. + abort(); } + + static StaticSemaphore_t op_sem_buf; + op_complete_sem = xSemaphoreCreateBinaryStatic(&op_sem_buf); + // Static semaphore creation is unlikley to fail but still basic sanity + assert(op_complete_sem != NULL); } +} + +static esp_err_t esp_aes_isr_initialise( void ) +{ + aes_hal_interrupt_clear(); + aes_hal_interrupt_enable(true); /* AES is clocked proportionally to CPU clock, take power management lock */ #ifdef CONFIG_PM_ENABLE @@ -433,7 +440,7 @@ static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, /* Only use interrupt for long AES operations */ if (len > AES_DMA_INTR_TRIG_LEN) { use_intr = true; - if (esp_aes_isr_initialise() == ESP_FAIL) { + if (esp_aes_isr_initialise() != ESP_OK) { ESP_LOGE(TAG, "ESP-AES ISR initialisation failed"); ret = -1; goto cleanup; @@ -576,7 +583,7 @@ int esp_aes_process_dma_gcm(esp_aes_context *ctx, const unsigned char *input, un /* Only use interrupt for long AES operations */ if (len > AES_DMA_INTR_TRIG_LEN) { use_intr = true; - if (esp_aes_isr_initialise() == ESP_FAIL) { + if (esp_aes_isr_initialise() != ESP_OK) { ESP_LOGE(TAG, "ESP-AES ISR initialisation failed"); ret = -1; goto cleanup; diff --git a/components/mbedtls/port/aes/dma/include/esp_aes_dma_priv.h b/components/mbedtls/port/aes/dma/include/esp_aes_dma_priv.h index 7880f188063..d8ddac8d288 100644 --- a/components/mbedtls/port/aes/dma/include/esp_aes_dma_priv.h +++ b/components/mbedtls/port/aes/dma/include/esp_aes_dma_priv.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -43,6 +35,11 @@ esp_err_t esp_aes_dma_start(const lldesc_t *input, const lldesc_t *output); */ bool esp_aes_dma_done(const lldesc_t *output); +/** + * @brief Allocate AES peripheral interrupt handler + */ +void esp_aes_intr_alloc(void); + #ifdef __cplusplus } #endif diff --git a/components/mbedtls/port/aes/esp_aes_common.c b/components/mbedtls/port/aes/esp_aes_common.c index 5af90a80030..578ec6656c1 100644 --- a/components/mbedtls/port/aes/esp_aes_common.c +++ b/components/mbedtls/port/aes/esp_aes_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: Apache-2.0 * - * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2016-2023 Espressif Systems (Shanghai) CO LTD */ /* * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. @@ -14,6 +14,7 @@ * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ +#include "sdkconfig.h" #include "aes/esp_aes_internal.h" #include "mbedtls/aes.h" #include "hal/aes_hal.h" @@ -24,7 +25,7 @@ #include #include "mbedtls/platform.h" -#if SOC_AES_GDMA +#if SOC_AES_SUPPORT_DMA #include "esp_aes_dma_priv.h" #endif @@ -39,10 +40,12 @@ bool valid_key_length(const esp_aes_context *ctx) return valid_len; } - -void esp_aes_init( esp_aes_context *ctx ) +void esp_aes_init(esp_aes_context *ctx) { - bzero( ctx, sizeof( esp_aes_context ) ); + bzero(ctx, sizeof(esp_aes_context)); +#if SOC_AES_SUPPORT_DMA && CONFIG_MBEDTLS_AES_USE_INTERRUPT + esp_aes_intr_alloc(); +#endif } void esp_aes_free( esp_aes_context *ctx ) diff --git a/components/mbedtls/port/aes/esp_aes_gcm.c b/components/mbedtls/port/aes/esp_aes_gcm.c index 80a3871146c..c91b4fdce1c 100644 --- a/components/mbedtls/port/aes/esp_aes_gcm.c +++ b/components/mbedtls/port/aes/esp_aes_gcm.c @@ -14,22 +14,27 @@ * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ -#include "soc/soc_caps.h" - +#include #include "aes/esp_aes.h" #include "aes/esp_aes_gcm.h" #include "aes/esp_aes_internal.h" #include "hal/aes_hal.h" -#include "esp_log.h" #include "mbedtls/aes.h" +#include "mbedtls/error.h" #include "mbedtls/gcm.h" + #include "esp_heap_caps.h" +#include "esp_log.h" +#include "soc/soc_caps.h" #include "soc/soc_memory_layout.h" -#include "mbedtls/error.h" -#include +#include "sdkconfig.h" + +#if SOC_AES_SUPPORT_DMA +#include "esp_aes_dma_priv.h" +#endif #define ESP_PUT_BE64(a, val) \ do { \ @@ -314,6 +319,10 @@ void esp_aes_gcm_init( esp_gcm_context *ctx) bzero(ctx, sizeof(esp_gcm_context)); +#if SOC_AES_SUPPORT_DMA && CONFIG_MBEDTLS_AES_USE_INTERRUPT + esp_aes_intr_alloc(); +#endif + ctx->gcm_state = ESP_AES_GCM_STATE_INIT; } diff --git a/components/mbedtls/port/bignum/esp_bignum.c b/components/mbedtls/port/bignum/esp_bignum.c index 1611f88e126..bda0baf8c0e 100644 --- a/components/mbedtls/port/bignum/esp_bignum.c +++ b/components/mbedtls/port/bignum/esp_bignum.c @@ -78,8 +78,8 @@ static esp_err_t esp_mpi_isr_initialise(void) mpi_hal_clear_interrupt(); mpi_hal_interrupt_enable(true); if (op_complete_sem == NULL) { - op_complete_sem = xSemaphoreCreateBinary(); - + static StaticSemaphore_t op_sem_buf; + op_complete_sem = xSemaphoreCreateBinaryStatic(&op_sem_buf); if (op_complete_sem == NULL) { ESP_LOGE(TAG, "Failed to create intr semaphore"); return ESP_FAIL; @@ -87,7 +87,16 @@ static esp_err_t esp_mpi_isr_initialise(void) const int isr_flags = esp_intr_level_to_flags(CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL); - esp_intr_alloc(ETS_RSA_INTR_SOURCE, isr_flags, esp_mpi_complete_isr, NULL, NULL); + esp_err_t ret; + ret = esp_intr_alloc(ETS_RSA_INTR_SOURCE, isr_flags, esp_mpi_complete_isr, NULL, NULL); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to allocate RSA interrupt %d", ret); + + // This should be treated as fatal error as this API would mostly + // be invoked within mbedTLS interface. There is no way for the system + // to proceed if the MPI interrupt allocation fails here. + abort(); + } } /* MPI is clocked proportionally to CPU clock, take power management lock */ @@ -400,7 +409,7 @@ static int esp_mpi_exp_mod( mbedtls_mpi *Z, const mbedtls_mpi *X, const mbedtls_ esp_mpi_enable_hardware_hw_op(); #if defined (CONFIG_MBEDTLS_MPI_USE_INTERRUPT) - if (esp_mpi_isr_initialise() == ESP_FAIL) { + if (esp_mpi_isr_initialise() != ESP_OK) { ret = -1; esp_mpi_disable_hardware_hw_op(); goto cleanup; diff --git a/components/mbedtls/port/ecdsa/ecdsa_alt.c b/components/mbedtls/port/ecdsa/ecdsa_alt.c index a4bef4dd5e3..c0fc7c793bc 100644 --- a/components/mbedtls/port/ecdsa/ecdsa_alt.c +++ b/components/mbedtls/port/ecdsa/ecdsa_alt.c @@ -244,13 +244,12 @@ static int esp_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi* r, mbedtls_mpi* s ecdsa_hal_config_t conf = { .mode = ECDSA_MODE_SIGN_GEN, .curve = curve, - .k_mode = ECDSA_K_USE_TRNG, .sha_mode = ECDSA_Z_USER_PROVIDED, .efuse_key_blk = d->MBEDTLS_PRIVATE(n), .use_km_key = 0, //TODO: IDF-7992 }; - ecdsa_hal_gen_signature(&conf, NULL, sha_le, r_le, s_le, len); + ecdsa_hal_gen_signature(&conf, sha_le, r_le, s_le, len); } while (!memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len)); esp_ecdsa_release_hardware(); @@ -470,7 +469,6 @@ static int esp_ecdsa_verify(mbedtls_ecp_group *grp, ecdsa_hal_config_t conf = { .mode = ECDSA_MODE_SIGN_VERIFY, .curve = curve, - .k_mode = ECDSA_K_USE_TRNG, .sha_mode = ECDSA_Z_USER_PROVIDED, }; diff --git a/components/mbedtls/port/esp_platform_time.c b/components/mbedtls/port/esp_platform_time.c index 541b664ab9b..1b30774b835 100644 --- a/components/mbedtls/port/esp_platform_time.c +++ b/components/mbedtls/port/esp_platform_time.c @@ -8,7 +8,7 @@ #include "mbedtls/platform_time.h" #ifdef MBEDTLS_PLATFORM_MS_TIME_ALT -mbedtls_ms_time_t mbedtls_ms_time() +mbedtls_ms_time_t mbedtls_ms_time(void) { int ret; struct timespec tv = {}; diff --git a/components/mbedtls/port/include/ecdsa/ecdsa_alt.h b/components/mbedtls/port/include/ecdsa/ecdsa_alt.h index 3e27b21551a..a8646979a75 100644 --- a/components/mbedtls/port/include/ecdsa/ecdsa_alt.h +++ b/components/mbedtls/port/include/ecdsa/ecdsa_alt.h @@ -24,14 +24,14 @@ extern "C" { * by the peripheral, a flag load_pubkey that is used specify if the public key has to be populated */ typedef struct { - mbedtls_ecp_group_id grp_id; - uint8_t efuse_block; + mbedtls_ecp_group_id grp_id; /*!< MbedTLS ECP group identifier */ + uint8_t efuse_block; /*!< EFuse block id for ECDSA private key */ #ifdef SOC_ECDSA_SUPPORT_EXPORT_PUBKEY - bool load_pubkey; + bool load_pubkey; /*!< Export ECDSA public key from the hardware */ #endif } esp_ecdsa_pk_conf_t; //TODO: IDF-7925 (Add a config to select the ecdsa key from the key manager peripheral) -#ifdef SOC_ECDSA_SUPPORT_EXPORT_PUBKEY +#if SOC_ECDSA_SUPPORT_EXPORT_PUBKEY || __DOXYGEN__ /** * @brief Populate the public key buffer of the mbedtls_ecp_keypair context. @@ -45,9 +45,10 @@ typedef struct { * - -1 if invalid efuse block is specified */ int esp_ecdsa_load_pubkey(mbedtls_ecp_keypair *keypair, int efuse_blk); -#endif -#ifdef CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN +#endif // SOC_ECDSA_SUPPORT_EXPORT_PUBKEY || __DOXYGEN__ + +#if CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN || __DOXYGEN__ /** * @brief Initialize MPI to notify mbedtls_ecdsa_sign to use the private key in efuse @@ -97,7 +98,8 @@ int esp_ecdsa_privkey_load_pk_context(mbedtls_pk_context *key_ctx, int efuse_blk * - -1 otherwise */ int esp_ecdsa_set_pk_context(mbedtls_pk_context *key_ctx, esp_ecdsa_pk_conf_t *conf); -#endif + +#endif // CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN || __DOXYGEN__ #ifdef __cplusplus } diff --git a/components/mbedtls/test_apps/main/app_main.c b/components/mbedtls/test_apps/main/app_main.c index 0716defabf3..27735fb98d9 100644 --- a/components/mbedtls/test_apps/main/app_main.c +++ b/components/mbedtls/test_apps/main/app_main.c @@ -1,16 +1,25 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "unity.h" +#include "mbedtls/aes.h" #include "memory_checks.h" +#include "soc/soc_caps.h" /* setUp runs before every test */ void setUp(void) { + // Execute mbedtls_aes_init operation to allocate AES interrupt + // allocation memory which is considered as leak otherwise +#if SOC_AES_SUPPORTED + mbedtls_aes_context ctx; + mbedtls_aes_init(&ctx); +#endif // SOC_AES_SUPPORTED + test_utils_record_free_mem(); test_utils_set_leak_level(CONFIG_UNITY_CRITICAL_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL); test_utils_set_leak_level(CONFIG_UNITY_WARN_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_GENERAL); diff --git a/components/mbedtls/test_apps/main/test_aes_sha_rsa.c b/components/mbedtls/test_apps/main/test_aes_sha_rsa.c index 497180fba1f..650d7b78820 100644 --- a/components/mbedtls/test_apps/main/test_aes_sha_rsa.c +++ b/components/mbedtls/test_apps/main/test_aes_sha_rsa.c @@ -14,7 +14,6 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" -#include "freertos/xtensa_timer.h" #include "unity.h" #include "test_utils.h" #include "esp32/rom/sha.h" diff --git a/components/newlib/CMakeLists.txt b/components/newlib/CMakeLists.txt index 9f30c6db68f..a74220bb7b5 100644 --- a/components/newlib/CMakeLists.txt +++ b/components/newlib/CMakeLists.txt @@ -55,6 +55,9 @@ list(APPEND EXTRA_LINK_FLAGS "-u newlib_include_pthread_impl") list(APPEND EXTRA_LINK_FLAGS "-u newlib_include_assert_impl") target_link_libraries(${COMPONENT_LIB} INTERFACE "${EXTRA_LINK_FLAGS}") +# Forces the linker to include newlib_init.c +target_link_libraries(${COMPONENT_LIB} INTERFACE "-u newlib_include_init_funcs") + if(CONFIG_NEWLIB_NANO_FORMAT) if(CMAKE_C_COMPILER_ID MATCHES "Clang") set(libc_dir_cmd ${CMAKE_C_COMPILER}) diff --git a/components/newlib/newlib_init.c b/components/newlib/newlib_init.c index 2c9b798c741..8072665a8a9 100644 --- a/components/newlib/newlib_init.c +++ b/components/newlib/newlib_init.c @@ -20,6 +20,7 @@ #include "esp_attr.h" #include "soc/soc_caps.h" #include "esp_rom_caps.h" +#include "esp_private/startup_internal.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/libc_stubs.h" @@ -176,8 +177,22 @@ void esp_newlib_init(void) esp_newlib_locks_init(); } +ESP_SYSTEM_INIT_FN(init_newlib, CORE, BIT(0), 102) +{ + esp_newlib_init(); + return ESP_OK; +} + void esp_setup_newlib_syscalls(void) __attribute__((alias("esp_newlib_init"))); +/** + * Postponed _GLOBAL_REENT stdio FPs initialization. + * + * Can not be a part of esp_reent_init() because stdio device may not initialized yet. + * + * Called from startup code and FreeRTOS, not intended to be called from + * application code. + */ void esp_newlib_init_global_stdio(const char *stdio_dev) { if (stdio_dev == NULL) @@ -207,3 +222,18 @@ void esp_newlib_init_global_stdio(const char *stdio_dev) #endif /* ESP_ROM_NEEDS_SWSETUP_WORKAROUND */ } } + +ESP_SYSTEM_INIT_FN(init_newlib_stdio, CORE, BIT(0), 115) +{ +#if defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE) + esp_newlib_init_global_stdio("/dev/console"); +#else + esp_newlib_init_global_stdio(NULL); +#endif + return ESP_OK; +} + +// Hook to force the linker to include this file +void newlib_include_init_funcs(void) +{ +} diff --git a/components/newlib/platform_include/sys/lock.h b/components/newlib/platform_include/sys/lock.h index 7299c401142..a7fa41ed857 100644 --- a/components/newlib/platform_include/sys/lock.h +++ b/components/newlib/platform_include/sys/lock.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include_next +#include "sdkconfig.h" #ifdef _RETARGETABLE_LOCKING @@ -13,15 +14,19 @@ * The size here should be sufficient for a FreeRTOS mutex. * This is checked by a static assertion in locks.c * - * Note 1: this might need to be made dependent on whether FreeRTOS + * Note: this might need to be made dependent on whether FreeRTOS * is included in the build. - * - * Note 2: the size is made sufficient for the case when - * configUSE_TRACE_FACILITY is enabled. If it is disabled, - * this definition wastes 8 bytes. */ struct __lock { +#if (CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES && CONFIG_FREERTOS_USE_TRACE_FACILITY) + int reserved[29]; +#elif (CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES && !CONFIG_FREERTOS_USE_TRACE_FACILITY) + int reserved[27]; +#elif (!CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES && CONFIG_FREERTOS_USE_TRACE_FACILITY) int reserved[23]; +#else + int reserved[21]; +#endif /* #if (CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES && CONFIG_FREERTOS_USE_TRACE_FACILITY) */ }; /* Compatibility definitions for the legacy ESP-specific locking implementation. diff --git a/components/newlib/test_apps/newlib/main/CMakeLists.txt b/components/newlib/test_apps/newlib/main/CMakeLists.txt index f59798a87a5..afd52fc0473 100644 --- a/components/newlib/test_apps/newlib/main/CMakeLists.txt +++ b/components/newlib/test_apps/newlib/main/CMakeLists.txt @@ -6,7 +6,6 @@ idf_component_register(SRCS "test_misc.c" "test_newlib.c" "test_setjmp.c" - "test_shared_stack_printf.c" "test_stdatomic.c" "test_time.c" PRIV_REQUIRES unity vfs cmock driver esp_timer spi_flash test_utils pthread esp_psram diff --git a/components/newlib/test_apps/newlib/main/test_newlib.c b/components/newlib/test_apps/newlib/main/test_newlib.c index 741af5c34c5..8cb32840c09 100644 --- a/components/newlib/test_apps/newlib/main/test_newlib.c +++ b/components/newlib/test_apps/newlib/main/test_newlib.c @@ -32,10 +32,10 @@ TEST_CASE("test atoX functions", "[newlib]") TEST_ASSERT_EQUAL_INT(2147483647, atoi("2147483647")); TEST_ASSERT_EQUAL_INT(42, atoi("000000042")); TEST_ASSERT_EQUAL_INT(0, strtol("foo", NULL, 10)); - TEST_ASSERT_EQUAL(0.123443, atof("0.123443")); - TEST_ASSERT_EQUAL(0.123443f, atoff("0.123443")); - TEST_ASSERT_EQUAL(31.41238, strtod("0.3141238e2", NULL)); - TEST_ASSERT_EQUAL(0.025f, strtof("0.025", NULL)); + TEST_ASSERT_EQUAL_DOUBLE(0.123443, atof("0.123443")); + TEST_ASSERT_EQUAL_FLOAT(0.123443f, atoff("0.123443")); + TEST_ASSERT_EQUAL_DOUBLE(31.41238, strtod("0.3141238e2", NULL)); + TEST_ASSERT_EQUAL_FLOAT(0.025f, strtof("0.025", NULL)); } TEST_CASE("test sprintf function", "[newlib]") diff --git a/components/newlib/test_apps/newlib/main/test_stdatomic.c b/components/newlib/test_apps/newlib/main/test_stdatomic.c index b41d36ac5c8..602dc45c038 100644 --- a/components/newlib/test_apps/newlib/main/test_stdatomic.c +++ b/components/newlib/test_apps/newlib/main/test_stdatomic.c @@ -218,104 +218,139 @@ TEST_EXCLUSION(8) #define ITER_COUNT 20000 -#define TEST_RACE_OPERATION(NAME, LHSTYPE, PRE, POST, INIT, FINAL) \ - \ -static _Atomic LHSTYPE var_##NAME = (INIT); \ - \ -static void *test_thread_##NAME (void *arg) \ -{ \ - for (int i = 0; i < ITER_COUNT; i++) \ - { \ - PRE var_##NAME POST; \ - } \ - return NULL; \ -} \ - \ -TEST_CASE("stdatomic - test_" #NAME, "[newlib_stdatomic]") \ -{ \ - pthread_t thread_id1; \ - pthread_t thread_id2; \ - esp_pthread_cfg_t cfg = esp_pthread_get_default_config(); \ - cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS; \ - esp_pthread_set_cfg(&cfg); \ - pthread_create (&thread_id1, NULL, test_thread_##NAME, NULL); \ - cfg.pin_to_core = xPortGetCoreID(); \ - esp_pthread_set_cfg(&cfg); \ - pthread_create (&thread_id2, NULL, test_thread_##NAME, NULL); \ - pthread_join (thread_id1, NULL); \ - pthread_join (thread_id2, NULL); \ - TEST_ASSERT_EQUAL((FINAL), var_##NAME); \ +#define TEST_RACE_OPERATION(ASSERT_SUFFIX, NAME, LHSTYPE, PRE, POST, INIT, FINAL) \ + \ +static _Atomic LHSTYPE var_##NAME; \ + \ +static void *test_thread_##NAME (void *arg) \ +{ \ + for (int i = 0; i < ITER_COUNT; i++) \ + { \ + PRE var_##NAME POST; \ + } \ + return NULL; \ +} \ + \ +TEST_CASE("stdatomic - test_" #NAME, "[newlib_stdatomic]") \ +{ \ + pthread_t thread_id1; \ + pthread_t thread_id2; \ + var_##NAME = (INIT); \ + esp_pthread_cfg_t cfg = esp_pthread_get_default_config(); \ + cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS; \ + esp_pthread_set_cfg(&cfg); \ + pthread_create (&thread_id1, NULL, test_thread_##NAME, NULL); \ + cfg.pin_to_core = xPortGetCoreID(); \ + esp_pthread_set_cfg(&cfg); \ + pthread_create (&thread_id2, NULL, test_thread_##NAME, NULL); \ + pthread_join (thread_id1, NULL); \ + pthread_join (thread_id2, NULL); \ + TEST_ASSERT_EQUAL##ASSERT_SUFFIX((FINAL), var_##NAME); \ +} + +// Note that the assert at the end is doing an excat bitwise comparison. +// This easily can fail due to rounding errors. However, there is currently +// no corresponding Unity assert macro for long double. USE THIS WITH CARE! +#define TEST_RACE_OPERATION_LONG_DOUBLE(NAME, LHSTYPE, PRE, POST, INIT, FINAL) \ + \ +static _Atomic LHSTYPE var_##NAME; \ + \ +static void *test_thread_##NAME (void *arg) \ +{ \ + for (int i = 0; i < ITER_COUNT; i++) \ + { \ + PRE var_##NAME POST; \ + } \ + return NULL; \ +} \ + \ +TEST_CASE("stdatomic - test_" #NAME, "[newlib_stdatomic]") \ +{ \ + pthread_t thread_id1; \ + pthread_t thread_id2; \ + var_##NAME = (INIT); \ + const LHSTYPE EXPECTED = (FINAL); \ + esp_pthread_cfg_t cfg = esp_pthread_get_default_config(); \ + cfg.pin_to_core = (xPortGetCoreID() + 1) % portNUM_PROCESSORS; \ + esp_pthread_set_cfg(&cfg); \ + pthread_create (&thread_id1, NULL, test_thread_##NAME, NULL); \ + cfg.pin_to_core = xPortGetCoreID(); \ + esp_pthread_set_cfg(&cfg); \ + pthread_create (&thread_id2, NULL, test_thread_##NAME, NULL); \ + pthread_join (thread_id1, NULL); \ + pthread_join (thread_id2, NULL); \ + TEST_ASSERT(EXPECTED == var_##NAME); \ } -TEST_RACE_OPERATION (uint8_add, uint8_t, , += 1, 0, (uint8_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_add_3, uint8_t, , += 3, 0, (uint8_t) (6*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_postinc, uint8_t, , ++, 0, (uint8_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_preinc, uint8_t, ++, , 0, (uint8_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_sub, uint8_t, , -= 1, 0, (uint8_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_sub_3, uint8_t, , -= 3, 0, (uint8_t) -(6*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_postdec, uint8_t, , --, 0, (uint8_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_predec, uint8_t, --, , 0, (uint8_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint8_mul, uint8_t, , *= 3, 1, (uint8_t) 0x1) - -TEST_RACE_OPERATION (uint16_add, uint16_t, , += 1, 0, (uint16_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_add_3, uint16_t, , += 3, 0, (uint16_t) (6*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_postinc, uint16_t, , ++, 0, (uint16_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_preinc, uint16_t, ++, , 0, (uint16_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_sub, uint16_t, , -= 1, 0, (uint16_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_sub_3, uint16_t, , -= 3, 0, (uint16_t) -(6*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_postdec, uint16_t, , --, 0, (uint16_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_predec, uint16_t, --, , 0, (uint16_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint16_mul, uint16_t, , *= 3, 1, (uint16_t) 0x6D01) - -TEST_RACE_OPERATION (uint32_add, uint32_t, , += 1, 0, (uint32_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_add_3, uint32_t, , += 3, 0, (uint32_t) (6*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_postinc, uint32_t, , ++, 0, (uint32_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_preinc, uint32_t, ++, , 0, (uint32_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_sub, uint32_t, , -= 1, 0, (uint32_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_sub_3, uint32_t, , -= 3, 0, (uint32_t) -(6*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_postdec, uint32_t, , --, 0, (uint32_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_predec, uint32_t, --, , 0, (uint32_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint32_mul, uint32_t, , *= 3, 1, (uint32_t) 0xC1E36D01U) - -TEST_RACE_OPERATION (uint64_add, uint64_t, , += 1, 0, (uint64_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_add_3, uint64_t, , += 3, 0, (uint64_t) (6*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_add_neg, uint64_t, , += 1, -10000, (uint64_t) (2*ITER_COUNT-10000)) -TEST_RACE_OPERATION (uint64_postinc, uint64_t, , ++, 0, (uint64_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_postinc_neg, uint64_t, , ++, -10000, (uint64_t) (2*ITER_COUNT-10000)) -TEST_RACE_OPERATION (uint64_preinc, uint64_t, ++, , 0, (uint64_t) (2*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_preinc_neg, uint64_t, ++, , -10000, (uint64_t) (2*ITER_COUNT-10000)) -TEST_RACE_OPERATION (uint64_sub, uint64_t, , -= 1, 0, (uint64_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_sub_3, uint64_t, , -= 3, 0, (uint64_t) -(6*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_sub_neg, uint64_t, , -= 1, 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) -TEST_RACE_OPERATION (uint64_postdec, uint64_t, , --, 0, (uint64_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_postdec_neg, uint64_t, , --, 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) -TEST_RACE_OPERATION (uint64_predec, uint64_t, --, , 0, (uint64_t) -(2*ITER_COUNT)) -TEST_RACE_OPERATION (uint64_predec_neg, uint64_t, --, , 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) -TEST_RACE_OPERATION (uint64_mul, uint64_t, , *= 3, 1, (uint64_t) 0x988EE974C1E36D01ULL) - -TEST_RACE_OPERATION (float_add, float, , += 1, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (complex_float_add, _Complex float, , += 1, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (float_postinc, float, , ++, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (float_preinc, float, ++, , 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (float_sub, float, , -= 1, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (complex_float_sub, _Complex float, , -= 1, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (float_postdec, float, , --, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (float_predec, float, --, , 0, -(2*ITER_COUNT)) - -TEST_RACE_OPERATION (double_add, double, , += 1, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (complex_double_add, _Complex double, , += 1, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (double_postinc, double, , ++, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (double_preinc, double, ++, , 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (double_sub, double, , -= 1, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (complex_double_sub, _Complex double, , -= 1, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (double_postdec, double, , --, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (double_predec, double, --, , 0, -(2*ITER_COUNT)) - -TEST_RACE_OPERATION (long_double_add, long double, , += 1, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (complex_long_double_add, _Complex long double, , += 1, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (long_double_postinc, long double, , ++, 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (long_double_sub, long double, , -= 1, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (long_double_preinc, long double, ++, , 0, (2*ITER_COUNT)) -TEST_RACE_OPERATION (complex_long_double_sub, _Complex long double, , -= 1, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (long_double_postdec, long double, , --, 0, -(2*ITER_COUNT)) -TEST_RACE_OPERATION (long_double_predec, long double, --, , 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_add, uint8_t, , += 1, 0, (uint8_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_add_3, uint8_t, , += 3, 0, (uint8_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_postinc, uint8_t, , ++, 0, (uint8_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_preinc, uint8_t, ++, , 0, (uint8_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_sub, uint8_t, , -= 1, 0, (uint8_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_sub_3, uint8_t, , -= 3, 0, (uint8_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_postdec, uint8_t, , --, 0, (uint8_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_predec, uint8_t, --, , 0, (uint8_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint8_mul, uint8_t, , *= 3, 1, (uint8_t) 0x1) + +TEST_RACE_OPERATION ( ,uint16_add, uint16_t, , += 1, 0, (uint16_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_add_3, uint16_t, , += 3, 0, (uint16_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_postinc, uint16_t, , ++, 0, (uint16_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_preinc, uint16_t, ++, , 0, (uint16_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_sub, uint16_t, , -= 1, 0, (uint16_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_sub_3, uint16_t, , -= 3, 0, (uint16_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_postdec, uint16_t, , --, 0, (uint16_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_predec, uint16_t, --, , 0, (uint16_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint16_mul, uint16_t, , *= 3, 1, (uint16_t) 0x6D01) + +TEST_RACE_OPERATION ( ,uint32_add, uint32_t, , += 1, 0, (uint32_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_add_3, uint32_t, , += 3, 0, (uint32_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_postinc, uint32_t, , ++, 0, (uint32_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_preinc, uint32_t, ++, , 0, (uint32_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_sub, uint32_t, , -= 1, 0, (uint32_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_sub_3, uint32_t, , -= 3, 0, (uint32_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_postdec, uint32_t, , --, 0, (uint32_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_predec, uint32_t, --, , 0, (uint32_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint32_mul, uint32_t, , *= 3, 1, (uint32_t) 0xC1E36D01U) + +TEST_RACE_OPERATION ( ,uint64_add, uint64_t, , += 1, 0, (uint64_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_add_3, uint64_t, , += 3, 0, (uint64_t) (6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_add_neg, uint64_t, , += 1, -10000, (uint64_t) (2*ITER_COUNT-10000)) +TEST_RACE_OPERATION ( ,uint64_postinc, uint64_t, , ++, 0, (uint64_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_postinc_neg, uint64_t, , ++, -10000, (uint64_t) (2*ITER_COUNT-10000)) +TEST_RACE_OPERATION ( ,uint64_preinc, uint64_t, ++, , 0, (uint64_t) (2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_preinc_neg, uint64_t, ++, , -10000, (uint64_t) (2*ITER_COUNT-10000)) +TEST_RACE_OPERATION ( ,uint64_sub, uint64_t, , -= 1, 0, (uint64_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_sub_3, uint64_t, , -= 3, 0, (uint64_t) -(6*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_sub_neg, uint64_t, , -= 1, 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) +TEST_RACE_OPERATION ( ,uint64_postdec, uint64_t, , --, 0, (uint64_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_postdec_neg, uint64_t, , --, 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) +TEST_RACE_OPERATION ( ,uint64_predec, uint64_t, --, , 0, (uint64_t) -(2*ITER_COUNT)) +TEST_RACE_OPERATION ( ,uint64_predec_neg, uint64_t, --, , 10000, (uint64_t) ((-2*ITER_COUNT)+10000)) +TEST_RACE_OPERATION ( ,uint64_mul, uint64_t, , *= 3, 1, (uint64_t) 0x988EE974C1E36D01ULL) + +TEST_RACE_OPERATION (_FLOAT ,float_add, float, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,complex_float_add, _Complex float, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,float_postinc, float, , ++, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,float_preinc, float, ++, , 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,float_sub, float, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,complex_float_sub, _Complex float, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,float_postdec, float, , --, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (_FLOAT ,float_predec, float, --, , 0, -(2*ITER_COUNT)) + +TEST_RACE_OPERATION (_DOUBLE ,double_add, double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,complex_double_add, _Complex double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,double_postinc, double, , ++, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,double_preinc, double, ++, , 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,double_sub, double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,complex_double_sub, _Complex double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,double_postdec, double, , --, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION (_DOUBLE ,double_predec, double, --, , 0, -(2*ITER_COUNT)) + +TEST_RACE_OPERATION_LONG_DOUBLE (long_double_add, long double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (complex_long_double_add, _Complex long double, , += 1, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (long_double_postinc, long double, , ++, 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (long_double_sub, long double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (long_double_preinc, long double, ++, , 0, (2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (complex_long_double_sub, _Complex long double, , -= 1, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (long_double_postdec, long double, , --, 0, -(2*ITER_COUNT)) +TEST_RACE_OPERATION_LONG_DOUBLE (long_double_predec, long double, --, , 0, -(2*ITER_COUNT)) diff --git a/components/nvs_flash/host_test/nvs_host_test/CMakeLists.txt b/components/nvs_flash/host_test/nvs_host_test/CMakeLists.txt index cd3f3ebece4..658d311f49f 100644 --- a/components/nvs_flash/host_test/nvs_host_test/CMakeLists.txt +++ b/components/nvs_flash/host_test/nvs_host_test/CMakeLists.txt @@ -2,9 +2,7 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -# Freertos is included via common components. However, CATCH isn't compatible with the FreeRTOS component yet, hence -# using the FreeRTOS mock component. -# target. +# This test app doesn't require FreeRTOS, using mock instead list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") project(nvs_host_test) diff --git a/components/nvs_flash/host_test/nvs_host_test/main/CMakeLists.txt b/components/nvs_flash/host_test/nvs_host_test/main/CMakeLists.txt index 508bfa0e17d..534f968c532 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/CMakeLists.txt +++ b/components/nvs_flash/host_test/nvs_host_test/main/CMakeLists.txt @@ -1,5 +1,4 @@ -idf_component_register(SRCS "main.cpp" - "test_nvs.cpp" +idf_component_register(SRCS "test_nvs.cpp" "test_partition_manager.cpp" "test_nvs_cxx_api.cpp" "test_nvs_handle.cpp" @@ -9,10 +8,13 @@ idf_component_register(SRCS "main.cpp" "../../../src" "../../../private_include" "../../../../mbedtls/mbedtls/include" - "../../../../../tools/catch" WHOLE_ARCHIVE REQUIRES nvs_flash) if(CMAKE_C_COMPILER_ID MATCHES "Clang") target_compile_options(${COMPONENT_LIB} PRIVATE -std=gnu++20) endif() + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/nvs_flash/host_test/nvs_host_test/main/idf_component.yml b/components/nvs_flash/host_test/nvs_host_test/main/idf_component.yml new file mode 100644 index 00000000000..f7982136b97 --- /dev/null +++ b/components/nvs_flash/host_test/nvs_host_test/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/catch2: "^3.4.0" diff --git a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs.cpp b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs.cpp index 44a9f44a9cf..bf1b66a3f6f 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs.cpp +++ b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs.cpp @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "catch.hpp" +#include #include "nvs.hpp" #include "sdkconfig.h" #include "nvs_partition_manager.hpp" @@ -383,7 +383,6 @@ TEST_CASE("storage can find items on second page if first is not fully written a PartitionEmulationFixture f(0, 3); nvs::Storage storage(f.part()); TEST_ESP_OK(storage.init(0, 3)); - int bar = 0; uint8_t bigdata[(nvs::Page::CHUNK_MAX_SIZE - nvs::Page::ENTRY_SIZE) / 2] = {0}; // write one big chunk of data ESP_ERROR_CHECK(storage.writeItem(0, nvs::ItemType::BLOB, "1", bigdata, sizeof(bigdata))); @@ -635,8 +634,6 @@ TEST_CASE("deinit partition doesn't affect other partition's open handles", "[nv const char *OTHER_PARTITION_NAME = "other_part"; PartitionEmulationFixture f(0, 10); PartitionEmulationFixture f_other(0, 10, OTHER_PARTITION_NAME); - const char *str = "value 0123456789abcdef0123456789abcdef"; - const uint8_t blob[8] = {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7}; nvs_handle_t handle_1; const uint32_t NVS_FLASH_SECTOR = 6; @@ -696,7 +693,6 @@ TEST_CASE("nvs_entry_info fails with ESP_ERR_INVALID_ARG if a parameter is NULL" TEST_CASE("nvs_entry_info doesn't change iterator on parameter error", "[nvs]") { nvs_iterator_t it = reinterpret_cast(0xbeef); - nvs_entry_info_t info; REQUIRE(nvs_entry_info(it, nullptr) == ESP_ERR_INVALID_ARG); CHECK(it == reinterpret_cast(0xbeef)); @@ -1001,8 +997,8 @@ TEST_CASE("wifi test", "[nvs]") TEST_ESP_OK(nvs_set_u8(net80211_handle, "wifi.opmode", opmode)); uint8_t country = 0; - TEST_ESP_ERR(nvs_get_u8(net80211_handle, "wifi.country", &opmode), ESP_ERR_NVS_NOT_FOUND); - TEST_ESP_OK(nvs_set_u8(net80211_handle, "wifi.country", opmode)); + TEST_ESP_ERR(nvs_get_u8(net80211_handle, "wifi.country", &country), ESP_ERR_NVS_NOT_FOUND); + TEST_ESP_OK(nvs_set_u8(net80211_handle, "wifi.country", country)); char ssid[36]; size_t size = sizeof(ssid); @@ -1330,7 +1326,6 @@ class RandomTest { case nvs::ItemType::SZ: { char buf[strBufLen]; - size_t len = strBufLen; size_t strLen = gen() % (strBufLen - 1); std::generate_n(buf, strLen, [&]() -> char { @@ -1896,8 +1891,6 @@ TEST_CASE("Check that orphaned blobs are erased during init", "[nvs]") { const size_t blob_size = nvs::Page::CHUNK_MAX_SIZE * 3 ; uint8_t blob[blob_size] = {0x11}; - uint8_t blob2[blob_size] = {0x22}; - uint8_t blob3[blob_size] = {0x33}; PartitionEmulationFixture f(0, 5); nvs::Storage storage(f.part()); @@ -2807,7 +2800,6 @@ static void check_nvs_part_gen_args(char const *flash_binary_filename, // n char buf[64] = {0}; uint8_t hexdata[] = {0x01, 0x02, 0x03, 0xab, 0xcd, 0xef}; size_t buflen = 64; - int j; TEST_ESP_OK( nvs_get_blob(handle, "dummyHex2BinKey", buf, &buflen)); CHECK(memcmp(buf, hexdata, buflen) == 0); @@ -2876,7 +2868,6 @@ static void check_nvs_part_gen_args_mfg(char const *flash_binary_filename, // n uint8_t hexdata[] = {0x01, 0x02, 0x03, 0xab, 0xcd, 0xef}; buflen = 64; - int j; TEST_ESP_OK( nvs_get_blob(handle, "dummyHex2BinKey", buf, &buflen)); CHECK(memcmp(buf, hexdata, buflen) == 0); @@ -3319,7 +3310,92 @@ TEST_CASE("nvs multiple write with same key but different types", "[nvs][xxx]") TEST_ESP_OK(nvs_flash_deinit_partition(NVS_DEFAULT_PART_NAME)); } +TEST_CASE("nvs find key tests", "[nvs]") +{ + const size_t buff_len = 4096; + + PartitionEmulationFixture f(0, 20); + f.randomize(100); + + nvs_handle_t handle_1; + nvs_handle_t handle_2; + + const uint32_t NVS_FLASH_SECTOR = 6; + const uint32_t NVS_FLASH_SECTOR_COUNT_MIN = 13; + + + TEST_ESP_ERR(nvs_open("namespace1", NVS_READWRITE, &handle_1), ESP_ERR_NVS_NOT_INITIALIZED); + for (uint16_t i = NVS_FLASH_SECTOR; i < NVS_FLASH_SECTOR + NVS_FLASH_SECTOR_COUNT_MIN; ++i) { + f.erase(i); + } + TEST_ESP_OK(nvs::NVSPartitionManager::get_instance()->init_custom(f.part(), + NVS_FLASH_SECTOR, + NVS_FLASH_SECTOR_COUNT_MIN)); + + nvs_type_t datatype_found; // datatype of entry found + + // open writeable namespace + TEST_ESP_OK(nvs_open("namespace1", NVS_READWRITE, &handle_1)); + // set value, erease value, test find before and after each of steps + TEST_ESP_ERR(nvs_find_key(handle_1, "foo", &datatype_found), ESP_ERR_NVS_NOT_FOUND); + // write "foo" as I32, should find it, first attempt without pointer to type variable + TEST_ESP_OK(nvs_set_i32(handle_1, "foo", 0x12345678)); + TEST_ESP_OK(nvs_find_key(handle_1, "foo", nullptr)); + // second search attempt with pointer to type variable specified + TEST_ESP_OK(nvs_find_key(handle_1, "foo", &datatype_found)); + CHECK(datatype_found == NVS_TYPE_I32); + TEST_ESP_OK(nvs_erase_key(handle_1, "foo")); + TEST_ESP_ERR(nvs_find_key(handle_1, "foo", &datatype_found), ESP_ERR_NVS_NOT_FOUND); + + // set value, rewrite value, erease value, test find before and after each of steps + TEST_ESP_ERR(nvs_find_key(handle_1, "foo1", &datatype_found), ESP_ERR_NVS_NOT_FOUND); + TEST_ESP_OK(nvs_set_i16(handle_1, "foo1", 0x1234)); + TEST_ESP_OK(nvs_find_key(handle_1, "foo1", &datatype_found)); + CHECK(datatype_found == NVS_TYPE_I16); + TEST_ESP_OK(nvs_set_i16(handle_1, "foo1", 0x4321)); + TEST_ESP_OK(nvs_find_key(handle_1, "foo1", &datatype_found)); + CHECK(datatype_found == NVS_TYPE_I16); + TEST_ESP_OK(nvs_erase_key(handle_1, "foo1")); + TEST_ESP_ERR(nvs_find_key(handle_1, "foo1", &datatype_found), ESP_ERR_NVS_NOT_FOUND); + + // set blob value, rewrite blob, delete blob, test find before and after each of steps + uint8_t *p_buff = (uint8_t *) malloc(buff_len); + CHECK(p_buff != nullptr); + TEST_ESP_ERR(nvs_find_key(handle_1, "foo2", &datatype_found), ESP_ERR_NVS_NOT_FOUND); + for(size_t i=0; i #include #include #include "nvs_handle_simple.hpp" diff --git a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_handle.cpp b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_handle.cpp index 6c6e35e1d11..dae567d4466 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_handle.cpp +++ b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_handle.cpp @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "catch.hpp" +#include #include #include #include "nvs_handle_simple.hpp" diff --git a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_initialization.cpp b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_initialization.cpp index 2482129535d..cd52f19a818 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_initialization.cpp +++ b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_initialization.cpp @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "catch.hpp" +#include #include "nvs.hpp" #include "nvs_partition_manager.hpp" #include "nvs_partition.hpp" @@ -12,8 +12,6 @@ TEST_CASE("nvs_flash_init_partition_ptr fails due to nullptr arg", "[nvs_custom_part]") { - const uint32_t NVS_FLASH_SECTOR = 6; - const uint32_t NVS_FLASH_SECTOR_COUNT_MIN = 3; uint8_t *p_part_desc_addr_start; CHECK(esp_partition_file_mmap((const uint8_t **)&p_part_desc_addr_start) == ESP_OK); diff --git a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_storage.cpp b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_storage.cpp index 7e19ce7d5d5..769c661260a 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_storage.cpp +++ b/components/nvs_flash/host_test/nvs_host_test/main/test_nvs_storage.cpp @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "catch.hpp" +#include #include #include "nvs_storage.hpp" #include "nvs_partition_manager.hpp" diff --git a/components/nvs_flash/host_test/nvs_host_test/main/test_partition_manager.cpp b/components/nvs_flash/host_test/nvs_host_test/main/test_partition_manager.cpp index 04989df2d09..4c995eaeecc 100644 --- a/components/nvs_flash/host_test/nvs_host_test/main/test_partition_manager.cpp +++ b/components/nvs_flash/host_test/nvs_host_test/main/test_partition_manager.cpp @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "catch.hpp" +#include #include #include #include "nvs_handle_simple.hpp" diff --git a/components/nvs_flash/include/nvs.h b/components/nvs_flash/include/nvs.h index 362404e937f..0378457fb32 100644 --- a/components/nvs_flash/include/nvs.h +++ b/components/nvs_flash/include/nvs.h @@ -481,6 +481,25 @@ esp_err_t nvs_get_str (nvs_handle_t handle, const char* key, char* out_value, si esp_err_t nvs_get_blob(nvs_handle_t handle, const char* key, void* out_value, size_t* length); /**@}*/ +/** + * @brief Lookup key-value pair with given key name. + * + * Note that function may indicate both existence of the key as well as the data type of NVS entry if it is found. + * + * @param[in] handle Storage handle obtained with nvs_open. + * @param[in] key Key name. Maximum length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. + * @param[out] out_type Pointer to the output variable populated with data type of NVS entry in case key was found. + * May be NULL, respective data type is then not provided. + * @return + * - ESP_OK if NVS entry for key provided was found + * - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist + * - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL + * - ESP_FAIL if there is an internal error; most likely due to corrupted + * NVS partition (only if NVS assertion checks are disabled) + * - other error codes from the underlying storage driver + */ +esp_err_t nvs_find_key(nvs_handle_t handle, const char* key, nvs_type_t* out_type); + /** * @brief Erase key-value pair with given key name. * diff --git a/components/nvs_flash/include/nvs_handle.hpp b/components/nvs_flash/include/nvs_handle.hpp index 2421e1a8617..97bf25697ac 100644 --- a/components/nvs_flash/include/nvs_handle.hpp +++ b/components/nvs_flash/include/nvs_handle.hpp @@ -164,6 +164,21 @@ class NVSHandle { */ virtual esp_err_t get_item_size(ItemType datatype, const char *key, size_t &size) = 0; + /** + * @brief Checks whether key exists and optionally returns also data type of associated entry. + * + * @param[in] key Key name. Maximum length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. + * @param[out] nvstype Nvs data type to of entry, if it exists. + * + * @return - ESP_OK if NVS entry for key provided was found. Data type will be returned via \c nvstype. + * - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist. + * - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL. + * - ESP_FAIL if there is an internal error; most likely due to corrupted + * NVS partition (only if NVS assertion checks are disabled). + * - other error codes from the underlying storage driver. + */ + virtual esp_err_t find_key(const char* key, nvs_type_t &nvstype) = 0; + /** * @brief Erases an entry. */ diff --git a/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py b/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py index 36739328b73..3bfe6dd952d 100755 --- a/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py +++ b/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py @@ -1,1103 +1,12 @@ #!/usr/bin/env python # -# esp-idf NVS partition generation tool. Tool helps in generating NVS-compatible -# partition binary, with key-value pair entries provided via a CSV file. +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD # -# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # -import argparse -import array -import binascii -import codecs -import csv -import datetime -import distutils.dir_util -import os -import random -import struct +import subprocess import sys -import textwrap -import zlib -from io import open - -try: - from cryptography.hazmat.backends import default_backend - from cryptography.hazmat.primitives import hashes, hmac - from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes -except ImportError: - print('The cryptography package is not installed.' - 'Please refer to the Get Started section of the ESP-IDF Programming Guide for ' - 'setting up the required packages.') - raise - -VERSION1_PRINT = 'V1 - Multipage Blob Support Disabled' -VERSION2_PRINT = 'V2 - Multipage Blob Support Enabled' - - -def reverse_hexbytes(addr_tmp): - addr = [] - reversed_bytes = '' - for i in range(0, len(addr_tmp), 2): - addr.append(addr_tmp[i:i + 2]) - reversed_bytes = ''.join(reversed(addr)) - - return reversed_bytes - - -def desc_format(*args): - desc = '' - for arg in args: - desc += textwrap.fill(replace_whitespace=False, text=arg) + '\n' - return desc - - -""" Class for standard NVS page structure """ - - -class Page(object): - # Item type codes - U8 = 0x01 - I8 = 0x11 - U16 = 0x02 - I16 = 0x12 - U32 = 0x04 - I32 = 0x14 - U64 = 0x08 - I64 = 0x18 - SZ = 0x21 - BLOB = 0x41 - BLOB_DATA = 0x42 - BLOB_IDX = 0x48 - - # Few Page constants - HEADER_SIZE = 32 - BITMAPARRAY_OFFSET = 32 - BITMAPARRAY_SIZE_IN_BYTES = 32 - FIRST_ENTRY_OFFSET = 64 - SINGLE_ENTRY_SIZE = 32 - CHUNK_ANY = 0xFF - ACTIVE = 0xFFFFFFFE - FULL = 0xFFFFFFFC - VERSION1 = 0xFF - VERSION2 = 0xFE - - PAGE_PARAMS = { - 'max_size': 4096, - 'max_blob_size': {VERSION1: 1984, VERSION2: 4000}, - 'max_entries': 126 - } - - def __init__(self, page_num, version, is_rsrv_page=False): - self.entry_num = 0 - self.bitmap_array = array.array('B') - self.version = version - self.page_buf = bytearray(b'\xff') * Page.PAGE_PARAMS['max_size'] - if not is_rsrv_page: - self.bitmap_array = self.create_bitmap_array() - self.set_header(page_num, version) - - def set_header(self, page_num, version): - # set page state to active - page_header = bytearray(b'\xff') * 32 - page_state_active_seq = Page.ACTIVE - struct.pack_into(' 2: - if not addr_len % 2: - addr_tmp = addr - else: - addr_tmp = init_tweak_val + addr - tweak_tmp = reverse_hexbytes(addr_tmp) - tweak_val = tweak_tmp + (init_tweak_val * (tweak_len_needed - (len(tweak_tmp)))) - else: - tweak_val = addr + (init_tweak_val * (tweak_len_needed - len(addr))) - - # Encrypt data - data_bytes = data_input[start_idx:end_idx] - if type(data_bytes) == bytes: - data_bytes = data_bytes.decode() - - data_val = data_bytes + (init_data_val * (data_len_needed - len(data_bytes))) - encr_data_ret = self.encrypt_entry(data_val, tweak_val, encr_key_input) - encr_data_to_write = encr_data_to_write + encr_data_ret - # Update values for encrypting next set of data bytes - start_idx = end_idx - end_idx = start_idx + 64 - entry_no += 1 - - return encr_data_to_write - - def write_entry_to_buf(self, data, entrycount,nvs_obj): - encr_data = bytearray() - - if nvs_obj.encrypt: - encr_data_ret = self.encrypt_data(data, entrycount,nvs_obj) - encr_data[0:len(encr_data_ret)] = encr_data_ret - data = encr_data - - data_offset = Page.FIRST_ENTRY_OFFSET + (Page.SINGLE_ENTRY_SIZE * self.entry_num) - start_idx = data_offset - end_idx = data_offset + len(data) - self.page_buf[start_idx:end_idx] = data - - # Set bitmap array for entries in current page - for i in range(0, entrycount): - self.write_bitmaparray() - self.entry_num += 1 - - def set_crc_header(self, entry_struct): - crc_data = bytearray(b'28') - crc_data[0:4] = entry_struct[0:4] - crc_data[4:28] = entry_struct[8:32] - crc_data = bytes(crc_data) - crc = zlib.crc32(crc_data, 0xFFFFFFFF) - struct.pack_into('= 0, 'Page overflow!!' - - # Split the binary data into two and store a chunk of available size onto curr page - if tailroom < remaining_size: - chunk_size = tailroom - else: - chunk_size = remaining_size - - remaining_size = remaining_size - chunk_size - - # Change type of data to BLOB_DATA - entry_struct[1] = Page.BLOB_DATA - - # Calculate no. of entries data chunk will require - datachunk_rounded_size = (chunk_size + 31) & ~31 - datachunk_entry_count = datachunk_rounded_size // 32 - datachunk_total_entry_count = datachunk_entry_count + 1 # +1 for the entry header - - # Set Span - entry_struct[2] = datachunk_total_entry_count - - # Update the chunkIndex - chunk_index = chunk_start + chunk_count - entry_struct[3] = chunk_index - - # Set data chunk - data_chunk = data[offset:offset + chunk_size] - - # Compute CRC of data chunk - struct.pack_into(' max_blob_size: - raise InputError(' Input File: Size (%d) exceeds max allowed length `%s` bytes for key `%s`.' - % (datalen, max_blob_size, key)) - - # Calculate no. of entries data will require - rounded_size = (datalen + 31) & ~31 - data_entry_count = rounded_size // 32 - total_entry_count = data_entry_count + 1 # +1 for the entry header - - # Check if page is already full and new page is needed to be created right away - if self.entry_num >= Page.PAGE_PARAMS['max_entries']: - raise PageFullError() - elif (self.entry_num + total_entry_count) >= Page.PAGE_PARAMS['max_entries']: - if not (self.version == Page.VERSION2 and encoding in ['hex2bin', 'binary', 'base64']): - raise PageFullError() - - # Entry header - entry_struct = bytearray(b'\xff') * 32 - # Set Namespace Index - entry_struct[0] = ns_index - # Set Span - if self.version == Page.VERSION2: - if encoding == 'string': - entry_struct[2] = data_entry_count + 1 - # Set Chunk Index - chunk_index = Page.CHUNK_ANY - entry_struct[3] = chunk_index - else: - entry_struct[2] = data_entry_count + 1 - - # set key - key_array = b'\x00' * 16 - entry_struct[8:24] = key_array - entry_struct[8:8 + len(key)] = key.encode() - - # set Type - if encoding == 'string': - entry_struct[1] = Page.SZ - elif encoding in ['hex2bin', 'binary', 'base64']: - entry_struct[1] = Page.BLOB - - if self.version == Page.VERSION2 and (encoding in ['hex2bin', 'binary', 'base64']): - entry_struct = self.write_varlen_binary_data(entry_struct,ns_index,key,data, - datalen,total_entry_count, encoding, nvs_obj) - else: - self.write_single_page_entry(entry_struct, data, datalen, data_entry_count, nvs_obj) - - """ Low-level function to write data of primitive type into page buffer. """ - def write_primitive_data(self, key, data, encoding, ns_index,nvs_obj): - # Check if entry exceeds max number of entries allowed per page - if self.entry_num >= Page.PAGE_PARAMS['max_entries']: - raise PageFullError() - - entry_struct = bytearray(b'\xff') * 32 - entry_struct[0] = ns_index # namespace index - entry_struct[2] = 0x01 # Span - chunk_index = Page.CHUNK_ANY - entry_struct[3] = chunk_index - - # write key - key_array = b'\x00' * 16 - entry_struct[8:24] = key_array - entry_struct[8:8 + len(key)] = key.encode() - - if encoding == 'u8': - entry_struct[1] = Page.U8 - struct.pack_into('/ - :param outdir: Target output dir to store files - :param filepath: Path of target file - ''' - bin_ext = '.bin' - # Expand if tilde(~) provided in path - outdir = os.path.expanduser(outdir) - - if filepath: - key_file_name, ext = os.path.splitext(filepath) - if not ext: - filepath = key_file_name + bin_ext - elif bin_ext not in ext: - sys.exit('Error: `%s`. Only `%s` extension allowed.' % (filepath, bin_ext)) - - # Create dir if does not exist - if not (os.path.isdir(outdir)): - distutils.dir_util.mkpath(outdir) - - filedir, filename = os.path.split(filepath) - filedir = os.path.join(outdir,filedir,'') - if filedir and not os.path.isdir(filedir): - distutils.dir_util.mkpath(filedir) - - if os.path.isabs(filepath): - if not outdir == os.getcwd(): - print('\nWarning: `%s` \n\t==> absolute path given so outdir is ignored for this file.' % filepath) - # Set to empty as outdir is ignored here - outdir = '' - - # Set full path - outdir + filename - filepath = os.path.join(outdir, '') + filepath - - return outdir, filepath - - -def encrypt(args): - ''' - Generate encrypted NVS Partition - :param args: Command line arguments given - ''' - key = None - bin_ext = '.bin' - - check_size(args.size) - if (args.keygen is False) and (not args.inputkey): - sys.exit('Error. --keygen or --inputkey argument needed.') - elif args.keygen and args.inputkey: - sys.exit('Error. --keygen and --inputkey both are not allowed.') - elif not args.keygen and args.keyfile: - print('\nWarning:','--inputkey argument is given. --keyfile argument will be ignored...') - - if args.inputkey: - # Check if key file has .bin extension - filename, ext = os.path.splitext(args.inputkey) - if bin_ext not in ext: - sys.exit('Error: `%s`. Only `%s` extension allowed.' % (args.inputkey, bin_ext)) - key = bytearray() - with open(args.inputkey, 'rb') as key_f: - key = key_f.read(64) - - # Generate encrypted NVS Partition - generate(args, is_encr_enabled=True, encr_key=key) - - -def decrypt_data(data_input, decr_key, page_num, entry_no, entry_size): - ''' - Decrypt NVS data entry - ''' - page_max_size = 4096 - first_entry_offset = 64 - init_tweak_val = '0' - tweak_len_needed = 32 # in hex - tweak_tmp = '' - - data_input = binascii.hexlify(data_input) - rel_addr = page_num * page_max_size + first_entry_offset - - # Set tweak value - offset = entry_no * entry_size - addr = hex(rel_addr + offset)[2:] - addr_len = len(addr) - if addr_len > 2: - if not addr_len % 2: - addr_tmp = addr - else: - addr_tmp = init_tweak_val + addr - tweak_tmp = reverse_hexbytes(addr_tmp) - tweak_val = tweak_tmp + (init_tweak_val * (tweak_len_needed - (len(tweak_tmp)))) - else: - tweak_val = addr + (init_tweak_val * (tweak_len_needed - len(addr))) - - if type(data_input) == bytes: - data_input = data_input.decode() - - # Decrypt 32 bytes of data using XTS-AES decryption - backend = default_backend() - plain_text = codecs.decode(data_input, 'hex') - tweak = codecs.decode(tweak_val, 'hex') - cipher = Cipher(algorithms.AES(decr_key), modes.XTS(tweak), backend=backend) - decryptor = cipher.decryptor() - decrypted_data = decryptor.update(plain_text) - - return decrypted_data - - -def decrypt(args): - ''' - Decrypt encrypted NVS Partition - :param args: Command line arguments given - ''' - bin_ext = '.bin' - nvs_read_bytes = 32 - decrypted_entry_no = 0 - file_entry_no = 0 - page_num = 0 - page_max_size = 4096 - start_entry_offset = 0 - empty_data_entry = bytearray(b'\xff') * nvs_read_bytes - - # Check if key file has .bin extension - input_files = [args.input, args.key, args.output] - for filepath in input_files: - filename, ext = os.path.splitext(filepath) - if bin_ext not in ext: - sys.exit('Error: `%s`. Only `%s` extension allowed.' % (filepath, bin_ext)) - with open(args.key,'rb') as decr_key_file: - decr_key = decr_key_file.read(64) - - args.outdir, args.output = set_target_filepath(args.outdir, args.output) - - output_buf = bytearray(b'\xff') - - with open(args.input, 'rb') as input_file, open(args.output,'wb') as output_file: - while True: - if file_entry_no == 128: - decrypted_entry_no = 0 - file_entry_no = 0 - page_num += 1 - data_entry = input_file.read(nvs_read_bytes) - if not data_entry: - break - if data_entry != empty_data_entry and file_entry_no not in [0,1]: - data_entry = decrypt_data(data_entry, decr_key, page_num, decrypted_entry_no, nvs_read_bytes) - decrypted_entry_no += 1 - write_entry_no = ((page_num * page_max_size) + file_entry_no) - start_idx = start_entry_offset + (write_entry_no * nvs_read_bytes) - end_idx = nvs_read_bytes - output_buf[start_idx:end_idx] = data_entry - file_entry_no += 1 - start_entry_offset += nvs_read_bytes - output_file.write(output_buf) - - print('\nCreated NVS decrypted binary: ===>', args.output) - - -def generate_key(args): - ''' - Generate encryption keys - :param args: Command line arguments given - ''' - page_max_size = 4096 - keys_dir = 'keys' - output_keyfile = None - bin_ext = '.bin' - - if not args.keyfile: - timestamp = datetime.datetime.now().strftime('%m-%d_%H-%M') - args.keyfile = 'keys-' + timestamp + bin_ext - - keys_outdir = os.path.join(args.outdir,keys_dir, '') - # Create keys/ dir in if does not exist - if not (os.path.isdir(keys_outdir)): - distutils.dir_util.mkpath(keys_outdir) - keys_outdir, output_keyfile = set_target_filepath(keys_outdir, args.keyfile) - - keys_buf = bytearray(b'\xff') * page_max_size - key = '' - - if args.key_protect_hmac: - HMAC_EKEY_SEED_ELEMENT = b'\x5A\x5A\xBE\xAE' - HMAC_TKEY_SEED_ELEMENT = b'\xA5\xA5\xDE\xCE' - hmac_key = b'' - - if args.kp_hmac_keygen: - hmac_key_str = ''.join(random.choice('0123456789abcdef') for _ in range(64)).strip() - hmac_key = codecs.decode(hmac_key_str, 'hex') - hmac_keyfile = '' - - if args.kp_hmac_keyfile: - hmac_keyfile = args.kp_hmac_keyfile - else: - hmac_keyfile = 'hmac-' + args.keyfile - - hmac_keyfile = set_target_filepath(keys_outdir, hmac_keyfile)[1] - with open(hmac_keyfile, 'wb') as hmac_key_file: - hmac_key_file.write(hmac_key) - else: - if not args.kp_hmac_inputkey: - raise RuntimeError('HMAC Key input file (HMAC-based encryption scheme) missing!') - - with open(args.kp_hmac_inputkey, 'rb') as input_keys_file: - hmac_key = input_keys_file.read() - - ekey_seed = HMAC_EKEY_SEED_ELEMENT * 8 - h_e = hmac.HMAC(hmac_key, hashes.SHA256()) - h_e.update(ekey_seed) - e_key = h_e.finalize() - - tkey_seed = HMAC_TKEY_SEED_ELEMENT * 8 - h_t = hmac.HMAC(hmac_key, hashes.SHA256()) - h_t.update(tkey_seed) - t_key = h_t.finalize() - - encr_key_bytes = e_key + t_key - key_len = len(encr_key_bytes) - key = f"{int.from_bytes(encr_key_bytes, 'big'):x}" - - keys_buf[0:key_len] = encr_key_bytes - crc_data = keys_buf[0:key_len] - crc_data = bytes(crc_data) - crc = zlib.crc32(crc_data, 0xFFFFFFFF) - struct.pack_into(' ', output_keyfile) - - return key - - -def generate(args, is_encr_enabled=False, encr_key=None): - ''' - Generate NVS Partition - :param args: Command line arguments given - :param is_encr_enabled: Encryption enabled/disabled - :param encr_key: Key to encrypt NVS partition - ''' - is_dir_new = False - bin_ext = '.bin' - - input_size = check_size(args.size) - if args.version == 1: - args.version = Page.VERSION1 - elif args.version == 2: - args.version = Page.VERSION2 - - # Check if key file has .bin extension - filename, ext = os.path.splitext(args.output) - if bin_ext not in ext: - sys.exit('Error: `%s`. Only `.bin` extension allowed.' % args.output) - args.outdir, args.output = set_target_filepath(args.outdir, args.output) - - if is_encr_enabled and not encr_key: - encr_key = generate_key(args) - - with open(args.input, 'rt', encoding='utf8') as input_file,\ - open(args.output, 'wb') as output_file,\ - nvs_open(output_file, input_size, args.version, is_encrypt=is_encr_enabled, key=encr_key) as nvs_obj: - # Comments are skipped - reader = csv.DictReader(filter(lambda row: row[0] != '#',input_file), delimiter=',') - if nvs_obj.version == Page.VERSION1: - version_set = VERSION1_PRINT - else: - version_set = VERSION2_PRINT - print('\nCreating NVS binary with version:', version_set) - - for row in reader: - try: - max_key_len = 15 - if len(row['key']) > max_key_len: - raise InputError('Length of key `%s` should be <= 15 characters.' % row['key']) - write_entry(nvs_obj, row['key'], row['type'], row['encoding'], row['value']) - except InputError as e: - print(e) - filedir, filename = os.path.split(args.output) - if filename: - print('\nWarning: NVS binary not created...') - os.remove(args.output) - if is_dir_new and not filedir == os.getcwd(): - print('\nWarning: Output dir not created...') - os.rmdir(filedir) - sys.exit(-2) - - print('\nCreated NVS binary: ===>', args.output) - - -def main(): - parser = argparse.ArgumentParser(description=desc_format('ESP NVS partition generation utility'), formatter_class=argparse.RawTextHelpFormatter) - subparser = parser.add_subparsers(title='Commands', - dest='command', - help=desc_format('Run nvs_partition_gen.py {command} -h for additional help')) - - parser_gen = subparser.add_parser('generate', - help=desc_format('Generate NVS partition'), - formatter_class=argparse.RawTextHelpFormatter) - parser_gen.set_defaults(func=generate) - parser_gen.add_argument('input', - default=None, - help=desc_format('Path to CSV file to parse')) - parser_gen.add_argument('output', - default=None, - help=desc_format('Path to output NVS binary file')) - parser_gen.add_argument('size', - default=None, - help=desc_format('Size of NVS partition in bytes (must be multiple of 4096)')) - parser_gen.add_argument('--version', - choices=[1,2], - default=2, - type=int, - help=desc_format( - 'Set multipage blob version.', - 'Version 1 - Multipage blob support disabled.', - 'Version 2 - Multipage blob support enabled.', - 'Default: Version 2')) - parser_gen.add_argument('--outdir', - default=os.getcwd(), - help=desc_format('Output directory to store files created (Default: current directory)')) - parser_gen_key = subparser.add_parser('generate-key', - help=desc_format('Generate keys for encryption'), - formatter_class=argparse.RawTextHelpFormatter) - parser_gen_key.set_defaults(func=generate_key) - parser_gen_key.add_argument('--key_protect_hmac', - action='store_true', - help=desc_format( - 'If set, the NVS encryption key protection scheme based on HMAC', - 'peripheral is used; else the default scheme based on Flash Encryption', - 'is used')) - parser_gen_key.add_argument('--kp_hmac_keygen', - action='store_true', - help=desc_format('Generate the HMAC key for HMAC-based encryption scheme')) - parser_gen_key.add_argument('--kp_hmac_keyfile', - default=None, - help=desc_format('Path to output HMAC key file')) - parser_gen_key.add_argument('--kp_hmac_inputkey', - default=None, - help=desc_format('File having the HMAC key for generating the NVS encryption keys')) - parser_gen_key.add_argument('--keyfile', - default=None, - help=desc_format('Path to output encryption keys file')) - parser_gen_key.add_argument('--outdir', - default=os.getcwd(), - help=desc_format('Output directory to store files created. (Default: current directory)')) - parser_encr = subparser.add_parser('encrypt', - help=desc_format('Generate NVS encrypted partition'), - formatter_class=argparse.RawTextHelpFormatter) - parser_encr.set_defaults(func=encrypt) - parser_encr.add_argument('input', - default=None, - help=desc_format('Path to CSV file to parse')) - parser_encr.add_argument('output', - default=None, - help=desc_format('Path to output NVS binary file')) - parser_encr.add_argument('size', - default=None, - help=desc_format('Size of NVS partition in bytes (must be multiple of 4096)')) - parser_encr.add_argument('--version', - choices=[1,2], - default=2, - type=int, - help=desc_format( - 'Set multipage blob version.', - 'Version 1 - Multipage blob support disabled.', - 'Version 2 - Multipage blob support enabled.', - 'Default: Version 2')) - parser_encr.add_argument('--keygen', - action='store_true', - help=desc_format('Generates key for encrypting NVS partition')) - parser_encr.add_argument('--keyfile', - default=None, - help=desc_format('Path to output encryption keys file')) - parser_encr.add_argument('--inputkey', - default=None, - help=desc_format('File having key for encrypting NVS partition')) - parser_encr.add_argument('--outdir', - default=os.getcwd(), - help=desc_format('Output directory to store files created. (Default: current directory)')) - parser_encr.add_argument('--key_protect_hmac', - action='store_true', - help=desc_format( - 'If set, the NVS encryption key protection scheme based on HMAC', - 'peripheral is used; else the default scheme based on Flash Encryption', - 'is used')) - parser_encr.add_argument('--kp_hmac_keygen', - action='store_true', - help=desc_format('Generate the HMAC key for HMAC-based encryption scheme')) - parser_encr.add_argument('--kp_hmac_keyfile', - default=None, - help=desc_format('Path to output HMAC key file')) - parser_encr.add_argument('--kp_hmac_inputkey', - default=None, - help=desc_format('File having the HMAC key for generating the NVS encryption keys')) - parser_decr = subparser.add_parser('decrypt', - help=desc_format('Decrypt NVS encrypted partition'), - formatter_class=argparse.RawTextHelpFormatter) - parser_decr.set_defaults(func=decrypt) - parser_decr.add_argument('input', - default=None, - help=desc_format('Path to encrypted NVS partition file to parse')) - parser_decr.add_argument('key', - default=None, - help=desc_format('Path to file having keys for decryption')) - parser_decr.add_argument('output', - default=None, - help='Path to output decrypted binary file') - parser_decr.add_argument('--outdir', - default=os.getcwd(), - help=desc_format('Output directory to store files created. (Default: current directory)')) - args = parser.parse_args() - - args.func(args) - if __name__ == '__main__': - main() + sys.exit(subprocess.run([sys.executable, '-m', 'esp_idf_nvs_partition_gen'] + sys.argv[1:]).returncode) diff --git a/components/nvs_flash/src/nvs_api.cpp b/components/nvs_flash/src/nvs_api.cpp index 6472a80819a..d349aea466d 100644 --- a/components/nvs_flash/src/nvs_api.cpp +++ b/components/nvs_flash/src/nvs_api.cpp @@ -306,6 +306,25 @@ extern "C" void nvs_close(nvs_handle_t handle) delete static_cast(it); } +extern "C" esp_err_t nvs_find_key(nvs_handle_t c_handle, const char* key, nvs_type_t* out_type) +{ + Lock lock; + ESP_LOGD(TAG, "%s %s", __func__, key); + NVSHandleSimple *handle; + auto err = nvs_find_ns_handle(c_handle, &handle); + if (err != ESP_OK) { + return err; + } + + nvs_type_t nvstype; + err = handle->find_key(key, nvstype); + + if(err == ESP_OK && out_type != nullptr) + *out_type = nvstype; + + return err; +} + extern "C" esp_err_t nvs_erase_key(nvs_handle_t c_handle, const char* key) { Lock lock; diff --git a/components/nvs_flash/src/nvs_handle_locked.cpp b/components/nvs_flash/src/nvs_handle_locked.cpp index 39218874488..898c8fed990 100644 --- a/components/nvs_flash/src/nvs_handle_locked.cpp +++ b/components/nvs_flash/src/nvs_handle_locked.cpp @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "nvs_handle_locked.hpp" namespace nvs { @@ -47,6 +39,12 @@ esp_err_t NVSHandleLocked::get_item_size(ItemType datatype, const char *key, siz return handle->get_item_size(datatype, key, size); } +esp_err_t NVSHandleLocked::find_key(const char* key, nvs_type_t &nvstype) +{ + Lock lock; + return handle->find_key(key, nvstype); +} + esp_err_t NVSHandleLocked::erase_item(const char* key) { Lock lock; return handle->erase_item(key); diff --git a/components/nvs_flash/src/nvs_handle_locked.hpp b/components/nvs_flash/src/nvs_handle_locked.hpp index b9b0cb56209..8a0f87663a4 100644 --- a/components/nvs_flash/src/nvs_handle_locked.hpp +++ b/components/nvs_flash/src/nvs_handle_locked.hpp @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef NVS_HANDLE_LOCKED_HPP_ #define NVS_HANDLE_LOCKED_HPP_ @@ -49,6 +41,8 @@ class NVSHandleLocked : public NVSHandle { esp_err_t get_item_size(ItemType datatype, const char *key, size_t &size) override; + esp_err_t find_key(const char* key, nvs_type_t &nvstype) override; + esp_err_t erase_item(const char* key) override; esp_err_t erase_all() override; diff --git a/components/nvs_flash/src/nvs_handle_simple.cpp b/components/nvs_flash/src/nvs_handle_simple.cpp index 658c811aadc..d6423eb2761 100644 --- a/components/nvs_flash/src/nvs_handle_simple.cpp +++ b/components/nvs_flash/src/nvs_handle_simple.cpp @@ -65,6 +65,23 @@ esp_err_t NVSHandleSimple::get_item_size(ItemType datatype, const char *key, siz return mStoragePtr->getItemDataSize(mNsIndex, datatype, key, size); } +esp_err_t NVSHandleSimple::find_key(const char* key, nvs_type_t &nvstype) +{ + if (!valid) return ESP_ERR_NVS_INVALID_HANDLE; + + nvs::ItemType datatype; + esp_err_t err = mStoragePtr->findKey(mNsIndex, key, &datatype); + if(err != ESP_OK) + return err; + + if(datatype == ItemType::BLOB_IDX || datatype == ItemType::BLOB) + datatype = ItemType::BLOB_DATA; + + nvstype = (nvs_type_t) datatype; + + return err; +} + esp_err_t NVSHandleSimple::erase_item(const char* key) { if (!valid) return ESP_ERR_NVS_INVALID_HANDLE; diff --git a/components/nvs_flash/src/nvs_handle_simple.hpp b/components/nvs_flash/src/nvs_handle_simple.hpp index fe93f9f706b..f7ccb31d27d 100644 --- a/components/nvs_flash/src/nvs_handle_simple.hpp +++ b/components/nvs_flash/src/nvs_handle_simple.hpp @@ -51,6 +51,8 @@ class NVSHandleSimple : public intrusive_list_node, esp_err_t get_item_size(ItemType datatype, const char *key, size_t &size) override; + esp_err_t find_key(const char *key, nvs_type_t &nvstype) override; + esp_err_t erase_item(const char *key) override; esp_err_t erase_all() override; diff --git a/components/nvs_flash/src/nvs_storage.cpp b/components/nvs_flash/src/nvs_storage.cpp index bac19955807..194bfe2b0c2 100644 --- a/components/nvs_flash/src/nvs_storage.cpp +++ b/components/nvs_flash/src/nvs_storage.cpp @@ -683,6 +683,26 @@ esp_err_t Storage::eraseNamespace(uint8_t nsIndex) } +esp_err_t Storage::findKey(const uint8_t nsIndex, const char* key, ItemType* datatype) +{ + if (mState != StorageState::ACTIVE) { + return ESP_ERR_NVS_NOT_INITIALIZED; + } + + Item item; + Page* findPage = nullptr; + auto err = findItem(nsIndex, ItemType::ANY, key, findPage, item); + if (err != ESP_OK) { + return err; + } + + if(datatype != nullptr) { + *datatype = item.datatype; + } + + return err; +} + esp_err_t Storage::getItemDataSize(uint8_t nsIndex, ItemType datatype, const char* key, size_t& dataSize) { if (mState != StorageState::ACTIVE) { diff --git a/components/nvs_flash/src/nvs_storage.hpp b/components/nvs_flash/src/nvs_storage.hpp index 9e64ac9bb58..7c19d6fb9aa 100644 --- a/components/nvs_flash/src/nvs_storage.hpp +++ b/components/nvs_flash/src/nvs_storage.hpp @@ -71,6 +71,8 @@ class Storage : public intrusive_list_node, public ExceptionlessAllocat esp_err_t readItem(uint8_t nsIndex, ItemType datatype, const char* key, void* data, size_t dataSize); + esp_err_t findKey(const uint8_t nsIndex, const char* key, ItemType* datatype); + esp_err_t getItemDataSize(uint8_t nsIndex, ItemType datatype, const char* key, size_t& dataSize); esp_err_t eraseItem(uint8_t nsIndex, ItemType datatype, const char* key); diff --git a/components/nvs_flash/test_apps/main/app_main.c b/components/nvs_flash/test_apps/main/app_main.c index 2dc22a84d7e..3016c4ef7ef 100644 --- a/components/nvs_flash/test_apps/main/app_main.c +++ b/components/nvs_flash/test_apps/main/app_main.c @@ -6,11 +6,27 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "unity.h" +#include "esp_partition.h" +#ifdef CONFIG_NVS_ENCRYPTION +#include "mbedtls/aes.h" +#endif #include "memory_checks.h" /* setUp runs before every test */ void setUp(void) { + // Execute mbedtls_aes_init operation to allocate AES interrupt + // allocation memory which is considered as memory leak otherwise +#if defined(CONFIG_NVS_ENCRYPTION) && defined(SOC_AES_SUPPORTED) + mbedtls_aes_context ctx; + mbedtls_aes_init(&ctx); +#endif + + // Calling esp_partition_find_first ensures that the paritions have been loaded + // and subsequent calls to esp_partition_find_first from the tests would not + // load partitions which otherwise gets considered as a memory leak. + esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, NULL); + test_utils_record_free_mem(); test_utils_set_leak_level(CONFIG_UNITY_CRITICAL_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL); test_utils_set_leak_level(CONFIG_UNITY_WARN_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_GENERAL); diff --git a/components/nvs_flash/test_apps/main/test_nvs.c b/components/nvs_flash/test_apps/main/test_nvs.c index 45abee6831e..4b34e5bddf4 100644 --- a/components/nvs_flash/test_apps/main/test_nvs.c +++ b/components/nvs_flash/test_apps/main/test_nvs.c @@ -97,12 +97,6 @@ TEST_CASE("nvs_flash_init_partition_ptr() works correctly", "[nvs]") } #ifdef CONFIG_SOC_HMAC_SUPPORTED -/* TODO: This test does not run in CI as the runner assigned has - * flash encryption enabled by default. Enabling flash encryption - * 'selects' NVS encryption; a new runner needs to be setup - * for testing the HMAC NVS encryption scheme without flash encryption - * enabled for this test. - */ TEST_CASE("test nvs encryption with HMAC-based scheme without toggling any config options", "[nvs_encr_hmac]") { nvs_handle_t handle; diff --git a/components/nvs_flash/test_apps/pytest_nvs_flash.py b/components/nvs_flash/test_apps/pytest_nvs_flash.py index 1da98e2da0a..174664912ed 100644 --- a/components/nvs_flash/test_apps/pytest_nvs_flash.py +++ b/components/nvs_flash/test_apps/pytest_nvs_flash.py @@ -26,6 +26,13 @@ def test_nvs_flash_encr_hmac(dut: IdfDut) -> None: dut.run_all_single_board_cases() +@pytest.mark.esp32c3 +@pytest.mark.nvs_encr_hmac +@pytest.mark.parametrize('config', ['nvs_encr_hmac_no_cfg_esp32c3'], indirect=True) +def test_nvs_flash_encr_hmac_no_cfg(dut: IdfDut) -> None: + dut.run_all_single_board_cases(group='nvs_encr_hmac', timeout=120) + + @pytest.mark.flash_encryption @pytest.mark.parametrize('config', CONFIGS_NVS_ENCR_FLASH_ENC, indirect=True) def test_nvs_flash_encr_flash_enc(dut: IdfDut) -> None: diff --git a/components/nvs_flash/test_apps/sdkconfig.ci.nvs_encr_hmac_no_cfg_esp32c3 b/components/nvs_flash/test_apps/sdkconfig.ci.nvs_encr_hmac_no_cfg_esp32c3 new file mode 100644 index 00000000000..6d5be69e260 --- /dev/null +++ b/components/nvs_flash/test_apps/sdkconfig.ci.nvs_encr_hmac_no_cfg_esp32c3 @@ -0,0 +1,22 @@ +# Restricting to ESP32C3 +CONFIG_IDF_TARGET="esp32c3" + +# NOTE: The runner for this test-app has flash-encryption enabled +# Partition Table +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_nvs_encr_flash_enc.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_nvs_encr_flash_enc.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x9000 + +# Enabling Flash Encryption +CONFIG_SECURE_FLASH_ENC_ENABLED=y +CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y +CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y +CONFIG_SECURE_BOOT_ALLOW_JTAG=y +CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y +CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y +CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y +CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y + +# Disabling NVS encryption +CONFIG_NVS_ENCRYPTION=n diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt index e0030687ab4..8dfd62708f2 100644 --- a/components/openthread/CMakeLists.txt +++ b/components/openthread/CMakeLists.txt @@ -18,6 +18,7 @@ if(CONFIG_OPENTHREAD_ENABLED) "openthread/include/openthread" "openthread/src" "openthread/src/core" + "openthread/src/lib" "openthread/src/lib/hdlc" "openthread/src/lib/spinel" "openthread/src/ncp" @@ -31,6 +32,7 @@ if(CONFIG_OPENTHREAD_ENABLED) "openthread/src/core/common" "openthread/src/core/crypto" "openthread/src/core/diags" + "openthread/src/core/instance" "openthread/src/core/mac" "openthread/src/core/radio" "openthread/src/core/thread" @@ -41,7 +43,7 @@ if(CONFIG_OPENTHREAD_ENABLED) set(exclude_srcs "openthread/examples/platforms/utils/logging_rtt.c" "openthread/examples/platforms/utils/soft_source_match_table.c" - "openthread/src/core/common/extension_example.cpp") + "openthread/src/core/instance/extension_example.cpp") if(CONFIG_OPENTHREAD_FTD OR CONFIG_OPENTHREAD_MTD) list(APPEND src_dirs @@ -194,7 +196,7 @@ idf_component_register(SRC_DIRS "${src_dirs}" EXCLUDE_SRCS "${exclude_srcs}" INCLUDE_DIRS "${public_include_dirs}" PRIV_INCLUDE_DIRS "${private_include_dirs}" - REQUIRES esp_netif lwip driver + REQUIRES esp_netif lwip esp_driver_uart driver LDFRAGMENTS linker.lf PRIV_REQUIRES console esp_event esp_partition esp_timer ieee802154 mbedtls nvs_flash) diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index d18ec6b8924..c298ca40e5f 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -163,6 +163,7 @@ menu "OpenThread" config OPENTHREAD_RCP_SPI bool "SPI RCP" + select GPIO_CTRL_FUNC_IN_IRAM help Select this to enable SPI connection to host. endchoice diff --git a/components/openthread/include/esp_openthread_border_router.h b/components/openthread/include/esp_openthread_border_router.h index 33f9244eb7d..3a6c6e96387 100644 --- a/components/openthread/include/esp_openthread_border_router.h +++ b/components/openthread/include/esp_openthread_border_router.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -69,8 +69,22 @@ void esp_openthread_register_rcp_failure_handler(esp_openthread_rcp_failure_hand /** * @brief Deinitializes the conneciton to RCP. * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if fail to deinitialize RCP + * + */ +esp_err_t esp_openthread_rcp_deinit(void); + +/** + * @brief Initializes the conneciton to RCP. + * + * @return + * - ESP_OK on success + * - ESP_FAIL if fail to initialize RCP + * */ -void esp_openthread_rcp_deinit(void); +esp_err_t esp_openthread_rcp_init(void); #ifdef __cplusplus } diff --git a/components/openthread/lib b/components/openthread/lib index 12f563ee490..648c28e7925 160000 --- a/components/openthread/lib +++ b/components/openthread/lib @@ -1 +1 @@ -Subproject commit 12f563ee490236f7332eb22f568e71c7c1d4a3b7 +Subproject commit 648c28e792567bc00602c92e43518c1784599251 diff --git a/components/openthread/openthread b/components/openthread/openthread index af5938e389b..41ef80717f4 160000 --- a/components/openthread/openthread +++ b/components/openthread/openthread @@ -1 +1 @@ -Subproject commit af5938e389be40650507748272bb6c6b3a2de2cf +Subproject commit 41ef80717f4b757440125932723cc8721ef42f7f diff --git a/components/openthread/private_include/esp_openthread_radio.h b/components/openthread/private_include/esp_openthread_radio.h index 7cf41a559b7..d3fa70aa2cc 100644 --- a/components/openthread/private_include/esp_openthread_radio.h +++ b/components/openthread/private_include/esp_openthread_radio.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/openthread/private_include/esp_spi_spinel_interface.hpp b/components/openthread/private_include/esp_spi_spinel_interface.hpp index 6b8ae2833e1..e5b0976e1fd 100644 --- a/components/openthread/private_include/esp_spi_spinel_interface.hpp +++ b/components/openthread/private_include/esp_spi_spinel_interface.hpp @@ -14,18 +14,12 @@ namespace esp { namespace openthread { -class SpiSpinelInterface { +class SpiSpinelInterface : public ot::Spinel::SpinelInterface { public: /** * @brief This constructor of object. - * - * @param[in] callback Callback on frame received - * @param[in] callback_context Callback context - * @param[in] frame_buffer A reference to a `RxFrameBuffer` object. - * */ - SpiSpinelInterface(ot::Spinel::SpinelInterface::ReceiveFrameCallback callback, void *callback_context, - ot::Spinel::SpinelInterface::RxFrameBuffer &frame_buffer); + SpiSpinelInterface(); /** * @brief This destructor of the object. @@ -34,24 +28,26 @@ class SpiSpinelInterface { ~SpiSpinelInterface(void); /** - * @brief This method initializes the spinel interface. + * Initializes the interface to the Radio Co-processor (RCP). + * + * @note This method should be called before reading and sending spinel frames to the interface. + * + * @param[in] aCallback Callback on frame received + * @param[in] aCallbackContext Callback context + * @param[in] aFrameBuffer A reference to a `RxFrameBuffer` object. + * + * @retval OT_ERROR_NONE The interface is initialized successfully + * @retval OT_ERROR_ALREADY The interface is already initialized. + * @retval OT_ERROR_FAILED Failed to initialize the interface. * - * @return - * - ESP_OK on success - * - ESP_ERR_INVALID_STATE if already initialized - * - ESP_ERR_NO_MEM if allocation has failed - * - ESP_FAIL on failure */ - esp_err_t Init(const esp_openthread_spi_host_config_t &spi_config); + otError Init(ReceiveFrameCallback aCallback, void *aCallbackContext, RxFrameBuffer &aFrameBuffer); /** - * @brief This method deinitializes the HDLC interface. + * Deinitializes the interface to the RCP. * - * @return - * - ESP_OK on success - * - ESP_FAIL on failure */ - esp_err_t Deinit(void); + void Deinit(void); /** * @brief This method encodes and sends a spinel frame to Radio Co-processor (RCP) over the socket. @@ -80,20 +76,42 @@ class SpiSpinelInterface { otError WaitForFrame(uint64_t timeout_us); /** - * This method performs spi processing to the RCP. + * Updates the file descriptor sets with file descriptors used by the radio driver. * - * @param[in] mainloop The mainloop context + * @param[in,out] aMainloopContext A pointer to the mainloop context. * */ - void Process(const void *mainloop); + void UpdateFdSet(void *aMainloopContext); /** - * This methods updates the mainloop context. + * Performs radio driver processing. * - * @param[inout] mainloop The mainloop context. + * @param[in] aMainloopContext A pointer to the mainloop context. * */ - void Update(void *mainloop); + void Process(const void *aMainloopContext); + + /** + * Returns the bus speed between the host and the radio. + * + * @returns Bus speed in bits/second. + * + */ + uint32_t GetBusSpeed(void) const; + + /** + * This method is called when RCP failure detected and resets internal states of the interface. + * + */ + otError HardwareReset(void); + + /** + * Returns the RCP interface metrics. + * + * @returns The RCP interface metrics. + * + */ + const otRcpInterfaceMetrics *GetRcpInterfaceMetrics(void) const { return &mInterfaceMetrics; } /** * This methods registers the callback for RCP failure. @@ -111,10 +129,33 @@ class SpiSpinelInterface { otError ResetConnection(void) { return OT_ERROR_NONE; } /** - * This method is called when RCP failure detected and resets internal states of the interface. + * @brief This method enable the spinel interface. * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if already initialized + * - ESP_ERR_NO_MEM if allocation has failed + * - ESP_FAIL on failure */ - otError HardwareReset(void); + esp_err_t Enable(const esp_openthread_spi_host_config_t &spi_config); + + /** + * @brief This method disable the spinel interface. + * + * @return + * - ESP_OK on success + * - ESP_FAIL on failure + */ + esp_err_t Disable(void); + + /** + * @brief This method should be called after radio is initialized. + * + * @return + * - ESP_OK on success + * - ESP_FAIL on failure + */ + esp_err_t AfterRadioInit(void); private: static constexpr uint8_t kSPIFrameHeaderSize = 5; @@ -130,14 +171,16 @@ class SpiSpinelInterface { int m_event_fd; volatile uint16_t m_pending_data_len; - ot::Spinel::SpinelInterface::ReceiveFrameCallback m_receiver_frame_callback; + ReceiveFrameCallback m_receiver_frame_callback; void *m_receiver_frame_context; - ot::Spinel::SpinelInterface::RxFrameBuffer &m_receive_frame_buffer; + RxFrameBuffer *m_receive_frame_buffer; bool m_has_pending_device_frame; spi_device_handle_t m_device; esp_openthread_rcp_failure_handler mRcpFailureHandler; + + otRcpInterfaceMetrics mInterfaceMetrics; }; } // namespace openthread diff --git a/components/openthread/private_include/esp_spinel_interface.hpp b/components/openthread/private_include/esp_spinel_interface.hpp new file mode 100644 index 00000000000..7a393e570d7 --- /dev/null +++ b/components/openthread/private_include/esp_spinel_interface.hpp @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" +#include "esp_openthread.h" +#include "esp_openthread_types.h" +#include "hal/uart_types.h" +#include "lib/spinel/spinel_interface.hpp" +#include "lib/hdlc/hdlc.hpp" +#include "openthread/error.h" + +namespace esp { +namespace openthread { + +/** + * This class defines an template to adapt both UartSpinelInterface and SpiSpinelInterface. + * + */ +template class SpinelInterfaceAdapter { +public: + /** + * @brief This constructor of object. + */ + SpinelInterfaceAdapter(void) {} + + /** + * @brief This destructor of the object. + * + */ + ~SpinelInterfaceAdapter(void) {} + + /** + * @brief This method return the underlying spinel interface. + * + * @return The underlying spinel interface. + * + */ + InterfaceType &GetSpinelInterface(void) { return mSpinelInterface; } + +private: + InterfaceType mSpinelInterface; +}; + +} // namespace openthread +} // namespace esp diff --git a/components/openthread/private_include/esp_uart_spinel_interface.hpp b/components/openthread/private_include/esp_uart_spinel_interface.hpp index d21c16a23bc..8926ab7fc13 100644 --- a/components/openthread/private_include/esp_uart_spinel_interface.hpp +++ b/components/openthread/private_include/esp_uart_spinel_interface.hpp @@ -21,18 +21,12 @@ namespace openthread { * This class defines an UART interface to the Radio Co-processor (RCP). * */ -class UartSpinelInterface { +class UartSpinelInterface : public ot::Spinel::SpinelInterface { public: /** * @brief This constructor of object. - * - * @param[in] callback Callback on frame received - * @param[in] callback_context Callback context - * @param[in] frame_buffer A reference to a `RxFrameBuffer` object. - * */ - UartSpinelInterface(ot::Spinel::SpinelInterface::ReceiveFrameCallback callback, void *callback_context, - ot::Spinel::SpinelInterface::RxFrameBuffer &frame_buffer); + UartSpinelInterface(void); /** * @brief This destructor of the object. @@ -41,80 +35,101 @@ class UartSpinelInterface { ~UartSpinelInterface(void); /** - * @brief This method initializes the HDLC interface. + * Initializes the interface to the Radio Co-processor (RCP). + * + * @note This method should be called before reading and sending spinel frames to the interface. + * + * @param[in] aCallback Callback on frame received + * @param[in] aCallbackContext Callback context + * @param[in] aFrameBuffer A reference to a `RxFrameBuffer` object. + * + * @retval OT_ERROR_NONE The interface is initialized successfully + * @retval OT_ERROR_ALREADY The interface is already initialized. + * @retval OT_ERROR_FAILED Failed to initialize the interface. * - * @return - * - ESP_OK on success - * - ESP_ERR_NO_MEM if allocation has failed - * - ESP_ERROR on failure */ - esp_err_t Init(const esp_openthread_uart_config_t &radio_uart_config); + otError Init(ReceiveFrameCallback aCallback, void *aCallbackContext, RxFrameBuffer &aFrameBuffer); /** - * @brief This method deinitializes the HDLC interface. + * Deinitializes the interface to the RCP. * */ - esp_err_t Deinit(void); + void Deinit(void); /** - * @brief This method encodes and sends a spinel frame to Radio Co-processor (RCP) over the socket. + * Encodes and sends a spinel frame to Radio Co-processor (RCP) over the socket. * - * @note This is blocking call, i.e., if the socket is not writable, this method waits for it to become writable - * for up to `kMaxWaitTime` interval. + * @param[in] aFrame A pointer to buffer containing the spinel frame to send. + * @param[in] aLength The length (number of bytes) in the frame. * - * @param[in] frame A pointer to buffer containing the spinel frame to send. - * @param[in] length The length (number of bytes) in the frame. - * - * @return - * -OT_ERROR_NONE Successfully encoded and sent the spinel frame. - * -OT_ERROR_NO_BUFS Insufficient buffer space available to encode the frame. - * -OT_ERROR_FAILED Failed to send due to socket not becoming writable within `kMaxWaitTime`. + * @retval OT_ERROR_NONE Successfully encoded and sent the spinel frame. + * @retval OT_ERROR_BUSY Failed due to another operation is on going. + * @retval OT_ERROR_NO_BUFS Insufficient buffer space available to encode the frame. + * @retval OT_ERROR_FAILED Failed to call the SPI driver to send the frame. * */ - otError SendFrame(const uint8_t *frame, uint16_t length); + otError SendFrame(const uint8_t *aFrame, uint16_t aLength); /** - * This method waits for receiving part or all of spinel frame within specified timeout. + * Waits for receiving part or all of spinel frame within specified interval. * - * @param[in] timeout_us The timeout value in microseconds. + * @param[in] aTimeout The timeout value in microseconds. * - * @return - * -OT_ERROR_NONE Part or all of spinel frame is received. - * -OT_ERROR_RESPONSE_TIMEOUT No spinel frame is received within @p timeout_us. + * @retval OT_ERROR_NONE Part or all of spinel frame is received. + * @retval OT_ERROR_RESPONSE_TIMEOUT No spinel frame is received within @p aTimeout. * */ - otError WaitForFrame(uint64_t timeout_us); + otError WaitForFrame(uint64_t aTimeoutUs); /** - * This method performs uart processing to the RCP. + * Updates the file descriptor sets with file descriptors used by the radio driver. * - * @param[in] mainloop The mainloop context + * @param[in,out] aMainloopContext A pointer to the mainloop context. * */ - void Process(const void *mainloop); + void UpdateFdSet(void *aMainloopContext); /** - * This methods updates the mainloop context. + * Performs radio driver processing. * - * @param[inout] mainloop The mainloop context. + * @param[in] aMainloopContext A pointer to the mainloop context. * */ - void Update(void *mainloop); + void Process(const void *aMainloopContext); /** - * This methods registers the callback for RCP failure. + * Returns the bus speed between the host and the radio. * - * @param[in] handler The RCP failure handler. + * @returns Bus speed in bits/second. * */ - void RegisterRcpFailureHandler(esp_openthread_rcp_failure_handler handler) { mRcpFailureHandler = handler; } + uint32_t GetBusSpeed(void) const; /** - * This method is called when RCP failure detected and resets internal states of the interface. + * Hardware resets the RCP. + * + * @retval OT_ERROR_NONE Successfully reset the RCP. + * @retval OT_ERROR_NOT_IMPLEMENT The hardware reset is not implemented. * */ otError HardwareReset(void); + /** + * Returns the RCP interface metrics. + * + * @returns The RCP interface metrics. + * + */ + const otRcpInterfaceMetrics *GetRcpInterfaceMetrics(void) const { return &mInterfaceMetrics; } + + /** + * This methods registers the callback for RCP failure. + * + * @param[in] handler The RCP failure handler. + * + */ + void RegisterRcpFailureHandler(esp_openthread_rcp_failure_handler handler) { mRcpFailureHandler = handler; } + /** * This method is called when RCP is reset to recreate the connection with it. * Intentionally empty. @@ -122,14 +137,25 @@ class UartSpinelInterface { */ otError ResetConnection(void) { return OT_ERROR_NONE; } + /** + * @brief This method enable the HDLC interface. + * + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM if allocation has failed + * - ESP_ERROR on failure + */ + esp_err_t Enable(const esp_openthread_uart_config_t &radio_uart_config); + + /** + * @brief This method disable the HDLC interface. + * + */ + esp_err_t Disable(void); + private: - enum { - /** - * Maximum spinel frame size. - * - */ - kMaxFrameSize = ot::Spinel::SpinelInterface::kMaxFrameSize, + enum { /** * Maximum wait time in Milliseconds for socket to become writable (see `SendFrame`). * @@ -152,9 +178,9 @@ class UartSpinelInterface { static void HandleHdlcFrame(void *context, otError error); void HandleHdlcFrame(otError error); - ot::Spinel::SpinelInterface::ReceiveFrameCallback m_receiver_frame_callback; + ReceiveFrameCallback m_receiver_frame_callback; void *m_receiver_frame_context; - ot::Spinel::SpinelInterface::RxFrameBuffer &m_receive_frame_buffer; + RxFrameBuffer *m_receive_frame_buffer; ot::Hdlc::Decoder m_hdlc_decoder; uint8_t *m_uart_rx_buffer; @@ -162,6 +188,8 @@ class UartSpinelInterface { esp_openthread_uart_config_t m_uart_config; int m_uart_fd; + otRcpInterfaceMetrics mInterfaceMetrics; + // Non-copyable, intentionally not implemented. UartSpinelInterface(const UartSpinelInterface &); UartSpinelInterface &operator=(const UartSpinelInterface &); diff --git a/components/openthread/src/esp_openthread_platform.cpp b/components/openthread/src/esp_openthread_platform.cpp index ef46800a78c..f6f29e278e5 100644 --- a/components/openthread/src/esp_openthread_platform.cpp +++ b/components/openthread/src/esp_openthread_platform.cpp @@ -20,7 +20,7 @@ #include "esp_partition.h" #include "common/code_utils.hpp" #include "common/logging.hpp" -#include "core/common/instance.hpp" +#include "core/instance/instance.hpp" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" #include "openthread/cli.h" diff --git a/components/openthread/src/port/esp_openthread_radio_spinel.cpp b/components/openthread/src/port/esp_openthread_radio_spinel.cpp index 2e0cab92f7a..83fdf9b006a 100644 --- a/components/openthread/src/port/esp_openthread_radio_spinel.cpp +++ b/components/openthread/src/port/esp_openthread_radio_spinel.cpp @@ -13,6 +13,7 @@ #include "esp_openthread_platform.h" #include "esp_openthread_types.h" #include "esp_system.h" +#include "esp_spinel_interface.hpp" #include "esp_spi_spinel_interface.hpp" #include "esp_uart_spinel_interface.hpp" #include "openthread-core-config.h" @@ -20,41 +21,100 @@ #include "lib/spinel/spinel.h" #include "openthread/platform/diag.h" #include "openthread/platform/radio.h" +#include "platform/exit_code.h" using ot::Spinel::RadioSpinel; +using esp::openthread::SpinelInterfaceAdapter; -#if CONFIG_OPENTHREAD_RADIO_SPINEL_UART +#if CONFIG_OPENTHREAD_RADIO_SPINEL_UART // CONFIG_OPENTHREAD_RADIO_SPINEL_UART using esp::openthread::UartSpinelInterface; -static RadioSpinel s_radio; +static SpinelInterfaceAdapter s_spinel_interface; #else // CONFIG_OPENTHREAD_RADIO_SPINEL_SPI using esp::openthread::SpiSpinelInterface; -static RadioSpinel s_radio; -#endif // CONFIG_OPENTHREAD_RADIO_SPINEL_UART +static SpinelInterfaceAdapter s_spinel_interface; +#endif + +static RadioSpinel s_radio; static const char *radiospinel_workflow = "radio_spinel"; +static const esp_openthread_radio_config_t *s_esp_openthread_radio_config = NULL; + +static void esp_openthread_radio_config_set(const esp_openthread_radio_config_t *config) +{ + s_esp_openthread_radio_config = config; +} + +static const esp_openthread_radio_config_t *esp_openthread_radio_config_get(void) +{ + return s_esp_openthread_radio_config; +} + esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *config) { -#if CONFIG_OPENTHREAD_RADIO_SPINEL_UART - ESP_RETURN_ON_ERROR(s_radio.GetSpinelInterface().Init(config->radio_config.radio_uart_config), OT_PLAT_LOG_TAG, + spinel_iid_t iidList[ot::Spinel::kSpinelHeaderMaxNumIid]; + iidList[0] = 0; + + ot::Spinel::RadioSpinelCallbacks callbacks; +#if CONFIG_OPENTHREAD_DIAG + callbacks.mDiagReceiveDone = otPlatDiagRadioReceiveDone; + callbacks.mDiagTransmitDone = otPlatDiagRadioTransmitDone; +#endif // OPENTHREAD_CONFIG_DIAG_ENABLE + callbacks.mEnergyScanDone = otPlatRadioEnergyScanDone; + callbacks.mReceiveDone = otPlatRadioReceiveDone; + callbacks.mTransmitDone = otPlatRadioTxDone; + callbacks.mTxStarted = otPlatRadioTxStarted; + s_radio.SetCallbacks(callbacks); + + esp_openthread_radio_config_set(&config->radio_config); +#if CONFIG_OPENTHREAD_RADIO_SPINEL_UART // CONFIG_OPENTHREAD_RADIO_SPINEL_UART + ESP_RETURN_ON_ERROR(s_spinel_interface.GetSpinelInterface().Enable(config->radio_config.radio_uart_config), OT_PLAT_LOG_TAG, "Spinel interface init falied"); -#else // CONFIG_OPENTHREAD_RADIO_SPINEL_SPI - ESP_RETURN_ON_ERROR(s_radio.GetSpinelInterface().Init(config->radio_config.radio_spi_config), OT_PLAT_LOG_TAG, +#else // CONFIG_OPENTHREAD_RADIO_SPINEL_SPI + ESP_RETURN_ON_ERROR(s_spinel_interface.GetSpinelInterface().Enable(config->radio_config.radio_spi_config), OT_PLAT_LOG_TAG, "Spinel interface init failed"); -#endif // CONFIG_OPENTHREAD_RADIO_SPINEL_UART - s_radio.Init(/*reset_radio=*/true, /*skip_rcp_compatibility_check=*/false); +#endif + s_radio.Init(s_spinel_interface.GetSpinelInterface(), /*reset_radio=*/true, /*skip_rcp_compatibility_check=*/false, iidList, ot::Spinel::kSpinelHeaderMaxNumIid); +#if CONFIG_OPENTHREAD_RADIO_SPINEL_SPI // CONFIG_OPENTHREAD_RADIO_SPINEL_SPI + ESP_RETURN_ON_ERROR(s_spinel_interface.GetSpinelInterface().AfterRadioInit(), OT_PLAT_LOG_TAG, "Spinel interface init falied"); +#endif return esp_openthread_platform_workflow_register(&esp_openthread_radio_update, &esp_openthread_radio_process, radiospinel_workflow); } void esp_openthread_register_rcp_failure_handler(esp_openthread_rcp_failure_handler handler) { - s_radio.GetSpinelInterface().RegisterRcpFailureHandler(handler); + s_spinel_interface.GetSpinelInterface().RegisterRcpFailureHandler(handler); +} + +esp_err_t esp_openthread_rcp_deinit(void) +{ + ESP_RETURN_ON_FALSE(otThreadGetDeviceRole(esp_openthread_get_instance()) == OT_DEVICE_ROLE_DISABLED, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "Thread is enabled, failed to deinitialize RCP"); + ESP_RETURN_ON_FALSE(!otIp6IsEnabled(esp_openthread_get_instance()), ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "OT interface is up, failed to deinitialize RCP"); + if (s_radio.IsEnabled()) { + ESP_RETURN_ON_FALSE(s_radio.Sleep() == OT_ERROR_NONE, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "Radio fails to sleep"); + ESP_RETURN_ON_FALSE(s_radio.Disable() == OT_ERROR_NONE, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "Fail to disable radio"); + } + ESP_RETURN_ON_FALSE(s_spinel_interface.GetSpinelInterface().Disable() == OT_ERROR_NONE, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "Fail to deinitialize UART"); + esp_openthread_platform_workflow_unregister(radiospinel_workflow); + return ESP_OK; } -void esp_openthread_rcp_deinit(void) +esp_err_t esp_openthread_rcp_init(void) { - s_radio.GetSpinelInterface().Deinit(); + const esp_openthread_radio_config_t *radio_config = esp_openthread_radio_config_get(); +#if CONFIG_OPENTHREAD_RADIO_SPINEL_UART + ESP_RETURN_ON_ERROR(s_spinel_interface.GetSpinelInterface().Enable(radio_config->radio_uart_config), OT_PLAT_LOG_TAG, + "Spinel interface init falied"); +#else // CONFIG_OPENTHREAD_RADIO_SPINEL_SPI + ESP_RETURN_ON_ERROR(s_spinel_interface.GetSpinelInterface().Enable(radio_config->radio_spi_config), OT_PLAT_LOG_TAG, + "Spinel interface init failed"); +#endif // CONFIG_OPENTHREAD_RADIO_SPINEL_UART + + ESP_RETURN_ON_FALSE(s_radio.Enable(esp_openthread_get_instance()) == OT_ERROR_NONE, ESP_FAIL, OT_PLAT_LOG_TAG, "Fail to enable radio"); + s_radio.RestoreProperties(); + return esp_openthread_platform_workflow_register(&esp_openthread_radio_update, &esp_openthread_radio_process, + radiospinel_workflow); } void esp_openthread_radio_deinit(void) @@ -72,7 +132,7 @@ esp_err_t esp_openthread_radio_process(otInstance *instance, const esp_openthrea void esp_openthread_radio_update(esp_openthread_mainloop_context_t *mainloop) { - s_radio.GetSpinelInterface().Update((void *)mainloop); + s_spinel_interface.GetSpinelInterface().UpdateFdSet((void *)mainloop); } void otPlatRadioGetIeeeEui64(otInstance *instance, uint8_t *ieee_eui64) diff --git a/components/openthread/src/port/esp_openthread_spi_slave.c b/components/openthread/src/port/esp_openthread_spi_slave.c index 33268bb8c5b..979e6067e79 100644 --- a/components/openthread/src/port/esp_openthread_spi_slave.c +++ b/components/openthread/src/port/esp_openthread_spi_slave.c @@ -17,10 +17,10 @@ #include "esp_attr.h" #include "esp_check.h" #include "esp_err.h" +#include "esp_heap_caps.h" #include "esp_openthread_common_macro.h" #include "esp_openthread_task_queue.h" #include "esp_openthread_types.h" -#include "esp_rom_sys.h" #include #include #include "driver/gpio.h" @@ -33,37 +33,38 @@ static const char *SPI_SLAVE_TAG = "spi_slave"; static void *s_context = NULL; -static uint8_t *s_prev_output_buf; -static uint16_t s_prev_output_len; -static uint8_t *s_prev_input_buf; -static uint16_t s_prev_input_len; +static uint8_t *s_output_buf; +static uint16_t s_output_len; +static uint8_t *s_input_buf; +static uint16_t s_input_len; static bool s_request_transaction = false; - -static esp_openthread_spi_slave_config_t s_spi_config; -static otPlatSpiSlaveTransactionProcessCallback s_process_callback = NULL; -static otPlatSpiSlaveTransactionCompleteCallback s_complete_callback = NULL; -static spi_slave_transaction_t s_spi_transaction; - typedef struct { uint16_t output_buf_len; uint16_t input_buf_len; } pending_transaction_t; +static otPlatSpiSlaveTransactionProcessCallback s_process_callback = NULL; +static otPlatSpiSlaveTransactionCompleteCallback s_complete_callback = NULL; + +static DRAM_ATTR esp_openthread_spi_slave_config_t *s_spi_config; +static DRAM_ATTR spi_slave_transaction_t *s_spi_transaction; +static DRAM_ATTR pending_transaction_t *s_pending_transaction; + static void IRAM_ATTR handle_spi_setup_done(spi_slave_transaction_t *trans) { if (s_request_transaction) { - gpio_set_level(s_spi_config.intr_pin, 0); + gpio_set_level(s_spi_config->intr_pin, 0); } } static void IRAM_ATTR handle_spi_transaction_done(spi_slave_transaction_t *trans) { - gpio_set_level(s_spi_config.intr_pin, 1); - pending_transaction_t *pending_transaction = (pending_transaction_t *)&(trans->user); + gpio_set_level(s_spi_config->intr_pin, 1); + pending_transaction_t *pending_transaction = (pending_transaction_t *)(trans->user); trans->trans_len /= CHAR_BIT; if (s_complete_callback && - s_complete_callback(s_context, (uint8_t *)trans->tx_buffer, pending_transaction->output_buf_len, + s_complete_callback(s_context, (void*)trans->tx_buffer, pending_transaction->output_buf_len, trans->rx_buffer, pending_transaction->input_buf_len, trans->trans_len)) { esp_openthread_task_queue_post(s_process_callback, s_context); } @@ -72,23 +73,38 @@ static void IRAM_ATTR handle_spi_transaction_done(spi_slave_transaction_t *trans esp_err_t esp_openthread_host_rcp_spi_init(const esp_openthread_platform_config_t *config) { - s_spi_config = config->host_config.spi_slave_config; + s_spi_config = heap_caps_malloc(sizeof(esp_openthread_spi_slave_config_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + ESP_RETURN_ON_FALSE(s_spi_config != NULL, ESP_ERR_NO_MEM, OT_PLAT_LOG_TAG, + "failed to allocate memory for SPI transaction on internal heap"); + memcpy(s_spi_config, &(config->host_config.spi_slave_config), sizeof(esp_openthread_spi_slave_config_t)); gpio_config_t io_conf = { .intr_type = GPIO_INTR_DISABLE, .mode = GPIO_MODE_OUTPUT, - .pin_bit_mask = (1 << s_spi_config.intr_pin), + .pin_bit_mask = (1 << s_spi_config->intr_pin), }; ESP_RETURN_ON_ERROR(gpio_config(&io_conf), OT_PLAT_LOG_TAG, "fail to configure SPI gpio"); - gpio_set_pull_mode(s_spi_config.bus_config.mosi_io_num, GPIO_PULLUP_ONLY); - gpio_set_pull_mode(s_spi_config.bus_config.sclk_io_num, GPIO_PULLUP_ONLY); - gpio_set_pull_mode(s_spi_config.slave_config.spics_io_num, GPIO_PULLUP_ONLY); + gpio_set_pull_mode(s_spi_config->bus_config.mosi_io_num, GPIO_PULLUP_ONLY); + gpio_set_pull_mode(s_spi_config->bus_config.sclk_io_num, GPIO_PULLUP_ONLY); + gpio_set_pull_mode(s_spi_config->slave_config.spics_io_num, GPIO_PULLUP_ONLY); + + s_spi_transaction = heap_caps_malloc(sizeof(spi_slave_transaction_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + s_pending_transaction = heap_caps_malloc(sizeof(pending_transaction_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + if (s_spi_transaction == NULL || s_pending_transaction == NULL) { + heap_caps_free(s_spi_config); + heap_caps_free(s_spi_transaction); + heap_caps_free(s_pending_transaction); + ESP_LOGE(OT_PLAT_LOG_TAG, "failed to allocate memory for SPI transaction on internal heap"); + return ESP_ERR_NO_MEM; + } + + s_spi_transaction->user = (void *)s_pending_transaction; /* Initialize SPI slave interface */ - s_spi_config.slave_config.post_setup_cb = handle_spi_setup_done; - s_spi_config.slave_config.post_trans_cb = handle_spi_transaction_done; - ESP_RETURN_ON_ERROR(spi_slave_initialize(s_spi_config.host_device, &s_spi_config.bus_config, - &s_spi_config.slave_config, SPI_DMA_CH_AUTO), + s_spi_config->slave_config.post_setup_cb = handle_spi_setup_done; + s_spi_config->slave_config.post_trans_cb = handle_spi_transaction_done; + ESP_RETURN_ON_ERROR(spi_slave_initialize(s_spi_config->host_device, &s_spi_config->bus_config, + &s_spi_config->slave_config, SPI_DMA_CH_AUTO), OT_PLAT_LOG_TAG, "fail to initialize SPI slave"); return ESP_OK; @@ -96,9 +112,15 @@ esp_err_t esp_openthread_host_rcp_spi_init(const esp_openthread_platform_config_ void esp_openthread_spi_slave_deinit(void) { - spi_slave_free(s_spi_config.host_device); - s_spi_config.slave_config.post_setup_cb = NULL; - s_spi_config.slave_config.post_trans_cb = NULL; + spi_slave_free(s_spi_config->host_device); + s_spi_config->slave_config.post_setup_cb = NULL; + s_spi_config->slave_config.post_trans_cb = NULL; + heap_caps_free(s_spi_config); + heap_caps_free(s_spi_transaction); + heap_caps_free(s_pending_transaction); + s_spi_config = NULL; + s_spi_transaction = NULL; + s_pending_transaction = NULL; return; } @@ -115,43 +137,38 @@ otError IRAM_ATTR otPlatSpiSlavePrepareTransaction(uint8_t *aOutputBuf, uint16_t uint16_t aInputBufLen, bool aRequestTransactionFlag) { esp_err_t trans_state = ESP_OK; - pending_transaction_t *pending_transaction = NULL; - if (aOutputBuf == NULL) { - aOutputBuf = s_prev_output_buf; - aOutputBufLen = s_prev_output_len; + uint16_t trans_length = 0; + + if (aOutputBuf != NULL) { + s_output_buf = aOutputBuf; + s_output_len = aOutputBufLen; } - if (aInputBuf == NULL) { - aInputBuf = s_prev_input_buf; - aInputBufLen = s_prev_input_len; + if (aInputBuf != NULL) { + s_input_buf = aInputBuf; + s_input_len = aInputBufLen; } - s_prev_output_buf = aOutputBuf; - s_prev_output_len = aOutputBufLen; - s_prev_input_buf = aInputBuf; - s_prev_input_len = aInputBufLen; - - s_spi_transaction.length = aOutputBufLen > aInputBufLen ? aOutputBufLen : aInputBufLen; - s_spi_transaction.length *= CHAR_BIT; - s_spi_transaction.rx_buffer = aInputBuf; - s_spi_transaction.tx_buffer = aOutputBuf; - - assert(sizeof(s_spi_transaction.user) >= sizeof(pending_transaction_t)); - pending_transaction = (pending_transaction_t *)&(s_spi_transaction.user); - pending_transaction->input_buf_len = aInputBufLen; - pending_transaction->output_buf_len = aOutputBufLen; - s_spi_transaction.user = pending_transaction; - s_request_transaction = aRequestTransactionFlag; - if ((gpio_get_level(s_spi_config.slave_config.spics_io_num) == 0)) { + trans_length = s_output_len > s_input_len ? s_output_len : s_input_len; + trans_length *= CHAR_BIT; + if ((gpio_get_level(s_spi_config->slave_config.spics_io_num) == 0)) { ESP_EARLY_LOGE(SPI_SLAVE_TAG, "SPI busy"); return OT_ERROR_BUSY; } + s_spi_transaction->length = trans_length; + s_spi_transaction->rx_buffer = s_input_buf; + s_spi_transaction->tx_buffer = s_output_buf; + + pending_transaction_t *pending_transaction = (pending_transaction_t *)s_spi_transaction->user; + pending_transaction->input_buf_len = s_input_len; + pending_transaction->output_buf_len = s_output_len; + s_request_transaction = aRequestTransactionFlag; if (xPortCanYield()) { - spi_slave_queue_reset(s_spi_config.host_device); - trans_state = spi_slave_queue_trans(s_spi_config.host_device, &s_spi_transaction, 0); + spi_slave_queue_reset(s_spi_config->host_device); + trans_state = spi_slave_queue_trans(s_spi_config->host_device, s_spi_transaction, 0); } else { - spi_slave_queue_reset_isr(s_spi_config.host_device); - trans_state = spi_slave_queue_trans_isr(s_spi_config.host_device, &s_spi_transaction); + spi_slave_queue_reset_isr(s_spi_config->host_device); + trans_state = spi_slave_queue_trans_isr(s_spi_config->host_device, s_spi_transaction); } if (trans_state == ESP_OK) { diff --git a/components/openthread/src/port/esp_openthread_uart.c b/components/openthread/src/port/esp_openthread_uart.c index 9c8ef64cde6..cd5fe9d61cc 100644 --- a/components/openthread/src/port/esp_openthread_uart.c +++ b/components/openthread/src/port/esp_openthread_uart.c @@ -20,6 +20,7 @@ #include "esp_vfs_dev.h" #include "common/logging.hpp" #include "driver/uart.h" +#include "driver/uart_vfs.h" #include "utils/uart.h" #include "esp_vfs_usb_serial_jtag.h" #include "driver/usb_serial_jtag.h" @@ -68,7 +69,7 @@ esp_err_t esp_openthread_uart_init_port(const esp_openthread_uart_config_t *conf OT_PLAT_LOG_TAG, "uart_set_pin failed"); ESP_RETURN_ON_ERROR(uart_driver_install(config->port, ESP_OPENTHREAD_UART_BUFFER_SIZE, 0, 0, NULL, 0), OT_PLAT_LOG_TAG, "uart_driver_install failed"); - esp_vfs_dev_uart_use_driver(config->port); + uart_vfs_dev_use_driver(config->port); return ESP_OK; } @@ -90,7 +91,7 @@ esp_err_t esp_openthread_host_cli_usb_init(const esp_openthread_platform_config_ ret = usb_serial_jtag_driver_install((usb_serial_jtag_driver_config_t *)&config->host_config.host_usb_config); esp_vfs_usb_serial_jtag_use_driver(); - esp_vfs_dev_uart_register(); + uart_vfs_dev_register(); return ret; } #endif @@ -113,8 +114,8 @@ esp_err_t esp_openthread_host_rcp_uart_init(const esp_openthread_platform_config ESP_RETURN_ON_ERROR(esp_openthread_uart_init_port(&config->host_config.host_uart_config), OT_PLAT_LOG_TAG, "esp_openthread_uart_init_port failed"); - esp_vfs_dev_uart_port_set_rx_line_endings(s_uart_port, ESP_LINE_ENDINGS_LF); - esp_vfs_dev_uart_port_set_tx_line_endings(s_uart_port, ESP_LINE_ENDINGS_LF); + uart_vfs_dev_port_set_rx_line_endings(s_uart_port, ESP_LINE_ENDINGS_LF); + uart_vfs_dev_port_set_tx_line_endings(s_uart_port, ESP_LINE_ENDINGS_LF); snprintf(uart_path, sizeof(uart_path), "/dev/uart/%d", s_uart_port); s_uart_fd = open(uart_path, O_RDWR | O_NONBLOCK); ESP_RETURN_ON_FALSE(s_uart_fd >= 0, ESP_FAIL, OT_PLAT_LOG_TAG, "open uart_path failed"); diff --git a/components/openthread/src/port/esp_openthread_udp.c b/components/openthread/src/port/esp_openthread_udp.c index 08c8e12e6c8..852c0a920a0 100644 --- a/components/openthread/src/port/esp_openthread_udp.c +++ b/components/openthread/src/port/esp_openthread_udp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -57,6 +57,7 @@ typedef struct { TaskHandle_t source_task; struct udp_pcb *pcb; uint8_t netif_index; + esp_err_t err; } udp_bind_netif_task_t; typedef struct { @@ -255,7 +256,6 @@ otError otPlatUdpBind(otUdpSocket *udp_socket) static void udp_bind_netif_task(void *ctx) { udp_bind_netif_task_t *task = (udp_bind_netif_task_t *)ctx; - udp_bind_netif(task->pcb, netif_get_by_index(task->netif_index)); xTaskNotifyGive(task->source_task); } @@ -276,16 +276,20 @@ static uint8_t get_netif_index(otNetifIdentifier netif_identifier) otError otPlatUdpBindToNetif(otUdpSocket *udp_socket, otNetifIdentifier netif_identifier) { + otError err = OT_ERROR_NONE; udp_bind_netif_task_t task = { .source_task = xTaskGetCurrentTaskHandle(), .pcb = (struct udp_pcb *)udp_socket->mHandle, .netif_index = get_netif_index(netif_identifier), + .err = ESP_OK, }; tcpip_callback(udp_bind_netif_task, &task); wait_for_task_notification(); - - return OT_ERROR_NONE; + if (task.err != ESP_OK) { + err = OT_ERROR_FAILED; + } + return err; } static void udp_connect_task(void *ctx) @@ -424,14 +428,20 @@ otError otPlatUdpSend(otUdpSocket *udp_socket, otMessage *message, const otMessa static void udp_multicast_join_leave_task(void *ctx) { udp_multicast_join_leave_task_t *task = (udp_multicast_join_leave_task_t *)ctx; + struct netif *target = netif_get_by_index(task->netif_index); - if (task->is_join) { - if (mld6_joingroup_netif(netif_get_by_index(task->netif_index), &task->addr) != ERR_OK) { - ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to join multicast group"); - } + if (target == NULL) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to %s multicast group, index%d netif is not ready", + task->is_join ? "join" : "leave", task->netif_index); } else { - if (mld6_leavegroup_netif(netif_get_by_index(task->netif_index), &task->addr) != ERR_OK) { - ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to leave multicast group"); + if (task->is_join) { + if (mld6_joingroup_netif(target, &task->addr) != ERR_OK) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to join multicast group"); + } + } else { + if (mld6_leavegroup_netif(target, &task->addr) != ERR_OK) { + ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to leave multicast group"); + } } } free(task); diff --git a/components/openthread/src/port/esp_spi_spinel_interface.cpp b/components/openthread/src/port/esp_spi_spinel_interface.cpp index bc5cd7e52c4..b89eff6779f 100644 --- a/components/openthread/src/port/esp_spi_spinel_interface.cpp +++ b/components/openthread/src/port/esp_spi_spinel_interface.cpp @@ -25,17 +25,39 @@ using ot::Spinel::SpinelInterface; namespace esp { namespace openthread { -SpiSpinelInterface::SpiSpinelInterface(SpinelInterface::ReceiveFrameCallback callback, void *callback_context, - SpinelInterface::RxFrameBuffer &frame_buffer) +SpiSpinelInterface::SpiSpinelInterface(void) : m_event_fd(-1) - , m_receiver_frame_callback(callback) - , m_receiver_frame_context(callback_context) - , m_receive_frame_buffer(frame_buffer) + , m_receiver_frame_callback(nullptr) + , m_receiver_frame_context(nullptr) + , m_receive_frame_buffer(nullptr) , mRcpFailureHandler(nullptr) { } -esp_err_t SpiSpinelInterface::Init(const esp_openthread_spi_host_config_t &spi_config) +SpiSpinelInterface::~SpiSpinelInterface(void) +{ + Deinit(); +} + +otError SpiSpinelInterface::Init(ReceiveFrameCallback aCallback, void *aCallbackContext, RxFrameBuffer &aFrameBuffer) +{ + otError error = OT_ERROR_NONE; + + m_receiver_frame_callback = aCallback; + m_receiver_frame_context = aCallbackContext; + m_receive_frame_buffer = &aFrameBuffer; + + return error; +} + +void SpiSpinelInterface::Deinit(void) +{ + m_receiver_frame_callback = nullptr; + m_receiver_frame_context = nullptr; + m_receive_frame_buffer = nullptr; +} + +esp_err_t SpiSpinelInterface::Enable(const esp_openthread_spi_host_config_t &spi_config) { ESP_RETURN_ON_FALSE(m_event_fd < 0, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "event fd was initialized"); m_spi_config = spi_config; @@ -62,10 +84,16 @@ esp_err_t SpiSpinelInterface::Init(const esp_openthread_spi_host_config_t &spi_c ESP_LOGI(OT_PLAT_LOG_TAG, "spinel SPI interface initialization completed"); + return ESP_OK; +} + +esp_err_t SpiSpinelInterface::AfterRadioInit(void) +{ return ConductSPITransaction(true, 0, 0); } -esp_err_t SpiSpinelInterface::Deinit(void) + +esp_err_t SpiSpinelInterface::Disable(void) { if (m_event_fd >= 0) { close(m_event_fd); @@ -80,11 +108,6 @@ esp_err_t SpiSpinelInterface::Deinit(void) return ESP_OK; } -SpiSpinelInterface::~SpiSpinelInterface(void) -{ - Deinit(); -} - otError SpiSpinelInterface::SendFrame(const uint8_t *frame, uint16_t length) { ESP_RETURN_ON_FALSE(frame, OT_ERROR_INVALID_ARGS, OT_PLAT_LOG_TAG, "empty frame"); @@ -113,13 +136,13 @@ esp_err_t SpiSpinelInterface::ConductSPITransaction(bool reset, uint16_t tx_data tx_frame.SetHeaderAcceptLen(rx_data_size); uint8_t *rx_buffer; - otError err = m_receive_frame_buffer.SetSkipLength(kSPIFrameHeaderSize); + otError err = m_receive_frame_buffer->SetSkipLength(kSPIFrameHeaderSize); ESP_RETURN_ON_FALSE(err == OT_ERROR_NONE, ESP_ERR_NO_MEM, OT_PLAT_LOG_TAG, "buffer space is insufficient"); - rx_buffer = m_receive_frame_buffer.GetFrame() - kSPIFrameHeaderSize; - if (m_receive_frame_buffer.GetFrameMaxLength() < rx_data_size) { - rx_data_size = m_receive_frame_buffer.GetFrameMaxLength(); + rx_buffer = m_receive_frame_buffer->GetFrame() - kSPIFrameHeaderSize; + if (m_receive_frame_buffer->GetFrameMaxLength() < rx_data_size) { + rx_data_size = m_receive_frame_buffer->GetFrameMaxLength(); } uint16_t data_size = tx_data_size > rx_data_size ? tx_data_size : rx_data_size; data_size += kSPIFrameHeaderSize; @@ -143,7 +166,7 @@ esp_err_t SpiSpinelInterface::ConductSPITransaction(bool reset, uint16_t tx_data if (rx_frame.IsResetFlagSet()) { ESP_LOGW(OT_PLAT_LOG_TAG, "RCP Reset"); - m_receive_frame_buffer.DiscardFrame(); + m_receive_frame_buffer->DiscardFrame(); return ESP_OK; } if (rx_frame.GetHeaderDataLen() == 0 && rx_frame.GetHeaderAcceptLen() == 0) { @@ -156,16 +179,16 @@ esp_err_t SpiSpinelInterface::ConductSPITransaction(bool reset, uint16_t tx_data if (gpio_get_level(m_spi_config.intr_pin) == 1) { m_pending_data_len = 0; } - if (m_receive_frame_buffer.SetLength(rx_frame.GetHeaderDataLen()) != OT_ERROR_NONE) { + if (m_receive_frame_buffer->SetLength(rx_frame.GetHeaderDataLen()) != OT_ERROR_NONE) { ESP_LOGW(OT_PLAT_LOG_TAG, "insufficient buffer space to hold a frame of length %d...", rx_frame.GetHeaderDataLen()); - m_receive_frame_buffer.DiscardFrame(); + m_receive_frame_buffer->DiscardFrame(); return ESP_ERR_NO_MEM; } m_receiver_frame_callback(m_receiver_frame_context); } else { m_pending_data_len = 0; - m_receive_frame_buffer.DiscardFrame(); + m_receive_frame_buffer->DiscardFrame(); } m_pending_data_len = 0; @@ -180,26 +203,26 @@ void SpiSpinelInterface::GpioIntrHandler(void *arg) write(instance->m_event_fd, &event, sizeof(event)); } -void SpiSpinelInterface::Update(void *mainloop) +void SpiSpinelInterface::UpdateFdSet(void *aMainloopContext) { if (m_pending_data_len > 0) { - ((esp_openthread_mainloop_context_t *)mainloop)->timeout.tv_sec = 0; - ((esp_openthread_mainloop_context_t *)mainloop)->timeout.tv_usec = 0; + ((esp_openthread_mainloop_context_t *)aMainloopContext)->timeout.tv_sec = 0; + ((esp_openthread_mainloop_context_t *)aMainloopContext)->timeout.tv_usec = 0; } - FD_SET(m_event_fd, &((esp_openthread_mainloop_context_t *)mainloop)->read_fds); - FD_SET(m_event_fd, &((esp_openthread_mainloop_context_t *)mainloop)->error_fds); - if (m_event_fd > ((esp_openthread_mainloop_context_t *)mainloop)->max_fd) { - ((esp_openthread_mainloop_context_t *)mainloop)->max_fd = m_event_fd; + FD_SET(m_event_fd, &((esp_openthread_mainloop_context_t *)aMainloopContext)->read_fds); + FD_SET(m_event_fd, &((esp_openthread_mainloop_context_t *)aMainloopContext)->error_fds); + if (m_event_fd > ((esp_openthread_mainloop_context_t *)aMainloopContext)->max_fd) { + ((esp_openthread_mainloop_context_t *)aMainloopContext)->max_fd = m_event_fd; } } -void SpiSpinelInterface::Process(const void *mainloop) +void SpiSpinelInterface::Process(const void *aMainloopContext) { - if (FD_ISSET(m_event_fd, &((esp_openthread_mainloop_context_t *)mainloop)->error_fds)) { + if (FD_ISSET(m_event_fd, &((esp_openthread_mainloop_context_t *)aMainloopContext)->error_fds)) { ESP_LOGE(OT_PLAT_LOG_TAG, "SPI INTR GPIO error event"); return; } - if (FD_ISSET(m_event_fd, &((esp_openthread_mainloop_context_t *)mainloop)->read_fds)) { + if (FD_ISSET(m_event_fd, &((esp_openthread_mainloop_context_t *)aMainloopContext)->read_fds)) { uint64_t event; read(m_event_fd, &event, sizeof(event)); m_pending_data_len = SpinelInterface::kMaxFrameSize; @@ -249,5 +272,10 @@ otError SpiSpinelInterface::HardwareReset(void) return OT_ERROR_NONE; } +uint32_t SpiSpinelInterface::GetBusSpeed(void) const +{ + return m_spi_config.spi_device.clock_speed_hz; +} + } // namespace openthread } // namespace esp diff --git a/components/openthread/src/port/esp_uart_spinel_interface.cpp b/components/openthread/src/port/esp_uart_spinel_interface.cpp index fc32043ed1a..6e795b6f5f5 100644 --- a/components/openthread/src/port/esp_uart_spinel_interface.cpp +++ b/components/openthread/src/port/esp_uart_spinel_interface.cpp @@ -17,7 +17,7 @@ #include "esp_openthread_common_macro.h" #include "esp_openthread_types.h" #include "esp_openthread_uart.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "core/common/code_utils.hpp" #include "core/common/logging.hpp" #include "driver/uart.h" @@ -27,13 +27,10 @@ namespace esp { namespace openthread { -UartSpinelInterface::UartSpinelInterface(ot::Spinel::SpinelInterface::ReceiveFrameCallback callback, - void *callback_context, - ot::Spinel::SpinelInterface::RxFrameBuffer &frame_buffer) - : m_receiver_frame_callback(callback) - , m_receiver_frame_context(callback_context) - , m_receive_frame_buffer(frame_buffer) - , m_hdlc_decoder(frame_buffer, HandleHdlcFrame, this) +UartSpinelInterface::UartSpinelInterface(void) + : m_receiver_frame_callback(nullptr) + , m_receiver_frame_context(nullptr) + , m_receive_frame_buffer(nullptr) , m_uart_fd(-1) , mRcpFailureHandler(nullptr) { @@ -41,9 +38,29 @@ UartSpinelInterface::UartSpinelInterface(ot::Spinel::SpinelInterface::ReceiveFra UartSpinelInterface::~UartSpinelInterface(void) { + Deinit(); } -esp_err_t UartSpinelInterface::Init(const esp_openthread_uart_config_t &radio_uart_config) +otError UartSpinelInterface::Init(ReceiveFrameCallback aCallback, void *aCallbackContext, RxFrameBuffer &aFrameBuffer) +{ + otError error = OT_ERROR_NONE; + + m_receiver_frame_callback = aCallback; + m_receiver_frame_context = aCallbackContext; + m_receive_frame_buffer = &aFrameBuffer; + m_hdlc_decoder.Init(aFrameBuffer, HandleHdlcFrame, this); + + return error; +} + +void UartSpinelInterface::Deinit(void) +{ + m_receiver_frame_callback = nullptr; + m_receiver_frame_context = nullptr; + m_receive_frame_buffer = nullptr; +} + +esp_err_t UartSpinelInterface::Enable(const esp_openthread_uart_config_t &radio_uart_config) { esp_err_t error = ESP_OK; m_uart_rx_buffer = static_cast(heap_caps_malloc(kMaxFrameSize, MALLOC_CAP_8BIT)); @@ -56,7 +73,7 @@ esp_err_t UartSpinelInterface::Init(const esp_openthread_uart_config_t &radio_ua return error; } -esp_err_t UartSpinelInterface::Deinit(void) +esp_err_t UartSpinelInterface::Disable(void) { if (m_uart_rx_buffer) { heap_caps_free(m_uart_rx_buffer); @@ -88,24 +105,14 @@ otError UartSpinelInterface::SendFrame(const uint8_t *frame, uint16_t length) return error; } -void UartSpinelInterface::Process(const void *mainloop) +void UartSpinelInterface::Process(const void *aMainloopContext) { - if (FD_ISSET(m_uart_fd, &((esp_openthread_mainloop_context_t *)mainloop)->read_fds)) { + if (FD_ISSET(m_uart_fd, &((esp_openthread_mainloop_context_t *)aMainloopContext)->read_fds)) { ESP_LOGD(OT_PLAT_LOG_TAG, "radio uart read event"); TryReadAndDecode(); } } -void UartSpinelInterface::Update(void *mainloop) -{ - // Register only READ events for radio UART and always wait - // for a radio WRITE to complete. - FD_SET(m_uart_fd, &((esp_openthread_mainloop_context_t *)mainloop)->read_fds); - if (m_uart_fd > ((esp_openthread_mainloop_context_t *)mainloop)->max_fd) { - ((esp_openthread_mainloop_context_t *)mainloop)->max_fd = m_uart_fd; - } -} - int UartSpinelInterface::TryReadAndDecode(void) { uint8_t buffer[UART_HW_FIFO_LEN(m_uart_config.port)]; @@ -246,7 +253,7 @@ void UartSpinelInterface::HandleHdlcFrame(otError error) m_receiver_frame_callback(m_receiver_frame_context); } else { ESP_LOGE(OT_PLAT_LOG_TAG, "dropping radio frame: %s", otThreadErrorToString(error)); - m_receive_frame_buffer.DiscardFrame(); + m_receive_frame_buffer->DiscardFrame(); } } @@ -258,8 +265,8 @@ esp_err_t UartSpinelInterface::InitUart(const esp_openthread_uart_config_t &radi ESP_RETURN_ON_ERROR(esp_openthread_uart_init_port(&radio_uart_config), OT_PLAT_LOG_TAG, "esp_openthread_uart_init_port failed"); // We have a driver now installed so set up the read/write functions to use driver also. - esp_vfs_dev_uart_port_set_tx_line_endings(m_uart_config.port, ESP_LINE_ENDINGS_LF); - esp_vfs_dev_uart_port_set_rx_line_endings(m_uart_config.port, ESP_LINE_ENDINGS_LF); + uart_vfs_dev_port_set_tx_line_endings(m_uart_config.port, ESP_LINE_ENDINGS_LF); + uart_vfs_dev_port_set_rx_line_endings(m_uart_config.port, ESP_LINE_ENDINGS_LF); snprintf(uart_path, sizeof(uart_path), "/dev/uart/%d", radio_uart_config.port); m_uart_fd = open(uart_path, O_RDWR | O_NONBLOCK); @@ -294,5 +301,20 @@ otError UartSpinelInterface::HardwareReset(void) return OT_ERROR_NONE; } +void UartSpinelInterface::UpdateFdSet(void *aMainloopContext) +{ + // Register only READ events for radio UART and always wait + // for a radio WRITE to complete. + FD_SET(m_uart_fd, &((esp_openthread_mainloop_context_t *)aMainloopContext)->read_fds); + if (m_uart_fd > ((esp_openthread_mainloop_context_t *)aMainloopContext)->max_fd) { + ((esp_openthread_mainloop_context_t *)aMainloopContext)->max_fd = m_uart_fd; + } +} + +uint32_t UartSpinelInterface::GetBusSpeed(void) const +{ + return m_uart_config.uart_config.baud_rate; +} + } // namespace openthread } // namespace esp diff --git a/components/partition_table/gen_esp32part.py b/components/partition_table/gen_esp32part.py index 5e18a86ed07..cce5b78e916 100755 --- a/components/partition_table/gen_esp32part.py +++ b/components/partition_table/gen_esp32part.py @@ -98,14 +98,18 @@ def get_alignment_offset_for_type(ptype): def get_alignment_size_for_type(ptype): - if ptype == APP_TYPE and secure == SECURE_V1: - # For secure boot v1 case, app partition must be 64K aligned - # signature block (68 bytes) lies at the very end of 64K block - return 0x10000 - if ptype == APP_TYPE and secure == SECURE_V2: - # For secure boot v2 case, app partition must be 4K aligned - # signature block (4K) is kept after padding the unsigned image to 64K boundary - return 0x1000 + if ptype == APP_TYPE: + if secure == SECURE_V1: + # For secure boot v1 case, app partition must be 64K aligned + # signature block (68 bytes) lies at the very end of 64K block + return 0x10000 + elif secure == SECURE_V2: + # For secure boot v2 case, app partition must be 4K aligned + # signature block (4K) is kept after padding the unsigned image to 64K boundary + return 0x1000 + else: + # For no secure boot enabled case, app partition must be 4K aligned (min. flash erase size) + return 0x1000 # No specific size alignement requirement as such return 0x1 @@ -441,7 +445,7 @@ def verify(self): offset_align = get_alignment_offset_for_type(self.type) if self.offset % offset_align: raise ValidationError(self, 'Offset 0x%x is not aligned to 0x%x' % (self.offset, offset_align)) - if self.type == APP_TYPE and secure is not SECURE_NONE: + if self.type == APP_TYPE: size_align = get_alignment_size_for_type(self.type) if self.size % size_align: raise ValidationError(self, 'Size 0x%x is not aligned to 0x%x' % (self.size, size_align)) diff --git a/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py b/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py index 8eb109c571d..1fcd855e183 100755 --- a/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py +++ b/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py @@ -410,14 +410,13 @@ def test_check_secure_app_size(self): def rge(args): return self._run_genesp32(sample_csv, args) - # Valid test that would pass with the above partition table - partfile = tempfile.mktemp() - self.assertEqual(rge([partfile]), b'Parsing CSV input...\nVerifying table...') - os.remove(partfile) - # Failure case 1, incorrect ota_0 partition size + # Failure case 1, incorrect ota_1 partition size + self.assertEqual(rge(['-q']), + b'Partition ota_1 invalid: Size 0x100800 is not aligned to 0x1000') + # Failure case 2, incorrect ota_0 partition size self.assertEqual(rge(['-q', '--secure', 'v1']), b'Partition ota_0 invalid: Size 0x101000 is not aligned to 0x10000') - # Failure case 2, incorrect ota_1 partition size + # Failure case 3, incorrect ota_1 partition size with Secure Boot V2 self.assertEqual(rge(['-q', '--secure', 'v2']), b'Partition ota_1 invalid: Size 0x100800 is not aligned to 0x1000') diff --git a/components/protocomm/CMakeLists.txt b/components/protocomm/CMakeLists.txt index e74a13cf305..ab026e55c84 100644 --- a/components/protocomm/CMakeLists.txt +++ b/components/protocomm/CMakeLists.txt @@ -6,8 +6,9 @@ endif() set(include_dirs include/common include/security - include/transports) -set(priv_include_dirs proto-c src/common src/crypto/srp6a/include) + include/transports + include/crypto/srp6a) +set(priv_include_dirs proto-c src/common) set(srcs "src/common/protocomm.c" "proto-c/constants.pb-c.c" diff --git a/components/protocomm/include/crypto/srp6a/esp_srp.h b/components/protocomm/include/crypto/srp6a/esp_srp.h new file mode 100644 index 00000000000..b02d78a5b57 --- /dev/null +++ b/components/protocomm/include/crypto/srp6a/esp_srp.h @@ -0,0 +1,236 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp_srp.h + * @brief SRP-6a protocol implementation + * + * More information on protocol can be found: https://datatracker.ietf.org/doc/html/rfc5054 + * + * This implementation is used by security2 of wifi_provisioning and local control features. + * Details on how these protocols use this feature can be found here: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-reference/provisioning/provisioning.html#security-2-scheme + * + * Below is the example usage of the srp6a protocol in protocomm component, + * which can help understand the APIs better. + * + * Variables used: + * + * N, g: group parameters (prime and generator) + * s: salt + * B, b: server's public and private values + * A, a: client's public and private values + * I: user name (aka "identity") + * P: password + * v: verifier + * k: SRP-6 multiplier + * + * salt (s) is random of given length, 16 in our case, which along with username and password + * is used to generate verifier. + * + * x = SHA1(s | SHA1(I | ":" | P)) + * v = g^x % N + * + * Steps involved (From protocomm component usage): + * Step1. Client Hello (PhoneApp): + * a. Generate Key pair: + * a (cli_privkey) = 256 bit random value, + * A (cli_pubkey) = g^a. + * g - generator, N - large safe prime, All arithmetic operations are performed in ring of integers modulo N, + * thus all occurrences like y^z should be read as y^z modulo N. + * b. SessionCmd0 (cli_pubkey, username I) + * + * Step2. Device(ESP): + * a. Obtain Salt and verifier stored on ESP + * Salt s = 256 bit random value, + * Verifier v = g^× where x = H(s | I | P) + * b. Generate Key Pair + * b (dev_privkey) = 256 bit random value + * B(dev_pubkey) = k*v + g^b where k = H(N, g) + * c. Shared Key K = H(S) where, + * S = (A * v^u) ^ b + * u = H(A, B) + * d. SessionResp0(dev_pubkey B, dev_random) + * + * Step3. Client (PhoneApp) + * a. shared_key(K) = H(S) where, + * S = (B - k*v) ^ (a + ux), + * u = H(A, B), + * k = H(N, g), + * V = g^x, + * x = H(s | I | P). + * b. Verification token + * client proof M = H[H(N) XOR H(g) | H(I) | S | A | B | K] + * c. SessionCmd1(Client proof M1) + * + * Step4. Device (ESP): + * a. Verify client: + * device generates M1 = H[H(N) XOR H(g) | H(I) | S | A | B | K] + * device verifies this M1 with the M1 obtained from Client + * b. Verification token: Device generate device proof M2 = H(A, M, K) + * c. Initialization Vector(IV): + * dev_rand = gen_16byte_random) This random number is to be used for AES-GCM operation + * for encryption and decryption of the data using the shared secret + * d. SessionResp1 (DeviceProofM2, dev_rand) + * + * Step5. Client (PhoneApp) + * a. Verify Device + * Client calculates device proof M2 as M2 = H(A, M, K) + * verifies this M2 with M2 obtained from device + */ + +/** + * @brief Large prime+generator to be used for the algorithm + */ +typedef enum { + /* SRP specific: + * N = 3072 bit large safe prime, + * g = generator */ + ESP_NG_3072 = 0, +} esp_ng_type_t; + +/** + * @brief esp_srp handle as the result of `esp_srp_init` + * + * The handle is returned by `esp_srp_init` on successful init. It is then + * passed for subsequent API calls as an argument. `esp_srp_free` can be used to + * clean up the handle. After `esp_srp_free` the handle becomes invalid. + */ +typedef struct esp_srp_handle esp_srp_handle_t; + +/** + * @brief Initialize srp context for given NG type + * + * @param ng NG type given by `esp_ng_type_t` + * @return esp_srp_handle_t* srp handle + * + * @note the handle gets freed with `esp_srp_free` + */ +esp_srp_handle_t *esp_srp_init(esp_ng_type_t ng); + +/** + * @brief free esp_srp_context + * + * @param hd handle to be free + */ +void esp_srp_free(esp_srp_handle_t *hd); + +/** + * @brief Returns B (pub key) and salt. [Step2.b] + * + * @param hd esp_srp handle + * @param username Username not expected NULL terminated + * @param username_len Username length + * @param pass Password not expected to be NULL terminated + * @param pass_len Pasword length + * @param salt_len Salt length + * @param bytes_B Public Key returned + * @param len_B Length of the public key + * @param bytes_salt Salt bytes generated + * @return esp_err_t ESP_OK on success, appropriate error otherwise + * + * @note *bytes_B MUST NOT BE FREED BY THE CALLER + * @note *bytes_salt MUST NOT BE FREE BY THE CALLER + */ +esp_err_t esp_srp_srv_pubkey(esp_srp_handle_t *hd, const char *username, int username_len, + const char *pass, int pass_len, int salt_len, + char **bytes_B, int *len_B, char **bytes_salt); + +/** + * @brief Generate salt-verifier pair, given username, password and salt length + * + * @param[in] username username + * @param[in] username_len length of the username + * @param[in] pass password + * @param[in] pass_len length of the password + * @param[out] bytes_salt generated salt on successful generation, or NULL + * @param[in] salt_len salt length + * @param[out] verifier generated verifier on successful generation, or NULL + * @param[out] verifier_len length of the generated verifier + * @return esp_err_t ESP_OK on success, appropriate error otherwise + * + * @note if API has returned ESP_OK, salt and verifier generated need to be freed by caller + * @note Usually, username and password are not saved on the device. Rather salt and verifier are + * generated outside the device and are embedded. + * this covenience API can be used to generate salt and verifier on the fly for development use case. + * OR for devices which intentionally want to generate different password each time and can send it + * to the client securely. e.g., a device has a display and it shows the pin + */ +esp_err_t esp_srp_gen_salt_verifier(const char *username, int username_len, + const char *pass, int pass_len, + char **bytes_salt, int salt_len, + char **verifier, int *verifier_len); + +/** + * @brief Set the Salt and Verifier pre-generated for a given password. + * This should be used only if the actual password is not available. + * The public key can then be generated using esp_srp_srv_pubkey_from_salt_verifier() + * and not esp_srp_srv_pubkey() + * + * @param hd esp_srp_handle + * @param salt pre-generated salt bytes + * @param salt_len length of the salt bytes + * @param verifier pre-generated verifier + * @param verifier_len length of the verifier bytes + * @return esp_err_t ESP_OK on success, appropriate error otherwise + */ +esp_err_t esp_srp_set_salt_verifier(esp_srp_handle_t *hd, const char *salt, int salt_len, + const char *verifier, int verifier_len); + +/** + * @brief Returns B (pub key)[Step2.b] when the salt and verifier are set using esp_srp_set_salt_verifier() + * + * @param hd esp_srp handle + * @param bytes_B Key returned to the called + * @param len_B Length of the key returned + * @return esp_err_t ESP_OK on success, appropriate error otherwise + * + * @note *bytes_B MUST NOT BE FREED BY THE CALLER + */ +esp_err_t esp_srp_srv_pubkey_from_salt_verifier(esp_srp_handle_t *hd, char **bytes_B, int *len_B); + +/** + * @brief Get session key in `*bytes_key` given by len in `*len_key`. [Step2.c]. + * + * This calculated session key is used for further communication given the proofs are + * exchanged/authenticated with `esp_srp_exchange_proofs` + * + * @param hd esp_srp handle + * @param bytes_A Private Key + * @param len_A Private Key length + * @param bytes_key Key returned to the caller + * @param len_key length of the key in *bytes_key + * @return esp_err_t ESP_OK on success, appropriate error otherwise + * + * @note *bytes_key MUST NOT BE FREED BY THE CALLER + */ +esp_err_t esp_srp_get_session_key(esp_srp_handle_t *hd, char *bytes_A, int len_A, char **bytes_key, uint16_t *len_key); + +/** + * @brief Complete the authentication. If this step fails, the session_key exchanged should not be used + * + * This is the final authentication step in SRP algorithm [Step4.1, Step4.b, Step4.c] + * + * @param hd esp_srp handle + * @param username Username not expected NULL terminated + * @param username_len Username length + * @param bytes_user_proof param in + * @param bytes_host_proof parameter out (should be SHA512_DIGEST_LENGTH) bytes in size + * @return esp_err_t ESP_OK if user's proof is ok and subsequently bytes_host_proof is populated with our own proof. + */ +esp_err_t esp_srp_exchange_proofs(esp_srp_handle_t *hd, char *username, uint16_t username_len, + char *bytes_user_proof, char *bytes_host_proof); + +#ifdef __cplusplus +} +#endif diff --git a/components/protocomm/src/crypto/srp6a/esp_srp.c b/components/protocomm/src/crypto/srp6a/esp_srp.c index 36fbc083422..bf3dd25cc5b 100644 --- a/components/protocomm/src/crypto/srp6a/esp_srp.c +++ b/components/protocomm/src/crypto/srp6a/esp_srp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,44 @@ static const char *TAG = "srp6a"; +typedef struct esp_srp_handle { + esp_ng_type_t type; + esp_mpi_ctx_t *ctx; + + /* N + * the bytes_n simply points to the static array + */ + esp_mpi_t *n; + const char *bytes_n; + int len_n; + + /* g + * the bytes_g simply points to the static array + */ + esp_mpi_t *g; + const char *bytes_g; + int len_g; + + /* Salt */ + esp_mpi_t *s; + char *bytes_s; + int len_s; + /* Verifier */ + esp_mpi_t *v; + /* B */ + esp_mpi_t *B; + char *bytes_B; + int len_B; + /* b */ + esp_mpi_t *b; + /* A */ + esp_mpi_t *A; + char *bytes_A; + int len_A; + /* K - session key*/ + char *session_key; +} esp_srp_handle; + static void hexdump_mpi(const char *name, esp_mpi_t *bn) { int len = 0; @@ -59,15 +97,13 @@ static const char N_3072[] = { static const char g_3072[] = { 5 }; -esp_err_t esp_srp_init(esp_srp_handle_t *hd, esp_ng_type_t ng) +esp_srp_handle_t *esp_srp_init(esp_ng_type_t ng) { - if (hd->allocated) { - esp_srp_free(hd); + esp_srp_handle_t *hd = calloc(1, sizeof(esp_srp_handle)); + if (!hd) { + return NULL; } - memset(hd, 0, sizeof(*hd)); - hd->allocated = 1; - hd->ctx = esp_mpi_ctx_new(); if (! hd->ctx) { goto error; @@ -90,18 +126,17 @@ esp_err_t esp_srp_init(esp_srp_handle_t *hd, esp_ng_type_t ng) goto error; } hd->type = ng; - return ESP_OK; + return hd; error: esp_srp_free(hd); - return ESP_FAIL; + return NULL; } void esp_srp_free(esp_srp_handle_t *hd) { - if (hd->allocated != 1) { + if (!hd) { return; } - if (hd->ctx) { esp_mpi_ctx_free(hd->ctx); } @@ -138,7 +173,7 @@ void esp_srp_free(esp_srp_handle_t *hd) if (hd->session_key) { free(hd->session_key); } - memset(hd, 0, sizeof(*hd)); + free(hd); } static esp_mpi_t *calculate_x(char *bytes_salt, int salt_len, const char *username, int username_len, const char *pass, int pass_len) @@ -223,7 +258,7 @@ static esp_mpi_t *calculate_u(esp_srp_handle_t *hd, char *A, int len_A) return calculate_padded_hash(hd, A, len_A, hd->bytes_B, hd->len_B); } -esp_err_t __esp_srp_srv_pubkey(esp_srp_handle_t *hd, char **bytes_B, int *len_B) +static esp_err_t __esp_srp_srv_pubkey(esp_srp_handle_t *hd, char **bytes_B, int *len_B) { esp_mpi_t *k = calculate_k(hd); esp_mpi_t *kv = NULL; @@ -279,48 +314,85 @@ esp_err_t __esp_srp_srv_pubkey(esp_srp_handle_t *hd, char **bytes_B, int *len_B) return ESP_FAIL; } -esp_err_t esp_srp_srv_pubkey(esp_srp_handle_t *hd, const char *username, int username_len, const char *pass, int pass_len, int salt_len, - char **bytes_B, int *len_B, char **bytes_salt) +static esp_err_t _esp_srp_gen_salt_verifier(esp_srp_handle_t *hd, const char *username, int username_len, + const char *pass, int pass_len, int salt_len) { /* Get Salt */ int str_salt_len; esp_mpi_t *x = NULL; hd->s = esp_mpi_new(); - if (! hd->s) { + if (!hd->s) { + ESP_LOGE(TAG, "Failed to allocate bignum s"); goto error; } esp_mpi_get_rand(hd->s, 8 * salt_len, -1, 0); - *bytes_salt = esp_mpi_to_bin(hd->s, &str_salt_len); - if (! *bytes_salt) { + hd->bytes_s = esp_mpi_to_bin(hd->s, &str_salt_len); + if (!hd->bytes_s) { + ESP_LOGE(TAG, "Failed to generate salt of len %d", salt_len); goto error; } - hd->bytes_s = *bytes_salt; hd->len_s = salt_len; ESP_LOGD(TAG, "Salt ->"); - ESP_LOG_BUFFER_HEX_LEVEL(TAG, *bytes_salt, str_salt_len, ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEX_LEVEL(TAG, hd->bytes_s, str_salt_len, ESP_LOG_DEBUG); /* Calculate X which is simply a hash for all these things */ - x = calculate_x(*bytes_salt, str_salt_len, username, username_len, pass, pass_len); - if (! x) { + x = calculate_x(hd->bytes_s, str_salt_len, username, username_len, pass, pass_len); + if (!x) { + ESP_LOGE(TAG, "Failed to calculate x"); goto error; } hexdump_mpi("x", x); /* v = g^x % N */ hd->v = esp_mpi_new(); - if (! hd->v) { + if (!hd->v) { + ESP_LOGE(TAG, "Failed to allocate bignum v"); goto error; } esp_mpi_a_exp_b_mod_c(hd->v, hd->g, x, hd->n, hd->ctx); hexdump_mpi("Verifier", hd->v); - if (__esp_srp_srv_pubkey(hd, bytes_B, len_B) < 0 ) { + esp_mpi_free(x); + return ESP_OK; + +error: + if (hd->s) { + esp_mpi_free(hd->s); + hd->s = NULL; + } + if (hd->bytes_s) { + free(hd->bytes_s); + hd->bytes_s = NULL; + hd->len_s = 0; + } + if (x) { + esp_mpi_free(x); + x = NULL; + } + if (hd->v) { + esp_mpi_free(hd->v); + hd->v = NULL; + } + return ESP_FAIL; +} + +esp_err_t esp_srp_srv_pubkey(esp_srp_handle_t *hd, const char *username, int username_len, + const char *pass, int pass_len, int salt_len, + char **bytes_B, int *len_B, char **bytes_salt) +{ + if (!hd || !username || !pass) { + return ESP_ERR_INVALID_ARG; + } + if (ESP_OK != _esp_srp_gen_salt_verifier(hd, username, username_len, pass, pass_len, salt_len)) { goto error; } + *bytes_salt = hd->bytes_s; - esp_mpi_free(x); + if (__esp_srp_srv_pubkey(hd, bytes_B, len_B) < 0 ) { + goto error; + } return ESP_OK; error: @@ -334,10 +406,6 @@ esp_err_t esp_srp_srv_pubkey(esp_srp_handle_t *hd, const char *username, int use hd->bytes_s = NULL; hd->len_s = 0; } - if (x) { - esp_mpi_free(x); - x = NULL; - } if (hd->v) { esp_mpi_free(hd->v); hd->v = NULL; @@ -347,9 +415,49 @@ esp_err_t esp_srp_srv_pubkey(esp_srp_handle_t *hd, const char *username, int use esp_err_t esp_srp_srv_pubkey_from_salt_verifier(esp_srp_handle_t *hd, char **bytes_B, int *len_B) { + if (!hd || !bytes_B || !len_B) { + return ESP_ERR_INVALID_ARG; + } return __esp_srp_srv_pubkey(hd, bytes_B, len_B); } +/* Generate salt-verifier pair for given username and password */ +esp_err_t esp_srp_gen_salt_verifier(const char *username, int username_len, + const char *pass, int pass_len, + char **bytes_salt, int salt_len, + char **verifier, int *verifier_len) +{ + esp_err_t ret = ESP_FAIL; + + /* allocate and init temporary SRP handle */ + esp_srp_handle_t *srp_hd = esp_srp_init(ESP_NG_3072); + if (!srp_hd) { + ESP_LOGE(TAG, "Failed to initialise security context!"); + return ESP_ERR_NO_MEM; + } + + // get salt and verifier + if (ESP_OK != _esp_srp_gen_salt_verifier(srp_hd, username, username_len, pass, pass_len, salt_len)) { + goto cleanup; + } + + // convert to verifier bytes + *verifier = esp_mpi_to_bin(srp_hd->v, verifier_len); + if (!*verifier) { + ESP_LOGE(TAG, "Failed to allocate verifier bytes!"); + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + + *bytes_salt = srp_hd->bytes_s; + srp_hd->bytes_s = NULL; // so that it won't be freed in `esp_srp_free` step + ret = ESP_OK; + +cleanup: + esp_srp_free(srp_hd); + return ret; +} + esp_err_t esp_srp_set_salt_verifier(esp_srp_handle_t *hd, const char *salt, int salt_len, const char *verifier, int verifier_len) { diff --git a/components/protocomm/src/crypto/srp6a/include/esp_srp_mpi.h b/components/protocomm/src/crypto/srp6a/esp_srp_mpi.h similarity index 100% rename from components/protocomm/src/crypto/srp6a/include/esp_srp_mpi.h rename to components/protocomm/src/crypto/srp6a/esp_srp_mpi.h diff --git a/components/protocomm/src/crypto/srp6a/include/esp_srp.h b/components/protocomm/src/crypto/srp6a/include/esp_srp.h deleted file mode 100644 index 972704f038c..00000000000 --- a/components/protocomm/src/crypto/srp6a/include/esp_srp.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "esp_srp_mpi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - /* SRP specific: - * N = 3072 bit large safe prime, - * g = generator */ - ESP_NG_3072 = 0, -} esp_ng_type_t; - -typedef struct esp_srp_handle { - int allocated; - esp_ng_type_t type; - esp_mpi_ctx_t *ctx; - - /* N - * the bytes_n simply points to the static array - */ - esp_mpi_t *n; - const char *bytes_n; - int len_n; - - /* g - * the bytes_g simply points to the static array - */ - esp_mpi_t *g; - const char *bytes_g; - int len_g; - - /* Salt */ - esp_mpi_t *s; - char *bytes_s; - int len_s; - /* Verifier */ - esp_mpi_t *v; - /* B */ - esp_mpi_t *B; - char *bytes_B; - int len_B; - /* b */ - esp_mpi_t *b; - /* A */ - esp_mpi_t *A; - char *bytes_A; - int len_A; - /* K - session key*/ - char *session_key; -} esp_srp_handle_t; - -int esp_srp_init(esp_srp_handle_t *hd, esp_ng_type_t ng); - -void esp_srp_free(esp_srp_handle_t *hd); - -/* Returns B (pub key) and salt - * - * *bytes_B MUST NOT BE FREED BY THE CALLER - * *bytes_salt MUST NOT BE FREE BY THE CALLER - * - */ -esp_err_t esp_srp_srv_pubkey(esp_srp_handle_t *hd, const char *username, int username_len, const char *pass, int pass_len, int salt_len, - char **bytes_B, int *len_B, char **bytes_salt); - -/* Set the Salt and Verifier pre-generated for a given password. - * This should be used only if the actual password is not available. - * The public key can then be generated using esp_srp_srv_pubkey_from_salt_verifier() - * and not esp_srp_srv_pubkey() - */ -esp_err_t esp_srp_set_salt_verifier(esp_srp_handle_t *hd, const char *salt, int salt_len, - const char *verifier, int verifier_len); - -/* Returns B (pub key) when the salt and verifier are set using esp_srp_set_salt_verifier() - * - * *bytes_B MUST NOT BE FREED BY THE CALLER - */ -esp_err_t esp_srp_srv_pubkey_from_salt_verifier(esp_srp_handle_t *hd, char **bytes_B, int *len_B); - -/* Returns bytes_key - * *bytes_key MUST NOT BE FREED BY THE CALLER - */ -esp_err_t esp_srp_get_session_key(esp_srp_handle_t *hd, char *bytes_A, int len_A, char **bytes_key, uint16_t *len_key); - -/* Exchange proofs - * Returns 1 if user's proof is ok. Also 1 when is returned, bytes_host_proof contains our proof. - * - * bytes_user_proof is parameter in - * bytes_host_proof is parameter out (should be SHA512_DIGEST_LENGTH) bytes in size - */ -esp_err_t esp_srp_exchange_proofs(esp_srp_handle_t *hd, char *username, uint16_t username_len, char *bytes_user_proof, char *bytes_host_proof); - -#ifdef __cplusplus -} -#endif diff --git a/components/protocomm/src/security/security2.c b/components/protocomm/src/security/security2.c index 8256114ad7f..73d104d47c6 100644 --- a/components/protocomm/src/security/security2.c +++ b/components/protocomm/src/security/security2.c @@ -109,15 +109,9 @@ static esp_err_t handle_session_command0(session_t *cur_session, hexdump("Client Public Key", (char *) in->sc0->client_pubkey.data, PUBLIC_KEY_LEN); /* Initialize mu srp context */ - cur_session->srp_hd = calloc(1, sizeof(esp_srp_handle_t)); - if (!cur_session->srp_hd) { - ESP_LOGE(TAG, "Failed to allocate security context!"); - return ESP_ERR_NO_MEM; - } - - if (esp_srp_init(cur_session->srp_hd, ESP_NG_3072) != ESP_OK) { + cur_session->srp_hd = esp_srp_init(ESP_NG_3072); + if (cur_session->srp_hd == NULL) { ESP_LOGE(TAG, "Failed to initialise security context!"); - free(cur_session->srp_hd); return ESP_FAIL; } @@ -131,14 +125,15 @@ static esp_err_t handle_session_command0(session_t *cur_session, ESP_LOGI(TAG, "Using salt and verifier to generate public key..."); if (sv->salt != NULL && sv->salt_len != 0 && sv->verifier != NULL && sv->verifier_len != 0) { - if (esp_srp_set_salt_verifier(cur_session->srp_hd, cur_session->salt, cur_session->salt_len, cur_session->verifier, cur_session->verifier_len) != ESP_OK) { + if (esp_srp_set_salt_verifier(cur_session->srp_hd, cur_session->salt, + cur_session->salt_len, cur_session->verifier, cur_session->verifier_len) != ESP_OK) { ESP_LOGE(TAG, "Failed to set salt and verifier!"); - free(cur_session->srp_hd); + esp_srp_free(cur_session->srp_hd); return ESP_FAIL; } if (esp_srp_srv_pubkey_from_salt_verifier(cur_session->srp_hd, &device_pubkey, &device_pubkey_len) != ESP_OK) { ESP_LOGE(TAG, "Failed to device public key!"); - free(cur_session->srp_hd); + esp_srp_free(cur_session->srp_hd); return ESP_FAIL; } } @@ -147,7 +142,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, if (esp_srp_get_session_key(cur_session->srp_hd, (char *) in->sc0->client_pubkey.data, PUBLIC_KEY_LEN, &cur_session->session_key, &cur_session->session_key_len) != ESP_OK) { ESP_LOGE(TAG, "Failed to generate device session key!"); - free(cur_session->srp_hd); + esp_srp_free(cur_session->srp_hd); return ESP_FAIL; } hexdump("Session Key", cur_session->session_key, cur_session->session_key_len); @@ -156,7 +151,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, S2SessionResp0 *out_resp = (S2SessionResp0 *) malloc(sizeof(S2SessionResp0)); if (!out || !out_resp) { ESP_LOGE(TAG, "Error allocating memory for response0"); - free(cur_session->srp_hd); + esp_srp_free(cur_session->srp_hd); free(out); free(out_resp); return ESP_ERR_NO_MEM; @@ -185,7 +180,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, cur_session->username = malloc(cur_session->username_len); if (!cur_session->username) { ESP_LOGE(TAG, "Failed to allocate memory!"); - free(cur_session->srp_hd); + esp_srp_free(cur_session->srp_hd); return ESP_ERR_NO_MEM; } memcpy(cur_session->username, in->sc0->client_username.data, in->sc0->client_username.len); @@ -365,7 +360,6 @@ static esp_err_t sec2_close_session(protocomm_security_handle_t handle, uint32_t if (cur_session->srp_hd) { esp_srp_free(cur_session->srp_hd); - free(cur_session->srp_hd); } memset(cur_session, 0, sizeof(session_t)); diff --git a/components/riscv/include/esp_private/panic_reason.h b/components/riscv/include/esp_private/panic_reason.h index a89f5708f76..252f6de9c0b 100644 --- a/components/riscv/include/esp_private/panic_reason.h +++ b/components/riscv/include/esp_private/panic_reason.h @@ -18,3 +18,5 @@ #endif #define PANIC_RSN_CACHEERR 3 + +#define MCAUSE_ILLEGAL_INSTRUCTION 2 diff --git a/components/riscv/include/riscv/csr.h b/components/riscv/include/riscv/csr.h index ebbda1d2fe0..17e1f723e31 100644 --- a/components/riscv/include/riscv/csr.h +++ b/components/riscv/include/riscv/csr.h @@ -148,7 +148,8 @@ extern "C" { #define TDATA1_EXECUTE (1<<2) /*R/W,Fire trigger on instruction fetch address match*/ #define TDATA1_USER (1<<3) /*R/W,allow trigger to be fired in user mode*/ #define TDATA1_MACHINE (1<<6) /*R/W,Allow trigger to be fired while hart is executing in machine mode*/ -#define TDATA1_MATCH (1<<7) +#define TDATA1_MATCH_EXACT (0) +#define TDATA1_MATCH_NAPOT (1<<7) #define TDATA1_MATCH_V (0xF) /*R/W,Address match type :0 : Exact byte match 1 : NAPOT range match */ #define TDATA1_MATCH_S (7) #define TDATA1_HIT_S (20) diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index 92f493ed88a..9048f52785e 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -134,6 +134,9 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val) #if CONFIG_IDF_TARGET_ESP32P4 // As per CLIC specs, mintstatus CSR should be at 0xFB1, however esp32p4 implements it at 0x346 #define MINTSTATUS 0x346 +#elif CONFIG_IDF_TARGET_ESP32C5 + // TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from P4) Check the correctness + #define MINTSTATUS 0x346 #else #error "rv_utils_get_mintstatus() is not implemented. Check for correct mintstatus register address." #endif /* CONFIG_IDF_TARGET_ESP32P4 */ @@ -298,30 +301,32 @@ FORCE_INLINE_ATTR void rv_utils_set_watchpoint(int wp_num, RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE); RV_WRITE_CSR(tdata1, TDATA1_USER | TDATA1_MACHINE | - TDATA1_MATCH | + ((size == 1) ? TDATA1_MATCH_EXACT : TDATA1_MATCH_NAPOT) | (on_read ? TDATA1_LOAD : 0) | (on_write ? TDATA1_STORE : 0)); /* From RISC-V Debug Specification: - * NAPOT (Naturally Aligned Power-Of-Two): + * tdata1(mcontrol) match = 0 : Exact byte match + * + * tdata1(mcontrol) match = 1 : NAPOT (Naturally Aligned Power-Of-Two): * Matches when the top M bits of any compare value match the top M bits of tdata2. * M is XLEN − 1 minus the index of the least-significant bit containing 0 in tdata2. + * Note: Expecting that size is number power of 2 (numbers should be in the range of 1 ~ 31) * - * Note: Expectng that size is number power of 2 - * - * Examples for understanding how to calculate NAPOT: + * Examples for understanding how to calculate match pattern to tdata2: * + * nnnn...nnnnn 1-byte Exact byte match * nnnn...nnnn0 2-byte NAPOT range * nnnn...nnn01 4-byte NAPOT range * nnnn...nn011 8-byte NAPOT range * nnnn...n0111 16-byte NAPOT range * nnnn...01111 32-byte NAPOT range + * ... + * n011...11111 2^31 byte NAPOT range * * where n are bits from original address */ - const uint32_t half_size = size >> 1; - uint32_t napot = wp_addr; - napot &= ~half_size; /* set the least-significant bit with zero */ - napot |= half_size - 1; /* fill all bits with ones after least-significant bit */ - RV_WRITE_CSR(tdata2, napot); + uint32_t match_pattern = (wp_addr & ~(size-1)) | ((size-1) >> 1); + + RV_WRITE_CSR(tdata2, match_pattern); } FORCE_INLINE_ATTR void rv_utils_clear_breakpoint(int bp_num) diff --git a/components/riscv/vectors.S b/components/riscv/vectors.S index 58a248309f0..274c2962316 100644 --- a/components/riscv/vectors.S +++ b/components/riscv/vectors.S @@ -22,6 +22,14 @@ #if ( SOC_CPU_COPROC_NUM > 0 ) /* Targets with coprocessors present a special CSR to get Illegal Instruction exception reason */ .equ EXT_ILL_CSR, 0x7F0 + + /* EXT_ILL CSR reasons are stored as follows: + * - Bit 0: FPU core instruction (Load/Store instructions NOT concerned) + * - Bit 1: Low-power core + * - Bit 2: PIE core */ + .equ EXT_ILL_RSN_FPU, 1 + .equ EXT_ILL_RSN_LP, 2 + .equ EXT_ILL_RSN_PIE, 4 #endif /* SOC_CPU_COPROC_NUM > 0 */ /* Macro which first allocates space on the stack to save general @@ -157,10 +165,16 @@ _panic_handler: bne s0, a1, _panic_handler_not_coproc /* In case this is due to a coprocessor, set ra right now to simplify the logic below */ la ra, _return_from_exception - /* EXT_ILL CSR should contain the reason for the Illegal Instruction. */ + /* EXT_ILL CSR should contain the reason for the Illegal Instruction */ csrr a0, EXT_ILL_CSR - bnez a0, _panic_handler_coproc -#if SOC_CPU_HAS_FPU_EXT_ILL_BUG && SOC_CPU_HAS_FPU + mv a2, a0 + /* Check if the FPU bit is set. When targets have the FPU reason bug (SOC_CPU_HAS_FPU_EXT_ILL_BUG), + * it is possible that another bit is set even if the reason is an FPU instruction. + * For example, bit 1 can be set and bit 0 won't, even if the reason is an FPU instruction. */ +#if SOC_CPU_HAS_FPU + andi a1, a0, EXT_ILL_RSN_FPU + bnez a1, rtos_save_fpu_coproc +#if SOC_CPU_HAS_FPU_EXT_ILL_BUG /* If the SOC present the hardware EXT_ILL CSR bug, it doesn't support FPU load/store detection * so we have to check the instruction's opcode (in `mtval` = `t0`) */ andi a0, t0, 0b1011111 @@ -173,21 +187,25 @@ _panic_handler: and a0, t0, a0 /* a0 = mtval & 0x6001 */ li a1, 0x6000 beq a0, a1, rtos_save_fpu_coproc + /* Check if the instruction is CSR-related */ + andi a0, t0, 0b1111111 + li a1, 0b1110011 + bne a0, a1, _panic_handler_not_fpu + /* Check if it's CSR number 1 (fflags), 2 (frm) or 3 (fcsr) */ + srli a0, t0, 20 + addi a0, a0, -1 + li a1, 3 + bltu a0, a1, rtos_save_fpu_coproc /* The instruction was not an FPU one, continue the exception */ -#endif /* SOC_CPU_HAS_FPU_EXT_ILL_BUG && SOC_CPU_HAS_FPU */ - j _panic_handler_not_coproc -_panic_handler_coproc: - /* EXT_ILL CSR reasons are stored as follows: - * - Bit 0: FPU core instruction (Load/Store instructions NOT concerned) - * - Bit 1: Low-power core - * - Bit 2: PIE core - */ -#if SOC_CPU_HAS_FPU - li a1, 1 - beq a0, a1, rtos_save_fpu_coproc +_panic_handler_not_fpu: + +#endif /* SOC_CPU_HAS_FPU_EXT_ILL_BUG */ #endif /* SOC_CPU_HAS_FPU */ + + /* Need to check the other coprocessors reason now, instruction is in register a2 */ /* Ignore LP and PIE for now, continue the exception */ _panic_handler_not_coproc: + #endif /* ( SOC_CPU_COPROC_NUM > 0 ) */ /* Call panic_from_exception(sp) or panic_from_isr(sp) diff --git a/components/sdmmc/CMakeLists.txt b/components/sdmmc/CMakeLists.txt index 0b65cf19b5d..243b26c4d60 100644 --- a/components/sdmmc/CMakeLists.txt +++ b/components/sdmmc/CMakeLists.txt @@ -11,5 +11,4 @@ idf_component_register(SRCS "sdmmc_cmd.c" "sdmmc_mmc.c" "sdmmc_sd.c" INCLUDE_DIRS include - REQUIRES driver PRIV_REQUIRES soc esp_timer) diff --git a/components/sdmmc/README.md b/components/sdmmc/README.md new file mode 100644 index 00000000000..7e18e31dd09 --- /dev/null +++ b/components/sdmmc/README.md @@ -0,0 +1,35 @@ +# SDMMC Protocol Layer Driver + +## SD Host Side Related Component Architecture + +### Architecture Graph + + ┌─────────────────────────────────────────────┐ + │ │ + │ SD Protocol Layer Driver: components/sdmmc │ + │ │ + └──────────▲────────────────────▲─────────────┘ + │ │ + │ │ + Implements │ │ Implements + │ │ + ┌──────────────────────────────────┴─────┐ ┌────┴───────────────────────────────────┐ + │ │ │ │ + │Host Driver: components/esp_driver_sdmmc│ │Host Driver: components/esp_driver_sdspi│ + │ │ │ │ + └────────────────────────────────────────┘ └────────────────────────────────────────┘ + +### Components + +- `sdmmc`: SD protocol layer driver, it provides SD protocol related definitions and interfaces. With corresponding implementation drivers, `sdmmc` APIs can help you: + - send commands to slave devices + - send and receive data + - handle error conditions within the bus +- `esp_driver_sdmmc`: SDMMC Host driver for ESP SDMMC hardware, it implements the `sdmmc` protocol interfaces. +- `esp_driver_sdspi`: SDSPI Host driver for ESP GPSPI hardware, it implements the `sdmmc` protocol interfaces. + +### Dependency + +- `esp_driver_sdmmc` is in driver layer (G2), it relies on `sdmmc` +- `esp_driver_sdspi` is in driver layer (G2), it relies on `sdmmc` +- `sdmmc` does not and should not rely on `esp_driver_sdmmc` or `esp_driver_sdspi`. Though `sdmmc` is independent, it still stays in G2. diff --git a/components/driver/sdmmc/include/driver/sdmmc_defs.h b/components/sdmmc/include/sd_protocol_defs.h similarity index 99% rename from components/driver/sdmmc/include/driver/sdmmc_defs.h rename to components/sdmmc/include/sd_protocol_defs.h index 56cff2407eb..a1b6a8ec022 100644 --- a/components/driver/sdmmc/include/driver/sdmmc_defs.h +++ b/components/sdmmc/include/sd_protocol_defs.h @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: ISC * - * SPDX-FileContributor: 2016-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2016-2023 Espressif Systems (Shanghai) CO LTD */ /* * Copyright (c) 2006 Uwe Stuehler @@ -75,7 +75,6 @@ extern "C" { #define SD_IO_RW_DIRECT 52 /* R5 */ #define SD_IO_RW_EXTENDED 53 /* R5 */ - /* OCR bits */ #define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */ #define MMC_OCR_ACCESS_MODE_MASK 0x60000000 /* bits 30:29 */ @@ -528,7 +527,6 @@ static inline uint32_t MMC_RSP_BITS(uint32_t *src, int start, int len) #define CISTPL_CODE_SDIO_EXT 0x92 #define CISTPL_CODE_END 0xFF - /* Timing */ #define SDMMC_TIMING_LEGACY 0 #define SDMMC_TIMING_HIGHSPEED 1 diff --git a/components/driver/sdmmc/include/driver/sdmmc_types.h b/components/sdmmc/include/sd_protocol_types.h similarity index 94% rename from components/driver/sdmmc/include/driver/sdmmc_types.h rename to components/sdmmc/include/sd_protocol_types.h index 6804ffbf7b6..61af3f80378 100644 --- a/components/driver/sdmmc/include/driver/sdmmc_types.h +++ b/components/sdmmc/include/sd_protocol_types.h @@ -110,15 +110,15 @@ typedef struct { * SD/MMC command information */ typedef struct { - uint32_t opcode; /*!< SD or MMC command index */ - uint32_t arg; /*!< SD/MMC command argument */ - sdmmc_response_t response; /*!< response buffer */ - void* data; /*!< buffer to send or read into */ - size_t datalen; /*!< length of data in the buffer */ - size_t buflen; /*!< length of the buffer */ - size_t blklen; /*!< block length */ - int flags; /*!< see below */ -/** @cond */ + uint32_t opcode; /*!< SD or MMC command index */ + uint32_t arg; /*!< SD/MMC command argument */ + sdmmc_response_t response; /*!< response buffer */ + void* data; /*!< buffer to send or read into */ + size_t datalen; /*!< length of data in the buffer */ + size_t buflen; /*!< length of the buffer */ + size_t blklen; /*!< block length */ + int flags; /*!< see below */ + /** @cond */ #define SCF_ITSDONE 0x0001 /*!< command is complete */ #define SCF_CMD(flags) ((flags) & 0x00f0) #define SCF_CMD_AC 0x0000 @@ -131,7 +131,7 @@ typedef struct { #define SCF_RSP_CRC 0x0400 #define SCF_RSP_IDX 0x0800 #define SCF_RSP_PRESENT 0x1000 -/* response types */ + /* response types */ #define SCF_RSP_R0 0 /*!< none */ #define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) #define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) @@ -142,11 +142,11 @@ typedef struct { #define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) #define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) #define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) -/* special flags */ + /* special flags */ #define SCF_WAIT_BUSY 0x2000 /*!< Wait for completion of card busy signal before returning */ -/** @endcond */ - esp_err_t error; /*!< error returned from transfer */ - uint32_t timeout_ms; /*!< response timeout, in milliseconds */ + /** @endcond */ + esp_err_t error; /*!< error returned from transfer */ + uint32_t timeout_ms; /*!< response timeout, in milliseconds */ } sdmmc_command_t; /** diff --git a/components/sdmmc/include/sdmmc_cmd.h b/components/sdmmc/include/sdmmc_cmd.h index 3b156826550..96889fbf993 100644 --- a/components/sdmmc/include/sdmmc_cmd.h +++ b/components/sdmmc/include/sdmmc_cmd.h @@ -8,7 +8,7 @@ #include #include "esp_err.h" -#include "driver/sdmmc_types.h" +#include "sd_protocol_types.h" #ifdef __cplusplus extern "C" { diff --git a/components/sdmmc/sdmmc_common.h b/components/sdmmc/sdmmc_common.h index ac4923a0371..f48f2cf0ccd 100644 --- a/components/sdmmc/sdmmc_common.h +++ b/components/sdmmc/sdmmc_common.h @@ -21,8 +21,8 @@ #include "esp_heap_caps.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "driver/sdmmc_defs.h" -#include "driver/sdmmc_types.h" +#include "sd_protocol_defs.h" +#include "sd_protocol_types.h" #include "sdmmc_cmd.h" #include "sys/param.h" #include "soc/soc_memory_layout.h" diff --git a/components/sdmmc/test/CMakeLists.txt b/components/sdmmc/test/CMakeLists.txt deleted file mode 100644 index 0648951eec3..00000000000 --- a/components/sdmmc/test/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock sdmmc test_utils - ) diff --git a/components/sdmmc/test/test_sd.c b/components/sdmmc/test/test_sd.c deleted file mode 100644 index 775777d7aa2..00000000000 --- a/components/sdmmc/test/test_sd.c +++ /dev/null @@ -1,1266 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include "sdkconfig.h" -#include "unity.h" -#include "driver/gpio.h" -#include "soc/soc_caps.h" -#if SOC_SDMMC_HOST_SUPPORTED -#include "driver/sdmmc_host.h" -#endif -#include "driver/sdspi_host.h" -#include "driver/sdmmc_defs.h" -#include "sdmmc_cmd.h" -#include "esp_log.h" -#include "esp_heap_caps.h" -#include "esp_rom_gpio.h" -#include "test_utils.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "soc/gpio_sig_map.h" -#include "soc/gpio_reg.h" - -// Currently no runners for S3 -#define WITH_SD_TEST (SOC_SDMMC_HOST_SUPPORTED && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)) -// Currently, no runners for S3, C2, and C6 -#define WITH_SDSPI_TEST (!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C2, ESP32C6, ESP32H2)) -// Can't test eMMC (slot 0) and PSRAM together -#define WITH_EMMC_TEST (SOC_SDMMC_HOST_SUPPORTED && !CONFIG_SPIRAM && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)) - -/* power supply enable pin */ -#define SD_TEST_BOARD_VSEL_EN_GPIO 27 - -/* power supply voltage select pin */ -#define SD_TEST_BOARD_VSEL_GPIO 26 -#define SD_TEST_BOARD_VSEL_3V3 1 -#define SD_TEST_BOARD_VSEL_1V8 0 - -/* time to wait for reset / power-on */ -#define SD_TEST_BOARD_PWR_RST_DELAY_MS 5 -#define SD_TEST_BOARD_PWR_ON_DELAY_MS 50 - -/* gpio which is not connected to actual CD pin, used to simulate CD behavior */ -#define CD_WP_TEST_GPIO 18 - -/* default GPIO selection */ -#ifdef CONFIG_IDF_TARGET_ESP32S2 -#define SDSPI_TEST_MOSI_PIN GPIO_NUM_35 -#define SDSPI_TEST_MISO_PIN GPIO_NUM_37 -#define SDSPI_TEST_SCLK_PIN GPIO_NUM_36 -#define SDSPI_TEST_CS_PIN GPIO_NUM_34 -#elif defined(CONFIG_IDF_TARGET_ESP32C3) -#define SDSPI_TEST_MOSI_PIN GPIO_NUM_4 -#define SDSPI_TEST_MISO_PIN GPIO_NUM_6 -#define SDSPI_TEST_SCLK_PIN GPIO_NUM_5 -#define SDSPI_TEST_CS_PIN GPIO_NUM_1 -#else -#define SDSPI_TEST_MOSI_PIN GPIO_NUM_15 -#define SDSPI_TEST_MISO_PIN GPIO_NUM_2 -#define SDSPI_TEST_SCLK_PIN GPIO_NUM_14 -#define SDSPI_TEST_CS_PIN GPIO_NUM_13 -#endif - -#define GPIO_ACTIVE_LOW 0 -#define GPIO_ACTIVE_HIGH 1 - -TEST_CASE("MMC_RSP_BITS", "[sd]") -{ - uint32_t data[2] = { 0x01234567, 0x89abcdef }; - TEST_ASSERT_EQUAL_HEX32(0x7, MMC_RSP_BITS(data, 0, 4)); - TEST_ASSERT_EQUAL_HEX32(0x567, MMC_RSP_BITS(data, 0, 12)); - TEST_ASSERT_EQUAL_HEX32(0xf0, MMC_RSP_BITS(data, 28, 8)); - TEST_ASSERT_EQUAL_HEX32(0x3, MMC_RSP_BITS(data, 1, 3)); - TEST_ASSERT_EQUAL_HEX32(0x11, MMC_RSP_BITS(data, 59, 5)); -} - -#if WITH_SD_TEST || WITH_EMMC_TEST -static void sd_test_board_power_on(void) -{ - gpio_set_direction(SD_TEST_BOARD_VSEL_GPIO, GPIO_MODE_OUTPUT); - gpio_set_level(SD_TEST_BOARD_VSEL_GPIO, SD_TEST_BOARD_VSEL_3V3); - gpio_set_direction(SD_TEST_BOARD_VSEL_EN_GPIO, GPIO_MODE_OUTPUT); - gpio_set_level(SD_TEST_BOARD_VSEL_EN_GPIO, 0); - usleep(SD_TEST_BOARD_PWR_RST_DELAY_MS * 1000); - gpio_set_level(SD_TEST_BOARD_VSEL_EN_GPIO, 1); - usleep(SD_TEST_BOARD_PWR_ON_DELAY_MS * 1000); -} - -static void sd_test_board_power_off(void) -{ - gpio_set_level(SD_TEST_BOARD_VSEL_EN_GPIO, 0); - gpio_set_direction(SD_TEST_BOARD_VSEL_GPIO, GPIO_MODE_INPUT); - gpio_set_level(SD_TEST_BOARD_VSEL_GPIO, 0); - gpio_set_direction(SD_TEST_BOARD_VSEL_EN_GPIO, GPIO_MODE_INPUT); -} - -static void probe_sd(int slot, int width, int freq_khz, int ddr) -{ - sd_test_board_power_on(); - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - config.slot = slot; - config.max_freq_khz = freq_khz; - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - if (width == 1) { - config.flags = SDMMC_HOST_FLAG_1BIT; - slot_config.width = 1; - } else if (width == 4) { - config.flags &= ~SDMMC_HOST_FLAG_8BIT; - slot_config.width = 4; - } else { - assert(!ddr && "host driver does not support 8-line DDR mode yet"); - } - if (!ddr) { - config.flags &= ~SDMMC_HOST_FLAG_DDR; - } - TEST_ESP_OK(sdmmc_host_init()); - TEST_ESP_OK(sdmmc_host_init_slot(slot, &slot_config)); - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - sdmmc_card_print_info(stdout, card); - uint8_t* buffer = heap_caps_malloc(512, MALLOC_CAP_DMA); - TEST_ESP_OK(sdmmc_read_sectors(card, buffer, 0, 1)); - free(buffer); - TEST_ESP_OK(sdmmc_host_deinit()); - free(card); - sd_test_board_power_off(); -} - -extern void sdmmc_host_get_clk_dividers(const int freq_khz, int *host_div, int *card_div); - -static void sd_test_check_clk_dividers(const int freq_khz, const int expected_host_div, const int expected_card_div) -{ - printf(" %6d | %2d | %2d\n", freq_khz, expected_host_div, expected_card_div); - int host_divider, card_divider; - sdmmc_host_get_clk_dividers(freq_khz, &host_divider, &card_divider); - TEST_ASSERT_EQUAL(host_divider, expected_host_div); - TEST_ASSERT_EQUAL(card_divider, expected_card_div); -} -#endif //WITH_SD_TEST || WITH_EMMC_TEST - -#if WITH_SD_TEST -TEST_CASE("probe SD, slot 1, 4-bit", "[sd][test_env=UT_T1_SDMODE]") -{ - probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_PROBING, 0); - probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_DEFAULT, 0); - probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_HIGHSPEED, 0); - //custom frequency test - probe_sd(SDMMC_HOST_SLOT_1, 4, 10000, 0); -} - -TEST_CASE("probe SD, slot 1, 1-bit", "[sd][test_env=UT_T1_SDMODE]") -{ - probe_sd(SDMMC_HOST_SLOT_1, 1, SDMMC_FREQ_PROBING, 0); - probe_sd(SDMMC_HOST_SLOT_1, 1, SDMMC_FREQ_DEFAULT, 0); - probe_sd(SDMMC_HOST_SLOT_1, 1, SDMMC_FREQ_HIGHSPEED, 0); -} - -//No runners for slot 0 -TEST_CASE("probe SD, slot 0, 4-bit", "[sd][ignore]") -{ - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_PROBING, 0); - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_DEFAULT, 0); - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_HIGHSPEED, 0); -} - -TEST_CASE("probe SD, slot 0, 1-bit", "[sd][ignore]") -{ - probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_PROBING, 0); - probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_DEFAULT, 0); - probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, 0); -} - -TEST_CASE("SD clock dividers calculation", "[sd][test_env=UT_T1_SDMODE]") -{ - printf("Frequency (kHz) | Expected host.div | Expected card.div\n"); - sd_test_check_clk_dividers(SDMMC_FREQ_PROBING, 10, 20); - sd_test_check_clk_dividers(SDMMC_FREQ_DEFAULT, 8, 0); - sd_test_check_clk_dividers(SDMMC_FREQ_HIGHSPEED, 4, 0); - sd_test_check_clk_dividers(36000, 5, 0); - sd_test_check_clk_dividers(30000, 6, 0); - sd_test_check_clk_dividers(16000, 10, 0); - sd_test_check_clk_dividers(10000, 2, 4); - sd_test_check_clk_dividers(6000, 2, 7); - sd_test_check_clk_dividers(1000, 2, 40); - sd_test_check_clk_dividers(600, 2, 67); -} -#endif //WITH_SD_TEST - -#if WITH_EMMC_TEST -TEST_CASE("probe eMMC, slot 0, 4-bit", "[sd][test_env=EMMC][ignore]") -{ - //Test with SDR - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_PROBING, 0); - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_DEFAULT, 0); - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_HIGHSPEED, 0); - //Test with DDR - probe_sd(SDMMC_HOST_SLOT_0, 4, SDMMC_FREQ_HIGHSPEED, 1); -} - -TEST_CASE("probe eMMC, slot 0, 8-bit", "[sd][test_env=EMMC][ignore]") -{ - //8-bit DDR not supported yet, test with SDR only - probe_sd(SDMMC_HOST_SLOT_0, 8, SDMMC_FREQ_PROBING, 0); - probe_sd(SDMMC_HOST_SLOT_0, 8, SDMMC_FREQ_DEFAULT, 0); - probe_sd(SDMMC_HOST_SLOT_0, 8, SDMMC_FREQ_HIGHSPEED, 0); -} -#endif // WITH_EMMC_TEST - -#if WITH_SDSPI_TEST - -#if !WITH_SD_TEST && !WITH_EMMC_TEST -static void sd_test_board_power_on(void) -{ - // do nothing -} - -static void sd_test_board_power_off(void) -{ - // do nothing -} -#endif - -static void test_sdspi_init_bus(spi_host_device_t host, int mosi_pin, int miso_pin, int clk_pin, int dma_chan) -{ - spi_bus_config_t bus_config = { - .mosi_io_num = mosi_pin, - .miso_io_num = miso_pin, - .sclk_io_num = clk_pin, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - esp_err_t err = spi_bus_initialize(host, &bus_config, dma_chan); - TEST_ESP_OK(err); -} - -static void test_sdspi_deinit_bus(spi_host_device_t host) -{ - esp_err_t err = spi_bus_free(host); - TEST_ESP_OK(err); -} - -static void probe_core(int slot, int freq_khz) -{ - sdmmc_host_t config = SDSPI_HOST_DEFAULT(); - config.slot = slot; - config.max_freq_khz = freq_khz; - - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - - TEST_ESP_OK(sdmmc_card_init(&config, card)); - sdmmc_card_print_info(stdout, card); - free(card); -} - -static void probe_spi(int freq_khz, int pin_miso, int pin_mosi, int pin_sck, int pin_cs) -{ - sd_test_board_power_on(); - - sdspi_dev_handle_t handle; - sdspi_device_config_t dev_config = SDSPI_DEVICE_CONFIG_DEFAULT(); - dev_config.gpio_cs = pin_cs; - test_sdspi_init_bus(dev_config.host_id, pin_mosi, pin_miso, pin_sck, SPI_DMA_CH_AUTO); - TEST_ESP_OK(sdspi_host_init()); - TEST_ESP_OK(sdspi_host_init_device(&dev_config, &handle)); - - probe_core(handle, freq_khz); - - TEST_ESP_OK(sdspi_host_deinit()); - test_sdspi_deinit_bus(dev_config.host_id); - sd_test_board_power_off(); -} - - -TEST_CASE("probe SD in SPI mode", "[sd][test_env=UT_T1_SPIMODE]") -{ - probe_spi(SDMMC_FREQ_DEFAULT, SDSPI_TEST_MISO_PIN, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_SCLK_PIN, SDSPI_TEST_CS_PIN); - //custom frequency test - probe_spi(10000, SDSPI_TEST_MISO_PIN, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_SCLK_PIN, SDSPI_TEST_CS_PIN); -} - -// No runner for this -TEST_CASE("probe SD in SPI mode, slot 0", "[sd][ignore]") -{ - probe_spi(SDMMC_FREQ_DEFAULT, 7, 11, 6, 10); -} -#endif //WITH_SDSPI_TEST - -#if WITH_SD_TEST || WITH_SDSPI_TEST || WITH_EMMC_TEST -// Fill buffer pointed to by 'dst' with 'count' 32-bit ints generated -// from 'rand' with the starting value of 'seed' -static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) { - srand(seed); - for (size_t i = 0; i < count; ++i) { - uint32_t val = rand(); - memcpy(dst + i * sizeof(uint32_t), &val, sizeof(val)); - } -} - -// Check if the buffer pointed to by 'dst' contains 'count' 32-bit -// ints generated from 'rand' with the starting value of 'seed' -static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) { - srand(seed); - for (size_t i = 0; i < count; ++i) { - uint32_t val; - memcpy(&val, src + i * sizeof(uint32_t), sizeof(val)); - TEST_ASSERT_EQUAL_HEX32(rand(), val); - } -} - -static void do_single_write_read_test(sdmmc_card_t* card, size_t start_block, - size_t block_count, size_t alignment, bool performance_log) -{ - size_t block_size = card->csd.sector_size; - size_t total_size = block_size * block_count; - printf(" %8d | %3d | %d | %4.1f ", start_block, block_count, alignment, total_size / 1024.0f); - - uint32_t* buffer = heap_caps_malloc(total_size + 4, MALLOC_CAP_DMA); - size_t offset = alignment % 4; - uint8_t* c_buffer = (uint8_t*) buffer + offset; - fill_buffer(start_block, c_buffer, total_size / sizeof(buffer[0])); - - struct timeval t_start_wr; - gettimeofday(&t_start_wr, NULL); - TEST_ESP_OK(sdmmc_write_sectors(card, c_buffer, start_block, block_count)); - struct timeval t_stop_wr; - gettimeofday(&t_stop_wr, NULL); - float time_wr = 1e3f * (t_stop_wr.tv_sec - t_start_wr.tv_sec) + 1e-3f * (t_stop_wr.tv_usec - t_start_wr.tv_usec); - - memset(buffer, 0xbb, total_size + 4); - - struct timeval t_start_rd; - gettimeofday(&t_start_rd, NULL); - TEST_ESP_OK(sdmmc_read_sectors(card, c_buffer, start_block, block_count)); - struct timeval t_stop_rd; - gettimeofday(&t_stop_rd, NULL); - float time_rd = 1e3f * (t_stop_rd.tv_sec - t_start_rd.tv_sec) + 1e-3f * (t_stop_rd.tv_usec - t_start_rd.tv_usec); - - printf(" | %6.2f | %5.2f | %6.2f | %5.2f\n", - time_wr, total_size / (time_wr / 1000) / (1024 * 1024), - time_rd, total_size / (time_rd / 1000) / (1024 * 1024)); - check_buffer(start_block, c_buffer, total_size / sizeof(buffer[0])); - free(buffer); - - if (performance_log) { - static const char wr_speed_str[] = "SDMMC_WR_SPEED"; - static const char rd_speed_str[] = "SDMMC_RD_SPEED"; - int aligned = ((alignment % 4) == 0)? 1: 0; - IDF_LOG_PERFORMANCE(wr_speed_str, "%d, blk_n: %d, aligned: %d", - (int)(total_size * 1000 / time_wr), block_count, aligned); - IDF_LOG_PERFORMANCE(rd_speed_str, "%d, blk_n: %d, aligned: %d", - (int)(total_size * 1000 / time_rd), block_count, aligned); - } -} - -typedef void (*sd_test_func_t)(sdmmc_card_t* card); - -static void test_read_write_performance(sdmmc_card_t* card) -{ - sdmmc_card_print_info(stdout, card); - printf(" sector | count | align | size(kB) | wr_time(ms) | wr_speed(MB/s) | rd_time(ms) | rd_speed(MB/s)\n"); - const int offset = 0; - const bool do_log = true; - //aligned - do_single_write_read_test(card, offset, 1, 4, do_log); - do_single_write_read_test(card, offset, 4, 4, do_log); - do_single_write_read_test(card, offset, 8, 4, do_log); - do_single_write_read_test(card, offset, 16, 4, do_log); - do_single_write_read_test(card, offset, 32, 4, do_log); - do_single_write_read_test(card, offset, 64, 4, do_log); - do_single_write_read_test(card, offset, 128, 4, do_log); - //unaligned - do_single_write_read_test(card, offset, 1, 1, do_log); - do_single_write_read_test(card, offset, 8, 1, do_log); - do_single_write_read_test(card, offset, 128, 1, do_log); -} - -static void test_read_write_with_offset(sdmmc_card_t* card) -{ - sdmmc_card_print_info(stdout, card); - printf(" sector | count | align | size(kB) | wr_time(ms) | wr_speed(MB/s) | rd_time(ms) | rd_speed(MB/s)\n"); - const bool no_log = false;; - //aligned - do_single_write_read_test(card, 1, 16, 4, no_log); - do_single_write_read_test(card, 16, 32, 4, no_log); - do_single_write_read_test(card, 48, 64, 4, no_log); - do_single_write_read_test(card, 128, 128, 4, no_log); - do_single_write_read_test(card, card->csd.capacity - 64, 32, 4, no_log); - do_single_write_read_test(card, card->csd.capacity - 64, 64, 4, no_log); - do_single_write_read_test(card, card->csd.capacity - 8, 1, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 1, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 4, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 8, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 16, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 32, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 64, 4, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 128, 4, no_log); - //unaligned - do_single_write_read_test(card, card->csd.capacity/2, 1, 1, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 8, 1, no_log); - do_single_write_read_test(card, card->csd.capacity/2, 128, 1, no_log); -} -#endif //WITH_SD_TEST || WITH_SDSPI_TEST || WITH_EMMC_TEST - -#if WITH_SD_TEST || WITH_EMMC_TEST -void sd_test_rw_blocks(int slot, int width, sd_test_func_t test_func) -{ - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - config.max_freq_khz = SDMMC_FREQ_HIGHSPEED; - config.slot = slot; - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - if (width != 0) { - slot_config.width = width; - } - if (slot_config.width == 8) { - config.flags &= ~SDMMC_HOST_FLAG_DDR; - } - TEST_ESP_OK(sdmmc_host_init()); - TEST_ESP_OK(sdmmc_host_init_slot(slot, &slot_config)); - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - test_func(card); - free(card); - TEST_ESP_OK(sdmmc_host_deinit()); -} -#endif //WITH_SD_TEST || WITH_EMMC_TEST - -#if WITH_SD_TEST -TEST_CASE("SDMMC performance test (SD slot 1, 4 line)", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(1, 4, test_read_write_performance); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC performance test (SD slot 1, 1 line)", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(1, 1, test_read_write_performance); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC test read/write with offset (SD slot 1)", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(1, 4, test_read_write_with_offset); - sd_test_board_power_off(); -} -#endif //WITH_SD_TEST - -#if WITH_EMMC_TEST -TEST_CASE("SDMMC performance test (eMMC slot 0, 4 line DDR)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 4, test_read_write_performance); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC test read/write with offset (eMMC slot 0, 4 line DDR)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 4, test_read_write_with_offset); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC performance test (eMMC slot 0, 8 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 8, test_read_write_performance); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC test read/write with offset (eMMC slot 0, 8 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 8, test_read_write_with_offset); - sd_test_board_power_off(); -} -#endif // WITH_EMMC_TEST - -#if WITH_SDSPI_TEST -void sdspi_test_rw_blocks(sd_test_func_t test_func) -{ - sd_test_board_power_on(); - - sdmmc_host_t config = SDSPI_HOST_DEFAULT(); - sdspi_dev_handle_t handle; - sdspi_device_config_t dev_config = SDSPI_DEVICE_CONFIG_DEFAULT(); - dev_config.host_id = config.slot; - dev_config.gpio_cs = SDSPI_TEST_CS_PIN; - test_sdspi_init_bus(dev_config.host_id, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_MISO_PIN, SDSPI_TEST_SCLK_PIN, SPI_DMA_CH_AUTO); - TEST_ESP_OK(sdspi_host_init()); - TEST_ESP_OK(sdspi_host_init_device(&dev_config, &handle)); - - // This test can only run under 20MHz on ESP32, because the runner connects the card to - // non-IOMUX pins of HSPI. - - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - test_func(card); - TEST_ESP_OK(sdspi_host_deinit()); - free(card); - test_sdspi_deinit_bus(dev_config.host_id); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC performance (SPI mode)", "[sdspi][test_env=UT_T1_SPIMODE]") -{ - sdspi_test_rw_blocks(test_read_write_performance); -} - -TEST_CASE("SDMMC test read/write with offset (SPI mode)", "[sdspi][test_env=UT_T1_SPIMODE]") -{ - sdspi_test_rw_blocks(test_read_write_with_offset); -} -#endif //WITH_SDSPI_TEST - -#if WITH_SD_TEST -TEST_CASE("reads and writes with an unaligned buffer", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - TEST_ESP_OK(sdmmc_host_init()); - - TEST_ESP_OK(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config)); - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - - const size_t buffer_size = 4096; - const size_t block_count = buffer_size / 512; - const size_t extra = 4; - uint8_t* buffer = heap_caps_malloc(buffer_size + extra, MALLOC_CAP_DMA); - - // Check read behavior: do aligned write, then unaligned read - const uint32_t seed = 0x89abcdef; - fill_buffer(seed, buffer, buffer_size / sizeof(uint32_t)); - TEST_ESP_OK(sdmmc_write_sectors(card, buffer, 0, block_count)); - memset(buffer, 0xcc, buffer_size + extra); - TEST_ESP_OK(sdmmc_read_sectors(card, buffer + 1, 0, block_count)); - check_buffer(seed, buffer + 1, buffer_size / sizeof(uint32_t)); - - // Check write behavior: do unaligned write, then aligned read - fill_buffer(seed, buffer + 1, buffer_size / sizeof(uint32_t)); - TEST_ESP_OK(sdmmc_write_sectors(card, buffer + 1, 8, block_count)); - memset(buffer, 0xcc, buffer_size + extra); - TEST_ESP_OK(sdmmc_read_sectors(card, buffer, 8, block_count)); - check_buffer(seed, buffer, buffer_size / sizeof(uint32_t)); - - free(buffer); - free(card); - TEST_ESP_OK(sdmmc_host_deinit()); - sd_test_board_power_off(); -} -#endif //WITH_SD_TEST - -#if WITH_SD_TEST || WITH_SDSPI_TEST -static void test_cd_input(int gpio_cd_num, const sdmmc_host_t* config) -{ - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - - // SDMMC host should have configured CD as input. - // Enable output as well (not using the driver, to avoid touching input - // enable bits). - esp_rom_gpio_connect_out_signal(gpio_cd_num, SIG_GPIO_OUT_IDX, false, false); - REG_WRITE(GPIO_ENABLE_W1TS_REG, BIT(gpio_cd_num)); - - // Check that card initialization fails if CD is high - REG_WRITE(GPIO_OUT_W1TS_REG, BIT(gpio_cd_num)); - usleep(10000); - TEST_ESP_ERR(ESP_ERR_NOT_FOUND, sdmmc_card_init(config, card)); - - // Check that card initialization succeeds if CD is low - REG_WRITE(GPIO_OUT_W1TC_REG, BIT(gpio_cd_num)); - usleep(10000); - esp_err_t err = sdmmc_card_init(config, card); - if (err != ESP_OK) { - usleep(10000); - // Try again, in case the card was not ready yet - err = sdmmc_card_init(config, card); - } - TEST_ESP_OK(err); - - free(card); -} - -static void test_wp_input(int gpio_wp_num, bool gpio_wp_polarity, const sdmmc_host_t* config) -{ - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - - // SDMMC host should have configured WP as input. - // Enable output as well (not using the driver, to avoid touching input - // enable bits). - esp_rom_gpio_connect_out_signal(gpio_wp_num, SIG_GPIO_OUT_IDX, false, false); - REG_WRITE(GPIO_ENABLE_W1TS_REG, BIT(gpio_wp_num)); - - // Check that the card can be initialized with WP low - REG_WRITE(GPIO_OUT_W1TC_REG, BIT(gpio_wp_num)); - TEST_ESP_OK(sdmmc_card_init(config, card)); - - uint32_t* data = heap_caps_calloc(1, 512, MALLOC_CAP_DMA); - - // Check that card write succeeds if WP is high - REG_WRITE((gpio_wp_polarity? GPIO_OUT_W1TC_REG : GPIO_OUT_W1TS_REG), BIT(gpio_wp_num)); - usleep(1000); - TEST_ESP_OK(sdmmc_write_sectors(card, &data, 0, 1)); - - // Check that write fails if WP is low - REG_WRITE((gpio_wp_polarity? GPIO_OUT_W1TS_REG : GPIO_OUT_W1TC_REG), BIT(gpio_wp_num)); - usleep(1000); - TEST_ESP_ERR(ESP_ERR_INVALID_STATE, sdmmc_write_sectors(card, &data, 0, 1)); - // ...but reads still work - TEST_ESP_OK(sdmmc_read_sectors(card, &data, 0, 1)); - - free(data); - free(card); -} -#endif //WITH_SD_TEST || WITH_SDSPI_TEST - -#if WITH_SD_TEST -TEST_CASE("CD input works in SD mode", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - slot_config.gpio_cd = CD_WP_TEST_GPIO; - TEST_ESP_OK(sdmmc_host_init()); - usleep(10000); - TEST_ESP_OK(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config)); - - test_cd_input(CD_WP_TEST_GPIO, &config); - - TEST_ESP_OK(sdmmc_host_deinit()); - sd_test_board_power_off(); -} - -TEST_CASE("WP input works in SD mode", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - slot_config.gpio_wp = CD_WP_TEST_GPIO; - bool gpio_wp_polarity = GPIO_ACTIVE_LOW; - if (gpio_wp_polarity) { - slot_config.flags |= SDMMC_SLOT_FLAG_WP_ACTIVE_HIGH; - } else { - slot_config.flags &= ~(SDMMC_SLOT_FLAG_WP_ACTIVE_HIGH); - } - TEST_ESP_OK(sdmmc_host_init()); - usleep(10000); - TEST_ESP_OK(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config)); - - test_wp_input(slot_config.gpio_wp, gpio_wp_polarity, &config); - - TEST_ESP_OK(sdmmc_host_deinit()); - sd_test_board_power_off(); -} -#endif //WITH_SD_TEST - -#if WITH_SDSPI_TEST -TEST_CASE("CD input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]") -{ - sd_test_board_power_on(); - - sdmmc_host_t config = SDSPI_HOST_DEFAULT(); - sdspi_dev_handle_t handle; - sdspi_device_config_t dev_config = SDSPI_DEVICE_CONFIG_DEFAULT(); - dev_config.host_id = config.slot; - dev_config.gpio_cs = SDSPI_TEST_CS_PIN; - dev_config.gpio_cd = CD_WP_TEST_GPIO; - test_sdspi_init_bus(dev_config.host_id, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_MISO_PIN, SDSPI_TEST_SCLK_PIN, SPI_DMA_CH_AUTO); - TEST_ESP_OK(sdspi_host_init()); - TEST_ESP_OK(sdspi_host_init_device(&dev_config, &handle)); - - config.slot = handle; - - test_cd_input(CD_WP_TEST_GPIO, &config); - - TEST_ESP_OK(sdspi_host_deinit()); - test_sdspi_deinit_bus(dev_config.host_id); - sd_test_board_power_off(); -} - -TEST_CASE("WP input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]") -{ - sd_test_board_power_on(); - - sdmmc_host_t config = SDSPI_HOST_DEFAULT(); - sdspi_dev_handle_t handle; - sdspi_device_config_t dev_config = SDSPI_DEVICE_CONFIG_DEFAULT(); - dev_config.host_id = config.slot; - dev_config.gpio_cs = SDSPI_TEST_CS_PIN; - dev_config.gpio_wp = CD_WP_TEST_GPIO; - dev_config.gpio_wp_polarity = GPIO_ACTIVE_LOW; - test_sdspi_init_bus(dev_config.host_id, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_MISO_PIN, SDSPI_TEST_SCLK_PIN, SPI_DMA_CH_AUTO); - - TEST_ESP_OK(sdspi_host_init()); - TEST_ESP_OK(sdspi_host_init_device(&dev_config, &handle)); - - config.slot = handle; - - test_wp_input(dev_config.gpio_wp, dev_config.gpio_wp_polarity, &config); - - TEST_ESP_OK(sdspi_host_deinit()); - test_sdspi_deinit_bus(dev_config.host_id); - sd_test_board_power_off(); -} -#endif //WITH_SDSPI_TEST - -#if WITH_SD_TEST || WITH_EMMC_TEST - -#define PATTERN_SEED 0x12345678 -#define FLAG_ERASE_TEST_ADJACENT (1 << 0) -#define FLAG_VERIFY_ERASE_STATE (1 << 1) -bool do_sanitize_flag = false; -static void ensure_sector_written(sdmmc_card_t* card, size_t sector, - uint8_t *pattern_buf, uint8_t *temp_buf) -{ - size_t block_size = card->csd.sector_size; - TEST_ESP_OK(sdmmc_write_sectors(card, pattern_buf, sector, 1)); - memset((void *)temp_buf, 0x00, block_size); - TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); - check_buffer(PATTERN_SEED, temp_buf, block_size / sizeof(uint32_t)); -} - -static void ensure_sector_intact(sdmmc_card_t* card, size_t sector, - uint8_t *pattern_buf, uint8_t *temp_buf) -{ - size_t block_size = card->csd.sector_size; - memset((void *)temp_buf, 0x00, block_size); - TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); - check_buffer(PATTERN_SEED, temp_buf, block_size / sizeof(uint32_t)); -} - -static int32_t ensure_sector_erase(sdmmc_card_t* card, size_t sector, - uint8_t *pattern_buf, uint8_t *temp_buf) -{ - size_t block_size = card->csd.sector_size; - memset((void *)temp_buf, 0, block_size); - TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, sector, 1)); - return memcmp(pattern_buf, temp_buf, block_size); -} - -static void do_single_erase_test(sdmmc_card_t* card, size_t start_block, - size_t block_count, uint8_t flags, sdmmc_erase_arg_t arg) -{ - size_t block_size = card->csd.sector_size; - uint8_t *temp_buf = NULL; - uint8_t *pattern_buf = NULL; - size_t end_block = (start_block + block_count - 1); - - /* - * To ensure erase is successful/valid - * selected blocks after erase should have erase state data pattern - * data of blocks adjacent to selected region should remain intact - */ - TEST_ESP_OK((start_block + block_count) > card->csd.capacity); - - pattern_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); - TEST_ASSERT_NOT_NULL(pattern_buf); - temp_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); - TEST_ASSERT_NOT_NULL(temp_buf); - - // create pattern buffer - fill_buffer(PATTERN_SEED, pattern_buf, block_size / sizeof(uint32_t)); - - // check if it's not the first block of device & write/read/verify pattern - if ((flags & FLAG_ERASE_TEST_ADJACENT) && start_block) { - ensure_sector_written(card, (start_block - 1), pattern_buf, temp_buf); - } - - ensure_sector_written(card, start_block, pattern_buf, temp_buf); - - // check if it's not the last block of device & write/read/verify pattern - if ((flags & FLAG_ERASE_TEST_ADJACENT) && (end_block < (card->csd.capacity - 1))) { - ensure_sector_written(card, (end_block + 1), pattern_buf, temp_buf); - } - - // when block count is 1, start and end block is same, hence skip - if (block_count != 1) { - ensure_sector_written(card, end_block, pattern_buf, temp_buf); - } - - // fill pattern to (start_block + end_block)/2 in the erase range - if(block_count > 2) { - ensure_sector_written(card, (start_block + end_block)/2, pattern_buf, temp_buf); - } - - float total_size = (block_count/1024.0f) * block_size; - printf(" %10d | %10d | %8.1f ", start_block, block_count, total_size); - fflush(stdout); - - // erase the blocks - struct timeval t_start_er; - gettimeofday(&t_start_er, NULL); - TEST_ESP_OK(sdmmc_erase_sectors(card, start_block, block_count, arg)); - if (do_sanitize_flag) { - TEST_ESP_OK(sdmmc_mmc_sanitize(card, block_count * 500)); - } - struct timeval t_stop_wr; - gettimeofday(&t_stop_wr, NULL); - float time_er = 1e3f * (t_stop_wr.tv_sec - t_start_er.tv_sec) + 1e-3f * (t_stop_wr.tv_usec - t_start_er.tv_usec); - printf(" | %8.2f\n", time_er); - - // ensure adjacent blocks are not affected - // block before start_block - if ((flags & FLAG_ERASE_TEST_ADJACENT) && start_block) { - ensure_sector_intact(card, (start_block - 1), pattern_buf, temp_buf); - } - - // block after end_block - if ((flags & FLAG_ERASE_TEST_ADJACENT) && (end_block < (card->csd.capacity - 1))) { - ensure_sector_intact(card, (end_block + 1), pattern_buf, temp_buf); - } - - uint8_t erase_mem_byte = 0xFF; - // ensure all the blocks are erased and are up to after erase state. - if (!card->is_mmc) { - erase_mem_byte = card->scr.erase_mem_state ? 0xFF : 0x00; - } else { - erase_mem_byte = card->ext_csd.erase_mem_state ? 0xFF : 0x00; - } - - memset((void *)pattern_buf, erase_mem_byte, block_size); - - // as it is block by block comparison, a time taking process. Really long - // when you do erase and verify on complete device. - if (flags & FLAG_VERIFY_ERASE_STATE) { - for (size_t i = 0; i < block_count; i++) { - if (ensure_sector_erase(card, (start_block + i), pattern_buf, temp_buf)) { - printf("Error: Sector %d erase\n", (start_block + i)); - break; - } - } - } - - free(temp_buf); - free(pattern_buf); -} -#endif // WITH_SD_TEST || WITH_EMMC_TEST - -#if WITH_SDSPI_TEST -static void test_sdspi_erase_blocks(size_t start_block, size_t block_count) -{ - sd_test_board_power_on(); - sdmmc_host_t config = SDSPI_HOST_DEFAULT(); - sdspi_dev_handle_t handle; - sdspi_device_config_t dev_config = SDSPI_DEVICE_CONFIG_DEFAULT(); - dev_config.host_id = config.slot; - dev_config.gpio_cs = SDSPI_TEST_CS_PIN; - test_sdspi_init_bus(dev_config.host_id, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_MISO_PIN, SDSPI_TEST_SCLK_PIN, SPI_DMA_CH_AUTO); - TEST_ESP_OK(sdspi_host_init()); - TEST_ESP_OK(sdspi_host_init_device(&dev_config, &handle)); - - // This test can only run under 20MHz on ESP32, because the runner connects the card to - // non-IOMUX pins of HSPI. - - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - sdmmc_card_print_info(stdout, card); - - // Ensure discard operation is not supported in sdspi - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, start_block, block_count, SDMMC_DISCARD_ARG)); - - printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); - printf("Erasing sectors %d-%d\n", start_block, (start_block + block_count -1)); - size_t block_size = card->csd.sector_size; - uint8_t *pattern_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); - TEST_ASSERT_NOT_NULL(pattern_buf); - uint8_t *temp_buf = (uint8_t *)heap_caps_malloc(block_size, MALLOC_CAP_DMA); - TEST_ASSERT_NOT_NULL(temp_buf); - - struct timeval t_start_er; - gettimeofday(&t_start_er, NULL); - TEST_ESP_OK(sdmmc_erase_sectors(card, start_block, block_count, SDMMC_ERASE_ARG)); - struct timeval t_stop_wr; - gettimeofday(&t_stop_wr, NULL); - float time_er = 1e3f * (t_stop_wr.tv_sec - t_start_er.tv_sec) + 1e-3f * (t_stop_wr.tv_usec - t_start_er.tv_usec); - printf("Erase duration: %.2fms\n", time_er); - - printf("Verifying erase state...\n"); - uint8_t erase_mem_byte = 0xFF; - // ensure all the blocks are erased and are up to after erase state. - if (!card->is_mmc) { - erase_mem_byte = card->scr.erase_mem_state ? 0xFF : 0x00; - } else { - erase_mem_byte = card->ext_csd.erase_mem_state ? 0xFF : 0x00; - } - - memset((void *)pattern_buf, erase_mem_byte, block_size); - - size_t i; - for (i = 0; i < block_count; i++) { - memset((void *)temp_buf, 0, block_size); - TEST_ESP_OK(sdmmc_read_sectors(card, temp_buf, (start_block + i), 1)); - if (memcmp(pattern_buf, temp_buf, block_size)) { - printf("Error: Sector %d erase\n", (start_block + i)); - break; - } - } - if (i == block_count) { - printf("Sectors erase success\n"); - } - TEST_ESP_OK(sdspi_host_deinit()); - test_sdspi_deinit_bus(dev_config.host_id); - free(card); - free(temp_buf); - free(pattern_buf); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC erase (SPI mode)", "[sdspi][test_env=UT_T1_SPIMODE]") -{ - test_sdspi_erase_blocks(0, 16); -} -#endif // WITH_SDSPI_TEST - -#if WITH_SD_TEST -static void test_sd_erase_blocks(sdmmc_card_t* card) -{ - sdmmc_card_print_info(stdout, card); - printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); - printf(" sector | count | size(kB) | er_time(ms) \n"); - /* - * bit-0: verify adjacent blocks of given range - * bit-1: verify erase state of blocks in range - */ - uint8_t flags = 0; - sdmmc_erase_arg_t arg = SDMMC_ERASE_ARG; - - //check for adjacent blocks and erase state of blocks - flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT | (uint8_t)FLAG_VERIFY_ERASE_STATE; - do_single_erase_test(card, 1, 16, flags, arg); - do_single_erase_test(card, 1, 13, flags, arg); - do_single_erase_test(card, 16, 32, flags, arg); - do_single_erase_test(card, 48, 64, flags, arg); - do_single_erase_test(card, 128, 128, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); - // single sector erase is failing on different make cards - do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 4, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 8, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 16, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 128, flags, arg); -#ifdef SDMMC_FULL_ERASE_TEST - /* - * check for adjacent blocks, do not check erase state of blocks as it is - * time taking process to verify all the blocks. - */ - flags &= ~(uint8_t)FLAG_VERIFY_ERASE_STATE; //comment this line to verify after-erase state - // erase complete card - do_single_erase_test(card, 0, card->csd.capacity, flags, arg); -#endif //SDMMC_FULL_ERASE_TEST -} - -static void test_sd_discard_blocks(sdmmc_card_t* card) -{ - /* MMC discard applies to write blocks */ - sdmmc_card_print_info(stdout, card); - /* - * bit-0: verify adjacent blocks of given range - * bit-1: verify erase state of blocks in range - */ - uint8_t flags = 0; - sdmmc_erase_arg_t arg = SDMMC_DISCARD_ARG; - - /* - * This test does run two tests - * test-1: check, sdmmc_erase_sectors to return ESP_ERR_NOT_SUPPORTED - * when arguments are condition not met. This test runs either the card - * supports discard or not. - * - * test-2: If card supports discard, perform the test accordingly and - * validate the behavior. - * - */ - uint32_t prev_discard_support = card->ssr.discard_support; - // overwrite discard_support as not-supported for -ve test - card->ssr.discard_support = 0; - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, 0, 32, arg)); - // restore discard_support - card->ssr.discard_support = prev_discard_support; - if (sdmmc_can_discard(card) != ESP_OK ) { - printf("Card/device do not support discard\n"); - return; - } - - printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); - printf(" sector | count | size(kB) | er_time(ms) \n"); - /* - * Check for adjacent blocks only. - * After discard operation, the original data may be remained partially or - * fully accessible to the host dependent on device. Hence do not verify - * the erased state of the blocks. - */ - flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT; - do_single_erase_test(card, 1, 16, flags, arg); - do_single_erase_test(card, 1, 13, flags, arg); - do_single_erase_test(card, 16, 32, flags, arg); - do_single_erase_test(card, 48, 64, flags, arg); - do_single_erase_test(card, 128, 128, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 4, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 8, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 16, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 128, flags, arg); -} - -TEST_CASE("SDMMC erase test (SD slot 1, 1 line)", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(1, 1, test_sd_erase_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC erase test (SD slot 1, 4 line)", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(1, 4, test_sd_erase_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC discard test (SD slot 1, 4 line)", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(1, 4, test_sd_discard_blocks); - sd_test_board_power_off(); -} -#endif //WITH_SD_TEST - -#if WITH_SD_TEST -TEST_CASE("sdmmc read/write/erase sector shoud return ESP_OK with sector count == 0", "[sd][test_env=UT_T1_SDMODE]") -{ - sd_test_board_power_on(); - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - TEST_ESP_OK(sdmmc_host_init()); - - TEST_ESP_OK(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config)); - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - - TEST_ESP_OK(sdmmc_write_sectors(card, NULL, 0, 0)); - TEST_ESP_OK(sdmmc_read_sectors(card, NULL, 0, 0)); - TEST_ESP_OK(sdmmc_erase_sectors(card, 0, 0, SDMMC_ERASE_ARG)); - - free(card); - TEST_ESP_OK(sdmmc_host_deinit()); - sd_test_board_power_off(); -} -#endif //WITH_SD_TEST - -#if WITH_EMMC_TEST -static void test_mmc_sanitize_blocks(sdmmc_card_t* card) -{ - /* MMC discard applies to write blocks */ - sdmmc_card_print_info(stdout, card); - printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); - - if (sdmmc_mmc_can_sanitize(card)) { - printf("Card/device do not support sanitize\n"); - return; - } - printf(" sector | count | size(kB) | er_time(ms) \n"); - /* - * bit-0: verify adjacent blocks of given range - * bit-1: verify erase state of blocks in range - */ - uint8_t flags = 0; - sdmmc_erase_arg_t arg = SDMMC_DISCARD_ARG; - do_sanitize_flag = true; - - /* - * Check for adjacent blocks only. - * After discard operation, the original data may be remained partially or - * fully accessible to the host dependent on device. Hence do not verify - * the erased state of the blocks. - * - * Note: After sanitize blocks has to be in erased state - */ - flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT | (uint8_t)FLAG_VERIFY_ERASE_STATE; - do_single_erase_test(card, 1, 16, flags, arg); - do_single_erase_test(card, 1, 13, flags, arg); - do_single_erase_test(card, 16, 32, flags, arg); - do_single_erase_test(card, 48, 64, flags, arg); - do_single_erase_test(card, 128, 128, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 4, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 8, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 16, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 128, flags, arg); - do_sanitize_flag = false; -} - -static void test_mmc_discard_blocks(sdmmc_card_t* card) -{ - /* MMC discard applies to write blocks */ - sdmmc_card_print_info(stdout, card); - printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); - - sdmmc_erase_arg_t arg = SDMMC_DISCARD_ARG; - uint32_t prev_ext_csd = card->ext_csd.rev; - // overwrite discard_support as not-supported for -ve test - card->ext_csd.rev = 0; - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, 0, 32, arg)); - // restore discard_support - card->ext_csd.rev = prev_ext_csd; - if (sdmmc_can_discard(card) != ESP_OK) { - printf("Card/device do not support discard\n"); - return; - } - - printf(" sector | count | size(kB) | er_time(ms) \n"); - /* - * bit-0: verify adjacent blocks of given range - * bit-1: verify erase state of blocks in range - */ - uint8_t flags = 0; - - /* - * Check for adjacent blocks only. - * After discard operation, the original data may be remained partially or - * fully accessible to the host dependent on device. Hence do not verify - * the erased state of the blocks. - */ - flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT; - do_single_erase_test(card, 1, 16, flags, arg); - do_single_erase_test(card, 1, 13, flags, arg); - do_single_erase_test(card, 16, 32, flags, arg); - do_single_erase_test(card, 48, 64, flags, arg); - do_single_erase_test(card, 128, 128, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 4, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 8, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 16, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 128, flags, arg); -} - -static void test_mmc_trim_blocks(sdmmc_card_t* card) -{ - /* MMC trim applies to write blocks */ - sdmmc_card_print_info(stdout, card); - printf("block size %d capacity %d\n", card->csd.sector_size, card->csd.capacity); - sdmmc_erase_arg_t arg = SDMMC_ERASE_ARG; - uint8_t prev_sec_feature = card->ext_csd.sec_feature; - // overwrite sec_feature - card->ext_csd.sec_feature &= ~(EXT_CSD_SEC_GB_CL_EN); - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, sdmmc_erase_sectors(card, 0, 32, arg)); - // restore sec_feature - card->ext_csd.sec_feature = prev_sec_feature; - if (sdmmc_can_trim(card) != ESP_OK) { - printf("Card/device do not support trim\n"); - return; - } - printf(" sector | count | size(kB) | er_time(ms) \n"); - /* - * bit-0: verify adjacent blocks of given range - * bit-1: verify erase state of blocks in range - */ - uint8_t flags = 0; - - //check for adjacent blocks and erase state of blocks - flags |= (uint8_t)FLAG_ERASE_TEST_ADJACENT | (uint8_t)FLAG_VERIFY_ERASE_STATE; - do_single_erase_test(card, 1, 16, flags, arg); - do_single_erase_test(card, 1, 13, flags, arg); - do_single_erase_test(card, 16, 32, flags, arg); - do_single_erase_test(card, 48, 64, flags, arg); - do_single_erase_test(card, 128, 128, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity - 64, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity - 8, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 1, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 4, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 8, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 16, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 32, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 64, flags, arg); - do_single_erase_test(card, card->csd.capacity/2, 128, flags, arg); -#ifdef SDMMC_FULL_ERASE_TEST - /* - * check for adjacent blocks, do not check erase state of blocks as it is - * time taking process to verify all the blocks. - */ - flags &= ~(uint8_t)FLAG_VERIFY_ERASE_STATE; //comment this line to verify after erase state - // erase complete card - do_single_erase_test(card, 0, card->csd.capacity, flags, arg); -#endif //SDMMC_FULL_ERASE_TEST -} - -TEST_CASE("SDMMC trim test (eMMC slot 0, 4 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 4, test_mmc_trim_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC trim test (eMMC slot 0, 8 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 8, test_mmc_trim_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC discard test (eMMC slot 0, 4 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 4, test_mmc_discard_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC discard test (eMMC slot 0, 8 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 8, test_mmc_discard_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC sanitize test (eMMC slot 0, 4 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 4, test_mmc_sanitize_blocks); - sd_test_board_power_off(); -} - -TEST_CASE("SDMMC sanitize test (eMMC slot 0, 8 line)", "[sd][test_env=EMMC][ignore]") -{ - sd_test_board_power_on(); - sd_test_rw_blocks(0, 8, test_mmc_sanitize_blocks); - sd_test_board_power_off(); -} -#endif //WITH_EMMC_TEST diff --git a/components/sdmmc/test/test_sdio.c b/components/sdmmc/test/test_sdio.c deleted file mode 100644 index 953aba7c351..00000000000 --- a/components/sdmmc/test/test_sdio.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/soc_caps.h" -#if SOC_SDMMC_HOST_SUPPORTED - -#include -#include -#include -#include "esp_log.h" -#include "esp_heap_caps.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "driver/gpio.h" -#include "driver/sdmmc_host.h" -#include "driver/sdmmc_defs.h" -#include "sdmmc_cmd.h" -#include "unity.h" -#include "soc/gpio_reg.h" - -/* Second ESP32 board attached as follows: - * Master Slave - * IO18 EN - * IO19 IO0 - * IO14 SD_CLK - * IO15 SD_CMD - * IO2 SD_D0 - * IO4 SD_D1 - * IO12 SD_D2 - * IO13 SD_D3 - */ - - -/* TODO: add SDIO slave header files, remove these definitions */ - -#define DR_REG_SLC_MASK 0xfffffc00 - -#define SLCCONF1 (DR_REG_SLC_BASE + 0x60) -#define SLC_SLC0_RX_STITCH_EN (BIT(6)) -#define SLC_SLC0_TX_STITCH_EN (BIT(5)) - -#define SLC0TX_LINK (DR_REG_SLC_BASE + 0x40) -#define SLC_SLC0_TXLINK_PARK (BIT(31)) -#define SLC_SLC0_TXLINK_RESTART (BIT(30)) -#define SLC_SLC0_TXLINK_START (BIT(29)) - -#define DR_REG_SLCHOST_MASK 0xfffffc00 -#define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64) -#define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C) -#define SLCHOST_CONF_W5 (DR_REG_SLCHOST_BASE + 0x80) -#define SLCHOST_WIN_CMD (DR_REG_SLCHOST_BASE + 0x84) - -#define SLC_WIN_CMD_READ 0x80 -#define SLC_WIN_CMD_WRITE 0xC0 -#define SLC_WIN_CMD_S 8 - -#define SLC_THRESHOLD_ADDR 0x1f800 - -static const char* TAG = "sdio_test"; - -static esp_err_t slave_slchost_reg_read(sdmmc_card_t* card, uint32_t addr, uint32_t* out_val) -{ - if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) { - ESP_LOGW(TAG, "%s: invalid addr 0x%08x", __func__, addr); - return ESP_ERR_INVALID_ARG; - } - return sdmmc_io_read_bytes(card, 1, addr & (~DR_REG_SLCHOST_MASK), out_val, sizeof(*out_val)); -} - -static esp_err_t slave_slchost_reg_write(sdmmc_card_t* card, uint32_t addr, uint32_t val) -{ - if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) { - ESP_LOGW(TAG, "%s: invalid addr 0x%08x", __func__, addr); - return ESP_ERR_INVALID_ARG; - } - return sdmmc_io_write_bytes(card, 1, addr & (~DR_REG_SLCHOST_MASK), &val, sizeof(val)); -} - -static esp_err_t slave_slc_reg_read(sdmmc_card_t* card, uint32_t addr, uint32_t* val) -{ - if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) { - ESP_LOGW(TAG, "%s: invalid addr 0x%08x", __func__, addr); - return ESP_ERR_INVALID_ARG; - } - uint32_t word = (addr - DR_REG_SLC_BASE) / 4; - if (word > INT8_MAX) { - return ESP_ERR_INVALID_ARG; - } - - uint32_t window_command = word | (SLC_WIN_CMD_READ << SLC_WIN_CMD_S); - esp_err_t err = slave_slchost_reg_write(card, SLCHOST_WIN_CMD, window_command); - if (err != ESP_OK) { - return err; - } - - return slave_slchost_reg_read(card, SLCHOST_STATE_W0, val); -} - -static esp_err_t slave_slc_reg_write(sdmmc_card_t* card, uint32_t addr, uint32_t val) -{ - if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) { - ESP_LOGW(TAG, "%s: invalid addr 0x%08x", __func__, addr); - return ESP_ERR_INVALID_ARG; - } - uint32_t word = (addr - DR_REG_SLC_BASE) / 4; - if (word > INT8_MAX) { - return ESP_ERR_INVALID_ARG; - } - - esp_err_t err = slave_slchost_reg_write(card, SLCHOST_CONF_W5, val); - if (err != ESP_OK) { - return err; - } - - uint32_t window_command = word | (SLC_WIN_CMD_WRITE << SLC_WIN_CMD_S); - return slave_slchost_reg_write(card, SLCHOST_WIN_CMD, window_command); -} - -/** Reset and put slave into download mode */ -static void reset_slave(void) -{ - const int pin_en = 18; - const int pin_io0 = 19; - gpio_config_t gpio_cfg = { - .pin_bit_mask = BIT64(pin_en) | BIT64(pin_io0), - .mode = GPIO_MODE_OUTPUT_OD, - }; - TEST_ESP_OK(gpio_config(&gpio_cfg)); - gpio_set_level(pin_en, 0); - gpio_set_level(pin_io0, 0); - vTaskDelay(10 / portTICK_PERIOD_MS); - gpio_set_level(pin_en, 1); - vTaskDelay(10 / portTICK_PERIOD_MS); - gpio_set_level(pin_io0, 1); -} - -static void sdio_slave_common_init(sdmmc_card_t* card) -{ - uint8_t card_cap; - esp_err_t err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_CARD_CAP, &card_cap); - TEST_ESP_OK(err); - printf("CAP: 0x%02x\n", card_cap); - - uint8_t hs; - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_HIGHSPEED, &hs); - TEST_ESP_OK(err); - printf("HS: 0x%02x\n", hs); - - -#define FUNC1_EN_MASK (BIT(1)) - - uint8_t ioe; - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe); - TEST_ESP_OK(err); - printf("IOE: 0x%02x\n", ioe); - - uint8_t ior = 0; - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior); - TEST_ESP_OK(err); - printf("IOR: 0x%02x\n", ior); - - // enable function 1 - ioe |= FUNC1_EN_MASK; - err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_FN_ENABLE, ioe, NULL); - TEST_ESP_OK(err); - - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe); - TEST_ESP_OK(err); - printf("IOE: 0x%02x\n", ioe); - - // wait for the card to become ready - while ( (ior & FUNC1_EN_MASK) == 0 ) { - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior); - TEST_ESP_OK(err); - printf("IOR: 0x%02x\n", ior); - } - - // get interrupt status - uint8_t ie; - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie); - TEST_ESP_OK(err); - printf("IE: 0x%02x\n", ie); - - // enable interrupts for function 1&2 and master enable - ie |= BIT(0) | FUNC1_EN_MASK; - err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_INT_ENABLE, ie, NULL); - TEST_ESP_OK(err); - - err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie); - TEST_ESP_OK(err); - printf("IE: 0x%02x\n", ie); -} - -/** Common for all SDIO devices, set block size for specific function */ -static void sdio_slave_set_blocksize(sdmmc_card_t* card, int function, uint16_t bs) -{ - const uint8_t* bs_u8 = (const uint8_t*) &bs; - uint16_t bs_read = 0; - uint8_t* bs_read_u8 = (uint8_t*) &bs_read; - uint32_t offset = SD_IO_FBR_START * function; - TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, bs_u8[0], NULL)); - TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, bs_u8[1], NULL)); - TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0])); - TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1])); - TEST_ASSERT_EQUAL_HEX16(bs, bs_read); -} - -/** - * ESP32 ROM code does not set some SDIO slave registers to the defaults - * we need, this function clears/sets some bits. - */ -static void esp32_slave_init_extra(sdmmc_card_t* card) -{ - printf("Initialize some ESP32 SDIO slave registers\n"); - - uint32_t reg_val; - TEST_ESP_OK( slave_slc_reg_read(card, SLCCONF1, ®_val) ); - reg_val &= ~(SLC_SLC0_RX_STITCH_EN | SLC_SLC0_TX_STITCH_EN); - TEST_ESP_OK( slave_slc_reg_write(card, SLCCONF1, reg_val) ); - - TEST_ESP_OK( slave_slc_reg_read(card, SLC0TX_LINK, ®_val) ); - reg_val |= SLC_SLC0_TXLINK_START; - TEST_ESP_OK( slave_slc_reg_write(card, SLC0TX_LINK, reg_val) ); -} - -/** - * ESP32 bootloader implements "SIP" protocol which can be used to exchange - * some commands, events, and data packets between the host and the slave. - * This function sends a SIP command, testing CMD53 block writes along the way. - */ -static void esp32_send_sip_command(sdmmc_card_t* card) -{ - printf("Test block write using CMD53\n"); - const size_t block_size = 512; - uint8_t* data = heap_caps_calloc(1, block_size, MALLOC_CAP_DMA); - struct sip_cmd_bootup { - uint32_t boot_addr; - uint32_t discard_link; - }; - struct sip_cmd_write_reg { - uint32_t addr; - uint32_t val; - }; - struct sip_hdr { - uint8_t fc[2]; - uint16_t len; - uint32_t cmdid; - uint32_t seq; - }; - - struct sip_hdr* hdr = (struct sip_hdr*) data; - size_t len; - -#define SEND_WRITE_REG_CMD - -#ifdef SEND_WRITE_REG_CMD - struct sip_cmd_write_reg *write_reg = (struct sip_cmd_write_reg*) (data + sizeof(*hdr)); - len = sizeof(*hdr) + sizeof(*write_reg); - hdr->cmdid = 3; /* SIP_CMD_WRITE_REG */ - write_reg->addr = GPIO_ENABLE_W1TS_REG; - write_reg->val = BIT(0) | BIT(2) | BIT(4); /* Turn of RGB LEDs on WROVER-KIT */ -#else - struct sip_cmd_bootup *bootup = (struct sip_cmd_bootup*) (data + sizeof(*hdr)); - len = sizeof(*hdr) + sizeof(*bootup); - hdr->cmdid = 5; /* SIP_CMD_BOOTUP */ - bootup->boot_addr = 0x4005a980; /* start_tb_console function in ROM */ - bootup->discard_link = 1; -#endif - hdr->len = len; - - TEST_ESP_OK( sdmmc_io_write_blocks(card, 1, SLC_THRESHOLD_ADDR - len, data, block_size) ); - free(data); -} - -static void test_cmd52_read_write_single_byte(sdmmc_card_t* card) -{ - esp_err_t err; - printf("Write bytes to slave's W0_REG using CMD52\n"); - const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE; - - const uint8_t test_byte_1 = 0xa5; - const uint8_t test_byte_2 = 0xb6; - // used to check Read-After-Write - uint8_t test_byte_1_raw; - uint8_t test_byte_2_raw; - uint8_t val = 0; - err = sdmmc_io_write_byte(card, 1, scratch_area_reg, test_byte_1, &test_byte_1_raw); - TEST_ESP_OK(err); - TEST_ASSERT_EQUAL_UINT8(test_byte_1, test_byte_1_raw); - err = sdmmc_io_write_byte(card, 1, scratch_area_reg + 1, test_byte_2, &test_byte_2_raw); - TEST_ESP_OK(err); - TEST_ASSERT_EQUAL_UINT8(test_byte_2, test_byte_2_raw); - - printf("Read back bytes using CMD52\n"); - TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg, &val)); - TEST_ASSERT_EQUAL_UINT8(test_byte_1, val); - - TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + 1, &val)); - TEST_ASSERT_EQUAL_UINT8(test_byte_2, val); -} - -static void test_cmd53_read_write_multiple_bytes(sdmmc_card_t* card, size_t n_bytes) -{ - printf("Write multiple bytes using CMD53\n"); - const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE; - - uint8_t* src = heap_caps_malloc(512, MALLOC_CAP_DMA); - uint32_t* src_32 = (uint32_t*) src; - - for (size_t i = 0; i < (n_bytes + 3) / 4; ++i) { - src_32[i] = rand(); - } - - TEST_ESP_OK(sdmmc_io_write_bytes(card, 1, scratch_area_reg, src, n_bytes)); - ESP_LOG_BUFFER_HEX(TAG, src, n_bytes); - - printf("Read back using CMD52\n"); - uint8_t* dst = heap_caps_malloc(512, MALLOC_CAP_DMA); - for (size_t i = 0; i < n_bytes; ++i) { - TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + i, &dst[i])); - } - ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes); - TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes); - - printf("Read back using CMD53\n"); - TEST_ESP_OK(sdmmc_io_read_bytes(card, 1, scratch_area_reg, dst, n_bytes)); - ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes); - TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes); - - free(src); - free(dst); -} - - -TEST_CASE("can probe and talk to ESP32 SDIO slave", "[sdio][ignore]") -{ - reset_slave(); - - /* Probe */ - sdmmc_host_t config = SDMMC_HOST_DEFAULT(); - config.flags = SDMMC_HOST_FLAG_1BIT; - config.max_freq_khz = SDMMC_FREQ_PROBING; - - sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); - (sdmmc_host_init()); - (sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config)); - sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); - TEST_ASSERT_NOT_NULL(card); - TEST_ESP_OK(sdmmc_card_init(&config, card)); - sdmmc_card_print_info(stdout, card); - - /* Set up standard SDIO registers */ - sdio_slave_common_init(card); - - srand(0); - for (int repeat = 0; repeat < 4; ++repeat) { - test_cmd52_read_write_single_byte(card); - test_cmd53_read_write_multiple_bytes(card, 1); - test_cmd53_read_write_multiple_bytes(card, 2); - test_cmd53_read_write_multiple_bytes(card, 3); - test_cmd53_read_write_multiple_bytes(card, 4); - test_cmd53_read_write_multiple_bytes(card, 5); - test_cmd53_read_write_multiple_bytes(card, 23); - test_cmd53_read_write_multiple_bytes(card, 24); - } - - sdio_slave_set_blocksize(card, 0, 512); - sdio_slave_set_blocksize(card, 1, 512); - - esp32_slave_init_extra(card); - - esp32_send_sip_command(card); - - TEST_ESP_OK(sdmmc_host_deinit()); - free(card); -} - -#endif //SOC_SDMMC_HOST_SUPPORTED diff --git a/components/sdmmc/test_apps/.build-test-rules.yml b/components/sdmmc/test_apps/.build-test-rules.yml deleted file mode 100644 index 47c051efabe..00000000000 --- a/components/sdmmc/test_apps/.build-test-rules.yml +++ /dev/null @@ -1,11 +0,0 @@ -# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps - -components/sdmmc/test_apps: - disable: - - if: IDF_TARGET in ["esp32h2"] - temporary: true - reason: Console component not supported on H2 yet - disable_test: - - if: IDF_TARGET not in ["esp32", "esp32s2", "esp32c3"] - temporary: true - reason: No runners for other targets yet diff --git a/components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/CMakeLists.txt b/components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/CMakeLists.txt deleted file mode 100644 index 5ba0a138104..00000000000 --- a/components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRCS cmd_sdmmc.c - INCLUDE_DIRS . - PRIV_REQUIRES console sdmmc sdmmc_test_board -) diff --git a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/CMakeLists.txt b/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/CMakeLists.txt deleted file mode 100644 index 16361f9bb6b..00000000000 --- a/components/sdmmc/test_apps/sdmmc_console/components/sdmmc_tests/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -idf_component_register( - SRCS - sdmmc_test_cd_wp_common.c - sdmmc_test_rw_common.c - PRIV_REQUIRES - sdmmc sdmmc_test_board esp_timer unity test_utils - WHOLE_ARCHIVE TRUE -) - -if(CONFIG_SOC_GPSPI_SUPPORTED) - target_sources( - ${COMPONENT_LIB} PRIVATE - sdmmc_test_rw_spi.c - sdmmc_test_begin_end_spi.c - sdmmc_test_probe_spi.c - sdmmc_test_cd_wp_spi.c - ) -endif() - -if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) - target_sources( - ${COMPONENT_LIB} PRIVATE - sdmmc_test_begin_end_sd.c - sdmmc_test_rw_sd.c - sdmmc_test_probe_sd.c - sdmmc_test_cd_wp_sd.c - ) -endif() diff --git a/components/soc/esp32/dport_access.c b/components/soc/esp32/dport_access.c index d37190ab502..95cebd9c42f 100644 --- a/components/soc/esp32/dport_access.c +++ b/components/soc/esp32/dport_access.c @@ -12,7 +12,7 @@ IRAM_ATTR uint32_t esp_dport_access_reg_read(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND +#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND return _DPORT_REG_READ(reg); #else uint32_t apb; @@ -34,7 +34,7 @@ IRAM_ATTR uint32_t esp_dport_access_reg_read(uint32_t reg) IRAM_ATTR uint32_t esp_dport_access_sequence_reg_read(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND +#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND return _DPORT_REG_READ(reg); #else uint32_t apb; diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index e51f180e760..530d6589f57 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -167,6 +167,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_RNG_SUPPORTED + bool + default y + config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL int default 5 @@ -275,6 +279,10 @@ config SOC_CPU_HAS_FPU bool default y +config SOC_HP_CPU_HAS_MULTIPLE_CORES + bool + default y + config SOC_CPU_BREAKPOINTS_NUM int default 2 @@ -283,7 +291,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE int default 64 @@ -311,6 +319,14 @@ config SOC_GPIO_VALID_GPIO_MASK hex default 0xFFFFFFFFFF +config SOC_GPIO_IN_RANGE_MAX + int + default 39 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 33 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0xEF0FEA @@ -651,21 +667,17 @@ config SOC_TIMER_GROUP_SUPPORT_APB bool default y -config SOC_TOUCH_VERSION_1 - bool - default y +config SOC_TOUCH_SENSOR_VERSION + int + default 1 config SOC_TOUCH_SENSOR_NUM int default 10 -config SOC_TOUCH_PAD_MEASURE_WAIT_MAX - hex - default 0xFF - -config SOC_TOUCH_PAD_THRESHOLD_MAX - bool - default n +config SOC_TOUCH_SAMPLER_NUM + int + default 1 config SOC_TWAI_CONTROLLER_NUM int diff --git a/components/soc/esp32/include/soc/dport_access.h b/components/soc/esp32/include/soc/dport_access.h index 823246aa6bb..972cbf49a4c 100644 --- a/components/soc/esp32/include/soc/dport_access.h +++ b/components/soc/esp32/include/soc/dport_access.h @@ -107,7 +107,7 @@ uint32_t esp_dport_access_sequence_reg_read(uint32_t reg); */ void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND +#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND #define DPORT_INTERRUPT_DISABLE() #define DPORT_INTERRUPT_RESTORE() #define DPORT_REG_READ(reg) _DPORT_REG_READ(reg) @@ -128,7 +128,7 @@ void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t __asm__ __volatile__("wsr.ps %0 ; rsync\n" \ : : "a" (__tmp) : "memory" ); \ }while(0) -#endif // defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND +#endif // defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND //get bit or get bits from register #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h index 3091138c392..74b87421dff 100644 --- a/components/soc/esp32/include/soc/dport_reg.h +++ b/components/soc/esp32/include/soc/dport_reg.h @@ -1077,8 +1077,10 @@ #define DPORT_RW_BTMAC_RST BIT(9) #define DPORT_RW_BTLP_RST BIT(10) +//ESP32 should not reset FE in esp_wifi_bt_power_domain_on(). +//The FE of ESP32 is not in the WIFI PD power domain. +//When turning off WIFI PD, the FE will not power down, so phy_wakeup_init() did not rewrite the FE register. #define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \ - DPORT_FE_RST | \ DPORT_WIFIMAC_RST | \ DPORT_BTBB_RST | \ DPORT_BTMAC_RST | \ diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 05e2a3fb7ee..696a057a8be 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -31,7 +31,7 @@ #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) -#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && SOC_DPORT_WORKAROUND +#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE ) && SOC_DPORT_WORKAROUND #define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); #else #define ASSERT_IF_DPORT_REG(_r, OP) diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 7c83fa99490..917a8e34315 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -32,9 +32,7 @@ * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` */ #pragma once @@ -101,6 +99,7 @@ #define SOC_MPU_SUPPORTED 1 #define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 +#define SOC_RNG_SUPPORTED 1 #if SOC_CAPS_ECO_VER < 200 #define SOC_DPORT_WORKAROUND 1 @@ -154,10 +153,11 @@ #define SOC_CPU_CORES_NUM 2 #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FPU 1 +#define SOC_HP_CPU_HAS_MULTIPLE_CORES 1 // Convenience boolean macro used to determine if a target has multiple cores. -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_CHAN_NUM 2 @@ -178,6 +178,9 @@ // GPIO >= 34 are input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39)) +#define SOC_GPIO_IN_RANGE_MAX 39 +#define SOC_GPIO_OUT_RANGE_MAX 33 + // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL @@ -313,11 +316,10 @@ #define SOC_TIMER_GROUP_SUPPORT_APB (1) /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ -#define SOC_TOUCH_VERSION_1 (1) /*! +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** AES_KEY_0_REG register + * Key material key_0 configure register + */ +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_1_REG register + * Key material key_1 configure register + */ +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) +/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ +#define AES_KEY_1 0xFFFFFFFFU +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFFU +#define AES_KEY_1_S 0 + +/** AES_KEY_2_REG register + * Key material key_2 configure register + */ +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) +/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ +#define AES_KEY_2 0xFFFFFFFFU +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFFU +#define AES_KEY_2_S 0 + +/** AES_KEY_3_REG register + * Key material key_3 configure register + */ +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) +/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ +#define AES_KEY_3 0xFFFFFFFFU +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFFU +#define AES_KEY_3_S 0 + +/** AES_KEY_4_REG register + * Key material key_4 configure register + */ +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) +/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ +#define AES_KEY_4 0xFFFFFFFFU +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFFU +#define AES_KEY_4_S 0 + +/** AES_KEY_5_REG register + * Key material key_5 configure register + */ +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) +/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ +#define AES_KEY_5 0xFFFFFFFFU +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFFU +#define AES_KEY_5_S 0 + +/** AES_KEY_6_REG register + * Key material key_6 configure register + */ +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) +/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ +#define AES_KEY_6 0xFFFFFFFFU +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFFU +#define AES_KEY_6_S 0 + +/** AES_KEY_7_REG register + * Key material key_7 configure register + */ +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) +/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ +#define AES_KEY_7 0xFFFFFFFFU +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFFU +#define AES_KEY_7_S 0 + +/** AES_TEXT_IN_0_REG register + * source text material text_in_0 configure register + */ +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_1_REG register + * source text material text_in_1 configure register + */ +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) +/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ +#define AES_TEXT_IN_1 0xFFFFFFFFU +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFFU +#define AES_TEXT_IN_1_S 0 + +/** AES_TEXT_IN_2_REG register + * source text material text_in_2 configure register + */ +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) +/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ +#define AES_TEXT_IN_2 0xFFFFFFFFU +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFFU +#define AES_TEXT_IN_2_S 0 + +/** AES_TEXT_IN_3_REG register + * source text material text_in_3 configure register + */ +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) +/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ +#define AES_TEXT_IN_3 0xFFFFFFFFU +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFFU +#define AES_TEXT_IN_3_S 0 + +/** AES_TEXT_OUT_0_REG register + * result text material text_out_0 configure register + */ +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_1_REG register + * result text material text_out_1 configure register + */ +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) +/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ +#define AES_TEXT_OUT_1 0xFFFFFFFFU +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFFU +#define AES_TEXT_OUT_1_S 0 + +/** AES_TEXT_OUT_2_REG register + * result text material text_out_2 configure register + */ +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) +/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ +#define AES_TEXT_OUT_2 0xFFFFFFFFU +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFFU +#define AES_TEXT_OUT_2_S 0 + +/** AES_TEXT_OUT_3_REG register + * result text material text_out_3 configure register + */ +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) +/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ +#define AES_TEXT_OUT_3 0xFFFFFFFFU +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFFU +#define AES_TEXT_OUT_3_S 0 + +/** AES_MODE_REG register + * AES Mode register + */ +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) +/** AES_MODE : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ +#define AES_MODE 0x00000007U +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007U +#define AES_MODE_S 0 + +/** AES_TRIGGER_REG register + * AES trigger register + */ +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) +/** AES_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001U +#define AES_TRIGGER_S 0 + +/** AES_STATE_REG register + * AES state register + */ +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) +/** AES_STATE : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ +#define AES_STATE 0x00000003U +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003U +#define AES_STATE_S 0 + +/** AES_IV_MEM register + * The memory that stores initialization vector + */ +#define AES_IV_MEM (DR_REG_AES_BASE + 0x50) +#define AES_IV_MEM_SIZE_BYTES 16 + +/** AES_H_MEM register + * The memory that stores GCM hash subkey + */ +#define AES_H_MEM (DR_REG_AES_BASE + 0x60) +#define AES_H_MEM_SIZE_BYTES 16 + +/** AES_J0_MEM register + * The memory that stores J0 + */ +#define AES_J0_MEM (DR_REG_AES_BASE + 0x70) +#define AES_J0_MEM_SIZE_BYTES 16 + +/** AES_T0_MEM register + * The memory that stores T0 + */ +#define AES_T0_MEM (DR_REG_AES_BASE + 0x80) +#define AES_T0_MEM_SIZE_BYTES 16 + +/** AES_DMA_ENABLE_REG register + * DMA-AES working mode register + */ +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) +/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001U +#define AES_DMA_ENABLE_S 0 + +/** AES_BLOCK_MODE_REG register + * AES cipher block mode register + */ +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) +/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ +#define AES_BLOCK_MODE 0x00000007U +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007U +#define AES_BLOCK_MODE_S 0 + +/** AES_BLOCK_NUM_REG register + * AES block number register + */ +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) +/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ +#define AES_BLOCK_NUM 0xFFFFFFFFU +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_BLOCK_NUM_S 0 + +/** AES_INC_SEL_REG register + * Standard incrementing function configure register + */ +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) +/** AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001U +#define AES_INC_SEL_S 0 + +/** AES_INT_CLEAR_REG register + * AES Interrupt clear register + */ +#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac) +/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ +#define AES_INT_CLEAR (BIT(0)) +#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S) +#define AES_INT_CLEAR_V 0x00000001U +#define AES_INT_CLEAR_S 0 + +/** AES_INT_ENA_REG register + * AES Interrupt enable register + */ +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) +/** AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001U +#define AES_INT_ENA_S 0 + +/** AES_DATE_REG register + * AES version control register + */ +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) +/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ +#define AES_DATE 0x3FFFFFFFU +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFFU +#define AES_DATE_S 0 + +/** AES_DMA_EXIT_REG register + * AES-DMA exit config + */ +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) +/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001U +#define AES_DMA_EXIT_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/aes_struct.h b/components/soc/esp32c5/include/soc/aes_struct.h new file mode 100644 index 00000000000..c337d9ceec6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/aes_struct.h @@ -0,0 +1,438 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: key register */ +/** Type of key_0 register + * Key material key_0 configure register + */ +typedef union { + struct { + /** key_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ + uint32_t key_0:32; + }; + uint32_t val; +} aes_key_0_reg_t; + +/** Type of key_1 register + * Key material key_1 configure register + */ +typedef union { + struct { + /** key_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ + uint32_t key_1:32; + }; + uint32_t val; +} aes_key_1_reg_t; + +/** Type of key_2 register + * Key material key_2 configure register + */ +typedef union { + struct { + /** key_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ + uint32_t key_2:32; + }; + uint32_t val; +} aes_key_2_reg_t; + +/** Type of key_3 register + * Key material key_3 configure register + */ +typedef union { + struct { + /** key_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ + uint32_t key_3:32; + }; + uint32_t val; +} aes_key_3_reg_t; + +/** Type of key_4 register + * Key material key_4 configure register + */ +typedef union { + struct { + /** key_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ + uint32_t key_4:32; + }; + uint32_t val; +} aes_key_4_reg_t; + +/** Type of key_5 register + * Key material key_5 configure register + */ +typedef union { + struct { + /** key_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ + uint32_t key_5:32; + }; + uint32_t val; +} aes_key_5_reg_t; + +/** Type of key_6 register + * Key material key_6 configure register + */ +typedef union { + struct { + /** key_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ + uint32_t key_6:32; + }; + uint32_t val; +} aes_key_6_reg_t; + +/** Type of key_7 register + * Key material key_7 configure register + */ +typedef union { + struct { + /** key_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ + uint32_t key_7:32; + }; + uint32_t val; +} aes_key_7_reg_t; + + +/** Group: text in register */ +/** Type of text_in_0 register + * source text material text_in_0 configure register + */ +typedef union { + struct { + /** text_in_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ + uint32_t text_in_0:32; + }; + uint32_t val; +} aes_text_in_0_reg_t; + +/** Type of text_in_1 register + * source text material text_in_1 configure register + */ +typedef union { + struct { + /** text_in_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ + uint32_t text_in_1:32; + }; + uint32_t val; +} aes_text_in_1_reg_t; + +/** Type of text_in_2 register + * source text material text_in_2 configure register + */ +typedef union { + struct { + /** text_in_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ + uint32_t text_in_2:32; + }; + uint32_t val; +} aes_text_in_2_reg_t; + +/** Type of text_in_3 register + * source text material text_in_3 configure register + */ +typedef union { + struct { + /** text_in_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ + uint32_t text_in_3:32; + }; + uint32_t val; +} aes_text_in_3_reg_t; + + +/** Group: text out register */ +/** Type of text_out_0 register + * result text material text_out_0 configure register + */ +typedef union { + struct { + /** text_out_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ + uint32_t text_out_0:32; + }; + uint32_t val; +} aes_text_out_0_reg_t; + +/** Type of text_out_1 register + * result text material text_out_1 configure register + */ +typedef union { + struct { + /** text_out_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ + uint32_t text_out_1:32; + }; + uint32_t val; +} aes_text_out_1_reg_t; + +/** Type of text_out_2 register + * result text material text_out_2 configure register + */ +typedef union { + struct { + /** text_out_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ + uint32_t text_out_2:32; + }; + uint32_t val; +} aes_text_out_2_reg_t; + +/** Type of text_out_3 register + * result text material text_out_3 configure register + */ +typedef union { + struct { + /** text_out_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ + uint32_t text_out_3:32; + }; + uint32_t val; +} aes_text_out_3_reg_t; + + +/** Group: Configuration register */ +/** Type of mode register + * AES Mode register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_mode_reg_t; + +/** Type of block_mode register + * AES cipher block mode register + */ +typedef union { + struct { + /** block_mode : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ + uint32_t block_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_block_mode_reg_t; + +/** Type of block_num register + * AES block number register + */ +typedef union { + struct { + /** block_num : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ + uint32_t block_num:32; + }; + uint32_t val; +} aes_block_num_reg_t; + +/** Type of inc_sel register + * Standard incrementing function configure register + */ +typedef union { + struct { + /** inc_sel : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ + uint32_t inc_sel:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_inc_sel_reg_t; + + +/** Group: Control/Status register */ +/** Type of trigger register + * AES trigger register + */ +typedef union { + struct { + /** trigger : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ + uint32_t trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_trigger_reg_t; + +/** Type of state register + * AES state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} aes_state_reg_t; + +/** Type of dma_enable register + * DMA-AES working mode register + */ +typedef union { + struct { + /** dma_enable : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ + uint32_t dma_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_enable_reg_t; + +/** Type of dma_exit register + * AES-DMA exit config + */ +typedef union { + struct { + /** dma_exit : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ + uint32_t dma_exit:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_exit_reg_t; + + +/** Group: memory type */ + +/** Group: interrupt register */ +/** Type of int_clear register + * AES Interrupt clear register + */ +typedef union { + struct { + /** int_clear : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ + uint32_t int_clear:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_clear_reg_t; + +/** Type of int_ena register + * AES Interrupt enable register + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_ena_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * AES version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} aes_date_reg_t; + + +typedef struct aes_dev_t { + volatile aes_key_0_reg_t key_0; + volatile aes_key_1_reg_t key_1; + volatile aes_key_2_reg_t key_2; + volatile aes_key_3_reg_t key_3; + volatile aes_key_4_reg_t key_4; + volatile aes_key_5_reg_t key_5; + volatile aes_key_6_reg_t key_6; + volatile aes_key_7_reg_t key_7; + volatile aes_text_in_0_reg_t text_in_0; + volatile aes_text_in_1_reg_t text_in_1; + volatile aes_text_in_2_reg_t text_in_2; + volatile aes_text_in_3_reg_t text_in_3; + volatile aes_text_out_0_reg_t text_out_0; + volatile aes_text_out_1_reg_t text_out_1; + volatile aes_text_out_2_reg_t text_out_2; + volatile aes_text_out_3_reg_t text_out_3; + volatile aes_mode_reg_t mode; + uint32_t reserved_044; + volatile aes_trigger_reg_t trigger; + volatile aes_state_reg_t state; + volatile uint32_t iv[4]; + volatile uint32_t h[4]; + volatile uint32_t j0[4]; + volatile uint32_t t0[4]; + volatile aes_dma_enable_reg_t dma_enable; + volatile aes_block_mode_reg_t block_mode; + volatile aes_block_num_reg_t block_num; + volatile aes_inc_sel_reg_t inc_sel; + uint32_t reserved_0a0[3]; + volatile aes_int_clear_reg_t int_clear; + volatile aes_int_ena_reg_t int_ena; + volatile aes_date_reg_t date; + volatile aes_dma_exit_reg_t dma_exit; +} aes_dev_t; + +extern aes_dev_t AES; + +#ifndef __cplusplus +_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/include/soc/apb_saradc_reg.h new file mode 100644 index 00000000000..179fe6a7d6e --- /dev/null +++ b/components/soc/esp32c5/include/soc/apb_saradc_reg.h @@ -0,0 +1,813 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** APB_SARADC_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) +/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ +#define APB_SARADC_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) +#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U +#define APB_SARADC_SARADC_START_FORCE_S 0 +/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ +#define APB_SARADC_SARADC_START (BIT(1)) +#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) +#define APB_SARADC_SARADC_START_V 0x00000001U +#define APB_SARADC_SARADC_START_S 1 +/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ +#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) +#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U +#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 +/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ +#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) +#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 +/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ +#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) +#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 +/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 +/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ +#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) +#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 +/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ +#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29)) +#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S) +#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U +#define APB_SARADC_SARADC2_PWDET_DRV_S 29 +/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 + +/** APB_SARADC_CTRL2_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) +/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ +#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) +#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 +/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) +#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR1_INV_S 9 +/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) +#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR2_INV_S 10 +/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ +#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) +#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_S 12 +/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ +#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) +#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U +#define APB_SARADC_SARADC_TIMER_EN_S 24 + +/** APB_SARADC_FILTER_CTRL1_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) +/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26 +/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29 + +/** APB_SARADC_SAR_PATT_TAB1_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) +/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 + +/** APB_SARADC_SAR_PATT_TAB2_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) +/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 + +/** APB_SARADC_ONETIME_SAMPLE_REG register + * digital saradc configure register + */ +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) +/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ +#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) +#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ +#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) +#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 +/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ +#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) +#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U +#define APB_SARADC_SARADC_ONETIME_START_S 29 +/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ +#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 +/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ +#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 + +/** APB_SARADC_ARB_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) +/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 +/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 + +/** APB_SARADC_FILTER_CTRL0_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18 +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22 +/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ +#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S) +#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U +#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31 + +/** APB_SARADC_SAR1DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) +/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ +#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S) +#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_S 0 + +/** APB_SARADC_SAR2DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) +/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ +#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S) +#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_S 0 + +/** APB_SARADC_THRES0_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) +/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18 + +/** APB_SARADC_THRES1_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) +/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18 + +/** APB_SARADC_THRES_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) +/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ +#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27 +/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ +#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S) +#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_EN_S 30 +/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ +#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S) +#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_EN_S 31 + +/** APB_SARADC_INT_ENA_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) +/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31 + +/** APB_SARADC_INT_RAW_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) +/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31 + +/** APB_SARADC_INT_ST_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) +/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31 + +/** APB_SARADC_INT_CLR_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) +/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31 + +/** APB_SARADC_DMA_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) +/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 +/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) +#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U +#define APB_SARADC_APB_ADC_TRANS_S 31 + +/** APB_SARADC_CLKM_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) +/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S) +#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_S 0 +/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ +#define APB_SARADC_CLKM_DIV_B 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S) +#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_S 8 +/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ +#define APB_SARADC_CLKM_DIV_A 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S) +#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_S 14 +/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; + * reg clk en + */ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) +#define APB_SARADC_CLK_EN_V 0x00000001U +#define APB_SARADC_CLK_EN_S 20 +/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ +#define APB_SARADC_CLK_SEL 0x00000003U +#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S) +#define APB_SARADC_CLK_SEL_V 0x00000003U +#define APB_SARADC_CLK_SEL_S 21 + +/** APB_SARADC_APB_TSENS_CTRL_REG register + * digital tsens configure register + */ +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) +/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ +#define APB_SARADC_TSENS_OUT 0x000000FFU +#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S) +#define APB_SARADC_TSENS_OUT_V 0x000000FFU +#define APB_SARADC_TSENS_OUT_S 0 +/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ +#define APB_SARADC_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S) +#define APB_SARADC_TSENS_IN_INV_V 0x00000001U +#define APB_SARADC_TSENS_IN_INV_S 13 +/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ +#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S) +#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_S 14 +/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ +#define APB_SARADC_TSENS_PU (BIT(22)) +#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S) +#define APB_SARADC_TSENS_PU_V 0x00000001U +#define APB_SARADC_TSENS_PU_S 22 + +/** APB_SARADC_TSENS_CTRL2_REG register + * digital tsens configure register + */ +#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) +/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ +#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) +#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U +#define APB_SARADC_TSENS_CLK_SEL_S 15 + +/** APB_SARADC_CALI_REG register + * digital saradc configure register + */ +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) +/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ +#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S) +#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_S 0 + +/** APB_TSENS_WAKE_REG register + * digital tsens configure register + */ +#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64) +/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ +#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S) +#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_S 0 +/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ +#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S) +#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_S 8 +/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ +#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16)) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16 +/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ +#define APB_SARADC_WAKEUP_MODE (BIT(17)) +#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S) +#define APB_SARADC_WAKEUP_MODE_V 0x00000001U +#define APB_SARADC_WAKEUP_MODE_S 17 +/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ +#define APB_SARADC_WAKEUP_EN (BIT(18)) +#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S) +#define APB_SARADC_WAKEUP_EN_V 0x00000001U +#define APB_SARADC_WAKEUP_EN_S 18 + +/** APB_TSENS_SAMPLE_REG register + * digital tsens configure register + */ +#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68) +/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ +#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S) +#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_S 0 +/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0; + * HW sample en + */ +#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16)) +#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S) +#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U +#define APB_SARADC_TSENS_SAMPLE_EN_S 16 + +/** APB_SARADC_CTRL_DATE_REG register + * version + */ +#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) +/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; + * version + */ +#define APB_SARADC_DATE 0xFFFFFFFFU +#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) +#define APB_SARADC_DATE_V 0xFFFFFFFFU +#define APB_SARADC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/include/soc/apb_saradc_struct.h new file mode 100644 index 00000000000..9f89d6c7292 --- /dev/null +++ b/components/soc/esp32c5/include/soc/apb_saradc_struct.h @@ -0,0 +1,696 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Register */ +/** Type of saradc_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ + uint32_t saradc_saradc_start_force:1; + /** saradc_saradc_start : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ + uint32_t saradc_saradc_start:1; + uint32_t reserved_2:4; + /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ + uint32_t saradc_saradc_sar_clk_gated:1; + /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + uint32_t saradc_saradc_sar_clk_div:8; + /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ + uint32_t saradc_saradc_sar_patt_len:3; + uint32_t reserved_18:5; + /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + uint32_t saradc_saradc_sar_patt_p_clear:1; + uint32_t reserved_24:3; + /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ + uint32_t saradc_saradc_xpd_sar_force:2; + /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ + uint32_t saradc_saradc2_pwdet_drv:1; + /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ + uint32_t saradc_saradc_wait_arb_cycle:2; + }; + uint32_t val; +} apb_saradc_ctrl_reg_t; + +/** Type of saradc_ctrl2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ + uint32_t saradc_saradc_meas_num_limit:1; + /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ + uint32_t saradc_saradc_max_meas_num:8; + /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar1_inv:1; + /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar2_inv:1; + uint32_t reserved_11:1; + /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ + uint32_t saradc_saradc_timer_target:12; + /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ + uint32_t saradc_saradc_timer_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} apb_saradc_ctrl2_reg_t; + +/** Type of saradc_filter_ctrl1 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ + uint32_t saradc_apb_saradc_filter_factor1:3; + /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ + uint32_t saradc_apb_saradc_filter_factor0:3; + }; + uint32_t val; +} apb_saradc_filter_ctrl1_reg_t; + +/** Type of saradc_sar_patt_tab1 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab1_reg_t; + +/** Type of saradc_sar_patt_tab2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab2_reg_t; + +/** Type of saradc_onetime_sample register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ + uint32_t saradc_saradc_onetime_atten:2; + /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ + uint32_t saradc_saradc_onetime_channel:4; + /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ + uint32_t saradc_saradc_onetime_start:1; + /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ + uint32_t saradc_saradc2_onetime_sample:1; + /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ + uint32_t saradc_saradc1_onetime_sample:1; + }; + uint32_t val; +} apb_saradc_onetime_sample_reg_t; + +/** Type of saradc_arb_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ + uint32_t saradc_adc_arb_apb_force:1; + /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ + uint32_t saradc_adc_arb_rtc_force:1; + /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ + uint32_t saradc_adc_arb_wifi_force:1; + /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ + uint32_t saradc_adc_arb_grant_force:1; + /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ + uint32_t saradc_adc_arb_apb_priority:2; + /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ + uint32_t saradc_adc_arb_rtc_priority:2; + /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ + uint32_t saradc_adc_arb_wifi_priority:2; + /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ + uint32_t saradc_adc_arb_fix_priority:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} apb_saradc_arb_ctrl_reg_t; + +/** Type of saradc_filter_ctrl0 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel1:4; + /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel0:4; + uint32_t reserved_26:5; + /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ + uint32_t saradc_apb_saradc_filter_reset:1; + }; + uint32_t val; +} apb_saradc_filter_ctrl0_reg_t; + +/** Type of saradc_sar1data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ + uint32_t saradc_apb_saradc1_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar1data_status_reg_t; + +/** Type of saradc_sar2data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ + uint32_t saradc_apb_saradc2_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar2data_status_reg_t; + +/** Type of saradc_thres0_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ + uint32_t saradc_apb_saradc_thres0_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_high:13; + /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres0_ctrl_reg_t; + +/** Type of saradc_thres1_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ + uint32_t saradc_apb_saradc_thres1_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_high:13; + /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres1_ctrl_reg_t; + +/** Type of saradc_thres_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ + uint32_t saradc_apb_saradc_thres_all_en:1; + uint32_t reserved_28:2; + /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ + uint32_t saradc_apb_saradc_thres1_en:1; + /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ + uint32_t saradc_apb_saradc_thres0_en:1; + }; + uint32_t val; +} apb_saradc_thres_ctrl_reg_t; + +/** Type of saradc_int_ena register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ + uint32_t saradc_apb_saradc_tsens_int_ena:1; + /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_low_int_ena:1; + /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_low_int_ena:1; + /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_high_int_ena:1; + /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_high_int_ena:1; + /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ + uint32_t saradc_apb_saradc2_done_int_ena:1; + /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ + uint32_t saradc_apb_saradc1_done_int_ena:1; + }; + uint32_t val; +} apb_saradc_int_ena_reg_t; + +/** Type of saradc_int_raw register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ + uint32_t saradc_apb_saradc_tsens_int_raw:1; + /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_low_int_raw:1; + /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_low_int_raw:1; + /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_high_int_raw:1; + /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_high_int_raw:1; + /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ + uint32_t saradc_apb_saradc2_done_int_raw:1; + /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ + uint32_t saradc_apb_saradc1_done_int_raw:1; + }; + uint32_t val; +} apb_saradc_int_raw_reg_t; + +/** Type of saradc_int_st register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ + uint32_t saradc_apb_saradc_tsens_int_st:1; + /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ + uint32_t saradc_apb_saradc_thres1_low_int_st:1; + /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ + uint32_t saradc_apb_saradc_thres0_low_int_st:1; + /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ + uint32_t saradc_apb_saradc_thres1_high_int_st:1; + /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ + uint32_t saradc_apb_saradc_thres0_high_int_st:1; + /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ + uint32_t saradc_apb_saradc2_done_int_st:1; + /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ + uint32_t saradc_apb_saradc1_done_int_st:1; + }; + uint32_t val; +} apb_saradc_int_st_reg_t; + +/** Type of saradc_int_clr register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ + uint32_t saradc_apb_saradc_tsens_int_clr:1; + /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_low_int_clr:1; + /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_low_int_clr:1; + /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_high_int_clr:1; + /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_high_int_clr:1; + /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ + uint32_t saradc_apb_saradc2_done_int_clr:1; + /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ + uint32_t saradc_apb_saradc1_done_int_clr:1; + }; + uint32_t val; +} apb_saradc_int_clr_reg_t; + +/** Type of saradc_dma_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ + uint32_t saradc_apb_adc_eof_num:16; + uint32_t reserved_16:14; + /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ + uint32_t saradc_apb_adc_reset_fsm:1; + /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ + uint32_t saradc_apb_adc_trans:1; + }; + uint32_t val; +} apb_saradc_dma_conf_reg_t; + +/** Type of saradc_clkm_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clk_en : R/W; bitpos: [20]; default: 0; + * reg clk en + */ + uint32_t saradc_clk_en:1; + /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ + uint32_t saradc_clk_sel:2; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_clkm_conf_reg_t; + +/** Type of saradc_apb_tsens_ctrl register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ + uint32_t saradc_tsens_out:8; + uint32_t reserved_8:5; + /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ + uint32_t saradc_tsens_in_inv:1; + /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ + uint32_t saradc_tsens_clk_div:8; + /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ + uint32_t saradc_tsens_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_apb_tsens_ctrl_reg_t; + +/** Type of saradc_tsens_ctrl2 register + * digital tsens configure register + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ + uint32_t saradc_tsens_clk_sel:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} apb_saradc_tsens_ctrl2_reg_t; + +/** Type of saradc_cali register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ + uint32_t saradc_apb_saradc_cali_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_cali_reg_t; + +/** Type of tsens_wake register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ + uint32_t saradc_wakeup_th_low:8; + /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ + uint32_t saradc_wakeup_th_high:8; + /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ + uint32_t saradc_wakeup_over_upper_th:1; + /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ + uint32_t saradc_wakeup_mode:1; + /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ + uint32_t saradc_wakeup_en:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} apb_tsens_wake_reg_t; + +/** Type of tsens_sample register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ + uint32_t saradc_tsens_sample_rate:16; + /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0; + * HW sample en + */ + uint32_t saradc_tsens_sample_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_tsens_sample_reg_t; + +/** Type of saradc_ctrl_date register + * version + */ +typedef union { + struct { + /** saradc_date : R/W; bitpos: [31:0]; default: 35676736; + * version + */ + uint32_t saradc_date:32; + }; + uint32_t val; +} apb_saradc_ctrl_date_reg_t; + + +typedef struct apb_dev_t { + volatile apb_saradc_ctrl_reg_t saradc_ctrl; + volatile apb_saradc_ctrl2_reg_t saradc_ctrl2; + volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1; + uint32_t reserved_00c[3]; + volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; + volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; + volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample; + volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl; + volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0; + volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status; + volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status; + volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl; + volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl; + volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl; + volatile apb_saradc_int_ena_reg_t saradc_int_ena; + volatile apb_saradc_int_raw_reg_t saradc_int_raw; + volatile apb_saradc_int_st_reg_t saradc_int_st; + volatile apb_saradc_int_clr_reg_t saradc_int_clr; + volatile apb_saradc_dma_conf_reg_t saradc_dma_conf; + volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; + volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2; + volatile apb_saradc_cali_reg_t saradc_cali; + volatile apb_tsens_wake_reg_t tsens_wake; + volatile apb_tsens_sample_reg_t tsens_sample; + uint32_t reserved_06c[228]; + volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date; +} apb_dev_t; + +extern apb_dev_t APB_SARADC; + +#ifndef __cplusplus +_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/assist_debug_reg.h b/components/soc/esp32c5/include/soc/assist_debug_reg.h new file mode 100644 index 00000000000..cda7314f216 --- /dev/null +++ b/components/soc/esp32c5/include/soc/assist_debug_reg.h @@ -0,0 +1,582 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register + * core0 monitor enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 + +/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register + * core0 monitor interrupt status register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 + +/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register + * core0 monitor interrupt enable register + */ +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 + +/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register + * core0 monitor interrupt clr register + */ +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register + * core0 area pc status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) +/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register + * core0 area sp status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) +/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register + * stack min value + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) +/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register + * stack max value + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) +/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_PC_REG register + * stack monitor pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) +/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register + * record enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) +/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 +/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 + +/** ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78) +/** ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0; + * need desc + */ +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_M (ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V << ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S) +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S 0 + +/** ASSIST_DEBUG_CLOCK_GATE_REG register + * clock register + */ +#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c) +/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ +#define ASSIST_DEBUG_CLK_EN (BIT(0)) +#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) +#define ASSIST_DEBUG_CLK_EN_V 0x00000001U +#define ASSIST_DEBUG_CLK_EN_S 0 + +/** ASSIST_DEBUG_DATE_REG register + * version register + */ +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) +/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35725648; + * version register + */ +#define ASSIST_DEBUG_DATE 0x0FFFFFFFU +#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S) +#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU +#define ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/assist_debug_struct.h b/components/soc/esp32c5/include/soc/assist_debug_struct.h new file mode 100644 index 00000000000..d4c634d0608 --- /dev/null +++ b/components/soc/esp32c5/include/soc/assist_debug_struct.h @@ -0,0 +1,549 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: monitor configuration registers */ +/** Type of core_0_montr_ena register + * core0 monitor enable configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ + uint32_t core_0_area_dram0_0_rd_ena:1; + /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ + uint32_t core_0_area_dram0_0_wr_ena:1; + /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ + uint32_t core_0_area_dram0_1_rd_ena:1; + /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ + uint32_t core_0_area_dram0_1_wr_ena:1; + /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ + uint32_t core_0_area_pif_0_rd_ena:1; + /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ + uint32_t core_0_area_pif_0_wr_ena:1; + /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ + uint32_t core_0_area_pif_1_rd_ena:1; + /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ + uint32_t core_0_area_pif_1_wr_ena:1; + /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ + uint32_t core_0_sp_spill_min_ena:1; + /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ + uint32_t core_0_sp_spill_max_ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_montr_ena_reg_t; + +/** Type of core_0_area_dram0_0_min register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ + uint32_t core_0_area_dram0_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_min_reg_t; + +/** Type of core_0_area_dram0_0_max register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ + uint32_t core_0_area_dram0_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_max_reg_t; + +/** Type of core_0_area_dram0_1_min register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ + uint32_t core_0_area_dram0_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_min_reg_t; + +/** Type of core_0_area_dram0_1_max register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ + uint32_t core_0_area_dram0_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_max_reg_t; + +/** Type of core_0_area_pif_0_min register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ + uint32_t core_0_area_pif_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_min_reg_t; + +/** Type of core_0_area_pif_0_max register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ + uint32_t core_0_area_pif_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_max_reg_t; + +/** Type of core_0_area_pif_1_min register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ + uint32_t core_0_area_pif_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_min_reg_t; + +/** Type of core_0_area_pif_1_max register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ + uint32_t core_0_area_pif_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_max_reg_t; + +/** Type of core_0_area_pc register + * core0 area pc status register + */ +typedef union { + struct { + /** core_0_area_pc : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ + uint32_t core_0_area_pc:32; + }; + uint32_t val; +} assist_debug_core_0_area_pc_reg_t; + +/** Type of core_0_area_sp register + * core0 area sp status register + */ +typedef union { + struct { + /** core_0_area_sp : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ + uint32_t core_0_area_sp:32; + }; + uint32_t val; +} assist_debug_core_0_area_sp_reg_t; + +/** Type of core_0_sp_min register + * stack min value + */ +typedef union { + struct { + /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ + uint32_t core_0_sp_min:32; + }; + uint32_t val; +} assist_debug_core_0_sp_min_reg_t; + +/** Type of core_0_sp_max register + * stack max value + */ +typedef union { + struct { + /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ + uint32_t core_0_sp_max:32; + }; + uint32_t val; +} assist_debug_core_0_sp_max_reg_t; + +/** Type of core_0_sp_pc register + * stack monitor pc status register + */ +typedef union { + struct { + /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ + uint32_t core_0_sp_pc:32; + }; + uint32_t val; +} assist_debug_core_0_sp_pc_reg_t; + + +/** Group: interrupt configuration register */ +/** Type of core_0_intr_raw register + * core0 monitor interrupt status register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ + uint32_t core_0_area_dram0_0_rd_raw:1; + /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ + uint32_t core_0_area_dram0_0_wr_raw:1; + /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ + uint32_t core_0_area_dram0_1_rd_raw:1; + /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ + uint32_t core_0_area_dram0_1_wr_raw:1; + /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ + uint32_t core_0_area_pif_0_rd_raw:1; + /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ + uint32_t core_0_area_pif_0_wr_raw:1; + /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ + uint32_t core_0_area_pif_1_rd_raw:1; + /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ + uint32_t core_0_area_pif_1_wr_raw:1; + /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ + uint32_t core_0_sp_spill_min_raw:1; + /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ + uint32_t core_0_sp_spill_max_raw:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_intr_raw_reg_t; + +/** Type of core_0_intr_ena register + * core0 monitor interrupt enable register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_rd_intr_ena:1; + /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_wr_intr_ena:1; + /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_rd_intr_ena:1; + /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_wr_intr_ena:1; + /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ + uint32_t core_0_area_pif_0_rd_intr_ena:1; + /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ + uint32_t core_0_area_pif_0_wr_intr_ena:1; + /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ + uint32_t core_0_area_pif_1_rd_intr_ena:1; + /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ + uint32_t core_0_area_pif_1_wr_intr_ena:1; + /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_min_intr_ena:1; + /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_max_intr_ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_intr_ena_reg_t; + +/** Type of core_0_intr_clr register + * core0 monitor interrupt clr register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_rd_clr:1; + /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_wr_clr:1; + /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_rd_clr:1; + /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_wr_clr:1; + /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ + uint32_t core_0_area_pif_0_rd_clr:1; + /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ + uint32_t core_0_area_pif_0_wr_clr:1; + /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ + uint32_t core_0_area_pif_1_rd_clr:1; + /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ + uint32_t core_0_area_pif_1_wr_clr:1; + /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_min_clr:1; + /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_max_clr:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_intr_clr_reg_t; + + +/** Group: pc reording configuration register */ +/** Type of core_0_rcd_en register + * record enable configuration register + */ +typedef union { + struct { + /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ + uint32_t core_0_rcd_recorden:1; + /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ + uint32_t core_0_rcd_pdebugen:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_rcd_en_reg_t; + + +/** Group: pc reording status register */ +/** Type of core_0_rcd_pdebugpc register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ + uint32_t core_0_rcd_pdebugpc:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugpc_reg_t; + +/** Type of core_0_rcd_pdebugsp register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ + uint32_t core_0_rcd_pdebugsp:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugsp_reg_t; + + +/** Group: cpu status registers */ +/** Type of core_0_lastpc_before_exception register + * cpu status register + */ +typedef union { + struct { + /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ + uint32_t core_0_lastpc_before_exc:32; + }; + uint32_t val; +} assist_debug_core_0_lastpc_before_exception_reg_t; + +/** Type of core_0_debug_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_debug_mode : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ + uint32_t core_0_debug_mode:1; + /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ + uint32_t core_0_debug_module_active:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_debug_mode_reg_t; + +/** Type of core_0_dmactive_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_dmactive_lpcore : RO; bitpos: [0]; default: 0; + * need desc + */ + uint32_t core_0_dmactive_lpcore:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_core_0_dmactive_mode_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * clock register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_clock_gate_reg_t; + +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725648; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} assist_debug_date_reg_t; + + +typedef struct assist_debug_dev_t { + volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena; + volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; + volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; + volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; + volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; + volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; + volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; + volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; + volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; + volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; + volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + uint32_t reserved_050[8]; + volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; + volatile assist_debug_core_0_dmactive_mode_reg_t core_0_dmactive_mode; + volatile assist_debug_clock_gate_reg_t clock_gate; + uint32_t reserved_080[223]; + volatile assist_debug_date_reg_t date; +} assist_debug_dev_t; + +extern assist_debug_dev_t ASSIST_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/include/soc/bitscrambler_reg.h new file mode 100644 index 00000000000..44bfc3c8745 --- /dev/null +++ b/components/soc/esp32c5/include/soc/bitscrambler_reg.h @@ -0,0 +1,481 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** BITSCRAMBLER_TX_INST_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0) +/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ +#define BITSCRAMBLER_TX_INST_IDX 0x00000007U +#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S) +#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U +#define BITSCRAMBLER_TX_INST_IDX_S 0 +/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ +#define BITSCRAMBLER_TX_INST_POS 0x0000000FU +#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S) +#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU +#define BITSCRAMBLER_TX_INST_POS_S 3 + +/** BITSCRAMBLER_TX_INST_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4) +/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4; + * write this bits to update instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG + */ +#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU +#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S) +#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU +#define BITSCRAMBLER_TX_INST_S 0 + +/** BITSCRAMBLER_RX_INST_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8) +/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ +#define BITSCRAMBLER_RX_INST_IDX 0x00000007U +#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S) +#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U +#define BITSCRAMBLER_RX_INST_IDX_S 0 +/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ +#define BITSCRAMBLER_RX_INST_POS 0x0000000FU +#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S) +#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU +#define BITSCRAMBLER_RX_INST_POS_S 3 + +/** BITSCRAMBLER_RX_INST_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc) +/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12; + * write this bits to update instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG + */ +#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU +#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S) +#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU +#define BITSCRAMBLER_RX_INST_S 0 + +/** BITSCRAMBLER_TX_LUT_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10) +/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_tx_lut_mode + */ +#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU +#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S) +#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU +#define BITSCRAMBLER_TX_LUT_IDX_S 0 +/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ +#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U +#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S) +#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U +#define BITSCRAMBLER_TX_LUT_MODE_S 11 + +/** BITSCRAMBLER_TX_LUT_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14) +/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20; + * write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + */ +#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU +#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S) +#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU +#define BITSCRAMBLER_TX_LUT_S 0 + +/** BITSCRAMBLER_RX_LUT_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18) +/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_rx_lut_mode + */ +#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU +#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S) +#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU +#define BITSCRAMBLER_RX_LUT_IDX_S 0 +/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ +#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U +#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S) +#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U +#define BITSCRAMBLER_RX_LUT_MODE_S 11 + +/** BITSCRAMBLER_RX_LUT_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c) +/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28; + * write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + */ +#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU +#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S) +#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU +#define BITSCRAMBLER_RX_LUT_S 0 + +/** BITSCRAMBLER_TX_TAILING_BITS_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20) +/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ +#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU +#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S) +#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU +#define BITSCRAMBLER_TX_TAILING_BITS_S 0 + +/** BITSCRAMBLER_RX_TAILING_BITS_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24) +/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ +#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU +#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S) +#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU +#define BITSCRAMBLER_RX_TAILING_BITS_S 0 + +/** BITSCRAMBLER_TX_CTRL_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28) +/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler tx + */ +#define BITSCRAMBLER_TX_ENA (BIT(0)) +#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S) +#define BITSCRAMBLER_TX_ENA_V 0x00000001U +#define BITSCRAMBLER_TX_ENA_S 0 +/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler tx core + */ +#define BITSCRAMBLER_TX_PAUSE (BIT(1)) +#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S) +#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U +#define BITSCRAMBLER_TX_PAUSE_S 1 +/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler tx core + */ +#define BITSCRAMBLER_TX_HALT (BIT(2)) +#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S) +#define BITSCRAMBLER_TX_HALT_V 0x00000001U +#define BITSCRAMBLER_TX_HALT_S 2 +/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler tx core EOF signal generating mode which is + * combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 + * counter by write peripheral buffer + */ +#define BITSCRAMBLER_TX_EOF_MODE (BIT(3)) +#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S) +#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_EOF_MODE_S 3 +/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler tx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ +#define BITSCRAMBLER_TX_COND_MODE (BIT(4)) +#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S) +#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_COND_MODE_S 4 +/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ +#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5)) +#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S) +#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_FETCH_MODE_S 5 +/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ +#define BITSCRAMBLER_TX_HALT_MODE (BIT(6)) +#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S) +#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_HALT_MODE_S 6 +/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler tx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ +#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7)) +#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S) +#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U +#define BITSCRAMBLER_TX_RD_DUMMY_S 7 +/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler tx fifo + */ +#define BITSCRAMBLER_TX_FIFO_RST (BIT(8)) +#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S) +#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U +#define BITSCRAMBLER_TX_FIFO_RST_S 8 + +/** BITSCRAMBLER_RX_CTRL_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c) +/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler rx + */ +#define BITSCRAMBLER_RX_ENA (BIT(0)) +#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S) +#define BITSCRAMBLER_RX_ENA_V 0x00000001U +#define BITSCRAMBLER_RX_ENA_S 0 +/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler rx core + */ +#define BITSCRAMBLER_RX_PAUSE (BIT(1)) +#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S) +#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U +#define BITSCRAMBLER_RX_PAUSE_S 1 +/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler rx core + */ +#define BITSCRAMBLER_RX_HALT (BIT(2)) +#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S) +#define BITSCRAMBLER_RX_HALT_V 0x00000001U +#define BITSCRAMBLER_RX_HALT_S 2 +/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler rx core EOF signal generating mode which is + * combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral + * buffer, 0 counter by write dma fifo + */ +#define BITSCRAMBLER_RX_EOF_MODE (BIT(3)) +#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S) +#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_EOF_MODE_S 3 +/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler rx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ +#define BITSCRAMBLER_RX_COND_MODE (BIT(4)) +#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S) +#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_COND_MODE_S 4 +/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ +#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5)) +#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S) +#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_FETCH_MODE_S 5 +/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ +#define BITSCRAMBLER_RX_HALT_MODE (BIT(6)) +#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S) +#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_HALT_MODE_S 6 +/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler rx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ +#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7)) +#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S) +#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U +#define BITSCRAMBLER_RX_RD_DUMMY_S 7 +/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler rx fifo + */ +#define BITSCRAMBLER_RX_FIFO_RST (BIT(8)) +#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S) +#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U +#define BITSCRAMBLER_RX_FIFO_RST_S 8 + +/** BITSCRAMBLER_TX_STATE_REG register + * Status registers + */ +#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30) +/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1; + * represents the bitscrambler tx core in halt mode + */ +#define BITSCRAMBLER_TX_IN_IDLE (BIT(0)) +#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S) +#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U +#define BITSCRAMBLER_TX_IN_IDLE_S 0 +/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0; + * represents the bitscrambler tx core in run mode + */ +#define BITSCRAMBLER_TX_IN_RUN (BIT(1)) +#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S) +#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U +#define BITSCRAMBLER_TX_IN_RUN_S 1 +/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0; + * represents the bitscrambler tx core in wait mode to wait write back done + */ +#define BITSCRAMBLER_TX_IN_WAIT (BIT(2)) +#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S) +#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U +#define BITSCRAMBLER_TX_IN_WAIT_S 2 +/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0; + * represents the bitscrambler tx core in pause mode + */ +#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3)) +#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S) +#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U +#define BITSCRAMBLER_TX_IN_PAUSE_S 3 +/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0; + * represents the bitscrambler tx fifo in empty state + */ +#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4)) +#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S) +#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U +#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4 +/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler tx core when get EOF + */ +#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU +#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S) +#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU +#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16 +/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler tx core + */ +#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30)) +#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S) +#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U +#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30 +/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_tx_eof_overload and + * reg_bitscrambler_tx_eof_get_cnt registers + */ +#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31)) +#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S) +#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U +#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31 + +/** BITSCRAMBLER_RX_STATE_REG register + * Status registers + */ +#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34) +/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1; + * represents the bitscrambler rx core in halt mode + */ +#define BITSCRAMBLER_RX_IN_IDLE (BIT(0)) +#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S) +#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U +#define BITSCRAMBLER_RX_IN_IDLE_S 0 +/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0; + * represents the bitscrambler rx core in run mode + */ +#define BITSCRAMBLER_RX_IN_RUN (BIT(1)) +#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S) +#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U +#define BITSCRAMBLER_RX_IN_RUN_S 1 +/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0; + * represents the bitscrambler rx core in wait mode to wait write back done + */ +#define BITSCRAMBLER_RX_IN_WAIT (BIT(2)) +#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S) +#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U +#define BITSCRAMBLER_RX_IN_WAIT_S 2 +/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0; + * represents the bitscrambler rx core in pause mode + */ +#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3)) +#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S) +#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U +#define BITSCRAMBLER_RX_IN_PAUSE_S 3 +/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0; + * represents the bitscrambler rx fifo in full state + */ +#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4)) +#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S) +#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U +#define BITSCRAMBLER_RX_FIFO_FULL_S 4 +/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler rx core when get EOF + */ +#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU +#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S) +#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU +#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16 +/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler rx core + */ +#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30)) +#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S) +#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U +#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30 +/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_rx_eof_overload and + * reg_bitscrambler_rx_eof_get_cnt registers + */ +#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31)) +#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S) +#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U +#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31 + +/** BITSCRAMBLER_SYS_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8) +/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0; + * write this bit to set the bitscrambler tx loop back to DMA rx + */ +#define BITSCRAMBLER_LOOP_MODE (BIT(0)) +#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S) +#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U +#define BITSCRAMBLER_LOOP_MODE_S 0 +/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0; + * Reserved + */ +#define BITSCRAMBLER_CLK_EN (BIT(31)) +#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S) +#define BITSCRAMBLER_CLK_EN_V 0x00000001U +#define BITSCRAMBLER_CLK_EN_S 31 + +/** BITSCRAMBLER_VERSION_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc) +/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024; + * Reserved + */ +#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU +#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S) +#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU +#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/include/soc/bitscrambler_struct.h new file mode 100644 index 00000000000..cfcca328ae8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/bitscrambler_struct.h @@ -0,0 +1,437 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of tx_inst_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ + uint32_t tx_inst_idx:3; + /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ + uint32_t tx_inst_pos:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} bitscrambler_tx_inst_cfg0_reg_t; + +/** Type of tx_inst_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_inst : R/W; bitpos: [31:0]; default: 4; + * write this bits to update instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG + */ + uint32_t tx_inst:32; + }; + uint32_t val; +} bitscrambler_tx_inst_cfg1_reg_t; + +/** Type of rx_inst_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ + uint32_t rx_inst_idx:3; + /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ + uint32_t rx_inst_pos:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} bitscrambler_rx_inst_cfg0_reg_t; + +/** Type of rx_inst_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_inst : R/W; bitpos: [31:0]; default: 12; + * write this bits to update instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG + */ + uint32_t rx_inst:32; + }; + uint32_t val; +} bitscrambler_rx_inst_cfg1_reg_t; + +/** Type of tx_lut_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_tx_lut_mode + */ + uint32_t tx_lut_idx:11; + /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ + uint32_t tx_lut_mode:2; + uint32_t reserved_13:19; + }; + uint32_t val; +} bitscrambler_tx_lut_cfg0_reg_t; + +/** Type of tx_lut_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_lut : R/W; bitpos: [31:0]; default: 20; + * write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + */ + uint32_t tx_lut:32; + }; + uint32_t val; +} bitscrambler_tx_lut_cfg1_reg_t; + +/** Type of rx_lut_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_rx_lut_mode + */ + uint32_t rx_lut_idx:11; + /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ + uint32_t rx_lut_mode:2; + uint32_t reserved_13:19; + }; + uint32_t val; +} bitscrambler_rx_lut_cfg0_reg_t; + +/** Type of rx_lut_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_lut : R/W; bitpos: [31:0]; default: 28; + * write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + */ + uint32_t rx_lut:32; + }; + uint32_t val; +} bitscrambler_rx_lut_cfg1_reg_t; + + +/** Group: Configuration registers */ +/** Type of tx_tailing_bits register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ + uint32_t tx_tailing_bits:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} bitscrambler_tx_tailing_bits_reg_t; + +/** Type of rx_tailing_bits register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ + uint32_t rx_tailing_bits:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} bitscrambler_rx_tailing_bits_reg_t; + +/** Type of tx_ctrl register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_ena : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler tx + */ + uint32_t tx_ena:1; + /** tx_pause : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler tx core + */ + uint32_t tx_pause:1; + /** tx_halt : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler tx core + */ + uint32_t tx_halt:1; + /** tx_eof_mode : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler tx core EOF signal generating mode which is + * combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 + * counter by write peripheral buffer + */ + uint32_t tx_eof_mode:1; + /** tx_cond_mode : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler tx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ + uint32_t tx_cond_mode:1; + /** tx_fetch_mode : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ + uint32_t tx_fetch_mode:1; + /** tx_halt_mode : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ + uint32_t tx_halt_mode:1; + /** tx_rd_dummy : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler tx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ + uint32_t tx_rd_dummy:1; + /** tx_fifo_rst : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler tx fifo + */ + uint32_t tx_fifo_rst:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} bitscrambler_tx_ctrl_reg_t; + +/** Type of rx_ctrl register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_ena : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler rx + */ + uint32_t rx_ena:1; + /** rx_pause : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler rx core + */ + uint32_t rx_pause:1; + /** rx_halt : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler rx core + */ + uint32_t rx_halt:1; + /** rx_eof_mode : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler rx core EOF signal generating mode which is + * combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral + * buffer, 0 counter by write dma fifo + */ + uint32_t rx_eof_mode:1; + /** rx_cond_mode : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler rx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ + uint32_t rx_cond_mode:1; + /** rx_fetch_mode : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ + uint32_t rx_fetch_mode:1; + /** rx_halt_mode : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ + uint32_t rx_halt_mode:1; + /** rx_rd_dummy : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler rx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ + uint32_t rx_rd_dummy:1; + /** rx_fifo_rst : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler rx fifo + */ + uint32_t rx_fifo_rst:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} bitscrambler_rx_ctrl_reg_t; + +/** Type of sys register + * Control and configuration registers + */ +typedef union { + struct { + /** loop_mode : R/W; bitpos: [0]; default: 0; + * write this bit to set the bitscrambler tx loop back to DMA rx + */ + uint32_t loop_mode:1; + uint32_t reserved_1:30; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + }; + uint32_t val; +} bitscrambler_sys_reg_t; + + +/** Group: Status registers */ +/** Type of tx_state register + * Status registers + */ +typedef union { + struct { + /** tx_in_idle : RO; bitpos: [0]; default: 1; + * represents the bitscrambler tx core in halt mode + */ + uint32_t tx_in_idle:1; + /** tx_in_run : RO; bitpos: [1]; default: 0; + * represents the bitscrambler tx core in run mode + */ + uint32_t tx_in_run:1; + /** tx_in_wait : RO; bitpos: [2]; default: 0; + * represents the bitscrambler tx core in wait mode to wait write back done + */ + uint32_t tx_in_wait:1; + /** tx_in_pause : RO; bitpos: [3]; default: 0; + * represents the bitscrambler tx core in pause mode + */ + uint32_t tx_in_pause:1; + /** tx_fifo_empty : RO; bitpos: [4]; default: 0; + * represents the bitscrambler tx fifo in empty state + */ + uint32_t tx_fifo_empty:1; + uint32_t reserved_5:11; + /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler tx core when get EOF + */ + uint32_t tx_eof_get_cnt:14; + /** tx_eof_overload : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler tx core + */ + uint32_t tx_eof_overload:1; + /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_tx_eof_overload and + * reg_bitscrambler_tx_eof_get_cnt registers + */ + uint32_t tx_eof_trace_clr:1; + }; + uint32_t val; +} bitscrambler_tx_state_reg_t; + +/** Type of rx_state register + * Status registers + */ +typedef union { + struct { + /** rx_in_idle : RO; bitpos: [0]; default: 1; + * represents the bitscrambler rx core in halt mode + */ + uint32_t rx_in_idle:1; + /** rx_in_run : RO; bitpos: [1]; default: 0; + * represents the bitscrambler rx core in run mode + */ + uint32_t rx_in_run:1; + /** rx_in_wait : RO; bitpos: [2]; default: 0; + * represents the bitscrambler rx core in wait mode to wait write back done + */ + uint32_t rx_in_wait:1; + /** rx_in_pause : RO; bitpos: [3]; default: 0; + * represents the bitscrambler rx core in pause mode + */ + uint32_t rx_in_pause:1; + /** rx_fifo_full : RO; bitpos: [4]; default: 0; + * represents the bitscrambler rx fifo in full state + */ + uint32_t rx_fifo_full:1; + uint32_t reserved_5:11; + /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler rx core when get EOF + */ + uint32_t rx_eof_get_cnt:14; + /** rx_eof_overload : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler rx core + */ + uint32_t rx_eof_overload:1; + /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_rx_eof_overload and + * reg_bitscrambler_rx_eof_get_cnt registers + */ + uint32_t rx_eof_trace_clr:1; + }; + uint32_t val; +} bitscrambler_rx_state_reg_t; + + +/** Group: Version register */ +/** Type of version register + * Control and configuration registers + */ +typedef union { + struct { + /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024; + * Reserved + */ + uint32_t bitscrambler_ver:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} bitscrambler_version_reg_t; + + +typedef struct bitscrambler_dev_t { + volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0; + volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1; + volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0; + volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1; + volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0; + volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1; + volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0; + volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1; + volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits; + volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits; + volatile bitscrambler_tx_ctrl_reg_t tx_ctrl; + volatile bitscrambler_rx_ctrl_reg_t rx_ctrl; + volatile bitscrambler_tx_state_reg_t tx_state; + volatile bitscrambler_rx_state_reg_t rx_state; + uint32_t reserved_038[48]; + volatile bitscrambler_sys_reg_t sys; + volatile bitscrambler_version_reg_t version; +} bitscrambler_dev_t; + +extern bitscrambler_dev_t BITSCRAMBLER; + +#ifndef __cplusplus +_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/cache_reg.h b/components/soc/esp32c5/include/soc/cache_reg.h new file mode 100644 index 00000000000..34bacbb7068 --- /dev/null +++ b/components/soc/esp32c5/include/soc/cache_reg.h @@ -0,0 +1,1289 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CACHE_L1_CACHE_CTRL_REG register + * L1 data Cache(L1-Cache) control register + */ +#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) +/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) +#define CACHE_L1_CACHE_SHUT_BUS0_M (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S) +#define CACHE_L1_CACHE_SHUT_BUS0_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS0_S 0 +/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) +#define CACHE_L1_CACHE_SHUT_BUS1_M (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S) +#define CACHE_L1_CACHE_SHUT_BUS1_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS1_S 1 +/** CACHE_L1_CACHE_SHUT_DBUS2 : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS2 (BIT(2)) +#define CACHE_L1_CACHE_SHUT_DBUS2_M (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S) +#define CACHE_L1_CACHE_SHUT_DBUS2_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS2_S 2 +/** CACHE_L1_CACHE_SHUT_DBUS3 : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS3 (BIT(3)) +#define CACHE_L1_CACHE_SHUT_DBUS3_M (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S) +#define CACHE_L1_CACHE_SHUT_DBUS3_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS3_S 3 + +/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) +/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ +#define CACHE_L1_CACHE_WRAP (BIT(4)) +#define CACHE_L1_CACHE_WRAP_M (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S) +#define CACHE_L1_CACHE_WRAP_V 0x00000001U +#define CACHE_L1_CACHE_WRAP_S 4 + +/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register + * Cache tag memory power control register + */ +#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24) +/** CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M (CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S 16 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M (CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S 17 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M (CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register + * Cache data memory power control register + */ +#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28) +/** CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M (CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S 16 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M (CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S 17 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M (CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S 18 + +/** CACHE_L1_CACHE_FREEZE_CTRL_REG register + * Cache Freeze control register + */ +#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c) +/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ +#define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) +#define CACHE_L1_CACHE_FREEZE_EN_M (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S) +#define CACHE_L1_CACHE_FREEZE_EN_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_EN_S 16 +/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) +#define CACHE_L1_CACHE_FREEZE_MODE_M (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S) +#define CACHE_L1_CACHE_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_MODE_S 17 +/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) +#define CACHE_L1_CACHE_FREEZE_DONE_M (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S) +#define CACHE_L1_CACHE_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_DONE_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register + * Cache data memory access configure register + */ +#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) +/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 + +/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register + * Cache tag memory access configure register + */ +#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34) +/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 + +/** CACHE_L1_CACHE_PRELOCK_CONF_REG register + * L1 Cache prelock configure register + */ +#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78) +/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ +#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_M (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S) +#define CACHE_L1_CACHE_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 + +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register + * L1 Cache prelock section0 address configure register + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register + * L1 Cache prelock section1 address configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80) +/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register + * L1 Cache prelock section size configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84) +/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_LOCK_CTRL_REG register + * Lock-class (manual lock) operation control register + */ +#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88) +/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ +#define CACHE_LOCK_ENA (BIT(0)) +#define CACHE_LOCK_ENA_M (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S) +#define CACHE_LOCK_ENA_V 0x00000001U +#define CACHE_LOCK_ENA_S 0 +/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ +#define CACHE_UNLOCK_ENA (BIT(1)) +#define CACHE_UNLOCK_ENA_M (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S) +#define CACHE_UNLOCK_ENA_V 0x00000001U +#define CACHE_UNLOCK_ENA_S 1 +/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ +#define CACHE_LOCK_DONE (BIT(2)) +#define CACHE_LOCK_DONE_M (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S) +#define CACHE_LOCK_DONE_V 0x00000001U +#define CACHE_LOCK_DONE_S 2 +/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ +#define CACHE_LOCK_RGID 0x0000000FU +#define CACHE_LOCK_RGID_M (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S) +#define CACHE_LOCK_RGID_V 0x0000000FU +#define CACHE_LOCK_RGID_S 3 + +/** CACHE_LOCK_MAP_REG register + * Lock (manual lock) map configure register + */ +#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c) +/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ +#define CACHE_LOCK_MAP 0x0000003FU +#define CACHE_LOCK_MAP_M (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S) +#define CACHE_LOCK_MAP_V 0x0000003FU +#define CACHE_LOCK_MAP_S 0 + +/** CACHE_LOCK_ADDR_REG register + * Lock (manual lock) address configure register + */ +#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90) +/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ +#define CACHE_LOCK_ADDR 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_M (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S) +#define CACHE_LOCK_ADDR_V 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_S 0 + +/** CACHE_LOCK_SIZE_REG register + * Lock (manual lock) size configure register + */ +#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94) +/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ +#define CACHE_LOCK_SIZE 0x0000FFFFU +#define CACHE_LOCK_SIZE_M (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S) +#define CACHE_LOCK_SIZE_V 0x0000FFFFU +#define CACHE_LOCK_SIZE_S 0 + +/** CACHE_SYNC_CTRL_REG register + * Sync-class operation control register + */ +#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98) +/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_INVALIDATE_ENA (BIT(0)) +#define CACHE_INVALIDATE_ENA_M (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S) +#define CACHE_INVALIDATE_ENA_V 0x00000001U +#define CACHE_INVALIDATE_ENA_S 0 +/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ +#define CACHE_CLEAN_ENA (BIT(1)) +#define CACHE_CLEAN_ENA_M (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S) +#define CACHE_CLEAN_ENA_V 0x00000001U +#define CACHE_CLEAN_ENA_S 1 +/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_ENA (BIT(2)) +#define CACHE_WRITEBACK_ENA_M (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S) +#define CACHE_WRITEBACK_ENA_V 0x00000001U +#define CACHE_WRITEBACK_ENA_S 2 +/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define CACHE_WRITEBACK_INVALIDATE_ENA_M (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S) +#define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x00000001U +#define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ +#define CACHE_SYNC_DONE (BIT(4)) +#define CACHE_SYNC_DONE_M (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S) +#define CACHE_SYNC_DONE_V 0x00000001U +#define CACHE_SYNC_DONE_S 4 +/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ +#define CACHE_SYNC_RGID 0x0000000FU +#define CACHE_SYNC_RGID_M (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S) +#define CACHE_SYNC_RGID_V 0x0000000FU +#define CACHE_SYNC_RGID_S 5 + +/** CACHE_SYNC_MAP_REG register + * Sync map configure register + */ +#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c) +/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ +#define CACHE_SYNC_MAP 0x0000003FU +#define CACHE_SYNC_MAP_M (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S) +#define CACHE_SYNC_MAP_V 0x0000003FU +#define CACHE_SYNC_MAP_S 0 + +/** CACHE_SYNC_ADDR_REG register + * Sync address configure register + */ +#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0) +/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ +#define CACHE_SYNC_ADDR 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_M (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S) +#define CACHE_SYNC_ADDR_V 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_S 0 + +/** CACHE_SYNC_SIZE_REG register + * Sync size configure register + */ +#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4) +/** CACHE_SYNC_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ +#define CACHE_SYNC_SIZE 0x00FFFFFFU +#define CACHE_SYNC_SIZE_M (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S) +#define CACHE_SYNC_SIZE_V 0x00FFFFFFU +#define CACHE_SYNC_SIZE_S 0 + +/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register + * L1 Cache preload-operation control register + */ +#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8) +/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_PRELOAD_ENA_M (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S) +#define CACHE_L1_CACHE_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ENA_S 0 +/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_PRELOAD_DONE_M (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S) +#define CACHE_L1_CACHE_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_DONE_S 1 +/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_PRELOAD_ORDER_M (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S) +#define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 +/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ +#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_M (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S) +#define CACHE_L1_CACHE_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 + +/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register + * L1 Cache preload address configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc) +/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_M (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S) +#define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register + * L1 Cache preload size configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0) +/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_M (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S) +#define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register + * L1 Cache autoload-operation control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134) +/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_M (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 +/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_M (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 +/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register + * L1 Cache autoload section 0 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register + * L1 Cache autoload section 0 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register + * L1 Cache autoload section 1 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register + * L1 Cache autoload section 1 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register + * Cache Access Counter Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158) +/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ENA_M (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S) +#define CACHE_L1_BUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ENA_S 4 +/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ENA_M (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S) +#define CACHE_L1_BUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ENA_S 5 + +/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register + * Cache Access Counter Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c) +/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_CLR_M (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S) +#define CACHE_L1_BUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_CLR_S 4 +/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_CLR_M (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S) +#define CACHE_L1_BUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_CLR_S 5 + +/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register + * Cache Access Counter Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160) +/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_RAW_M (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S) +#define CACHE_L1_BUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_RAW_S 4 +/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_RAW_M (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S) +#define CACHE_L1_BUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_RAW_S 5 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register + * Cache Access Counter Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164) +/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ST_M (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S) +#define CACHE_L1_BUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ST_S 4 +/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ST_M (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S) +#define CACHE_L1_BUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ST_S 5 + +/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register + * Cache Access Fail Configuration register + */ +#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168) +/** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0; + * The bit is used to configure l1 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE (BIT(4)) +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register + * Cache Access Fail Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c) +/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ENA_M (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S) +#define CACHE_L1_CACHE_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register + * L1-Cache Access Fail Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170) +/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_CLR_M (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S) +#define CACHE_L1_CACHE_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register + * Cache Access Fail Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174) +/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_RAW_M (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S) +#define CACHE_L1_CACHE_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register + * Cache Access Fail Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178) +/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ST_M (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S) +#define CACHE_L1_CACHE_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ST_S 4 + +/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register + * Cache Access Counter enable and clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c) +/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_ENA (BIT(4)) +#define CACHE_L1_BUS0_CNT_ENA_M (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S) +#define CACHE_L1_BUS0_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_CNT_ENA_S 4 +/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_ENA (BIT(5)) +#define CACHE_L1_BUS1_CNT_ENA_M (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S) +#define CACHE_L1_BUS1_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_CNT_ENA_S 5 +/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_CLR (BIT(20)) +#define CACHE_L1_BUS0_CNT_CLR_M (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S) +#define CACHE_L1_BUS0_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_CNT_CLR_S 20 +/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_CLR (BIT(21)) +#define CACHE_L1_BUS1_CNT_CLR_M (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S) +#define CACHE_L1_BUS1_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_CNT_CLR_S 21 + +/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register + * L1-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0) +/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_M (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S) +#define CACHE_L1_BUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register + * L1-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4) +/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_M (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S) +#define CACHE_L1_BUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register + * L1-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) +/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_CONFLICT_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S) +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S 0 + +/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register + * L1-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) +/** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_M (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus0 WB-Access Counter register + */ +#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0) +/** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_M (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register + * L1-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4) +/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_M (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S) +#define CACHE_L1_BUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register + * L1-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8) +/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_M (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S) +#define CACHE_L1_BUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register + * L1-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc) +/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_M (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S) +#define CACHE_L1_BUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register + * L1-DCache bus1 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0) +/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S) +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus1 WB-Access Counter register + */ +#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4) +/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus1 accesses L1-Cache. + */ +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S) +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210) +/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_M (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S) +#define CACHE_L1_ICACHE0_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_S 0 +/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_M (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S) +#define CACHE_L1_ICACHE0_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214) +/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_M (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S) +#define CACHE_L1_ICACHE0_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218) +/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_M (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S) +#define CACHE_L1_ICACHE1_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_S 0 +/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_M (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S) +#define CACHE_L1_ICACHE1_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c) +/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_M (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S) +#define CACHE_L1_ICACHE1_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_S 0 + +/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register + * L1-Cache Access Fail ID/attribution information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230) +/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ID 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_M (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S) +#define CACHE_L1_CACHE_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_S 0 +/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_M (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S) +#define CACHE_L1_CACHE_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_S 16 + +/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register + * L1-Cache Access Fail Address information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234) +/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_M (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S) +#define CACHE_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_S 0 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register + * L1-Cache Access Fail Interrupt enable register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238) +/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 +/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ +#define CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define CACHE_SYNC_DONE_INT_ENA_M (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S) +#define CACHE_SYNC_DONE_INT_ENA_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ENA_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 +/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define CACHE_SYNC_ERR_INT_ENA_M (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S) +#define CACHE_SYNC_ERR_INT_ENA_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ENA_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register + * Sync Preload operation Interrupt clear register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c) +/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 +/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ +#define CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define CACHE_SYNC_DONE_INT_CLR_M (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S) +#define CACHE_SYNC_DONE_INT_CLR_V 0x00000001U +#define CACHE_SYNC_DONE_INT_CLR_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 +/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define CACHE_SYNC_ERR_INT_CLR_M (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S) +#define CACHE_SYNC_ERR_INT_CLR_V 0x00000001U +#define CACHE_SYNC_ERR_INT_CLR_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register + * Sync Preload operation Interrupt raw register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240) +/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 +/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define CACHE_SYNC_DONE_INT_RAW_M (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S) +#define CACHE_SYNC_DONE_INT_RAW_V 0x00000001U +#define CACHE_SYNC_DONE_INT_RAW_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 +/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ +#define CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define CACHE_SYNC_ERR_INT_RAW_M (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S) +#define CACHE_SYNC_ERR_INT_RAW_V 0x00000001U +#define CACHE_SYNC_ERR_INT_RAW_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register + * L1-Cache Access Fail Interrupt status register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244) +/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 +/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define CACHE_SYNC_DONE_INT_ST_M (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S) +#define CACHE_SYNC_DONE_INT_ST_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ST_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 +/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define CACHE_SYNC_ERR_INT_ST_M (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S) +#define CACHE_SYNC_ERR_INT_ST_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ST_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register + * Cache Sync/Preload Operation exception register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248) +/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ +#define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_M (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S) +#define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 +/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ +#define CACHE_SYNC_ERR_CODE 0x00000003U +#define CACHE_SYNC_ERR_CODE_M (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S) +#define CACHE_SYNC_ERR_CODE_V 0x00000003U +#define CACHE_SYNC_ERR_CODE_S 12 + +/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register + * Cache Sync Reset control register + */ +#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c) +/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_CACHE_SYNC_RST (BIT(4)) +#define CACHE_L1_CACHE_SYNC_RST_M (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S) +#define CACHE_L1_CACHE_SYNC_RST_V 0x00000001U +#define CACHE_L1_CACHE_SYNC_RST_S 4 + +/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register + * Cache Preload Reset control register + */ +#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250) +/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_CACHE_PLD_RST (BIT(4)) +#define CACHE_L1_CACHE_PLD_RST_M (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S) +#define CACHE_L1_CACHE_PLD_RST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_RST_S 4 + +/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register + * Cache Autoload buffer clear control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254) +/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ +#define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) +#define CACHE_L1_CACHE_ALD_BUF_CLR_M (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S) +#define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 + +/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register + * Unallocate request buffer clear registers + */ +#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258) +/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) +#define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) +#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 + +/** CACHE_L1_CACHE_OBJECT_CTRL_REG register + * Cache Tag and Data memory Object control register + */ +#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c) +/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) +#define CACHE_L1_CACHE_TAG_OBJECT_M (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S) +#define CACHE_L1_CACHE_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_TAG_OBJECT_S 4 +/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) +#define CACHE_L1_CACHE_MEM_OBJECT_M (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S) +#define CACHE_L1_CACHE_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_MEM_OBJECT_S 10 + +/** CACHE_L1_CACHE_WAY_OBJECT_REG register + * Cache Tag and Data memory way register + */ +#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260) +/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ +#define CACHE_L1_CACHE_WAY_OBJECT 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_M (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S) +#define CACHE_L1_CACHE_WAY_OBJECT_V 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_S 0 + +/** CACHE_L1_CACHE_VADDR_REG register + * Cache Vaddr register + */ +#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264) +/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ +#define CACHE_L1_CACHE_VADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_VADDR_M (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S) +#define CACHE_L1_CACHE_VADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_VADDR_S 0 + +/** CACHE_L1_CACHE_DEBUG_BUS_REG register + * Cache Tag/data memory content register + */ +#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268) +/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ +#define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_M (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S) +#define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_S 0 + +/** CACHE_DATE_REG register + * Version control register + */ +#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) +/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36716800; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define CACHE_DATE 0x0FFFFFFFU +#define CACHE_DATE_M (CACHE_DATE_V << CACHE_DATE_S) +#define CACHE_DATE_V 0x0FFFFFFFU +#define CACHE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/cache_struct.h b/components/soc/esp32c5/include/soc/cache_struct.h new file mode 100644 index 00000000000..871f93c19e3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/cache_struct.h @@ -0,0 +1,1410 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of l1_cache_ctrl register + * L1 data Cache(L1-Cache) control register + */ +typedef union { + struct { + /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus0:1; + /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus1:1; + /** l1_cache_shut_dbus2 : R/W; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus2:1; + /** l1_cache_shut_dbus3 : R/W; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} cache_l1_cache_ctrl_reg_t; + + +/** Group: Wrap Mode Control and configuration registers */ +/** Type of l1_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ + uint32_t l1_cache_wrap:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_wrap_around_ctrl_reg_t; + + +/** Group: Cache Tag Memory Power Control registers */ +/** Type of l1_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_tag_mem_force_on:1; + /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l1_cache_tag_mem_force_pd:1; + /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_tag_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_tag_mem_power_ctrl_reg_t; + + +/** Group: Cache Data Memory Power Control registers */ +/** Type of l1_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_data_mem_force_on:1; + /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_cache_data_mem_force_pd:1; + /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_data_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_data_mem_power_ctrl_reg_t; + + +/** Group: Cache Freeze Control registers */ +/** Type of l1_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ + uint32_t l1_cache_freeze_en:1; + /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_cache_freeze_mode:1; + /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_freeze_done:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_freeze_ctrl_reg_t; + + +/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Type of l1_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_rd_en:1; + /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_data_mem_acs_conf_reg_t; + + +/** Group: Cache Tag Memory Access Control and Configuration registers */ +/** Type of l1_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_rd_en:1; + /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_tag_mem_acs_conf_reg_t; + + +/** Group: Prelock Control and configuration registers */ +/** Type of l1_cache_prelock_conf register + * L1 Cache prelock configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct0_en:1; + /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct1_en:1; + /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ + uint32_t l1_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_prelock_conf_reg_t; + +/** Type of l1_cache_prelock_sct0_addr register + * L1 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_prelock_sct0_addr_reg_t; + +/** Type of l1_dcache_prelock_sct1_addr register + * L1 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct1_addr_reg_t; + +/** Type of l1_dcache_prelock_sct_size register + * L1 Cache prelock section size configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_cache_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_cache_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct_size_reg_t; + + +/** Group: Lock Control and configuration registers */ +/** Type of lock_ctrl register + * Lock-class (manual lock) operation control register + */ +typedef union { + struct { + /** lock_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ + uint32_t lock_ena:1; + /** unlock_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ + uint32_t unlock_ena:1; + /** lock_done : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ + uint32_t lock_done:1; + /** lock_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ + uint32_t lock_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_lock_ctrl_reg_t; + +/** Type of lock_map register + * Lock (manual lock) map configure register + */ +typedef union { + struct { + /** lock_map : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ + uint32_t lock_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_lock_map_reg_t; + +/** Type of lock_addr register + * Lock (manual lock) address configure register + */ +typedef union { + struct { + /** lock_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ + uint32_t lock_addr:32; + }; + uint32_t val; +} cache_lock_addr_reg_t; + +/** Type of lock_size register + * Lock (manual lock) size configure register + */ +typedef union { + struct { + /** lock_size : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ + uint32_t lock_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_lock_size_reg_t; + + +/** Group: Sync Control and configuration registers */ +/** Type of sync_ctrl register + * Sync-class operation control register + */ +typedef union { + struct { + /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t invalidate_ena:1; + /** clean_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ + uint32_t clean_ena:1; + /** writeback_ena : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_ena:1; + /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_invalidate_ena:1; + /** sync_done : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ + uint32_t sync_done:1; + /** sync_rgid : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ + uint32_t sync_rgid:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} cache_sync_ctrl_reg_t; + +/** Type of sync_map register + * Sync map configure register + */ +typedef union { + struct { + /** sync_map : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ + uint32_t sync_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_sync_map_reg_t; + +/** Type of sync_addr register + * Sync address configure register + */ +typedef union { + struct { + /** sync_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ + uint32_t sync_addr:32; + }; + uint32_t val; +} cache_sync_addr_reg_t; + +/** Type of sync_size register + * Sync size configure register + */ +typedef union { + struct { + /** sync_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ + uint32_t sync_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_sync_size_reg_t; + + +/** Group: Preload Control and configuration registers */ +/** Type of l1_cache_preload_ctrl register + * L1 Cache preload-operation control register + */ +typedef union { + struct { + /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_cache_preload_ena:1; + /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_cache_preload_done:1; + /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_cache_preload_order:1; + /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ + uint32_t l1_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_cache_preload_ctrl_reg_t; + +/** Type of l1_dcache_preload_addr register + * L1 Cache preload address configure register + */ +typedef union { + struct { + /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l1_cache_preload_addr:32; + }; + uint32_t val; +} cache_l1_dcache_preload_addr_reg_t; + +/** Type of l1_dcache_preload_size register + * L1 Cache preload size configure register + */ +typedef union { + struct { + /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l1_cache_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_dcache_preload_size_reg_t; + + +/** Group: Autoload Control and configuration registers */ +/** Type of l1_cache_autoload_ctrl register + * L1 Cache autoload-operation control register + */ +typedef union { + struct { + /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ + uint32_t l1_cache_autoload_ena:1; + /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_autoload_done:1; + /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l1_cache_autoload_order:1; + /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct0_ena:1; + /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct1_ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} cache_l1_cache_autoload_ctrl_reg_t; + +/** Type of l1_cache_autoload_sct0_addr register + * L1 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_addr_reg_t; + +/** Type of l1_cache_autoload_sct0_size register + * L1 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_size_reg_t; + +/** Type of l1_cache_autoload_sct1_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_addr_reg_t; + +/** Type of l1_cache_autoload_sct1_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_size_reg_t; + + +/** Group: Interrupt registers */ +/** Type of l1_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_ena:1; + /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_ena_reg_t; + +/** Type of l1_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_clr:1; + /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_clr_reg_t; + +/** Type of l1_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_raw:1; + /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_raw_reg_t; + +/** Type of l1_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_st:1; + /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_st_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_ena_reg_t; + +/** Type of l1_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_clr_reg_t; + +/** Type of l1_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ + uint32_t l1_cache_fail_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_raw_reg_t; + +/** Type of l1_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_st_reg_t; + +/** Type of sync_l1_cache_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_cache_pld_done_int_ena:1; + uint32_t reserved_5:1; + /** sync_done_int_ena : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ + uint32_t sync_done_int_ena:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_ena:1; + uint32_t reserved_12:1; + /** sync_err_int_ena : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_ena_reg_t; + +/** Type of sync_l1_cache_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ + uint32_t l1_cache_pld_done_int_clr:1; + uint32_t reserved_5:1; + /** sync_done_int_clr : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ + uint32_t sync_done_int_clr:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_clr:1; + uint32_t reserved_12:1; + /** sync_err_int_clr : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_clr_reg_t; + +/** Type of sync_l1_cache_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ + uint32_t l1_cache_pld_done_int_raw:1; + uint32_t reserved_5:1; + /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ + uint32_t sync_done_int_raw:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ + uint32_t l1_cache_pld_err_int_raw:1; + uint32_t reserved_12:1; + /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ + uint32_t sync_err_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_raw_reg_t; + +/** Type of sync_l1_cache_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ + uint32_t l1_cache_pld_done_int_st:1; + uint32_t reserved_5:1; + /** sync_done_int_st : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ + uint32_t sync_done_int_st:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_st:1; + uint32_t reserved_12:1; + /** sync_err_int_st : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_st_reg_t; + + +/** Group: Cache Access Fail Configuration register */ +/** Type of l1_cache_acs_fail_ctrl register + * Cache Access Fail Configuration register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; + * The bit is used to configure l1 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_cache_acs_fail_check_mode:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_ctrl_reg_t; + + +/** Group: Access Statistics registers */ +/** Type of l1_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_ena:1; + /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_ena:1; + uint32_t reserved_6:14; + /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_clr:1; + /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_clr:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_ctrl_reg_t; + +/** Type of l1_bus0_acs_hit_cnt register + * L1-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_hit_cnt_reg_t; + +/** Type of l1_bus0_acs_miss_cnt register + * L1-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_miss_cnt_reg_t; + +/** Type of l1_bus0_acs_conflict_cnt register + * L1-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_conflict_rd_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register + * L1-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register + * L1-DCache bus0 WB-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l1_bus1_acs_hit_cnt register + * L1-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_hit_cnt_reg_t; + +/** Type of l1_bus1_acs_miss_cnt register + * L1-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_miss_cnt_reg_t; + +/** Type of l1_bus1_acs_conflict_cnt register + * L1-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register + * L1-DCache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ + uint32_t l1_dbus1_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register + * L1-DCache bus1 WB-Access Counter register + */ +typedef union { + struct { + /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus1 accesses L1-Cache. + */ + uint32_t l1_dbus1_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t; + + +/** Group: Access Fail Debug registers */ +/** Type of l1_icache0_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_id:16; + /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_id_attr_reg_t; + +/** Type of l1_icache0_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_addr_reg_t; + +/** Type of l1_icache1_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_id:16; + /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_id_attr_reg_t; + +/** Type of l1_icache1_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_addr_reg_t; + +/** Type of l1_dcache_acs_fail_id_attr register + * L1-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_id:16; + /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_attr:16; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_id_attr_reg_t; + +/** Type of l1_dcache_acs_fail_addr register + * L1-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_addr:32; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_addr_reg_t; + + +/** Group: Operation Exception registers */ +/** Type of sync_l1_cache_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ + uint32_t l1_cache_pld_err_code:2; + uint32_t reserved_10:2; + /** sync_err_code : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ + uint32_t sync_err_code:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_exception_reg_t; + + +/** Group: Sync Reset control and configuration registers */ +/** Type of l1_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_cache_sync_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_sync_rst_ctrl_reg_t; + + +/** Group: Preload Reset control and configuration registers */ +/** Type of l1_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_cache_pld_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_preload_rst_ctrl_reg_t; + + +/** Group: Autoload buffer clear control and configuration registers */ +/** Type of l1_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ + uint32_t l1_cache_ald_buf_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_autoload_buf_clr_ctrl_reg_t; + + +/** Group: Unallocate request buffer clear registers */ +/** Type of l1_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_cache_unalloc_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_unallocate_buffer_clear_reg_t; + + +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_tag_object:1; + uint32_t reserved_5:5; + /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_mem_object:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} cache_l1_cache_object_ctrl_reg_t; + +/** Type of l1_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l1_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} cache_l1_cache_way_object_reg_t; + +/** Type of l1_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l1_cache_vaddr:32; + }; + uint32_t val; +} cache_l1_cache_vaddr_reg_t; + +/** Type of l1_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 616; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l1_cache_debug_bus:32; + }; + uint32_t val; +} cache_l1_cache_debug_bus_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716800; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_date_reg_t; + + +typedef struct cache_dev_t { + uint32_t reserved_000; + volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl; + uint32_t reserved_008[6]; + volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; + volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl; + volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl; + volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; + volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; + volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; + uint32_t reserved_038[16]; + volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; + volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; + volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; + volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile cache_lock_ctrl_reg_t lock_ctrl; + volatile cache_lock_map_reg_t lock_map; + volatile cache_lock_addr_reg_t lock_addr; + volatile cache_lock_size_reg_t lock_size; + volatile cache_sync_ctrl_reg_t sync_ctrl; + volatile cache_sync_map_reg_t sync_map; + volatile cache_sync_addr_reg_t sync_addr; + volatile cache_sync_size_reg_t sync_size; + uint32_t reserved_0a8[12]; + volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; + volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; + volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size; + uint32_t reserved_0e4[20]; + volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; + volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; + volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; + volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; + volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; + uint32_t reserved_148[4]; + volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; + volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; + volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; + volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; + volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl; + volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; + volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; + volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; + volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; + volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; + uint32_t reserved_180[16]; + volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; + volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; + volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; + volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt; + volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; + volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; + volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; + volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt; + uint32_t reserved_1e8[10]; + volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; + volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; + volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; + volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; + uint32_t reserved_220[4]; + volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr; + volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + volatile cache_sync_l1_cache_preload_int_ena_reg_t sync_l1_cache_preload_int_ena; + volatile cache_sync_l1_cache_preload_int_clr_reg_t sync_l1_cache_preload_int_clr; + volatile cache_sync_l1_cache_preload_int_raw_reg_t sync_l1_cache_preload_int_raw; + volatile cache_sync_l1_cache_preload_int_st_reg_t sync_l1_cache_preload_int_st; + volatile cache_sync_l1_cache_preload_exception_reg_t sync_l1_cache_preload_exception; + volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; + volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; + volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; + volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; + volatile cache_l1_cache_way_object_reg_t l1_cache_way_object; + volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr; + volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus; + uint32_t reserved_26c[100]; + volatile cache_date_reg_t date; +} cache_dev_t; + +extern cache_dev_t CACHE; + +#ifndef __cplusplus +_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/clic_reg.h b/components/soc/esp32c5/include/soc/clic_reg.h new file mode 100644 index 00000000000..1bfe74d623e --- /dev/null +++ b/components/soc/esp32c5/include/soc/clic_reg.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define NLBITS 3 +#define CLIC_EXT_INTR_NUM_OFFSET 16 +#define DUALCORE_CLIC_CTRL_OFF 0x10000 + +#define DR_REG_CLIC_BASE ( 0x20800000 ) +#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 ) + +#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0) +/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NMBITS 0x00000003 +#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S)) +#define CLIC_INT_CONFIG_NMBITS_V 0x3 +#define CLIC_INT_CONFIG_NMBITS_S 5 +/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NLBITS 0x0000000F +#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S)) +#define CLIC_INT_CONFIG_NLBITS_V 0xF +#define CLIC_INT_CONFIG_NLBITS_S 1 +/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NVBITS (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_M (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_V 0x1 +#define CLIC_INT_CONFIG_NVBITS_S 0 + +#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4) +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_CTLBITS 0x0000000F +#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S)) +#define CLIC_INT_INFO_CTLBITS_V 0xF +#define CLIC_INT_INFO_CTLBITS_S 21 +/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_VERSION 0x000000FF +#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S)) +#define CLIC_INT_INFO_VERSION_V 0xFF +#define CLIC_INT_INFO_VERSION_S 13 +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_NUM_INT 0x00001FFF +#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S)) +#define CLIC_INT_INFO_NUM_INT_V 0x1FFF +#define CLIC_INT_INFO_NUM_INT_S 0 + +#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8) +/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_CPU_INT_THRESH 0x000000FF +#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S)) +#define CLIC_CPU_INT_THRESH_V 0xFF +#define CLIC_CPU_INT_THRESH_S 24 + +#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4) +/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_CTL 0x000000FF +#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S)) +#define CLIC_INT_CTL_V 0xFF +#define CLIC_INT_CTL_S 24 +/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_MODE 0x00000003 +#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S)) +#define CLIC_INT_ATTR_MODE_V 0x3 +#define CLIC_INT_ATTR_MODE_S 22 +/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_TRIG 0x00000003 +#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S)) +#define CLIC_INT_ATTR_TRIG_V 0x3 +#define CLIC_INT_ATTR_TRIG_S 17 +/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_SHV (BIT(16)) +#define CLIC_INT_ATTR_SHV_M (BIT(16)) +#define CLIC_INT_ATTR_SHV_V 0x1 +#define CLIC_INT_ATTR_SHV_S 16 +/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IE (BIT(8)) +#define CLIC_INT_IE_M (BIT(8)) +#define CLIC_INT_IE_V 0x1 +#define CLIC_INT_IE_S 8 +/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IP (BIT(0)) +#define CLIC_INT_IP_M (BIT(0)) +#define CLIC_INT_IP_V 0x1 +#define CLIC_INT_IP_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h new file mode 100644 index 00000000000..77412234004 --- /dev/null +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -0,0 +1,485 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32C5 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 40MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +// TODO: [ESP32C5] IDF-8642 (inherit from C6) +/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ + SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ + // For LP peripherals + SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ + + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6) + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) + GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) + TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ +} soc_periph_tg_clk_src_legacy_t; + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of RMT + */ +#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of RMT clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6) + RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_rmt_clk_src_t; + +/** + * @brief Type of RMT clock source, reserved for the legacy RMT driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6) + RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */ + RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ +} soc_periph_rmt_clk_src_legacy_t; + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Temperature Sensor + */ +#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of Temp Sensor clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6) + TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +} soc_periph_temperature_sensor_clk_src_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8722 (inherit from C6) + UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ +} soc_periph_uart_clk_src_legacy_t; + +/** + * @brief Type of LP_UART clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6) + LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ + LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ + LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ +} soc_periph_lp_uart_clk_src_t; + +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_capture_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Carrier + */ +#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM carrier clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_carrier_clk_src_t; + +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} + +/** + * @brief I2S clock source enum + */ +typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6) + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ + I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ +} soc_periph_i2s_clk_src_t; + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2C + */ +#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of I2C clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8694, IDF-8696 (inherit from C6) + I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ +} soc_periph_i2c_clk_src_t; + +///////////////////////////////////////////////LP_I2C/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LP_I2C + */ +#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} + +/** + * @brief Type of LP_I2C clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6) + LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */ + LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */ + LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */ +} soc_periph_lp_i2c_clk_src_t; + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6) + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SDM + */ +#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Sigma Delta Modulator clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8687 (inherit from C6) + SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_sdm_clk_src_t; + +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Glitch Filter + */ +#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Glitch filter clock source + */ + +typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6) + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + +//////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of TWAI + */ +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} + +/** + * @brief TWAI clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6) + TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +} soc_periph_twai_clk_src_t; + +//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of ADC digital controller + */ +#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief ADC digital controller clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6) + ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ +} soc_periph_adc_digi_clk_src_t; + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6) + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LEDC + */ +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of LEDC clock source, reserved for the legacy LEDC driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8684 (inherit from C6) + LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + + LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ +} soc_periph_ledc_clk_src_legacy_t; + +//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of PARLIO + */ +#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} + +/** + * @brief PARLIO clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6) + PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ + PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ +} soc_periph_parlio_clk_src_t; + +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ + CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ + CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */ + CLKOUT_SIG_CPU = 16, /*!< CPU clock */ + CLKOUT_SIG_AHB = 17, /*!< AHB clock */ + CLKOUT_SIG_APB = 18, /*!< APB clock */ + CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ + CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ + CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ + CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/dport_access.h b/components/soc/esp32c5/include/soc/dport_access.h new file mode 100644 index 00000000000..d5d1550b607 --- /dev/null +++ b/components/soc/esp32c5/include/soc/dport_access.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ds_reg.h b/components/soc/esp32c5/include/soc/ds_reg.h new file mode 100644 index 00000000000..d164a129309 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ds_reg.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** DS_Y_MEM register + * memory that stores Y + */ +#define DS_Y_MEM (DR_REG_DS_BASE + 0x0) +#define DS_Y_MEM_SIZE_BYTES 512 + +/** DS_M_MEM register + * memory that stores M + */ +#define DS_M_MEM (DR_REG_DS_BASE + 0x200) +#define DS_M_MEM_SIZE_BYTES 512 + +/** DS_RB_MEM register + * memory that stores Rb + */ +#define DS_RB_MEM (DR_REG_DS_BASE + 0x400) +#define DS_RB_MEM_SIZE_BYTES 512 + +/** DS_BOX_MEM register + * memory that stores BOX + */ +#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600) +#define DS_BOX_MEM_SIZE_BYTES 48 + +/** DS_IV_MEM register + * memory that stores IV + */ +#define DS_IV_MEM (DR_REG_DS_BASE + 0x630) +#define DS_IV_MEM_SIZE_BYTES 16 + +/** DS_X_MEM register + * memory that stores X + */ +#define DS_X_MEM (DR_REG_DS_BASE + 0x800) +#define DS_X_MEM_SIZE_BYTES 512 + +/** DS_Z_MEM register + * memory that stores Z + */ +#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00) +#define DS_Z_MEM_SIZE_BYTES 512 + +/** DS_SET_START_REG register + * DS start control register + */ +#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00) +/** DS_SET_START : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ +#define DS_SET_START (BIT(0)) +#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S) +#define DS_SET_START_V 0x00000001U +#define DS_SET_START_S 0 + +/** DS_SET_CONTINUE_REG register + * DS continue control register + */ +#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04) +/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ +#define DS_SET_CONTINUE (BIT(0)) +#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S) +#define DS_SET_CONTINUE_V 0x00000001U +#define DS_SET_CONTINUE_S 0 + +/** DS_SET_FINISH_REG register + * DS finish control register + */ +#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08) +/** DS_SET_FINISH : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ +#define DS_SET_FINISH (BIT(0)) +#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S) +#define DS_SET_FINISH_V 0x00000001U +#define DS_SET_FINISH_S 0 + +/** DS_QUERY_BUSY_REG register + * DS query busy register + */ +#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c) +/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ +#define DS_QUERY_BUSY (BIT(0)) +#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S) +#define DS_QUERY_BUSY_V 0x00000001U +#define DS_QUERY_BUSY_S 0 + +/** DS_QUERY_KEY_WRONG_REG register + * DS query key-wrong counter register + */ +#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10) +/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ +#define DS_QUERY_KEY_WRONG 0x0000000FU +#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S) +#define DS_QUERY_KEY_WRONG_V 0x0000000FU +#define DS_QUERY_KEY_WRONG_S 0 + +/** DS_QUERY_CHECK_REG register + * DS query check result register + */ +#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14) +/** DS_MD_ERROR : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ +#define DS_MD_ERROR (BIT(0)) +#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S) +#define DS_MD_ERROR_V 0x00000001U +#define DS_MD_ERROR_S 0 +/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ +#define DS_PADDING_BAD (BIT(1)) +#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S) +#define DS_PADDING_BAD_V 0x00000001U +#define DS_PADDING_BAD_S 1 + +/** DS_DATE_REG register + * DS version control register + */ +#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20) +/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ +#define DS_DATE 0x3FFFFFFFU +#define DS_DATE_M (DS_DATE_V << DS_DATE_S) +#define DS_DATE_V 0x3FFFFFFFU +#define DS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ds_struct.h b/components/soc/esp32c5/include/soc/ds_struct.h new file mode 100644 index 00000000000..74682d8e178 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ds_struct.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: memory type */ + +/** Group: Control/Status registers */ +/** Type of set_start register + * DS start control register + */ +typedef union { + struct { + /** set_start : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_start_reg_t; + +/** Type of set_continue register + * DS continue control register + */ +typedef union { + struct { + /** set_continue : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ + uint32_t set_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_continue_reg_t; + +/** Type of set_finish register + * DS finish control register + */ +typedef union { + struct { + /** set_finish : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ + uint32_t set_finish:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_finish_reg_t; + +/** Type of query_busy register + * DS query busy register + */ +typedef union { + struct { + /** query_busy : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ + uint32_t query_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_query_busy_reg_t; + +/** Type of query_key_wrong register + * DS query key-wrong counter register + */ +typedef union { + struct { + /** query_key_wrong : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ + uint32_t query_key_wrong:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ds_query_key_wrong_reg_t; + +/** Type of query_check register + * DS query check result register + */ +typedef union { + struct { + /** md_error : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ + uint32_t md_error:1; + /** padding_bad : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ + uint32_t padding_bad:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ds_query_check_reg_t; + + +/** Group: version control register */ +/** Type of date register + * DS version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} ds_date_reg_t; + + +typedef struct ds_dev_t { + volatile uint32_t y[128]; + volatile uint32_t m[128]; + volatile uint32_t rb[128]; + volatile uint32_t box[12]; + volatile uint32_t iv[4]; + uint32_t reserved_640[112]; + volatile uint32_t x[128]; + volatile uint32_t z[128]; + uint32_t reserved_c00[128]; + volatile ds_set_start_reg_t set_start; + volatile ds_set_continue_reg_t set_continue; + volatile ds_set_finish_reg_t set_finish; + volatile ds_query_busy_reg_t query_busy; + volatile ds_query_key_wrong_reg_t query_key_wrong; + volatile ds_query_check_reg_t query_check; + uint32_t reserved_e18[2]; + volatile ds_date_reg_t date; +} ds_dev_t; + +extern ds_dev_t DS; + +#ifndef __cplusplus +_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/include/soc/ecc_mult_reg.h new file mode 100644 index 00000000000..c67c09ab477 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecc_mult_reg.h @@ -0,0 +1,167 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECC_MULT_INT_RAW_REG register + * ECC interrupt raw register, valid in level. + */ +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) +/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +/** ECC_MULT_INT_ST_REG register + * ECC interrupt status register. + */ +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) +/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +/** ECC_MULT_INT_ENA_REG register + * ECC interrupt enable register. + */ +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) +/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +/** ECC_MULT_INT_CLR_REG register + * ECC interrupt clear register. + */ +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) +/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +/** ECC_MULT_CONF_REG register + * ECC configure register + */ +#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) +/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) +#define ECC_MULT_START_V 0x00000001U +#define ECC_MULT_START_S 0 +/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) +#define ECC_MULT_RESET_V 0x00000001U +#define ECC_MULT_RESET_S 1 +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ +#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) +#define ECC_MULT_KEY_LENGTH_V 0x00000001U +#define ECC_MULT_KEY_LENGTH_S 2 +/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0; + * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). + * 1: p(mod base of curve) + */ +#define ECC_MULT_MOD_BASE (BIT(3)) +#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) +#define ECC_MULT_MOD_BASE_V 0x00000001U +#define ECC_MULT_MOD_BASE_S 3 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point + * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point + * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + */ +#define ECC_MULT_WORK_MODE 0x0000000FU +#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) +#define ECC_MULT_WORK_MODE_V 0x0000000FU +#define ECC_MULT_WORK_MODE_S 4 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define ECC_MULT_SECURITY_MODE (BIT(8)) +#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) +#define ECC_MULT_SECURITY_MODE_V 0x00000001U +#define ECC_MULT_SECURITY_MODE_S 8 +/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ +#define ECC_MULT_VERIFICATION_RESULT (BIT(29)) +#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) +#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U +#define ECC_MULT_VERIFICATION_RESULT_S 29 +/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECC_MULT_CLK_EN (BIT(30)) +#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) +#define ECC_MULT_CLK_EN_V 0x00000001U +#define ECC_MULT_CLK_EN_S 30 +/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0; + * ECC memory clock gate force on register + */ +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 + +/** ECC_MULT_DATE_REG register + * Version control register + */ +#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704; + * ECC mult version control register + */ +#define ECC_MULT_DATE 0x0FFFFFFFU +#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) +#define ECC_MULT_DATE_V 0x0FFFFFFFU +#define ECC_MULT_DATE_S 0 + +/** ECC_MULT_K_MEM register + * The memory that stores k. + */ +#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) +#define ECC_MULT_K_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PX_MEM register + * The memory that stores Px. + */ +#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) +#define ECC_MULT_PX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PY_MEM register + * The memory that stores Py. + */ +#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) +#define ECC_MULT_PY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/include/soc/ecc_mult_struct.h new file mode 100644 index 00000000000..da6e1030637 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecc_mult_struct.h @@ -0,0 +1,164 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECC interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_raw_reg_t; + +/** Type of int_st register + * ECC interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_st_reg_t; + +/** Type of int_ena register + * ECC interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_ena_reg_t; + +/** Type of int_clr register + * ECC interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of conf register + * ECC configure register + */ +typedef union { + struct { + /** start : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ + uint32_t start:1; + /** reset : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ + uint32_t reset:1; + /** key_length : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ + uint32_t key_length:1; + /** mod_base : R/W; bitpos: [3]; default: 0; + * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). + * 1: p(mod base of curve) + */ + uint32_t mod_base:1; + /** work_mode : R/W; bitpos: [7:4]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point + * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point + * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + */ + uint32_t work_mode:4; + /** security_mode : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t security_mode:1; + uint32_t reserved_9:20; + /** verification_result : RO/SS; bitpos: [29]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ + uint32_t verification_result:1; + /** clk_en : R/W; bitpos: [30]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0; + * ECC memory clock gate force on register + */ + uint32_t mem_clock_gate_force_on:1; + }; + uint32_t val; +} ecc_mult_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * ECC mult version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecc_mult_date_reg_t; + + +typedef struct ecc_mult_dev_t { + uint32_t reserved_000[3]; + volatile ecc_mult_int_raw_reg_t int_raw; + volatile ecc_mult_int_st_reg_t int_st; + volatile ecc_mult_int_ena_reg_t int_ena; + volatile ecc_mult_int_clr_reg_t int_clr; + volatile ecc_mult_conf_reg_t conf; + uint32_t reserved_020[55]; + volatile ecc_mult_date_reg_t date; + volatile uint32_t k[8]; + volatile uint32_t px[8]; + volatile uint32_t py[8]; +} ecc_mult_dev_t; + +extern ecc_mult_dev_t ECC; + +#ifndef __cplusplus +_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecdsa_reg.h b/components/soc/esp32c5/include/soc/ecdsa_reg.h new file mode 100644 index 00000000000..6e09925e090 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecdsa_reg.h @@ -0,0 +1,318 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECDSA_CONF_REG register + * ECDSA configure register + */ +#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) +/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ +#define ECDSA_WORK_MODE 0x00000003U +#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) +#define ECDSA_WORK_MODE_V 0x00000003U +#define ECDSA_WORK_MODE_S 0 +/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ +#define ECDSA_ECC_CURVE (BIT(2)) +#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) +#define ECDSA_ECC_CURVE_V 0x00000001U +#define ECDSA_ECC_CURVE_S 2 +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ +#define ECDSA_SOFTWARE_SET_K (BIT(3)) +#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) +#define ECDSA_SOFTWARE_SET_K_V 0x00000001U +#define ECDSA_SOFTWARE_SET_K_S 3 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ +#define ECDSA_SOFTWARE_SET_Z (BIT(4)) +#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) +#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U +#define ECDSA_SOFTWARE_SET_Z_S 4 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ +#define ECDSA_DETERMINISTIC_K (BIT(5)) +#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) +#define ECDSA_DETERMINISTIC_K_V 0x00000001U +#define ECDSA_DETERMINISTIC_K_S 5 +/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0; + * The (loop number - 1) value in the deterministic derivation algorithm to derive k. + */ +#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU +#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S) +#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU +#define ECDSA_DETERMINISTIC_LOOP_S 6 + +/** ECDSA_CLK_REG register + * ECDSA clock gate register + */ +#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) +/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) +#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) +#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U +#define ECDSA_CLK_GATE_FORCE_ON_S 0 + +/** ECDSA_INT_RAW_REG register + * ECDSA interrupt raw register, valid in level. + */ +#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) +/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_RAW (BIT(0)) +#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S) +#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U +#define ECDSA_CALC_DONE_INT_RAW_S 0 +/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) +#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_RAW_S 1 + +/** ECDSA_INT_ST_REG register + * ECDSA interrupt status register. + */ +#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) +/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_ST (BIT(0)) +#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S) +#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U +#define ECDSA_CALC_DONE_INT_ST_S 0 +/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ST (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) +#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ST_S 1 + +/** ECDSA_INT_ENA_REG register + * ECDSA interrupt enable register. + */ +#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) +/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_ENA (BIT(0)) +#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S) +#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U +#define ECDSA_CALC_DONE_INT_ENA_S 0 +/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) +#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ENA_S 1 + +/** ECDSA_INT_CLR_REG register + * ECDSA interrupt clear register. + */ +#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) +/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_CLR (BIT(0)) +#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S) +#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U +#define ECDSA_CALC_DONE_INT_CLR_S 0 +/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) +#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_CLR_S 1 + +/** ECDSA_START_REG register + * ECDSA start register + */ +#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) +/** ECDSA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ +#define ECDSA_START (BIT(0)) +#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) +#define ECDSA_START_V 0x00000001U +#define ECDSA_START_S 0 +/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_LOAD_DONE (BIT(1)) +#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) +#define ECDSA_LOAD_DONE_V 0x00000001U +#define ECDSA_LOAD_DONE_S 1 +/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_GET_DONE (BIT(2)) +#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) +#define ECDSA_GET_DONE_V 0x00000001U +#define ECDSA_GET_DONE_S 2 + +/** ECDSA_STATE_REG register + * ECDSA status register + */ +#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) +/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ +#define ECDSA_BUSY 0x00000003U +#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) +#define ECDSA_BUSY_V 0x00000003U +#define ECDSA_BUSY_S 0 + +/** ECDSA_RESULT_REG register + * ECDSA result register + */ +#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) +/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ +#define ECDSA_OPERATION_RESULT (BIT(0)) +#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) +#define ECDSA_OPERATION_RESULT_V 0x00000001U +#define ECDSA_OPERATION_RESULT_S 0 +/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0; + * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the + * curve order, then actually taken k = k mod n. + */ +#define ECDSA_K_VALUE_WARNING (BIT(1)) +#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S) +#define ECDSA_K_VALUE_WARNING_V 0x00000001U +#define ECDSA_K_VALUE_WARNING_S 1 + +/** ECDSA_DATE_REG register + * Version control register + */ +#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656; + * ECDSA version control register + */ +#define ECDSA_DATE 0x0FFFFFFFU +#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) +#define ECDSA_DATE_V 0x0FFFFFFFU +#define ECDSA_DATE_S 0 + +/** ECDSA_SHA_MODE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) +/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ +#define ECDSA_SHA_MODE 0x00000007U +#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) +#define ECDSA_SHA_MODE_V 0x00000007U +#define ECDSA_SHA_MODE_S 0 + +/** ECDSA_SHA_START_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) +/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_START (BIT(0)) +#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) +#define ECDSA_SHA_START_V 0x00000001U +#define ECDSA_SHA_START_S 0 + +/** ECDSA_SHA_CONTINUE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) +/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_CONTINUE (BIT(0)) +#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) +#define ECDSA_SHA_CONTINUE_V 0x00000001U +#define ECDSA_SHA_CONTINUE_S 0 + +/** ECDSA_SHA_BUSY_REG register + * ECDSA status register + */ +#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) +/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ +#define ECDSA_SHA_BUSY (BIT(0)) +#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) +#define ECDSA_SHA_BUSY_V 0x00000001U +#define ECDSA_SHA_BUSY_S 0 + +/** ECDSA_MESSAGE_MEM register + * The memory that stores message. + */ +#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 + +/** ECDSA_R_MEM register + * The memory that stores r. + */ +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00) +#define ECDSA_R_MEM_SIZE_BYTES 32 + +/** ECDSA_S_MEM register + * The memory that stores s. + */ +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20) +#define ECDSA_S_MEM_SIZE_BYTES 32 + +/** ECDSA_Z_MEM register + * The memory that stores software written z. + */ +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40) +#define ECDSA_Z_MEM_SIZE_BYTES 32 + +/** ECDSA_QAX_MEM register + * The memory that stores x coordinates of QA or software written k. + */ +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60) +#define ECDSA_QAX_MEM_SIZE_BYTES 32 + +/** ECDSA_QAY_MEM register + * The memory that stores y coordinates of QA. + */ +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80) +#define ECDSA_QAY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecdsa_struct.h b/components/soc/esp32c5/include/soc/ecdsa_struct.h new file mode 100644 index 00000000000..c319499a4de --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecdsa_struct.h @@ -0,0 +1,324 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Data Memory */ + +/** Group: Configuration registers */ +/** Type of conf register + * ECDSA configure register + */ +typedef union { + struct { + /** work_mode : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ + uint32_t work_mode:2; + /** ecc_curve : R/W; bitpos: [2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ + uint32_t ecc_curve:1; + /** software_set_k : R/W; bitpos: [3]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ + uint32_t software_set_k:1; + /** software_set_z : R/W; bitpos: [4]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ + uint32_t software_set_z:1; + /** deterministic_k : R/W; bitpos: [5]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ + uint32_t deterministic_k:1; + /** deterministic_loop : R/W; bitpos: [21:6]; default: 0; + * The (loop number - 1) value in the deterministic derivation algorithm to derive k. + */ + uint32_t deterministic_loop:16; + uint32_t reserved_22:10; + }; + uint32_t val; +} ecdsa_conf_reg_t; + +/** Type of start register + * ECDSA start register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ + uint32_t start:1; + /** load_done : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t load_done:1; + /** get_done : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t get_done:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_start_reg_t; + + +/** Group: Clock and reset registers */ +/** Type of clk register + * ECDSA clock gate register + */ +typedef union { + struct { + /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_gate_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECDSA interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_raw_reg_t; + +/** Type of int_st register + * ECDSA interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + /** sha_release_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_st_reg_t; + +/** Type of int_ena register + * ECDSA interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + /** sha_release_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_ena_reg_t; + +/** Type of int_clr register + * ECDSA interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + /** sha_release_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_clr_reg_t; + + +/** Group: Status registers */ +/** Type of state register + * ECDSA status register + */ +typedef union { + struct { + /** busy : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ + uint32_t busy:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * ECDSA result register + */ +typedef union { + struct { + /** operation_result : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ + uint32_t operation_result:1; + /** k_value_warning : RO/SS; bitpos: [1]; default: 0; + * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the + * curve order, then actually taken k = k mod n. + */ + uint32_t k_value_warning:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_result_reg_t; + + +/** Group: SHA register */ +/** Type of sha_mode register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_mode : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ + uint32_t sha_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_sha_mode_reg_t; + +/** Type of sha_start register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_start : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_start_reg_t; + +/** Type of sha_continue register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_continue : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_continue_reg_t; + +/** Type of sha_busy register + * ECDSA status register + */ +typedef union { + struct { + /** sha_busy : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ + uint32_t sha_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_busy_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716656; + * ECDSA version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecdsa_date_reg_t; + + +typedef struct ecdsa_dev_t { + uint32_t reserved_000; + volatile ecdsa_conf_reg_t conf; + volatile ecdsa_clk_reg_t clk; + volatile ecdsa_int_raw_reg_t int_raw; + volatile ecdsa_int_st_reg_t int_st; + volatile ecdsa_int_ena_reg_t int_ena; + volatile ecdsa_int_clr_reg_t int_clr; + volatile ecdsa_start_reg_t start; + volatile ecdsa_state_reg_t state; + volatile ecdsa_result_reg_t result; + uint32_t reserved_028[53]; + volatile ecdsa_date_reg_t date; + uint32_t reserved_100[64]; + volatile ecdsa_sha_mode_reg_t sha_mode; + uint32_t reserved_204[3]; + volatile ecdsa_sha_start_reg_t sha_start; + volatile ecdsa_sha_continue_reg_t sha_continue; + volatile ecdsa_sha_busy_reg_t sha_busy; + uint32_t reserved_21c[25]; + volatile uint32_t message[8]; + uint32_t reserved_2a0[472]; + volatile uint32_t r[8]; + volatile uint32_t s[8]; + volatile uint32_t z[8]; + volatile uint32_t qax[8]; + volatile uint32_t qay[8]; +} ecdsa_dev_t; + +extern ecdsa_dev_t ECDSA; + +#ifndef __cplusplus +_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/efuse_reg.h b/components/soc/esp32c5/include/soc/efuse_reg.h new file mode 100644 index 00000000000..0d9424909a9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/efuse_reg.h @@ -0,0 +1,2365 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 + +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 + +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_S 0 + +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_WR_DIS_S 0 + +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_HUK_GEN_STATE_PART1 : RO; bitpos: [31:27]; default: 0; + * Represents the validation of HUK generate mode. + */ +#define EFUSE_HUK_GEN_STATE_PART1 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_M (EFUSE_HUK_GEN_STATE_PART1_V << EFUSE_HUK_GEN_STATE_PART1_S) +#define EFUSE_HUK_GEN_STATE_PART1_V 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_S 27 + +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_HUK_GEN_STATE_PART2 : RO; bitpos: [3:0]; default: 0; + * Represents the validation of HUK generate mode. + */ +#define EFUSE_HUK_GEN_STATE_PART2 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_M (EFUSE_HUK_GEN_STATE_PART2_V << EFUSE_HUK_GEN_STATE_PART2_S) +#define EFUSE_HUK_GEN_STATE_PART2_V 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0; + * Represents the key manager random number switch cycle. + */ +#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_S 4 +/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0; + * Represents whether corresponding key can only be deployed once. + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 6 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0; + * Represents which corresponding key must come from key manager. + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 10 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0; + * Represents whether to disable software written init key and force use + * efuse_init_key. + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(14)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 +/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [15]; default: 0; + * TBD. + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE (BIT(15)) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x00000001U +#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 15 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 + +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ +#define EFUSE_SEC_DPA_LEVEL 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) +#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_S 16 +/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0; + * TBD. + */ +#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) +#define EFUSE_ECDSA_ENABLE_SOFT_K_M (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S) +#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x00000001U +#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ +#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) +#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_S 19 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 + +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; + * TBD. + */ +#define EFUSE_LOCK_KM_KEY (BIT(3)) +#define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) +#define EFUSE_LOCK_KM_KEY_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 8 +/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 +/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ +#define EFUSE_HYS_EN_PAD (BIT(26)) +#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) +#define EFUSE_HYS_EN_PAD_V 0x00000001U +#define EFUSE_HYS_EN_PAD_S 26 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_RESERVED_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RESERVED_0 0x000000FFU +#define EFUSE_RESERVED_0_M (EFUSE_RESERVED_0_V << EFUSE_RESERVED_0_S) +#define EFUSE_RESERVED_0_V 0x000000FFU +#define EFUSE_RESERVED_0_S 24 + +/** EFUSE_RD_MAC_SYS_0_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU +#define EFUSE_MAC_0_S 0 + +/** EFUSE_RD_MAC_SYS_1_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 + +/** EFUSE_RD_MAC_SYS_2_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_S 0 +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_0 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_S 14 + +/** EFUSE_RD_MAC_SYS_3_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/** EFUSE_RD_MAC_SYS_4_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/** EFUSE_RD_MAC_SYS_5_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/** EFUSE_RD_USR_DATA0_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU +#define EFUSE_USR_DATA0_S 0 + +/** EFUSE_RD_USR_DATA1_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU +#define EFUSE_USR_DATA1_S 0 + +/** EFUSE_RD_USR_DATA2_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU +#define EFUSE_USR_DATA2_S 0 + +/** EFUSE_RD_USR_DATA3_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU +#define EFUSE_USR_DATA3_S 0 + +/** EFUSE_RD_USR_DATA4_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU +#define EFUSE_USR_DATA4_S 0 + +/** EFUSE_RD_USR_DATA5_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU +#define EFUSE_USR_DATA5_S 0 + +/** EFUSE_RD_USR_DATA6_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 + +/** EFUSE_RD_USR_DATA7_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_S 0 + +/** EFUSE_RD_KEY0_DATA1_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_S 0 + +/** EFUSE_RD_KEY0_DATA2_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_S 0 + +/** EFUSE_RD_KEY0_DATA3_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_S 0 + +/** EFUSE_RD_KEY0_DATA4_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_S 0 + +/** EFUSE_RD_KEY0_DATA5_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_S 0 + +/** EFUSE_RD_KEY0_DATA6_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_S 0 + +/** EFUSE_RD_KEY0_DATA7_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_S 0 + +/** EFUSE_RD_KEY1_DATA0_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_S 0 + +/** EFUSE_RD_KEY1_DATA1_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_S 0 + +/** EFUSE_RD_KEY1_DATA2_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_S 0 + +/** EFUSE_RD_KEY1_DATA3_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_S 0 + +/** EFUSE_RD_KEY1_DATA4_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_S 0 + +/** EFUSE_RD_KEY1_DATA5_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_S 0 + +/** EFUSE_RD_KEY1_DATA6_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_S 0 + +/** EFUSE_RD_KEY1_DATA7_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_S 0 + +/** EFUSE_RD_KEY2_DATA0_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_S 0 + +/** EFUSE_RD_KEY2_DATA1_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_S 0 + +/** EFUSE_RD_KEY2_DATA2_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_S 0 + +/** EFUSE_RD_KEY2_DATA3_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_S 0 + +/** EFUSE_RD_KEY2_DATA4_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_S 0 + +/** EFUSE_RD_KEY2_DATA5_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_S 0 + +/** EFUSE_RD_KEY2_DATA6_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_S 0 + +/** EFUSE_RD_KEY2_DATA7_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_S 0 + +/** EFUSE_RD_KEY3_DATA0_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_S 0 + +/** EFUSE_RD_KEY3_DATA1_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_S 0 + +/** EFUSE_RD_KEY3_DATA2_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_S 0 + +/** EFUSE_RD_KEY3_DATA3_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_S 0 + +/** EFUSE_RD_KEY3_DATA4_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_S 0 + +/** EFUSE_RD_KEY3_DATA5_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_S 0 + +/** EFUSE_RD_KEY3_DATA6_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_S 0 + +/** EFUSE_RD_KEY3_DATA7_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_S 0 + +/** EFUSE_RD_KEY4_DATA0_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_S 0 + +/** EFUSE_RD_KEY4_DATA1_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_S 0 + +/** EFUSE_RD_KEY4_DATA2_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_S 0 + +/** EFUSE_RD_KEY4_DATA3_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_S 0 + +/** EFUSE_RD_KEY4_DATA4_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_S 0 + +/** EFUSE_RD_KEY4_DATA5_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_S 0 + +/** EFUSE_RD_KEY4_DATA6_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_S 0 + +/** EFUSE_RD_KEY4_DATA7_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_S 0 + +/** EFUSE_RD_KEY5_DATA0_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_S 0 + +/** EFUSE_RD_KEY5_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_S 0 + +/** EFUSE_RD_KEY5_DATA2_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_S 0 + +/** EFUSE_RD_KEY5_DATA3_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_S 0 + +/** EFUSE_RD_KEY5_DATA4_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_S 0 + +/** EFUSE_RD_KEY5_DATA5_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_S 0 + +/** EFUSE_RD_KEY5_DATA6_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_S 0 + +/** EFUSE_RD_KEY5_DATA7_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_S 0 + +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 +/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) +#define EFUSE_DIS_TWAI_ERR_V 0x00000001U +#define EFUSE_DIS_TWAI_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_HUK_GEN_STATE_PART1_ERR : RO; bitpos: [31:27]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART1. + */ +#define EFUSE_HUK_GEN_STATE_PART1_ERR 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_ERR_M (EFUSE_HUK_GEN_STATE_PART1_ERR_V << EFUSE_HUK_GEN_STATE_PART1_ERR_S) +#define EFUSE_HUK_GEN_STATE_PART1_ERR_V 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_ERR_S 27 + +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_HUK_GEN_STATE_PART2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART2. + */ +#define EFUSE_HUK_GEN_STATE_PART2_ERR 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_ERR_M (EFUSE_HUK_GEN_STATE_PART2_ERR_V << EFUSE_HUK_GEN_STATE_PART2_ERR_S) +#define EFUSE_HUK_GEN_STATE_PART2_ERR_V 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_ERR_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0; + * Indicates a programming error of EFUSE_KM_RND_SWITCH_CYCLE. + */ +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 4 +/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0; + * Indicates a programming error of EFUSE_KM_DEPLOY_ONLY_ONCE. + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 6 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0; + * Indicates a programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY. + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 10 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY. + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(14)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 14 +/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of EFUSE_KM_DISABLE_DEPLOY_MODE. + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR (BIT(15)) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x00000001U +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 15 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 +/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0; + * Reserved. + */ +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S) +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x00000001U +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 +/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ +#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; + * TBD. + */ +#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) +#define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) +#define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_ERR_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 +/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of HYS_EN_PAD. + */ +#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) +#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) +#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U +#define EFUSE_HYS_EN_PAD_ERR_S 26 + +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +/** EFUSE_RESERVED_0_ERR : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RESERVED_0_ERR 0x000000FFU +#define EFUSE_RESERVED_0_ERR_M (EFUSE_RESERVED_0_ERR_V << EFUSE_RESERVED_0_ERR_S) +#define EFUSE_RESERVED_0_ERR_V 0x000000FFU +#define EFUSE_RESERVED_0_ERR_S 24 + +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_MAC_SYS_ERR_NUM_M (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S) +#define EFUSE_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SYS is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_MAC_SYS_FAIL_M (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S) +#define EFUSE_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_MAC_SYS_FAIL_S 3 +/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART1_ERR_NUM_M (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S) +#define EFUSE_SYS_PART1_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_ERR_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 + +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 + +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 + +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 + +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U +#define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 + +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U +#define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U +#define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U +#define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U +#define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 + +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU +#define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 + +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU +#define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 + +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 + +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ +#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U +#define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/include/soc/efuse_struct.h new file mode 100644 index 00000000000..56bdc22ca28 --- /dev/null +++ b/components/soc/esp32c5/include/soc/efuse_struct.h @@ -0,0 +1,2244 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: ******** Registers */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t rd_dis:7; + uint32_t reserved_7:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_jtag:1; + uint32_t reserved_10:2; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t spi_download_mspi_dis:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_twai:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ + uint32_t dis_download_manual_encrypt:1; + uint32_t reserved_21:4; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ + uint32_t vdd_spi_as_gpio:1; + /** huk_gen_state_part1 : RO; bitpos: [31:27]; default: 0; + * Represents the validation of HUK generate mode. + */ + uint32_t huk_gen_state_part1:5; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** huk_gen_state_part2 : RO; bitpos: [3:0]; default: 0; + * Represents the validation of HUK generate mode. + */ + uint32_t huk_gen_state_part2:4; + /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0; + * Represents the key manager random number switch cycle. + */ + uint32_t km_rnd_switch_cycle:2; + /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0; + * Represents whether corresponding key can only be deployed once. + */ + uint32_t km_deploy_only_once:4; + /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0; + * Represents which corresponding key must come from key manager. + */ + uint32_t force_use_key_manager_key:4; + /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0; + * Represents whether to disable software written init key and force use + * efuse_init_key. + */ + uint32_t force_disable_sw_init_key:1; + /** km_disable_deploy_mode : RO; bitpos: [15]; default: 0; + * TBD. + */ + uint32_t km_disable_deploy_mode:1; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t sec_dpa_level:2; + /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0; + * TBD. + */ + uint32_t ecdsa_enable_soft_k:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ + uint32_t crypt_dpa_enable:1; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_aggressive_revoke:1; + uint32_t reserved_22:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** lock_km_key : RO; bitpos: [3]; default: 0; + * TBD. + */ + uint32_t lock_km_key:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ + uint32_t hys_en_pad:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + // TODO: [ESP32C5] IDF-8674 (inherit from C6) seems an error in csv, need to check + uint32_t reserved_0:24; + /** reserved_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_sys_0 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys_0_reg_t; + +/** Type of rd_mac_sys_1 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys_1_reg_t; + +/** Type of rd_mac_sys_2 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_1:14; + /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_0:18; + }; + uint32_t val; +} efuse_rd_mac_sys_2_reg_t; + +/** Type of rd_mac_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys_3_reg_t; + +/** Type of rd_mac_sys_4 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys_4_reg_t; + +/** Type of rd_mac_sys_5 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_0:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data6:32; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ + uint32_t usr_data7:32; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ + uint32_t rd_dis_err:7; + uint32_t reserved_7:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ + uint32_t dis_usb_jtag_err:1; + uint32_t reserved_10:2; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ + uint32_t spi_download_mspi_dis_err:1; + /** dis_twai_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ + uint32_t dis_twai_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + uint32_t reserved_21:4; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ + uint32_t vdd_spi_as_gpio_err:1; + /** huk_gen_state_part1_err : RO; bitpos: [31:27]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART1. + */ + uint32_t huk_gen_state_part1_err:5; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** huk_gen_state_part2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART2. + */ + uint32_t huk_gen_state_part2_err:4; + /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0; + * Indicates a programming error of EFUSE_KM_RND_SWITCH_CYCLE. + */ + uint32_t km_rnd_switch_cycle_err:2; + /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0; + * Indicates a programming error of EFUSE_KM_DEPLOY_ONLY_ONCE. + */ + uint32_t km_deploy_only_once_err:4; + /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0; + * Indicates a programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY. + */ + uint32_t force_use_key_manager_key_err:4; + /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY. + */ + uint32_t force_disable_sw_init_key_err:1; + /** km_disable_deploy_mode_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of EFUSE_KM_DISABLE_DEPLOY_MODE. + */ + uint32_t km_disable_deploy_mode_err:1; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_level_err:2; + /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0; + * Reserved. + */ + uint32_t ecdsa_enable_soft_k_err:1; + /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ + uint32_t crypt_dpa_enable_err:1; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + uint32_t reserved_22:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ + uint32_t dis_direct_boot_err:1; + /** usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ + uint32_t usb_serial_jtag_rom_print_err:1; + /** lock_km_key_err : RO; bitpos: [3]; default: 0; + * TBD. + */ + uint32_t lock_km_key_err:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ + uint32_t secure_version_err:16; + /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ + uint32_t secure_boot_disable_fast_wake_err:1; + /** hys_en_pad_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of HYS_EN_PAD. + */ + uint32_t hys_en_pad_err:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** reserved_0_err : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t reserved_0_err:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_sys_err_num:3; + /** mac_sys_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SYS is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_sys_fail:1; + /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_err_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ + uint32_t op_code:16; + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + uint32_t reserved_4:6; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct efuse_dev_t { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_190[12]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gdma_reg.h b/components/soc/esp32c5/include/soc/gdma_reg.h new file mode 100644 index 00000000000..bc014834e19 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gdma_reg.h @@ -0,0 +1,3213 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH2_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) +/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_M (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_M (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH2_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) +/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ST_M (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S) +#define GDMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ST_M (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S) +#define GDMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) +/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_M (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_M (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) +/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_M (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_M (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH2_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50) +/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH2_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54) +/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 +/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58) +/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c) +/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * MISC register + */ +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 36720912; + * register version. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configure 0 register of Rx channel 0 + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 + +/** GDMA_IN_CONF1_CH0_REG register + * Configure 1 register of Rx channel 0 + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of Rx channel 0 + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of Rx channel 0 + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Link descriptor configure and control register of Rx channel 0 + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 21 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 22 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 23 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 24 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of Rx channel 0 + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of Rx channel 0 + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection of Rx channel 0 + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configure 0 register of Tx channel 0 + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configure 1 register of Tx channel 0 + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of Tx channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of Rx channel 0 + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Link descriptor configure and control register of Tx channel 0 + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 20 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 21 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 23 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of Tx channel 0 + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection of Tx channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configure 0 register of Rx channel 1 + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 + +/** GDMA_IN_CONF1_CH1_REG register + * Configure 1 register of Rx channel 1 + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of Rx channel 1 + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of Rx channel 1 + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Link descriptor configure and control register of Rx channel 1 + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 21 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 22 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 23 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 24 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of Rx channel 1 + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when EOF occurs of Rx channel 1 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when errors occur of Rx channel 1 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of Rx channel 1 + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection of Rx channel 1 + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configure 0 register of Tx channel 1 + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configure 1 register of Tx channel 1 + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of Tx channel 1 + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of Rx channel 1 + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Link descriptor configure and control register of Tx channel 1 + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 20 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 21 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 23 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of Tx channel 1 + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Outlink descriptor address when EOF occurs of Tx channel 1 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 1 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of Tx channel 1 + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection of Tx channel 1 + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_IN_CONF0_CH2_REG register + * Configure 0 register of Rx channel 2 + */ +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) +/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S) +#define GDMA_IN_RST_CH2_V 0x00000001U +#define GDMA_IN_RST_CH2_S 0 +/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S) +#define GDMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S) +#define GDMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH2 (BIT(5)) +#define GDMA_IN_ETM_EN_CH2_M (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S) +#define GDMA_IN_ETM_EN_CH2_V 0x00000001U +#define GDMA_IN_ETM_EN_CH2_S 5 + +/** GDMA_IN_CONF1_CH2_REG register + * Configure 1 register of Rx channel 2 + */ +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) +/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH2_S 12 + +/** GDMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of Rx channel 2 + */ +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) +/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ +#define GDMA_INFIFO_FULL_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_CH2_M (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S) +#define GDMA_INFIFO_FULL_CH2_V 0x00000001U +#define GDMA_INFIFO_FULL_CH2_S 0 +/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ +#define GDMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH2_M (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S) +#define GDMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH2_S 1 +/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ +#define GDMA_INFIFO_CNT_CH2 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_M (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S) +#define GDMA_INFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_M (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_M (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_M (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_M (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH2_S 27 + +/** GDMA_IN_POP_CH2_REG register + * Pop control register of Rx channel 2 + */ +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) +/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_M (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S) +#define GDMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_S 0 +/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S) +#define GDMA_INFIFO_POP_CH2_V 0x00000001U +#define GDMA_INFIFO_POP_CH2_S 12 + +/** GDMA_IN_LINK_CH2_REG register + * Link descriptor configure and control register of Rx channel 2 + */ +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_M (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S) +#define GDMA_INLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_S 0 +/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S) +#define GDMA_INLINK_STOP_CH2_V 0x00000001U +#define GDMA_INLINK_STOP_CH2_S 21 +/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S) +#define GDMA_INLINK_START_CH2_V 0x00000001U +#define GDMA_INLINK_START_CH2_S 22 +/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S) +#define GDMA_INLINK_RESTART_CH2_V 0x00000001U +#define GDMA_INLINK_RESTART_CH2_S 23 +/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S) +#define GDMA_INLINK_PARK_CH2_V 0x00000001U +#define GDMA_INLINK_PARK_CH2_S 24 + +/** GDMA_IN_STATE_CH2_REG register + * Receive status of Rx channel 2 + */ +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_M (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_M (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S) +#define GDMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH2 0x00000007U +#define GDMA_IN_STATE_CH2_M (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S) +#define GDMA_IN_STATE_CH2_V 0x00000007U +#define GDMA_IN_STATE_CH2_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when EOF occurs of Rx channel 2 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when errors occur of Rx channel 2 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_DSCR_CH2_REG register + * Current inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_M (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_S 0 + +/** GDMA_IN_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_M (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_M (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_IN_PRI_CH2_REG register + * Priority register of Rx channel 2 + */ +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) +/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH2 0x0000000FU +#define GDMA_RX_PRI_CH2_M (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S) +#define GDMA_RX_PRI_CH2_V 0x0000000FU +#define GDMA_RX_PRI_CH2_S 0 + +/** GDMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection of Rx channel 2 + */ +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH2 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_M (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S) +#define GDMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_S 0 + +/** GDMA_OUT_CONF0_CH2_REG register + * Configure 0 register of Tx channel 2 + */ +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S) +#define GDMA_OUT_RST_CH2_V 0x00000001U +#define GDMA_OUT_RST_CH2_S 0 +/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S) +#define GDMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH2 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH2_M (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S) +#define GDMA_OUT_ETM_EN_CH2_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH2_S 6 + +/** GDMA_OUT_CONF1_CH2_REG register + * Configure 1 register of Tx channel 2 + */ +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +/** GDMA_OUTFIFO_STATUS_CH2_REG register + * Transmit FIFO status of Tx channel 2 + */ +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH2_M (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S) +#define GDMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH2_S 0 +/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH2_M (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S) +#define GDMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH2_S 1 +/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ +#define GDMA_OUTFIFO_CNT_CH2 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_M (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S) +#define GDMA_OUTFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** GDMA_OUT_PUSH_CH2_REG register + * Push control register of Rx channel 2 + */ +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) +/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_M (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_S 0 +/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH2_S 9 + +/** GDMA_OUT_LINK_CH2_REG register + * Link descriptor configure and control register of Tx channel 2 + */ +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_M (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S) +#define GDMA_OUTLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_S 0 +/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S) +#define GDMA_OUTLINK_STOP_CH2_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH2_S 20 +/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S) +#define GDMA_OUTLINK_START_CH2_V 0x00000001U +#define GDMA_OUTLINK_START_CH2_S 21 +/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S) +#define GDMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S) +#define GDMA_OUTLINK_PARK_CH2_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH2_S 23 + +/** GDMA_OUT_STATE_CH2_REG register + * Transmit status of Tx channel 2 + */ +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_M (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH2 0x00000007U +#define GDMA_OUT_STATE_CH2_M (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S) +#define GDMA_OUT_STATE_CH2_V 0x00000007U +#define GDMA_OUT_STATE_CH2_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register + * Outlink descriptor address when EOF occurs of Tx channel 2 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_M (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 2 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_DSCR_CH2_REG register + * Current inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_M (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +/** GDMA_OUT_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_M (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_M (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_OUT_PRI_CH2_REG register + * Priority register of Tx channel 2 + */ +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) +/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH2 0x0000000FU +#define GDMA_TX_PRI_CH2_M (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S) +#define GDMA_TX_PRI_CH2_V 0x0000000FU +#define GDMA_TX_PRI_CH2_S 0 + +/** GDMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection of Tx channel 2 + */ +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_M (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S) +#define GDMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +/** GDMA_BT_TX_SEL_REG register + * Bit scrambler selection + */ +#define GDMA_BT_TX_SEL_REG (DR_REG_GDMA_BASE + 0x284) +/** GDMA_BT_TX_SEL_CH0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch tx channel 0 across bit scrambler module + */ +#define GDMA_BT_TX_SEL_CH0 (BIT(0)) +#define GDMA_BT_TX_SEL_CH0_M (GDMA_BT_TX_SEL_CH0_V << GDMA_BT_TX_SEL_CH0_S) +#define GDMA_BT_TX_SEL_CH0_V 0x00000001U +#define GDMA_BT_TX_SEL_CH0_S 0 +/** GDMA_BT_TX_SEL_CH1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch tx channel 1 across bit scrambler module + */ +#define GDMA_BT_TX_SEL_CH1 (BIT(1)) +#define GDMA_BT_TX_SEL_CH1_M (GDMA_BT_TX_SEL_CH1_V << GDMA_BT_TX_SEL_CH1_S) +#define GDMA_BT_TX_SEL_CH1_V 0x00000001U +#define GDMA_BT_TX_SEL_CH1_S 1 +/** GDMA_BT_TX_SEL_CH2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch tx channel 2 across bit scrambler module + */ +#define GDMA_BT_TX_SEL_CH2 (BIT(2)) +#define GDMA_BT_TX_SEL_CH2_M (GDMA_BT_TX_SEL_CH2_V << GDMA_BT_TX_SEL_CH2_S) +#define GDMA_BT_TX_SEL_CH2_V 0x00000001U +#define GDMA_BT_TX_SEL_CH2_S 2 + +/** GDMA_BT_RX_SEL_REG register + * Bit scrambler selection + */ +#define GDMA_BT_RX_SEL_REG (DR_REG_GDMA_BASE + 0x288) +/** GDMA_BT_RX_SEL_CH0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch rx channel 0 across bit scrambler module + */ +#define GDMA_BT_RX_SEL_CH0 (BIT(0)) +#define GDMA_BT_RX_SEL_CH0_M (GDMA_BT_RX_SEL_CH0_V << GDMA_BT_RX_SEL_CH0_S) +#define GDMA_BT_RX_SEL_CH0_V 0x00000001U +#define GDMA_BT_RX_SEL_CH0_S 0 +/** GDMA_BT_RX_SEL_CH1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch rx channel 1 across bit scrambler module + */ +#define GDMA_BT_RX_SEL_CH1 (BIT(1)) +#define GDMA_BT_RX_SEL_CH1_M (GDMA_BT_RX_SEL_CH1_V << GDMA_BT_RX_SEL_CH1_S) +#define GDMA_BT_RX_SEL_CH1_V 0x00000001U +#define GDMA_BT_RX_SEL_CH1_S 1 +/** GDMA_BT_RX_SEL_CH2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch rx channel 2 across bit scrambler module + */ +#define GDMA_BT_RX_SEL_CH2 (BIT(2)) +#define GDMA_BT_RX_SEL_CH2_M (GDMA_BT_RX_SEL_CH2_V << GDMA_BT_RX_SEL_CH2_S) +#define GDMA_BT_RX_SEL_CH2_V 0x00000001U +#define GDMA_BT_RX_SEL_CH2_S 2 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gdma_struct.h b/components/soc/esp32c5/include/soc/gdma_struct.h new file mode 100644 index 00000000000..429106c9e06 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gdma_struct.h @@ -0,0 +1,2167 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers in */ +/** Type of in_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ + uint32_t in_done_chn_int_raw:1; + /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ + uint32_t in_suc_eof_chn_int_raw:1; + /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ + uint32_t in_err_eof_chn_int_raw:1; + /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ + uint32_t in_dscr_err_chn_int_raw:1; + /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ + uint32_t in_dscr_empty_chn_int_raw:1; + /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ + uint32_t infifo_ovf_chn_int_raw:1; + /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ + uint32_t infifo_udf_chn_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_st:1; + /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_st:1; + /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_st:1; + /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_st:1; + /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_st:1; + /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_st:1; + /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_ena:1; + /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_ena:1; + /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_ena:1; + /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_ena:1; + /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_ena:1; + /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_ena:1; + /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_clr:1; + /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_clr:1; + /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_clr:1; + /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_clr:1; + /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_clr:1; + /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_clr:1; + /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + + +/** Group: Interrupt Registers out */ +/** Type of out_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ + uint32_t out_done_chn_int_raw:1; + /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ + uint32_t out_eof_chn_int_raw:1; + /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ + uint32_t out_dscr_err_chn_int_raw:1; + /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ + uint32_t out_total_eof_chn_int_raw:1; + /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ + uint32_t outfifo_ovf_chn_int_raw:1; + /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ + uint32_t outfifo_udf_chn_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_st:1; + /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_st:1; + /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_st:1; + /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_st:1; + /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_st:1; + /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_ena:1; + /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_ena:1; + /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_ena:1; + /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_ena:1; + /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_ena:1; + /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_clr:1; + /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_clr:1; + /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_clr:1; + /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_clr:1; + /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_clr:1; + /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * MISC register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36720912; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Configuration Registers0 */ +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 0 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 0 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 0 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 0 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_pri_chn register + * Priority register of Rx channel 0 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 0 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_ch0 register + * Configure 0 register of Tx channel 0 + */ +typedef union { + struct { + /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_ch0:1; + /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch0:1; + /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_ch0:1; + /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_ch0:1; + /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_ch0:1; + /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_ch0:1; + /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ + uint32_t out_etm_en_ch0:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_ch0_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 0 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 0 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 0 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 0. + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 0 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +/** Group: Configuration Registers1 */ +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 1 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 1 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 1 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 1 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 1 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 1 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 1 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_pri_chn register + * Priority register of Rx channel 1 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 1 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel 1 + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm + * task. + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 1 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 1 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 1 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 1 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 1 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 1 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 1 + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 1 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +/** Group: Configuration Registers2 */ +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 2 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 2 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 2 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 2 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 2 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 2 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 2 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_pri_chn register + * Priority register of Rx channel 2 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 2 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel 2 + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm + * task. + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 2 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 2 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 2 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 2 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 2 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 2 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 2 + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 2 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of bt_tx_sel register + * Bit scrambler selection + */ +typedef union { + struct { + /** bt_tx_sel_ch0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch tx channel 0 across bit scrambler module + */ + uint32_t bt_tx_sel_ch0:1; + /** bt_tx_sel_ch1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch tx channel 1 across bit scrambler module + */ + uint32_t bt_tx_sel_ch1:1; + /** bt_tx_sel_ch2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch tx channel 2 across bit scrambler module + */ + uint32_t bt_tx_sel_ch2:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gdma_bt_tx_sel_reg_t; + +/** Type of bt_rx_sel register + * Bit scrambler selection + */ +typedef union { + struct { + /** bt_rx_sel_ch0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch rx channel 0 across bit scrambler module + */ + uint32_t bt_rx_sel_ch0:1; + /** bt_rx_sel_ch1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch rx channel 1 across bit scrambler module + */ + uint32_t bt_rx_sel_ch1:1; + /** bt_rx_sel_ch2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch rx channel 2 across bit scrambler module + */ + uint32_t bt_rx_sel_ch2:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gdma_bt_rx_sel_reg_t; + + +typedef struct gdma_dev_t { + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch2; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch2; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; + volatile gdma_in_pop_chn_reg_t in_pop_ch0; + volatile gdma_in_link_chn_reg_t in_link_ch0; + volatile gdma_in_state_chn_reg_t in_state_ch0; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; + volatile gdma_in_pri_chn_reg_t in_pri_ch0; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; + uint32_t reserved_0a4[11]; + volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; + volatile gdma_out_push_chn_reg_t out_push_ch0; + volatile gdma_out_link_chn_reg_t out_link_ch0; + volatile gdma_out_state_chn_reg_t out_state_ch0; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; + volatile gdma_out_pri_chn_reg_t out_pri_ch0; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; + uint32_t reserved_104[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; + volatile gdma_in_pop_chn_reg_t in_pop_ch1; + volatile gdma_in_link_chn_reg_t in_link_ch1; + volatile gdma_in_state_chn_reg_t in_state_ch1; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; + volatile gdma_in_pri_chn_reg_t in_pri_ch1; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; + uint32_t reserved_164[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; + volatile gdma_out_push_chn_reg_t out_push_ch1; + volatile gdma_out_link_chn_reg_t out_link_ch1; + volatile gdma_out_state_chn_reg_t out_state_ch1; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; + volatile gdma_out_pri_chn_reg_t out_pri_ch1; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; + uint32_t reserved_1c4[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch2; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch2; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch2; + volatile gdma_in_pop_chn_reg_t in_pop_ch2; + volatile gdma_in_link_chn_reg_t in_link_ch2; + volatile gdma_in_state_chn_reg_t in_state_ch2; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch2; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; + volatile gdma_in_pri_chn_reg_t in_pri_ch2; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2; + uint32_t reserved_224[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch2; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch2; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2; + volatile gdma_out_push_chn_reg_t out_push_ch2; + volatile gdma_out_link_chn_reg_t out_link_ch2; + volatile gdma_out_state_chn_reg_t out_state_ch2; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch2; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; + volatile gdma_out_pri_chn_reg_t out_pri_ch2; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2; + volatile gdma_bt_tx_sel_reg_t bt_tx_sel; + volatile gdma_bt_rx_sel_reg_t bt_rx_sel; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x28c, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_ext_reg.h b/components/soc/esp32c5/include/soc/gpio_ext_reg.h new file mode 100644 index 00000000000..0f28c353157 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_ext_reg.h @@ -0,0 +1,1102 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_EXT_SIGMADELTA0_REG register + * Duty Cycle Configure Register of SDM0 + */ +#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) +/** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD0_IN 0x000000FFU +#define GPIO_EXT_SD0_IN_M (GPIO_EXT_SD0_IN_V << GPIO_EXT_SD0_IN_S) +#define GPIO_EXT_SD0_IN_V 0x000000FFU +#define GPIO_EXT_SD0_IN_S 0 +/** GPIO_EXT_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD0_PRESCALE 0x000000FFU +#define GPIO_EXT_SD0_PRESCALE_M (GPIO_EXT_SD0_PRESCALE_V << GPIO_EXT_SD0_PRESCALE_S) +#define GPIO_EXT_SD0_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD0_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA1_REG register + * Duty Cycle Configure Register of SDM1 + */ +#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) +/** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD1_IN 0x000000FFU +#define GPIO_EXT_SD1_IN_M (GPIO_EXT_SD1_IN_V << GPIO_EXT_SD1_IN_S) +#define GPIO_EXT_SD1_IN_V 0x000000FFU +#define GPIO_EXT_SD1_IN_S 0 +/** GPIO_EXT_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD1_PRESCALE 0x000000FFU +#define GPIO_EXT_SD1_PRESCALE_M (GPIO_EXT_SD1_PRESCALE_V << GPIO_EXT_SD1_PRESCALE_S) +#define GPIO_EXT_SD1_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD1_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA2_REG register + * Duty Cycle Configure Register of SDM2 + */ +#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) +/** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD2_IN 0x000000FFU +#define GPIO_EXT_SD2_IN_M (GPIO_EXT_SD2_IN_V << GPIO_EXT_SD2_IN_S) +#define GPIO_EXT_SD2_IN_V 0x000000FFU +#define GPIO_EXT_SD2_IN_S 0 +/** GPIO_EXT_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD2_PRESCALE 0x000000FFU +#define GPIO_EXT_SD2_PRESCALE_M (GPIO_EXT_SD2_PRESCALE_V << GPIO_EXT_SD2_PRESCALE_S) +#define GPIO_EXT_SD2_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD2_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA3_REG register + * Duty Cycle Configure Register of SDM3 + */ +#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) +/** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD3_IN 0x000000FFU +#define GPIO_EXT_SD3_IN_M (GPIO_EXT_SD3_IN_V << GPIO_EXT_SD3_IN_S) +#define GPIO_EXT_SD3_IN_V 0x000000FFU +#define GPIO_EXT_SD3_IN_S 0 +/** GPIO_EXT_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD3_PRESCALE 0x000000FFU +#define GPIO_EXT_SD3_PRESCALE_M (GPIO_EXT_SD3_PRESCALE_V << GPIO_EXT_SD3_PRESCALE_S) +#define GPIO_EXT_SD3_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD3_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA_MISC_REG register + * MISC Register + */ +#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) +/** GPIO_EXT_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ +#define GPIO_EXT_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_EXT_FUNCTION_CLK_EN_M (GPIO_EXT_FUNCTION_CLK_EN_V << GPIO_EXT_FUNCTION_CLK_EN_S) +#define GPIO_EXT_FUNCTION_CLK_EN_V 0x00000001U +#define GPIO_EXT_FUNCTION_CLK_EN_S 30 +/** GPIO_EXT_SPI_SWAP : R/W; bitpos: [31]; default: 0; + * Reserved. + */ +#define GPIO_EXT_SPI_SWAP (BIT(31)) +#define GPIO_EXT_SPI_SWAP_M (GPIO_EXT_SPI_SWAP_V << GPIO_EXT_SPI_SWAP_S) +#define GPIO_EXT_SPI_SWAP_V 0x00000001U +#define GPIO_EXT_SPI_SWAP_S 31 + +/** GPIO_EXT_PAD_COMP_CONFIG_REG register + * PAD Compare configure Register + */ +#define GPIO_EXT_PAD_COMP_CONFIG_REG (DR_REG_GPIO_EXT_BASE + 0x28) +/** GPIO_EXT_XPD_COMP : R/W; bitpos: [0]; default: 0; + * Pad compare enable bit. + */ +#define GPIO_EXT_XPD_COMP (BIT(0)) +#define GPIO_EXT_XPD_COMP_M (GPIO_EXT_XPD_COMP_V << GPIO_EXT_XPD_COMP_S) +#define GPIO_EXT_XPD_COMP_V 0x00000001U +#define GPIO_EXT_XPD_COMP_S 0 +/** GPIO_EXT_MODE_COMP : R/W; bitpos: [1]; default: 0; + * 1 to enable external reference from PAD[0]. 0 to enable internal reference, + * meanwhile PAD[0] can be used as a regular GPIO. + */ +#define GPIO_EXT_MODE_COMP (BIT(1)) +#define GPIO_EXT_MODE_COMP_M (GPIO_EXT_MODE_COMP_V << GPIO_EXT_MODE_COMP_S) +#define GPIO_EXT_MODE_COMP_V 0x00000001U +#define GPIO_EXT_MODE_COMP_S 1 +/** GPIO_EXT_DREF_COMP : R/W; bitpos: [4:2]; default: 0; + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + */ +#define GPIO_EXT_DREF_COMP 0x00000007U +#define GPIO_EXT_DREF_COMP_M (GPIO_EXT_DREF_COMP_V << GPIO_EXT_DREF_COMP_S) +#define GPIO_EXT_DREF_COMP_V 0x00000007U +#define GPIO_EXT_DREF_COMP_S 2 +/** GPIO_EXT_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0; + * Zero Detect mode select. + */ +#define GPIO_EXT_ZERO_DET_MODE 0x00000003U +#define GPIO_EXT_ZERO_DET_MODE_M (GPIO_EXT_ZERO_DET_MODE_V << GPIO_EXT_ZERO_DET_MODE_S) +#define GPIO_EXT_ZERO_DET_MODE_V 0x00000003U +#define GPIO_EXT_ZERO_DET_MODE_S 5 + +/** GPIO_EXT_PAD_COMP_FILTER_REG register + * Zero Detect filter Register + */ +#define GPIO_EXT_PAD_COMP_FILTER_REG (DR_REG_GPIO_EXT_BASE + 0x2c) +/** GPIO_EXT_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0; + * Zero Detect filter cycle length + */ +#define GPIO_EXT_ZERO_DET_FILTER_CNT 0xFFFFFFFFU +#define GPIO_EXT_ZERO_DET_FILTER_CNT_M (GPIO_EXT_ZERO_DET_FILTER_CNT_V << GPIO_EXT_ZERO_DET_FILTER_CNT_S) +#define GPIO_EXT_ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU +#define GPIO_EXT_ZERO_DET_FILTER_CNT_S 0 + +/** GPIO_EXT_GLITCH_FILTER_CH0_REG register + * Glitch Filter Configure Register of Channel0 + */ +#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH1_REG register + * Glitch Filter Configure Register of Channel1 + */ +#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH2_REG register + * Glitch Filter Configure Register of Channel2 + */ +#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH3_REG register + * Glitch Filter Configure Register of Channel3 + */ +#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH4_REG register + * Glitch Filter Configure Register of Channel4 + */ +#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH5_REG register + * Glitch Filter Configure Register of Channel5 + */ +#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH6_REG register + * Glitch Filter Configure Register of Channel6 + */ +#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH7_REG register + * Glitch Filter Configure Register of Channel7 + */ +#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register + * Etm Config register of Channel0 + */ +#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register + * Etm Config register of Channel1 + */ +#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register + * Etm Config register of Channel2 + */ +#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register + * Etm Config register of Channel3 + */ +#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register + * Etm Config register of Channel4 + */ +#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register + * Etm Config register of Channel5 + */ +#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register + * Etm Config register of Channel6 + */ +#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register + * Etm Config register of Channel7 + */ +#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_TASK_P0_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) +/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO0_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO1_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO2_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO3_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P1_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) +/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO4_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO5_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO6_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO7_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P2_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) +/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO8_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO9_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO10_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO11_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P3_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) +/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO12_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO13_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO14_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO15_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P4_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) +/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO16_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO17_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO18_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO19_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P5_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) +/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO20_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO21_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO22_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO23_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P6_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) +/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO24_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_M (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO25_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_M (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO26_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S 17 + +/** GPIO_EXT_INT_RAW_REG register + * GPIOSD interrupt raw register + */ +#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0xe0) +/** GPIO_EXT_COMP0_NEG_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt raw + */ +#define GPIO_EXT_COMP0_NEG_INT_RAW (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_RAW_M (GPIO_EXT_COMP0_NEG_INT_RAW_V << GPIO_EXT_COMP0_NEG_INT_RAW_S) +#define GPIO_EXT_COMP0_NEG_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_RAW_S 0 +/** GPIO_EXT_COMP0_POS_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt raw + */ +#define GPIO_EXT_COMP0_POS_INT_RAW (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_RAW_M (GPIO_EXT_COMP0_POS_INT_RAW_V << GPIO_EXT_COMP0_POS_INT_RAW_S) +#define GPIO_EXT_COMP0_POS_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_RAW_S 1 +/** GPIO_EXT_COMP0_ALL_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt raw + */ +#define GPIO_EXT_COMP0_ALL_INT_RAW (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_RAW_M (GPIO_EXT_COMP0_ALL_INT_RAW_V << GPIO_EXT_COMP0_ALL_INT_RAW_S) +#define GPIO_EXT_COMP0_ALL_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_RAW_S 2 + +/** GPIO_EXT_INT_ST_REG register + * GPIOSD interrupt masked register + */ +#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0xe4) +/** GPIO_EXT_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt status + */ +#define GPIO_EXT_COMP0_NEG_INT_ST (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_ST_M (GPIO_EXT_COMP0_NEG_INT_ST_V << GPIO_EXT_COMP0_NEG_INT_ST_S) +#define GPIO_EXT_COMP0_NEG_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_ST_S 0 +/** GPIO_EXT_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt status + */ +#define GPIO_EXT_COMP0_POS_INT_ST (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_ST_M (GPIO_EXT_COMP0_POS_INT_ST_V << GPIO_EXT_COMP0_POS_INT_ST_S) +#define GPIO_EXT_COMP0_POS_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_ST_S 1 +/** GPIO_EXT_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt status + */ +#define GPIO_EXT_COMP0_ALL_INT_ST (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_ST_M (GPIO_EXT_COMP0_ALL_INT_ST_V << GPIO_EXT_COMP0_ALL_INT_ST_S) +#define GPIO_EXT_COMP0_ALL_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_ST_S 2 + +/** GPIO_EXT_INT_ENA_REG register + * GPIOSD interrupt enable register + */ +#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0xe8) +/** GPIO_EXT_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1; + * analog comparator pos edge interrupt enable + */ +#define GPIO_EXT_COMP0_NEG_INT_ENA (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_ENA_M (GPIO_EXT_COMP0_NEG_INT_ENA_V << GPIO_EXT_COMP0_NEG_INT_ENA_S) +#define GPIO_EXT_COMP0_NEG_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_ENA_S 0 +/** GPIO_EXT_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1; + * analog comparator neg edge interrupt enable + */ +#define GPIO_EXT_COMP0_POS_INT_ENA (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_ENA_M (GPIO_EXT_COMP0_POS_INT_ENA_V << GPIO_EXT_COMP0_POS_INT_ENA_S) +#define GPIO_EXT_COMP0_POS_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_ENA_S 1 +/** GPIO_EXT_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1; + * analog comparator neg or pos edge interrupt enable + */ +#define GPIO_EXT_COMP0_ALL_INT_ENA (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_ENA_M (GPIO_EXT_COMP0_ALL_INT_ENA_V << GPIO_EXT_COMP0_ALL_INT_ENA_S) +#define GPIO_EXT_COMP0_ALL_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_ENA_S 2 + +/** GPIO_EXT_INT_CLR_REG register + * GPIOSD interrupt clear register + */ +#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0xec) +/** GPIO_EXT_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt clear + */ +#define GPIO_EXT_COMP0_NEG_INT_CLR (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_CLR_M (GPIO_EXT_COMP0_NEG_INT_CLR_V << GPIO_EXT_COMP0_NEG_INT_CLR_S) +#define GPIO_EXT_COMP0_NEG_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_CLR_S 0 +/** GPIO_EXT_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt clear + */ +#define GPIO_EXT_COMP0_POS_INT_CLR (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_CLR_M (GPIO_EXT_COMP0_POS_INT_CLR_V << GPIO_EXT_COMP0_POS_INT_CLR_S) +#define GPIO_EXT_COMP0_POS_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_CLR_S 1 +/** GPIO_EXT_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt clear + */ +#define GPIO_EXT_COMP0_ALL_INT_CLR (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_CLR_M (GPIO_EXT_COMP0_ALL_INT_CLR_V << GPIO_EXT_COMP0_ALL_INT_CLR_S) +#define GPIO_EXT_COMP0_ALL_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_CLR_S 2 + +/** GPIO_EXT_VERSION_REG register + * Version Control Register + */ +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) +/** GPIO_EXT_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 36704513; + * Version control register. + */ +#define GPIO_EXT_GPIO_SD_DATE 0x0FFFFFFFU +#define GPIO_EXT_GPIO_SD_DATE_M (GPIO_EXT_GPIO_SD_DATE_V << GPIO_EXT_GPIO_SD_DATE_S) +#define GPIO_EXT_GPIO_SD_DATE_V 0x0FFFFFFFU +#define GPIO_EXT_GPIO_SD_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/include/soc/gpio_ext_struct.h new file mode 100644 index 00000000000..f4a65cb89c4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_ext_struct.h @@ -0,0 +1,340 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SDM Configure Registers */ +/** Type of sigmadeltan register + * Duty Cycle Configure Register of SDMn + */ +typedef union { + struct { + /** sdn_in : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ + uint32_t sdn_in:8; + /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ + uint32_t sdn_prescale:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_ext_sigmadeltan_reg_t; + +/** Type of sigmadelta_misc register + * MISC Register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** function_clk_en : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ + uint32_t function_clk_en:1; + /** spi_swap : R/W; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t spi_swap:1; + }; + uint32_t val; +} gpio_ext_sigmadelta_misc_reg_t; + + +/** Group: Configure Registers */ +/** Type of pad_comp_config register + * PAD Compare configure Register + */ +typedef union { + struct { + /** xpd_comp : R/W; bitpos: [0]; default: 0; + * Pad compare enable bit. + */ + uint32_t xpd_comp:1; + /** mode_comp : R/W; bitpos: [1]; default: 0; + * 1 to enable external reference from PAD[0]. 0 to enable internal reference, + * meanwhile PAD[0] can be used as a regular GPIO. + */ + uint32_t mode_comp:1; + /** dref_comp : R/W; bitpos: [4:2]; default: 0; + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + */ + uint32_t dref_comp:3; + /** zero_det_mode : R/W; bitpos: [6:5]; default: 0; + * Zero Detect mode select. + */ + uint32_t zero_det_mode:2; + uint32_t reserved_7:25; + }; + uint32_t val; +} gpio_ext_pad_comp_config_reg_t; + +/** Type of pad_comp_filter register + * Zero Detect filter Register + */ +typedef union { + struct { + /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0; + * Zero Detect filter cycle length + */ + uint32_t zero_det_filter_cnt:32; + }; + uint32_t val; +} gpio_ext_pad_comp_filter_reg_t; + + +/** Group: Glitch filter Configure Registers */ +/** Type of glitch_filter_chn register + * Glitch Filter Configure Register of Channeln + */ +typedef union { + struct { + /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ + uint32_t filter_ch0_en:1; + /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ + uint32_t filter_ch0_input_io_num:6; + /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ + uint32_t filter_ch0_window_thres:6; + /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ + uint32_t filter_ch0_window_width:6; + uint32_t reserved_19:13; + }; + uint32_t val; +} gpio_ext_glitch_filter_chn_reg_t; + + +/** Group: Etm Configure Registers */ +/** Type of etm_event_chn_cfg register + * Etm Config register of Channeln + */ +typedef union { + struct { + /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ + uint32_t etm_ch0_event_sel:5; + uint32_t reserved_5:2; + /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ + uint32_t etm_ch0_event_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_ext_etm_event_chn_cfg_reg_t; + +/** Type of etm_task_pn_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio0_en:1; + /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio0_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio1_en:1; + /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio1_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio2_en:1; + /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio2_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio3_en:1; + /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio3_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_etm_task_pn_cfg_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * GPIOSD interrupt raw register + */ +typedef union { + struct { + /** comp0_neg_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt raw + */ + uint32_t comp0_neg_int_raw:1; + /** comp0_pos_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt raw + */ + uint32_t comp0_pos_int_raw:1; + /** comp0_all_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt raw + */ + uint32_t comp0_all_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_raw_reg_t; + +/** Type of int_st register + * GPIOSD interrupt masked register + */ +typedef union { + struct { + /** comp0_neg_int_st : RO; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt status + */ + uint32_t comp0_neg_int_st:1; + /** comp0_pos_int_st : RO; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt status + */ + uint32_t comp0_pos_int_st:1; + /** comp0_all_int_st : RO; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt status + */ + uint32_t comp0_all_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_st_reg_t; + +/** Type of int_ena register + * GPIOSD interrupt enable register + */ +typedef union { + struct { + /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1; + * analog comparator pos edge interrupt enable + */ + uint32_t comp0_neg_int_ena:1; + /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1; + * analog comparator neg edge interrupt enable + */ + uint32_t comp0_pos_int_ena:1; + /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1; + * analog comparator neg or pos edge interrupt enable + */ + uint32_t comp0_all_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_ena_reg_t; + +/** Type of int_clr register + * GPIOSD interrupt clear register + */ +typedef union { + struct { + /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt clear + */ + uint32_t comp0_neg_int_clr:1; + /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt clear + */ + uint32_t comp0_pos_int_clr:1; + /** comp0_all_int_clr : WT; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt clear + */ + uint32_t comp0_all_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version Control Register + */ +typedef union { + struct { + /** gpio_sd_date : R/W; bitpos: [27:0]; default: 36704513; + * Version control register. + */ + uint32_t gpio_sd_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_version_reg_t; + + +typedef struct gpio_sd_dev_t { + volatile gpio_ext_sigmadeltan_reg_t channel[4]; + uint32_t reserved_010[5]; + volatile gpio_ext_sigmadelta_misc_reg_t misc; +} gpio_sd_dev_t; + +typedef struct gpio_ana_cmpr_dev_t { + volatile gpio_ext_pad_comp_config_reg_t pad_comp_config; + volatile gpio_ext_pad_comp_filter_reg_t pad_comp_filter; +} gpio_ana_cmpr_dev_t; + +typedef struct { + volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + +typedef struct gpio_etm_dev_t { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7]; +} gpio_etm_dev_t; + +typedef struct gpio_ext_dev_t { + volatile gpio_sd_dev_t sigma_delta; + volatile gpio_ana_cmpr_dev_t ana_cmpr; + volatile gpio_glitch_filter_dev_t glitch_filter; + uint32_t reserved_050[4]; + volatile gpio_etm_dev_t etm; + uint32_t reserved_0bc[9]; + volatile gpio_ext_int_raw_reg_t int_raw; + volatile gpio_ext_int_st_reg_t int_st; + volatile gpio_ext_int_ena_reg_t int_ena; + volatile gpio_ext_int_clr_reg_t int_clr; + uint32_t reserved_0f0[3]; + volatile gpio_ext_version_reg_t version; +} gpio_ext_dev_t; + +extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_pins.h b/components/soc/esp32c5/include/soc/gpio_pins.h new file mode 100644 index 00000000000..b6d59de94cf --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_pins.h @@ -0,0 +1,20 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5] IDF-8717 (inherit from C6) +#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_reg.h b/components/soc/esp32c5/include/soc/gpio_reg.h new file mode 100644 index 00000000000..d0765dd0402 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_reg.h @@ -0,0 +1,5727 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_BT_SELECT_REG register + * GPIO bit select register + */ +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ +#define GPIO_BT_SEL 0xFFFFFFFFU +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFFU +#define GPIO_BT_SEL_S 0 + +/** GPIO_OUT_REG register + * GPIO output register for GPIO0-30 + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [30:0]; default: 0; + * GPIO output register for GPIO0-30 + */ +#define GPIO_OUT_DATA_ORIG 0x7FFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0x7FFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 + +/** GPIO_OUT_W1TS_REG register + * GPIO output set register for GPIO0-30 + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [30:0]; default: 0; + * GPIO output set register for GPIO0-30 + */ +#define GPIO_OUT_W1TS 0x7FFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0x7FFFFFFFU +#define GPIO_OUT_W1TS_S 0 + +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register for GPIO0-30 + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [30:0]; default: 0; + * GPIO output clear register for GPIO0-30 + */ +#define GPIO_OUT_W1TC 0x7FFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0x7FFFFFFFU +#define GPIO_OUT_W1TC_S 0 + +/** GPIO_SDIO_SELECT_REG register + * GPIO sdio select register + */ +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) +/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ +#define GPIO_SDIO_SEL 0x000000FFU +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FFU +#define GPIO_SDIO_SEL_S 0 + +/** GPIO_ENABLE_REG register + * GPIO output enable register for GPIO0-30 + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO output enable register for GPIO0-30 + */ +#define GPIO_ENABLE_DATA 0x7FFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0x7FFFFFFFU +#define GPIO_ENABLE_DATA_S 0 + +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/** GPIO_ENABLE_W1TS : WT; bitpos: [30:0]; default: 0; + * GPIO output enable set register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TS 0x7FFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0x7FFFFFFFU +#define GPIO_ENABLE_W1TS_S 0 + +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/** GPIO_ENABLE_W1TC : WT; bitpos: [30:0]; default: 0; + * GPIO output enable clear register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TC 0x7FFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0x7FFFFFFFU +#define GPIO_ENABLE_W1TC_S 0 + +/** GPIO_STRAP_REG register + * pad strapping register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU +#define GPIO_STRAPPING_S 0 + +/** GPIO_IN_REG register + * GPIO input register for GPIO0-30 + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [30:0]; default: 0; + * GPIO input register for GPIO0-30 + */ +#define GPIO_IN_DATA_NEXT 0x7FFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0x7FFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 + +/** GPIO_STATUS_REG register + * GPIO interrupt status register for GPIO0-30 + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO interrupt status register for GPIO0-30 + */ +#define GPIO_STATUS_INTERRUPT 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 + +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register for GPIO0-30 + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_STATUS_W1TS : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status set register for GPIO0-30 + */ +#define GPIO_STATUS_W1TS 0x7FFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0x7FFFFFFFU +#define GPIO_STATUS_W1TS_S 0 + +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register for GPIO0-30 + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) +/** GPIO_STATUS_W1TC : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-30 + */ +#define GPIO_STATUS_W1TC 0x7FFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0x7FFFFFFFU +#define GPIO_STATUS_W1TC_S 0 + +/** GPIO_PCPU_INT_REG register + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) +/** GPIO_PROCPU_INT : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ +#define GPIO_PROCPU_INT 0x7FFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0x7FFFFFFFU +#define GPIO_PROCPU_INT_S 0 + +/** GPIO_PCPU_NMI_INT_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/** GPIO_PROCPU_NMI_INT : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ +#define GPIO_PROCPU_NMI_INT 0x7FFFFFFFU +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0x7FFFFFFFU +#define GPIO_PROCPU_NMI_INT_S 0 + +/** GPIO_CPUSDIO_INT_REG register + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_SDIO_INT : RO; bitpos: [30:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ +#define GPIO_SDIO_INT 0x7FFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0x7FFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN0_CONFIG 0x00000003U +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003U +#define GPIO_PIN0_CONFIG_S 11 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 + +/** GPIO_PIN1_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN1_CONFIG 0x00000003U +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003U +#define GPIO_PIN1_CONFIG_S 11 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 + +/** GPIO_PIN2_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN2_CONFIG 0x00000003U +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003U +#define GPIO_PIN2_CONFIG_S 11 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 + +/** GPIO_PIN3_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN3_CONFIG 0x00000003U +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003U +#define GPIO_PIN3_CONFIG_S 11 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 + +/** GPIO_PIN4_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN4_CONFIG 0x00000003U +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003U +#define GPIO_PIN4_CONFIG_S 11 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 + +/** GPIO_PIN5_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN5_CONFIG 0x00000003U +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003U +#define GPIO_PIN5_CONFIG_S 11 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 + +/** GPIO_PIN6_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN6_CONFIG 0x00000003U +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003U +#define GPIO_PIN6_CONFIG_S 11 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 + +/** GPIO_PIN7_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN7_CONFIG 0x00000003U +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003U +#define GPIO_PIN7_CONFIG_S 11 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 + +/** GPIO_PIN8_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN8_CONFIG 0x00000003U +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003U +#define GPIO_PIN8_CONFIG_S 11 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 + +/** GPIO_PIN9_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN9_CONFIG 0x00000003U +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003U +#define GPIO_PIN9_CONFIG_S 11 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 + +/** GPIO_PIN10_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN10_CONFIG 0x00000003U +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003U +#define GPIO_PIN10_CONFIG_S 11 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 + +/** GPIO_PIN11_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN11_CONFIG 0x00000003U +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003U +#define GPIO_PIN11_CONFIG_S 11 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 + +/** GPIO_PIN12_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN12_CONFIG 0x00000003U +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003U +#define GPIO_PIN12_CONFIG_S 11 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 + +/** GPIO_PIN13_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN13_CONFIG 0x00000003U +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003U +#define GPIO_PIN13_CONFIG_S 11 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 + +/** GPIO_PIN14_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN14_CONFIG 0x00000003U +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003U +#define GPIO_PIN14_CONFIG_S 11 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 + +/** GPIO_PIN15_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN15_CONFIG 0x00000003U +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003U +#define GPIO_PIN15_CONFIG_S 11 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 + +/** GPIO_PIN16_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN16_CONFIG 0x00000003U +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003U +#define GPIO_PIN16_CONFIG_S 11 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 + +/** GPIO_PIN17_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN17_CONFIG 0x00000003U +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003U +#define GPIO_PIN17_CONFIG_S 11 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 + +/** GPIO_PIN18_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN18_CONFIG 0x00000003U +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003U +#define GPIO_PIN18_CONFIG_S 11 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 + +/** GPIO_PIN19_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN19_CONFIG 0x00000003U +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003U +#define GPIO_PIN19_CONFIG_S 11 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 + +/** GPIO_PIN20_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN20_CONFIG 0x00000003U +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003U +#define GPIO_PIN20_CONFIG_S 11 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 + +/** GPIO_PIN21_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN21_CONFIG 0x00000003U +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003U +#define GPIO_PIN21_CONFIG_S 11 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 + +/** GPIO_PIN22_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN22_CONFIG 0x00000003U +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003U +#define GPIO_PIN22_CONFIG_S 11 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 + +/** GPIO_PIN23_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN23_CONFIG 0x00000003U +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003U +#define GPIO_PIN23_CONFIG_S 11 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 + +/** GPIO_PIN24_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN24_CONFIG 0x00000003U +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003U +#define GPIO_PIN24_CONFIG_S 11 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 + +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN25_CONFIG 0x00000003U +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003U +#define GPIO_PIN25_CONFIG_S 11 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN26_CONFIG 0x00000003U +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003U +#define GPIO_PIN26_CONFIG_S 11 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN27_CONFIG 0x00000003U +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003U +#define GPIO_PIN27_CONFIG_S 11 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN28_CONFIG 0x00000003U +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003U +#define GPIO_PIN28_CONFIG_S 11 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN29_CONFIG 0x00000003U +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003U +#define GPIO_PIN29_CONFIG_S 11 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 + +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN30_CONFIG 0x00000003U +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003U +#define GPIO_PIN30_CONFIG_S 11 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 + +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [30:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 7 + +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 7 + +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 7 + +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 7 + +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 7 + +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 7 + +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 7 + +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 7 + +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 7 + +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 7 + +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 7 + +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 7 + +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 7 + +/** GPIO_FUNC19_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) +/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC19_IN_SEL 0x0000003FU +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003FU +#define GPIO_FUNC19_IN_SEL_S 0 +/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001U +#define GPIO_SIG19_IN_SEL_S 7 + +/** GPIO_FUNC21_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) +/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC21_IN_SEL 0x0000003FU +#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) +#define GPIO_FUNC21_IN_SEL_V 0x0000003FU +#define GPIO_FUNC21_IN_SEL_S 0 +/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) +#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) +#define GPIO_SIG21_IN_SEL_V 0x00000001U +#define GPIO_SIG21_IN_SEL_S 7 + +/** GPIO_FUNC22_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) +/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC22_IN_SEL 0x0000003FU +#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) +#define GPIO_FUNC22_IN_SEL_V 0x0000003FU +#define GPIO_FUNC22_IN_SEL_S 0 +/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) +#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) +#define GPIO_SIG22_IN_SEL_V 0x00000001U +#define GPIO_SIG22_IN_SEL_S 7 + +/** GPIO_FUNC23_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) +/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC23_IN_SEL 0x0000003FU +#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) +#define GPIO_FUNC23_IN_SEL_V 0x0000003FU +#define GPIO_FUNC23_IN_SEL_S 0 +/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) +#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) +#define GPIO_SIG23_IN_SEL_V 0x00000001U +#define GPIO_SIG23_IN_SEL_S 7 + +/** GPIO_FUNC24_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) +/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC24_IN_SEL 0x0000003FU +#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) +#define GPIO_FUNC24_IN_SEL_V 0x0000003FU +#define GPIO_FUNC24_IN_SEL_S 0 +/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) +#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) +#define GPIO_SIG24_IN_SEL_V 0x00000001U +#define GPIO_SIG24_IN_SEL_S 7 + +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 7 + +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 7 + +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 7 + +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 7 + +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 7 + +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 7 + +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 7 + +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 7 + +/** GPIO_FUNC40_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) +/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC40_IN_SEL 0x0000003FU +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003FU +#define GPIO_FUNC40_IN_SEL_S 0 +/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001U +#define GPIO_SIG40_IN_SEL_S 7 + +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 7 + +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 7 + +/** GPIO_FUNC45_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC45_IN_SEL 0x0000003FU +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003FU +#define GPIO_FUNC45_IN_SEL_S 0 +/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001U +#define GPIO_SIG45_IN_SEL_S 7 + +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 7 + +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 7 + +/** GPIO_FUNC48_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC48_IN_SEL 0x0000003FU +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003FU +#define GPIO_FUNC48_IN_SEL_S 0 +/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001U +#define GPIO_SIG48_IN_SEL_S 7 + +/** GPIO_FUNC49_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC49_IN_SEL 0x0000003FU +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003FU +#define GPIO_FUNC49_IN_SEL_S 0 +/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001U +#define GPIO_SIG49_IN_SEL_S 7 + +/** GPIO_FUNC50_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) +/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC50_IN_SEL 0x0000003FU +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003FU +#define GPIO_FUNC50_IN_SEL_S 0 +/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001U +#define GPIO_SIG50_IN_SEL_S 7 + +/** GPIO_FUNC51_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC51_IN_SEL 0x0000003FU +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003FU +#define GPIO_FUNC51_IN_SEL_S 0 +/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001U +#define GPIO_SIG51_IN_SEL_S 7 + +/** GPIO_FUNC52_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC52_IN_SEL 0x0000003FU +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003FU +#define GPIO_FUNC52_IN_SEL_S 0 +/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001U +#define GPIO_SIG52_IN_SEL_S 7 + +/** GPIO_FUNC53_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC53_IN_SEL 0x0000003FU +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003FU +#define GPIO_FUNC53_IN_SEL_S 0 +/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001U +#define GPIO_SIG53_IN_SEL_S 7 + +/** GPIO_FUNC54_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) +/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC54_IN_SEL 0x0000003FU +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003FU +#define GPIO_FUNC54_IN_SEL_S 0 +/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001U +#define GPIO_SIG54_IN_SEL_S 7 + +/** GPIO_FUNC63_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC63_IN_SEL 0x0000003FU +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003FU +#define GPIO_FUNC63_IN_SEL_S 0 +/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001U +#define GPIO_SIG63_IN_SEL_S 7 + +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 7 + +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 7 + +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 7 + +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 7 + +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 7 + +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 7 + +/** GPIO_FUNC70_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) +/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC70_IN_SEL 0x0000003FU +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003FU +#define GPIO_FUNC70_IN_SEL_S 0 +/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001U +#define GPIO_SIG70_IN_SEL_S 7 + +/** GPIO_FUNC71_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC71_IN_SEL 0x0000003FU +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003FU +#define GPIO_FUNC71_IN_SEL_S 0 +/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001U +#define GPIO_SIG71_IN_SEL_S 7 + +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 7 + +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 7 + +/** GPIO_FUNC77_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC77_IN_SEL 0x0000003FU +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000003FU +#define GPIO_FUNC77_IN_SEL_S 0 +/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001U +#define GPIO_SIG77_IN_SEL_S 7 + +/** GPIO_FUNC81_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC81_IN_SEL 0x0000003FU +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003FU +#define GPIO_FUNC81_IN_SEL_S 0 +/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001U +#define GPIO_SIG81_IN_SEL_S 7 + +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 7 + +/** GPIO_FUNC83_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC83_IN_SEL 0x0000003FU +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000003FU +#define GPIO_FUNC83_IN_SEL_S 0 +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001U +#define GPIO_SIG83_IN_SEL_S 7 + +/** GPIO_FUNC84_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) +/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC84_IN_SEL 0x0000003FU +#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) +#define GPIO_FUNC84_IN_SEL_V 0x0000003FU +#define GPIO_FUNC84_IN_SEL_S 0 +/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) +#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/** GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) +#define GPIO_SIG84_IN_SEL_V 0x00000001U +#define GPIO_SIG84_IN_SEL_S 7 + +/** GPIO_FUNC85_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) +/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC85_IN_SEL 0x0000003FU +#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) +#define GPIO_FUNC85_IN_SEL_V 0x0000003FU +#define GPIO_FUNC85_IN_SEL_S 0 +/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) +#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/** GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) +#define GPIO_SIG85_IN_SEL_V 0x00000001U +#define GPIO_SIG85_IN_SEL_S 7 + +/** GPIO_FUNC86_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) +/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC86_IN_SEL 0x0000003FU +#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) +#define GPIO_FUNC86_IN_SEL_V 0x0000003FU +#define GPIO_FUNC86_IN_SEL_S 0 +/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) +#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) +#define GPIO_SIG86_IN_SEL_V 0x00000001U +#define GPIO_SIG86_IN_SEL_S 7 + +/** GPIO_FUNC87_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) +/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC87_IN_SEL 0x0000003FU +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003FU +#define GPIO_FUNC87_IN_SEL_S 0 +/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001U +#define GPIO_SIG87_IN_SEL_S 7 + +/** GPIO_FUNC88_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) +/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC88_IN_SEL 0x0000003FU +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003FU +#define GPIO_FUNC88_IN_SEL_S 0 +/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001U +#define GPIO_SIG88_IN_SEL_S 7 + +/** GPIO_FUNC89_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) +/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC89_IN_SEL 0x0000003FU +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003FU +#define GPIO_FUNC89_IN_SEL_S 0 +/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001U +#define GPIO_SIG89_IN_SEL_S 7 + +/** GPIO_FUNC90_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) +/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC90_IN_SEL 0x0000003FU +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003FU +#define GPIO_FUNC90_IN_SEL_S 0 +/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001U +#define GPIO_SIG90_IN_SEL_S 7 + +/** GPIO_FUNC91_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) +/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC91_IN_SEL 0x0000003FU +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003FU +#define GPIO_FUNC91_IN_SEL_S 0 +/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001U +#define GPIO_SIG91_IN_SEL_S 7 + +/** GPIO_FUNC92_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC92_IN_SEL 0x0000003FU +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003FU +#define GPIO_FUNC92_IN_SEL_S 0 +/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001U +#define GPIO_SIG92_IN_SEL_S 7 + +/** GPIO_FUNC93_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) +/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC93_IN_SEL 0x0000003FU +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003FU +#define GPIO_FUNC93_IN_SEL_S 0 +/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001U +#define GPIO_SIG93_IN_SEL_S 7 + +/** GPIO_FUNC94_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) +/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC94_IN_SEL 0x0000003FU +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003FU +#define GPIO_FUNC94_IN_SEL_S 0 +/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001U +#define GPIO_SIG94_IN_SEL_S 7 + +/** GPIO_FUNC95_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) +/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC95_IN_SEL 0x0000003FU +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003FU +#define GPIO_FUNC95_IN_SEL_S 0 +/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001U +#define GPIO_SIG95_IN_SEL_S 7 + +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 7 + +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 7 + +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 7 + +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 7 + +/** GPIO_FUNC101_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC101_IN_SEL 0x0000003FU +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003FU +#define GPIO_FUNC101_IN_SEL_S 0 +/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001U +#define GPIO_SIG101_IN_SEL_S 7 + +/** GPIO_FUNC102_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC102_IN_SEL 0x0000003FU +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003FU +#define GPIO_FUNC102_IN_SEL_S 0 +/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001U +#define GPIO_SIG102_IN_SEL_S 7 + +/** GPIO_FUNC103_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC103_IN_SEL 0x0000003FU +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003FU +#define GPIO_FUNC103_IN_SEL_S 0 +/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001U +#define GPIO_SIG103_IN_SEL_S 7 + +/** GPIO_FUNC104_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC104_IN_SEL 0x0000003FU +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003FU +#define GPIO_FUNC104_IN_SEL_S 0 +/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001U +#define GPIO_SIG104_IN_SEL_S 7 + +/** GPIO_FUNC105_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC105_IN_SEL 0x0000003FU +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003FU +#define GPIO_FUNC105_IN_SEL_S 0 +/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001U +#define GPIO_SIG105_IN_SEL_S 7 + +/** GPIO_FUNC106_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC106_IN_SEL 0x0000003FU +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003FU +#define GPIO_FUNC106_IN_SEL_S 0 +/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001U +#define GPIO_SIG106_IN_SEL_S 7 + +/** GPIO_FUNC107_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC107_IN_SEL 0x0000003FU +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003FU +#define GPIO_FUNC107_IN_SEL_S 0 +/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001U +#define GPIO_SIG107_IN_SEL_S 7 + +/** GPIO_FUNC108_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC108_IN_SEL 0x0000003FU +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003FU +#define GPIO_FUNC108_IN_SEL_S 0 +/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001U +#define GPIO_SIG108_IN_SEL_S 7 + +/** GPIO_FUNC109_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC109_IN_SEL 0x0000003FU +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003FU +#define GPIO_FUNC109_IN_SEL_S 0 +/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001U +#define GPIO_SIG109_IN_SEL_S 7 + +/** GPIO_FUNC110_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC110_IN_SEL 0x0000003FU +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003FU +#define GPIO_FUNC110_IN_SEL_S 0 +/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001U +#define GPIO_SIG110_IN_SEL_S 7 + +/** GPIO_FUNC111_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC111_IN_SEL 0x0000003FU +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003FU +#define GPIO_FUNC111_IN_SEL_S 0 +/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001U +#define GPIO_SIG111_IN_SEL_S 7 + +/** GPIO_FUNC112_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC112_IN_SEL 0x0000003FU +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003FU +#define GPIO_FUNC112_IN_SEL_S 0 +/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001U +#define GPIO_SIG112_IN_SEL_S 7 + +/** GPIO_FUNC113_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC113_IN_SEL 0x0000003FU +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003FU +#define GPIO_FUNC113_IN_SEL_S 0 +/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001U +#define GPIO_SIG113_IN_SEL_S 7 + +/** GPIO_FUNC114_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) +/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC114_IN_SEL 0x0000003FU +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003FU +#define GPIO_FUNC114_IN_SEL_S 0 +/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001U +#define GPIO_SIG114_IN_SEL_S 7 + +/** GPIO_FUNC115_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC115_IN_SEL 0x0000003FU +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003FU +#define GPIO_FUNC115_IN_SEL_S 0 +/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001U +#define GPIO_SIG115_IN_SEL_S 7 + +/** GPIO_FUNC116_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC116_IN_SEL 0x0000003FU +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003FU +#define GPIO_FUNC116_IN_SEL_S 0 +/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001U +#define GPIO_SIG116_IN_SEL_S 7 + +/** GPIO_FUNC117_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC117_IN_SEL 0x0000003FU +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003FU +#define GPIO_FUNC117_IN_SEL_S 0 +/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001U +#define GPIO_SIG117_IN_SEL_S 7 + +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 7 + +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 7 + +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 7 + +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 7 + +/** GPIO_FUNC122_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC122_IN_SEL 0x0000003FU +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003FU +#define GPIO_FUNC122_IN_SEL_S 0 +/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001U +#define GPIO_SIG122_IN_SEL_S 7 + +/** GPIO_FUNC123_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC123_IN_SEL 0x0000003FU +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003FU +#define GPIO_FUNC123_IN_SEL_S 0 +/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001U +#define GPIO_SIG123_IN_SEL_S 7 + +/** GPIO_FUNC124_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC124_IN_SEL 0x0000003FU +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003FU +#define GPIO_FUNC124_IN_SEL_S 0 +/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001U +#define GPIO_SIG124_IN_SEL_S 7 + +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC0_OUT_SEL 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_SEL_S 9 +/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_INV_SEL_S 10 + +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC1_OUT_SEL 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_SEL_S 9 +/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_INV_SEL_S 10 + +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) +/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC2_OUT_SEL 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_SEL_S 9 +/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_INV_SEL_S 10 + +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC3_OUT_SEL 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_SEL_S 9 +/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_INV_SEL_S 10 + +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC4_OUT_SEL 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_SEL_S 9 +/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_INV_SEL_S 10 + +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC5_OUT_SEL 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_SEL_S 9 +/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_INV_SEL_S 10 + +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) +/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC6_OUT_SEL 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_SEL_S 9 +/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_INV_SEL_S 10 + +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC7_OUT_SEL 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_SEL_S 9 +/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_INV_SEL_S 10 + +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC8_OUT_SEL 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_SEL_S 9 +/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_INV_SEL_S 10 + +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC9_OUT_SEL 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_SEL_S 9 +/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_INV_SEL_S 10 + +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) +/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC10_OUT_SEL 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_SEL_S 9 +/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_INV_SEL_S 10 + +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC11_OUT_SEL 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_SEL_S 9 +/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_INV_SEL_S 10 + +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC12_OUT_SEL 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_SEL_S 9 +/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_INV_SEL_S 10 + +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC13_OUT_SEL 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_SEL_S 9 +/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_INV_SEL_S 10 + +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) +/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC14_OUT_SEL 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_SEL_S 9 +/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_INV_SEL_S 10 + +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC15_OUT_SEL 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_SEL_S 9 +/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_INV_SEL_S 10 + +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC16_OUT_SEL 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_SEL_S 9 +/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_INV_SEL_S 10 + +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC17_OUT_SEL 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_SEL_S 9 +/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_INV_SEL_S 10 + +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) +/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC18_OUT_SEL 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_SEL_S 9 +/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_INV_SEL_S 10 + +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) +/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC19_OUT_SEL 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_SEL_S 9 +/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_INV_SEL_S 10 + +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) +/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC20_OUT_SEL 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_SEL_S 9 +/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_INV_SEL_S 10 + +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) +/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC21_OUT_SEL 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_SEL_S 9 +/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_INV_SEL_S 10 + +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) +/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC22_OUT_SEL 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_SEL_S 9 +/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_INV_SEL_S 10 + +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) +/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC23_OUT_SEL 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_SEL_S 9 +/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_INV_SEL_S 10 + +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) +/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC24_OUT_SEL 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_SEL_S 9 +/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_INV_SEL_S 10 + +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_SEL_S 9 +/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_INV_SEL_S 10 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_SEL_S 9 +/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_INV_SEL_S 10 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_SEL_S 9 +/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_INV_SEL_S 10 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_SEL_S 9 +/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_INV_SEL_S 10 + +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) +/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_SEL_S 9 +/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_INV_SEL_S 10 + +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) +/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 8 +/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OEN_SEL (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_SEL_S 9 +/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_INV_SEL_S 10 + +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_DATE_REG register + * GPIO version register + */ +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 36704512; + * version register + */ +#define GPIO_DATE 0x0FFFFFFFU +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFFU +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_sig_map.h b/components/soc/esp32c5/include/soc/gpio_sig_map.h new file mode 100644 index 00000000000..b998fffc807 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_sig_map.h @@ -0,0 +1,177 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define USB_JTAG_TDO_BRIDGE_IDX 19 +#define USB_JTAG_TRST_IDX 19 +#define USB_OTG_32K_IN_IDX 21 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define I2CEXT0_SCL_IN_IDX 45 +#define I2CEXT0_SCL_OUT_IDX 45 +#define I2CEXT0_SDA_IN_IDX 46 +#define I2CEXT0_SDA_OUT_IDX 46 +#define PARL_RX_DATA0_IDX 47 +#define PARL_TX_DATA0_IDX 47 +#define PARL_RX_DATA1_IDX 48 +#define PARL_TX_DATA1_IDX 48 +#define PARL_RX_DATA2_IDX 49 +#define PARL_TX_DATA2_IDX 49 +#define PARL_RX_DATA3_IDX 50 +#define PARL_TX_DATA3_IDX 50 +#define PARL_RX_DATA4_IDX 51 +#define PARL_TX_DATA4_IDX 51 +#define PARL_RX_DATA5_IDX 52 +#define PARL_TX_DATA5_IDX 52 +#define PARL_RX_DATA6_IDX 53 +#define PARL_TX_DATA6_IDX 53 +#define PARL_RX_DATA7_IDX 54 +#define PARL_TX_DATA7_IDX 54 +#define SDIO_TOHOST_INT_OUT_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_MUX_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define PARL_RX_CLK_IN_IDX 69 +#define PARL_RX_CLK_OUT_IDX 69 +#define PARL_TX_CLK_IN_IDX 70 +#define PARL_TX_CLK_OUT_IDX 70 +#define RMT_SIG_IN0_IDX 71 +#define RMT_SIG_OUT0_IDX 71 +#define RMT_SIG_IN1_IDX 72 +#define RMT_SIG_OUT1_IDX 72 +#define TWAI0_RX_IDX 73 +#define TWAI0_TX_IDX 73 +#define TWAI0_BUS_OFF_ON_IDX 74 +#define TWAI0_CLKOUT_IDX 75 +#define TWAI0_STANDBY_IDX 76 +#define TWAI1_RX_IDX 77 +#define TWAI1_TX_IDX 77 +#define TWAI1_BUS_OFF_ON_IDX 78 +#define TWAI1_CLKOUT_IDX 79 +#define TWAI1_STANDBY_IDX 80 +#define PCNT_RST_IN0_IDX 83 +#define GPIO_SD0_OUT_IDX 83 +#define PCNT_RST_IN1_IDX 84 +#define GPIO_SD1_OUT_IDX 84 +#define PCNT_RST_IN2_IDX 85 +#define GPIO_SD2_OUT_IDX 85 +#define PCNT_RST_IN3_IDX 86 +#define GPIO_SD3_OUT_IDX 86 +#define PWM0_SYNC0_IN_IDX 87 +#define PWM0_OUT0A_IDX 87 +#define PWM0_SYNC1_IN_IDX 88 +#define PWM0_OUT0B_IDX 88 +#define PWM0_SYNC2_IN_IDX 89 +#define PWM0_OUT1A_IDX 89 +#define PWM0_F0_IN_IDX 90 +#define PWM0_OUT1B_IDX 90 +#define PWM0_F1_IN_IDX 91 +#define PWM0_OUT2A_IDX 91 +#define PWM0_F2_IN_IDX 92 +#define PWM0_OUT2B_IDX 92 +#define PWM0_CAP0_IN_IDX 93 +#define PWM0_CAP1_IN_IDX 94 +#define PWM0_CAP2_IN_IDX 95 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 101 +#define FSPICS1_OUT_IDX 101 +#define PCNT_SIG_CH1_IN0_IDX 102 +#define FSPICS2_OUT_IDX 102 +#define PCNT_CTRL_CH0_IN0_IDX 103 +#define FSPICS3_OUT_IDX 103 +#define PCNT_CTRL_CH1_IN0_IDX 104 +#define FSPICS4_OUT_IDX 104 +#define PCNT_SIG_CH0_IN1_IDX 105 +#define FSPICS5_OUT_IDX 105 +#define PCNT_SIG_CH1_IN1_IDX 106 +#define PCNT_CTRL_CH0_IN1_IDX 107 +#define PCNT_CTRL_CH1_IN1_IDX 108 +#define PCNT_SIG_CH0_IN2_IDX 109 +#define PCNT_SIG_CH1_IN2_IDX 110 +#define PCNT_CTRL_CH0_IN2_IDX 111 +#define PCNT_CTRL_CH1_IN2_IDX 112 +#define PCNT_SIG_CH0_IN3_IDX 113 +#define PCNT_SIG_CH1_IN3_IDX 114 +#define SPICLK_OUT_MUX_IDX 114 +#define PCNT_CTRL_CH0_IN3_IDX 115 +#define SPICS0_OUT_IDX 115 +#define PCNT_CTRL_CH1_IN3_IDX 116 +#define SPICS1_OUT_IDX 116 +#define SPIQ_IN_IDX 121 +#define SPIQ_OUT_IDX 121 +#define SPID_IN_IDX 122 +#define SPID_OUT_IDX 122 +#define SPIHD_IN_IDX 123 +#define SPIHD_OUT_IDX 123 +#define SPIWP_IN_IDX 124 +#define SPIWP_OUT_IDX 124 +#define CLK_OUT_OUT1_IDX 125 +#define CLK_OUT_OUT2_IDX 126 +#define CLK_OUT_OUT3_IDX 127 +#define GPIO_MAP_DATE_IDX 0x2301100 diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/include/soc/gpio_struct.h new file mode 100644 index 00000000000..0044e173fc0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_struct.h @@ -0,0 +1,2661 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration register */ +/** Type of bt_select register + * GPIO bit select register + */ +typedef union { + struct { + /** bt_sel : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ + uint32_t bt_sel:32; + }; + uint32_t val; +} gpio_bt_select_reg_t; + +/** Type of out register + * GPIO output register for GPIO0-30 + */ +typedef union { + struct { + /** out_data_orig : R/W/SC/WTC; bitpos: [30:0]; default: 0; + * GPIO output register for GPIO0-30 + */ + uint32_t out_data_orig:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register for GPIO0-30 + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [30:0]; default: 0; + * GPIO output set register for GPIO0-30 + */ + uint32_t out_w1ts:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register for GPIO0-30 + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [30:0]; default: 0; + * GPIO output clear register for GPIO0-30 + */ + uint32_t out_w1tc:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of sdio_select register + * GPIO sdio select register + */ +typedef union { + struct { + /** sdio_sel : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ + uint32_t sdio_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_sdio_select_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-30 + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO output enable register for GPIO0-30 + */ + uint32_t enable_data:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register for GPIO0-30 + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [30:0]; default: 0; + * GPIO output enable set register for GPIO0-30 + */ + uint32_t enable_w1ts:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register for GPIO0-30 + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [30:0]; default: 0; + * GPIO output enable clear register for GPIO0-30 + */ + uint32_t enable_w1tc:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of strap register + * pad strapping register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-30 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [30:0]; default: 0; + * GPIO input register for GPIO0-30 + */ + uint32_t in_data_next:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_in_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO interrupt status register for GPIO0-30 + */ + uint32_t status_interrupt:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register for GPIO0-30 + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status set register for GPIO0-30 + */ + uint32_t status_w1ts:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register for GPIO0-30 + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-30 + */ + uint32_t status_w1tc:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of pcpu_int register + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ + uint32_t procpu_int:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_pcpu_int_reg_t; + +/** Type of pcpu_nmi_int register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** procpu_nmi_int : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ + uint32_t procpu_nmi_int:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_pcpu_nmi_int_reg_t; + +/** Type of cpusdio_int register + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [30:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ + uint32_t sdio_int:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_cpusdio_int_reg_t; + +/** Type of pinn register + * GPIO pin configuration register + */ +typedef union { + struct { + /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pinn_sync2_bypass:2; + /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ + uint32_t pinn_pad_driver:1; + /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pinn_sync1_bypass:2; + uint32_t reserved_5:2; + /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ + uint32_t pinn_int_type:3; + /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ + uint32_t pinn_wakeup_enable:1; + /** pinn_config : R/W; bitpos: [12:11]; default: 0; + * reserved + */ + uint32_t pinn_config:2; + /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ + uint32_t pinn_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pinn_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [30:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_next_reg_t; + +/** Type of func0_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func0_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func0_in_sel:6; + /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func0_in_inv_sel:1; + /** sig0_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig0_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func0_in_sel_cfg_reg_t; + +/** Type of func6_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func6_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func6_in_sel:6; + /** func6_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func6_in_inv_sel:1; + /** sig6_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig6_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func6_in_sel_cfg_reg_t; + +/** Type of func7_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func7_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func7_in_sel:6; + /** func7_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func7_in_inv_sel:1; + /** sig7_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig7_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func7_in_sel_cfg_reg_t; + +/** Type of func8_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func8_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func8_in_sel:6; + /** func8_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func8_in_inv_sel:1; + /** sig8_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig8_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func8_in_sel_cfg_reg_t; + +/** Type of func9_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func9_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func9_in_sel:6; + /** func9_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func9_in_inv_sel:1; + /** sig9_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig9_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func9_in_sel_cfg_reg_t; + +/** Type of func10_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func10_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func10_in_sel:6; + /** func10_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func10_in_inv_sel:1; + /** sig10_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig10_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func10_in_sel_cfg_reg_t; + +/** Type of func11_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func11_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func11_in_sel:6; + /** func11_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func11_in_inv_sel:1; + /** sig11_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig11_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func11_in_sel_cfg_reg_t; + +/** Type of func12_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func12_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func12_in_sel:6; + /** func12_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func12_in_inv_sel:1; + /** sig12_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig12_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func12_in_sel_cfg_reg_t; + +/** Type of func13_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func13_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func13_in_sel:6; + /** func13_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func13_in_inv_sel:1; + /** sig13_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig13_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func13_in_sel_cfg_reg_t; + +/** Type of func14_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func14_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func14_in_sel:6; + /** func14_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func14_in_inv_sel:1; + /** sig14_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig14_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func14_in_sel_cfg_reg_t; + +/** Type of func15_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func15_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func15_in_sel:6; + /** func15_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func15_in_inv_sel:1; + /** sig15_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig15_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func15_in_sel_cfg_reg_t; + +/** Type of func16_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func16_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func16_in_sel:6; + /** func16_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func16_in_inv_sel:1; + /** sig16_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig16_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func16_in_sel_cfg_reg_t; + +/** Type of func17_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func17_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func17_in_sel:6; + /** func17_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func17_in_inv_sel:1; + /** sig17_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig17_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func17_in_sel_cfg_reg_t; + +/** Type of func19_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func19_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func19_in_sel:6; + /** func19_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func19_in_inv_sel:1; + /** sig19_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig19_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func19_in_sel_cfg_reg_t; + +/** Type of func21_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func21_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func21_in_sel:6; + /** func21_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func21_in_inv_sel:1; + /** sig21_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig21_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func21_in_sel_cfg_reg_t; + +/** Type of func22_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func22_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func22_in_sel:6; + /** func22_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func22_in_inv_sel:1; + /** sig22_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig22_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func22_in_sel_cfg_reg_t; + +/** Type of func23_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func23_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func23_in_sel:6; + /** func23_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func23_in_inv_sel:1; + /** sig23_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig23_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func23_in_sel_cfg_reg_t; + +/** Type of func24_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func24_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func24_in_sel:6; + /** func24_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func24_in_inv_sel:1; + /** sig24_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig24_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func24_in_sel_cfg_reg_t; + +/** Type of func28_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func28_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func28_in_sel:6; + /** func28_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func28_in_inv_sel:1; + /** sig28_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig28_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func28_in_sel_cfg_reg_t; + +/** Type of func29_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func29_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func29_in_sel:6; + /** func29_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func29_in_inv_sel:1; + /** sig29_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig29_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func29_in_sel_cfg_reg_t; + +/** Type of func30_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func30_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func30_in_sel:6; + /** func30_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func30_in_inv_sel:1; + /** sig30_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig30_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func30_in_sel_cfg_reg_t; + +/** Type of func31_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func31_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func31_in_sel:6; + /** func31_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func31_in_inv_sel:1; + /** sig31_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig31_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func31_in_sel_cfg_reg_t; + +/** Type of func32_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func32_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func32_in_sel:6; + /** func32_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func32_in_inv_sel:1; + /** sig32_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig32_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func32_in_sel_cfg_reg_t; + +/** Type of func33_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func33_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func33_in_sel:6; + /** func33_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func33_in_inv_sel:1; + /** sig33_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig33_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func33_in_sel_cfg_reg_t; + +/** Type of func34_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func34_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func34_in_sel:6; + /** func34_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func34_in_inv_sel:1; + /** sig34_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig34_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func34_in_sel_cfg_reg_t; + +/** Type of func35_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func35_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func35_in_sel:6; + /** func35_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func35_in_inv_sel:1; + /** sig35_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig35_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func35_in_sel_cfg_reg_t; + +/** Type of func40_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func40_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func40_in_sel:6; + /** func40_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func40_in_inv_sel:1; + /** sig40_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig40_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func40_in_sel_cfg_reg_t; + +/** Type of func41_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func41_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func41_in_sel:6; + /** func41_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func41_in_inv_sel:1; + /** sig41_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig41_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func41_in_sel_cfg_reg_t; + +/** Type of func42_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func42_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func42_in_sel:6; + /** func42_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func42_in_inv_sel:1; + /** sig42_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig42_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func42_in_sel_cfg_reg_t; + +/** Type of func45_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func45_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func45_in_sel:6; + /** func45_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func45_in_inv_sel:1; + /** sig45_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig45_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func45_in_sel_cfg_reg_t; + +/** Type of func46_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func46_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func46_in_sel:6; + /** func46_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func46_in_inv_sel:1; + /** sig46_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig46_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func46_in_sel_cfg_reg_t; + +/** Type of func47_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func47_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func47_in_sel:6; + /** func47_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func47_in_inv_sel:1; + /** sig47_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig47_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func47_in_sel_cfg_reg_t; + +/** Type of func48_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func48_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func48_in_sel:6; + /** func48_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func48_in_inv_sel:1; + /** sig48_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig48_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func48_in_sel_cfg_reg_t; + +/** Type of func49_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func49_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func49_in_sel:6; + /** func49_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func49_in_inv_sel:1; + /** sig49_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig49_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func49_in_sel_cfg_reg_t; + +/** Type of func50_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func50_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func50_in_sel:6; + /** func50_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func50_in_inv_sel:1; + /** sig50_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig50_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func50_in_sel_cfg_reg_t; + +/** Type of func51_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func51_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func51_in_sel:6; + /** func51_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func51_in_inv_sel:1; + /** sig51_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig51_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func51_in_sel_cfg_reg_t; + +/** Type of func52_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func52_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func52_in_sel:6; + /** func52_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func52_in_inv_sel:1; + /** sig52_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig52_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func52_in_sel_cfg_reg_t; + +/** Type of func53_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func53_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func53_in_sel:6; + /** func53_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func53_in_inv_sel:1; + /** sig53_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig53_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func53_in_sel_cfg_reg_t; + +/** Type of func54_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func54_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func54_in_sel:6; + /** func54_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func54_in_inv_sel:1; + /** sig54_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig54_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func54_in_sel_cfg_reg_t; + +/** Type of func63_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func63_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func63_in_sel:6; + /** func63_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func63_in_inv_sel:1; + /** sig63_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig63_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func63_in_sel_cfg_reg_t; + +/** Type of func64_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func64_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func64_in_sel:6; + /** func64_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func64_in_inv_sel:1; + /** sig64_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig64_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func64_in_sel_cfg_reg_t; + +/** Type of func65_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func65_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func65_in_sel:6; + /** func65_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func65_in_inv_sel:1; + /** sig65_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig65_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func65_in_sel_cfg_reg_t; + +/** Type of func66_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func66_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func66_in_sel:6; + /** func66_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func66_in_inv_sel:1; + /** sig66_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig66_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func66_in_sel_cfg_reg_t; + +/** Type of func67_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func67_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func67_in_sel:6; + /** func67_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func67_in_inv_sel:1; + /** sig67_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig67_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func67_in_sel_cfg_reg_t; + +/** Type of func68_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func68_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func68_in_sel:6; + /** func68_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func68_in_inv_sel:1; + /** sig68_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig68_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func68_in_sel_cfg_reg_t; + +/** Type of func69_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func69_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func69_in_sel:6; + /** func69_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func69_in_inv_sel:1; + /** sig69_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig69_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func69_in_sel_cfg_reg_t; + +/** Type of func70_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func70_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func70_in_sel:6; + /** func70_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func70_in_inv_sel:1; + /** sig70_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig70_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func70_in_sel_cfg_reg_t; + +/** Type of func71_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func71_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func71_in_sel:6; + /** func71_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func71_in_inv_sel:1; + /** sig71_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig71_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func71_in_sel_cfg_reg_t; + +/** Type of func72_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func72_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func72_in_sel:6; + /** func72_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func72_in_inv_sel:1; + /** sig72_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig72_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func72_in_sel_cfg_reg_t; + +/** Type of func73_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func73_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func73_in_sel:6; + /** func73_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func73_in_inv_sel:1; + /** sig73_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig73_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func73_in_sel_cfg_reg_t; + +/** Type of func77_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func77_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func77_in_sel:6; + /** func77_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func77_in_inv_sel:1; + /** sig77_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig77_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func77_in_sel_cfg_reg_t; + +/** Type of func81_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func81_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func81_in_sel:6; + /** func81_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func81_in_inv_sel:1; + /** sig81_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig81_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func81_in_sel_cfg_reg_t; + +/** Type of func82_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func82_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func82_in_sel:6; + /** func82_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func82_in_inv_sel:1; + /** sig82_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig82_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func82_in_sel_cfg_reg_t; + +/** Type of func83_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func83_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func83_in_sel:6; + /** func83_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func83_in_inv_sel:1; + /** sig83_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig83_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func83_in_sel_cfg_reg_t; + +/** Type of func84_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func84_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func84_in_sel:6; + /** func84_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func84_in_inv_sel:1; + /** sig84_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig84_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func84_in_sel_cfg_reg_t; + +/** Type of func85_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func85_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func85_in_sel:6; + /** func85_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func85_in_inv_sel:1; + /** sig85_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig85_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func85_in_sel_cfg_reg_t; + +/** Type of func86_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func86_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func86_in_sel:6; + /** func86_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func86_in_inv_sel:1; + /** sig86_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig86_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func86_in_sel_cfg_reg_t; + +/** Type of func87_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func87_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func87_in_sel:6; + /** func87_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func87_in_inv_sel:1; + /** sig87_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig87_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func87_in_sel_cfg_reg_t; + +/** Type of func88_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func88_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func88_in_sel:6; + /** func88_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func88_in_inv_sel:1; + /** sig88_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig88_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func88_in_sel_cfg_reg_t; + +/** Type of func89_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func89_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func89_in_sel:6; + /** func89_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func89_in_inv_sel:1; + /** sig89_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig89_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func89_in_sel_cfg_reg_t; + +/** Type of func90_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func90_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func90_in_sel:6; + /** func90_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func90_in_inv_sel:1; + /** sig90_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig90_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func90_in_sel_cfg_reg_t; + +/** Type of func91_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func91_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func91_in_sel:6; + /** func91_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func91_in_inv_sel:1; + /** sig91_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig91_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func91_in_sel_cfg_reg_t; + +/** Type of func92_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func92_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func92_in_sel:6; + /** func92_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func92_in_inv_sel:1; + /** sig92_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig92_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func92_in_sel_cfg_reg_t; + +/** Type of func93_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func93_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func93_in_sel:6; + /** func93_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func93_in_inv_sel:1; + /** sig93_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig93_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func93_in_sel_cfg_reg_t; + +/** Type of func94_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func94_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func94_in_sel:6; + /** func94_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func94_in_inv_sel:1; + /** sig94_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig94_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func94_in_sel_cfg_reg_t; + +/** Type of func95_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func95_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func95_in_sel:6; + /** func95_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func95_in_inv_sel:1; + /** sig95_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig95_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func95_in_sel_cfg_reg_t; + +/** Type of func97_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func97_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func97_in_sel:6; + /** func97_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func97_in_inv_sel:1; + /** sig97_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig97_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func97_in_sel_cfg_reg_t; + +/** Type of func98_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func98_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func98_in_sel:6; + /** func98_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func98_in_inv_sel:1; + /** sig98_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig98_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func98_in_sel_cfg_reg_t; + +/** Type of func99_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func99_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func99_in_sel:6; + /** func99_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func99_in_inv_sel:1; + /** sig99_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig99_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func99_in_sel_cfg_reg_t; + +/** Type of func100_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func100_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func100_in_sel:6; + /** func100_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func100_in_inv_sel:1; + /** sig100_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig100_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func100_in_sel_cfg_reg_t; + +/** Type of func101_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func101_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func101_in_sel:6; + /** func101_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func101_in_inv_sel:1; + /** sig101_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig101_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func101_in_sel_cfg_reg_t; + +/** Type of func102_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func102_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func102_in_sel:6; + /** func102_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func102_in_inv_sel:1; + /** sig102_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig102_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func102_in_sel_cfg_reg_t; + +/** Type of func103_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func103_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func103_in_sel:6; + /** func103_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func103_in_inv_sel:1; + /** sig103_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig103_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func103_in_sel_cfg_reg_t; + +/** Type of func104_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func104_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func104_in_sel:6; + /** func104_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func104_in_inv_sel:1; + /** sig104_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig104_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func104_in_sel_cfg_reg_t; + +/** Type of func105_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func105_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func105_in_sel:6; + /** func105_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func105_in_inv_sel:1; + /** sig105_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig105_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func105_in_sel_cfg_reg_t; + +/** Type of func106_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func106_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func106_in_sel:6; + /** func106_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func106_in_inv_sel:1; + /** sig106_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig106_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func106_in_sel_cfg_reg_t; + +/** Type of func107_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func107_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func107_in_sel:6; + /** func107_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func107_in_inv_sel:1; + /** sig107_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig107_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func107_in_sel_cfg_reg_t; + +/** Type of func108_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func108_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func108_in_sel:6; + /** func108_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func108_in_inv_sel:1; + /** sig108_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig108_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func108_in_sel_cfg_reg_t; + +/** Type of func109_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func109_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func109_in_sel:6; + /** func109_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func109_in_inv_sel:1; + /** sig109_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig109_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func109_in_sel_cfg_reg_t; + +/** Type of func110_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func110_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func110_in_sel:6; + /** func110_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func110_in_inv_sel:1; + /** sig110_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig110_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func110_in_sel_cfg_reg_t; + +/** Type of func111_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func111_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func111_in_sel:6; + /** func111_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func111_in_inv_sel:1; + /** sig111_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig111_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func111_in_sel_cfg_reg_t; + +/** Type of func112_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func112_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func112_in_sel:6; + /** func112_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func112_in_inv_sel:1; + /** sig112_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig112_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func112_in_sel_cfg_reg_t; + +/** Type of func113_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func113_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func113_in_sel:6; + /** func113_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func113_in_inv_sel:1; + /** sig113_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig113_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func113_in_sel_cfg_reg_t; + +/** Type of func114_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func114_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func114_in_sel:6; + /** func114_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func114_in_inv_sel:1; + /** sig114_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig114_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func114_in_sel_cfg_reg_t; + +/** Type of func115_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func115_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func115_in_sel:6; + /** func115_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func115_in_inv_sel:1; + /** sig115_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig115_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func115_in_sel_cfg_reg_t; + +/** Type of func116_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func116_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func116_in_sel:6; + /** func116_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func116_in_inv_sel:1; + /** sig116_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig116_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func116_in_sel_cfg_reg_t; + +/** Type of func117_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func117_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func117_in_sel:6; + /** func117_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func117_in_inv_sel:1; + /** sig117_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig117_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func117_in_sel_cfg_reg_t; + +/** Type of func118_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func118_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func118_in_sel:6; + /** func118_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func118_in_inv_sel:1; + /** sig118_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig118_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func118_in_sel_cfg_reg_t; + +/** Type of func119_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func119_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func119_in_sel:6; + /** func119_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func119_in_inv_sel:1; + /** sig119_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig119_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func119_in_sel_cfg_reg_t; + +/** Type of func120_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func120_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func120_in_sel:6; + /** func120_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func120_in_inv_sel:1; + /** sig120_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig120_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func120_in_sel_cfg_reg_t; + +/** Type of func121_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func121_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func121_in_sel:6; + /** func121_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func121_in_inv_sel:1; + /** sig121_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig121_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func121_in_sel_cfg_reg_t; + +/** Type of func122_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func122_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func122_in_sel:6; + /** func122_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func122_in_inv_sel:1; + /** sig122_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig122_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func122_in_sel_cfg_reg_t; + +/** Type of func123_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func123_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func123_in_sel:6; + /** func123_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func123_in_inv_sel:1; + /** sig123_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig123_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func123_in_sel_cfg_reg_t; + +/** Type of func124_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func124_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func124_in_sel:6; + /** func124_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func124_in_inv_sel:1; + /** sig124_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig124_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func124_in_sel_cfg_reg_t; + +/** Type of funcn_out_sel_cfg register + * GPIO output function select register + */ +typedef union { + struct { + /** funcn_out_sel : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ + uint32_t funcn_out_sel:8; + /** funcn_out_inv_sel : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ + uint32_t funcn_out_inv_sel:1; + /** funcn_oen_sel : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ + uint32_t funcn_oen_sel:1; + /** funcn_oen_inv_sel : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ + uint32_t funcn_oen_inv_sel:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} gpio_funcn_out_sel_cfg_reg_t; + +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + +/** Type of date register + * GPIO version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36704512; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_date_reg_t; + + +typedef struct gpio_dev_t { + volatile gpio_bt_select_reg_t bt_select; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + uint32_t reserved_010[3]; + volatile gpio_sdio_select_reg_t sdio_select; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + uint32_t reserved_02c[3]; + volatile gpio_strap_reg_t strap; + volatile gpio_in_reg_t in; + uint32_t reserved_040; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + uint32_t reserved_050[3]; + volatile gpio_pcpu_int_reg_t pcpu_int; + volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; + volatile gpio_cpusdio_int_reg_t cpusdio_int; + uint32_t reserved_068[3]; + volatile gpio_pinn_reg_t pinn[31]; + uint32_t reserved_0f0[23]; + volatile gpio_status_next_reg_t status_next; + uint32_t reserved_150; + volatile gpio_func0_in_sel_cfg_reg_t func0_in_sel_cfg; + uint32_t reserved_158[5]; + volatile gpio_func6_in_sel_cfg_reg_t func6_in_sel_cfg; + volatile gpio_func7_in_sel_cfg_reg_t func7_in_sel_cfg; + volatile gpio_func8_in_sel_cfg_reg_t func8_in_sel_cfg; + volatile gpio_func9_in_sel_cfg_reg_t func9_in_sel_cfg; + volatile gpio_func10_in_sel_cfg_reg_t func10_in_sel_cfg; + volatile gpio_func11_in_sel_cfg_reg_t func11_in_sel_cfg; + volatile gpio_func12_in_sel_cfg_reg_t func12_in_sel_cfg; + volatile gpio_func13_in_sel_cfg_reg_t func13_in_sel_cfg; + volatile gpio_func14_in_sel_cfg_reg_t func14_in_sel_cfg; + volatile gpio_func15_in_sel_cfg_reg_t func15_in_sel_cfg; + volatile gpio_func16_in_sel_cfg_reg_t func16_in_sel_cfg; + volatile gpio_func17_in_sel_cfg_reg_t func17_in_sel_cfg; + uint32_t reserved_19c; + volatile gpio_func19_in_sel_cfg_reg_t func19_in_sel_cfg; + uint32_t reserved_1a4; + volatile gpio_func21_in_sel_cfg_reg_t func21_in_sel_cfg; + volatile gpio_func22_in_sel_cfg_reg_t func22_in_sel_cfg; + volatile gpio_func23_in_sel_cfg_reg_t func23_in_sel_cfg; + volatile gpio_func24_in_sel_cfg_reg_t func24_in_sel_cfg; + uint32_t reserved_1b8[3]; + volatile gpio_func28_in_sel_cfg_reg_t func28_in_sel_cfg; + volatile gpio_func29_in_sel_cfg_reg_t func29_in_sel_cfg; + volatile gpio_func30_in_sel_cfg_reg_t func30_in_sel_cfg; + volatile gpio_func31_in_sel_cfg_reg_t func31_in_sel_cfg; + volatile gpio_func32_in_sel_cfg_reg_t func32_in_sel_cfg; + volatile gpio_func33_in_sel_cfg_reg_t func33_in_sel_cfg; + volatile gpio_func34_in_sel_cfg_reg_t func34_in_sel_cfg; + volatile gpio_func35_in_sel_cfg_reg_t func35_in_sel_cfg; + uint32_t reserved_1e4[4]; + volatile gpio_func40_in_sel_cfg_reg_t func40_in_sel_cfg; + volatile gpio_func41_in_sel_cfg_reg_t func41_in_sel_cfg; + volatile gpio_func42_in_sel_cfg_reg_t func42_in_sel_cfg; + uint32_t reserved_200[2]; + volatile gpio_func45_in_sel_cfg_reg_t func45_in_sel_cfg; + volatile gpio_func46_in_sel_cfg_reg_t func46_in_sel_cfg; + volatile gpio_func47_in_sel_cfg_reg_t func47_in_sel_cfg; + volatile gpio_func48_in_sel_cfg_reg_t func48_in_sel_cfg; + volatile gpio_func49_in_sel_cfg_reg_t func49_in_sel_cfg; + volatile gpio_func50_in_sel_cfg_reg_t func50_in_sel_cfg; + volatile gpio_func51_in_sel_cfg_reg_t func51_in_sel_cfg; + volatile gpio_func52_in_sel_cfg_reg_t func52_in_sel_cfg; + volatile gpio_func53_in_sel_cfg_reg_t func53_in_sel_cfg; + volatile gpio_func54_in_sel_cfg_reg_t func54_in_sel_cfg; + uint32_t reserved_230[8]; + volatile gpio_func63_in_sel_cfg_reg_t func63_in_sel_cfg; + volatile gpio_func64_in_sel_cfg_reg_t func64_in_sel_cfg; + volatile gpio_func65_in_sel_cfg_reg_t func65_in_sel_cfg; + volatile gpio_func66_in_sel_cfg_reg_t func66_in_sel_cfg; + volatile gpio_func67_in_sel_cfg_reg_t func67_in_sel_cfg; + volatile gpio_func68_in_sel_cfg_reg_t func68_in_sel_cfg; + volatile gpio_func69_in_sel_cfg_reg_t func69_in_sel_cfg; + volatile gpio_func70_in_sel_cfg_reg_t func70_in_sel_cfg; + volatile gpio_func71_in_sel_cfg_reg_t func71_in_sel_cfg; + volatile gpio_func72_in_sel_cfg_reg_t func72_in_sel_cfg; + volatile gpio_func73_in_sel_cfg_reg_t func73_in_sel_cfg; + uint32_t reserved_27c[3]; + volatile gpio_func77_in_sel_cfg_reg_t func77_in_sel_cfg; + uint32_t reserved_28c[3]; + volatile gpio_func81_in_sel_cfg_reg_t func81_in_sel_cfg; + volatile gpio_func82_in_sel_cfg_reg_t func82_in_sel_cfg; + volatile gpio_func83_in_sel_cfg_reg_t func83_in_sel_cfg; + volatile gpio_func84_in_sel_cfg_reg_t func84_in_sel_cfg; + volatile gpio_func85_in_sel_cfg_reg_t func85_in_sel_cfg; + volatile gpio_func86_in_sel_cfg_reg_t func86_in_sel_cfg; + volatile gpio_func87_in_sel_cfg_reg_t func87_in_sel_cfg; + volatile gpio_func88_in_sel_cfg_reg_t func88_in_sel_cfg; + volatile gpio_func89_in_sel_cfg_reg_t func89_in_sel_cfg; + volatile gpio_func90_in_sel_cfg_reg_t func90_in_sel_cfg; + volatile gpio_func91_in_sel_cfg_reg_t func91_in_sel_cfg; + volatile gpio_func92_in_sel_cfg_reg_t func92_in_sel_cfg; + volatile gpio_func93_in_sel_cfg_reg_t func93_in_sel_cfg; + volatile gpio_func94_in_sel_cfg_reg_t func94_in_sel_cfg; + volatile gpio_func95_in_sel_cfg_reg_t func95_in_sel_cfg; + uint32_t reserved_2d4; + volatile gpio_func97_in_sel_cfg_reg_t func97_in_sel_cfg; + volatile gpio_func98_in_sel_cfg_reg_t func98_in_sel_cfg; + volatile gpio_func99_in_sel_cfg_reg_t func99_in_sel_cfg; + volatile gpio_func100_in_sel_cfg_reg_t func100_in_sel_cfg; + volatile gpio_func101_in_sel_cfg_reg_t func101_in_sel_cfg; + volatile gpio_func102_in_sel_cfg_reg_t func102_in_sel_cfg; + volatile gpio_func103_in_sel_cfg_reg_t func103_in_sel_cfg; + volatile gpio_func104_in_sel_cfg_reg_t func104_in_sel_cfg; + volatile gpio_func105_in_sel_cfg_reg_t func105_in_sel_cfg; + volatile gpio_func106_in_sel_cfg_reg_t func106_in_sel_cfg; + volatile gpio_func107_in_sel_cfg_reg_t func107_in_sel_cfg; + volatile gpio_func108_in_sel_cfg_reg_t func108_in_sel_cfg; + volatile gpio_func109_in_sel_cfg_reg_t func109_in_sel_cfg; + volatile gpio_func110_in_sel_cfg_reg_t func110_in_sel_cfg; + volatile gpio_func111_in_sel_cfg_reg_t func111_in_sel_cfg; + volatile gpio_func112_in_sel_cfg_reg_t func112_in_sel_cfg; + volatile gpio_func113_in_sel_cfg_reg_t func113_in_sel_cfg; + volatile gpio_func114_in_sel_cfg_reg_t func114_in_sel_cfg; + volatile gpio_func115_in_sel_cfg_reg_t func115_in_sel_cfg; + volatile gpio_func116_in_sel_cfg_reg_t func116_in_sel_cfg; + volatile gpio_func117_in_sel_cfg_reg_t func117_in_sel_cfg; + volatile gpio_func118_in_sel_cfg_reg_t func118_in_sel_cfg; + volatile gpio_func119_in_sel_cfg_reg_t func119_in_sel_cfg; + volatile gpio_func120_in_sel_cfg_reg_t func120_in_sel_cfg; + volatile gpio_func121_in_sel_cfg_reg_t func121_in_sel_cfg; + volatile gpio_func122_in_sel_cfg_reg_t func122_in_sel_cfg; + volatile gpio_func123_in_sel_cfg_reg_t func123_in_sel_cfg; + volatile gpio_func124_in_sel_cfg_reg_t func124_in_sel_cfg; + uint32_t reserved_348[131]; + volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[31]; + uint32_t reserved_5d0[23]; + volatile gpio_clock_gate_reg_t clock_gate; + uint32_t reserved_630[51]; + volatile gpio_date_reg_t date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hardware_lock_reg.h b/components/soc/esp32c5/include/soc/hardware_lock_reg.h new file mode 100644 index 00000000000..75451751c66 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hardware_lock_reg.h @@ -0,0 +1,76 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ATOMIC_ADDR_LOCK_REG register + * hardware lock regsiter + */ +#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0) +/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0; + * read to acquire hardware lock, write to release hardware lock + */ +#define ATOMIC_LOCK 0x00000003U +#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S) +#define ATOMIC_LOCK_V 0x00000003U +#define ATOMIC_LOCK_S 0 + +/** ATOMIC_LR_ADDR_REG register + * gloable lr address regsiter + */ +#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4) +/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0; + * backup gloable address + */ +#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S) +#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_ADDR_S 0 + +/** ATOMIC_LR_VALUE_REG register + * gloable lr value regsiter + */ +#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8) +/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0; + * backup gloable value + */ +#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S) +#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_VALUE_S 0 + +/** ATOMIC_LOCK_STATUS_REG register + * lock status regsiter + */ +#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc) +/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0; + * read hareware lock status for debug + */ +#define ATOMIC_LOCK_STATUS 0x00000003U +#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S) +#define ATOMIC_LOCK_STATUS_V 0x00000003U +#define ATOMIC_LOCK_STATUS_S 0 + +/** ATOMIC_COUNTER_REG register + * wait counter register + */ +#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10) +/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0; + * delay counter + */ +#define ATOMIC_WAIT_COUNTER 0x0000FFFFU +#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S) +#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU +#define ATOMIC_WAIT_COUNTER_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hardware_lock_struct.h b/components/soc/esp32c5/include/soc/hardware_lock_struct.h new file mode 100644 index 00000000000..799d6b4ba91 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hardware_lock_struct.h @@ -0,0 +1,98 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of addr_lock register + * hardware lock regsiter + */ +typedef union { + struct { + /** lock : R/W; bitpos: [1:0]; default: 0; + * read to acquire hardware lock, write to release hardware lock + */ + uint32_t lock:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} atomic_addr_lock_reg_t; + +/** Type of lr_addr register + * gloable lr address regsiter + */ +typedef union { + struct { + /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0; + * backup gloable address + */ + uint32_t gloable_lr_addr:32; + }; + uint32_t val; +} atomic_lr_addr_reg_t; + +/** Type of lr_value register + * gloable lr value regsiter + */ +typedef union { + struct { + /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0; + * backup gloable value + */ + uint32_t gloable_lr_value:32; + }; + uint32_t val; +} atomic_lr_value_reg_t; + +/** Type of lock_status register + * lock status regsiter + */ +typedef union { + struct { + /** lock_status : RO; bitpos: [1:0]; default: 0; + * read hareware lock status for debug + */ + uint32_t lock_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} atomic_lock_status_reg_t; + +/** Type of counter register + * wait counter register + */ +typedef union { + struct { + /** wait_counter : R/W; bitpos: [15:0]; default: 0; + * delay counter + */ + uint32_t wait_counter:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} atomic_counter_reg_t; + + +typedef struct atomic_dev_t { + volatile atomic_addr_lock_reg_t addr_lock; + volatile atomic_lr_addr_reg_t lr_addr; + volatile atomic_lr_value_reg_t lr_value; + volatile atomic_lock_status_reg_t lock_status; + volatile atomic_counter_reg_t counter; +} atomic_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hmac_reg.h b/components/soc/esp32c5/include/soc/hmac_reg.h new file mode 100644 index 00000000000..9ed7eb12735 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hmac_reg.h @@ -0,0 +1,232 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HMAC_SET_START_REG register + * Process control register 0. + */ +#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40) +/** HMAC_SET_START : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ +#define HMAC_SET_START (BIT(0)) +#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S) +#define HMAC_SET_START_V 0x00000001U +#define HMAC_SET_START_S 0 + +/** HMAC_SET_PARA_PURPOSE_REG register + * Configure purpose. + */ +#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44) +/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ +#define HMAC_PURPOSE_SET 0x0000000FU +#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S) +#define HMAC_PURPOSE_SET_V 0x0000000FU +#define HMAC_PURPOSE_SET_S 0 + +/** HMAC_SET_PARA_KEY_REG register + * Configure key. + */ +#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48) +/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ +#define HMAC_KEY_SET 0x00000007U +#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S) +#define HMAC_KEY_SET_V 0x00000007U +#define HMAC_KEY_SET_S 0 + +/** HMAC_SET_PARA_FINISH_REG register + * Finish initial configuration. + */ +#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c) +/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ +#define HMAC_SET_PARA_END (BIT(0)) +#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S) +#define HMAC_SET_PARA_END_V 0x00000001U +#define HMAC_SET_PARA_END_S 0 + +/** HMAC_SET_MESSAGE_ONE_REG register + * Process control register 1. + */ +#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50) +/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ +#define HMAC_SET_TEXT_ONE (BIT(0)) +#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S) +#define HMAC_SET_TEXT_ONE_V 0x00000001U +#define HMAC_SET_TEXT_ONE_S 0 + +/** HMAC_SET_MESSAGE_ING_REG register + * Process control register 2. + */ +#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54) +/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ +#define HMAC_SET_TEXT_ING (BIT(0)) +#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S) +#define HMAC_SET_TEXT_ING_V 0x00000001U +#define HMAC_SET_TEXT_ING_S 0 + +/** HMAC_SET_MESSAGE_END_REG register + * Process control register 3. + */ +#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58) +/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ +#define HMAC_SET_TEXT_END (BIT(0)) +#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S) +#define HMAC_SET_TEXT_END_V 0x00000001U +#define HMAC_SET_TEXT_END_S 0 + +/** HMAC_SET_RESULT_FINISH_REG register + * Process control register 4. + */ +#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c) +/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ +#define HMAC_SET_RESULT_END (BIT(0)) +#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S) +#define HMAC_SET_RESULT_END_V 0x00000001U +#define HMAC_SET_RESULT_END_S 0 + +/** HMAC_SET_INVALIDATE_JTAG_REG register + * Invalidate register 0. + */ +#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60) +/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ +#define HMAC_SET_INVALIDATE_JTAG (BIT(0)) +#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S) +#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U +#define HMAC_SET_INVALIDATE_JTAG_S 0 + +/** HMAC_SET_INVALIDATE_DS_REG register + * Invalidate register 1. + */ +#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64) +/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ +#define HMAC_SET_INVALIDATE_DS (BIT(0)) +#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S) +#define HMAC_SET_INVALIDATE_DS_V 0x00000001U +#define HMAC_SET_INVALIDATE_DS_S 0 + +/** HMAC_QUERY_ERROR_REG register + * Error register. + */ +#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68) +/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ +#define HMAC_QUREY_CHECK (BIT(0)) +#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S) +#define HMAC_QUREY_CHECK_V 0x00000001U +#define HMAC_QUREY_CHECK_S 0 + +/** HMAC_QUERY_BUSY_REG register + * Busy register. + */ +#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c) +/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ +#define HMAC_BUSY_STATE (BIT(0)) +#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S) +#define HMAC_BUSY_STATE_V 0x00000001U +#define HMAC_BUSY_STATE_S 0 + +/** HMAC_WR_MESSAGE_MEM register + * Message block memory. + */ +#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80) +#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64 + +/** HMAC_RD_RESULT_MEM register + * Result from upstream. + */ +#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0) +#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32 + +/** HMAC_SET_MESSAGE_PAD_REG register + * Process control register 5. + */ +#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0) +/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0; + * Start software padding. + */ +#define HMAC_SET_TEXT_PAD (BIT(0)) +#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S) +#define HMAC_SET_TEXT_PAD_V 0x00000001U +#define HMAC_SET_TEXT_PAD_S 0 + +/** HMAC_ONE_BLOCK_REG register + * Process control register 6. + */ +#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4) +/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ +#define HMAC_SET_ONE_BLOCK (BIT(0)) +#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S) +#define HMAC_SET_ONE_BLOCK_V 0x00000001U +#define HMAC_SET_ONE_BLOCK_S 0 + +/** HMAC_SOFT_JTAG_CTRL_REG register + * Jtag register 0. + */ +#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8) +/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ +#define HMAC_SOFT_JTAG_CTRL (BIT(0)) +#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S) +#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U +#define HMAC_SOFT_JTAG_CTRL_S 0 + +/** HMAC_WR_JTAG_REG register + * Jtag register 1. + */ +#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc) +/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ +#define HMAC_WR_JTAG 0xFFFFFFFFU +#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S) +#define HMAC_WR_JTAG_V 0xFFFFFFFFU +#define HMAC_WR_JTAG_S 0 + +/** HMAC_DATE_REG register + * Date register. + */ +#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc) +/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ +#define HMAC_DATE 0x3FFFFFFFU +#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S) +#define HMAC_DATE_V 0x3FFFFFFFU +#define HMAC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hmac_struct.h b/components/soc/esp32c5/include/soc/hmac_struct.h new file mode 100644 index 00000000000..088c652c51c --- /dev/null +++ b/components/soc/esp32c5/include/soc/hmac_struct.h @@ -0,0 +1,292 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of set_start register + * Process control register 0. + */ +typedef union { + struct { + /** set_start : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_start_reg_t; + +/** Type of set_para_purpose register + * Configure purpose. + */ +typedef union { + struct { + /** purpose_set : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ + uint32_t purpose_set:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} hmac_set_para_purpose_reg_t; + +/** Type of set_para_key register + * Configure key. + */ +typedef union { + struct { + /** key_set : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ + uint32_t key_set:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} hmac_set_para_key_reg_t; + +/** Type of set_para_finish register + * Finish initial configuration. + */ +typedef union { + struct { + /** set_para_end : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ + uint32_t set_para_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_para_finish_reg_t; + +/** Type of set_message_one register + * Process control register 1. + */ +typedef union { + struct { + /** set_text_one : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ + uint32_t set_text_one:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_one_reg_t; + +/** Type of set_message_ing register + * Process control register 2. + */ +typedef union { + struct { + /** set_text_ing : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ + uint32_t set_text_ing:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_ing_reg_t; + +/** Type of set_message_end register + * Process control register 3. + */ +typedef union { + struct { + /** set_text_end : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ + uint32_t set_text_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_end_reg_t; + +/** Type of set_result_finish register + * Process control register 4. + */ +typedef union { + struct { + /** set_result_end : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ + uint32_t set_result_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_result_finish_reg_t; + +/** Type of set_invalidate_jtag register + * Invalidate register 0. + */ +typedef union { + struct { + /** set_invalidate_jtag : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ + uint32_t set_invalidate_jtag:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_jtag_reg_t; + +/** Type of set_invalidate_ds register + * Invalidate register 1. + */ +typedef union { + struct { + /** set_invalidate_ds : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ + uint32_t set_invalidate_ds:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_ds_reg_t; + +/** Type of set_message_pad register + * Process control register 5. + */ +typedef union { + struct { + /** set_text_pad : WO; bitpos: [0]; default: 0; + * Start software padding. + */ + uint32_t set_text_pad:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_pad_reg_t; + +/** Type of one_block register + * Process control register 6. + */ +typedef union { + struct { + /** set_one_block : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ + uint32_t set_one_block:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_one_block_reg_t; + +/** Type of soft_jtag_ctrl register + * Jtag register 0. + */ +typedef union { + struct { + /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ + uint32_t soft_jtag_ctrl:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_soft_jtag_ctrl_reg_t; + +/** Type of wr_jtag register + * Jtag register 1. + */ +typedef union { + struct { + /** wr_jtag : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ + uint32_t wr_jtag:32; + }; + uint32_t val; +} hmac_wr_jtag_reg_t; + + +/** Group: Status Register */ +/** Type of query_error register + * Error register. + */ +typedef union { + struct { + /** qurey_check : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ + uint32_t qurey_check:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_error_reg_t; + +/** Type of query_busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_busy_reg_t; + + +/** Group: Memory Type */ + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} hmac_date_reg_t; + + +typedef struct hmac_dev_t { + uint32_t reserved_000[16]; + volatile hmac_set_start_reg_t set_start; + volatile hmac_set_para_purpose_reg_t set_para_purpose; + volatile hmac_set_para_key_reg_t set_para_key; + volatile hmac_set_para_finish_reg_t set_para_finish; + volatile hmac_set_message_one_reg_t set_message_one; + volatile hmac_set_message_ing_reg_t set_message_ing; + volatile hmac_set_message_end_reg_t set_message_end; + volatile hmac_set_result_finish_reg_t set_result_finish; + volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag; + volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds; + volatile hmac_query_error_reg_t query_error; + volatile hmac_query_busy_reg_t query_busy; + uint32_t reserved_070[4]; + volatile uint32_t wr_message[16]; + volatile uint32_t rd_result[8]; + uint32_t reserved_0e0[4]; + volatile hmac_set_message_pad_reg_t set_message_pad; + volatile hmac_one_block_reg_t one_block; + volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl; + volatile hmac_wr_jtag_reg_t wr_jtag; + uint32_t reserved_100[63]; + volatile hmac_date_reg_t date; +} hmac_dev_t; + +extern hmac_dev_t HMAC; + +#ifndef __cplusplus +_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_apm_reg.h b/components/soc/esp32c5/include/soc/hp_apm_reg.h new file mode 100644 index 00000000000..5779eea6fa0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_apm_reg.h @@ -0,0 +1,1950 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) +/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ +#define HP_APM_REGION_FILTER_EN 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) +#define HP_APM_REGION_FILTER_EN_V 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_S 0 + +/** HP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) +/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) +#define HP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_S 0 + +/** HP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) +/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) +#define HP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_S 0 + +/** HP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) +/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_X (BIT(0)) +#define HP_APM_REGION0_R0_PMS_X_M (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S) +#define HP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_X_S 0 +/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_W (BIT(1)) +#define HP_APM_REGION0_R0_PMS_W_M (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S) +#define HP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_W_S 1 +/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_R (BIT(2)) +#define HP_APM_REGION0_R0_PMS_R_M (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S) +#define HP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_R_S 2 +/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_X (BIT(4)) +#define HP_APM_REGION0_R1_PMS_X_M (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S) +#define HP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_X_S 4 +/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_W (BIT(5)) +#define HP_APM_REGION0_R1_PMS_W_M (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S) +#define HP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_W_S 5 +/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_R (BIT(6)) +#define HP_APM_REGION0_R1_PMS_R_M (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S) +#define HP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_R_S 6 +/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_X (BIT(8)) +#define HP_APM_REGION0_R2_PMS_X_M (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S) +#define HP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_X_S 8 +/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_W (BIT(9)) +#define HP_APM_REGION0_R2_PMS_W_M (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S) +#define HP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_W_S 9 +/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_R (BIT(10)) +#define HP_APM_REGION0_R2_PMS_R_M (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S) +#define HP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_R_S 10 +/** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION0_LOCK (BIT(11)) +#define HP_APM_REGION0_LOCK_M (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S) +#define HP_APM_REGION0_LOCK_V 0x00000001U +#define HP_APM_REGION0_LOCK_S 11 + +/** HP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) +/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) +#define HP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_S 0 + +/** HP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) +/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) +#define HP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_S 0 + +/** HP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) +/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_X (BIT(0)) +#define HP_APM_REGION1_R0_PMS_X_M (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S) +#define HP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_X_S 0 +/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_W (BIT(1)) +#define HP_APM_REGION1_R0_PMS_W_M (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S) +#define HP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_W_S 1 +/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_R (BIT(2)) +#define HP_APM_REGION1_R0_PMS_R_M (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S) +#define HP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_R_S 2 +/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_X (BIT(4)) +#define HP_APM_REGION1_R1_PMS_X_M (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S) +#define HP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_X_S 4 +/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_W (BIT(5)) +#define HP_APM_REGION1_R1_PMS_W_M (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S) +#define HP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_W_S 5 +/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_R (BIT(6)) +#define HP_APM_REGION1_R1_PMS_R_M (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S) +#define HP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_R_S 6 +/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_X (BIT(8)) +#define HP_APM_REGION1_R2_PMS_X_M (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S) +#define HP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_X_S 8 +/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_W (BIT(9)) +#define HP_APM_REGION1_R2_PMS_W_M (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S) +#define HP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_W_S 9 +/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_R (BIT(10)) +#define HP_APM_REGION1_R2_PMS_R_M (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S) +#define HP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_R_S 10 +/** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ +#define HP_APM_REGION1_LOCK (BIT(11)) +#define HP_APM_REGION1_LOCK_M (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S) +#define HP_APM_REGION1_LOCK_V 0x00000001U +#define HP_APM_REGION1_LOCK_S 11 + +/** HP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) +/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) +#define HP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_S 0 + +/** HP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) +/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) +#define HP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_S 0 + +/** HP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) +/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_X (BIT(0)) +#define HP_APM_REGION2_R0_PMS_X_M (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S) +#define HP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_X_S 0 +/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_W (BIT(1)) +#define HP_APM_REGION2_R0_PMS_W_M (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S) +#define HP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_W_S 1 +/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_R (BIT(2)) +#define HP_APM_REGION2_R0_PMS_R_M (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S) +#define HP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_R_S 2 +/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_X (BIT(4)) +#define HP_APM_REGION2_R1_PMS_X_M (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S) +#define HP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_X_S 4 +/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_W (BIT(5)) +#define HP_APM_REGION2_R1_PMS_W_M (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S) +#define HP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_W_S 5 +/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_R (BIT(6)) +#define HP_APM_REGION2_R1_PMS_R_M (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S) +#define HP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_R_S 6 +/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_X (BIT(8)) +#define HP_APM_REGION2_R2_PMS_X_M (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S) +#define HP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_X_S 8 +/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_W (BIT(9)) +#define HP_APM_REGION2_R2_PMS_W_M (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S) +#define HP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_W_S 9 +/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_R (BIT(10)) +#define HP_APM_REGION2_R2_PMS_R_M (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S) +#define HP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_R_S 10 +/** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ +#define HP_APM_REGION2_LOCK (BIT(11)) +#define HP_APM_REGION2_LOCK_M (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S) +#define HP_APM_REGION2_LOCK_V 0x00000001U +#define HP_APM_REGION2_LOCK_S 11 + +/** HP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) +/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) +#define HP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_S 0 + +/** HP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) +/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) +#define HP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_S 0 + +/** HP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) +/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_X (BIT(0)) +#define HP_APM_REGION3_R0_PMS_X_M (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S) +#define HP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_X_S 0 +/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_W (BIT(1)) +#define HP_APM_REGION3_R0_PMS_W_M (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S) +#define HP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_W_S 1 +/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_R (BIT(2)) +#define HP_APM_REGION3_R0_PMS_R_M (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S) +#define HP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_R_S 2 +/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_X (BIT(4)) +#define HP_APM_REGION3_R1_PMS_X_M (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S) +#define HP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_X_S 4 +/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_W (BIT(5)) +#define HP_APM_REGION3_R1_PMS_W_M (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S) +#define HP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_W_S 5 +/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_R (BIT(6)) +#define HP_APM_REGION3_R1_PMS_R_M (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S) +#define HP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_R_S 6 +/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_X (BIT(8)) +#define HP_APM_REGION3_R2_PMS_X_M (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S) +#define HP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_X_S 8 +/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_W (BIT(9)) +#define HP_APM_REGION3_R2_PMS_W_M (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S) +#define HP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_W_S 9 +/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_R (BIT(10)) +#define HP_APM_REGION3_R2_PMS_R_M (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S) +#define HP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_R_S 10 +/** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ +#define HP_APM_REGION3_LOCK (BIT(11)) +#define HP_APM_REGION3_LOCK_M (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S) +#define HP_APM_REGION3_LOCK_V 0x00000001U +#define HP_APM_REGION3_LOCK_S 11 + +/** HP_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) +/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ +#define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) +#define HP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_S 0 + +/** HP_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) +/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ +#define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) +#define HP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_S 0 + +/** HP_APM_REGION4_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) +/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_X (BIT(0)) +#define HP_APM_REGION4_R0_PMS_X_M (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S) +#define HP_APM_REGION4_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_X_S 0 +/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_W (BIT(1)) +#define HP_APM_REGION4_R0_PMS_W_M (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S) +#define HP_APM_REGION4_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_W_S 1 +/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_R (BIT(2)) +#define HP_APM_REGION4_R0_PMS_R_M (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S) +#define HP_APM_REGION4_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_R_S 2 +/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_X (BIT(4)) +#define HP_APM_REGION4_R1_PMS_X_M (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S) +#define HP_APM_REGION4_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_X_S 4 +/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_W (BIT(5)) +#define HP_APM_REGION4_R1_PMS_W_M (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S) +#define HP_APM_REGION4_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_W_S 5 +/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_R (BIT(6)) +#define HP_APM_REGION4_R1_PMS_R_M (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S) +#define HP_APM_REGION4_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_R_S 6 +/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_X (BIT(8)) +#define HP_APM_REGION4_R2_PMS_X_M (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S) +#define HP_APM_REGION4_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_X_S 8 +/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_W (BIT(9)) +#define HP_APM_REGION4_R2_PMS_W_M (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S) +#define HP_APM_REGION4_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_W_S 9 +/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_R (BIT(10)) +#define HP_APM_REGION4_R2_PMS_R_M (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S) +#define HP_APM_REGION4_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_R_S 10 +/** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region4 configuration + */ +#define HP_APM_REGION4_LOCK (BIT(11)) +#define HP_APM_REGION4_LOCK_M (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S) +#define HP_APM_REGION4_LOCK_V 0x00000001U +#define HP_APM_REGION4_LOCK_S 11 + +/** HP_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) +/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ +#define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) +#define HP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_S 0 + +/** HP_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) +/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ +#define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) +#define HP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_S 0 + +/** HP_APM_REGION5_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) +/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_X (BIT(0)) +#define HP_APM_REGION5_R0_PMS_X_M (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S) +#define HP_APM_REGION5_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_X_S 0 +/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_W (BIT(1)) +#define HP_APM_REGION5_R0_PMS_W_M (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S) +#define HP_APM_REGION5_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_W_S 1 +/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_R (BIT(2)) +#define HP_APM_REGION5_R0_PMS_R_M (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S) +#define HP_APM_REGION5_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_R_S 2 +/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_X (BIT(4)) +#define HP_APM_REGION5_R1_PMS_X_M (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S) +#define HP_APM_REGION5_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_X_S 4 +/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_W (BIT(5)) +#define HP_APM_REGION5_R1_PMS_W_M (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S) +#define HP_APM_REGION5_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_W_S 5 +/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_R (BIT(6)) +#define HP_APM_REGION5_R1_PMS_R_M (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S) +#define HP_APM_REGION5_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_R_S 6 +/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_X (BIT(8)) +#define HP_APM_REGION5_R2_PMS_X_M (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S) +#define HP_APM_REGION5_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_X_S 8 +/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_W (BIT(9)) +#define HP_APM_REGION5_R2_PMS_W_M (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S) +#define HP_APM_REGION5_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_W_S 9 +/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_R (BIT(10)) +#define HP_APM_REGION5_R2_PMS_R_M (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S) +#define HP_APM_REGION5_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_R_S 10 +/** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region5 configuration + */ +#define HP_APM_REGION5_LOCK (BIT(11)) +#define HP_APM_REGION5_LOCK_M (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S) +#define HP_APM_REGION5_LOCK_V 0x00000001U +#define HP_APM_REGION5_LOCK_S 11 + +/** HP_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) +/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ +#define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) +#define HP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_S 0 + +/** HP_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) +/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ +#define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) +#define HP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_S 0 + +/** HP_APM_REGION6_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) +/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_X (BIT(0)) +#define HP_APM_REGION6_R0_PMS_X_M (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S) +#define HP_APM_REGION6_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_X_S 0 +/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_W (BIT(1)) +#define HP_APM_REGION6_R0_PMS_W_M (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S) +#define HP_APM_REGION6_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_W_S 1 +/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_R (BIT(2)) +#define HP_APM_REGION6_R0_PMS_R_M (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S) +#define HP_APM_REGION6_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_R_S 2 +/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_X (BIT(4)) +#define HP_APM_REGION6_R1_PMS_X_M (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S) +#define HP_APM_REGION6_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_X_S 4 +/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_W (BIT(5)) +#define HP_APM_REGION6_R1_PMS_W_M (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S) +#define HP_APM_REGION6_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_W_S 5 +/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_R (BIT(6)) +#define HP_APM_REGION6_R1_PMS_R_M (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S) +#define HP_APM_REGION6_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_R_S 6 +/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_X (BIT(8)) +#define HP_APM_REGION6_R2_PMS_X_M (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S) +#define HP_APM_REGION6_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_X_S 8 +/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_W (BIT(9)) +#define HP_APM_REGION6_R2_PMS_W_M (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S) +#define HP_APM_REGION6_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_W_S 9 +/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_R (BIT(10)) +#define HP_APM_REGION6_R2_PMS_R_M (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S) +#define HP_APM_REGION6_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_R_S 10 +/** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region6 configuration + */ +#define HP_APM_REGION6_LOCK (BIT(11)) +#define HP_APM_REGION6_LOCK_M (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S) +#define HP_APM_REGION6_LOCK_V 0x00000001U +#define HP_APM_REGION6_LOCK_S 11 + +/** HP_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) +/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ +#define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) +#define HP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_S 0 + +/** HP_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) +/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ +#define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) +#define HP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_S 0 + +/** HP_APM_REGION7_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) +/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_X (BIT(0)) +#define HP_APM_REGION7_R0_PMS_X_M (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S) +#define HP_APM_REGION7_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_X_S 0 +/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_W (BIT(1)) +#define HP_APM_REGION7_R0_PMS_W_M (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S) +#define HP_APM_REGION7_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_W_S 1 +/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_R (BIT(2)) +#define HP_APM_REGION7_R0_PMS_R_M (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S) +#define HP_APM_REGION7_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_R_S 2 +/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_X (BIT(4)) +#define HP_APM_REGION7_R1_PMS_X_M (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S) +#define HP_APM_REGION7_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_X_S 4 +/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_W (BIT(5)) +#define HP_APM_REGION7_R1_PMS_W_M (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S) +#define HP_APM_REGION7_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_W_S 5 +/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_R (BIT(6)) +#define HP_APM_REGION7_R1_PMS_R_M (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S) +#define HP_APM_REGION7_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_R_S 6 +/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_X (BIT(8)) +#define HP_APM_REGION7_R2_PMS_X_M (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S) +#define HP_APM_REGION7_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_X_S 8 +/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_W (BIT(9)) +#define HP_APM_REGION7_R2_PMS_W_M (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S) +#define HP_APM_REGION7_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_W_S 9 +/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_R (BIT(10)) +#define HP_APM_REGION7_R2_PMS_R_M (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S) +#define HP_APM_REGION7_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_R_S 10 +/** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region7 configuration + */ +#define HP_APM_REGION7_LOCK (BIT(11)) +#define HP_APM_REGION7_LOCK_M (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S) +#define HP_APM_REGION7_LOCK_V 0x00000001U +#define HP_APM_REGION7_LOCK_S 11 + +/** HP_APM_REGION8_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) +/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ +#define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) +#define HP_APM_REGION8_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_S 0 + +/** HP_APM_REGION8_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) +/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ +#define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) +#define HP_APM_REGION8_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_S 0 + +/** HP_APM_REGION8_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) +/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_X (BIT(0)) +#define HP_APM_REGION8_R0_PMS_X_M (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S) +#define HP_APM_REGION8_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_X_S 0 +/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_W (BIT(1)) +#define HP_APM_REGION8_R0_PMS_W_M (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S) +#define HP_APM_REGION8_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_W_S 1 +/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_R (BIT(2)) +#define HP_APM_REGION8_R0_PMS_R_M (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S) +#define HP_APM_REGION8_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_R_S 2 +/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_X (BIT(4)) +#define HP_APM_REGION8_R1_PMS_X_M (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S) +#define HP_APM_REGION8_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_X_S 4 +/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_W (BIT(5)) +#define HP_APM_REGION8_R1_PMS_W_M (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S) +#define HP_APM_REGION8_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_W_S 5 +/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_R (BIT(6)) +#define HP_APM_REGION8_R1_PMS_R_M (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S) +#define HP_APM_REGION8_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_R_S 6 +/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_X (BIT(8)) +#define HP_APM_REGION8_R2_PMS_X_M (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S) +#define HP_APM_REGION8_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_X_S 8 +/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_W (BIT(9)) +#define HP_APM_REGION8_R2_PMS_W_M (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S) +#define HP_APM_REGION8_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_W_S 9 +/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_R (BIT(10)) +#define HP_APM_REGION8_R2_PMS_R_M (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S) +#define HP_APM_REGION8_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_R_S 10 +/** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region8 configuration + */ +#define HP_APM_REGION8_LOCK (BIT(11)) +#define HP_APM_REGION8_LOCK_M (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S) +#define HP_APM_REGION8_LOCK_V 0x00000001U +#define HP_APM_REGION8_LOCK_S 11 + +/** HP_APM_REGION9_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) +/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ +#define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) +#define HP_APM_REGION9_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_S 0 + +/** HP_APM_REGION9_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) +/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ +#define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) +#define HP_APM_REGION9_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_S 0 + +/** HP_APM_REGION9_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) +/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_X (BIT(0)) +#define HP_APM_REGION9_R0_PMS_X_M (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S) +#define HP_APM_REGION9_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_X_S 0 +/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_W (BIT(1)) +#define HP_APM_REGION9_R0_PMS_W_M (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S) +#define HP_APM_REGION9_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_W_S 1 +/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_R (BIT(2)) +#define HP_APM_REGION9_R0_PMS_R_M (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S) +#define HP_APM_REGION9_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_R_S 2 +/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_X (BIT(4)) +#define HP_APM_REGION9_R1_PMS_X_M (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S) +#define HP_APM_REGION9_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_X_S 4 +/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_W (BIT(5)) +#define HP_APM_REGION9_R1_PMS_W_M (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S) +#define HP_APM_REGION9_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_W_S 5 +/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_R (BIT(6)) +#define HP_APM_REGION9_R1_PMS_R_M (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S) +#define HP_APM_REGION9_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_R_S 6 +/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_X (BIT(8)) +#define HP_APM_REGION9_R2_PMS_X_M (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S) +#define HP_APM_REGION9_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_X_S 8 +/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_W (BIT(9)) +#define HP_APM_REGION9_R2_PMS_W_M (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S) +#define HP_APM_REGION9_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_W_S 9 +/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_R (BIT(10)) +#define HP_APM_REGION9_R2_PMS_R_M (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S) +#define HP_APM_REGION9_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_R_S 10 +/** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region9 configuration + */ +#define HP_APM_REGION9_LOCK (BIT(11)) +#define HP_APM_REGION9_LOCK_M (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S) +#define HP_APM_REGION9_LOCK_V 0x00000001U +#define HP_APM_REGION9_LOCK_S 11 + +/** HP_APM_REGION10_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) +/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ +#define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) +#define HP_APM_REGION10_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_S 0 + +/** HP_APM_REGION10_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) +/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ +#define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) +#define HP_APM_REGION10_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_S 0 + +/** HP_APM_REGION10_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) +/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_X (BIT(0)) +#define HP_APM_REGION10_R0_PMS_X_M (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S) +#define HP_APM_REGION10_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_X_S 0 +/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_W (BIT(1)) +#define HP_APM_REGION10_R0_PMS_W_M (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S) +#define HP_APM_REGION10_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_W_S 1 +/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_R (BIT(2)) +#define HP_APM_REGION10_R0_PMS_R_M (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S) +#define HP_APM_REGION10_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_R_S 2 +/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_X (BIT(4)) +#define HP_APM_REGION10_R1_PMS_X_M (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S) +#define HP_APM_REGION10_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_X_S 4 +/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_W (BIT(5)) +#define HP_APM_REGION10_R1_PMS_W_M (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S) +#define HP_APM_REGION10_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_W_S 5 +/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_R (BIT(6)) +#define HP_APM_REGION10_R1_PMS_R_M (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S) +#define HP_APM_REGION10_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_R_S 6 +/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_X (BIT(8)) +#define HP_APM_REGION10_R2_PMS_X_M (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S) +#define HP_APM_REGION10_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_X_S 8 +/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_W (BIT(9)) +#define HP_APM_REGION10_R2_PMS_W_M (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S) +#define HP_APM_REGION10_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_W_S 9 +/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_R (BIT(10)) +#define HP_APM_REGION10_R2_PMS_R_M (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S) +#define HP_APM_REGION10_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_R_S 10 +/** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region10 configuration + */ +#define HP_APM_REGION10_LOCK (BIT(11)) +#define HP_APM_REGION10_LOCK_M (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S) +#define HP_APM_REGION10_LOCK_V 0x00000001U +#define HP_APM_REGION10_LOCK_S 11 + +/** HP_APM_REGION11_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) +/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ +#define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) +#define HP_APM_REGION11_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_S 0 + +/** HP_APM_REGION11_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) +/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ +#define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) +#define HP_APM_REGION11_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_S 0 + +/** HP_APM_REGION11_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) +/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_X (BIT(0)) +#define HP_APM_REGION11_R0_PMS_X_M (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S) +#define HP_APM_REGION11_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_X_S 0 +/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_W (BIT(1)) +#define HP_APM_REGION11_R0_PMS_W_M (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S) +#define HP_APM_REGION11_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_W_S 1 +/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_R (BIT(2)) +#define HP_APM_REGION11_R0_PMS_R_M (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S) +#define HP_APM_REGION11_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_R_S 2 +/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_X (BIT(4)) +#define HP_APM_REGION11_R1_PMS_X_M (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S) +#define HP_APM_REGION11_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_X_S 4 +/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_W (BIT(5)) +#define HP_APM_REGION11_R1_PMS_W_M (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S) +#define HP_APM_REGION11_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_W_S 5 +/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_R (BIT(6)) +#define HP_APM_REGION11_R1_PMS_R_M (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S) +#define HP_APM_REGION11_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_R_S 6 +/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_X (BIT(8)) +#define HP_APM_REGION11_R2_PMS_X_M (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S) +#define HP_APM_REGION11_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_X_S 8 +/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_W (BIT(9)) +#define HP_APM_REGION11_R2_PMS_W_M (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S) +#define HP_APM_REGION11_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_W_S 9 +/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_R (BIT(10)) +#define HP_APM_REGION11_R2_PMS_R_M (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S) +#define HP_APM_REGION11_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_R_S 10 +/** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region11 configuration + */ +#define HP_APM_REGION11_LOCK (BIT(11)) +#define HP_APM_REGION11_LOCK_M (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S) +#define HP_APM_REGION11_LOCK_V 0x00000001U +#define HP_APM_REGION11_LOCK_S 11 + +/** HP_APM_REGION12_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) +/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ +#define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) +#define HP_APM_REGION12_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_S 0 + +/** HP_APM_REGION12_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) +/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ +#define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) +#define HP_APM_REGION12_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_S 0 + +/** HP_APM_REGION12_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) +/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_X (BIT(0)) +#define HP_APM_REGION12_R0_PMS_X_M (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S) +#define HP_APM_REGION12_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_X_S 0 +/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_W (BIT(1)) +#define HP_APM_REGION12_R0_PMS_W_M (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S) +#define HP_APM_REGION12_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_W_S 1 +/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_R (BIT(2)) +#define HP_APM_REGION12_R0_PMS_R_M (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S) +#define HP_APM_REGION12_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_R_S 2 +/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_X (BIT(4)) +#define HP_APM_REGION12_R1_PMS_X_M (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S) +#define HP_APM_REGION12_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_X_S 4 +/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_W (BIT(5)) +#define HP_APM_REGION12_R1_PMS_W_M (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S) +#define HP_APM_REGION12_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_W_S 5 +/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_R (BIT(6)) +#define HP_APM_REGION12_R1_PMS_R_M (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S) +#define HP_APM_REGION12_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_R_S 6 +/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_X (BIT(8)) +#define HP_APM_REGION12_R2_PMS_X_M (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S) +#define HP_APM_REGION12_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_X_S 8 +/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_W (BIT(9)) +#define HP_APM_REGION12_R2_PMS_W_M (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S) +#define HP_APM_REGION12_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_W_S 9 +/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_R (BIT(10)) +#define HP_APM_REGION12_R2_PMS_R_M (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S) +#define HP_APM_REGION12_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_R_S 10 +/** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region12 configuration + */ +#define HP_APM_REGION12_LOCK (BIT(11)) +#define HP_APM_REGION12_LOCK_M (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S) +#define HP_APM_REGION12_LOCK_V 0x00000001U +#define HP_APM_REGION12_LOCK_S 11 + +/** HP_APM_REGION13_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) +/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ +#define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) +#define HP_APM_REGION13_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_S 0 + +/** HP_APM_REGION13_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) +/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ +#define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) +#define HP_APM_REGION13_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_S 0 + +/** HP_APM_REGION13_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) +/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_X (BIT(0)) +#define HP_APM_REGION13_R0_PMS_X_M (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S) +#define HP_APM_REGION13_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_X_S 0 +/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_W (BIT(1)) +#define HP_APM_REGION13_R0_PMS_W_M (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S) +#define HP_APM_REGION13_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_W_S 1 +/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_R (BIT(2)) +#define HP_APM_REGION13_R0_PMS_R_M (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S) +#define HP_APM_REGION13_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_R_S 2 +/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_X (BIT(4)) +#define HP_APM_REGION13_R1_PMS_X_M (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S) +#define HP_APM_REGION13_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_X_S 4 +/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_W (BIT(5)) +#define HP_APM_REGION13_R1_PMS_W_M (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S) +#define HP_APM_REGION13_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_W_S 5 +/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_R (BIT(6)) +#define HP_APM_REGION13_R1_PMS_R_M (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S) +#define HP_APM_REGION13_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_R_S 6 +/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_X (BIT(8)) +#define HP_APM_REGION13_R2_PMS_X_M (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S) +#define HP_APM_REGION13_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_X_S 8 +/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_W (BIT(9)) +#define HP_APM_REGION13_R2_PMS_W_M (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S) +#define HP_APM_REGION13_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_W_S 9 +/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_R (BIT(10)) +#define HP_APM_REGION13_R2_PMS_R_M (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S) +#define HP_APM_REGION13_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_R_S 10 +/** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region13 configuration + */ +#define HP_APM_REGION13_LOCK (BIT(11)) +#define HP_APM_REGION13_LOCK_M (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S) +#define HP_APM_REGION13_LOCK_V 0x00000001U +#define HP_APM_REGION13_LOCK_S 11 + +/** HP_APM_REGION14_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) +/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ +#define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) +#define HP_APM_REGION14_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_S 0 + +/** HP_APM_REGION14_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) +/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ +#define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) +#define HP_APM_REGION14_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_S 0 + +/** HP_APM_REGION14_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) +/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_X (BIT(0)) +#define HP_APM_REGION14_R0_PMS_X_M (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S) +#define HP_APM_REGION14_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_X_S 0 +/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_W (BIT(1)) +#define HP_APM_REGION14_R0_PMS_W_M (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S) +#define HP_APM_REGION14_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_W_S 1 +/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_R (BIT(2)) +#define HP_APM_REGION14_R0_PMS_R_M (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S) +#define HP_APM_REGION14_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_R_S 2 +/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_X (BIT(4)) +#define HP_APM_REGION14_R1_PMS_X_M (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S) +#define HP_APM_REGION14_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_X_S 4 +/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_W (BIT(5)) +#define HP_APM_REGION14_R1_PMS_W_M (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S) +#define HP_APM_REGION14_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_W_S 5 +/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_R (BIT(6)) +#define HP_APM_REGION14_R1_PMS_R_M (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S) +#define HP_APM_REGION14_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_R_S 6 +/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_X (BIT(8)) +#define HP_APM_REGION14_R2_PMS_X_M (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S) +#define HP_APM_REGION14_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_X_S 8 +/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_W (BIT(9)) +#define HP_APM_REGION14_R2_PMS_W_M (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S) +#define HP_APM_REGION14_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_W_S 9 +/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_R (BIT(10)) +#define HP_APM_REGION14_R2_PMS_R_M (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S) +#define HP_APM_REGION14_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_R_S 10 +/** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region14 configuration + */ +#define HP_APM_REGION14_LOCK (BIT(11)) +#define HP_APM_REGION14_LOCK_M (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S) +#define HP_APM_REGION14_LOCK_V 0x00000001U +#define HP_APM_REGION14_LOCK_S 11 + +/** HP_APM_REGION15_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) +/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ +#define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) +#define HP_APM_REGION15_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_S 0 + +/** HP_APM_REGION15_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) +/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ +#define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) +#define HP_APM_REGION15_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_S 0 + +/** HP_APM_REGION15_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) +/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_X (BIT(0)) +#define HP_APM_REGION15_R0_PMS_X_M (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S) +#define HP_APM_REGION15_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_X_S 0 +/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_W (BIT(1)) +#define HP_APM_REGION15_R0_PMS_W_M (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S) +#define HP_APM_REGION15_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_W_S 1 +/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_R (BIT(2)) +#define HP_APM_REGION15_R0_PMS_R_M (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S) +#define HP_APM_REGION15_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_R_S 2 +/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_X (BIT(4)) +#define HP_APM_REGION15_R1_PMS_X_M (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S) +#define HP_APM_REGION15_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_X_S 4 +/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_W (BIT(5)) +#define HP_APM_REGION15_R1_PMS_W_M (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S) +#define HP_APM_REGION15_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_W_S 5 +/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_R (BIT(6)) +#define HP_APM_REGION15_R1_PMS_R_M (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S) +#define HP_APM_REGION15_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_R_S 6 +/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_X (BIT(8)) +#define HP_APM_REGION15_R2_PMS_X_M (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S) +#define HP_APM_REGION15_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_X_S 8 +/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_W (BIT(9)) +#define HP_APM_REGION15_R2_PMS_W_M (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S) +#define HP_APM_REGION15_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_W_S 9 +/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_R (BIT(10)) +#define HP_APM_REGION15_R2_PMS_R_M (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S) +#define HP_APM_REGION15_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_R_S 10 +/** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region15 configuration + */ +#define HP_APM_REGION15_LOCK (BIT(11)) +#define HP_APM_REGION15_LOCK_M (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S) +#define HP_APM_REGION15_LOCK_V 0x00000001U +#define HP_APM_REGION15_LOCK_S 11 + +/** HP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) +/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define HP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define HP_APM_M0_PMS_FUNC_EN_M (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S) +#define HP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M0_PMS_FUNC_EN_S 0 +/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define HP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define HP_APM_M1_PMS_FUNC_EN_M (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S) +#define HP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M1_PMS_FUNC_EN_S 1 +/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define HP_APM_M2_PMS_FUNC_EN (BIT(2)) +#define HP_APM_M2_PMS_FUNC_EN_M (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S) +#define HP_APM_M2_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M2_PMS_FUNC_EN_S 2 +/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define HP_APM_M3_PMS_FUNC_EN (BIT(3)) +#define HP_APM_M3_PMS_FUNC_EN_M (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S) +#define HP_APM_M3_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M3_PMS_FUNC_EN_S 3 + +/** HP_APM_M0_STATUS_REG register + * M0 status register + */ +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) +/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) +#define HP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_S 0 + +/** HP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) +/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M0_REGION_STATUS_CLR_M (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S) +#define HP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M0_REGION_STATUS_CLR_S 0 + +/** HP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) +/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) +#define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_S 0 +/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M0_EXCEPTION_MODE 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) +#define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_S 16 +/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M0_EXCEPTION_ID 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) +#define HP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_S 18 + +/** HP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) +/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) +#define HP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_S 0 + +/** HP_APM_M1_STATUS_REG register + * M1 status register + */ +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) +/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) +#define HP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_S 0 + +/** HP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) +/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M1_REGION_STATUS_CLR_M (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S) +#define HP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M1_REGION_STATUS_CLR_S 0 + +/** HP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) +/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) +#define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_S 0 +/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M1_EXCEPTION_MODE 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) +#define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_S 16 +/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M1_EXCEPTION_ID 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) +#define HP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_S 18 + +/** HP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) +/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) +#define HP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_S 0 + +/** HP_APM_M2_STATUS_REG register + * M2 status register + */ +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) +/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M2_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) +#define HP_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_S 0 + +/** HP_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) +/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M2_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M2_REGION_STATUS_CLR_M (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S) +#define HP_APM_M2_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M2_REGION_STATUS_CLR_S 0 + +/** HP_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) +/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) +#define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_S 0 +/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M2_EXCEPTION_MODE 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) +#define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_S 16 +/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M2_EXCEPTION_ID 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) +#define HP_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_S 18 + +/** HP_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) +/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) +#define HP_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_S 0 + +/** HP_APM_M3_STATUS_REG register + * M3 status register + */ +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) +/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M3_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) +#define HP_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_S 0 + +/** HP_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) +/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M3_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M3_REGION_STATUS_CLR_M (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S) +#define HP_APM_M3_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M3_REGION_STATUS_CLR_S 0 + +/** HP_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) +/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) +#define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_S 0 +/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M3_EXCEPTION_MODE 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) +#define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_S 16 +/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M3_EXCEPTION_ID 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) +#define HP_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_S 18 + +/** HP_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) +/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) +#define HP_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_S 0 + +/** HP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) +/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define HP_APM_M0_APM_INT_EN (BIT(0)) +#define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) +#define HP_APM_M0_APM_INT_EN_V 0x00000001U +#define HP_APM_M0_APM_INT_EN_S 0 +/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define HP_APM_M1_APM_INT_EN (BIT(1)) +#define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) +#define HP_APM_M1_APM_INT_EN_V 0x00000001U +#define HP_APM_M1_APM_INT_EN_S 1 +/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ +#define HP_APM_M2_APM_INT_EN (BIT(2)) +#define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) +#define HP_APM_M2_APM_INT_EN_V 0x00000001U +#define HP_APM_M2_APM_INT_EN_S 2 +/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ +#define HP_APM_M3_APM_INT_EN (BIT(3)) +#define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) +#define HP_APM_M3_APM_INT_EN_V 0x00000001U +#define HP_APM_M3_APM_INT_EN_S 3 + +/** HP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c) +/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define HP_APM_CLK_EN (BIT(0)) +#define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) +#define HP_APM_CLK_EN_V 0x00000001U +#define HP_APM_CLK_EN_S 0 + +/** HP_APM_DATE_REG register + * Version register + */ +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) +/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ +#define HP_APM_DATE 0x0FFFFFFFU +#define HP_APM_DATE_M (HP_APM_DATE_V << HP_APM_DATE_S) +#define HP_APM_DATE_V 0x0FFFFFFFU +#define HP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_apm_struct.h b/components/soc/esp32c5/include/soc/hp_apm_struct.h new file mode 100644 index 00000000000..04c89c8a5ee --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_apm_struct.h @@ -0,0 +1,1734 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} hp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} hp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} hp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} hp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} hp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} hp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} hp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} hp_apm_region3_addr_end_reg_t; + +/** Type of region4_addr_start register + * Region address register + */ +typedef union { + struct { + /** region4_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ + uint32_t region4_addr_start:32; + }; + uint32_t val; +} hp_apm_region4_addr_start_reg_t; + +/** Type of region4_addr_end register + * Region address register + */ +typedef union { + struct { + /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ + uint32_t region4_addr_end:32; + }; + uint32_t val; +} hp_apm_region4_addr_end_reg_t; + +/** Type of region5_addr_start register + * Region address register + */ +typedef union { + struct { + /** region5_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ + uint32_t region5_addr_start:32; + }; + uint32_t val; +} hp_apm_region5_addr_start_reg_t; + +/** Type of region5_addr_end register + * Region address register + */ +typedef union { + struct { + /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ + uint32_t region5_addr_end:32; + }; + uint32_t val; +} hp_apm_region5_addr_end_reg_t; + +/** Type of region6_addr_start register + * Region address register + */ +typedef union { + struct { + /** region6_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ + uint32_t region6_addr_start:32; + }; + uint32_t val; +} hp_apm_region6_addr_start_reg_t; + +/** Type of region6_addr_end register + * Region address register + */ +typedef union { + struct { + /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ + uint32_t region6_addr_end:32; + }; + uint32_t val; +} hp_apm_region6_addr_end_reg_t; + +/** Type of region7_addr_start register + * Region address register + */ +typedef union { + struct { + /** region7_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ + uint32_t region7_addr_start:32; + }; + uint32_t val; +} hp_apm_region7_addr_start_reg_t; + +/** Type of region7_addr_end register + * Region address register + */ +typedef union { + struct { + /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ + uint32_t region7_addr_end:32; + }; + uint32_t val; +} hp_apm_region7_addr_end_reg_t; + +/** Type of region8_addr_start register + * Region address register + */ +typedef union { + struct { + /** region8_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ + uint32_t region8_addr_start:32; + }; + uint32_t val; +} hp_apm_region8_addr_start_reg_t; + +/** Type of region8_addr_end register + * Region address register + */ +typedef union { + struct { + /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ + uint32_t region8_addr_end:32; + }; + uint32_t val; +} hp_apm_region8_addr_end_reg_t; + +/** Type of region9_addr_start register + * Region address register + */ +typedef union { + struct { + /** region9_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ + uint32_t region9_addr_start:32; + }; + uint32_t val; +} hp_apm_region9_addr_start_reg_t; + +/** Type of region9_addr_end register + * Region address register + */ +typedef union { + struct { + /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ + uint32_t region9_addr_end:32; + }; + uint32_t val; +} hp_apm_region9_addr_end_reg_t; + +/** Type of region10_addr_start register + * Region address register + */ +typedef union { + struct { + /** region10_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ + uint32_t region10_addr_start:32; + }; + uint32_t val; +} hp_apm_region10_addr_start_reg_t; + +/** Type of region10_addr_end register + * Region address register + */ +typedef union { + struct { + /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ + uint32_t region10_addr_end:32; + }; + uint32_t val; +} hp_apm_region10_addr_end_reg_t; + +/** Type of region11_addr_start register + * Region address register + */ +typedef union { + struct { + /** region11_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ + uint32_t region11_addr_start:32; + }; + uint32_t val; +} hp_apm_region11_addr_start_reg_t; + +/** Type of region11_addr_end register + * Region address register + */ +typedef union { + struct { + /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ + uint32_t region11_addr_end:32; + }; + uint32_t val; +} hp_apm_region11_addr_end_reg_t; + +/** Type of region12_addr_start register + * Region address register + */ +typedef union { + struct { + /** region12_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ + uint32_t region12_addr_start:32; + }; + uint32_t val; +} hp_apm_region12_addr_start_reg_t; + +/** Type of region12_addr_end register + * Region address register + */ +typedef union { + struct { + /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ + uint32_t region12_addr_end:32; + }; + uint32_t val; +} hp_apm_region12_addr_end_reg_t; + +/** Type of region13_addr_start register + * Region address register + */ +typedef union { + struct { + /** region13_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ + uint32_t region13_addr_start:32; + }; + uint32_t val; +} hp_apm_region13_addr_start_reg_t; + +/** Type of region13_addr_end register + * Region address register + */ +typedef union { + struct { + /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ + uint32_t region13_addr_end:32; + }; + uint32_t val; +} hp_apm_region13_addr_end_reg_t; + +/** Type of region14_addr_start register + * Region address register + */ +typedef union { + struct { + /** region14_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ + uint32_t region14_addr_start:32; + }; + uint32_t val; +} hp_apm_region14_addr_start_reg_t; + +/** Type of region14_addr_end register + * Region address register + */ +typedef union { + struct { + /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ + uint32_t region14_addr_end:32; + }; + uint32_t val; +} hp_apm_region14_addr_end_reg_t; + +/** Type of region15_addr_start register + * Region address register + */ +typedef union { + struct { + /** region15_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ + uint32_t region15_addr_start:32; + }; + uint32_t val; +} hp_apm_region15_addr_start_reg_t; + +/** Type of region15_addr_end register + * Region address register + */ +typedef union { + struct { + /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ + uint32_t region15_addr_end:32; + }; + uint32_t val; +} hp_apm_region15_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + /** region0_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t region0_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + /** region1_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ + uint32_t region1_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + /** region2_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ + uint32_t region2_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + /** region3_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ + uint32_t region3_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region3_pms_attr_reg_t; + +/** Type of region4_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region4_r0_pms_x:1; + /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region4_r0_pms_w:1; + /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region4_r0_pms_r:1; + uint32_t reserved_3:1; + /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region4_r1_pms_x:1; + /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region4_r1_pms_w:1; + /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region4_r1_pms_r:1; + uint32_t reserved_7:1; + /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region4_r2_pms_x:1; + /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region4_r2_pms_w:1; + /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region4_r2_pms_r:1; + /** region4_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region4 configuration + */ + uint32_t region4_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region4_pms_attr_reg_t; + +/** Type of region5_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region5_r0_pms_x:1; + /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region5_r0_pms_w:1; + /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region5_r0_pms_r:1; + uint32_t reserved_3:1; + /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region5_r1_pms_x:1; + /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region5_r1_pms_w:1; + /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region5_r1_pms_r:1; + uint32_t reserved_7:1; + /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region5_r2_pms_x:1; + /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region5_r2_pms_w:1; + /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region5_r2_pms_r:1; + /** region5_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region5 configuration + */ + uint32_t region5_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region5_pms_attr_reg_t; + +/** Type of region6_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region6_r0_pms_x:1; + /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region6_r0_pms_w:1; + /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region6_r0_pms_r:1; + uint32_t reserved_3:1; + /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region6_r1_pms_x:1; + /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region6_r1_pms_w:1; + /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region6_r1_pms_r:1; + uint32_t reserved_7:1; + /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region6_r2_pms_x:1; + /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region6_r2_pms_w:1; + /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region6_r2_pms_r:1; + /** region6_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region6 configuration + */ + uint32_t region6_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region6_pms_attr_reg_t; + +/** Type of region7_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region7_r0_pms_x:1; + /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region7_r0_pms_w:1; + /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region7_r0_pms_r:1; + uint32_t reserved_3:1; + /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region7_r1_pms_x:1; + /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region7_r1_pms_w:1; + /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region7_r1_pms_r:1; + uint32_t reserved_7:1; + /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region7_r2_pms_x:1; + /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region7_r2_pms_w:1; + /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region7_r2_pms_r:1; + /** region7_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region7 configuration + */ + uint32_t region7_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region7_pms_attr_reg_t; + +/** Type of region8_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region8_r0_pms_x:1; + /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region8_r0_pms_w:1; + /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region8_r0_pms_r:1; + uint32_t reserved_3:1; + /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region8_r1_pms_x:1; + /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region8_r1_pms_w:1; + /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region8_r1_pms_r:1; + uint32_t reserved_7:1; + /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region8_r2_pms_x:1; + /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region8_r2_pms_w:1; + /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region8_r2_pms_r:1; + /** region8_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region8 configuration + */ + uint32_t region8_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region8_pms_attr_reg_t; + +/** Type of region9_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region9_r0_pms_x:1; + /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region9_r0_pms_w:1; + /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region9_r0_pms_r:1; + uint32_t reserved_3:1; + /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region9_r1_pms_x:1; + /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region9_r1_pms_w:1; + /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region9_r1_pms_r:1; + uint32_t reserved_7:1; + /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region9_r2_pms_x:1; + /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region9_r2_pms_w:1; + /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region9_r2_pms_r:1; + /** region9_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region9 configuration + */ + uint32_t region9_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region9_pms_attr_reg_t; + +/** Type of region10_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region10_r0_pms_x:1; + /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region10_r0_pms_w:1; + /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region10_r0_pms_r:1; + uint32_t reserved_3:1; + /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region10_r1_pms_x:1; + /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region10_r1_pms_w:1; + /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region10_r1_pms_r:1; + uint32_t reserved_7:1; + /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region10_r2_pms_x:1; + /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region10_r2_pms_w:1; + /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region10_r2_pms_r:1; + /** region10_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region10 configuration + */ + uint32_t region10_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region10_pms_attr_reg_t; + +/** Type of region11_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region11_r0_pms_x:1; + /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region11_r0_pms_w:1; + /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region11_r0_pms_r:1; + uint32_t reserved_3:1; + /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region11_r1_pms_x:1; + /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region11_r1_pms_w:1; + /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region11_r1_pms_r:1; + uint32_t reserved_7:1; + /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region11_r2_pms_x:1; + /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region11_r2_pms_w:1; + /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region11_r2_pms_r:1; + /** region11_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region11 configuration + */ + uint32_t region11_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region11_pms_attr_reg_t; + +/** Type of region12_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region12_r0_pms_x:1; + /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region12_r0_pms_w:1; + /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region12_r0_pms_r:1; + uint32_t reserved_3:1; + /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region12_r1_pms_x:1; + /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region12_r1_pms_w:1; + /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region12_r1_pms_r:1; + uint32_t reserved_7:1; + /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region12_r2_pms_x:1; + /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region12_r2_pms_w:1; + /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region12_r2_pms_r:1; + /** region12_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region12 configuration + */ + uint32_t region12_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region12_pms_attr_reg_t; + +/** Type of region13_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region13_r0_pms_x:1; + /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region13_r0_pms_w:1; + /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region13_r0_pms_r:1; + uint32_t reserved_3:1; + /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region13_r1_pms_x:1; + /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region13_r1_pms_w:1; + /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region13_r1_pms_r:1; + uint32_t reserved_7:1; + /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region13_r2_pms_x:1; + /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region13_r2_pms_w:1; + /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region13_r2_pms_r:1; + /** region13_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region13 configuration + */ + uint32_t region13_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region13_pms_attr_reg_t; + +/** Type of region14_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region14_r0_pms_x:1; + /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region14_r0_pms_w:1; + /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region14_r0_pms_r:1; + uint32_t reserved_3:1; + /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region14_r1_pms_x:1; + /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region14_r1_pms_w:1; + /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region14_r1_pms_r:1; + uint32_t reserved_7:1; + /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region14_r2_pms_x:1; + /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region14_r2_pms_w:1; + /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region14_r2_pms_r:1; + /** region14_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region14 configuration + */ + uint32_t region14_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region14_pms_attr_reg_t; + +/** Type of region15_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region15_r0_pms_x:1; + /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region15_r0_pms_w:1; + /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region15_r0_pms_r:1; + uint32_t reserved_3:1; + /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region15_r1_pms_x:1; + /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region15_r1_pms_w:1; + /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region15_r1_pms_r:1; + uint32_t reserved_7:1; + /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region15_r2_pms_x:1; + /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region15_r2_pms_w:1; + /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region15_r2_pms_r:1; + /** region15_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region15 configuration + */ + uint32_t region15_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region15_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + /** m2_pms_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_pms_func_en:1; + /** m3_pms_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_pms_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} hp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} hp_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m2_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} hp_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m3_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} hp_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_apm_date_reg_t; + + +typedef struct hp_apm_dev_t { + volatile hp_apm_region_filter_en_reg_t region_filter_en; + volatile hp_apm_region0_addr_start_reg_t region0_addr_start; + volatile hp_apm_region0_addr_end_reg_t region0_addr_end; + volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile hp_apm_region1_addr_start_reg_t region1_addr_start; + volatile hp_apm_region1_addr_end_reg_t region1_addr_end; + volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile hp_apm_region2_addr_start_reg_t region2_addr_start; + volatile hp_apm_region2_addr_end_reg_t region2_addr_end; + volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile hp_apm_region3_addr_start_reg_t region3_addr_start; + volatile hp_apm_region3_addr_end_reg_t region3_addr_end; + volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr; + volatile hp_apm_region4_addr_start_reg_t region4_addr_start; + volatile hp_apm_region4_addr_end_reg_t region4_addr_end; + volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr; + volatile hp_apm_region5_addr_start_reg_t region5_addr_start; + volatile hp_apm_region5_addr_end_reg_t region5_addr_end; + volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr; + volatile hp_apm_region6_addr_start_reg_t region6_addr_start; + volatile hp_apm_region6_addr_end_reg_t region6_addr_end; + volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr; + volatile hp_apm_region7_addr_start_reg_t region7_addr_start; + volatile hp_apm_region7_addr_end_reg_t region7_addr_end; + volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr; + volatile hp_apm_region8_addr_start_reg_t region8_addr_start; + volatile hp_apm_region8_addr_end_reg_t region8_addr_end; + volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr; + volatile hp_apm_region9_addr_start_reg_t region9_addr_start; + volatile hp_apm_region9_addr_end_reg_t region9_addr_end; + volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr; + volatile hp_apm_region10_addr_start_reg_t region10_addr_start; + volatile hp_apm_region10_addr_end_reg_t region10_addr_end; + volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr; + volatile hp_apm_region11_addr_start_reg_t region11_addr_start; + volatile hp_apm_region11_addr_end_reg_t region11_addr_end; + volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr; + volatile hp_apm_region12_addr_start_reg_t region12_addr_start; + volatile hp_apm_region12_addr_end_reg_t region12_addr_end; + volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr; + volatile hp_apm_region13_addr_start_reg_t region13_addr_start; + volatile hp_apm_region13_addr_end_reg_t region13_addr_end; + volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr; + volatile hp_apm_region14_addr_start_reg_t region14_addr_start; + volatile hp_apm_region14_addr_end_reg_t region14_addr_end; + volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr; + volatile hp_apm_region15_addr_start_reg_t region15_addr_start; + volatile hp_apm_region15_addr_end_reg_t region15_addr_end; + volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr; + volatile hp_apm_func_ctrl_reg_t func_ctrl; + volatile hp_apm_m0_status_reg_t m0_status; + volatile hp_apm_m0_status_clr_reg_t m0_status_clr; + volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile hp_apm_m1_status_reg_t m1_status; + volatile hp_apm_m1_status_clr_reg_t m1_status_clr; + volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile hp_apm_m2_status_reg_t m2_status; + volatile hp_apm_m2_status_clr_reg_t m2_status_clr; + volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile hp_apm_m3_status_reg_t m3_status; + volatile hp_apm_m3_status_clr_reg_t m3_status_clr; + volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1; + volatile hp_apm_int_en_reg_t int_en; + volatile hp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_110[443]; + volatile hp_apm_date_reg_t date; +} hp_apm_dev_t; + +extern hp_apm_dev_t HP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_system_reg.h b/components/soc/esp32c5/include/soc/hp_system_reg.h new file mode 100644 index 00000000000..d6bcde83a6c --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_system_reg.h @@ -0,0 +1,436 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +#define HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYS_BASE + 0x0) +/** HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/** HP_SYS_SRAM_USAGE_CONF_REG register + * HP memory usage configuration register + */ +#define HP_SYS_SRAM_USAGE_CONF_REG (DR_REG_HP_SYS_BASE + 0x4) +/** HP_SYS_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ +#define HP_SYS_SRAM_USAGE 0x0000000FU +#define HP_SYS_SRAM_USAGE_M (HP_SYS_SRAM_USAGE_V << HP_SYS_SRAM_USAGE_S) +#define HP_SYS_SRAM_USAGE_V 0x0000000FU +#define HP_SYS_SRAM_USAGE_S 8 +/** HP_SYS_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ +#define HP_SYS_MAC_DUMP_ALLOC (BIT(16)) +#define HP_SYS_MAC_DUMP_ALLOC_M (HP_SYS_MAC_DUMP_ALLOC_V << HP_SYS_MAC_DUMP_ALLOC_S) +#define HP_SYS_MAC_DUMP_ALLOC_V 0x00000001U +#define HP_SYS_MAC_DUMP_ALLOC_S 16 + +/** HP_SYS_SEC_DPA_CONF_REG register + * HP anti-DPA security configuration register + */ +#define HP_SYS_SEC_DPA_CONF_REG (DR_REG_HP_SYS_BASE + 0x8) +/** HP_SYS_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + */ +#define HP_SYS_SEC_DPA_LEVEL 0x00000003U +#define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S) +#define HP_SYS_SEC_DPA_LEVEL_V 0x00000003U +#define HP_SYS_SEC_DPA_LEVEL_S 0 +/** HP_SYS_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + */ +#define HP_SYS_SEC_DPA_CFG_SEL (BIT(2)) +#define HP_SYS_SEC_DPA_CFG_SEL_M (HP_SYS_SEC_DPA_CFG_SEL_V << HP_SYS_SEC_DPA_CFG_SEL_S) +#define HP_SYS_SEC_DPA_CFG_SEL_V 0x00000001U +#define HP_SYS_SEC_DPA_CFG_SEL_S 2 + +/** HP_SYS_CPU_PERI_TIMEOUT_CONF_REG register + * CPU_PERI_TIMEOUT configuration register + */ +#define HP_SYS_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0xc) +/** HP_SYS_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYS_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_THRES_M (HP_SYS_CPU_PERI_TIMEOUT_THRES_V << HP_SYS_CPU_PERI_TIMEOUT_THRES_S) +#define HP_SYS_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_THRES_S 0 +/** HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG register + * CPU_PERI_TIMEOUT_ADDR register + */ +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x10) +/** HP_SYS_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_M (HP_SYS_CPU_PERI_TIMEOUT_ADDR_V << HP_SYS_CPU_PERI_TIMEOUT_ADDR_S) +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYS_CPU_PERI_TIMEOUT_UID_REG register + * CPU_PERI_TIMEOUT_UID register + */ +#define HP_SYS_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x14) +/** HP_SYS_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYS_CPU_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYS_CPU_PERI_TIMEOUT_UID_M (HP_SYS_CPU_PERI_TIMEOUT_UID_V << HP_SYS_CPU_PERI_TIMEOUT_UID_S) +#define HP_SYS_CPU_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYS_CPU_PERI_TIMEOUT_UID_S 0 + +/** HP_SYS_HP_PERI_TIMEOUT_CONF_REG register + * HP_PERI_TIMEOUT configuration register + */ +#define HP_SYS_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x18) +/** HP_SYS_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYS_HP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYS_HP_PERI_TIMEOUT_THRES_M (HP_SYS_HP_PERI_TIMEOUT_THRES_V << HP_SYS_HP_PERI_TIMEOUT_THRES_S) +#define HP_SYS_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYS_HP_PERI_TIMEOUT_THRES_S 0 +/** HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYS_HP_PERI_TIMEOUT_ADDR_REG register + * HP_PERI_TIMEOUT_ADDR register + */ +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x1c) +/** HP_SYS_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYS_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_M (HP_SYS_HP_PERI_TIMEOUT_ADDR_V << HP_SYS_HP_PERI_TIMEOUT_ADDR_S) +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYS_HP_PERI_TIMEOUT_UID_REG register + * HP_PERI_TIMEOUT_UID register + */ +#define HP_SYS_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x20) +/** HP_SYS_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYS_HP_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYS_HP_PERI_TIMEOUT_UID_M (HP_SYS_HP_PERI_TIMEOUT_UID_V << HP_SYS_HP_PERI_TIMEOUT_UID_S) +#define HP_SYS_HP_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYS_HP_PERI_TIMEOUT_UID_S 0 + +/** HP_SYS_SDIO_CTRL_REG register + * SDIO Control configuration register + */ +#define HP_SYS_SDIO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x30) +/** HP_SYS_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ +#define HP_SYS_DIS_SDIO_PROB (BIT(0)) +#define HP_SYS_DIS_SDIO_PROB_M (HP_SYS_DIS_SDIO_PROB_V << HP_SYS_DIS_SDIO_PROB_S) +#define HP_SYS_DIS_SDIO_PROB_V 0x00000001U +#define HP_SYS_DIS_SDIO_PROB_S 0 +/** HP_SYS_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ +#define HP_SYS_SDIO_WIN_ACCESS_EN (BIT(1)) +#define HP_SYS_SDIO_WIN_ACCESS_EN_M (HP_SYS_SDIO_WIN_ACCESS_EN_V << HP_SYS_SDIO_WIN_ACCESS_EN_S) +#define HP_SYS_SDIO_WIN_ACCESS_EN_V 0x00000001U +#define HP_SYS_SDIO_WIN_ACCESS_EN_S 1 + +/** HP_SYS_ROM_TABLE_LOCK_REG register + * Rom-Table lock register + */ +#define HP_SYS_ROM_TABLE_LOCK_REG (DR_REG_HP_SYS_BASE + 0x38) +/** HP_SYS_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; + * XXXX + */ +#define HP_SYS_ROM_TABLE_LOCK (BIT(0)) +#define HP_SYS_ROM_TABLE_LOCK_M (HP_SYS_ROM_TABLE_LOCK_V << HP_SYS_ROM_TABLE_LOCK_S) +#define HP_SYS_ROM_TABLE_LOCK_V 0x00000001U +#define HP_SYS_ROM_TABLE_LOCK_S 0 + +/** HP_SYS_ROM_TABLE_REG register + * Rom-Table register + */ +#define HP_SYS_ROM_TABLE_REG (DR_REG_HP_SYS_BASE + 0x3c) +/** HP_SYS_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ +#define HP_SYS_ROM_TABLE 0xFFFFFFFFU +#define HP_SYS_ROM_TABLE_M (HP_SYS_ROM_TABLE_V << HP_SYS_ROM_TABLE_S) +#define HP_SYS_ROM_TABLE_V 0xFFFFFFFFU +#define HP_SYS_ROM_TABLE_S 0 + +/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register + * Core Debug runstall configure register + */ +#define HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x40) +/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + */ +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0)) +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S) +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S 0 +/** HP_SYS_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0; + * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: + * not stalled. + */ +#define HP_SYS_CORE_RUNSTALLED (BIT(1)) +#define HP_SYS_CORE_RUNSTALLED_M (HP_SYS_CORE_RUNSTALLED_V << HP_SYS_CORE_RUNSTALLED_S) +#define HP_SYS_CORE_RUNSTALLED_V 0x00000001U +#define HP_SYS_CORE_RUNSTALLED_S 1 + +/** HP_SYS_SPROM_CTRL_REG register + * reserved + */ +#define HP_SYS_SPROM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70) +/** HP_SYS_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; + * reserved + */ +#define HP_SYS_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SPROM_MEM_AUX_CTRL_M (HP_SYS_SPROM_MEM_AUX_CTRL_V << HP_SYS_SPROM_MEM_AUX_CTRL_S) +#define HP_SYS_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SPROM_MEM_AUX_CTRL_S 0 + +/** HP_SYS_SPRAM_CTRL_REG register + * reserved + */ +#define HP_SYS_SPRAM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x74) +/** HP_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ +#define HP_SYS_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SPRAM_MEM_AUX_CTRL_M (HP_SYS_SPRAM_MEM_AUX_CTRL_V << HP_SYS_SPRAM_MEM_AUX_CTRL_S) +#define HP_SYS_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SPRAM_MEM_AUX_CTRL_S 0 + +/** HP_SYS_SPRF_CTRL_REG register + * reserved + */ +#define HP_SYS_SPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x78) +/** HP_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ +#define HP_SYS_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SPRF_MEM_AUX_CTRL_M (HP_SYS_SPRF_MEM_AUX_CTRL_V << HP_SYS_SPRF_MEM_AUX_CTRL_S) +#define HP_SYS_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SPRF_MEM_AUX_CTRL_S 0 + +/** HP_SYS_SDPRF_CTRL_REG register + * reserved + */ +#define HP_SYS_SDPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x7c) +/** HP_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define HP_SYS_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SDPRF_MEM_AUX_CTRL_M (HP_SYS_SDPRF_MEM_AUX_CTRL_V << HP_SYS_SDPRF_MEM_AUX_CTRL_S) +#define HP_SYS_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SDPRF_MEM_AUX_CTRL_S 0 + +/** HP_SYS_AUDIO_CODEX_CTRL0_REG register + * reserved + */ +#define HP_SYS_AUDIO_CODEX_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x80) +/** HP_SYS_DAC_IN_R1_IE : R/W; bitpos: [0]; default: 1; + * reserved + */ +#define HP_SYS_DAC_IN_R1_IE (BIT(0)) +#define HP_SYS_DAC_IN_R1_IE_M (HP_SYS_DAC_IN_R1_IE_V << HP_SYS_DAC_IN_R1_IE_S) +#define HP_SYS_DAC_IN_R1_IE_V 0x00000001U +#define HP_SYS_DAC_IN_R1_IE_S 0 +/** HP_SYS_DAC_IN_R1_OE : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYS_DAC_IN_R1_OE (BIT(1)) +#define HP_SYS_DAC_IN_R1_OE_M (HP_SYS_DAC_IN_R1_OE_V << HP_SYS_DAC_IN_R1_OE_S) +#define HP_SYS_DAC_IN_R1_OE_V 0x00000001U +#define HP_SYS_DAC_IN_R1_OE_S 1 +/** HP_SYS_DAC_IN_R0_IE : R/W; bitpos: [2]; default: 1; + * reserved + */ +#define HP_SYS_DAC_IN_R0_IE (BIT(2)) +#define HP_SYS_DAC_IN_R0_IE_M (HP_SYS_DAC_IN_R0_IE_V << HP_SYS_DAC_IN_R0_IE_S) +#define HP_SYS_DAC_IN_R0_IE_V 0x00000001U +#define HP_SYS_DAC_IN_R0_IE_S 2 +/** HP_SYS_DAC_IN_R0_OE : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define HP_SYS_DAC_IN_R0_OE (BIT(3)) +#define HP_SYS_DAC_IN_R0_OE_M (HP_SYS_DAC_IN_R0_OE_V << HP_SYS_DAC_IN_R0_OE_S) +#define HP_SYS_DAC_IN_R0_OE_V 0x00000001U +#define HP_SYS_DAC_IN_R0_OE_S 3 +/** HP_SYS_ADC_DATA_4_IE : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_4_IE (BIT(4)) +#define HP_SYS_ADC_DATA_4_IE_M (HP_SYS_ADC_DATA_4_IE_V << HP_SYS_ADC_DATA_4_IE_S) +#define HP_SYS_ADC_DATA_4_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_4_IE_S 4 +/** HP_SYS_ADC_DATA_4_OE : R/W; bitpos: [5]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_4_OE (BIT(5)) +#define HP_SYS_ADC_DATA_4_OE_M (HP_SYS_ADC_DATA_4_OE_V << HP_SYS_ADC_DATA_4_OE_S) +#define HP_SYS_ADC_DATA_4_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_4_OE_S 5 +/** HP_SYS_ADC_DATA_3_IE : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_3_IE (BIT(6)) +#define HP_SYS_ADC_DATA_3_IE_M (HP_SYS_ADC_DATA_3_IE_V << HP_SYS_ADC_DATA_3_IE_S) +#define HP_SYS_ADC_DATA_3_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_3_IE_S 6 +/** HP_SYS_ADC_DATA_3_OE : R/W; bitpos: [7]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_3_OE (BIT(7)) +#define HP_SYS_ADC_DATA_3_OE_M (HP_SYS_ADC_DATA_3_OE_V << HP_SYS_ADC_DATA_3_OE_S) +#define HP_SYS_ADC_DATA_3_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_3_OE_S 7 +/** HP_SYS_ADC_DATA_2_IE : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_2_IE (BIT(8)) +#define HP_SYS_ADC_DATA_2_IE_M (HP_SYS_ADC_DATA_2_IE_V << HP_SYS_ADC_DATA_2_IE_S) +#define HP_SYS_ADC_DATA_2_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_2_IE_S 8 +/** HP_SYS_ADC_DATA_2_OE : R/W; bitpos: [9]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_2_OE (BIT(9)) +#define HP_SYS_ADC_DATA_2_OE_M (HP_SYS_ADC_DATA_2_OE_V << HP_SYS_ADC_DATA_2_OE_S) +#define HP_SYS_ADC_DATA_2_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_2_OE_S 9 +/** HP_SYS_ADC_DATA_1_IE : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_1_IE (BIT(10)) +#define HP_SYS_ADC_DATA_1_IE_M (HP_SYS_ADC_DATA_1_IE_V << HP_SYS_ADC_DATA_1_IE_S) +#define HP_SYS_ADC_DATA_1_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_1_IE_S 10 +/** HP_SYS_ADC_DATA_1_OE : R/W; bitpos: [11]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_1_OE (BIT(11)) +#define HP_SYS_ADC_DATA_1_OE_M (HP_SYS_ADC_DATA_1_OE_V << HP_SYS_ADC_DATA_1_OE_S) +#define HP_SYS_ADC_DATA_1_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_1_OE_S 11 +/** HP_SYS_ADC_DATA_0_IE : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_0_IE (BIT(12)) +#define HP_SYS_ADC_DATA_0_IE_M (HP_SYS_ADC_DATA_0_IE_V << HP_SYS_ADC_DATA_0_IE_S) +#define HP_SYS_ADC_DATA_0_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_0_IE_S 12 +/** HP_SYS_ADC_DATA_0_OE : R/W; bitpos: [13]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_0_OE (BIT(13)) +#define HP_SYS_ADC_DATA_0_OE_M (HP_SYS_ADC_DATA_0_OE_V << HP_SYS_ADC_DATA_0_OE_S) +#define HP_SYS_ADC_DATA_0_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_0_OE_S 13 +/** HP_SYS_ADC_CK_DATA_IE : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define HP_SYS_ADC_CK_DATA_IE (BIT(14)) +#define HP_SYS_ADC_CK_DATA_IE_M (HP_SYS_ADC_CK_DATA_IE_V << HP_SYS_ADC_CK_DATA_IE_S) +#define HP_SYS_ADC_CK_DATA_IE_V 0x00000001U +#define HP_SYS_ADC_CK_DATA_IE_S 14 +/** HP_SYS_ADC_CK_DATA_OE : R/W; bitpos: [15]; default: 1; + * reserved + */ +#define HP_SYS_ADC_CK_DATA_OE (BIT(15)) +#define HP_SYS_ADC_CK_DATA_OE_M (HP_SYS_ADC_CK_DATA_OE_V << HP_SYS_ADC_CK_DATA_OE_S) +#define HP_SYS_ADC_CK_DATA_OE_V 0x00000001U +#define HP_SYS_ADC_CK_DATA_OE_S 15 + +/** HP_SYS_DATE_REG register + * Date register. + */ +#define HP_SYS_DATE_REG (DR_REG_HP_SYS_BASE + 0x3fc) +/** HP_SYS_DATE : R/W; bitpos: [27:0]; default: 36720768; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ +#define HP_SYS_DATE 0x0FFFFFFFU +#define HP_SYS_DATE_M (HP_SYS_DATE_V << HP_SYS_DATE_S) +#define HP_SYS_DATE_V 0x0FFFFFFFU +#define HP_SYS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_system_struct.h b/components/soc/esp32c5/include/soc/hp_system_struct.h new file mode 100644 index 00000000000..442fa11ecb4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_system_struct.h @@ -0,0 +1,428 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of external_device_encrypt_decrypt_control register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +typedef union { + struct { + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ + uint32_t enable_download_manual_encrypt:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_sys_external_device_encrypt_decrypt_control_reg_t; + +/** Type of sram_usage_conf register + * HP memory usage configuration register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** sram_usage : R/W; bitpos: [11:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ + uint32_t sram_usage:4; + uint32_t reserved_12:4; + /** mac_dump_alloc : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ + uint32_t mac_dump_alloc:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hp_sys_sram_usage_conf_reg_t; + +/** Type of sec_dpa_conf register + * HP anti-DPA security configuration register + */ +typedef union { + struct { + /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + */ + uint32_t sec_dpa_level:2; + /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_cfg_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} hp_sys_sec_dpa_conf_reg_t; + +/** Type of sdio_ctrl register + * SDIO Control configuration register + */ +typedef union { + struct { + /** dis_sdio_prob : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ + uint32_t dis_sdio_prob:1; + /** sdio_win_access_en : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ + uint32_t sdio_win_access_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_sys_sdio_ctrl_reg_t; + +/** Type of rom_table_lock register + * Rom-Table lock register + */ +typedef union { + struct { + /** rom_table_lock : R/W; bitpos: [0]; default: 0; + * XXXX + */ + uint32_t rom_table_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_sys_rom_table_lock_reg_t; + +/** Type of rom_table register + * Rom-Table register + */ +typedef union { + struct { + /** rom_table : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ + uint32_t rom_table:32; + }; + uint32_t val; +} hp_sys_rom_table_reg_t; + +/** Type of core_debug_runstall_conf register + * Core Debug runstall configure register + */ +typedef union { + struct { + /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0; + * Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + */ + uint32_t core_debug_runstall_enable:1; + /** core_runstalled : RO; bitpos: [1]; default: 0; + * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: + * not stalled. + */ + uint32_t core_runstalled:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_sys_core_debug_runstall_conf_reg_t; + +/** Type of sprom_ctrl register + * reserved + */ +typedef union { + struct { + /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + * reserved + */ + uint32_t sprom_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_sprom_ctrl_reg_t; + +/** Type of spram_ctrl register + * reserved + */ +typedef union { + struct { + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ + uint32_t spram_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_spram_ctrl_reg_t; + +/** Type of sprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ + uint32_t sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_sprf_ctrl_reg_t; + +/** Type of sdprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_sdprf_ctrl_reg_t; + +/** Type of audio_codex_ctrl0 register + * reserved + */ +typedef union { + struct { + /** dac_in_r1_ie : R/W; bitpos: [0]; default: 1; + * reserved + */ + uint32_t dac_in_r1_ie:1; + /** dac_in_r1_oe : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t dac_in_r1_oe:1; + /** dac_in_r0_ie : R/W; bitpos: [2]; default: 1; + * reserved + */ + uint32_t dac_in_r0_ie:1; + /** dac_in_r0_oe : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t dac_in_r0_oe:1; + /** adc_data_4_ie : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t adc_data_4_ie:1; + /** adc_data_4_oe : R/W; bitpos: [5]; default: 1; + * reserved + */ + uint32_t adc_data_4_oe:1; + /** adc_data_3_ie : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t adc_data_3_ie:1; + /** adc_data_3_oe : R/W; bitpos: [7]; default: 1; + * reserved + */ + uint32_t adc_data_3_oe:1; + /** adc_data_2_ie : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t adc_data_2_ie:1; + /** adc_data_2_oe : R/W; bitpos: [9]; default: 1; + * reserved + */ + uint32_t adc_data_2_oe:1; + /** adc_data_1_ie : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t adc_data_1_ie:1; + /** adc_data_1_oe : R/W; bitpos: [11]; default: 1; + * reserved + */ + uint32_t adc_data_1_oe:1; + /** adc_data_0_ie : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t adc_data_0_ie:1; + /** adc_data_0_oe : R/W; bitpos: [13]; default: 1; + * reserved + */ + uint32_t adc_data_0_oe:1; + /** adc_ck_data_ie : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t adc_ck_data_ie:1; + /** adc_ck_data_oe : R/W; bitpos: [15]; default: 1; + * reserved + */ + uint32_t adc_ck_data_oe:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_sys_audio_codex_ctrl0_reg_t; + + +/** Group: Timeout Register */ +/** Type of cpu_peri_timeout_conf register + * CPU_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t cpu_peri_timeout_thres:16; + /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t cpu_peri_timeout_int_clear:1; + /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ + uint32_t cpu_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_conf_reg_t; + +/** Type of cpu_peri_timeout_addr register + * CPU_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t cpu_peri_timeout_addr:32; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_addr_reg_t; + +/** Type of cpu_peri_timeout_uid register + * CPU_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t cpu_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_uid_reg_t; + +/** Type of hp_peri_timeout_conf register + * HP_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t hp_peri_timeout_thres:16; + /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t hp_peri_timeout_int_clear:1; + /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ + uint32_t hp_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_conf_reg_t; + +/** Type of hp_peri_timeout_addr register + * HP_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t hp_peri_timeout_addr:32; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_addr_reg_t; + +/** Type of hp_peri_timeout_uid register + * HP_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t hp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_uid_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720768; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_sys_date_reg_t; + + +typedef struct hp_sys_dev_t { + volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; + volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf; + volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf; + volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; + volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; + volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; + volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; + volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; + volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; + uint32_t reserved_024[3]; + volatile hp_sys_sdio_ctrl_reg_t sdio_ctrl; + uint32_t reserved_034; + volatile hp_sys_rom_table_lock_reg_t rom_table_lock; + volatile hp_sys_rom_table_reg_t rom_table; + volatile hp_sys_core_debug_runstall_conf_reg_t core_debug_runstall_conf; + uint32_t reserved_044[11]; + volatile hp_sys_sprom_ctrl_reg_t sprom_ctrl; + volatile hp_sys_spram_ctrl_reg_t spram_ctrl; + volatile hp_sys_sprf_ctrl_reg_t sprf_ctrl; + volatile hp_sys_sdprf_ctrl_reg_t sdprf_ctrl; + volatile hp_sys_audio_codex_ctrl0_reg_t audio_codex_ctrl0; + uint32_t reserved_084[222]; + volatile hp_sys_date_reg_t date; +} hp_sys_dev_t; + +extern hp_sys_dev_t HP_SYSTEM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/huk_reg.h b/components/soc/esp32c5/include/soc/huk_reg.h new file mode 100644 index 00000000000..3f394c71e45 --- /dev/null +++ b/components/soc/esp32c5/include/soc/huk_reg.h @@ -0,0 +1,222 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HUK_CLK_REG register + * HUK Generator clock gate control register + */ +#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4) +/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define HUK_CLK_EN (BIT(0)) +#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S) +#define HUK_CLK_EN_V 0x00000001U +#define HUK_CLK_EN_S 0 +/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define HUK_MEM_CG_FORCE_ON (BIT(1)) +#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S) +#define HUK_MEM_CG_FORCE_ON_V 0x00000001U +#define HUK_MEM_CG_FORCE_ON_S 1 + +/** HUK_INT_RAW_REG register + * HUK Generator interrupt raw register, valid in level. + */ +#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8) +/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_RAW (BIT(0)) +#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S) +#define HUK_PREP_DONE_INT_RAW_V 0x00000001U +#define HUK_PREP_DONE_INT_RAW_S 0 +/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_RAW (BIT(1)) +#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S) +#define HUK_PROC_DONE_INT_RAW_V 0x00000001U +#define HUK_PROC_DONE_INT_RAW_S 1 +/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_RAW (BIT(2)) +#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S) +#define HUK_POST_DONE_INT_RAW_V 0x00000001U +#define HUK_POST_DONE_INT_RAW_S 2 + +/** HUK_INT_ST_REG register + * HUK Generator interrupt status register. + */ +#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc) +/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_ST (BIT(0)) +#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S) +#define HUK_PREP_DONE_INT_ST_V 0x00000001U +#define HUK_PREP_DONE_INT_ST_S 0 +/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_ST (BIT(1)) +#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S) +#define HUK_PROC_DONE_INT_ST_V 0x00000001U +#define HUK_PROC_DONE_INT_ST_S 1 +/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_ST (BIT(2)) +#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S) +#define HUK_POST_DONE_INT_ST_V 0x00000001U +#define HUK_POST_DONE_INT_ST_S 2 + +/** HUK_INT_ENA_REG register + * HUK Generator interrupt enable register. + */ +#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10) +/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_ENA (BIT(0)) +#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S) +#define HUK_PREP_DONE_INT_ENA_V 0x00000001U +#define HUK_PREP_DONE_INT_ENA_S 0 +/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_ENA (BIT(1)) +#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S) +#define HUK_PROC_DONE_INT_ENA_V 0x00000001U +#define HUK_PROC_DONE_INT_ENA_S 1 +/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_ENA (BIT(2)) +#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S) +#define HUK_POST_DONE_INT_ENA_V 0x00000001U +#define HUK_POST_DONE_INT_ENA_S 2 + +/** HUK_INT_CLR_REG register + * HUK Generator interrupt clear register. + */ +#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14) +/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_CLR (BIT(0)) +#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S) +#define HUK_PREP_DONE_INT_CLR_V 0x00000001U +#define HUK_PREP_DONE_INT_CLR_S 0 +/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_CLR (BIT(1)) +#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S) +#define HUK_PROC_DONE_INT_CLR_V 0x00000001U +#define HUK_PROC_DONE_INT_CLR_S 1 +/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_CLR (BIT(2)) +#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S) +#define HUK_POST_DONE_INT_CLR_V 0x00000001U +#define HUK_POST_DONE_INT_CLR_S 2 + +/** HUK_CONF_REG register + * HUK Generator configuration register + */ +#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20) +/** HUK_MODE : R/W; bitpos: [0]; default: 0; + * Set this field to choose the huk process. 1: process huk generate mode. 0: process + * huk recovery mode. + */ +#define HUK_MODE (BIT(0)) +#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S) +#define HUK_MODE_V 0x00000001U +#define HUK_MODE_S 0 + +/** HUK_START_REG register + * HUK Generator control register + */ +#define HUK_START_REG (DR_REG_HUK_BASE + 0x24) +/** HUK_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ +#define HUK_START (BIT(0)) +#define HUK_START_M (HUK_START_V << HUK_START_S) +#define HUK_START_V 0x00000001U +#define HUK_START_S 0 +/** HUK_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start HUK Generator at IDLE state. + */ +#define HUK_CONTINUE (BIT(1)) +#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S) +#define HUK_CONTINUE_V 0x00000001U +#define HUK_CONTINUE_S 1 + +/** HUK_STATE_REG register + * HUK Generator state register + */ +#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28) +/** HUK_STATE : RO; bitpos: [1:0]; default: 0; + * The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define HUK_STATE 0x00000003U +#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S) +#define HUK_STATE_V 0x00000003U +#define HUK_STATE_S 0 + +/** HUK_STATUS_REG register + * HUK Generator HUK status register + */ +#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34) +/** HUK_STATUS : RO; bitpos: [1:0]; default: 0; + * The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. + * 2: HUK is generated but invalid. 3: reserved. + */ +#define HUK_STATUS 0x00000003U +#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S) +#define HUK_STATUS_V 0x00000003U +#define HUK_STATUS_S 0 +/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0; + * The risk level of HUK. 0-6: the higher the risk level is, the more error bits there + * are in the PUF SRAM. 7: Error Level, HUK is invalid. + */ +#define HUK_RISK_LEVEL 0x00000007U +#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S) +#define HUK_RISK_LEVEL_V 0x00000007U +#define HUK_RISK_LEVEL_S 2 + +/** HUK_DATE_REG register + * Version control register + */ +#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc) +/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704; + * HUK Generator version control register. + */ +#define HUK_DATE 0x0FFFFFFFU +#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S) +#define HUK_DATE_V 0x0FFFFFFFU +#define HUK_DATE_S 0 + +/** HUK_INFO_MEM register + * The memory that stores HUK info. + */ +#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100) +#define HUK_INFO_MEM_SIZE_BYTES 384 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/include/soc/huk_struct.h new file mode 100644 index 00000000000..98f7e666b06 --- /dev/null +++ b/components/soc/esp32c5/include/soc/huk_struct.h @@ -0,0 +1,242 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * HUK Generator clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * HUK Generator interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_raw_reg_t; + +/** Type of int_st register + * HUK Generator interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_st_reg_t; + +/** Type of int_ena register + * HUK Generator interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_ena_reg_t; + +/** Type of int_clr register + * HUK Generator interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the huk_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_clr_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * HUK Generator configuration register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [0]; default: 0; + * Set this field to choose the huk process. 1: process huk generate mode. 0: process + * huk recovery mode. + */ + uint32_t mode:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} huk_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * HUK Generator control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start HUK Generator at IDLE state. + */ + uint32_t continue:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * HUK Generator state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_state_reg_t; + + +/** Group: Result registers */ +/** Type of status register + * HUK Generator HUK status register + */ +typedef union { + struct { + /** status : RO; bitpos: [1:0]; default: 0; + * The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. + * 2: HUK is generated but invalid. 3: reserved. + */ + uint32_t status:2; + /** risk_level : RO; bitpos: [4:2]; default: 0; + * The risk level of HUK. 0-6: the higher the risk level is, the more error bits there + * are in the PUF SRAM. 7: Error Level, HUK is invalid. + */ + uint32_t risk_level:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} huk_status_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * HUK Generator version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} huk_date_reg_t; + + +typedef struct huk_dev_t { + uint32_t reserved_000; + volatile huk_clk_reg_t clk; + volatile huk_int_raw_reg_t int_raw; + volatile huk_int_st_reg_t int_st; + volatile huk_int_ena_reg_t int_ena; + volatile huk_int_clr_reg_t int_clr; + uint32_t reserved_018[2]; + volatile huk_conf_reg_t conf; + volatile huk_start_reg_t start; + volatile huk_state_reg_t state; + uint32_t reserved_02c[2]; + volatile huk_status_reg_t status; + uint32_t reserved_038[49]; + volatile huk_date_reg_t date; + volatile uint32_t info[96]; +} huk_dev_t; + +extern huk_dev_t HUK; + +#ifndef __cplusplus +_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2c_reg.h b/components/soc/esp32c5/include/soc/i2c_reg.h new file mode 100644 index 00000000000..49f3185e78c --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2c_reg.h @@ -0,0 +1,1521 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL Clock. + */ +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define I2C_SCL_LOW_PERIOD_S 0 + +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) +/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * Configures the SDA output mode + * 1: Direct output, + * + * 0: Open drain output. + */ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) +#define I2C_SDA_FORCE_OUT_V 0x00000001U +#define I2C_SDA_FORCE_OUT_S 0 +/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * Configures the SCL output mode + * 1: Direct output, + * + * 0: Open drain output. + */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) +#define I2C_SCL_FORCE_OUT_V 0x00000001U +#define I2C_SCL_FORCE_OUT_S 1 +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; + * Configures the module as an I2C Master or Slave. + * 0: Slave + * + * 1: Master + */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) +#define I2C_MS_MODE_V 0x00000001U +#define I2C_MS_MODE_S 4 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 +/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; + * Configures to enable slave to send data automatically + * 0: Disable + * + * 1: Enable + */ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check + * + * 1: Check + */ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; + * Configures to support the 7bit general call function. + * 0: Not support + * + * 1: Support + */ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) +#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/** I2C_SR_REG register + * Describe I2C work status. + */ +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U +#define I2C_RESP_REC_S 0 +/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * Represents the transfer direction in slave mode,. + * 1: Master reads from slave, + * + * 0: Master writes to slave. + */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) +#define I2C_SLAVE_RW_V 0x00000001U +#define I2C_SLAVE_RW_S 1 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; + * Represents whether the address sent by the master is equal to the address of the + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * + * 1: Equal + */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) +#define I2C_SLAVE_ADDRESSED_V 0x00000001U +#define I2C_SLAVE_ADDRESSED_S 5 +/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; + * Represents the number of data bytes to be sent. + */ +#define I2C_RXFIFO_CNT 0x0000003FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000003FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + * + * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. + */ +#define I2C_STRETCH_CAUSE 0x00000003U +#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) +#define I2C_STRETCH_CAUSE_V 0x00000003U +#define I2C_STRETCH_CAUSE_S 14 +/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ +#define I2C_TXFIFO_CNT 0x0000003FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000003FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 + +/** I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU +#define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 + +/** I2C_SLAVE_ADDR_REG register + * Local slave address setting + */ +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) +/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * Configure the slave address of I2C Slave. + */ +#define I2C_SLAVE_ADDR 0x00007FFFU +#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) +#define I2C_SLAVE_ADDR_V 0x00007FFFU +#define I2C_SLAVE_ADDR_S 0 +/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * + * 1: Enable + */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) +#define I2C_ADDR_10BIT_EN_V 0x00000001U +#define I2C_ADDR_10BIT_EN_S 31 + +/** I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ +#define I2C_RXFIFO_RADDR 0x0000001FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000001FU +#define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ +#define I2C_RXFIFO_WADDR 0x0000001FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000001FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ +#define I2C_TXFIFO_RADDR 0x0000001FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000001FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ +#define I2C_TXFIFO_WADDR 0x0000001FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000001FU +#define I2C_TXFIFO_WADDR_S 15 +/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C slave mode. + */ +#define I2C_SLAVE_RW_POINT 0x000000FFU +#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) +#define I2C_SLAVE_RW_POINT_V 0x000000FFU +#define I2C_SLAVE_RW_POINT_S 22 + +/** I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define I2C_RXFIFO_WM_THRHD 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; + * Configures to enable double addressing mode. When this mode is enabled, the byte + * received after the I2C address byte represents the offset address in the I2C Slave + * RAM. + * 0: Disable + * + * 1: Enable + */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) +#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 + +/** I2C_DATA_REG register + * Rx FIFO read data. + */ +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c) +/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU +#define I2C_FIFO_RDATA_S 0 + +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 +/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) +#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 + +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 +/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; + * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) +#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 + +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to enable the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to enable the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * Write 1 to enable I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 +/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; + * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) +#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 + +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 +/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) +#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ST_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 + +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU +#define I2C_SDA_HOLD_TIME_S 0 + +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_S 0 + +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_S 0 + +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and SCL rising edge for a stop condition. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU +#define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 + +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU +#define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 + +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU +#define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 + +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU +#define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 + +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU +#define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 + +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU +#define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 + +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU +#define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 + +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU +#define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 + +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU +#define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 + +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 + +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U +#define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_sda_force_out is 1. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 + +/** I2C_SCL_STRETCH_CONF_REG register + * Set SCL stretch of I2C slave + */ +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) +/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk + */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) +#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_S 0 +/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable slave SCL stretch function. + * 0: Disable + * + * 1: Enable + * The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and + * stretch event happens. The stretch cause can be seen in reg_stretch_cause. + */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * + * 1: Clear + */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * + * 1: Enable + */ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * + * 1: High level + */ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050; + * Version control register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU +#define I2C_DATE_S 0 + +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) +/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 + +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) +/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/include/soc/i2c_struct.h new file mode 100644 index 00000000000..ccfc7b278df --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2c_struct.h @@ -0,0 +1,1123 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL Clock. + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and SCL rising edge for a stop condition. + * Measurement unit: i2c_sclk + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 0; + * Configures the SDA output mode + * 1: Direct output, + * + * 0: Open drain output. + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 0; + * Configures the SCL output mode + * 1: Direct output, + * + * 0: Open drain output. + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ + uint32_t rx_full_ack_level:1; + /** ms_mode : R/W; bitpos: [4]; default: 0; + * Configures the module as an I2C Master or Slave. + * 0: Slave + * + * 1: Master + */ + uint32_t ms_mode:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ + uint32_t conf_upgate:1; + /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; + * Configures to enable slave to send data automatically + * 0: Disable + * + * 1: Enable + */ + uint32_t slv_tx_auto_start_en:1; + /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check + * + * 1: Check + */ + uint32_t addr_10bit_rw_check_en:1; + /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; + * Configures to support the 7bit general call function. + * 0: Not support + * + * 1: Support + */ + uint32_t addr_broadcasting_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of slave_addr register + * Local slave address setting + */ +typedef union { + struct { + /** slave_addr : R/W; bitpos: [14:0]; default: 0; + * Configure the slave address of I2C Slave. + */ + uint32_t slave_addr:15; + uint32_t reserved_15:16; + /** addr_10bit_en : R/W; bitpos: [31]; default: 0; + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * + * 1: Enable + */ + uint32_t addr_10bit_en:1; + }; + uint32_t val; +} i2c_slave_addr_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:5; + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:5; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; + * Configures to enable double addressing mode. When this mode is enabled, the byte + * received after the I2C address byte represents the offset address in the I2C Slave + * RAM. + * 0: Disable + * + * 1: Enable + */ + uint32_t fifo_addr_cfg_en:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_sda_force_out is 1. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ +typedef union { + struct { + /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk + */ + uint32_t stretch_protect_num:10; + /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; + * Configures to enable slave SCL stretch function. + * 0: Disable + * + * 1: Enable + * The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and + * stretch event happens. The stretch cause can be seen in reg_stretch_cause. + */ + uint32_t slave_scl_stretch_en:1; + /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * + * 1: Clear + */ + uint32_t slave_scl_stretch_clr:1; + /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * + * 1: Enable + */ + uint32_t slave_byte_ack_ctl_en:1; + /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * + * 1: High level + */ + uint32_t slave_byte_ack_lvl:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} i2c_scl_stretch_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ + uint32_t resp_rec:1; + /** slave_rw : RO; bitpos: [1]; default: 0; + * Represents the transfer direction in slave mode,. + * 1: Master reads from slave, + * + * 0: Master writes to slave. + */ + uint32_t slave_rw:1; + uint32_t reserved_2:1; + /** arb_lost : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ + uint32_t bus_busy:1; + /** slave_addressed : RO; bitpos: [5]; default: 0; + * Represents whether the address sent by the master is equal to the address of the + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * + * 1: Equal + */ + uint32_t slave_addressed:1; + uint32_t reserved_6:2; + /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; + * Represents the number of data bytes to be sent. + */ + uint32_t rxfifo_cnt:6; + /** stretch_cause : RO; bitpos: [15:14]; default: 3; + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + * + * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. + */ + uint32_t stretch_cause:2; + uint32_t reserved_16:2; + /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ + uint32_t txfifo_cnt:6; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ + uint32_t rxfifo_raddr:5; + /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ + uint32_t rxfifo_waddr:5; + /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ + uint32_t txfifo_raddr:5; + /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ + uint32_t txfifo_waddr:5; + uint32_t reserved_20:2; + /** slave_rw_point : RO; bitpos: [29:22]; default: 0; + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C slave mode. + */ + uint32_t slave_rw_point:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_raw:1; + /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_raw:1; + /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_raw:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_clr:1; + /** general_call_int_clr : WT; bitpos: [17]; default: 0; + * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_clr:1; + /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_clr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to enable the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to enable the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * Write 1 to enable I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_ena:1; + /** general_call_int_ena : R/W; bitpos: [17]; default: 0; + * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_ena:1; + /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_ena:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_st:1; + /** general_call_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_st:1; + /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_st:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd register + * I2C command register n + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ + uint32_t command:14; + uint32_t reserved_14:17; + /** command_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command_done:1; + }; + uint32_t val; +} i2c_comd_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656050; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct i2c_dev_t { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + volatile i2c_slave_addr_reg_t slave_addr; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + uint32_t reserved_054; + volatile i2c_comd_reg_t comd[8]; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; + uint32_t reserved_088[28]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} i2c_dev_t; + +extern i2c_dev_t I2C0; +extern i2c_dev_t I2C1; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2s_reg.h b/components/soc/esp32c5/include/soc/i2s_reg.h new file mode 100644 index 00000000000..21d7c896926 --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2s_reg.h @@ -0,0 +1,1268 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2S_INT_RAW_REG register + * I2S interrupt raw register, valid in level. + */ +#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) +/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S) +#define I2S_RX_DONE_INT_RAW_V 0x00000001U +#define I2S_RX_DONE_INT_RAW_S 0 +/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S) +#define I2S_TX_DONE_INT_RAW_V 0x00000001U +#define I2S_TX_DONE_INT_RAW_S 1 +/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001U +#define I2S_RX_HUNG_INT_RAW_S 2 +/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001U +#define I2S_TX_HUNG_INT_RAW_S 3 + +/** I2S_INT_ST_REG register + * I2S interrupt status register. + */ +#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) +/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S) +#define I2S_RX_DONE_INT_ST_V 0x00000001U +#define I2S_RX_DONE_INT_ST_S 0 +/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S) +#define I2S_TX_DONE_INT_ST_V 0x00000001U +#define I2S_TX_DONE_INT_ST_S 1 +/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001U +#define I2S_RX_HUNG_INT_ST_S 2 +/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001U +#define I2S_TX_HUNG_INT_ST_S 3 + +/** I2S_INT_ENA_REG register + * I2S interrupt enable register. + */ +#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) +/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S) +#define I2S_RX_DONE_INT_ENA_V 0x00000001U +#define I2S_RX_DONE_INT_ENA_S 0 +/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S) +#define I2S_TX_DONE_INT_ENA_V 0x00000001U +#define I2S_TX_DONE_INT_ENA_S 1 +/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001U +#define I2S_RX_HUNG_INT_ENA_S 2 +/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001U +#define I2S_TX_HUNG_INT_ENA_S 3 + +/** I2S_INT_CLR_REG register + * I2S interrupt clear register. + */ +#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) +/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S) +#define I2S_RX_DONE_INT_CLR_V 0x00000001U +#define I2S_RX_DONE_INT_CLR_S 0 +/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S) +#define I2S_TX_DONE_INT_CLR_V 0x00000001U +#define I2S_TX_DONE_INT_CLR_S 1 +/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001U +#define I2S_RX_HUNG_INT_CLR_S 2 +/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001U +#define I2S_TX_HUNG_INT_CLR_S 3 + +/** I2S_RX_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20) +/** I2S_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001U +#define I2S_RX_RESET_S 0 +/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001U +#define I2S_RX_FIFO_RESET_S 1 +/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001U +#define I2S_RX_START_S 2 +/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001U +#define I2S_RX_SLAVE_MOD_S 3 +/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ +#define I2S_RX_STOP_MODE 0x00000003U +#define I2S_RX_STOP_MODE_M (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S) +#define I2S_RX_STOP_MODE_V 0x00000003U +#define I2S_RX_STOP_MODE_S 4 +/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ +#define I2S_RX_MONO (BIT(6)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001U +#define I2S_RX_MONO_S 6 +/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001U +#define I2S_RX_BIG_ENDIAN_S 7 +/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S) +#define I2S_RX_UPDATE_V 0x00000001U +#define I2S_RX_UPDATE_S 8 +/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S) +#define I2S_RX_MONO_FST_VLD_V 0x00000001U +#define I2S_RX_MONO_FST_VLD_S 9 +/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_RX_PCM_CONF 0x00000003U +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000003U +#define I2S_RX_PCM_CONF_S 10 +/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001U +#define I2S_RX_PCM_BYPASS_S 12 +/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ +#define I2S_RX_MSB_SHIFT (BIT(13)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001U +#define I2S_RX_MSB_SHIFT_S 13 +/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S) +#define I2S_RX_LEFT_ALIGN_V 0x00000001U +#define I2S_RX_LEFT_ALIGN_S 15 +/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S) +#define I2S_RX_24_FILL_EN_V 0x00000001U +#define I2S_RX_24_FILL_EN_S 16 +/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S) +#define I2S_RX_WS_IDLE_POL_V 0x00000001U +#define I2S_RX_WS_IDLE_POL_S 17 +/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S) +#define I2S_RX_BIT_ORDER_V 0x00000001U +#define I2S_RX_BIT_ORDER_S 18 +/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S) +#define I2S_RX_TDM_EN_V 0x00000001U +#define I2S_RX_TDM_EN_S 19 +/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S) +#define I2S_RX_PDM_EN_V 0x00000001U +#define I2S_RX_PDM_EN_S 20 +/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ +#define I2S_RX_BCK_DIV_NUM 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_S 21 + +/** I2S_TX_CONF_REG register + * I2S TX configure register + */ +#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24) +/** I2S_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001U +#define I2S_TX_RESET_S 0 +/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001U +#define I2S_TX_FIFO_RESET_S 1 +/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001U +#define I2S_TX_START_S 2 +/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001U +#define I2S_TX_SLAVE_MOD_S 3 +/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ +#define I2S_TX_STOP_EN (BIT(4)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001U +#define I2S_TX_STOP_EN_S 4 +/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ +#define I2S_TX_CHAN_EQUAL (BIT(5)) +#define I2S_TX_CHAN_EQUAL_M (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S) +#define I2S_TX_CHAN_EQUAL_V 0x00000001U +#define I2S_TX_CHAN_EQUAL_S 5 +/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ +#define I2S_TX_MONO (BIT(6)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001U +#define I2S_TX_MONO_S 6 +/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001U +#define I2S_TX_BIG_ENDIAN_S 7 +/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S) +#define I2S_TX_UPDATE_V 0x00000001U +#define I2S_TX_UPDATE_S 8 +/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S) +#define I2S_TX_MONO_FST_VLD_V 0x00000001U +#define I2S_TX_MONO_FST_VLD_S 9 +/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_TX_PCM_CONF 0x00000003U +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000003U +#define I2S_TX_PCM_CONF_S 10 +/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001U +#define I2S_TX_PCM_BYPASS_S 12 +/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ +#define I2S_TX_MSB_SHIFT (BIT(13)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001U +#define I2S_TX_MSB_SHIFT_S 13 +/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ +#define I2S_TX_BCK_NO_DLY (BIT(14)) +#define I2S_TX_BCK_NO_DLY_M (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S) +#define I2S_TX_BCK_NO_DLY_V 0x00000001U +#define I2S_TX_BCK_NO_DLY_S 14 +/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S) +#define I2S_TX_LEFT_ALIGN_V 0x00000001U +#define I2S_TX_LEFT_ALIGN_S 15 +/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S) +#define I2S_TX_24_FILL_EN_V 0x00000001U +#define I2S_TX_24_FILL_EN_S 16 +/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S) +#define I2S_TX_WS_IDLE_POL_V 0x00000001U +#define I2S_TX_WS_IDLE_POL_S 17 +/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S) +#define I2S_TX_BIT_ORDER_V 0x00000001U +#define I2S_TX_BIT_ORDER_S 18 +/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S) +#define I2S_TX_TDM_EN_V 0x00000001U +#define I2S_TX_TDM_EN_S 19 +/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S) +#define I2S_TX_PDM_EN_V 0x00000001U +#define I2S_TX_PDM_EN_S 20 +/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ +#define I2S_TX_BCK_DIV_NUM 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_S 21 +/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ +#define I2S_TX_CHAN_MOD 0x00000007U +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007U +#define I2S_TX_CHAN_MOD_S 27 +/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ +#define I2S_SIG_LOOPBACK (BIT(30)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001U +#define I2S_SIG_LOOPBACK_S 30 + +/** I2S_RX_CONF1_REG register + * I2S RX configure register 1 + */ +#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28) +/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_RX_TDM_WS_WIDTH 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_M (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S) +#define I2S_RX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_S 0 +/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_RX_BITS_MOD 0x0000001FU +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000001FU +#define I2S_RX_BITS_MOD_S 14 +/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ +#define I2S_RX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_M (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_S 19 +/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ +#define I2S_RX_TDM_CHAN_BITS 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_M (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S) +#define I2S_RX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_CONF1_REG register + * I2S TX configure register 1 + */ +#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c) +/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_TX_TDM_WS_WIDTH 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_M (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S) +#define I2S_TX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_S 0 +/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_TX_BITS_MOD 0x0000001FU +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000001FU +#define I2S_TX_BITS_MOD_S 14 +/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ +#define I2S_TX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_M (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_S 19 +/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ +#define I2S_TX_TDM_CHAN_BITS 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_M (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S) +#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_PCM2PDM_CONF_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40) +/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_M (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S) +#define I2S_TX_PDM_SINC_OSR2_V 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_S 1 +/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ +#define I2S_TX_PDM_PRESCALE 0x000000FFU +#define I2S_TX_PDM_PRESCALE_M (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S) +#define I2S_TX_PDM_PRESCALE_V 0x000000FFU +#define I2S_TX_PDM_PRESCALE_S 5 +/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_M (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_M (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_M (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S) +#define I2S_PCM2PDM_CONV_EN_V 0x00000001U +#define I2S_PCM2PDM_CONV_EN_S 25 + +/** I2S_TX_PCM2PDM_CONF1_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44) +/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ +#define I2S_TX_PDM_FP 0x000003FFU +#define I2S_TX_PDM_FP_M (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S) +#define I2S_TX_PDM_FP_V 0x000003FFU +#define I2S_TX_PDM_FP_S 0 +/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ +#define I2S_TX_PDM_FS 0x000003FFU +#define I2S_TX_PDM_FS_M (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S) +#define I2S_TX_PDM_FS_V 0x000003FFU +#define I2S_TX_PDM_FS_S 10 +/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_M (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S) +#define I2S_TX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_M (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S) +#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_S 23 + +/** I2S_RX_PDM2PCM_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48) +/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ +#define I2S_RX_PDM2PCM_EN (BIT(19)) +#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S) +#define I2S_RX_PDM2PCM_EN_V 0x00000001U +#define I2S_RX_PDM2PCM_EN_S 19 +/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U +#define I2S_RX_PDM_SINC_DSR_16_EN_S 20 +/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ +#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S) +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21 +/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ +#define I2S_RX_PDM_HP_BYPASS (BIT(25)) +#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S) +#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U +#define I2S_RX_PDM_HP_BYPASS_S 25 +/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_RX_IIR_HP_MULT12_5 0x00000007U +#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S) +#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_RX_IIR_HP_MULT12_5_S 26 +/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_RX_IIR_HP_MULT12_0 0x00000007U +#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S) +#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_RX_IIR_HP_MULT12_0_S 29 + +/** I2S_RX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50) +/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S) +#define I2S_RX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN8_EN_S 8 +/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S) +#define I2S_RX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN9_EN_S 9 +/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S) +#define I2S_RX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN10_EN_S 10 +/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S) +#define I2S_RX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN11_EN_S 11 +/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S) +#define I2S_RX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN12_EN_S 12 +/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S) +#define I2S_RX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN13_EN_S 13 +/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S) +#define I2S_RX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN14_EN_S 14 +/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S) +#define I2S_RX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN15_EN_S 15 +/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_M (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 + +/** I2S_TX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54) +/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S) +#define I2S_TX_TDM_CHAN0_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN0_EN_S 0 +/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S) +#define I2S_TX_TDM_CHAN1_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN1_EN_S 1 +/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S) +#define I2S_TX_TDM_CHAN2_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN2_EN_S 2 +/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S) +#define I2S_TX_TDM_CHAN3_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN3_EN_S 3 +/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S) +#define I2S_TX_TDM_CHAN4_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN4_EN_S 4 +/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S) +#define I2S_TX_TDM_CHAN5_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN5_EN_S 5 +/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S) +#define I2S_TX_TDM_CHAN6_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN6_EN_S 6 +/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S) +#define I2S_TX_TDM_CHAN7_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN7_EN_S 7 +/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S) +#define I2S_TX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN8_EN_S 8 +/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S) +#define I2S_TX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN9_EN_S 9 +/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S) +#define I2S_TX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN10_EN_S 10 +/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S) +#define I2S_TX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN11_EN_S 11 +/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S) +#define I2S_TX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN12_EN_S 12 +/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S) +#define I2S_TX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN13_EN_S 13 +/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S) +#define I2S_TX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN14_EN_S 14 +/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S) +#define I2S_TX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN15_EN_S 15 +/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_M (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x00000001U +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 + +/** I2S_RX_TIMING_REG register + * I2S RX timing control register + */ +#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58) +/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD_IN_DM 0x00000003U +#define I2S_RX_SD_IN_DM_M (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S) +#define I2S_RX_SD_IN_DM_V 0x00000003U +#define I2S_RX_SD_IN_DM_S 0 +/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD1_IN_DM 0x00000003U +#define I2S_RX_SD1_IN_DM_M (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S) +#define I2S_RX_SD1_IN_DM_V 0x00000003U +#define I2S_RX_SD1_IN_DM_S 4 +/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0; + * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD2_IN_DM 0x00000003U +#define I2S_RX_SD2_IN_DM_M (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S) +#define I2S_RX_SD2_IN_DM_V 0x00000003U +#define I2S_RX_SD2_IN_DM_S 8 +/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0; + * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD3_IN_DM 0x00000003U +#define I2S_RX_SD3_IN_DM_M (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S) +#define I2S_RX_SD3_IN_DM_V 0x00000003U +#define I2S_RX_SD3_IN_DM_S 12 +/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_OUT_DM 0x00000003U +#define I2S_RX_WS_OUT_DM_M (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S) +#define I2S_RX_WS_OUT_DM_V 0x00000003U +#define I2S_RX_WS_OUT_DM_S 16 +/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_OUT_DM 0x00000003U +#define I2S_RX_BCK_OUT_DM_M (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S) +#define I2S_RX_BCK_OUT_DM_V 0x00000003U +#define I2S_RX_BCK_OUT_DM_S 20 +/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_IN_DM 0x00000003U +#define I2S_RX_WS_IN_DM_M (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S) +#define I2S_RX_WS_IN_DM_V 0x00000003U +#define I2S_RX_WS_IN_DM_S 24 +/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_IN_DM 0x00000003U +#define I2S_RX_BCK_IN_DM_M (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S) +#define I2S_RX_BCK_IN_DM_V 0x00000003U +#define I2S_RX_BCK_IN_DM_S 28 + +/** I2S_TX_TIMING_REG register + * I2S TX timing control register + */ +#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c) +/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD_OUT_DM 0x00000003U +#define I2S_TX_SD_OUT_DM_M (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S) +#define I2S_TX_SD_OUT_DM_V 0x00000003U +#define I2S_TX_SD_OUT_DM_S 0 +/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD1_OUT_DM 0x00000003U +#define I2S_TX_SD1_OUT_DM_M (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S) +#define I2S_TX_SD1_OUT_DM_V 0x00000003U +#define I2S_TX_SD1_OUT_DM_S 4 +/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_OUT_DM 0x00000003U +#define I2S_TX_WS_OUT_DM_M (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S) +#define I2S_TX_WS_OUT_DM_V 0x00000003U +#define I2S_TX_WS_OUT_DM_S 16 +/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_OUT_DM 0x00000003U +#define I2S_TX_BCK_OUT_DM_M (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S) +#define I2S_TX_BCK_OUT_DM_V 0x00000003U +#define I2S_TX_BCK_OUT_DM_S 20 +/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_IN_DM 0x00000003U +#define I2S_TX_WS_IN_DM_M (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S) +#define I2S_TX_WS_IN_DM_V 0x00000003U +#define I2S_TX_WS_IN_DM_S 24 +/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_IN_DM 0x00000003U +#define I2S_TX_BCK_IN_DM_M (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S) +#define I2S_TX_BCK_IN_DM_V 0x00000003U +#define I2S_TX_BCK_IN_DM_S 28 + +/** I2S_LC_HUNG_CONF_REG register + * I2S HUNG configure register. + */ +#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60) +/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_S 0 +/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/** I2S_RXEOF_NUM_REG register + * I2S RX data number control register. + */ +#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64) +/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ +#define I2S_RX_EOF_NUM 0x00000FFFU +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0x00000FFFU +#define I2S_RX_EOF_NUM_S 0 + +/** I2S_CONF_SIGLE_DATA_REG register + * I2S signal data register + */ +#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68) +/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ +#define I2S_SINGLE_DATA 0xFFFFFFFFU +#define I2S_SINGLE_DATA_M (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S) +#define I2S_SINGLE_DATA_V 0xFFFFFFFFU +#define I2S_SINGLE_DATA_S 0 + +/** I2S_STATE_REG register + * I2S TX status register + */ +#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c) +/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001U +#define I2S_TX_IDLE_S 0 + +/** I2S_ETM_CONF_REG register + * I2S ETM configure register + */ +#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70) +/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_TX_SEND_WORD_NUM 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_M (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S) +#define I2S_ETM_TX_SEND_WORD_NUM_V 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_S 0 +/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_RX_RECEIVE_WORD_NUM 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_M (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S) +#define I2S_ETM_RX_RECEIVE_WORD_NUM_V 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_S 10 + +/** I2S_FIFO_CNT_REG register + * I2S sync counter register + */ +#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74) +/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0; + * tx fifo counter value. + */ +#define I2S_TX_FIFO_CNT 0x7FFFFFFFU +#define I2S_TX_FIFO_CNT_M (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S) +#define I2S_TX_FIFO_CNT_V 0x7FFFFFFFU +#define I2S_TX_FIFO_CNT_S 0 +/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx fifo counter. + */ +#define I2S_TX_FIFO_CNT_RST (BIT(31)) +#define I2S_TX_FIFO_CNT_RST_M (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S) +#define I2S_TX_FIFO_CNT_RST_V 0x00000001U +#define I2S_TX_FIFO_CNT_RST_S 31 + +/** I2S_BCK_CNT_REG register + * I2S sync counter register + */ +#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78) +/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0; + * tx bck counter value. + */ +#define I2S_TX_BCK_CNT 0x7FFFFFFFU +#define I2S_TX_BCK_CNT_M (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S) +#define I2S_TX_BCK_CNT_V 0x7FFFFFFFU +#define I2S_TX_BCK_CNT_S 0 +/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx bck counter. + */ +#define I2S_TX_BCK_CNT_RST (BIT(31)) +#define I2S_TX_BCK_CNT_RST_M (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S) +#define I2S_TX_BCK_CNT_RST_V 0x00000001U +#define I2S_TX_BCK_CNT_RST_S 31 + +/** I2S_CLK_GATE_REG register + * Clock gate register + */ +#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c) +/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ +#define I2S_CLK_EN (BIT(0)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001U +#define I2S_CLK_EN_S 0 + +/** I2S_DATE_REG register + * Version control register + */ +#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80) +/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024; + * I2S version control register + */ +#define I2S_DATE 0x0FFFFFFFU +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0x0FFFFFFFU +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2s_struct.h b/components/soc/esp32c5/include/soc/i2s_struct.h new file mode 100644 index 00000000000..71fc30249ce --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2s_struct.h @@ -0,0 +1,1007 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt registers */ +/** Type of int_raw register + * I2S interrupt raw register, valid in level. + */ +typedef union { + struct { + /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_raw:1; + /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_raw:1; + /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_raw_reg_t; + +/** Type of int_st register + * I2S interrupt status register. + */ +typedef union { + struct { + /** rx_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_st_reg_t; + +/** Type of int_ena register + * I2S interrupt enable register. + */ +typedef union { + struct { + /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_ena_reg_t; + +/** Type of int_clr register + * I2S interrupt clear register. + */ +typedef union { + struct { + /** rx_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of rx_conf register + * I2S RX configure register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ + uint32_t rx_reset:1; + /** rx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ + uint32_t rx_fifo_reset:1; + /** rx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ + uint32_t rx_start:1; + /** rx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ + uint32_t rx_slave_mod:1; + /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ + uint32_t rx_stop_mode:2; + /** rx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ + uint32_t rx_mono:1; + /** rx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ + uint32_t rx_big_endian:1; + /** rx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t rx_update:1; + /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ + uint32_t rx_mono_fst_vld:1; + /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t rx_pcm_conf:2; + /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + uint32_t rx_pcm_bypass:1; + /** rx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ + uint32_t rx_msb_shift:1; + uint32_t reserved_14:1; + /** rx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ + uint32_t rx_left_align:1; + /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ + uint32_t rx_24_fill_en:1; + /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ + uint32_t rx_ws_idle_pol:1; + /** rx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ + uint32_t rx_bit_order:1; + /** rx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ + uint32_t rx_tdm_en:1; + /** rx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ + uint32_t rx_pdm_en:1; + /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + uint32_t rx_bck_div_num:6; + uint32_t reserved_27:5; + }; + uint32_t val; +} i2s_rx_conf_reg_t; + +/** Type of rx_conf1 register + * I2S RX configure register 1 + */ +typedef union { + struct { + /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t rx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t rx_bits_mod:5; + /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ + uint32_t rx_half_sample_bits:8; + /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ + uint32_t rx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_rx_conf1_reg_t; + +/** Type of rx_pdm2pcm_conf register + * I2S RX configure register + */ +typedef union { + struct { + uint32_t reserved_0:19; + /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ + uint32_t rx_pdm2pcm_en:1; + /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ + uint32_t rx_pdm_sinc_dsr_16_en:1; + /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ + uint32_t rx_pdm2pcm_amplify_num:4; + /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ + uint32_t rx_pdm_hp_bypass:1; + /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t rx_iir_hp_mult12_5:3; + /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t rx_iir_hp_mult12_0:3; + }; + uint32_t val; +} i2s_rx_pdm2pcm_conf_reg_t; + +/** Type of rx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan0_en:1; + /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan1_en:1; + /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan2_en:1; + /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan3_en:1; + /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan4_en:1; + /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan5_en:1; + /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan6_en:1; + /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan7_en:1; + /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan8_en:1; + /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan9_en:1; + /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan10_en:1; + /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan11_en:1; + /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan12_en:1; + /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan13_en:1; + /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan14_en:1; + /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan15_en:1; + /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t rx_tdm_tot_chan_num:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_rx_tdm_ctrl_reg_t; + +/** Type of rxeof_num register + * I2S RX data number control register. + */ +typedef union { + struct { + /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ + uint32_t rx_eof_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_rxeof_num_reg_t; + + +/** Group: TX Control and configuration registers */ +/** Type of tx_conf register + * I2S TX configure register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + uint32_t tx_reset:1; + /** tx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ + uint32_t tx_fifo_reset:1; + /** tx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ + uint32_t tx_start:1; + /** tx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ + uint32_t tx_slave_mod:1; + /** tx_stop_en : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ + uint32_t tx_stop_en:1; + /** tx_chan_equal : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ + uint32_t tx_chan_equal:1; + /** tx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + uint32_t tx_mono:1; + /** tx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ + uint32_t tx_big_endian:1; + /** tx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t tx_update:1; + /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ + uint32_t tx_mono_fst_vld:1; + /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t tx_pcm_conf:2; + /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + uint32_t tx_pcm_bypass:1; + /** tx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ + uint32_t tx_msb_shift:1; + /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ + uint32_t tx_bck_no_dly:1; + /** tx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ + uint32_t tx_left_align:1; + /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ + uint32_t tx_24_fill_en:1; + /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ + uint32_t tx_ws_idle_pol:1; + /** tx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ + uint32_t tx_bit_order:1; + /** tx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ + uint32_t tx_tdm_en:1; + /** tx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ + uint32_t tx_pdm_en:1; + /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + uint32_t tx_bck_div_num:6; + /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + uint32_t tx_chan_mod:3; + /** sig_loopback : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ + uint32_t sig_loopback:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2s_tx_conf_reg_t; + +/** Type of tx_conf1 register + * I2S TX configure register 1 + */ +typedef union { + struct { + /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t tx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t tx_bits_mod:5; + /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ + uint32_t tx_half_sample_bits:8; + /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ + uint32_t tx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_tx_conf1_reg_t; + +/** Type of tx_pcm2pdm_conf register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ + uint32_t tx_pdm_sinc_osr2:4; + /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ + uint32_t tx_pdm_prescale:8; + /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_hp_in_shift:2; + /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_lp_in_shift:2; + /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sinc_in_shift:2; + /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sigmadelta_in_shift:2; + /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ + uint32_t tx_pdm_sigmadelta_dither2:1; + /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ + uint32_t tx_pdm_sigmadelta_dither:1; + /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ + uint32_t tx_pdm_dac_2out_en:1; + /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ + uint32_t tx_pdm_dac_mode_en:1; + /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ + uint32_t pcm2pdm_conv_en:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf1 register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ + uint32_t tx_pdm_fp:10; + /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ + uint32_t tx_pdm_fs:10; + /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t tx_iir_hp_mult12_5:3; + /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t tx_iir_hp_mult12_0:3; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf1_reg_t; + +/** Type of tx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan0_en:1; + /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan1_en:1; + /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan2_en:1; + /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan3_en:1; + /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan4_en:1; + /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan5_en:1; + /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan6_en:1; + /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan7_en:1; + /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan8_en:1; + /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan9_en:1; + /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan10_en:1; + /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan11_en:1; + /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan12_en:1; + /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan13_en:1; + /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan14_en:1; + /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan15_en:1; + /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t tx_tdm_tot_chan_num:4; + /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ + uint32_t tx_tdm_skip_msk_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} i2s_tx_tdm_ctrl_reg_t; + + +/** Group: RX clock and timing registers */ +/** Type of rx_timing register + * I2S RX timing control register + */ +typedef union { + struct { + /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd_in_dm:2; + uint32_t reserved_2:2; + /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd1_in_dm:2; + uint32_t reserved_6:2; + /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0; + * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd2_in_dm:2; + uint32_t reserved_10:2; + /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0; + * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd3_in_dm:2; + uint32_t reserved_14:2; + /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_out_dm:2; + uint32_t reserved_18:2; + /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_out_dm:2; + uint32_t reserved_22:2; + /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_in_dm:2; + uint32_t reserved_26:2; + /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_timing_reg_t; + + +/** Group: TX clock and timing registers */ +/** Type of tx_timing register + * I2S TX timing control register + */ +typedef union { + struct { + /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd_out_dm:2; + uint32_t reserved_2:2; + /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd1_out_dm:2; + uint32_t reserved_6:10; + /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_out_dm:2; + uint32_t reserved_18:2; + /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_out_dm:2; + uint32_t reserved_22:2; + /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_in_dm:2; + uint32_t reserved_26:2; + /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_timing_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of lc_hung_conf register + * I2S HUNG configure register. + */ +typedef union { + struct { + /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ + uint32_t lc_fifo_timeout:8; + /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + uint32_t lc_fifo_timeout_shift:3; + /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + uint32_t lc_fifo_timeout_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_lc_hung_conf_reg_t; + +/** Type of conf_sigle_data register + * I2S signal data register + */ +typedef union { + struct { + /** single_data : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ + uint32_t single_data:32; + }; + uint32_t val; +} i2s_conf_sigle_data_reg_t; + + +/** Group: TX status registers */ +/** Type of state register + * I2S TX status register + */ +typedef union { + struct { + /** tx_idle : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ + uint32_t tx_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_state_reg_t; + + +/** Group: ETM registers */ +/** Type of etm_conf register + * I2S ETM configure register + */ +typedef union { + struct { + /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_tx_send_word_num:10; + /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_rx_receive_word_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_etm_conf_reg_t; + + +/** Group: Sync counter registers */ +/** Type of fifo_cnt register + * I2S sync counter register + */ +typedef union { + struct { + /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0; + * tx fifo counter value. + */ + uint32_t tx_fifo_cnt:31; + /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx fifo counter. + */ + uint32_t tx_fifo_cnt_rst:1; + }; + uint32_t val; +} i2s_fifo_cnt_reg_t; + +/** Type of bck_cnt register + * I2S sync counter register + */ +typedef union { + struct { + /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0; + * tx bck counter value. + */ + uint32_t tx_bck_cnt:31; + /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx bck counter. + */ + uint32_t tx_bck_cnt_rst:1; + }; + uint32_t val; +} i2s_bck_cnt_reg_t; + + +/** Group: Clock registers */ +/** Type of clk_gate register + * Clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_clk_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36713024; + * I2S version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_date_reg_t; + + +typedef struct i2s_dev_t { + uint32_t reserved_000[3]; + volatile i2s_int_raw_reg_t int_raw; + volatile i2s_int_st_reg_t int_st; + volatile i2s_int_ena_reg_t int_ena; + volatile i2s_int_clr_reg_t int_clr; + uint32_t reserved_01c; + volatile i2s_rx_conf_reg_t rx_conf; + volatile i2s_tx_conf_reg_t tx_conf; + volatile i2s_rx_conf1_reg_t rx_conf1; + volatile i2s_tx_conf1_reg_t tx_conf1; + uint32_t reserved_030[4]; + volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; + volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; + volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf; + uint32_t reserved_04c; + volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; + volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; + volatile i2s_rx_timing_reg_t rx_timing; + volatile i2s_tx_timing_reg_t tx_timing; + volatile i2s_lc_hung_conf_reg_t lc_hung_conf; + volatile i2s_rxeof_num_reg_t rxeof_num; + volatile i2s_conf_sigle_data_reg_t conf_sigle_data; + volatile i2s_state_reg_t state; + volatile i2s_etm_conf_reg_t etm_conf; + volatile i2s_fifo_cnt_reg_t fifo_cnt; + volatile i2s_bck_cnt_reg_t bck_cnt; + volatile i2s_clk_gate_reg_t clk_gate; + volatile i2s_date_reg_t date; +} i2s_dev_t; + +extern i2s_dev_t I2S0; + +#ifndef __cplusplus +_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h new file mode 100644 index 00000000000..81c3db3d25b --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h @@ -0,0 +1,1105 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register + * WIFI_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register + * WIFI_MAC_NMI mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register + * WIFI_PWR_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register + * WIFI_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register + * BT_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register + * BT_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register + * BT_BB_NMI mapping register + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register + * LP_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register + * COEX_INTR mapping register + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) +#define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register + * BLE_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register + * BLE_SEC_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register + * I2C_MST_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register + * ZB_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register + * PMU_INTR mapping register + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) +#define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register + * EFUSE_INTR mapping register + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register + * LP_RTC_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register + * LP_UART_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/** INTERRUPT_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_UART_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_M (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register + * LP_I2C_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/** INTERRUPT_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register + * LP_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register + * LP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register + * LP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register + * LP_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register + * HUK_INTR mapping register + */ +#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HUK_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HUK_INTR_MAP_M (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S) +#define INTERRUPT_CORE0_HUK_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HUK_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * CPU_INTR_FROM_CPU_1 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * CPU_INTR_FROM_CPU_2 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * CPU_INTR_FROM_CPU_3 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register + * ASSIST_DEBUG_INTR mapping register + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register + * TRACE_INTR mapping register + */ +#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TRACE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S) +#define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register + * CACHE_INTR mapping register + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * GPIO_INTERRUPT_PRO mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * GPIO_INTERRUPT_PRO_NMI mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG register + * GPIO_INTERRUPT_SD mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S 0 + +/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register + * PAU_INTR mapping register + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) +#define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register + * HP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register + * MODEM_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register + * HP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register + * HP_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register + * HP_APM_M2_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register + * HP_APM_M3_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register + * LP_APM0_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +/** INTERRUPT_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM0_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register + * MSPI_INTR mapping register + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register + * I2S1_INTR mapping register + */ +#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2S1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S) +#define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register + * UHCI0_INTR mapping register + */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register + * UART0_INTR mapping register + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) +#define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register + * UART1_INTR mapping register + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register + * LEDC_INTR mapping register + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register + * CAN0_INTR mapping register + */ +#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CAN0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INTR_MAP_M (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S) +#define INTERRUPT_CORE0_CAN0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CAN1_INTR_MAP_REG register + * CAN1_INTR mapping register + */ +#define INTERRUPT_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +/** INTERRUPT_CORE0_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CAN1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INTR_MAP_M (INTERRUPT_CORE0_CAN1_INTR_MAP_V << INTERRUPT_CORE0_CAN1_INTR_MAP_S) +#define INTERRUPT_CORE0_CAN1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_INTR_MAP_REG register + * USB_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register + * RMT_INTR mapping register + */ +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_RMT_INTR_MAP_M (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register + * I2C_EXT0_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register + * TG0_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register + * TG0_T1_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +/** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register + * TG0_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register + * TG1_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register + * TG1_T1_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +/** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register + * TG1_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register + * SYSTIMER_TARGET0_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register + * SYSTIMER_TARGET1_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register + * SYSTIMER_TARGET2_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register + * APB_ADC_INTR mapping register + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PWM_INTR_MAP_REG register + * PWM_INTR mapping register + */ +#define INTERRUPT_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +/** INTERRUPT_CORE0_PWM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PWM_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM_INTR_MAP_M (INTERRUPT_CORE0_PWM_INTR_MAP_V << INTERRUPT_CORE0_PWM_INTR_MAP_S) +#define INTERRUPT_CORE0_PWM_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PWM_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register + * PCNT_INTR mapping register + */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INTR_MAP_M (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register + * PARL_IO_TX_INTR mapping register + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register + * PARL_IO_RX_INTR mapping register + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register + * SLC0_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register + * SLC1_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG register + * USB_OTG20_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG register + * USB_OTG20_MULTI_PROC_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG register + * USB_OTG20_MISC_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register + * DMA_IN_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register + * DMA_IN_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register + * DMA_IN_CH2_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register + * DMA_OUT_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register + * DMA_OUT_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register + * DMA_OUT_CH2_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register + * GPSPI2_INTR mapping register + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_AES_INTR_MAP_REG register + * AES_INTR mapping register + */ +#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_AES_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_AES_INTR_MAP_M (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S) +#define INTERRUPT_CORE0_AES_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AES_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register + * SHA_INTR mapping register + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) +#define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register + * RSA_INTR mapping register + */ +#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_RSA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_RSA_INTR_MAP_M (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S) +#define INTERRUPT_CORE0_RSA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RSA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register + * ECC_INTR mapping register + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) +#define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register + * ECDSA_INTR mapping register + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_KM_INTR_MAP_REG register + * KM_INTR mapping register + */ +#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_KM_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_KM_INTR_MAP_M (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S) +#define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_KM_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register + * Status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_M (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S) +#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register + * Status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_M (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S) +#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register + * Status register for interrupt sources 64 ~ 95 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S) +#define INTERRUPT_CORE0_INT_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_S 0 + +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 + +/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36717104; + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_M (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h new file mode 100644 index 00000000000..4688fd1cc95 --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h @@ -0,0 +1,1385 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of wifi_mac_intr_map register + * WIFI_MAC_INTR mapping register + */ +typedef union { + struct { + /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_mac_intr_map_reg_t; + +/** Type of wifi_mac_nmi_map register + * WIFI_MAC_NMI mapping register + */ +typedef union { + struct { + /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_mac_nmi_map_reg_t; + +/** Type of wifi_pwr_intr_map register + * WIFI_PWR_INTR mapping register + */ +typedef union { + struct { + /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_pwr_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_pwr_intr_map_reg_t; + +/** Type of wifi_bb_intr_map register + * WIFI_BB_INTR mapping register + */ +typedef union { + struct { + /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_bb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_bb_intr_map_reg_t; + +/** Type of bt_mac_intr_map register + * BT_MAC_INTR mapping register + */ +typedef union { + struct { + /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_bt_mac_intr_map_reg_t; + +/** Type of bt_bb_intr_map register + * BT_BB_INTR mapping register + */ +typedef union { + struct { + /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_bt_bb_intr_map_reg_t; + +/** Type of bt_bb_nmi_map register + * BT_BB_NMI mapping register + */ +typedef union { + struct { + /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_bt_bb_nmi_map_reg_t; + +/** Type of lp_timer_intr_map register + * LP_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_timer_intr_map_reg_t; + +/** Type of coex_intr_map register + * COEX_INTR mapping register + */ +typedef union { + struct { + /** coex_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t coex_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_coex_intr_map_reg_t; + +/** Type of ble_timer_intr_map register + * BLE_TIMER_INTR mapping register + */ +typedef union { + struct { + /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ble_timer_intr_map_reg_t; + +/** Type of ble_sec_intr_map register + * BLE_SEC_INTR mapping register + */ +typedef union { + struct { + /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_sec_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ble_sec_intr_map_reg_t; + +/** Type of i2c_mst_intr_map register + * I2C_MST_INTR mapping register + */ +typedef union { + struct { + /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_mst_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c_mst_intr_map_reg_t; + +/** Type of zb_mac_intr_map register + * ZB_MAC_INTR mapping register + */ +typedef union { + struct { + /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t zb_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_zb_mac_intr_map_reg_t; + +/** Type of pmu_intr_map register + * PMU_INTR mapping register + */ +typedef union { + struct { + /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pmu_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmu_intr_map_reg_t; + +/** Type of efuse_intr_map register + * EFUSE_INTR mapping register + */ +typedef union { + struct { + /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t efuse_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_efuse_intr_map_reg_t; + +/** Type of lp_rtc_timer_intr_map register + * LP_RTC_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_rtc_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_rtc_timer_intr_map_reg_t; + +/** Type of lp_uart_intr_map register + * LP_UART_INTR mapping register + */ +typedef union { + struct { + /** lp_uart_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_uart_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_uart_intr_map_reg_t; + +/** Type of lp_i2c_intr_map register + * LP_I2C_INTR mapping register + */ +typedef union { + struct { + /** lp_i2c_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_i2c_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_i2c_intr_map_reg_t; + +/** Type of lp_wdt_intr_map register + * LP_WDT_INTR mapping register + */ +typedef union { + struct { + /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_wdt_intr_map_reg_t; + +/** Type of lp_peri_timeout_intr_map register + * LP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_peri_timeout_intr_map_reg_t; + +/** Type of lp_apm_m0_intr_map register + * LP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm_m0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_apm_m0_intr_map_reg_t; + +/** Type of lp_apm_m1_intr_map register + * LP_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** lp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm_m1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_apm_m1_intr_map_reg_t; + +/** Type of huk_intr_map register + * HUK_INTR mapping register + */ +typedef union { + struct { + /** huk_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t huk_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_huk_intr_map_reg_t; + +/** Type of cpu_intr_from_cpu_0_map register + * CPU_INTR_FROM_CPU_0 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t; + +/** Type of cpu_intr_from_cpu_1_map register + * CPU_INTR_FROM_CPU_1 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t; + +/** Type of cpu_intr_from_cpu_2_map register + * CPU_INTR_FROM_CPU_2 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t; + +/** Type of cpu_intr_from_cpu_3_map register + * CPU_INTR_FROM_CPU_3 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t; + +/** Type of assist_debug_intr_map register + * ASSIST_DEBUG_INTR mapping register + */ +typedef union { + struct { + /** assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t assist_debug_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_assist_debug_intr_map_reg_t; + +/** Type of trace_intr_map register + * TRACE_INTR mapping register + */ +typedef union { + struct { + /** trace_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t trace_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_trace_intr_map_reg_t; + +/** Type of cache_intr_map register + * CACHE_INTR mapping register + */ +typedef union { + struct { + /** cache_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cache_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cache_intr_map_reg_t; + +/** Type of cpu_peri_timeout_intr_map register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_peri_timeout_intr_map_reg_t; + +/** Type of gpio_interrupt_pro_map register + * GPIO_INTERRUPT_PRO mapping register + */ +typedef union { + struct { + /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_pro_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_pro_map_reg_t; + +/** Type of gpio_interrupt_pro_nmi_map register + * GPIO_INTERRUPT_PRO_NMI mapping register + */ +typedef union { + struct { + /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_pro_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_pro_nmi_map_reg_t; + +/** Type of gpio_interrupt_sd_map register + * GPIO_INTERRUPT_SD mapping register + */ +typedef union { + struct { + /** gpio_interrupt_sd_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_sd_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_sd_map_reg_t; + +/** Type of pau_intr_map register + * PAU_INTR mapping register + */ +typedef union { + struct { + /** pau_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pau_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pau_intr_map_reg_t; + +/** Type of hp_peri_timeout_intr_map register + * HP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_peri_timeout_intr_map_reg_t; + +/** Type of modem_peri_timeout_intr_map register + * MODEM_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t modem_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_modem_peri_timeout_intr_map_reg_t; + +/** Type of hp_apm_m0_intr_map register + * HP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m0_intr_map_reg_t; + +/** Type of hp_apm_m1_intr_map register + * HP_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m1_intr_map_reg_t; + +/** Type of hp_apm_m2_intr_map register + * HP_APM_M2_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m2_intr_map_reg_t; + +/** Type of hp_apm_m3_intr_map register + * HP_APM_M3_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m3_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m3_intr_map_reg_t; + +/** Type of lp_apm0_intr_map register + * LP_APM0_INTR mapping register + */ +typedef union { + struct { + /** lp_apm0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_apm0_intr_map_reg_t; + +/** Type of mspi_intr_map register + * MSPI_INTR mapping register + */ +typedef union { + struct { + /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t mspi_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_mspi_intr_map_reg_t; + +/** Type of i2s1_intr_map register + * I2S1_INTR mapping register + */ +typedef union { + struct { + /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2s1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s1_intr_map_reg_t; + +/** Type of uhci0_intr_map register + * UHCI0_INTR mapping register + */ +typedef union { + struct { + /** uhci0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uhci0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uhci0_intr_map_reg_t; + +/** Type of uart0_intr_map register + * UART0_INTR mapping register + */ +typedef union { + struct { + /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart0_intr_map_reg_t; + +/** Type of uart1_intr_map register + * UART1_INTR mapping register + */ +typedef union { + struct { + /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart1_intr_map_reg_t; + +/** Type of ledc_intr_map register + * LEDC_INTR mapping register + */ +typedef union { + struct { + /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ledc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ledc_intr_map_reg_t; + +/** Type of can0_intr_map register + * CAN0_INTR mapping register + */ +typedef union { + struct { + /** can0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t can0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can0_intr_map_reg_t; + +/** Type of can1_intr_map register + * CAN1_INTR mapping register + */ +typedef union { + struct { + /** can1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t can1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can1_intr_map_reg_t; + +/** Type of usb_intr_map register + * USB_INTR mapping register + */ +typedef union { + struct { + /** usb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_intr_map_reg_t; + +/** Type of rmt_intr_map register + * RMT_INTR mapping register + */ +typedef union { + struct { + /** rmt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t rmt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rmt_intr_map_reg_t; + +/** Type of i2c_ext0_intr_map register + * I2C_EXT0_INTR mapping register + */ +typedef union { + struct { + /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_ext0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c_ext0_intr_map_reg_t; + +/** Type of tg0_t0_intr_map register + * TG0_T0_INTR mapping register + */ +typedef union { + struct { + /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg0_t0_intr_map_reg_t; + +/** Type of tg0_t1_intr_map register + * TG0_T1_INTR mapping register + */ +typedef union { + struct { + /** tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg0_t1_intr_map_reg_t; + +/** Type of tg0_wdt_intr_map register + * TG0_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg0_wdt_intr_map_reg_t; + +/** Type of tg1_t0_intr_map register + * TG1_T0_INTR mapping register + */ +typedef union { + struct { + /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg1_t0_intr_map_reg_t; + +/** Type of tg1_t1_intr_map register + * TG1_T1_INTR mapping register + */ +typedef union { + struct { + /** tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg1_t1_intr_map_reg_t; + +/** Type of tg1_wdt_intr_map register + * TG1_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg1_wdt_intr_map_reg_t; + +/** Type of systimer_target0_intr_map register + * SYSTIMER_TARGET0_INTR mapping register + */ +typedef union { + struct { + /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target0_intr_map_reg_t; + +/** Type of systimer_target1_intr_map register + * SYSTIMER_TARGET1_INTR mapping register + */ +typedef union { + struct { + /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target1_intr_map_reg_t; + +/** Type of systimer_target2_intr_map register + * SYSTIMER_TARGET2_INTR mapping register + */ +typedef union { + struct { + /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target2_intr_map_reg_t; + +/** Type of apb_adc_intr_map register + * APB_ADC_INTR mapping register + */ +typedef union { + struct { + /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t apb_adc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_apb_adc_intr_map_reg_t; + +/** Type of pwm_intr_map register + * PWM_INTR mapping register + */ +typedef union { + struct { + /** pwm_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pwm_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pwm_intr_map_reg_t; + +/** Type of pcnt_intr_map register + * PCNT_INTR mapping register + */ +typedef union { + struct { + /** pcnt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pcnt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pcnt_intr_map_reg_t; + +/** Type of parl_io_tx_intr_map register + * PARL_IO_TX_INTR mapping register + */ +typedef union { + struct { + /** parl_io_tx_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t parl_io_tx_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_parl_io_tx_intr_map_reg_t; + +/** Type of parl_io_rx_intr_map register + * PARL_IO_RX_INTR mapping register + */ +typedef union { + struct { + /** parl_io_rx_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t parl_io_rx_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_parl_io_rx_intr_map_reg_t; + +/** Type of slc0_intr_map register + * SLC0_INTR mapping register + */ +typedef union { + struct { + /** slc0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t slc0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_slc0_intr_map_reg_t; + +/** Type of slc1_intr_map register + * SLC1_INTR mapping register + */ +typedef union { + struct { + /** slc1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t slc1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_slc1_intr_map_reg_t; + +/** Type of usb_otg20_intr_map register + * USB_OTG20_INTR mapping register + */ +typedef union { + struct { + /** usb_otg20_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg20_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg20_intr_map_reg_t; + +/** Type of usb_otg20_multi_proc_intr_map register + * USB_OTG20_MULTI_PROC_INTR mapping register + */ +typedef union { + struct { + /** usb_otg20_multi_proc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg20_multi_proc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg20_multi_proc_intr_map_reg_t; + +/** Type of usb_otg20_misc_intr_map register + * USB_OTG20_MISC_INTR mapping register + */ +typedef union { + struct { + /** usb_otg20_misc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg20_misc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg20_misc_intr_map_reg_t; + +/** Type of dma_in_ch0_intr_map register + * DMA_IN_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_in_ch0_intr_map_reg_t; + +/** Type of dma_in_ch1_intr_map register + * DMA_IN_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_in_ch1_intr_map_reg_t; + +/** Type of dma_in_ch2_intr_map register + * DMA_IN_CH2_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_in_ch2_intr_map_reg_t; + +/** Type of dma_out_ch0_intr_map register + * DMA_OUT_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_out_ch0_intr_map_reg_t; + +/** Type of dma_out_ch1_intr_map register + * DMA_OUT_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_out_ch1_intr_map_reg_t; + +/** Type of dma_out_ch2_intr_map register + * DMA_OUT_CH2_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_out_ch2_intr_map_reg_t; + +/** Type of gpspi2_intr_map register + * GPSPI2_INTR mapping register + */ +typedef union { + struct { + /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpspi2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpspi2_intr_map_reg_t; + +/** Type of aes_intr_map register + * AES_INTR mapping register + */ +typedef union { + struct { + /** aes_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t aes_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_aes_intr_map_reg_t; + +/** Type of sha_intr_map register + * SHA_INTR mapping register + */ +typedef union { + struct { + /** sha_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t sha_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sha_intr_map_reg_t; + +/** Type of rsa_intr_map register + * RSA_INTR mapping register + */ +typedef union { + struct { + /** rsa_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t rsa_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rsa_intr_map_reg_t; + +/** Type of ecc_intr_map register + * ECC_INTR mapping register + */ +typedef union { + struct { + /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecc_intr_map_reg_t; + +/** Type of ecdsa_intr_map register + * ECDSA_INTR mapping register + */ +typedef union { + struct { + /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecdsa_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecdsa_intr_map_reg_t; + +/** Type of km_intr_map register + * KM_INTR mapping register + */ +typedef union { + struct { + /** km_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t km_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_km_intr_map_reg_t; + +/** Type of int_status_reg_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_0_reg_t; + +/** Type of int_status_reg_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_1_reg_t; + +/** Type of int_status_reg_2 register + * Status register for interrupt sources 64 ~ 95 + */ +typedef union { + struct { + /** int_status_2 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_2:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_2_reg_t; + +/** Type of clock_gate register + * Interrupt clock gating configure register + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: Version Register */ +/** Type of interrupt_date register + * Version control register + */ +typedef union { + struct { + /** interrupt_date : R/W; bitpos: [27:0]; default: 36717104; + * Version control register + */ + uint32_t interrupt_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core0_interrupt_date_reg_t; + + +typedef struct intmtx_core0_dev_t { + volatile interrupt_core0_wifi_mac_intr_map_reg_t wifi_mac_intr_map; + volatile interrupt_core0_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; + volatile interrupt_core0_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; + volatile interrupt_core0_wifi_bb_intr_map_reg_t wifi_bb_intr_map; + volatile interrupt_core0_bt_mac_intr_map_reg_t bt_mac_intr_map; + volatile interrupt_core0_bt_bb_intr_map_reg_t bt_bb_intr_map; + volatile interrupt_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map; + volatile interrupt_core0_lp_timer_intr_map_reg_t lp_timer_intr_map; + volatile interrupt_core0_coex_intr_map_reg_t coex_intr_map; + volatile interrupt_core0_ble_timer_intr_map_reg_t ble_timer_intr_map; + volatile interrupt_core0_ble_sec_intr_map_reg_t ble_sec_intr_map; + volatile interrupt_core0_i2c_mst_intr_map_reg_t i2c_mst_intr_map; + volatile interrupt_core0_zb_mac_intr_map_reg_t zb_mac_intr_map; + volatile interrupt_core0_pmu_intr_map_reg_t pmu_intr_map; + volatile interrupt_core0_efuse_intr_map_reg_t efuse_intr_map; + volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; + volatile interrupt_core0_lp_uart_intr_map_reg_t lp_uart_intr_map; + volatile interrupt_core0_lp_i2c_intr_map_reg_t lp_i2c_intr_map; + volatile interrupt_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map; + volatile interrupt_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; + volatile interrupt_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; + volatile interrupt_core0_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map; + volatile interrupt_core0_huk_intr_map_reg_t huk_intr_map; + volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; + volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; + volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; + volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; + volatile interrupt_core0_assist_debug_intr_map_reg_t assist_debug_intr_map; + volatile interrupt_core0_trace_intr_map_reg_t trace_intr_map; + volatile interrupt_core0_cache_intr_map_reg_t cache_intr_map; + volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; + volatile interrupt_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; + volatile interrupt_core0_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map; + volatile interrupt_core0_gpio_interrupt_sd_map_reg_t gpio_interrupt_sd_map; + volatile interrupt_core0_pau_intr_map_reg_t pau_intr_map; + volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; + volatile interrupt_core0_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; + volatile interrupt_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; + volatile interrupt_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; + volatile interrupt_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; + volatile interrupt_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; + volatile interrupt_core0_lp_apm0_intr_map_reg_t lp_apm0_intr_map; + volatile interrupt_core0_mspi_intr_map_reg_t mspi_intr_map; + volatile interrupt_core0_i2s1_intr_map_reg_t i2s1_intr_map; + volatile interrupt_core0_uhci0_intr_map_reg_t uhci0_intr_map; + volatile interrupt_core0_uart0_intr_map_reg_t uart0_intr_map; + volatile interrupt_core0_uart1_intr_map_reg_t uart1_intr_map; + volatile interrupt_core0_ledc_intr_map_reg_t ledc_intr_map; + volatile interrupt_core0_can0_intr_map_reg_t can0_intr_map; + volatile interrupt_core0_can1_intr_map_reg_t can1_intr_map; + volatile interrupt_core0_usb_intr_map_reg_t usb_intr_map; + volatile interrupt_core0_rmt_intr_map_reg_t rmt_intr_map; + volatile interrupt_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; + volatile interrupt_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map; + volatile interrupt_core0_tg0_t1_intr_map_reg_t tg0_t1_intr_map; + volatile interrupt_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; + volatile interrupt_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map; + volatile interrupt_core0_tg1_t1_intr_map_reg_t tg1_t1_intr_map; + volatile interrupt_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; + volatile interrupt_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map; + volatile interrupt_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map; + volatile interrupt_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map; + volatile interrupt_core0_apb_adc_intr_map_reg_t apb_adc_intr_map; + volatile interrupt_core0_pwm_intr_map_reg_t pwm_intr_map; + volatile interrupt_core0_pcnt_intr_map_reg_t pcnt_intr_map; + volatile interrupt_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map; + volatile interrupt_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map; + volatile interrupt_core0_slc0_intr_map_reg_t slc0_intr_map; + volatile interrupt_core0_slc1_intr_map_reg_t slc1_intr_map; + volatile interrupt_core0_usb_otg20_intr_map_reg_t usb_otg20_intr_map; + volatile interrupt_core0_usb_otg20_multi_proc_intr_map_reg_t usb_otg20_multi_proc_intr_map; + volatile interrupt_core0_usb_otg20_misc_intr_map_reg_t usb_otg20_misc_intr_map; + volatile interrupt_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; + volatile interrupt_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; + volatile interrupt_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; + volatile interrupt_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; + volatile interrupt_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; + volatile interrupt_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map; + volatile interrupt_core0_gpspi2_intr_map_reg_t gpspi2_intr_map; + volatile interrupt_core0_aes_intr_map_reg_t aes_intr_map; + volatile interrupt_core0_sha_intr_map_reg_t sha_intr_map; + volatile interrupt_core0_rsa_intr_map_reg_t rsa_intr_map; + volatile interrupt_core0_ecc_intr_map_reg_t ecc_intr_map; + volatile interrupt_core0_ecdsa_intr_map_reg_t ecdsa_intr_map; + volatile interrupt_core0_km_intr_map_reg_t km_intr_map; + volatile interrupt_core0_int_status_reg_0_reg_t int_status_reg_0; + volatile interrupt_core0_int_status_reg_1_reg_t int_status_reg_1; + volatile interrupt_core0_int_status_reg_2_reg_t int_status_reg_2; + volatile interrupt_core0_clock_gate_reg_t clock_gate; + uint32_t reserved_164[422]; + volatile interrupt_core0_interrupt_date_reg_t interrupt_date; +} interrupt_core0_dev_t; + +extern intmtx_core0_dev_t INTMTX; + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core0_dev_t) == 0x800, "Invalid size of interrupt_core0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/interrupt_reg.h b/components/soc/esp32c5/include/soc/interrupt_reg.h new file mode 100644 index 00000000000..c2ee2f9e2f6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupt_reg.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/reg_base.h" +#include "soc/interrupt_matrix_reg.h" +#include "soc/clic_reg.h" +#include "soc/soc_caps.h" + +/** + * ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y) + * + * The memory map for interrupt registers is on a per-core basis, CLIC_INT_THRESH_REG points to + * the current core interrupt register, whereas CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF points + * to the other core registers, regardless of the core we are currently running on. + */ +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG) +#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF) + +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG diff --git a/components/soc/esp32c5/include/soc/interrupts.h b/components/soc/esp32c5/include/soc/interrupts.h new file mode 100644 index 00000000000..c3fce379970 --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupts.h @@ -0,0 +1,106 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from C6) + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_ZB_MAC_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_UART_INTR_SOURCE, + ETS_LP_I2C_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_LP_APM_M1_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_LP_APM0_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/ + ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */ + ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */ + ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */ + ETS_APB_ADC_INTR_SOURCE = 60, /**< interrupt of APB ADC, LEVEL*/ + ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/ + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_INTR_SOURCE, + ETS_SLC0_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ + ETS_GSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/intpri_reg.h b/components/soc/esp32c5/include/soc/intpri_reg.h new file mode 100644 index 00000000000..67aa1c8cff0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/intpri_reg.h @@ -0,0 +1,88 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTPRI_CPU_INTR_FROM_CPU_0_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90) +/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S) +#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_0_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_1_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94) +/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S) +#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_1_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_2_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98) +/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S) +#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_2_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_3_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c) +/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S) +#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_3_S 0 + +/** INTPRI_DATE_REG register + * register description + */ +#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0) +/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784; + * Need add description + */ +#define INTPRI_DATE 0x0FFFFFFFU +#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S) +#define INTPRI_DATE_V 0x0FFFFFFFU +#define INTPRI_DATE_S 0 + +/** INTPRI_CLOCK_GATE_REG register + * register description + */ +#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4) +/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTPRI_CLK_EN (BIT(0)) +#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S) +#define INTPRI_CLK_EN_V 0x00000001U +#define INTPRI_CLK_EN_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/intpri_struct.h b/components/soc/esp32c5/include/soc/intpri_struct.h new file mode 100644 index 00000000000..460811245d8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/intpri_struct.h @@ -0,0 +1,121 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of cpu_intr_from_cpu_0 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_0_reg_t; + +/** Type of cpu_intr_from_cpu_1 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_1_reg_t; + +/** Type of cpu_intr_from_cpu_2 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_2:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_2_reg_t; + +/** Type of cpu_intr_from_cpu_3 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_3:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_3_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * register description + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36712784; + * Need add description + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} intpri_date_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_clock_gate_reg_t; + + +typedef struct intpri_dev_t { + uint32_t reserved_000[36]; + volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; + volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; + volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; + volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; + volatile intpri_date_reg_t date; + volatile intpri_clock_gate_reg_t clock_gate; +} intpri_dev_t; + +extern intpri_dev_t INTPRI; + +#ifndef __cplusplus +_Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/io_mux_reg.h b/components/soc/esp32c5/include/soc/io_mux_reg.h new file mode 100644 index 00000000000..f97e3c0b445 --- /dev/null +++ b/components/soc/esp32c5/include/soc/io_mux_reg.h @@ -0,0 +1,3054 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** IO_MUX_PIN_CTRL_REG register + * Clock Output Configuration Register + */ +#define IO_MUX_PIN_CTRL_REG (DR_REG_IO_MUX_BASE + 0x0) +/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT1 0x0000001FU +#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S) +#define IO_MUX_CLK_OUT1_V 0x0000001FU +#define IO_MUX_CLK_OUT1_S 0 +/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT2 0x0000001FU +#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S) +#define IO_MUX_CLK_OUT2_V 0x0000001FU +#define IO_MUX_CLK_OUT2_S 5 +/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT3 0x0000001FU +#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S) +#define IO_MUX_CLK_OUT3_V 0x0000001FU +#define IO_MUX_CLK_OUT3_S 10 + +/** IO_MUX_GPIO0_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4) +/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO0_MCU_OE (BIT(0)) +#define IO_MUX_GPIO0_MCU_OE_M (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S) +#define IO_MUX_GPIO0_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO0_MCU_OE_S 0 +/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO0_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO0_SLP_SEL_M (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S) +#define IO_MUX_GPIO0_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO0_SLP_SEL_S 1 +/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO0_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO0_MCU_WPD_M (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S) +#define IO_MUX_GPIO0_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO0_MCU_WPD_S 2 +/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO0_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO0_MCU_WPU_M (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S) +#define IO_MUX_GPIO0_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO0_MCU_WPU_S 3 +/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO0_MCU_IE (BIT(4)) +#define IO_MUX_GPIO0_MCU_IE_M (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S) +#define IO_MUX_GPIO0_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO0_MCU_IE_S 4 +/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO0_MCU_DRV 0x00000003U +#define IO_MUX_GPIO0_MCU_DRV_M (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S) +#define IO_MUX_GPIO0_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO0_MCU_DRV_S 5 +/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO0_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO0_FUN_WPD_M (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S) +#define IO_MUX_GPIO0_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO0_FUN_WPD_S 7 +/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO0_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO0_FUN_WPU_M (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S) +#define IO_MUX_GPIO0_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO0_FUN_WPU_S 8 +/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO0_FUN_IE (BIT(9)) +#define IO_MUX_GPIO0_FUN_IE_M (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S) +#define IO_MUX_GPIO0_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO0_FUN_IE_S 9 +/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO0_FUN_DRV 0x00000003U +#define IO_MUX_GPIO0_FUN_DRV_M (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S) +#define IO_MUX_GPIO0_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO0_FUN_DRV_S 10 +/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO0_MCU_SEL 0x00000007U +#define IO_MUX_GPIO0_MCU_SEL_M (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S) +#define IO_MUX_GPIO0_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO0_MCU_SEL_S 12 +/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO0_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO0_FILTER_EN_M (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S) +#define IO_MUX_GPIO0_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO0_FILTER_EN_S 15 +/** IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO0_HYS_EN (BIT(16)) +#define IO_MUX_GPIO0_HYS_EN_M (IO_MUX_GPIO0_HYS_EN_V << IO_MUX_GPIO0_HYS_EN_S) +#define IO_MUX_GPIO0_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO0_HYS_EN_S 16 +/** IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO0_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO0_HYS_SEL_M (IO_MUX_GPIO0_HYS_SEL_V << IO_MUX_GPIO0_HYS_SEL_S) +#define IO_MUX_GPIO0_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO0_HYS_SEL_S 17 + +/** IO_MUX_GPIO1_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8) +/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO1_MCU_OE (BIT(0)) +#define IO_MUX_GPIO1_MCU_OE_M (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S) +#define IO_MUX_GPIO1_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO1_MCU_OE_S 0 +/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO1_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO1_SLP_SEL_M (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S) +#define IO_MUX_GPIO1_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO1_SLP_SEL_S 1 +/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO1_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO1_MCU_WPD_M (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S) +#define IO_MUX_GPIO1_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO1_MCU_WPD_S 2 +/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO1_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO1_MCU_WPU_M (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S) +#define IO_MUX_GPIO1_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO1_MCU_WPU_S 3 +/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO1_MCU_IE (BIT(4)) +#define IO_MUX_GPIO1_MCU_IE_M (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S) +#define IO_MUX_GPIO1_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO1_MCU_IE_S 4 +/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO1_MCU_DRV 0x00000003U +#define IO_MUX_GPIO1_MCU_DRV_M (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S) +#define IO_MUX_GPIO1_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO1_MCU_DRV_S 5 +/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO1_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO1_FUN_WPD_M (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S) +#define IO_MUX_GPIO1_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO1_FUN_WPD_S 7 +/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO1_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO1_FUN_WPU_M (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S) +#define IO_MUX_GPIO1_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO1_FUN_WPU_S 8 +/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO1_FUN_IE (BIT(9)) +#define IO_MUX_GPIO1_FUN_IE_M (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S) +#define IO_MUX_GPIO1_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO1_FUN_IE_S 9 +/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO1_FUN_DRV 0x00000003U +#define IO_MUX_GPIO1_FUN_DRV_M (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S) +#define IO_MUX_GPIO1_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO1_FUN_DRV_S 10 +/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO1_MCU_SEL 0x00000007U +#define IO_MUX_GPIO1_MCU_SEL_M (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S) +#define IO_MUX_GPIO1_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO1_MCU_SEL_S 12 +/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO1_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO1_FILTER_EN_M (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S) +#define IO_MUX_GPIO1_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO1_FILTER_EN_S 15 +/** IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO1_HYS_EN (BIT(16)) +#define IO_MUX_GPIO1_HYS_EN_M (IO_MUX_GPIO1_HYS_EN_V << IO_MUX_GPIO1_HYS_EN_S) +#define IO_MUX_GPIO1_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO1_HYS_EN_S 16 +/** IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO1_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO1_HYS_SEL_M (IO_MUX_GPIO1_HYS_SEL_V << IO_MUX_GPIO1_HYS_SEL_S) +#define IO_MUX_GPIO1_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO1_HYS_SEL_S 17 + +/** IO_MUX_GPIO2_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc) +/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO2_MCU_OE (BIT(0)) +#define IO_MUX_GPIO2_MCU_OE_M (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S) +#define IO_MUX_GPIO2_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO2_MCU_OE_S 0 +/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO2_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO2_SLP_SEL_M (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S) +#define IO_MUX_GPIO2_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO2_SLP_SEL_S 1 +/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO2_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO2_MCU_WPD_M (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S) +#define IO_MUX_GPIO2_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO2_MCU_WPD_S 2 +/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO2_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO2_MCU_WPU_M (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S) +#define IO_MUX_GPIO2_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO2_MCU_WPU_S 3 +/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO2_MCU_IE (BIT(4)) +#define IO_MUX_GPIO2_MCU_IE_M (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S) +#define IO_MUX_GPIO2_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO2_MCU_IE_S 4 +/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO2_MCU_DRV 0x00000003U +#define IO_MUX_GPIO2_MCU_DRV_M (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S) +#define IO_MUX_GPIO2_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO2_MCU_DRV_S 5 +/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO2_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO2_FUN_WPD_M (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S) +#define IO_MUX_GPIO2_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO2_FUN_WPD_S 7 +/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO2_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO2_FUN_WPU_M (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S) +#define IO_MUX_GPIO2_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO2_FUN_WPU_S 8 +/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO2_FUN_IE (BIT(9)) +#define IO_MUX_GPIO2_FUN_IE_M (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S) +#define IO_MUX_GPIO2_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO2_FUN_IE_S 9 +/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO2_FUN_DRV 0x00000003U +#define IO_MUX_GPIO2_FUN_DRV_M (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S) +#define IO_MUX_GPIO2_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO2_FUN_DRV_S 10 +/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO2_MCU_SEL 0x00000007U +#define IO_MUX_GPIO2_MCU_SEL_M (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S) +#define IO_MUX_GPIO2_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO2_MCU_SEL_S 12 +/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO2_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO2_FILTER_EN_M (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S) +#define IO_MUX_GPIO2_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO2_FILTER_EN_S 15 +/** IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO2_HYS_EN (BIT(16)) +#define IO_MUX_GPIO2_HYS_EN_M (IO_MUX_GPIO2_HYS_EN_V << IO_MUX_GPIO2_HYS_EN_S) +#define IO_MUX_GPIO2_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO2_HYS_EN_S 16 +/** IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO2_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO2_HYS_SEL_M (IO_MUX_GPIO2_HYS_SEL_V << IO_MUX_GPIO2_HYS_SEL_S) +#define IO_MUX_GPIO2_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO2_HYS_SEL_S 17 + +/** IO_MUX_GPIO3_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10) +/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO3_MCU_OE (BIT(0)) +#define IO_MUX_GPIO3_MCU_OE_M (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S) +#define IO_MUX_GPIO3_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO3_MCU_OE_S 0 +/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO3_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO3_SLP_SEL_M (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S) +#define IO_MUX_GPIO3_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO3_SLP_SEL_S 1 +/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO3_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO3_MCU_WPD_M (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S) +#define IO_MUX_GPIO3_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO3_MCU_WPD_S 2 +/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO3_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO3_MCU_WPU_M (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S) +#define IO_MUX_GPIO3_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO3_MCU_WPU_S 3 +/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO3_MCU_IE (BIT(4)) +#define IO_MUX_GPIO3_MCU_IE_M (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S) +#define IO_MUX_GPIO3_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO3_MCU_IE_S 4 +/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO3_MCU_DRV 0x00000003U +#define IO_MUX_GPIO3_MCU_DRV_M (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S) +#define IO_MUX_GPIO3_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO3_MCU_DRV_S 5 +/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO3_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO3_FUN_WPD_M (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S) +#define IO_MUX_GPIO3_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO3_FUN_WPD_S 7 +/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO3_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO3_FUN_WPU_M (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S) +#define IO_MUX_GPIO3_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO3_FUN_WPU_S 8 +/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO3_FUN_IE (BIT(9)) +#define IO_MUX_GPIO3_FUN_IE_M (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S) +#define IO_MUX_GPIO3_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO3_FUN_IE_S 9 +/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO3_FUN_DRV 0x00000003U +#define IO_MUX_GPIO3_FUN_DRV_M (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S) +#define IO_MUX_GPIO3_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO3_FUN_DRV_S 10 +/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO3_MCU_SEL 0x00000007U +#define IO_MUX_GPIO3_MCU_SEL_M (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S) +#define IO_MUX_GPIO3_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO3_MCU_SEL_S 12 +/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO3_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO3_FILTER_EN_M (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S) +#define IO_MUX_GPIO3_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO3_FILTER_EN_S 15 +/** IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO3_HYS_EN (BIT(16)) +#define IO_MUX_GPIO3_HYS_EN_M (IO_MUX_GPIO3_HYS_EN_V << IO_MUX_GPIO3_HYS_EN_S) +#define IO_MUX_GPIO3_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO3_HYS_EN_S 16 +/** IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO3_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO3_HYS_SEL_M (IO_MUX_GPIO3_HYS_SEL_V << IO_MUX_GPIO3_HYS_SEL_S) +#define IO_MUX_GPIO3_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO3_HYS_SEL_S 17 + +/** IO_MUX_GPIO4_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14) +/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO4_MCU_OE (BIT(0)) +#define IO_MUX_GPIO4_MCU_OE_M (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S) +#define IO_MUX_GPIO4_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO4_MCU_OE_S 0 +/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO4_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO4_SLP_SEL_M (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S) +#define IO_MUX_GPIO4_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO4_SLP_SEL_S 1 +/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO4_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO4_MCU_WPD_M (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S) +#define IO_MUX_GPIO4_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO4_MCU_WPD_S 2 +/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO4_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO4_MCU_WPU_M (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S) +#define IO_MUX_GPIO4_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO4_MCU_WPU_S 3 +/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO4_MCU_IE (BIT(4)) +#define IO_MUX_GPIO4_MCU_IE_M (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S) +#define IO_MUX_GPIO4_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO4_MCU_IE_S 4 +/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO4_MCU_DRV 0x00000003U +#define IO_MUX_GPIO4_MCU_DRV_M (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S) +#define IO_MUX_GPIO4_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO4_MCU_DRV_S 5 +/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO4_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO4_FUN_WPD_M (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S) +#define IO_MUX_GPIO4_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO4_FUN_WPD_S 7 +/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO4_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO4_FUN_WPU_M (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S) +#define IO_MUX_GPIO4_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO4_FUN_WPU_S 8 +/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO4_FUN_IE (BIT(9)) +#define IO_MUX_GPIO4_FUN_IE_M (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S) +#define IO_MUX_GPIO4_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO4_FUN_IE_S 9 +/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO4_FUN_DRV 0x00000003U +#define IO_MUX_GPIO4_FUN_DRV_M (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S) +#define IO_MUX_GPIO4_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO4_FUN_DRV_S 10 +/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO4_MCU_SEL 0x00000007U +#define IO_MUX_GPIO4_MCU_SEL_M (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S) +#define IO_MUX_GPIO4_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO4_MCU_SEL_S 12 +/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO4_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO4_FILTER_EN_M (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S) +#define IO_MUX_GPIO4_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO4_FILTER_EN_S 15 +/** IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO4_HYS_EN (BIT(16)) +#define IO_MUX_GPIO4_HYS_EN_M (IO_MUX_GPIO4_HYS_EN_V << IO_MUX_GPIO4_HYS_EN_S) +#define IO_MUX_GPIO4_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO4_HYS_EN_S 16 +/** IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO4_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO4_HYS_SEL_M (IO_MUX_GPIO4_HYS_SEL_V << IO_MUX_GPIO4_HYS_SEL_S) +#define IO_MUX_GPIO4_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO4_HYS_SEL_S 17 + +/** IO_MUX_GPIO5_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18) +/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO5_MCU_OE (BIT(0)) +#define IO_MUX_GPIO5_MCU_OE_M (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S) +#define IO_MUX_GPIO5_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO5_MCU_OE_S 0 +/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO5_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO5_SLP_SEL_M (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S) +#define IO_MUX_GPIO5_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO5_SLP_SEL_S 1 +/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO5_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO5_MCU_WPD_M (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S) +#define IO_MUX_GPIO5_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO5_MCU_WPD_S 2 +/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO5_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO5_MCU_WPU_M (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S) +#define IO_MUX_GPIO5_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO5_MCU_WPU_S 3 +/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO5_MCU_IE (BIT(4)) +#define IO_MUX_GPIO5_MCU_IE_M (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S) +#define IO_MUX_GPIO5_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO5_MCU_IE_S 4 +/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO5_MCU_DRV 0x00000003U +#define IO_MUX_GPIO5_MCU_DRV_M (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S) +#define IO_MUX_GPIO5_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO5_MCU_DRV_S 5 +/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO5_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO5_FUN_WPD_M (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S) +#define IO_MUX_GPIO5_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO5_FUN_WPD_S 7 +/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO5_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO5_FUN_WPU_M (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S) +#define IO_MUX_GPIO5_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO5_FUN_WPU_S 8 +/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO5_FUN_IE (BIT(9)) +#define IO_MUX_GPIO5_FUN_IE_M (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S) +#define IO_MUX_GPIO5_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO5_FUN_IE_S 9 +/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO5_FUN_DRV 0x00000003U +#define IO_MUX_GPIO5_FUN_DRV_M (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S) +#define IO_MUX_GPIO5_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO5_FUN_DRV_S 10 +/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO5_MCU_SEL 0x00000007U +#define IO_MUX_GPIO5_MCU_SEL_M (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S) +#define IO_MUX_GPIO5_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO5_MCU_SEL_S 12 +/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO5_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO5_FILTER_EN_M (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S) +#define IO_MUX_GPIO5_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO5_FILTER_EN_S 15 +/** IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO5_HYS_EN (BIT(16)) +#define IO_MUX_GPIO5_HYS_EN_M (IO_MUX_GPIO5_HYS_EN_V << IO_MUX_GPIO5_HYS_EN_S) +#define IO_MUX_GPIO5_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO5_HYS_EN_S 16 +/** IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO5_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO5_HYS_SEL_M (IO_MUX_GPIO5_HYS_SEL_V << IO_MUX_GPIO5_HYS_SEL_S) +#define IO_MUX_GPIO5_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO5_HYS_SEL_S 17 + +/** IO_MUX_GPIO6_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c) +/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO6_MCU_OE (BIT(0)) +#define IO_MUX_GPIO6_MCU_OE_M (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S) +#define IO_MUX_GPIO6_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO6_MCU_OE_S 0 +/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO6_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO6_SLP_SEL_M (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S) +#define IO_MUX_GPIO6_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO6_SLP_SEL_S 1 +/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO6_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO6_MCU_WPD_M (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S) +#define IO_MUX_GPIO6_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO6_MCU_WPD_S 2 +/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO6_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO6_MCU_WPU_M (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S) +#define IO_MUX_GPIO6_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO6_MCU_WPU_S 3 +/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO6_MCU_IE (BIT(4)) +#define IO_MUX_GPIO6_MCU_IE_M (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S) +#define IO_MUX_GPIO6_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO6_MCU_IE_S 4 +/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO6_MCU_DRV 0x00000003U +#define IO_MUX_GPIO6_MCU_DRV_M (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S) +#define IO_MUX_GPIO6_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO6_MCU_DRV_S 5 +/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO6_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO6_FUN_WPD_M (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S) +#define IO_MUX_GPIO6_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO6_FUN_WPD_S 7 +/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO6_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO6_FUN_WPU_M (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S) +#define IO_MUX_GPIO6_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO6_FUN_WPU_S 8 +/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO6_FUN_IE (BIT(9)) +#define IO_MUX_GPIO6_FUN_IE_M (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S) +#define IO_MUX_GPIO6_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO6_FUN_IE_S 9 +/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO6_FUN_DRV 0x00000003U +#define IO_MUX_GPIO6_FUN_DRV_M (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S) +#define IO_MUX_GPIO6_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO6_FUN_DRV_S 10 +/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO6_MCU_SEL 0x00000007U +#define IO_MUX_GPIO6_MCU_SEL_M (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S) +#define IO_MUX_GPIO6_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO6_MCU_SEL_S 12 +/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO6_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO6_FILTER_EN_M (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S) +#define IO_MUX_GPIO6_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO6_FILTER_EN_S 15 +/** IO_MUX_GPIO6_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO6_HYS_EN (BIT(16)) +#define IO_MUX_GPIO6_HYS_EN_M (IO_MUX_GPIO6_HYS_EN_V << IO_MUX_GPIO6_HYS_EN_S) +#define IO_MUX_GPIO6_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO6_HYS_EN_S 16 +/** IO_MUX_GPIO6_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO6_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO6_HYS_SEL_M (IO_MUX_GPIO6_HYS_SEL_V << IO_MUX_GPIO6_HYS_SEL_S) +#define IO_MUX_GPIO6_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO6_HYS_SEL_S 17 + +/** IO_MUX_GPIO7_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20) +/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO7_MCU_OE (BIT(0)) +#define IO_MUX_GPIO7_MCU_OE_M (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S) +#define IO_MUX_GPIO7_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO7_MCU_OE_S 0 +/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO7_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO7_SLP_SEL_M (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S) +#define IO_MUX_GPIO7_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO7_SLP_SEL_S 1 +/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO7_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO7_MCU_WPD_M (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S) +#define IO_MUX_GPIO7_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO7_MCU_WPD_S 2 +/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO7_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO7_MCU_WPU_M (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S) +#define IO_MUX_GPIO7_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO7_MCU_WPU_S 3 +/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO7_MCU_IE (BIT(4)) +#define IO_MUX_GPIO7_MCU_IE_M (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S) +#define IO_MUX_GPIO7_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO7_MCU_IE_S 4 +/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO7_MCU_DRV 0x00000003U +#define IO_MUX_GPIO7_MCU_DRV_M (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S) +#define IO_MUX_GPIO7_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO7_MCU_DRV_S 5 +/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO7_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO7_FUN_WPD_M (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S) +#define IO_MUX_GPIO7_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO7_FUN_WPD_S 7 +/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO7_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO7_FUN_WPU_M (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S) +#define IO_MUX_GPIO7_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO7_FUN_WPU_S 8 +/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO7_FUN_IE (BIT(9)) +#define IO_MUX_GPIO7_FUN_IE_M (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S) +#define IO_MUX_GPIO7_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO7_FUN_IE_S 9 +/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO7_FUN_DRV 0x00000003U +#define IO_MUX_GPIO7_FUN_DRV_M (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S) +#define IO_MUX_GPIO7_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO7_FUN_DRV_S 10 +/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO7_MCU_SEL 0x00000007U +#define IO_MUX_GPIO7_MCU_SEL_M (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S) +#define IO_MUX_GPIO7_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO7_MCU_SEL_S 12 +/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO7_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO7_FILTER_EN_M (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S) +#define IO_MUX_GPIO7_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO7_FILTER_EN_S 15 +/** IO_MUX_GPIO7_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO7_HYS_EN (BIT(16)) +#define IO_MUX_GPIO7_HYS_EN_M (IO_MUX_GPIO7_HYS_EN_V << IO_MUX_GPIO7_HYS_EN_S) +#define IO_MUX_GPIO7_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO7_HYS_EN_S 16 +/** IO_MUX_GPIO7_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO7_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO7_HYS_SEL_M (IO_MUX_GPIO7_HYS_SEL_V << IO_MUX_GPIO7_HYS_SEL_S) +#define IO_MUX_GPIO7_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO7_HYS_SEL_S 17 + +/** IO_MUX_GPIO8_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24) +/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO8_MCU_OE (BIT(0)) +#define IO_MUX_GPIO8_MCU_OE_M (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S) +#define IO_MUX_GPIO8_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO8_MCU_OE_S 0 +/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO8_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO8_SLP_SEL_M (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S) +#define IO_MUX_GPIO8_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO8_SLP_SEL_S 1 +/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO8_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO8_MCU_WPD_M (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S) +#define IO_MUX_GPIO8_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO8_MCU_WPD_S 2 +/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO8_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO8_MCU_WPU_M (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S) +#define IO_MUX_GPIO8_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO8_MCU_WPU_S 3 +/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO8_MCU_IE (BIT(4)) +#define IO_MUX_GPIO8_MCU_IE_M (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S) +#define IO_MUX_GPIO8_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO8_MCU_IE_S 4 +/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO8_MCU_DRV 0x00000003U +#define IO_MUX_GPIO8_MCU_DRV_M (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S) +#define IO_MUX_GPIO8_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO8_MCU_DRV_S 5 +/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO8_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO8_FUN_WPD_M (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S) +#define IO_MUX_GPIO8_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO8_FUN_WPD_S 7 +/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO8_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO8_FUN_WPU_M (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S) +#define IO_MUX_GPIO8_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO8_FUN_WPU_S 8 +/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO8_FUN_IE (BIT(9)) +#define IO_MUX_GPIO8_FUN_IE_M (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S) +#define IO_MUX_GPIO8_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO8_FUN_IE_S 9 +/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO8_FUN_DRV 0x00000003U +#define IO_MUX_GPIO8_FUN_DRV_M (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S) +#define IO_MUX_GPIO8_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO8_FUN_DRV_S 10 +/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO8_MCU_SEL 0x00000007U +#define IO_MUX_GPIO8_MCU_SEL_M (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S) +#define IO_MUX_GPIO8_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO8_MCU_SEL_S 12 +/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO8_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO8_FILTER_EN_M (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S) +#define IO_MUX_GPIO8_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO8_FILTER_EN_S 15 +/** IO_MUX_GPIO8_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO8_HYS_EN (BIT(16)) +#define IO_MUX_GPIO8_HYS_EN_M (IO_MUX_GPIO8_HYS_EN_V << IO_MUX_GPIO8_HYS_EN_S) +#define IO_MUX_GPIO8_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO8_HYS_EN_S 16 +/** IO_MUX_GPIO8_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO8_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO8_HYS_SEL_M (IO_MUX_GPIO8_HYS_SEL_V << IO_MUX_GPIO8_HYS_SEL_S) +#define IO_MUX_GPIO8_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO8_HYS_SEL_S 17 + +/** IO_MUX_GPIO9_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28) +/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO9_MCU_OE (BIT(0)) +#define IO_MUX_GPIO9_MCU_OE_M (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S) +#define IO_MUX_GPIO9_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO9_MCU_OE_S 0 +/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO9_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO9_SLP_SEL_M (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S) +#define IO_MUX_GPIO9_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO9_SLP_SEL_S 1 +/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO9_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO9_MCU_WPD_M (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S) +#define IO_MUX_GPIO9_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO9_MCU_WPD_S 2 +/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO9_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO9_MCU_WPU_M (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S) +#define IO_MUX_GPIO9_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO9_MCU_WPU_S 3 +/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO9_MCU_IE (BIT(4)) +#define IO_MUX_GPIO9_MCU_IE_M (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S) +#define IO_MUX_GPIO9_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO9_MCU_IE_S 4 +/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO9_MCU_DRV 0x00000003U +#define IO_MUX_GPIO9_MCU_DRV_M (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S) +#define IO_MUX_GPIO9_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO9_MCU_DRV_S 5 +/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO9_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO9_FUN_WPD_M (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S) +#define IO_MUX_GPIO9_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO9_FUN_WPD_S 7 +/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO9_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO9_FUN_WPU_M (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S) +#define IO_MUX_GPIO9_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO9_FUN_WPU_S 8 +/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO9_FUN_IE (BIT(9)) +#define IO_MUX_GPIO9_FUN_IE_M (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S) +#define IO_MUX_GPIO9_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO9_FUN_IE_S 9 +/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO9_FUN_DRV 0x00000003U +#define IO_MUX_GPIO9_FUN_DRV_M (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S) +#define IO_MUX_GPIO9_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO9_FUN_DRV_S 10 +/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO9_MCU_SEL 0x00000007U +#define IO_MUX_GPIO9_MCU_SEL_M (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S) +#define IO_MUX_GPIO9_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO9_MCU_SEL_S 12 +/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO9_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO9_FILTER_EN_M (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S) +#define IO_MUX_GPIO9_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO9_FILTER_EN_S 15 +/** IO_MUX_GPIO9_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO9_HYS_EN (BIT(16)) +#define IO_MUX_GPIO9_HYS_EN_M (IO_MUX_GPIO9_HYS_EN_V << IO_MUX_GPIO9_HYS_EN_S) +#define IO_MUX_GPIO9_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO9_HYS_EN_S 16 +/** IO_MUX_GPIO9_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO9_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO9_HYS_SEL_M (IO_MUX_GPIO9_HYS_SEL_V << IO_MUX_GPIO9_HYS_SEL_S) +#define IO_MUX_GPIO9_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO9_HYS_SEL_S 17 + +/** IO_MUX_GPIO10_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c) +/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO10_MCU_OE (BIT(0)) +#define IO_MUX_GPIO10_MCU_OE_M (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S) +#define IO_MUX_GPIO10_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO10_MCU_OE_S 0 +/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO10_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO10_SLP_SEL_M (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S) +#define IO_MUX_GPIO10_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO10_SLP_SEL_S 1 +/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO10_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO10_MCU_WPD_M (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S) +#define IO_MUX_GPIO10_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO10_MCU_WPD_S 2 +/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO10_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO10_MCU_WPU_M (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S) +#define IO_MUX_GPIO10_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO10_MCU_WPU_S 3 +/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO10_MCU_IE (BIT(4)) +#define IO_MUX_GPIO10_MCU_IE_M (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S) +#define IO_MUX_GPIO10_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO10_MCU_IE_S 4 +/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO10_MCU_DRV 0x00000003U +#define IO_MUX_GPIO10_MCU_DRV_M (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S) +#define IO_MUX_GPIO10_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO10_MCU_DRV_S 5 +/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO10_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO10_FUN_WPD_M (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S) +#define IO_MUX_GPIO10_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO10_FUN_WPD_S 7 +/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO10_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO10_FUN_WPU_M (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S) +#define IO_MUX_GPIO10_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO10_FUN_WPU_S 8 +/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO10_FUN_IE (BIT(9)) +#define IO_MUX_GPIO10_FUN_IE_M (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S) +#define IO_MUX_GPIO10_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO10_FUN_IE_S 9 +/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO10_FUN_DRV 0x00000003U +#define IO_MUX_GPIO10_FUN_DRV_M (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S) +#define IO_MUX_GPIO10_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO10_FUN_DRV_S 10 +/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO10_MCU_SEL 0x00000007U +#define IO_MUX_GPIO10_MCU_SEL_M (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S) +#define IO_MUX_GPIO10_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO10_MCU_SEL_S 12 +/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO10_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO10_FILTER_EN_M (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S) +#define IO_MUX_GPIO10_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO10_FILTER_EN_S 15 +/** IO_MUX_GPIO10_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO10_HYS_EN (BIT(16)) +#define IO_MUX_GPIO10_HYS_EN_M (IO_MUX_GPIO10_HYS_EN_V << IO_MUX_GPIO10_HYS_EN_S) +#define IO_MUX_GPIO10_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO10_HYS_EN_S 16 +/** IO_MUX_GPIO10_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO10_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO10_HYS_SEL_M (IO_MUX_GPIO10_HYS_SEL_V << IO_MUX_GPIO10_HYS_SEL_S) +#define IO_MUX_GPIO10_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO10_HYS_SEL_S 17 + +/** IO_MUX_GPIO11_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30) +/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO11_MCU_OE (BIT(0)) +#define IO_MUX_GPIO11_MCU_OE_M (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S) +#define IO_MUX_GPIO11_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO11_MCU_OE_S 0 +/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO11_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO11_SLP_SEL_M (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S) +#define IO_MUX_GPIO11_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO11_SLP_SEL_S 1 +/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO11_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO11_MCU_WPD_M (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S) +#define IO_MUX_GPIO11_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO11_MCU_WPD_S 2 +/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO11_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO11_MCU_WPU_M (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S) +#define IO_MUX_GPIO11_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO11_MCU_WPU_S 3 +/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO11_MCU_IE (BIT(4)) +#define IO_MUX_GPIO11_MCU_IE_M (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S) +#define IO_MUX_GPIO11_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO11_MCU_IE_S 4 +/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO11_MCU_DRV 0x00000003U +#define IO_MUX_GPIO11_MCU_DRV_M (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S) +#define IO_MUX_GPIO11_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO11_MCU_DRV_S 5 +/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO11_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO11_FUN_WPD_M (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S) +#define IO_MUX_GPIO11_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO11_FUN_WPD_S 7 +/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO11_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO11_FUN_WPU_M (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S) +#define IO_MUX_GPIO11_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO11_FUN_WPU_S 8 +/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO11_FUN_IE (BIT(9)) +#define IO_MUX_GPIO11_FUN_IE_M (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S) +#define IO_MUX_GPIO11_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO11_FUN_IE_S 9 +/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO11_FUN_DRV 0x00000003U +#define IO_MUX_GPIO11_FUN_DRV_M (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S) +#define IO_MUX_GPIO11_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO11_FUN_DRV_S 10 +/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO11_MCU_SEL 0x00000007U +#define IO_MUX_GPIO11_MCU_SEL_M (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S) +#define IO_MUX_GPIO11_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO11_MCU_SEL_S 12 +/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO11_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO11_FILTER_EN_M (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S) +#define IO_MUX_GPIO11_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO11_FILTER_EN_S 15 +/** IO_MUX_GPIO11_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO11_HYS_EN (BIT(16)) +#define IO_MUX_GPIO11_HYS_EN_M (IO_MUX_GPIO11_HYS_EN_V << IO_MUX_GPIO11_HYS_EN_S) +#define IO_MUX_GPIO11_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO11_HYS_EN_S 16 +/** IO_MUX_GPIO11_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO11_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO11_HYS_SEL_M (IO_MUX_GPIO11_HYS_SEL_V << IO_MUX_GPIO11_HYS_SEL_S) +#define IO_MUX_GPIO11_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO11_HYS_SEL_S 17 + +/** IO_MUX_GPIO12_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34) +/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO12_MCU_OE (BIT(0)) +#define IO_MUX_GPIO12_MCU_OE_M (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S) +#define IO_MUX_GPIO12_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO12_MCU_OE_S 0 +/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO12_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO12_SLP_SEL_M (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S) +#define IO_MUX_GPIO12_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO12_SLP_SEL_S 1 +/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO12_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO12_MCU_WPD_M (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S) +#define IO_MUX_GPIO12_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO12_MCU_WPD_S 2 +/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO12_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO12_MCU_WPU_M (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S) +#define IO_MUX_GPIO12_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO12_MCU_WPU_S 3 +/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO12_MCU_IE (BIT(4)) +#define IO_MUX_GPIO12_MCU_IE_M (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S) +#define IO_MUX_GPIO12_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO12_MCU_IE_S 4 +/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO12_MCU_DRV 0x00000003U +#define IO_MUX_GPIO12_MCU_DRV_M (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S) +#define IO_MUX_GPIO12_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO12_MCU_DRV_S 5 +/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO12_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO12_FUN_WPD_M (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S) +#define IO_MUX_GPIO12_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO12_FUN_WPD_S 7 +/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO12_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO12_FUN_WPU_M (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S) +#define IO_MUX_GPIO12_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO12_FUN_WPU_S 8 +/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO12_FUN_IE (BIT(9)) +#define IO_MUX_GPIO12_FUN_IE_M (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S) +#define IO_MUX_GPIO12_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO12_FUN_IE_S 9 +/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO12_FUN_DRV 0x00000003U +#define IO_MUX_GPIO12_FUN_DRV_M (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S) +#define IO_MUX_GPIO12_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO12_FUN_DRV_S 10 +/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO12_MCU_SEL 0x00000007U +#define IO_MUX_GPIO12_MCU_SEL_M (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S) +#define IO_MUX_GPIO12_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO12_MCU_SEL_S 12 +/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO12_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO12_FILTER_EN_M (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S) +#define IO_MUX_GPIO12_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO12_FILTER_EN_S 15 +/** IO_MUX_GPIO12_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO12_HYS_EN (BIT(16)) +#define IO_MUX_GPIO12_HYS_EN_M (IO_MUX_GPIO12_HYS_EN_V << IO_MUX_GPIO12_HYS_EN_S) +#define IO_MUX_GPIO12_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO12_HYS_EN_S 16 +/** IO_MUX_GPIO12_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO12_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO12_HYS_SEL_M (IO_MUX_GPIO12_HYS_SEL_V << IO_MUX_GPIO12_HYS_SEL_S) +#define IO_MUX_GPIO12_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO12_HYS_SEL_S 17 + +/** IO_MUX_GPIO13_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38) +/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO13_MCU_OE (BIT(0)) +#define IO_MUX_GPIO13_MCU_OE_M (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S) +#define IO_MUX_GPIO13_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO13_MCU_OE_S 0 +/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO13_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO13_SLP_SEL_M (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S) +#define IO_MUX_GPIO13_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO13_SLP_SEL_S 1 +/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO13_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO13_MCU_WPD_M (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S) +#define IO_MUX_GPIO13_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO13_MCU_WPD_S 2 +/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO13_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO13_MCU_WPU_M (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S) +#define IO_MUX_GPIO13_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO13_MCU_WPU_S 3 +/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO13_MCU_IE (BIT(4)) +#define IO_MUX_GPIO13_MCU_IE_M (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S) +#define IO_MUX_GPIO13_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO13_MCU_IE_S 4 +/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO13_MCU_DRV 0x00000003U +#define IO_MUX_GPIO13_MCU_DRV_M (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S) +#define IO_MUX_GPIO13_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO13_MCU_DRV_S 5 +/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO13_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO13_FUN_WPD_M (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S) +#define IO_MUX_GPIO13_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO13_FUN_WPD_S 7 +/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO13_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO13_FUN_WPU_M (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S) +#define IO_MUX_GPIO13_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO13_FUN_WPU_S 8 +/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO13_FUN_IE (BIT(9)) +#define IO_MUX_GPIO13_FUN_IE_M (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S) +#define IO_MUX_GPIO13_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO13_FUN_IE_S 9 +/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO13_FUN_DRV 0x00000003U +#define IO_MUX_GPIO13_FUN_DRV_M (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S) +#define IO_MUX_GPIO13_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO13_FUN_DRV_S 10 +/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO13_MCU_SEL 0x00000007U +#define IO_MUX_GPIO13_MCU_SEL_M (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S) +#define IO_MUX_GPIO13_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO13_MCU_SEL_S 12 +/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO13_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO13_FILTER_EN_M (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S) +#define IO_MUX_GPIO13_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO13_FILTER_EN_S 15 +/** IO_MUX_GPIO13_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO13_HYS_EN (BIT(16)) +#define IO_MUX_GPIO13_HYS_EN_M (IO_MUX_GPIO13_HYS_EN_V << IO_MUX_GPIO13_HYS_EN_S) +#define IO_MUX_GPIO13_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO13_HYS_EN_S 16 +/** IO_MUX_GPIO13_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO13_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO13_HYS_SEL_M (IO_MUX_GPIO13_HYS_SEL_V << IO_MUX_GPIO13_HYS_SEL_S) +#define IO_MUX_GPIO13_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO13_HYS_SEL_S 17 + +/** IO_MUX_GPIO14_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c) +/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO14_MCU_OE (BIT(0)) +#define IO_MUX_GPIO14_MCU_OE_M (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S) +#define IO_MUX_GPIO14_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO14_MCU_OE_S 0 +/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO14_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO14_SLP_SEL_M (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S) +#define IO_MUX_GPIO14_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO14_SLP_SEL_S 1 +/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO14_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO14_MCU_WPD_M (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S) +#define IO_MUX_GPIO14_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO14_MCU_WPD_S 2 +/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO14_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO14_MCU_WPU_M (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S) +#define IO_MUX_GPIO14_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO14_MCU_WPU_S 3 +/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO14_MCU_IE (BIT(4)) +#define IO_MUX_GPIO14_MCU_IE_M (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S) +#define IO_MUX_GPIO14_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO14_MCU_IE_S 4 +/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO14_MCU_DRV 0x00000003U +#define IO_MUX_GPIO14_MCU_DRV_M (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S) +#define IO_MUX_GPIO14_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO14_MCU_DRV_S 5 +/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO14_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO14_FUN_WPD_M (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S) +#define IO_MUX_GPIO14_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO14_FUN_WPD_S 7 +/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO14_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO14_FUN_WPU_M (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S) +#define IO_MUX_GPIO14_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO14_FUN_WPU_S 8 +/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO14_FUN_IE (BIT(9)) +#define IO_MUX_GPIO14_FUN_IE_M (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S) +#define IO_MUX_GPIO14_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO14_FUN_IE_S 9 +/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO14_FUN_DRV 0x00000003U +#define IO_MUX_GPIO14_FUN_DRV_M (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S) +#define IO_MUX_GPIO14_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO14_FUN_DRV_S 10 +/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO14_MCU_SEL 0x00000007U +#define IO_MUX_GPIO14_MCU_SEL_M (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S) +#define IO_MUX_GPIO14_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO14_MCU_SEL_S 12 +/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO14_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO14_FILTER_EN_M (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S) +#define IO_MUX_GPIO14_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO14_FILTER_EN_S 15 +/** IO_MUX_GPIO14_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO14_HYS_EN (BIT(16)) +#define IO_MUX_GPIO14_HYS_EN_M (IO_MUX_GPIO14_HYS_EN_V << IO_MUX_GPIO14_HYS_EN_S) +#define IO_MUX_GPIO14_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO14_HYS_EN_S 16 +/** IO_MUX_GPIO14_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO14_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO14_HYS_SEL_M (IO_MUX_GPIO14_HYS_SEL_V << IO_MUX_GPIO14_HYS_SEL_S) +#define IO_MUX_GPIO14_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO14_HYS_SEL_S 17 + +/** IO_MUX_GPIO15_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40) +/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO15_MCU_OE (BIT(0)) +#define IO_MUX_GPIO15_MCU_OE_M (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S) +#define IO_MUX_GPIO15_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO15_MCU_OE_S 0 +/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO15_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO15_SLP_SEL_M (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S) +#define IO_MUX_GPIO15_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO15_SLP_SEL_S 1 +/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO15_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO15_MCU_WPD_M (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S) +#define IO_MUX_GPIO15_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO15_MCU_WPD_S 2 +/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO15_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO15_MCU_WPU_M (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S) +#define IO_MUX_GPIO15_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO15_MCU_WPU_S 3 +/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO15_MCU_IE (BIT(4)) +#define IO_MUX_GPIO15_MCU_IE_M (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S) +#define IO_MUX_GPIO15_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO15_MCU_IE_S 4 +/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO15_MCU_DRV 0x00000003U +#define IO_MUX_GPIO15_MCU_DRV_M (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S) +#define IO_MUX_GPIO15_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO15_MCU_DRV_S 5 +/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO15_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO15_FUN_WPD_M (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S) +#define IO_MUX_GPIO15_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO15_FUN_WPD_S 7 +/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO15_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO15_FUN_WPU_M (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S) +#define IO_MUX_GPIO15_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO15_FUN_WPU_S 8 +/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO15_FUN_IE (BIT(9)) +#define IO_MUX_GPIO15_FUN_IE_M (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S) +#define IO_MUX_GPIO15_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO15_FUN_IE_S 9 +/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO15_FUN_DRV 0x00000003U +#define IO_MUX_GPIO15_FUN_DRV_M (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S) +#define IO_MUX_GPIO15_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO15_FUN_DRV_S 10 +/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO15_MCU_SEL 0x00000007U +#define IO_MUX_GPIO15_MCU_SEL_M (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S) +#define IO_MUX_GPIO15_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO15_MCU_SEL_S 12 +/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO15_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO15_FILTER_EN_M (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S) +#define IO_MUX_GPIO15_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO15_FILTER_EN_S 15 +/** IO_MUX_GPIO15_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO15_HYS_EN (BIT(16)) +#define IO_MUX_GPIO15_HYS_EN_M (IO_MUX_GPIO15_HYS_EN_V << IO_MUX_GPIO15_HYS_EN_S) +#define IO_MUX_GPIO15_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO15_HYS_EN_S 16 +/** IO_MUX_GPIO15_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO15_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO15_HYS_SEL_M (IO_MUX_GPIO15_HYS_SEL_V << IO_MUX_GPIO15_HYS_SEL_S) +#define IO_MUX_GPIO15_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO15_HYS_SEL_S 17 + +/** IO_MUX_GPIO16_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44) +/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO16_MCU_OE (BIT(0)) +#define IO_MUX_GPIO16_MCU_OE_M (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S) +#define IO_MUX_GPIO16_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO16_MCU_OE_S 0 +/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO16_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO16_SLP_SEL_M (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S) +#define IO_MUX_GPIO16_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO16_SLP_SEL_S 1 +/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO16_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO16_MCU_WPD_M (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S) +#define IO_MUX_GPIO16_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO16_MCU_WPD_S 2 +/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO16_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO16_MCU_WPU_M (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S) +#define IO_MUX_GPIO16_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO16_MCU_WPU_S 3 +/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO16_MCU_IE (BIT(4)) +#define IO_MUX_GPIO16_MCU_IE_M (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S) +#define IO_MUX_GPIO16_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO16_MCU_IE_S 4 +/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO16_MCU_DRV 0x00000003U +#define IO_MUX_GPIO16_MCU_DRV_M (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S) +#define IO_MUX_GPIO16_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO16_MCU_DRV_S 5 +/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO16_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO16_FUN_WPD_M (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S) +#define IO_MUX_GPIO16_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO16_FUN_WPD_S 7 +/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO16_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO16_FUN_WPU_M (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S) +#define IO_MUX_GPIO16_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO16_FUN_WPU_S 8 +/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO16_FUN_IE (BIT(9)) +#define IO_MUX_GPIO16_FUN_IE_M (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S) +#define IO_MUX_GPIO16_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO16_FUN_IE_S 9 +/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO16_FUN_DRV 0x00000003U +#define IO_MUX_GPIO16_FUN_DRV_M (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S) +#define IO_MUX_GPIO16_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO16_FUN_DRV_S 10 +/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO16_MCU_SEL 0x00000007U +#define IO_MUX_GPIO16_MCU_SEL_M (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S) +#define IO_MUX_GPIO16_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO16_MCU_SEL_S 12 +/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO16_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO16_FILTER_EN_M (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S) +#define IO_MUX_GPIO16_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO16_FILTER_EN_S 15 +/** IO_MUX_GPIO16_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO16_HYS_EN (BIT(16)) +#define IO_MUX_GPIO16_HYS_EN_M (IO_MUX_GPIO16_HYS_EN_V << IO_MUX_GPIO16_HYS_EN_S) +#define IO_MUX_GPIO16_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO16_HYS_EN_S 16 +/** IO_MUX_GPIO16_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO16_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO16_HYS_SEL_M (IO_MUX_GPIO16_HYS_SEL_V << IO_MUX_GPIO16_HYS_SEL_S) +#define IO_MUX_GPIO16_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO16_HYS_SEL_S 17 + +/** IO_MUX_GPIO17_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48) +/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO17_MCU_OE (BIT(0)) +#define IO_MUX_GPIO17_MCU_OE_M (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S) +#define IO_MUX_GPIO17_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO17_MCU_OE_S 0 +/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO17_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO17_SLP_SEL_M (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S) +#define IO_MUX_GPIO17_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO17_SLP_SEL_S 1 +/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO17_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO17_MCU_WPD_M (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S) +#define IO_MUX_GPIO17_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO17_MCU_WPD_S 2 +/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO17_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO17_MCU_WPU_M (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S) +#define IO_MUX_GPIO17_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO17_MCU_WPU_S 3 +/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO17_MCU_IE (BIT(4)) +#define IO_MUX_GPIO17_MCU_IE_M (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S) +#define IO_MUX_GPIO17_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO17_MCU_IE_S 4 +/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO17_MCU_DRV 0x00000003U +#define IO_MUX_GPIO17_MCU_DRV_M (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S) +#define IO_MUX_GPIO17_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO17_MCU_DRV_S 5 +/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO17_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO17_FUN_WPD_M (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S) +#define IO_MUX_GPIO17_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO17_FUN_WPD_S 7 +/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO17_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO17_FUN_WPU_M (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S) +#define IO_MUX_GPIO17_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO17_FUN_WPU_S 8 +/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO17_FUN_IE (BIT(9)) +#define IO_MUX_GPIO17_FUN_IE_M (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S) +#define IO_MUX_GPIO17_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO17_FUN_IE_S 9 +/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO17_FUN_DRV 0x00000003U +#define IO_MUX_GPIO17_FUN_DRV_M (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S) +#define IO_MUX_GPIO17_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO17_FUN_DRV_S 10 +/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO17_MCU_SEL 0x00000007U +#define IO_MUX_GPIO17_MCU_SEL_M (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S) +#define IO_MUX_GPIO17_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO17_MCU_SEL_S 12 +/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO17_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO17_FILTER_EN_M (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S) +#define IO_MUX_GPIO17_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO17_FILTER_EN_S 15 +/** IO_MUX_GPIO17_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO17_HYS_EN (BIT(16)) +#define IO_MUX_GPIO17_HYS_EN_M (IO_MUX_GPIO17_HYS_EN_V << IO_MUX_GPIO17_HYS_EN_S) +#define IO_MUX_GPIO17_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO17_HYS_EN_S 16 +/** IO_MUX_GPIO17_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO17_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO17_HYS_SEL_M (IO_MUX_GPIO17_HYS_SEL_V << IO_MUX_GPIO17_HYS_SEL_S) +#define IO_MUX_GPIO17_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO17_HYS_SEL_S 17 + +/** IO_MUX_GPIO18_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c) +/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO18_MCU_OE (BIT(0)) +#define IO_MUX_GPIO18_MCU_OE_M (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S) +#define IO_MUX_GPIO18_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO18_MCU_OE_S 0 +/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO18_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO18_SLP_SEL_M (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S) +#define IO_MUX_GPIO18_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO18_SLP_SEL_S 1 +/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO18_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO18_MCU_WPD_M (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S) +#define IO_MUX_GPIO18_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO18_MCU_WPD_S 2 +/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO18_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO18_MCU_WPU_M (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S) +#define IO_MUX_GPIO18_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO18_MCU_WPU_S 3 +/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO18_MCU_IE (BIT(4)) +#define IO_MUX_GPIO18_MCU_IE_M (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S) +#define IO_MUX_GPIO18_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO18_MCU_IE_S 4 +/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO18_MCU_DRV 0x00000003U +#define IO_MUX_GPIO18_MCU_DRV_M (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S) +#define IO_MUX_GPIO18_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO18_MCU_DRV_S 5 +/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO18_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO18_FUN_WPD_M (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S) +#define IO_MUX_GPIO18_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO18_FUN_WPD_S 7 +/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO18_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO18_FUN_WPU_M (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S) +#define IO_MUX_GPIO18_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO18_FUN_WPU_S 8 +/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO18_FUN_IE (BIT(9)) +#define IO_MUX_GPIO18_FUN_IE_M (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S) +#define IO_MUX_GPIO18_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO18_FUN_IE_S 9 +/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO18_FUN_DRV 0x00000003U +#define IO_MUX_GPIO18_FUN_DRV_M (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S) +#define IO_MUX_GPIO18_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO18_FUN_DRV_S 10 +/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO18_MCU_SEL 0x00000007U +#define IO_MUX_GPIO18_MCU_SEL_M (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S) +#define IO_MUX_GPIO18_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO18_MCU_SEL_S 12 +/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO18_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO18_FILTER_EN_M (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S) +#define IO_MUX_GPIO18_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO18_FILTER_EN_S 15 +/** IO_MUX_GPIO18_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO18_HYS_EN (BIT(16)) +#define IO_MUX_GPIO18_HYS_EN_M (IO_MUX_GPIO18_HYS_EN_V << IO_MUX_GPIO18_HYS_EN_S) +#define IO_MUX_GPIO18_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO18_HYS_EN_S 16 +/** IO_MUX_GPIO18_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO18_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO18_HYS_SEL_M (IO_MUX_GPIO18_HYS_SEL_V << IO_MUX_GPIO18_HYS_SEL_S) +#define IO_MUX_GPIO18_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO18_HYS_SEL_S 17 + +/** IO_MUX_GPIO19_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50) +/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO19_MCU_OE (BIT(0)) +#define IO_MUX_GPIO19_MCU_OE_M (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S) +#define IO_MUX_GPIO19_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO19_MCU_OE_S 0 +/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO19_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO19_SLP_SEL_M (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S) +#define IO_MUX_GPIO19_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO19_SLP_SEL_S 1 +/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO19_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO19_MCU_WPD_M (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S) +#define IO_MUX_GPIO19_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO19_MCU_WPD_S 2 +/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO19_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO19_MCU_WPU_M (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S) +#define IO_MUX_GPIO19_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO19_MCU_WPU_S 3 +/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO19_MCU_IE (BIT(4)) +#define IO_MUX_GPIO19_MCU_IE_M (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S) +#define IO_MUX_GPIO19_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO19_MCU_IE_S 4 +/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO19_MCU_DRV 0x00000003U +#define IO_MUX_GPIO19_MCU_DRV_M (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S) +#define IO_MUX_GPIO19_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO19_MCU_DRV_S 5 +/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO19_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO19_FUN_WPD_M (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S) +#define IO_MUX_GPIO19_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO19_FUN_WPD_S 7 +/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO19_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO19_FUN_WPU_M (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S) +#define IO_MUX_GPIO19_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO19_FUN_WPU_S 8 +/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO19_FUN_IE (BIT(9)) +#define IO_MUX_GPIO19_FUN_IE_M (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S) +#define IO_MUX_GPIO19_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO19_FUN_IE_S 9 +/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO19_FUN_DRV 0x00000003U +#define IO_MUX_GPIO19_FUN_DRV_M (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S) +#define IO_MUX_GPIO19_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO19_FUN_DRV_S 10 +/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO19_MCU_SEL 0x00000007U +#define IO_MUX_GPIO19_MCU_SEL_M (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S) +#define IO_MUX_GPIO19_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO19_MCU_SEL_S 12 +/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO19_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO19_FILTER_EN_M (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S) +#define IO_MUX_GPIO19_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO19_FILTER_EN_S 15 +/** IO_MUX_GPIO19_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO19_HYS_EN (BIT(16)) +#define IO_MUX_GPIO19_HYS_EN_M (IO_MUX_GPIO19_HYS_EN_V << IO_MUX_GPIO19_HYS_EN_S) +#define IO_MUX_GPIO19_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO19_HYS_EN_S 16 +/** IO_MUX_GPIO19_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO19_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO19_HYS_SEL_M (IO_MUX_GPIO19_HYS_SEL_V << IO_MUX_GPIO19_HYS_SEL_S) +#define IO_MUX_GPIO19_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO19_HYS_SEL_S 17 + +/** IO_MUX_GPIO20_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54) +/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO20_MCU_OE (BIT(0)) +#define IO_MUX_GPIO20_MCU_OE_M (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S) +#define IO_MUX_GPIO20_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO20_MCU_OE_S 0 +/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO20_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO20_SLP_SEL_M (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S) +#define IO_MUX_GPIO20_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO20_SLP_SEL_S 1 +/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO20_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO20_MCU_WPD_M (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S) +#define IO_MUX_GPIO20_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO20_MCU_WPD_S 2 +/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO20_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO20_MCU_WPU_M (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S) +#define IO_MUX_GPIO20_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO20_MCU_WPU_S 3 +/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO20_MCU_IE (BIT(4)) +#define IO_MUX_GPIO20_MCU_IE_M (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S) +#define IO_MUX_GPIO20_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO20_MCU_IE_S 4 +/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO20_MCU_DRV 0x00000003U +#define IO_MUX_GPIO20_MCU_DRV_M (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S) +#define IO_MUX_GPIO20_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO20_MCU_DRV_S 5 +/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO20_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO20_FUN_WPD_M (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S) +#define IO_MUX_GPIO20_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO20_FUN_WPD_S 7 +/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO20_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO20_FUN_WPU_M (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S) +#define IO_MUX_GPIO20_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO20_FUN_WPU_S 8 +/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO20_FUN_IE (BIT(9)) +#define IO_MUX_GPIO20_FUN_IE_M (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S) +#define IO_MUX_GPIO20_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO20_FUN_IE_S 9 +/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO20_FUN_DRV 0x00000003U +#define IO_MUX_GPIO20_FUN_DRV_M (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S) +#define IO_MUX_GPIO20_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO20_FUN_DRV_S 10 +/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO20_MCU_SEL 0x00000007U +#define IO_MUX_GPIO20_MCU_SEL_M (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S) +#define IO_MUX_GPIO20_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO20_MCU_SEL_S 12 +/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO20_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO20_FILTER_EN_M (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S) +#define IO_MUX_GPIO20_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO20_FILTER_EN_S 15 +/** IO_MUX_GPIO20_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO20_HYS_EN (BIT(16)) +#define IO_MUX_GPIO20_HYS_EN_M (IO_MUX_GPIO20_HYS_EN_V << IO_MUX_GPIO20_HYS_EN_S) +#define IO_MUX_GPIO20_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO20_HYS_EN_S 16 +/** IO_MUX_GPIO20_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO20_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO20_HYS_SEL_M (IO_MUX_GPIO20_HYS_SEL_V << IO_MUX_GPIO20_HYS_SEL_S) +#define IO_MUX_GPIO20_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO20_HYS_SEL_S 17 + +/** IO_MUX_GPIO21_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58) +/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO21_MCU_OE (BIT(0)) +#define IO_MUX_GPIO21_MCU_OE_M (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S) +#define IO_MUX_GPIO21_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO21_MCU_OE_S 0 +/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO21_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO21_SLP_SEL_M (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S) +#define IO_MUX_GPIO21_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO21_SLP_SEL_S 1 +/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO21_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO21_MCU_WPD_M (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S) +#define IO_MUX_GPIO21_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO21_MCU_WPD_S 2 +/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO21_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO21_MCU_WPU_M (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S) +#define IO_MUX_GPIO21_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO21_MCU_WPU_S 3 +/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO21_MCU_IE (BIT(4)) +#define IO_MUX_GPIO21_MCU_IE_M (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S) +#define IO_MUX_GPIO21_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO21_MCU_IE_S 4 +/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO21_MCU_DRV 0x00000003U +#define IO_MUX_GPIO21_MCU_DRV_M (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S) +#define IO_MUX_GPIO21_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO21_MCU_DRV_S 5 +/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO21_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO21_FUN_WPD_M (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S) +#define IO_MUX_GPIO21_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO21_FUN_WPD_S 7 +/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO21_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO21_FUN_WPU_M (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S) +#define IO_MUX_GPIO21_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO21_FUN_WPU_S 8 +/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO21_FUN_IE (BIT(9)) +#define IO_MUX_GPIO21_FUN_IE_M (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S) +#define IO_MUX_GPIO21_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO21_FUN_IE_S 9 +/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO21_FUN_DRV 0x00000003U +#define IO_MUX_GPIO21_FUN_DRV_M (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S) +#define IO_MUX_GPIO21_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO21_FUN_DRV_S 10 +/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO21_MCU_SEL 0x00000007U +#define IO_MUX_GPIO21_MCU_SEL_M (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S) +#define IO_MUX_GPIO21_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO21_MCU_SEL_S 12 +/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO21_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO21_FILTER_EN_M (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S) +#define IO_MUX_GPIO21_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO21_FILTER_EN_S 15 +/** IO_MUX_GPIO21_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO21_HYS_EN (BIT(16)) +#define IO_MUX_GPIO21_HYS_EN_M (IO_MUX_GPIO21_HYS_EN_V << IO_MUX_GPIO21_HYS_EN_S) +#define IO_MUX_GPIO21_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO21_HYS_EN_S 16 +/** IO_MUX_GPIO21_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO21_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO21_HYS_SEL_M (IO_MUX_GPIO21_HYS_SEL_V << IO_MUX_GPIO21_HYS_SEL_S) +#define IO_MUX_GPIO21_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO21_HYS_SEL_S 17 + +/** IO_MUX_GPIO22_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c) +/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO22_MCU_OE (BIT(0)) +#define IO_MUX_GPIO22_MCU_OE_M (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S) +#define IO_MUX_GPIO22_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO22_MCU_OE_S 0 +/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO22_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO22_SLP_SEL_M (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S) +#define IO_MUX_GPIO22_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO22_SLP_SEL_S 1 +/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO22_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO22_MCU_WPD_M (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S) +#define IO_MUX_GPIO22_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO22_MCU_WPD_S 2 +/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO22_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO22_MCU_WPU_M (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S) +#define IO_MUX_GPIO22_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO22_MCU_WPU_S 3 +/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO22_MCU_IE (BIT(4)) +#define IO_MUX_GPIO22_MCU_IE_M (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S) +#define IO_MUX_GPIO22_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO22_MCU_IE_S 4 +/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO22_MCU_DRV 0x00000003U +#define IO_MUX_GPIO22_MCU_DRV_M (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S) +#define IO_MUX_GPIO22_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO22_MCU_DRV_S 5 +/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO22_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO22_FUN_WPD_M (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S) +#define IO_MUX_GPIO22_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO22_FUN_WPD_S 7 +/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO22_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO22_FUN_WPU_M (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S) +#define IO_MUX_GPIO22_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO22_FUN_WPU_S 8 +/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO22_FUN_IE (BIT(9)) +#define IO_MUX_GPIO22_FUN_IE_M (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S) +#define IO_MUX_GPIO22_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO22_FUN_IE_S 9 +/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO22_FUN_DRV 0x00000003U +#define IO_MUX_GPIO22_FUN_DRV_M (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S) +#define IO_MUX_GPIO22_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO22_FUN_DRV_S 10 +/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO22_MCU_SEL 0x00000007U +#define IO_MUX_GPIO22_MCU_SEL_M (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S) +#define IO_MUX_GPIO22_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO22_MCU_SEL_S 12 +/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO22_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO22_FILTER_EN_M (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S) +#define IO_MUX_GPIO22_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO22_FILTER_EN_S 15 +/** IO_MUX_GPIO22_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO22_HYS_EN (BIT(16)) +#define IO_MUX_GPIO22_HYS_EN_M (IO_MUX_GPIO22_HYS_EN_V << IO_MUX_GPIO22_HYS_EN_S) +#define IO_MUX_GPIO22_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO22_HYS_EN_S 16 +/** IO_MUX_GPIO22_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO22_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO22_HYS_SEL_M (IO_MUX_GPIO22_HYS_SEL_V << IO_MUX_GPIO22_HYS_SEL_S) +#define IO_MUX_GPIO22_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO22_HYS_SEL_S 17 + +/** IO_MUX_GPIO23_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60) +/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO23_MCU_OE (BIT(0)) +#define IO_MUX_GPIO23_MCU_OE_M (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S) +#define IO_MUX_GPIO23_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO23_MCU_OE_S 0 +/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO23_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO23_SLP_SEL_M (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S) +#define IO_MUX_GPIO23_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO23_SLP_SEL_S 1 +/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO23_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO23_MCU_WPD_M (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S) +#define IO_MUX_GPIO23_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO23_MCU_WPD_S 2 +/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO23_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO23_MCU_WPU_M (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S) +#define IO_MUX_GPIO23_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO23_MCU_WPU_S 3 +/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO23_MCU_IE (BIT(4)) +#define IO_MUX_GPIO23_MCU_IE_M (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S) +#define IO_MUX_GPIO23_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO23_MCU_IE_S 4 +/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO23_MCU_DRV 0x00000003U +#define IO_MUX_GPIO23_MCU_DRV_M (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S) +#define IO_MUX_GPIO23_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO23_MCU_DRV_S 5 +/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO23_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO23_FUN_WPD_M (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S) +#define IO_MUX_GPIO23_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO23_FUN_WPD_S 7 +/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO23_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO23_FUN_WPU_M (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S) +#define IO_MUX_GPIO23_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO23_FUN_WPU_S 8 +/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO23_FUN_IE (BIT(9)) +#define IO_MUX_GPIO23_FUN_IE_M (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S) +#define IO_MUX_GPIO23_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO23_FUN_IE_S 9 +/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO23_FUN_DRV 0x00000003U +#define IO_MUX_GPIO23_FUN_DRV_M (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S) +#define IO_MUX_GPIO23_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO23_FUN_DRV_S 10 +/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO23_MCU_SEL 0x00000007U +#define IO_MUX_GPIO23_MCU_SEL_M (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S) +#define IO_MUX_GPIO23_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO23_MCU_SEL_S 12 +/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO23_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO23_FILTER_EN_M (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S) +#define IO_MUX_GPIO23_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO23_FILTER_EN_S 15 +/** IO_MUX_GPIO23_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO23_HYS_EN (BIT(16)) +#define IO_MUX_GPIO23_HYS_EN_M (IO_MUX_GPIO23_HYS_EN_V << IO_MUX_GPIO23_HYS_EN_S) +#define IO_MUX_GPIO23_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO23_HYS_EN_S 16 +/** IO_MUX_GPIO23_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO23_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO23_HYS_SEL_M (IO_MUX_GPIO23_HYS_SEL_V << IO_MUX_GPIO23_HYS_SEL_S) +#define IO_MUX_GPIO23_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO23_HYS_SEL_S 17 + +/** IO_MUX_GPIO24_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64) +/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO24_MCU_OE (BIT(0)) +#define IO_MUX_GPIO24_MCU_OE_M (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S) +#define IO_MUX_GPIO24_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO24_MCU_OE_S 0 +/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO24_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO24_SLP_SEL_M (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S) +#define IO_MUX_GPIO24_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO24_SLP_SEL_S 1 +/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO24_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO24_MCU_WPD_M (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S) +#define IO_MUX_GPIO24_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO24_MCU_WPD_S 2 +/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO24_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO24_MCU_WPU_M (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S) +#define IO_MUX_GPIO24_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO24_MCU_WPU_S 3 +/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO24_MCU_IE (BIT(4)) +#define IO_MUX_GPIO24_MCU_IE_M (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S) +#define IO_MUX_GPIO24_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO24_MCU_IE_S 4 +/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO24_MCU_DRV 0x00000003U +#define IO_MUX_GPIO24_MCU_DRV_M (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S) +#define IO_MUX_GPIO24_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO24_MCU_DRV_S 5 +/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO24_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO24_FUN_WPD_M (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S) +#define IO_MUX_GPIO24_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO24_FUN_WPD_S 7 +/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO24_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO24_FUN_WPU_M (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S) +#define IO_MUX_GPIO24_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO24_FUN_WPU_S 8 +/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO24_FUN_IE (BIT(9)) +#define IO_MUX_GPIO24_FUN_IE_M (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S) +#define IO_MUX_GPIO24_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO24_FUN_IE_S 9 +/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO24_FUN_DRV 0x00000003U +#define IO_MUX_GPIO24_FUN_DRV_M (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S) +#define IO_MUX_GPIO24_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO24_FUN_DRV_S 10 +/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO24_MCU_SEL 0x00000007U +#define IO_MUX_GPIO24_MCU_SEL_M (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S) +#define IO_MUX_GPIO24_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO24_MCU_SEL_S 12 +/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO24_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO24_FILTER_EN_M (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S) +#define IO_MUX_GPIO24_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO24_FILTER_EN_S 15 +/** IO_MUX_GPIO24_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO24_HYS_EN (BIT(16)) +#define IO_MUX_GPIO24_HYS_EN_M (IO_MUX_GPIO24_HYS_EN_V << IO_MUX_GPIO24_HYS_EN_S) +#define IO_MUX_GPIO24_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO24_HYS_EN_S 16 +/** IO_MUX_GPIO24_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO24_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO24_HYS_SEL_M (IO_MUX_GPIO24_HYS_SEL_V << IO_MUX_GPIO24_HYS_SEL_S) +#define IO_MUX_GPIO24_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO24_HYS_SEL_S 17 + +/** IO_MUX_GPIO25_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68) +/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO25_MCU_OE (BIT(0)) +#define IO_MUX_GPIO25_MCU_OE_M (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S) +#define IO_MUX_GPIO25_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO25_MCU_OE_S 0 +/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO25_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO25_SLP_SEL_M (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S) +#define IO_MUX_GPIO25_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO25_SLP_SEL_S 1 +/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO25_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO25_MCU_WPD_M (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S) +#define IO_MUX_GPIO25_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO25_MCU_WPD_S 2 +/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO25_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO25_MCU_WPU_M (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S) +#define IO_MUX_GPIO25_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO25_MCU_WPU_S 3 +/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO25_MCU_IE (BIT(4)) +#define IO_MUX_GPIO25_MCU_IE_M (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S) +#define IO_MUX_GPIO25_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO25_MCU_IE_S 4 +/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO25_MCU_DRV 0x00000003U +#define IO_MUX_GPIO25_MCU_DRV_M (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S) +#define IO_MUX_GPIO25_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO25_MCU_DRV_S 5 +/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO25_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO25_FUN_WPD_M (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S) +#define IO_MUX_GPIO25_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO25_FUN_WPD_S 7 +/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO25_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO25_FUN_WPU_M (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S) +#define IO_MUX_GPIO25_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO25_FUN_WPU_S 8 +/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO25_FUN_IE (BIT(9)) +#define IO_MUX_GPIO25_FUN_IE_M (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S) +#define IO_MUX_GPIO25_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO25_FUN_IE_S 9 +/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO25_FUN_DRV 0x00000003U +#define IO_MUX_GPIO25_FUN_DRV_M (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S) +#define IO_MUX_GPIO25_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO25_FUN_DRV_S 10 +/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO25_MCU_SEL 0x00000007U +#define IO_MUX_GPIO25_MCU_SEL_M (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S) +#define IO_MUX_GPIO25_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO25_MCU_SEL_S 12 +/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO25_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO25_FILTER_EN_M (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S) +#define IO_MUX_GPIO25_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO25_FILTER_EN_S 15 +/** IO_MUX_GPIO25_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO25_HYS_EN (BIT(16)) +#define IO_MUX_GPIO25_HYS_EN_M (IO_MUX_GPIO25_HYS_EN_V << IO_MUX_GPIO25_HYS_EN_S) +#define IO_MUX_GPIO25_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO25_HYS_EN_S 16 +/** IO_MUX_GPIO25_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO25_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO25_HYS_SEL_M (IO_MUX_GPIO25_HYS_SEL_V << IO_MUX_GPIO25_HYS_SEL_S) +#define IO_MUX_GPIO25_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO25_HYS_SEL_S 17 + +/** IO_MUX_GPIO26_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c) +/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO26_MCU_OE (BIT(0)) +#define IO_MUX_GPIO26_MCU_OE_M (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S) +#define IO_MUX_GPIO26_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO26_MCU_OE_S 0 +/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO26_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO26_SLP_SEL_M (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S) +#define IO_MUX_GPIO26_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO26_SLP_SEL_S 1 +/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO26_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO26_MCU_WPD_M (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S) +#define IO_MUX_GPIO26_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO26_MCU_WPD_S 2 +/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO26_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO26_MCU_WPU_M (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S) +#define IO_MUX_GPIO26_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO26_MCU_WPU_S 3 +/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO26_MCU_IE (BIT(4)) +#define IO_MUX_GPIO26_MCU_IE_M (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S) +#define IO_MUX_GPIO26_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO26_MCU_IE_S 4 +/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO26_MCU_DRV 0x00000003U +#define IO_MUX_GPIO26_MCU_DRV_M (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S) +#define IO_MUX_GPIO26_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO26_MCU_DRV_S 5 +/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO26_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO26_FUN_WPD_M (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S) +#define IO_MUX_GPIO26_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO26_FUN_WPD_S 7 +/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO26_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO26_FUN_WPU_M (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S) +#define IO_MUX_GPIO26_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO26_FUN_WPU_S 8 +/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO26_FUN_IE (BIT(9)) +#define IO_MUX_GPIO26_FUN_IE_M (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S) +#define IO_MUX_GPIO26_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO26_FUN_IE_S 9 +/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO26_FUN_DRV 0x00000003U +#define IO_MUX_GPIO26_FUN_DRV_M (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S) +#define IO_MUX_GPIO26_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO26_FUN_DRV_S 10 +/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO26_MCU_SEL 0x00000007U +#define IO_MUX_GPIO26_MCU_SEL_M (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S) +#define IO_MUX_GPIO26_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO26_MCU_SEL_S 12 +/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO26_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO26_FILTER_EN_M (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S) +#define IO_MUX_GPIO26_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO26_FILTER_EN_S 15 +/** IO_MUX_GPIO26_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO26_HYS_EN (BIT(16)) +#define IO_MUX_GPIO26_HYS_EN_M (IO_MUX_GPIO26_HYS_EN_V << IO_MUX_GPIO26_HYS_EN_S) +#define IO_MUX_GPIO26_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO26_HYS_EN_S 16 +/** IO_MUX_GPIO26_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO26_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO26_HYS_SEL_M (IO_MUX_GPIO26_HYS_SEL_V << IO_MUX_GPIO26_HYS_SEL_S) +#define IO_MUX_GPIO26_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO26_HYS_SEL_S 17 + +/** IO_MUX_DATE_REG register + * IO MUX Version Control Register + */ +#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc) +/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36708704; + * Version control register + */ +#define IO_MUX_REG_DATE 0x0FFFFFFFU +#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) +#define IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define IO_MUX_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/io_mux_struct.h b/components/soc/esp32c5/include/soc/io_mux_struct.h new file mode 100644 index 00000000000..85dc6ac9075 --- /dev/null +++ b/components/soc/esp32c5/include/soc/io_mux_struct.h @@ -0,0 +1,143 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Registers */ +/** Type of pin_ctrl register + * Clock Output Configuration Register + */ +typedef union { + struct { + /** clk_out1 : R/W; bitpos: [4:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ + uint32_t clk_out1:5; + /** clk_out2 : R/W; bitpos: [9:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ + uint32_t clk_out2:5; + /** clk_out3 : R/W; bitpos: [14:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ + uint32_t clk_out3:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} io_mux_pin_ctrl_reg_t; + +/** Type of gpion register + * IO MUX Configure Register for pad XTAL_32K_P + */ +typedef union { + struct { + /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ + uint32_t gpion_mcu_oe:1; + /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ + uint32_t gpion_slp_sel:1; + /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ + uint32_t gpion_mcu_wpd:1; + /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ + uint32_t gpion_mcu_wpu:1; + /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ + uint32_t gpion_mcu_ie:1; + /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ + uint32_t gpion_mcu_drv:2; + /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ + uint32_t gpion_fun_wpd:1; + /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ + uint32_t gpion_fun_wpu:1; + /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ + uint32_t gpion_fun_ie:1; + /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ + uint32_t gpion_fun_drv:2; + /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ + uint32_t gpion_mcu_sel:3; + /** gpion_filter_en : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ + uint32_t gpion_filter_en:1; + /** gpion_hys_en : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ + uint32_t gpion_hys_en:1; + /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ + uint32_t gpion_hys_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} io_mux_gpion_reg_t; + +/** Type of date register + * IO MUX Version Control Register + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 36708704; + * Version control register + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} io_mux_date_reg_t; + + +typedef struct io_mux_dev_t { + volatile io_mux_pin_ctrl_reg_t pin_ctrl; + volatile io_mux_gpion_reg_t gpion[27]; + uint32_t reserved_070[35]; + volatile io_mux_date_reg_t date; +} io_mux_dev_t; + +extern io_mux_dev_t IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/keymng_reg.h b/components/soc/esp32c5/include/soc/keymng_reg.h new file mode 100644 index 00000000000..d75565dbc8b --- /dev/null +++ b/components/soc/esp32c5/include/soc/keymng_reg.h @@ -0,0 +1,337 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** KEYMNG_CLK_REG register + * Key Manager clock gate control register + */ +#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) +/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define KEYMNG_CLK_EN (BIT(0)) +#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S) +#define KEYMNG_CLK_EN_V 0x00000001U +#define KEYMNG_CLK_EN_S 0 +/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) +#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) +#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_MEM_CG_FORCE_ON_S 1 + +/** KEYMNG_INT_RAW_REG register + * Key Manager interrupt raw register, valid in level. + */ +#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) +/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) +#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) +#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_RAW_S 0 +/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) +#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) +#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_RAW_S 1 +/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) +#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) +#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_POST_DONE_INT_RAW_S 2 + +/** KEYMNG_INT_ST_REG register + * Key Manager interrupt status register. + */ +#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) +/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) +#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ST_S 0 +/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) +#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ST_S 1 +/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ST (BIT(2)) +#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) +#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ST_S 2 + +/** KEYMNG_INT_ENA_REG register + * Key Manager interrupt enable register. + */ +#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) +/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) +#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ENA_S 0 +/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) +#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ENA_S 1 +/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) +#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) +#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ENA_S 2 + +/** KEYMNG_INT_CLR_REG register + * Key Manager interrupt clear register. + */ +#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) +/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) +#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) +#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_CLR_S 0 +/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) +#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) +#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_CLR_S 1 +/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) +#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) +#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_POST_DONE_INT_CLR_S 2 + +/** KEYMNG_STATIC_REG register + * Key Manager static configuration register + */ +#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) +/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [1:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key + */ +#define KEYMNG_USE_EFUSE_KEY 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S) +#define KEYMNG_USE_EFUSE_KEY_V 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_S 0 +/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ +#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) +#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_S 4 +/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY (BIT(9)) +#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) +#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_S 9 +/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0; + * Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use + * xts-aes-128. + */ +#define KEYMNG_XTS_AES_KEY_LEN (BIT(10)) +#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S) +#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U +#define KEYMNG_XTS_AES_KEY_LEN_S 10 + +/** KEYMNG_LOCK_REG register + * Key Manager static configuration locker register + */ +#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) +/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [1:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 +/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ +#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4)) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4 +/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5)) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5 +/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_xts_aes_key_len. + */ +#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6)) +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S) +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6 + +/** KEYMNG_CONF_REG register + * Key Manager configuration register + */ +#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) +/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ +#define KEYMNG_KGEN_MODE 0x00000007U +#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) +#define KEYMNG_KGEN_MODE_V 0x00000007U +#define KEYMNG_KGEN_MODE_S 0 +/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3: + * xts_256_2_key. 4. xts_128_key. others: reserved. + */ +#define KEYMNG_KEY_PURPOSE 0x0000000FU +#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) +#define KEYMNG_KEY_PURPOSE_V 0x0000000FU +#define KEYMNG_KEY_PURPOSE_S 3 + +/** KEYMNG_START_REG register + * Key Manager control register + */ +#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) +/** KEYMNG_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ +#define KEYMNG_START (BIT(0)) +#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) +#define KEYMNG_START_V 0x00000001U +#define KEYMNG_START_S 0 +/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ +#define KEYMNG_CONTINUE (BIT(1)) +#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) +#define KEYMNG_CONTINUE_V 0x00000001U +#define KEYMNG_CONTINUE_S 1 + +/** KEYMNG_STATE_REG register + * Key Manager state register + */ +#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) +/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define KEYMNG_STATE 0x00000003U +#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) +#define KEYMNG_STATE_V 0x00000003U +#define KEYMNG_STATE_S 0 + +/** KEYMNG_RESULT_REG register + * Key Manager operation result register + */ +#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) +/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ +#define KEYMNG_PROC_RESULT (BIT(0)) +#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) +#define KEYMNG_PROC_RESULT_V 0x00000001U +#define KEYMNG_PROC_RESULT_S 0 + +/** KEYMNG_KEY_VLD_REG register + * Key Manager key status register + */ +#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) +/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S) +#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_VLD_S 0 +/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_xts. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_XTS_VLD (BIT(1)) +#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S) +#define KEYMNG_KEY_XTS_VLD_V 0x00000001U +#define KEYMNG_KEY_XTS_VLD_S 1 + +/** KEYMNG_HUK_VLD_REG register + * Key Manager HUK status register + */ +#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) +/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ +#define KEYMNG_HUK_VALID (BIT(0)) +#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) +#define KEYMNG_HUK_VALID_V 0x00000001U +#define KEYMNG_HUK_VALID_S 0 + +/** KEYMNG_DATE_REG register + * Version control register + */ +#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704; + * Key Manager version control register. + */ +#define KEYMNG_DATE 0x0FFFFFFFU +#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) +#define KEYMNG_DATE_V 0x0FFFFFFFU +#define KEYMNG_DATE_S 0 + +/** KEYMNG_ASSIST_INFO_MEM register + * The memory that stores assist key info. + */ +#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) +#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_PUBLIC_INFO_MEM register + * The memory that stores public key info. + */ +#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) +#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_SW_INIT_KEY_MEM register + * The memory that stores software written init key. + */ +#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) +#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/include/soc/keymng_struct.h new file mode 100644 index 00000000000..b809a7ce27f --- /dev/null +++ b/components/soc/esp32c5/include/soc/keymng_struct.h @@ -0,0 +1,340 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * Key Manager clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Key Manager interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_raw_reg_t; + +/** Type of int_st register + * Key Manager interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_st_reg_t; + +/** Type of int_ena register + * Key Manager interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_ena_reg_t; + +/** Type of int_clr register + * Key Manager interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_clr_reg_t; + + +/** Group: Static configuration registers */ +/** Type of static register + * Key Manager static configuration register + */ +typedef union { + struct { + /** use_efuse_key : R/W; bitpos: [1:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key + */ + uint32_t use_efuse_key:2; + uint32_t reserved_2:2; + /** rnd_switch_cycle : R/W; bitpos: [8:4]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ + uint32_t rnd_switch_cycle:5; + /** use_sw_init_key : R/W; bitpos: [9]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ + uint32_t use_sw_init_key:1; + /** xts_aes_key_len : R/W; bitpos: [10]; default: 0; + * Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use + * xts-aes-128. + */ + uint32_t xts_aes_key_len:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} keymng_static_reg_t; + +/** Type of lock register + * Key Manager static configuration locker register + */ +typedef union { + struct { + /** use_efuse_key_lock : R/W1; bitpos: [1:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ + uint32_t use_efuse_key_lock:2; + uint32_t reserved_2:2; + /** rnd_switch_cycle_lock : R/W1; bitpos: [4]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ + uint32_t rnd_switch_cycle_lock:1; + /** use_sw_init_key_lock : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ + uint32_t use_sw_init_key_lock:1; + /** xts_aes_key_len_lock : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_xts_aes_key_len. + */ + uint32_t xts_aes_key_len_lock:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_lock_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** kgen_mode : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ + uint32_t kgen_mode:3; + /** key_purpose : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3: + * xts_256_2_key. 4. xts_128_key. others: reserved. + */ + uint32_t key_purpose:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * Key Manager control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ + uint32_t continue:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * Key Manager state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * Key Manager operation result register + */ +typedef union { + struct { + /** proc_result : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ + uint32_t proc_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_result_reg_t; + +/** Type of key_vld register + * Key Manager key status register + */ +typedef union { + struct { + /** key_ecdsa_vld : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_ecdsa_vld:1; + /** key_xts_vld : RO; bitpos: [1]; default: 0; + * The status bit for key_xts. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_xts_vld:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_key_vld_reg_t; + +/** Type of huk_vld register + * Key Manager HUK status register + */ +typedef union { + struct { + /** huk_valid : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ + uint32_t huk_valid:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_huk_vld_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * Key Manager version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} keymng_date_reg_t; + + +typedef struct keymng_dev_t { + uint32_t reserved_000; + volatile keymng_clk_reg_t clk; + volatile keymng_int_raw_reg_t int_raw; + volatile keymng_int_st_reg_t int_st; + volatile keymng_int_ena_reg_t int_ena; + volatile keymng_int_clr_reg_t int_clr; + volatile keymng_static_reg_t static; + volatile keymng_lock_reg_t lock; + volatile keymng_conf_reg_t conf; + volatile keymng_start_reg_t start; + volatile keymng_state_reg_t state; + volatile keymng_result_reg_t result; + volatile keymng_key_vld_reg_t key_vld; + volatile keymng_huk_vld_reg_t huk_vld; + uint32_t reserved_038[49]; + volatile keymng_date_reg_t date; + volatile uint32_t assist_info[16]; + volatile uint32_t public_info[16]; + volatile uint32_t sw_init_key[8]; +} keymng_dev_t; + +extern keymng_dev_t KEYMNG; + +#ifndef __cplusplus +_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ledc_reg.h b/components/soc/esp32c5/include/soc/ledc_reg.h new file mode 100644 index 00000000000..6f13034d720 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ledc_reg.h @@ -0,0 +1,2334 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 0.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 0 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, + * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel + * 0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt + * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 0. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 0. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 1.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 1 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, + * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel + * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt + * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 1. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 1. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 2.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 2 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, + * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel + * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt + * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 2. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 2. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 3.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 3 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, + * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel + * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt + * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 3. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 3. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 4.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 4 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, + * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel + * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt + * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 4. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 4. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 5.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 5 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, + * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel + * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt + * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 5. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 5. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration register + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 0. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 0.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 0. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and + * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value register + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration register + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 1. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 1.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 1. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and + * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value register + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration register + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 2. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 2.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 2. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and + * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value register + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration register + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 3. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 3.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 3. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and + * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value register + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Interrupt raw status register + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/** LEDC_INT_ST_REG register + * Interrupt masked status register + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/** LEDC_INT_ENA_REG register + * Interrupt enable register + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/** LEDC_INT_CLR_REG register + * Interrupt clear register + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch0. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch1. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch2. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch3. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch4. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch5. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer0. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer1. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer2. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer3. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 captured count value register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 captured count value register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 captured count value register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 captured count value register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * LEDC global configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 36716928; + * Configures the version. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ledc_struct.h b/components/soc/esp32c5/include/soc/ledc_struct.h new file mode 100644 index 00000000000..c068877af05 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ledc_struct.h @@ -0,0 +1,1080 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel n selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ + uint32_t timer_sel_chn:2; + /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel n.\\0: Signal output + * disable\\1: Signal output enable + */ + uint32_t sig_out_en_chn:1; + /** idle_lv_chn : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel n is inactive. Valid only when + * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + */ + uint32_t idle_lv_chn:1; + /** para_up_chn : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, + * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel + * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ + uint32_t para_up_chn:1; + /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt + * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num_chn:10; + /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + */ + uint32_t ovf_cnt_en_chn:1; + /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ + uint32_t ovf_cnt_reset_chn:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel n. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ + uint32_t hpoint_chn:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + +/** Type of chn_duty register + * Initial duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel n. + */ + uint32_t duty_chn:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ + uint32_t duty_start_chn:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of chn_duty_r register + * Current duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn_r : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel n. + */ + uint32_t duty_chn_r:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + + +/** Group: timer conf */ +/** Type of timern_conf register + * Timer n configuration register + */ +typedef union { + struct { + /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer n. + */ + uint32_t timern_duty_res:5; + /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer n.The least significant eight bits + * represent the fractional part. + */ + uint32_t clk_div_timern:18; + /** timern_pause : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + */ + uint32_t timern_pause:1; + /** timern_rst : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer n. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ + uint32_t timern_rst:1; + uint32_t reserved_25:1; + /** timern_para_up : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and + * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ + uint32_t timern_para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timern_conf_reg_t; + +/** Type of timern_value register + * Timer n current counter value register + */ +typedef union { + struct { + /** timern_cnt : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer n. + */ + uint32_t timern_cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_value_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: gamma */ +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t chn_gamma_entry_num:5; + /** chn_gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Pause + */ + uint32_t chn_gamma_pause:1; + /** chn_gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Resume + */ + uint32_t chn_gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + + +/** Group: ledc etm */ +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + uint32_t reserved_6:2; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + uint32_t reserved_14:2; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + uint32_t reserved_14:2; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + uint32_t reserved_22:2; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + uint32_t reserved_6:2; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + uint32_t reserved_14:2; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + + +/** Group: timer */ +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timern_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timern_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timern_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + + +/** Group: ram */ +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + uint32_t reserved_8:23; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 36716928; + * Configures the version. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + +typedef struct { + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_rd; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[6]; +} ledc_ch_group_reg_t; + +typedef struct { + volatile ledc_timern_conf_reg_t conf; + volatile ledc_timern_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_timerx_reg_t timer[4]; +} ledc_timer_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_conf_reg_t gamma_conf[6]; +} ledc_ch_gamma_conf_group_reg_t; + +typedef struct { + volatile ledc_timern_cmp_reg_t cmp[4]; +} ledc_timer_cmp_group_reg_t; + +typedef struct { + volatile ledc_timern_cnt_cap_reg_t cnt_cap[4]; +} ledc_timer_cnt_cap_group_reg_t; + +typedef struct ledc_dev_t { + volatile ledc_ch_group_reg_t channel_group[1]; + uint32_t reserved_078[10]; + volatile ledc_timer_group_reg_t timer_group[1]; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1]; + uint32_t reserved_118[2]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_12c[5]; + volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1]; + volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1]; + uint32_t reserved_160[4]; + volatile ledc_conf_reg_t conf; + volatile ledc_date_reg_t date; +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h new file mode 100644 index 00000000000..079aff0bd30 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h @@ -0,0 +1,228 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8) +/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_S 0 + +/** LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10) +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14) +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18) +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c) +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384; + * need_des + */ +#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 0 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h new file mode 100644 index 00000000000..a9f5e7dae9d --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h @@ -0,0 +1,252 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of fib_enable register + * need_des + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384; + * need_des + */ + uint32_t lp_ana_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct lp_ana_dev_t { + volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl; + volatile lp_ana_fib_enable_reg_t fib_enable; + volatile lp_ana_int_raw_reg_t int_raw; + volatile lp_ana_int_st_reg_t int_st; + volatile lp_ana_int_ena_reg_t int_ena; + volatile lp_ana_int_clr_reg_t int_clr; + volatile lp_ana_lp_int_raw_reg_t lp_int_raw; + volatile lp_ana_lp_int_st_reg_t lp_int_st; + volatile lp_ana_lp_int_ena_reg_t lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_030[243]; + volatile lp_ana_date_reg_t date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_aon_reg.h b/components/soc/esp32c5/include/soc/lp_aon_reg.h new file mode 100644 index 00000000000..39b2fb96741 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_aon_reg.h @@ -0,0 +1,466 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_LPBUS_REG register + * need_des + */ +#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) +/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 +/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 +/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 +/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) +#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) +#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_S 31 + +/** LP_AON_SDIO_ACTIVE_REG register + * need_des + */ +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des + */ +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_MODEM_BUS_REG register + * need_des + */ +#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58) +/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31)) +#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S) +#define LP_AON_MODEM_SYNC_BRIDGE_EN_V 0x00000001U +#define LP_AON_MODEM_SYNC_BRIDGE_EN_S 31 + +/** LP_AON_AUDIO_CODEC_CTRL_REG register + * need_des + */ +#define LP_AON_AUDIO_CODEC_CTRL_REG (DR_REG_LP_AON_BASE + 0x5c) +/** LP_AON_RTC_XPD_SDADC : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_RTC_XPD_SDADC (BIT(0)) +#define LP_AON_RTC_XPD_SDADC_M (LP_AON_RTC_XPD_SDADC_V << LP_AON_RTC_XPD_SDADC_S) +#define LP_AON_RTC_XPD_SDADC_V 0x00000001U +#define LP_AON_RTC_XPD_SDADC_S 0 +/** LP_AON_RTC_EN_CLK_AUDIO_DAC : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_RTC_EN_CLK_AUDIO_DAC (BIT(1)) +#define LP_AON_RTC_EN_CLK_AUDIO_DAC_M (LP_AON_RTC_EN_CLK_AUDIO_DAC_V << LP_AON_RTC_EN_CLK_AUDIO_DAC_S) +#define LP_AON_RTC_EN_CLK_AUDIO_DAC_V 0x00000001U +#define LP_AON_RTC_EN_CLK_AUDIO_DAC_S 1 +/** LP_AON_RTC_XPD_BIAS_AUDIO_DAC : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC (BIT(2)) +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_M (LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V << LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S) +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V 0x00000001U +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S 2 +/** LP_AON_RTC_XPD_PLLA : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_AON_RTC_XPD_PLLA (BIT(3)) +#define LP_AON_RTC_XPD_PLLA_M (LP_AON_RTC_XPD_PLLA_V << LP_AON_RTC_XPD_PLLA_S) +#define LP_AON_RTC_XPD_PLLA_V 0x00000001U +#define LP_AON_RTC_XPD_PLLA_S 3 + +/** LP_AON_SPRAM_CTRL_REG register + * need_des + */ +#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60) +/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S) +#define LP_AON_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_AON_SPRAM_MEM_AUX_CTRL_S 0 + +/** LP_AON_SPRF_CTRL_REG register + * need_des + */ +#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64) +/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S) +#define LP_AON_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_AON_SPRF_MEM_AUX_CTRL_S 0 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_aon_struct.h b/components/soc/esp32c5/include/soc/lp_aon_struct.h new file mode 100644 index 00000000000..4e3ce38a483 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_aon_struct.h @@ -0,0 +1,365 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of store n register + * need_des + */ +typedef union { + struct { + /** lp_aon_store : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store:32; + }; + uint32_t val; +} lp_aon_store_reg_t; + +/** Type of gpio_mux register + * need_des + */ +typedef union { + struct { + /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of sys_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t force_download_boot:1; + /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_reset:1; + /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t cpu_core0_ocd_halt_on_reset:1; + /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t cpu_core0_stat_vector_sel:1; + /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status:8; + uint32_t reserved_8:6; + /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status_clr:1; + /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t ext_wakeup_sel:8; + /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t ext_wakeup_lv:8; + /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of lpbus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_fsm_idle:1; + /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_sel_status:1; + /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t fast_mem_mux_sel_update:1; + /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_sel:1; + }; + uint32_t val; +} lp_aon_lpbus_reg_t; + +/** Type of sdio_active register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des + */ + uint32_t sdio_act_dnum:10; + }; + uint32_t val; +} lp_aon_sdio_active_reg_t; + +/** Type of lpcore register + * need_des + */ +typedef union { + struct { + /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag_clr:1; + /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of modem_bus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t modem_sync_bridge_en:1; + }; + uint32_t val; +} lp_aon_modem_bus_reg_t; + +/** Type of audio_codec_ctrl register + * need_des + */ +typedef union { + struct { + /** rtc_xpd_sdadc : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t rtc_xpd_sdadc:1; + /** rtc_en_clk_audio_dac : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t rtc_en_clk_audio_dac:1; + /** rtc_xpd_bias_audio_dac : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t rtc_xpd_bias_audio_dac:1; + /** rtc_xpd_plla : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t rtc_xpd_plla:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_aon_audio_codec_ctrl_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +/** Group: Configuration Register */ +/** Type of spram_ctrl register + * need_des + */ +typedef union { + struct { + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t spram_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_aon_spram_ctrl_reg_t; + +/** Type of sprf_ctrl register + * need_des + */ +typedef union { + struct { + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_aon_sprf_ctrl_reg_t; + + +typedef struct lp_aon_dev_t { + volatile lp_aon_store_reg_t store[10]; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + volatile lp_aon_lpbus_reg_t lpbus; + volatile lp_aon_sdio_active_reg_t sdio_active; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + volatile lp_aon_modem_bus_reg_t modem_bus; + volatile lp_aon_audio_codec_ctrl_reg_t audio_codec_ctrl; + volatile lp_aon_spram_ctrl_reg_t spram_ctrl; + volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl; + uint32_t reserved_068[229]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/include/soc/lp_apm0_reg.h new file mode 100644 index 00000000000..f2228c5ab32 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm0_reg.h @@ -0,0 +1,534 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM0_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) +#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_S 0 + +/** LP_APM0_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) +/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) +#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_S 0 + +/** LP_APM0_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) +/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) +#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_S 0 + +/** LP_APM0_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) +/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) +#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_X_S 0 +/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) +#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_W_S 1 +/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) +#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_R_S 2 +/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) +#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_X_S 4 +/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) +#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_W_S 5 +/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) +#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_R_S 6 +/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) +#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_X_S 8 +/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) +#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_W_S 9 +/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) +#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_R_S 10 +/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM0_REGION0_LOCK (BIT(11)) +#define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S) +#define LP_APM0_REGION0_LOCK_V 0x00000001U +#define LP_APM0_REGION0_LOCK_S 11 + +/** LP_APM0_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) +/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) +#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_S 0 + +/** LP_APM0_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) +/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) +#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_S 0 + +/** LP_APM0_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) +/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) +#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_X_S 0 +/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) +#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_W_S 1 +/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) +#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_R_S 2 +/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) +#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_X_S 4 +/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) +#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_W_S 5 +/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) +#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_R_S 6 +/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) +#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_X_S 8 +/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) +#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_W_S 9 +/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) +#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_R_S 10 +/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ +#define LP_APM0_REGION1_LOCK (BIT(11)) +#define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S) +#define LP_APM0_REGION1_LOCK_V 0x00000001U +#define LP_APM0_REGION1_LOCK_S 11 + +/** LP_APM0_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) +/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) +#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_S 0 + +/** LP_APM0_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) +/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) +#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_S 0 + +/** LP_APM0_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) +/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) +#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_X_S 0 +/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) +#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_W_S 1 +/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) +#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_R_S 2 +/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) +#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_X_S 4 +/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) +#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_W_S 5 +/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) +#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_R_S 6 +/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) +#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_X_S 8 +/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) +#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_W_S 9 +/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) +#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_R_S 10 +/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ +#define LP_APM0_REGION2_LOCK (BIT(11)) +#define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S) +#define LP_APM0_REGION2_LOCK_V 0x00000001U +#define LP_APM0_REGION2_LOCK_S 11 + +/** LP_APM0_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) +/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) +#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_S 0 + +/** LP_APM0_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) +/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) +#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_S 0 + +/** LP_APM0_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) +/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) +#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_X_S 0 +/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) +#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_W_S 1 +/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) +#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_R_S 2 +/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) +#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_X_S 4 +/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) +#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_W_S 5 +/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) +#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_R_S 6 +/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) +#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_X_S 8 +/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) +#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_W_S 9 +/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) +#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_R_S 10 +/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ +#define LP_APM0_REGION3_LOCK (BIT(11)) +#define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S) +#define LP_APM0_REGION3_LOCK_V 0x00000001U +#define LP_APM0_REGION3_LOCK_S 11 + +/** LP_APM0_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) +/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) +#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM0_M0_PMS_FUNC_EN_S 0 + +/** LP_APM0_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) +/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) +#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM0_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) +/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) +#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM0_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM0_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) +#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_S 0 +/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) +#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_S 16 +/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) +#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_S 18 + +/** LP_APM0_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) +/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) +#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM0_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) +/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM0_M0_APM_INT_EN (BIT(0)) +#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) +#define LP_APM0_M0_APM_INT_EN_V 0x00000001U +#define LP_APM0_M0_APM_INT_EN_S 0 + +/** LP_APM0_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) +/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM0_CLK_EN (BIT(0)) +#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) +#define LP_APM0_CLK_EN_V 0x00000001U +#define LP_APM0_CLK_EN_S 0 + +/** LP_APM0_DATE_REG register + * Version register + */ +#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) +/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ +#define LP_APM0_DATE 0x0FFFFFFFU +#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) +#define LP_APM0_DATE_V 0x0FFFFFFFU +#define LP_APM0_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/include/soc/lp_apm0_struct.h new file mode 100644 index 00000000000..72fc8a3b6aa --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm0_struct.h @@ -0,0 +1,515 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm0_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm0_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm0_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm0_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm0_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm0_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm0_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm0_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm0_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + /** region0_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t region0_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + /** region1_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ + uint32_t region1_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + /** region2_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ + uint32_t region2_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + /** region3_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ + uint32_t region3_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm0_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm0_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm0_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm0_date_reg_t; + + +typedef struct lp_apm0_dev_t { + volatile lp_apm0_region_filter_en_reg_t region_filter_en; + volatile lp_apm0_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm0_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm0_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm0_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm0_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm0_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm0_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm0_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm0_func_ctrl_reg_t func_ctrl; + volatile lp_apm0_m0_status_reg_t m0_status; + volatile lp_apm0_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm0_int_en_reg_t int_en; + volatile lp_apm0_clock_gate_reg_t clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm0_date_reg_t date; +} lp_apm0_dev_t; + +extern lp_apm0_dev_t LP_APM0; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm_reg.h b/components/soc/esp32c5/include/soc/lp_apm_reg.h new file mode 100644 index 00000000000..17b6ef43a62 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm_reg.h @@ -0,0 +1,610 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x0000000FU +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 +/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION0_LOCK (BIT(11)) +#define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S) +#define LP_APM_REGION0_LOCK_V 0x00000001U +#define LP_APM_REGION0_LOCK_S 11 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 +/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ +#define LP_APM_REGION1_LOCK (BIT(11)) +#define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S) +#define LP_APM_REGION1_LOCK_V 0x00000001U +#define LP_APM_REGION1_LOCK_S 11 + +/** LP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) +/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) +#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_S 0 + +/** LP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) +/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) +#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_S 0 + +/** LP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) +/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S) +#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_X_S 0 +/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S) +#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_W_S 1 +/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S) +#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_R_S 2 +/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S) +#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_X_S 4 +/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S) +#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_W_S 5 +/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S) +#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_R_S 6 +/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S) +#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_X_S 8 +/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S) +#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_W_S 9 +/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S) +#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_R_S 10 +/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ +#define LP_APM_REGION2_LOCK (BIT(11)) +#define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S) +#define LP_APM_REGION2_LOCK_V 0x00000001U +#define LP_APM_REGION2_LOCK_S 11 + +/** LP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) +/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) +#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_S 0 + +/** LP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) +/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) +#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_S 0 + +/** LP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) +/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S) +#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_X_S 0 +/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S) +#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_W_S 1 +/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S) +#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_R_S 2 +/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S) +#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_X_S 4 +/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S) +#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_W_S 5 +/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S) +#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_R_S 6 +/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S) +#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_X_S 8 +/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S) +#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_W_S 9 +/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S) +#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_R_S 10 +/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ +#define LP_APM_REGION3_LOCK (BIT(11)) +#define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S) +#define LP_APM_REGION3_LOCK_V 0x00000001U +#define LP_APM_REGION3_LOCK_S 11 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 +/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define LP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S) +#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M1_PMS_FUNC_EN_S 1 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_M1_STATUS_REG register + * M1 status register + */ +#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) +/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) +#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M1_EXCEPTION_STATUS_S 0 + +/** LP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) +/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S) +#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M1_REGION_STATUS_CLR_S 0 + +/** LP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) +/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) +#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_S 0 +/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M1_EXCEPTION_MODE 0x00000003U +#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) +#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M1_EXCEPTION_MODE_S 16 +/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M1_EXCEPTION_ID 0x0000001FU +#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) +#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M1_EXCEPTION_ID_S 18 + +/** LP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) +/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) +#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M1_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 +/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define LP_APM_M1_APM_INT_EN (BIT(1)) +#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) +#define LP_APM_M1_APM_INT_EN_V 0x00000001U +#define LP_APM_M1_APM_INT_EN_S 1 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm_struct.h b/components/soc/esp32c5/include/soc/lp_apm_struct.h new file mode 100644 index 00000000000..8f7c3569121 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm_struct.h @@ -0,0 +1,599 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + /** region0_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t region0_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + /** region1_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ + uint32_t region1_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + /** region2_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ + uint32_t region2_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + /** region3_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ + uint32_t region3_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:4; + uint32_t reserved_4:12; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} lp_apm_m1_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct lp_apm_dev_t { + volatile lp_apm_region_filter_en_reg_t region_filter_en; + volatile lp_apm_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm_func_ctrl_reg_t func_ctrl; + volatile lp_apm_m0_status_reg_t m0_status; + volatile lp_apm_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm_m1_status_reg_t m1_status; + volatile lp_apm_m1_status_clr_reg_t m1_status_clr; + volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile lp_apm_int_en_reg_t int_en; + volatile lp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/include/soc/lp_clkrst_reg.h new file mode 100644 index 00000000000..6cd5afc5036 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_clkrst_reg.h @@ -0,0 +1,404 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * need_des + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_HUK_RESET_EN (BIT(27)) +#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S) +#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U +#define LP_CLKRST_HUK_RESET_EN_S 27 +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * need_des + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21 +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * need_des + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_HUK_CLK_SEL (BIT(29)) +#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S) +#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U +#define LP_CLKRST_HUK_CLK_SEL_S 29 +/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) +#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) +#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 +/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) +#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) +#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_UART_CLK_SEL_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h new file mode 100644 index 00000000000..3f348c0cd55 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h @@ -0,0 +1,354 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * need_des + */ + uint32_t fast_clk_sel:2; + /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; + * need_des + */ + uint32_t lp_peri_div_num:8; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t aon_slow_oen:1; + /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t aon_fast_oen:1; + /** sosc_oen : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t sosc_oen:1; + /** fosc_oen : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t fosc_oen:1; + /** osc32k_oen : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t osc32k_oen:1; + /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t xtal32k_oen:1; + /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t core_efuse_oen:1; + /** slow_oen : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t slow_oen:1; + /** fast_oen : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t fast_oen:1; + /** rng_oen : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t rng_oen:1; + /** lpbus_oen : R/W; bitpos: [10]; default: 1; + * need_des + */ + uint32_t lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** huk_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t huk_reset_en:1; + /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t aon_efuse_core_reset_en:1; + /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_timer_reset_en:1; + /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_reset_en:1; + /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of reset_cause register + * need_des + */ +typedef union { + struct { + /** reset_cause : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t reset_cause:5; + /** core0_reset_flag : RO; bitpos: [5]; default: 1; + * need_des + */ + uint32_t core0_reset_flag:1; + uint32_t reserved_6:23; + /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t core0_reset_cause_clr:1; + /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_set:1; + /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of cpu_reset register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ + uint32_t hpcore0_lockup_reset_en:1; + /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_length:3; + /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_en:1; + /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * need_des + */ + uint32_t cpu_stall_wait:5; + /** cpu_stall_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** huk_clk_sel : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t huk_clk_sel:1; + /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_i2c_clk_sel:1; + /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_uart_clk_sel:1; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** clkrst_date : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ + uint32_t clkrst_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct lp_clkrst_dev_t { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_lpperi_reg_t lpperi; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h similarity index 98% rename from components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h rename to components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h index ed40ee7b053..5e67e185b31 100644 --- a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h +++ b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h similarity index 97% rename from components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h rename to components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h index 46aedaf634a..37f45487c33 100644 --- a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h +++ b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/soc/esp32c5/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_reg.h new file mode 100644 index 00000000000..fc0e24966e7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_i2c_reg.h @@ -0,0 +1,1285 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 + +/** LP_I2C_CTR_REG register + * Transmission setting + */ +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 + +/** LP_I2C_SR_REG register + * Describe I2C work status. + */ +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; + * Represents the number of data bytes to be sent. + */ +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 + +/** LP_I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 + +/** LP_I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 + +/** LP_I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 + +/** LP_I2C_DATA_REG register + * Rx FIFO read data. + */ +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 + +/** LP_I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 + +/** LP_I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 + +/** LP_I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to anable the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to anable the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * Write 1 to anable I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 + +/** LP_I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 + +/** LP_I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 + +/** LP_I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 + +/** LP_I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** LP_I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 + +/** LP_I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** LP_I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 + +/** LP_I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 + +/** LP_I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 + +/** LP_I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 + +/** LP_I2C_COMD0_REG register + * I2C command register 0 + */ +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 + +/** LP_I2C_COMD1_REG register + * I2C command register 1 + */ +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 + +/** LP_I2C_COMD2_REG register + * I2C command register 2 + */ +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 + +/** LP_I2C_COMD3_REG register + * I2C command register 3 + */ +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 + +/** LP_I2C_COMD4_REG register + * I2C command register 4 + */ +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 + +/** LP_I2C_COMD5_REG register + * I2C command register 5 + */ +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 + +/** LP_I2C_COMD6_REG register + * I2C command register 6 + */ +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 + +/** LP_I2C_COMD7_REG register + * I2C command register 7 + */ +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 + +/** LP_I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_I2C_M (LP_I2C_SCL_ST_TO_I2C_V << LP_I2C_SCL_ST_TO_I2C_S) +#define LP_I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_I2C_S 0 + +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_I2C_M (LP_I2C_SCL_MAIN_ST_TO_I2C_V << LP_I2C_SCL_MAIN_ST_TO_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** LP_I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 + +/** LP_I2C_DATE_REG register + * Version register + */ +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 35656003; + * Version control register. + */ +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 + +/** LP_I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 + +/** LP_I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_struct.h new file mode 100644 index 00000000000..ad31d582861 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_i2c_struct.h @@ -0,0 +1,963 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ + uint32_t rx_full_ack_level:1; + uint32_t reserved_4:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ + uint32_t conf_upgate:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2c_to_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:4; + uint32_t reserved_4:1; + /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:4; + uint32_t reserved_9:1; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + uint32_t reserved_11:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} lp_i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_i2c_scl_sp_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ + uint32_t resp_rec:1; + uint32_t reserved_1:2; + /** arb_lost : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ + uint32_t bus_busy:1; + uint32_t reserved_5:3; + /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0; + * Represents the number of data bytes to be sent. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_13:5; + /** txfifo_cnt : RO; bitpos: [22:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_23:1; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ + uint32_t rxfifo_raddr:4; + uint32_t reserved_4:1; + /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ + uint32_t rxfifo_waddr:4; + uint32_t reserved_9:1; + /** txfifo_raddr : RO; bitpos: [13:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ + uint32_t txfifo_raddr:4; + uint32_t reserved_14:1; + /** txfifo_waddr : RO; bitpos: [18:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ + uint32_t txfifo_waddr:4; + uint32_t reserved_19:13; + }; + uint32_t val; +} lp_i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : RO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to anable the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to anable the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * Write 1 to anable I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd register + * I2C command register n + */ +typedef union { + struct { + /** command : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ + uint32_t command:14; + uint32_t reserved_14:17; + /** command_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command n is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command_done:1; + }; + uint32_t val; +} lp_i2c_comd_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656003; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} lp_i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} lp_i2c_rxfifo_start_addr_reg_t; + + +typedef struct lp_i2c_dev_t { + volatile lp_i2c_scl_low_period_reg_t scl_low_period; + volatile lp_i2c_ctr_reg_t ctr; + volatile lp_i2c_sr_reg_t sr; + volatile lp_i2c_to_reg_t to; + uint32_t reserved_010; + volatile lp_i2c_fifo_st_reg_t fifo_st; + volatile lp_i2c_fifo_conf_reg_t fifo_conf; + volatile lp_i2c_data_reg_t data; + volatile lp_i2c_int_raw_reg_t int_raw; + volatile lp_i2c_int_clr_reg_t int_clr; + volatile lp_i2c_int_ena_reg_t int_ena; + volatile lp_i2c_int_status_reg_t int_status; + volatile lp_i2c_sda_hold_reg_t sda_hold; + volatile lp_i2c_sda_sample_reg_t sda_sample; + volatile lp_i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile lp_i2c_scl_start_hold_reg_t scl_start_hold; + volatile lp_i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile lp_i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile lp_i2c_filter_cfg_reg_t filter_cfg; + volatile lp_i2c_clk_conf_reg_t clk_conf; + volatile lp_i2c_comd_reg_t comd[8]; + volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf; + uint32_t reserved_084[29]; + volatile lp_i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile lp_i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile lp_i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} lp_i2c_dev_t; + +extern lp_i2c_dev_t LP_I2C; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_io_reg.h b/components/soc/esp32c5/include/soc/lp_io_reg.h new file mode 100644 index 00000000000..6382de6eed6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_io_reg.h @@ -0,0 +1,1263 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_IO_OUT_DATA_REG register + * need des + */ +#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0) +/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_OUT_DATA 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_M (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S) +#define LP_IO_LP_GPIO_OUT_DATA_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_S 0 + +/** LP_IO_OUT_DATA_W1TS_REG register + * need des + */ +#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4) +/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_OUT_DATA_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S) +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S 0 + +/** LP_IO_OUT_DATA_W1TC_REG register + * need des + */ +#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8) +/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_OUT_DATA_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S) +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S 0 + +/** LP_IO_OUT_ENABLE_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc) +/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_ENABLE 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_M (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S) +#define LP_IO_LP_GPIO_ENABLE_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_S 0 + +/** LP_IO_OUT_ENABLE_W1TS_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10) +/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_ENABLE_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TS_M (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S) +#define LP_IO_LP_GPIO_ENABLE_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TS_S 0 + +/** LP_IO_OUT_ENABLE_W1TC_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14) +/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_ENABLE_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TC_M (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S) +#define LP_IO_LP_GPIO_ENABLE_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TC_S 0 + +/** LP_IO_STATUS_REG register + * need des + */ +#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18) +/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_STATUS_INTERRUPT 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S) +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S 0 + +/** LP_IO_STATUS_W1TS_REG register + * need des + */ +#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c) +/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_STATUS_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TS_M (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S) +#define LP_IO_LP_GPIO_STATUS_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TS_S 0 + +/** LP_IO_STATUS_W1TC_REG register + * need des + */ +#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20) +/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_STATUS_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TC_M (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S) +#define LP_IO_LP_GPIO_STATUS_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TC_S 0 + +/** LP_IO_IN_REG register + * need des + */ +#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24) +/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO_IN_DATA_NEXT 0x000000FFU +#define LP_IO_LP_GPIO_IN_DATA_NEXT_M (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S) +#define LP_IO_LP_GPIO_IN_DATA_NEXT_V 0x000000FFU +#define LP_IO_LP_GPIO_IN_DATA_NEXT_S 0 + +/** LP_IO_PIN0_REG register + * need des + */ +#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28) +/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO0_SYNC_BYPASS_M (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO0_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO0_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO0_PAD_DRIVER_M (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S) +#define LP_IO_LP_GPIO0_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO0_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO0_INT_TYPE_M (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S) +#define LP_IO_LP_GPIO0_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO0_INT_TYPE_S 7 +/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO0_FILTER_EN_M (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S) +#define LP_IO_LP_GPIO0_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO0_FILTER_EN_S 11 + +/** LP_IO_PIN1_REG register + * need des + */ +#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c) +/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO1_SYNC_BYPASS_M (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO1_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO1_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO1_PAD_DRIVER_M (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S) +#define LP_IO_LP_GPIO1_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO1_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO1_INT_TYPE_M (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S) +#define LP_IO_LP_GPIO1_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO1_INT_TYPE_S 7 +/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO1_FILTER_EN_M (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S) +#define LP_IO_LP_GPIO1_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO1_FILTER_EN_S 11 + +/** LP_IO_PIN2_REG register + * need des + */ +#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30) +/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO2_SYNC_BYPASS_M (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO2_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO2_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO2_PAD_DRIVER_M (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S) +#define LP_IO_LP_GPIO2_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO2_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO2_INT_TYPE_M (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S) +#define LP_IO_LP_GPIO2_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO2_INT_TYPE_S 7 +/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO2_FILTER_EN_M (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S) +#define LP_IO_LP_GPIO2_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO2_FILTER_EN_S 11 + +/** LP_IO_PIN3_REG register + * need des + */ +#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34) +/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO3_SYNC_BYPASS_M (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO3_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO3_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO3_PAD_DRIVER_M (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S) +#define LP_IO_LP_GPIO3_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO3_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO3_INT_TYPE_M (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S) +#define LP_IO_LP_GPIO3_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO3_INT_TYPE_S 7 +/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO3_FILTER_EN_M (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S) +#define LP_IO_LP_GPIO3_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO3_FILTER_EN_S 11 + +/** LP_IO_PIN4_REG register + * need des + */ +#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38) +/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO4_SYNC_BYPASS_M (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO4_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO4_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO4_PAD_DRIVER_M (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S) +#define LP_IO_LP_GPIO4_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO4_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO4_INT_TYPE_M (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S) +#define LP_IO_LP_GPIO4_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO4_INT_TYPE_S 7 +/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO4_FILTER_EN_M (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S) +#define LP_IO_LP_GPIO4_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO4_FILTER_EN_S 11 + +/** LP_IO_PIN5_REG register + * need des + */ +#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c) +/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO5_SYNC_BYPASS_M (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO5_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO5_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO5_PAD_DRIVER_M (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S) +#define LP_IO_LP_GPIO5_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO5_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO5_INT_TYPE_M (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S) +#define LP_IO_LP_GPIO5_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO5_INT_TYPE_S 7 +/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO5_FILTER_EN_M (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S) +#define LP_IO_LP_GPIO5_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO5_FILTER_EN_S 11 + +/** LP_IO_PIN6_REG register + * need des + */ +#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40) +/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO6_SYNC_BYPASS_M (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO6_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO6_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO6_PAD_DRIVER_M (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S) +#define LP_IO_LP_GPIO6_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO6_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO6_INT_TYPE_M (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S) +#define LP_IO_LP_GPIO6_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO6_INT_TYPE_S 7 +/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO6_FILTER_EN_M (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S) +#define LP_IO_LP_GPIO6_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO6_FILTER_EN_S 11 + +/** LP_IO_PIN7_REG register + * need des + */ +#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44) +/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO7_SYNC_BYPASS_M (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO7_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO7_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO7_PAD_DRIVER_M (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S) +#define LP_IO_LP_GPIO7_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO7_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO7_INT_TYPE_M (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S) +#define LP_IO_LP_GPIO7_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO7_INT_TYPE_S 7 +/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO7_FILTER_EN_M (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S) +#define LP_IO_LP_GPIO7_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO7_FILTER_EN_S 11 + +/** LP_IO_GPIO0_REG register + * need des + */ +#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48) +/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO0_MCU_OE_M (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S) +#define LP_IO_LP_GPIO0_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_OE_S 0 +/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO0_SLP_SEL_M (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S) +#define LP_IO_LP_GPIO0_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO0_SLP_SEL_S 1 +/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO0_MCU_WPD_M (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S) +#define LP_IO_LP_GPIO0_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_WPD_S 2 +/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO0_MCU_WPU_M (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S) +#define LP_IO_LP_GPIO0_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_WPU_S 3 +/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO0_MCU_IE_M (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S) +#define LP_IO_LP_GPIO0_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_IE_S 4 +/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO0_MCU_DRV_M (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S) +#define LP_IO_LP_GPIO0_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO0_MCU_DRV_S 5 +/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO0_FUN_WPD_M (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S) +#define LP_IO_LP_GPIO0_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_WPD_S 7 +/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO0_FUN_WPU_M (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S) +#define LP_IO_LP_GPIO0_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_WPU_S 8 +/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO0_FUN_IE_M (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S) +#define LP_IO_LP_GPIO0_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_IE_S 9 +/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO0_FUN_DRV_M (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S) +#define LP_IO_LP_GPIO0_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO0_FUN_DRV_S 10 +/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO0_MCU_SEL_M (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S) +#define LP_IO_LP_GPIO0_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO0_MCU_SEL_S 12 + +/** LP_IO_GPIO1_REG register + * need des + */ +#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c) +/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO1_MCU_OE_M (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S) +#define LP_IO_LP_GPIO1_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_OE_S 0 +/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO1_SLP_SEL_M (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S) +#define LP_IO_LP_GPIO1_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO1_SLP_SEL_S 1 +/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO1_MCU_WPD_M (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S) +#define LP_IO_LP_GPIO1_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_WPD_S 2 +/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO1_MCU_WPU_M (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S) +#define LP_IO_LP_GPIO1_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_WPU_S 3 +/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO1_MCU_IE_M (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S) +#define LP_IO_LP_GPIO1_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_IE_S 4 +/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO1_MCU_DRV_M (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S) +#define LP_IO_LP_GPIO1_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO1_MCU_DRV_S 5 +/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO1_FUN_WPD_M (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S) +#define LP_IO_LP_GPIO1_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_WPD_S 7 +/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO1_FUN_WPU_M (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S) +#define LP_IO_LP_GPIO1_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_WPU_S 8 +/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO1_FUN_IE_M (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S) +#define LP_IO_LP_GPIO1_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_IE_S 9 +/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO1_FUN_DRV_M (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S) +#define LP_IO_LP_GPIO1_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO1_FUN_DRV_S 10 +/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO1_MCU_SEL_M (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S) +#define LP_IO_LP_GPIO1_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO1_MCU_SEL_S 12 + +/** LP_IO_GPIO2_REG register + * need des + */ +#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50) +/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO2_MCU_OE_M (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S) +#define LP_IO_LP_GPIO2_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_OE_S 0 +/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO2_SLP_SEL_M (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S) +#define LP_IO_LP_GPIO2_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO2_SLP_SEL_S 1 +/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO2_MCU_WPD_M (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S) +#define LP_IO_LP_GPIO2_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_WPD_S 2 +/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO2_MCU_WPU_M (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S) +#define LP_IO_LP_GPIO2_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_WPU_S 3 +/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO2_MCU_IE_M (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S) +#define LP_IO_LP_GPIO2_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_IE_S 4 +/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO2_MCU_DRV_M (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S) +#define LP_IO_LP_GPIO2_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO2_MCU_DRV_S 5 +/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO2_FUN_WPD_M (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S) +#define LP_IO_LP_GPIO2_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_WPD_S 7 +/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO2_FUN_WPU_M (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S) +#define LP_IO_LP_GPIO2_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_WPU_S 8 +/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO2_FUN_IE_M (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S) +#define LP_IO_LP_GPIO2_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_IE_S 9 +/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO2_FUN_DRV_M (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S) +#define LP_IO_LP_GPIO2_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO2_FUN_DRV_S 10 +/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO2_MCU_SEL_M (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S) +#define LP_IO_LP_GPIO2_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO2_MCU_SEL_S 12 + +/** LP_IO_GPIO3_REG register + * need des + */ +#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54) +/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO3_MCU_OE_M (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S) +#define LP_IO_LP_GPIO3_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_OE_S 0 +/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO3_SLP_SEL_M (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S) +#define LP_IO_LP_GPIO3_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO3_SLP_SEL_S 1 +/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO3_MCU_WPD_M (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S) +#define LP_IO_LP_GPIO3_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_WPD_S 2 +/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO3_MCU_WPU_M (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S) +#define LP_IO_LP_GPIO3_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_WPU_S 3 +/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO3_MCU_IE_M (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S) +#define LP_IO_LP_GPIO3_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_IE_S 4 +/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO3_MCU_DRV_M (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S) +#define LP_IO_LP_GPIO3_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO3_MCU_DRV_S 5 +/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO3_FUN_WPD_M (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S) +#define LP_IO_LP_GPIO3_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_WPD_S 7 +/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO3_FUN_WPU_M (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S) +#define LP_IO_LP_GPIO3_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_WPU_S 8 +/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO3_FUN_IE_M (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S) +#define LP_IO_LP_GPIO3_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_IE_S 9 +/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO3_FUN_DRV_M (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S) +#define LP_IO_LP_GPIO3_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO3_FUN_DRV_S 10 +/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO3_MCU_SEL_M (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S) +#define LP_IO_LP_GPIO3_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO3_MCU_SEL_S 12 + +/** LP_IO_GPIO4_REG register + * need des + */ +#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58) +/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO4_MCU_OE_M (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S) +#define LP_IO_LP_GPIO4_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_OE_S 0 +/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO4_SLP_SEL_M (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S) +#define LP_IO_LP_GPIO4_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO4_SLP_SEL_S 1 +/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO4_MCU_WPD_M (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S) +#define LP_IO_LP_GPIO4_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_WPD_S 2 +/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO4_MCU_WPU_M (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S) +#define LP_IO_LP_GPIO4_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_WPU_S 3 +/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO4_MCU_IE_M (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S) +#define LP_IO_LP_GPIO4_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_IE_S 4 +/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO4_MCU_DRV_M (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S) +#define LP_IO_LP_GPIO4_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO4_MCU_DRV_S 5 +/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO4_FUN_WPD_M (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S) +#define LP_IO_LP_GPIO4_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_WPD_S 7 +/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO4_FUN_WPU_M (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S) +#define LP_IO_LP_GPIO4_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_WPU_S 8 +/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO4_FUN_IE_M (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S) +#define LP_IO_LP_GPIO4_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_IE_S 9 +/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO4_FUN_DRV_M (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S) +#define LP_IO_LP_GPIO4_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO4_FUN_DRV_S 10 +/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO4_MCU_SEL_M (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S) +#define LP_IO_LP_GPIO4_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO4_MCU_SEL_S 12 + +/** LP_IO_GPIO5_REG register + * need des + */ +#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c) +/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO5_MCU_OE_M (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S) +#define LP_IO_LP_GPIO5_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_OE_S 0 +/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO5_SLP_SEL_M (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S) +#define LP_IO_LP_GPIO5_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO5_SLP_SEL_S 1 +/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO5_MCU_WPD_M (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S) +#define LP_IO_LP_GPIO5_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_WPD_S 2 +/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO5_MCU_WPU_M (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S) +#define LP_IO_LP_GPIO5_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_WPU_S 3 +/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO5_MCU_IE_M (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S) +#define LP_IO_LP_GPIO5_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_IE_S 4 +/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO5_MCU_DRV_M (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S) +#define LP_IO_LP_GPIO5_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO5_MCU_DRV_S 5 +/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO5_FUN_WPD_M (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S) +#define LP_IO_LP_GPIO5_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_WPD_S 7 +/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO5_FUN_WPU_M (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S) +#define LP_IO_LP_GPIO5_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_WPU_S 8 +/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO5_FUN_IE_M (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S) +#define LP_IO_LP_GPIO5_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_IE_S 9 +/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO5_FUN_DRV_M (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S) +#define LP_IO_LP_GPIO5_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO5_FUN_DRV_S 10 +/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO5_MCU_SEL_M (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S) +#define LP_IO_LP_GPIO5_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO5_MCU_SEL_S 12 + +/** LP_IO_GPIO6_REG register + * need des + */ +#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60) +/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO6_MCU_OE_M (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S) +#define LP_IO_LP_GPIO6_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_OE_S 0 +/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO6_SLP_SEL_M (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S) +#define LP_IO_LP_GPIO6_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO6_SLP_SEL_S 1 +/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO6_MCU_WPD_M (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S) +#define LP_IO_LP_GPIO6_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_WPD_S 2 +/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO6_MCU_WPU_M (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S) +#define LP_IO_LP_GPIO6_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_WPU_S 3 +/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO6_MCU_IE_M (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S) +#define LP_IO_LP_GPIO6_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_IE_S 4 +/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO6_MCU_DRV_M (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S) +#define LP_IO_LP_GPIO6_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO6_MCU_DRV_S 5 +/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO6_FUN_WPD_M (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S) +#define LP_IO_LP_GPIO6_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_WPD_S 7 +/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO6_FUN_WPU_M (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S) +#define LP_IO_LP_GPIO6_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_WPU_S 8 +/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO6_FUN_IE_M (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S) +#define LP_IO_LP_GPIO6_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_IE_S 9 +/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO6_FUN_DRV_M (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S) +#define LP_IO_LP_GPIO6_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO6_FUN_DRV_S 10 +/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO6_MCU_SEL_M (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S) +#define LP_IO_LP_GPIO6_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO6_MCU_SEL_S 12 + +/** LP_IO_GPIO7_REG register + * need des + */ +#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64) +/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO7_MCU_OE_M (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S) +#define LP_IO_LP_GPIO7_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_OE_S 0 +/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO7_SLP_SEL_M (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S) +#define LP_IO_LP_GPIO7_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO7_SLP_SEL_S 1 +/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO7_MCU_WPD_M (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S) +#define LP_IO_LP_GPIO7_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_WPD_S 2 +/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO7_MCU_WPU_M (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S) +#define LP_IO_LP_GPIO7_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_WPU_S 3 +/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO7_MCU_IE_M (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S) +#define LP_IO_LP_GPIO7_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_IE_S 4 +/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO7_MCU_DRV_M (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S) +#define LP_IO_LP_GPIO7_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO7_MCU_DRV_S 5 +/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO7_FUN_WPD_M (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S) +#define LP_IO_LP_GPIO7_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_WPD_S 7 +/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO7_FUN_WPU_M (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S) +#define LP_IO_LP_GPIO7_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_WPU_S 8 +/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO7_FUN_IE_M (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S) +#define LP_IO_LP_GPIO7_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_IE_S 9 +/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO7_FUN_DRV_M (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S) +#define LP_IO_LP_GPIO7_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO7_FUN_DRV_S 10 +/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO7_MCU_SEL_M (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S) +#define LP_IO_LP_GPIO7_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO7_MCU_SEL_S 12 + +/** LP_IO_STATUS_INTERRUPT_REG register + * need des + */ +#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68) +/** LP_IO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0; + * need des + */ +#define LP_IO_STATUS_INTERRUPT_NEXT 0x000000FFU +#define LP_IO_STATUS_INTERRUPT_NEXT_M (LP_IO_STATUS_INTERRUPT_NEXT_V << LP_IO_STATUS_INTERRUPT_NEXT_S) +#define LP_IO_STATUS_INTERRUPT_NEXT_V 0x000000FFU +#define LP_IO_STATUS_INTERRUPT_NEXT_S 0 + +/** LP_IO_DEBUG_SEL0_REG register + * need des + */ +#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c) +/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL0 0x0000007FU +#define LP_IO_LP_DEBUG_SEL0_M (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S) +#define LP_IO_LP_DEBUG_SEL0_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL0_S 0 +/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL1 0x0000007FU +#define LP_IO_LP_DEBUG_SEL1_M (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S) +#define LP_IO_LP_DEBUG_SEL1_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL1_S 7 +/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL2 0x0000007FU +#define LP_IO_LP_DEBUG_SEL2_M (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S) +#define LP_IO_LP_DEBUG_SEL2_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL2_S 14 +/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL3 0x0000007FU +#define LP_IO_LP_DEBUG_SEL3_M (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S) +#define LP_IO_LP_DEBUG_SEL3_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL3_S 21 + +/** LP_IO_DEBUG_SEL1_REG register + * need des + */ +#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70) +/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL4 0x0000007FU +#define LP_IO_LP_DEBUG_SEL4_M (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S) +#define LP_IO_LP_DEBUG_SEL4_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL4_S 0 + +/** LP_IO_LPI2C_REG register + * need des + */ +#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74) +/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1; + * need des + */ +#define LP_IO_LP_I2C_SDA_IE (BIT(30)) +#define LP_IO_LP_I2C_SDA_IE_M (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S) +#define LP_IO_LP_I2C_SDA_IE_V 0x00000001U +#define LP_IO_LP_I2C_SDA_IE_S 30 +/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1; + * need des + */ +#define LP_IO_LP_I2C_SCL_IE (BIT(31)) +#define LP_IO_LP_I2C_SCL_IE_M (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S) +#define LP_IO_LP_I2C_SCL_IE_V 0x00000001U +#define LP_IO_LP_I2C_SCL_IE_S 31 + +/** LP_IO_DATE_REG register + * need des + */ +#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc) +/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032; + * need des + */ +#define LP_IO_LP_IO_DATE 0x7FFFFFFFU +#define LP_IO_LP_IO_DATE_M (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S) +#define LP_IO_LP_IO_DATE_V 0x7FFFFFFFU +#define LP_IO_LP_IO_DATE_S 0 +/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * need des + */ +#define LP_IO_CLK_EN (BIT(31)) +#define LP_IO_CLK_EN_M (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S) +#define LP_IO_CLK_EN_V 0x00000001U +#define LP_IO_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_io_struct.h b/components/soc/esp32c5/include/soc/lp_io_struct.h new file mode 100644 index 00000000000..0a8698c5f72 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_io_struct.h @@ -0,0 +1,740 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of out_data register + * need des + */ +typedef union { + struct { + /** lp_gpio_out_data : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t lp_gpio_out_data:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_reg_t; + +/** Type of out_data_w1ts register + * need des + */ +typedef union { + struct { + /** lp_gpio_out_data_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t lp_gpio_out_data_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_w1ts_reg_t; + +/** Type of out_data_w1tc register + * need des + */ +typedef union { + struct { + /** lp_gpio_out_data_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t lp_gpio_out_data_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_w1tc_reg_t; + +/** Type of out_enable register + * need des + */ +typedef union { + struct { + /** lp_gpio_enable : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t lp_gpio_enable:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_reg_t; + +/** Type of out_enable_w1ts register + * need des + */ +typedef union { + struct { + /** lp_gpio_enable_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t lp_gpio_enable_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_w1ts_reg_t; + +/** Type of out_enable_w1tc register + * need des + */ +typedef union { + struct { + /** lp_gpio_enable_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t lp_gpio_enable_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_w1tc_reg_t; + +/** Type of status register + * need des + */ +typedef union { + struct { + /** lp_gpio_status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t lp_gpio_status_interrupt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_reg_t; + +/** Type of status_w1ts register + * need des + */ +typedef union { + struct { + /** lp_gpio_status_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t lp_gpio_status_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_w1ts_reg_t; + +/** Type of status_w1tc register + * need des + */ +typedef union { + struct { + /** lp_gpio_status_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t lp_gpio_status_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_w1tc_reg_t; + +/** Type of in register + * need des + */ +typedef union { + struct { + /** lp_gpio_in_data_next : RO; bitpos: [7:0]; default: 0; + * need des + */ + uint32_t lp_gpio_in_data_next:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_in_reg_t; + +/** Type of pin n register + * need des + */ +typedef union { + struct { + /** lp_gpio_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio_sync_bypass:2; + /** lp_gpio_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio_pad_driver:1; + /** lp_gpio_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio_int_type:3; + /** lp_gpio_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio_wakeup_enable:1; + /** lp_gpio_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin_reg_t; + +/** Type of gpio n register + * need des + */ +typedef union { + struct { + /** lp_gpio_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio_mcu_oe:1; + /** lp_gpio_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio_slp_sel:1; + /** lp_gpio_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio_mcu_wpd:1; + /** lp_gpio_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio_mcu_wpu:1; + /** lp_gpio_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio_mcu_ie:1; + /** lp_gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio_mcu_drv:2; + /** lp_gpio_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio_fun_wpd:1; + /** lp_gpio_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio_fun_wpu:1; + /** lp_gpio_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio_fun_ie:1; + /** lp_gpio_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio_fun_drv:2; + /** lp_gpio_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio_reg_t; + +/** Type of gpio1 register + * need des + */ +typedef union { + struct { + /** lp_gpio1_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_oe:1; + /** lp_gpio1_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio1_slp_sel:1; + /** lp_gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_wpd:1; + /** lp_gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_wpu:1; + /** lp_gpio1_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_ie:1; + /** lp_gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_drv:2; + /** lp_gpio1_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_wpd:1; + /** lp_gpio1_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_wpu:1; + /** lp_gpio1_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_ie:1; + /** lp_gpio1_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_drv:2; + /** lp_gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio1_reg_t; + +/** Type of gpio2 register + * need des + */ +typedef union { + struct { + /** lp_gpio2_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_oe:1; + /** lp_gpio2_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio2_slp_sel:1; + /** lp_gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_wpd:1; + /** lp_gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_wpu:1; + /** lp_gpio2_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_ie:1; + /** lp_gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_drv:2; + /** lp_gpio2_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_wpd:1; + /** lp_gpio2_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_wpu:1; + /** lp_gpio2_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_ie:1; + /** lp_gpio2_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_drv:2; + /** lp_gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio2_reg_t; + +/** Type of gpio3 register + * need des + */ +typedef union { + struct { + /** lp_gpio3_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_oe:1; + /** lp_gpio3_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio3_slp_sel:1; + /** lp_gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_wpd:1; + /** lp_gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_wpu:1; + /** lp_gpio3_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_ie:1; + /** lp_gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_drv:2; + /** lp_gpio3_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_wpd:1; + /** lp_gpio3_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_wpu:1; + /** lp_gpio3_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_ie:1; + /** lp_gpio3_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_drv:2; + /** lp_gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio3_reg_t; + +/** Type of gpio4 register + * need des + */ +typedef union { + struct { + /** lp_gpio4_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_oe:1; + /** lp_gpio4_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio4_slp_sel:1; + /** lp_gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_wpd:1; + /** lp_gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_wpu:1; + /** lp_gpio4_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_ie:1; + /** lp_gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_drv:2; + /** lp_gpio4_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_wpd:1; + /** lp_gpio4_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_wpu:1; + /** lp_gpio4_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_ie:1; + /** lp_gpio4_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_drv:2; + /** lp_gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio4_reg_t; + +/** Type of gpio5 register + * need des + */ +typedef union { + struct { + /** lp_gpio5_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_oe:1; + /** lp_gpio5_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio5_slp_sel:1; + /** lp_gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_wpd:1; + /** lp_gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_wpu:1; + /** lp_gpio5_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_ie:1; + /** lp_gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_drv:2; + /** lp_gpio5_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_wpd:1; + /** lp_gpio5_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_wpu:1; + /** lp_gpio5_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_ie:1; + /** lp_gpio5_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_drv:2; + /** lp_gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio5_reg_t; + +/** Type of gpio6 register + * need des + */ +typedef union { + struct { + /** lp_gpio6_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_oe:1; + /** lp_gpio6_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio6_slp_sel:1; + /** lp_gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_wpd:1; + /** lp_gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_wpu:1; + /** lp_gpio6_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_ie:1; + /** lp_gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_drv:2; + /** lp_gpio6_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_wpd:1; + /** lp_gpio6_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_wpu:1; + /** lp_gpio6_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_ie:1; + /** lp_gpio6_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_drv:2; + /** lp_gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio6_reg_t; + +/** Type of gpio7 register + * need des + */ +typedef union { + struct { + /** lp_gpio7_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_oe:1; + /** lp_gpio7_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio7_slp_sel:1; + /** lp_gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_wpd:1; + /** lp_gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_wpu:1; + /** lp_gpio7_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_ie:1; + /** lp_gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_drv:2; + /** lp_gpio7_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_wpd:1; + /** lp_gpio7_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_wpu:1; + /** lp_gpio7_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_ie:1; + /** lp_gpio7_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_drv:2; + /** lp_gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio7_reg_t; + +/** Type of status_interrupt register + * need des + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [7:0]; default: 0; + * need des + */ + uint32_t status_interrupt_next:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_interrupt_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t lp_debug_sel0:7; + /** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t lp_debug_sel1:7; + /** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t lp_debug_sel2:7; + /** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t lp_debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_io_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t lp_debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_io_debug_sel1_reg_t; + +/** Type of lpi2c register + * need des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1; + * need des + */ + uint32_t lp_i2c_sda_ie:1; + /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1; + * need des + */ + uint32_t lp_i2c_scl_ie:1; + }; + uint32_t val; +} lp_io_lpi2c_reg_t; + +/** Type of date register + * need des + */ +typedef union { + struct { + /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032; + * need des + */ + uint32_t lp_io_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_io_date_reg_t; + + +typedef struct lp_io_dev_t { + volatile lp_io_out_data_reg_t out_data; + volatile lp_io_out_data_w1ts_reg_t out_data_w1ts; + volatile lp_io_out_data_w1tc_reg_t out_data_w1tc; + volatile lp_io_out_enable_reg_t out_enable; + volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts; + volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc; + volatile lp_io_status_reg_t status; + volatile lp_io_status_w1ts_reg_t status_w1ts; + volatile lp_io_status_w1tc_reg_t status_w1tc; + volatile lp_io_in_reg_t in; + volatile lp_io_pin_reg_t pin[8]; + volatile lp_io_gpio_reg_t gpio[8]; + volatile lp_io_status_interrupt_reg_t status_interrupt; + volatile lp_io_debug_sel0_reg_t debug_sel0; + volatile lp_io_debug_sel1_reg_t debug_sel1; + volatile lp_io_lpi2c_reg_t lpi2c; + uint32_t reserved_078[225]; + volatile lp_io_date_reg_t date; +} lp_io_dev_t; + +extern lp_io_dev_t LP_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_tee_reg.h b/components/soc/esp32c5/include/soc/lp_tee_reg.h new file mode 100644 index 00000000000..872bfbbfe1c --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_tee_reg.h @@ -0,0 +1,72 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) +/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define LP_TEE_M0_MODE 0x00000003U +#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) +#define LP_TEE_M0_MODE_V 0x00000003U +#define LP_TEE_M0_MODE_S 0 +/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define LP_TEE_M0_LOCK (BIT(2)) +#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S) +#define LP_TEE_M0_LOCK_V 0x00000001U +#define LP_TEE_M0_LOCK_S 2 + +/** LP_TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4) +/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_TEE_CLK_EN (BIT(0)) +#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) +#define LP_TEE_CLK_EN_V 0x00000001U +#define LP_TEE_CLK_EN_S 0 + +/** LP_TEE_FORCE_ACC_HP_REG register + * need_des + */ +#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) +/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) +#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) +#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U +#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 + +/** LP_TEE_DATE_REG register + * Version register + */ +#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) +/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ +#define LP_TEE_DATE_REG 0x0FFFFFFFU +#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S) +#define LP_TEE_DATE_REG_V 0x0FFFFFFFU +#define LP_TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_tee_struct.h b/components/soc/esp32c5/include/soc/lp_tee_struct.h new file mode 100644 index 00000000000..7951c479f25 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_tee_struct.h @@ -0,0 +1,99 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 3; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + /** m0_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t m0_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_tee_m0_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_clock_gate_reg_t; + + +/** Group: configure_register */ +/** Type of force_acc_hp register + * need_des + */ +typedef union { + struct { + /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_acc_hpmem_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_force_acc_hp_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_tee_date_reg_t; + + +typedef struct lp_tee_dev_t { + volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile lp_tee_clock_gate_reg_t clock_gate; + uint32_t reserved_008[34]; + volatile lp_tee_force_acc_hp_reg_t force_acc_hp; + uint32_t reserved_094[26]; + volatile lp_tee_date_reg_t date; +} lp_tee_dev_t; + +extern lp_tee_dev_t LP_TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_timer_reg.h b/components/soc/esp32c5/include/soc/lp_timer_reg.h new file mode 100644 index 00000000000..7628cbf7e0a --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_timer_reg.h @@ -0,0 +1,342 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_TAR1_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** LP_TIMER_TAR1_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_LP_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** LP_TIMER_LP_INT_ST_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** LP_TIMER_LP_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** LP_TIMER_LP_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/include/soc/lp_timer_struct.h new file mode 100644 index 00000000000..2af34d6a37a --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_timer_struct.h @@ -0,0 +1,335 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of tar_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low:32; + }; + uint32_t val; +} lp_timer_tar_low_reg_t; + +/** Type of tar_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high:16; + uint32_t reserved_16:15; + /** main_timer_tar_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en:1; + }; + uint32_t val; +} lp_timer_tar_high_reg_t; + +/** Type of update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** main_timer_update : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t main_timer_update:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of main_buf_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf_low:32; + }; + uint32_t val; +} lp_timer_main_buf_low_reg_t; + +/** Type of main_buf_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf_high_reg_t; + +/** Type of main_buf1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of main_buf1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_raw:1; + /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_st:1; + /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_ena:1; + /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_clr:1; + /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + +typedef struct { + volatile lp_timer_tar_low_reg_t lo; + volatile lp_timer_tar_high_reg_t hi; +} lp_timer_target_reg_t; + +typedef struct { + volatile lp_timer_main_buf_low_reg_t lo; + volatile lp_timer_main_buf_high_reg_t hi; +} lp_timer_counter_reg_t; + +typedef struct lp_timer_dev_t { + volatile lp_timer_target_reg_t target[2]; + volatile lp_timer_update_reg_t update; + volatile lp_timer_counter_reg_t counter[2]; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_uart_reg.h b/components/soc/esp32c5/include/soc/lp_uart_reg.h new file mode 100644 index 00000000000..a23d7aeb7ba --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_uart_reg.h @@ -0,0 +1,1381 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_UART_FIFO_REG register + * FIFO data register + */ +#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0) +/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define LP_UART_RXFIFO_RD_BYTE 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_M (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S) +#define LP_UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_S 0 + +/** LP_UART_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4) +/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define LP_UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_RAW_M (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S) +#define LP_UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_RAW_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define LP_UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_M (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define LP_UART_PARITY_ERR_INT_RAW (BIT(2)) +#define LP_UART_PARITY_ERR_INT_RAW_M (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S) +#define LP_UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_RAW_S 2 +/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define LP_UART_FRM_ERR_INT_RAW (BIT(3)) +#define LP_UART_FRM_ERR_INT_RAW_M (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S) +#define LP_UART_FRM_ERR_INT_RAW_V 0x00000001U +#define LP_UART_FRM_ERR_INT_RAW_S 3 +/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define LP_UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_RAW_M (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S) +#define LP_UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_RAW_S 4 +/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define LP_UART_DSR_CHG_INT_RAW (BIT(5)) +#define LP_UART_DSR_CHG_INT_RAW_M (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S) +#define LP_UART_DSR_CHG_INT_RAW_V 0x00000001U +#define LP_UART_DSR_CHG_INT_RAW_S 5 +/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define LP_UART_CTS_CHG_INT_RAW (BIT(6)) +#define LP_UART_CTS_CHG_INT_RAW_M (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S) +#define LP_UART_CTS_CHG_INT_RAW_V 0x00000001U +#define LP_UART_CTS_CHG_INT_RAW_S 6 +/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define LP_UART_BRK_DET_INT_RAW (BIT(7)) +#define LP_UART_BRK_DET_INT_RAW_M (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S) +#define LP_UART_BRK_DET_INT_RAW_V 0x00000001U +#define LP_UART_BRK_DET_INT_RAW_S 7 +/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define LP_UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_RAW_M (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S) +#define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 +/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XON_INT_RAW (BIT(9)) +#define LP_UART_SW_XON_INT_RAW_M (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S) +#define LP_UART_SW_XON_INT_RAW_V 0x00000001U +#define LP_UART_SW_XON_INT_RAW_S 9 +/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XOFF_INT_RAW (BIT(10)) +#define LP_UART_SW_XOFF_INT_RAW_M (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S) +#define LP_UART_SW_XOFF_INT_RAW_V 0x00000001U +#define LP_UART_SW_XOFF_INT_RAW_S 10 +/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define LP_UART_GLITCH_DET_INT_RAW (BIT(11)) +#define LP_UART_GLITCH_DET_INT_RAW_M (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S) +#define LP_UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_RAW_S 11 +/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define LP_UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_RAW_M (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_RAW_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define LP_UART_TX_DONE_INT_RAW (BIT(14)) +#define LP_UART_TX_DONE_INT_RAW_M (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S) +#define LP_UART_TX_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_DONE_INT_RAW_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define LP_UART_WAKEUP_INT_RAW (BIT(19)) +#define LP_UART_WAKEUP_INT_RAW_M (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S) +#define LP_UART_WAKEUP_INT_RAW_V 0x00000001U +#define LP_UART_WAKEUP_INT_RAW_S 19 + +/** LP_UART_INT_ST_REG register + * Masked interrupt status + */ +#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8) +/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ST_M (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S) +#define LP_UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ST_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ST_M (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S) +#define LP_UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ST_S 1 +/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define LP_UART_PARITY_ERR_INT_ST (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ST_M (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S) +#define LP_UART_PARITY_ERR_INT_ST_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ST_S 2 +/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define LP_UART_FRM_ERR_INT_ST (BIT(3)) +#define LP_UART_FRM_ERR_INT_ST_M (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S) +#define LP_UART_FRM_ERR_INT_ST_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ST_S 3 +/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ST_M (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S) +#define LP_UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ST_S 4 +/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define LP_UART_DSR_CHG_INT_ST (BIT(5)) +#define LP_UART_DSR_CHG_INT_ST_M (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S) +#define LP_UART_DSR_CHG_INT_ST_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ST_S 5 +/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define LP_UART_CTS_CHG_INT_ST (BIT(6)) +#define LP_UART_CTS_CHG_INT_ST_M (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S) +#define LP_UART_CTS_CHG_INT_ST_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ST_S 6 +/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define LP_UART_BRK_DET_INT_ST (BIT(7)) +#define LP_UART_BRK_DET_INT_ST_M (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S) +#define LP_UART_BRK_DET_INT_ST_V 0x00000001U +#define LP_UART_BRK_DET_INT_ST_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ST_M (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S) +#define LP_UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ST_S 8 +/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define LP_UART_SW_XON_INT_ST (BIT(9)) +#define LP_UART_SW_XON_INT_ST_M (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S) +#define LP_UART_SW_XON_INT_ST_V 0x00000001U +#define LP_UART_SW_XON_INT_ST_S 9 +/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define LP_UART_SW_XOFF_INT_ST (BIT(10)) +#define LP_UART_SW_XOFF_INT_ST_M (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S) +#define LP_UART_SW_XOFF_INT_ST_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ST_S 10 +/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define LP_UART_GLITCH_DET_INT_ST (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ST_M (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S) +#define LP_UART_GLITCH_DET_INT_ST_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ST_S 11 +/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define LP_UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ST_M (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S) +#define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ST_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define LP_UART_TX_DONE_INT_ST (BIT(14)) +#define LP_UART_TX_DONE_INT_ST_M (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S) +#define LP_UART_TX_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_DONE_INT_ST_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define LP_UART_WAKEUP_INT_ST (BIT(19)) +#define LP_UART_WAKEUP_INT_ST_M (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S) +#define LP_UART_WAKEUP_INT_ST_V 0x00000001U +#define LP_UART_WAKEUP_INT_ST_S 19 + +/** LP_UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc) +/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define LP_UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ENA_M (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S) +#define LP_UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ENA_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_M (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define LP_UART_PARITY_ERR_INT_ENA (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ENA_M (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S) +#define LP_UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ENA_S 2 +/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define LP_UART_FRM_ERR_INT_ENA (BIT(3)) +#define LP_UART_FRM_ERR_INT_ENA_M (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S) +#define LP_UART_FRM_ERR_INT_ENA_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ENA_S 3 +/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define LP_UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ENA_M (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S) +#define LP_UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ENA_S 4 +/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define LP_UART_DSR_CHG_INT_ENA (BIT(5)) +#define LP_UART_DSR_CHG_INT_ENA_M (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S) +#define LP_UART_DSR_CHG_INT_ENA_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ENA_S 5 +/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define LP_UART_CTS_CHG_INT_ENA (BIT(6)) +#define LP_UART_CTS_CHG_INT_ENA_M (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S) +#define LP_UART_CTS_CHG_INT_ENA_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ENA_S 6 +/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define LP_UART_BRK_DET_INT_ENA (BIT(7)) +#define LP_UART_BRK_DET_INT_ENA_M (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S) +#define LP_UART_BRK_DET_INT_ENA_V 0x00000001U +#define LP_UART_BRK_DET_INT_ENA_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define LP_UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ENA_M (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S) +#define LP_UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ENA_S 8 +/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define LP_UART_SW_XON_INT_ENA (BIT(9)) +#define LP_UART_SW_XON_INT_ENA_M (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S) +#define LP_UART_SW_XON_INT_ENA_V 0x00000001U +#define LP_UART_SW_XON_INT_ENA_S 9 +/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define LP_UART_SW_XOFF_INT_ENA (BIT(10)) +#define LP_UART_SW_XOFF_INT_ENA_M (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S) +#define LP_UART_SW_XOFF_INT_ENA_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ENA_S 10 +/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define LP_UART_GLITCH_DET_INT_ENA (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ENA_M (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S) +#define LP_UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ENA_S 11 +/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define LP_UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ENA_M (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ENA_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define LP_UART_TX_DONE_INT_ENA (BIT(14)) +#define LP_UART_TX_DONE_INT_ENA_M (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S) +#define LP_UART_TX_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_DONE_INT_ENA_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define LP_UART_WAKEUP_INT_ENA (BIT(19)) +#define LP_UART_WAKEUP_INT_ENA_M (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S) +#define LP_UART_WAKEUP_INT_ENA_V 0x00000001U +#define LP_UART_WAKEUP_INT_ENA_S 19 + +/** LP_UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10) +/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define LP_UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_CLR_M (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S) +#define LP_UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_CLR_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define LP_UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_M (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define LP_UART_PARITY_ERR_INT_CLR (BIT(2)) +#define LP_UART_PARITY_ERR_INT_CLR_M (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S) +#define LP_UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_CLR_S 2 +/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define LP_UART_FRM_ERR_INT_CLR (BIT(3)) +#define LP_UART_FRM_ERR_INT_CLR_M (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S) +#define LP_UART_FRM_ERR_INT_CLR_V 0x00000001U +#define LP_UART_FRM_ERR_INT_CLR_S 3 +/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define LP_UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_CLR_M (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S) +#define LP_UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_CLR_S 4 +/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define LP_UART_DSR_CHG_INT_CLR (BIT(5)) +#define LP_UART_DSR_CHG_INT_CLR_M (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S) +#define LP_UART_DSR_CHG_INT_CLR_V 0x00000001U +#define LP_UART_DSR_CHG_INT_CLR_S 5 +/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define LP_UART_CTS_CHG_INT_CLR (BIT(6)) +#define LP_UART_CTS_CHG_INT_CLR_M (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S) +#define LP_UART_CTS_CHG_INT_CLR_V 0x00000001U +#define LP_UART_CTS_CHG_INT_CLR_S 6 +/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define LP_UART_BRK_DET_INT_CLR (BIT(7)) +#define LP_UART_BRK_DET_INT_CLR_M (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S) +#define LP_UART_BRK_DET_INT_CLR_V 0x00000001U +#define LP_UART_BRK_DET_INT_CLR_S 7 +/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define LP_UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_CLR_M (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S) +#define LP_UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_CLR_S 8 +/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define LP_UART_SW_XON_INT_CLR (BIT(9)) +#define LP_UART_SW_XON_INT_CLR_M (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S) +#define LP_UART_SW_XON_INT_CLR_V 0x00000001U +#define LP_UART_SW_XON_INT_CLR_S 9 +/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define LP_UART_SW_XOFF_INT_CLR (BIT(10)) +#define LP_UART_SW_XOFF_INT_CLR_M (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S) +#define LP_UART_SW_XOFF_INT_CLR_V 0x00000001U +#define LP_UART_SW_XOFF_INT_CLR_S 10 +/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define LP_UART_GLITCH_DET_INT_CLR (BIT(11)) +#define LP_UART_GLITCH_DET_INT_CLR_M (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S) +#define LP_UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_CLR_S 11 +/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define LP_UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_CLR_M (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_CLR_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define LP_UART_TX_DONE_INT_CLR (BIT(14)) +#define LP_UART_TX_DONE_INT_CLR_M (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S) +#define LP_UART_TX_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_DONE_INT_CLR_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define LP_UART_WAKEUP_INT_CLR (BIT(19)) +#define LP_UART_WAKEUP_INT_CLR_M (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S) +#define LP_UART_WAKEUP_INT_CLR_V 0x00000001U +#define LP_UART_WAKEUP_INT_CLR_S 19 + +/** LP_UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14) +/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define LP_UART_CLKDIV 0x00000FFFU +#define LP_UART_CLKDIV_M (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S) +#define LP_UART_CLKDIV_V 0x00000FFFU +#define LP_UART_CLKDIV_S 0 +/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define LP_UART_CLKDIV_FRAG 0x0000000FU +#define LP_UART_CLKDIV_FRAG_M (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S) +#define LP_UART_CLKDIV_FRAG_V 0x0000000FU +#define LP_UART_CLKDIV_FRAG_S 20 + +/** LP_UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18) +/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define LP_UART_GLITCH_FILT 0x000000FFU +#define LP_UART_GLITCH_FILT_M (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S) +#define LP_UART_GLITCH_FILT_V 0x000000FFU +#define LP_UART_GLITCH_FILT_S 0 +/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define LP_UART_GLITCH_FILT_EN (BIT(8)) +#define LP_UART_GLITCH_FILT_EN_M (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S) +#define LP_UART_GLITCH_FILT_EN_V 0x00000001U +#define LP_UART_GLITCH_FILT_EN_S 8 + +/** LP_UART_STATUS_REG register + * UART status register + */ +#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c) +/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define LP_UART_RXFIFO_CNT 0x0000001FU +#define LP_UART_RXFIFO_CNT_M (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S) +#define LP_UART_RXFIFO_CNT_V 0x0000001FU +#define LP_UART_RXFIFO_CNT_S 3 +/** LP_UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define LP_UART_DSRN (BIT(13)) +#define LP_UART_DSRN_M (LP_UART_DSRN_V << LP_UART_DSRN_S) +#define LP_UART_DSRN_V 0x00000001U +#define LP_UART_DSRN_S 13 +/** LP_UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define LP_UART_CTSN (BIT(14)) +#define LP_UART_CTSN_M (LP_UART_CTSN_V << LP_UART_CTSN_S) +#define LP_UART_CTSN_V 0x00000001U +#define LP_UART_CTSN_S 14 +/** LP_UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define LP_UART_RXD (BIT(15)) +#define LP_UART_RXD_M (LP_UART_RXD_V << LP_UART_RXD_S) +#define LP_UART_RXD_V 0x00000001U +#define LP_UART_RXD_S 15 +/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define LP_UART_TXFIFO_CNT 0x0000001FU +#define LP_UART_TXFIFO_CNT_M (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S) +#define LP_UART_TXFIFO_CNT_V 0x0000001FU +#define LP_UART_TXFIFO_CNT_S 19 +/** LP_UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define LP_UART_DTRN (BIT(29)) +#define LP_UART_DTRN_M (LP_UART_DTRN_V << LP_UART_DTRN_S) +#define LP_UART_DTRN_V 0x00000001U +#define LP_UART_DTRN_S 29 +/** LP_UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define LP_UART_RTSN (BIT(30)) +#define LP_UART_RTSN_M (LP_UART_RTSN_V << LP_UART_RTSN_S) +#define LP_UART_RTSN_V 0x00000001U +#define LP_UART_RTSN_S 30 +/** LP_UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define LP_UART_TXD (BIT(31)) +#define LP_UART_TXD_M (LP_UART_TXD_V << LP_UART_TXD_S) +#define LP_UART_TXD_V 0x00000001U +#define LP_UART_TXD_S 31 + +/** LP_UART_CONF0_SYNC_REG register + * Configuration register 0 + */ +#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20) +/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define LP_UART_PARITY (BIT(0)) +#define LP_UART_PARITY_M (LP_UART_PARITY_V << LP_UART_PARITY_S) +#define LP_UART_PARITY_V 0x00000001U +#define LP_UART_PARITY_S 0 +/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define LP_UART_PARITY_EN (BIT(1)) +#define LP_UART_PARITY_EN_M (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S) +#define LP_UART_PARITY_EN_V 0x00000001U +#define LP_UART_PARITY_EN_S 1 +/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define LP_UART_BIT_NUM 0x00000003U +#define LP_UART_BIT_NUM_M (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S) +#define LP_UART_BIT_NUM_V 0x00000003U +#define LP_UART_BIT_NUM_S 2 +/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define LP_UART_STOP_BIT_NUM 0x00000003U +#define LP_UART_STOP_BIT_NUM_M (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S) +#define LP_UART_STOP_BIT_NUM_V 0x00000003U +#define LP_UART_STOP_BIT_NUM_S 4 +/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define LP_UART_TXD_BRK (BIT(6)) +#define LP_UART_TXD_BRK_M (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S) +#define LP_UART_TXD_BRK_V 0x00000001U +#define LP_UART_TXD_BRK_S 6 +/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define LP_UART_LOOPBACK (BIT(12)) +#define LP_UART_LOOPBACK_M (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S) +#define LP_UART_LOOPBACK_V 0x00000001U +#define LP_UART_LOOPBACK_S 12 +/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define LP_UART_TX_FLOW_EN (BIT(13)) +#define LP_UART_TX_FLOW_EN_M (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S) +#define LP_UART_TX_FLOW_EN_V 0x00000001U +#define LP_UART_TX_FLOW_EN_S 13 +/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define LP_UART_RXD_INV (BIT(15)) +#define LP_UART_RXD_INV_M (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S) +#define LP_UART_RXD_INV_V 0x00000001U +#define LP_UART_RXD_INV_S 15 +/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define LP_UART_TXD_INV (BIT(16)) +#define LP_UART_TXD_INV_M (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S) +#define LP_UART_TXD_INV_V 0x00000001U +#define LP_UART_TXD_INV_S 16 +/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define LP_UART_DIS_RX_DAT_OVF (BIT(17)) +#define LP_UART_DIS_RX_DAT_OVF_M (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S) +#define LP_UART_DIS_RX_DAT_OVF_V 0x00000001U +#define LP_UART_DIS_RX_DAT_OVF_S 17 +/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define LP_UART_ERR_WR_MASK (BIT(18)) +#define LP_UART_ERR_WR_MASK_M (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S) +#define LP_UART_ERR_WR_MASK_V 0x00000001U +#define LP_UART_ERR_WR_MASK_S 18 +/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define LP_UART_MEM_CLK_EN (BIT(20)) +#define LP_UART_MEM_CLK_EN_M (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S) +#define LP_UART_MEM_CLK_EN_V 0x00000001U +#define LP_UART_MEM_CLK_EN_S 20 +/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define LP_UART_SW_RTS (BIT(21)) +#define LP_UART_SW_RTS_M (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S) +#define LP_UART_SW_RTS_V 0x00000001U +#define LP_UART_SW_RTS_S 21 +/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define LP_UART_RXFIFO_RST (BIT(22)) +#define LP_UART_RXFIFO_RST_M (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S) +#define LP_UART_RXFIFO_RST_V 0x00000001U +#define LP_UART_RXFIFO_RST_S 22 +/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define LP_UART_TXFIFO_RST (BIT(23)) +#define LP_UART_TXFIFO_RST_M (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S) +#define LP_UART_TXFIFO_RST_V 0x00000001U +#define LP_UART_TXFIFO_RST_S 23 + +/** LP_UART_CONF1_REG register + * Configuration register 1 + */ +#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24) +/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define LP_UART_RXFIFO_FULL_THRHD 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_M (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S) +#define LP_UART_RXFIFO_FULL_THRHD_V 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_S 3 +/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define LP_UART_TXFIFO_EMPTY_THRHD 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_M (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S) +#define LP_UART_TXFIFO_EMPTY_THRHD_V 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_S 11 +/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define LP_UART_CTS_INV (BIT(16)) +#define LP_UART_CTS_INV_M (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S) +#define LP_UART_CTS_INV_V 0x00000001U +#define LP_UART_CTS_INV_S 16 +/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define LP_UART_DSR_INV (BIT(17)) +#define LP_UART_DSR_INV_M (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S) +#define LP_UART_DSR_INV_V 0x00000001U +#define LP_UART_DSR_INV_S 17 +/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define LP_UART_RTS_INV (BIT(18)) +#define LP_UART_RTS_INV_M (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S) +#define LP_UART_RTS_INV_V 0x00000001U +#define LP_UART_RTS_INV_S 18 +/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define LP_UART_DTR_INV (BIT(19)) +#define LP_UART_DTR_INV_M (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S) +#define LP_UART_DTR_INV_V 0x00000001U +#define LP_UART_DTR_INV_S 19 +/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define LP_UART_SW_DTR (BIT(20)) +#define LP_UART_SW_DTR_M (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S) +#define LP_UART_SW_DTR_V 0x00000001U +#define LP_UART_SW_DTR_S 20 +/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define LP_UART_CLK_EN (BIT(21)) +#define LP_UART_CLK_EN_M (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S) +#define LP_UART_CLK_EN_V 0x00000001U +#define LP_UART_CLK_EN_S 21 + +/** LP_UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c) +/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define LP_UART_RX_FLOW_THRHD 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_M (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S) +#define LP_UART_RX_FLOW_THRHD_V 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_S 3 +/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define LP_UART_RX_FLOW_EN (BIT(8)) +#define LP_UART_RX_FLOW_EN_M (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S) +#define LP_UART_RX_FLOW_EN_V 0x00000001U +#define LP_UART_RX_FLOW_EN_S 8 + +/** LP_UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30) +/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define LP_UART_WK_CHAR1 0x000000FFU +#define LP_UART_WK_CHAR1_M (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S) +#define LP_UART_WK_CHAR1_V 0x000000FFU +#define LP_UART_WK_CHAR1_S 0 +/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define LP_UART_WK_CHAR2 0x000000FFU +#define LP_UART_WK_CHAR2_M (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S) +#define LP_UART_WK_CHAR2_V 0x000000FFU +#define LP_UART_WK_CHAR2_S 8 +/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define LP_UART_WK_CHAR3 0x000000FFU +#define LP_UART_WK_CHAR3_M (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S) +#define LP_UART_WK_CHAR3_V 0x000000FFU +#define LP_UART_WK_CHAR3_S 16 +/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define LP_UART_WK_CHAR4 0x000000FFU +#define LP_UART_WK_CHAR4_M (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S) +#define LP_UART_WK_CHAR4_V 0x000000FFU +#define LP_UART_WK_CHAR4_S 24 + +/** LP_UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34) +/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define LP_UART_WK_CHAR0 0x000000FFU +#define LP_UART_WK_CHAR0_M (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S) +#define LP_UART_WK_CHAR0_V 0x000000FFU +#define LP_UART_WK_CHAR0_S 0 + +/** LP_UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38) +/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define LP_UART_ACTIVE_THRESHOLD 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_M (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S) +#define LP_UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_S 0 +/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define LP_UART_RX_WAKE_UP_THRHD 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_M (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S) +#define LP_UART_RX_WAKE_UP_THRHD_V 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_S 13 +/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define LP_UART_WK_CHAR_NUM 0x00000007U +#define LP_UART_WK_CHAR_NUM_M (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S) +#define LP_UART_WK_CHAR_NUM_V 0x00000007U +#define LP_UART_WK_CHAR_NUM_S 18 +/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define LP_UART_WK_CHAR_MASK 0x0000001FU +#define LP_UART_WK_CHAR_MASK_M (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S) +#define LP_UART_WK_CHAR_MASK_V 0x0000001FU +#define LP_UART_WK_CHAR_MASK_S 21 +/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define LP_UART_WK_MODE_SEL 0x00000003U +#define LP_UART_WK_MODE_SEL_M (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S) +#define LP_UART_WK_MODE_SEL_V 0x00000003U +#define LP_UART_WK_MODE_SEL_S 26 + +/** LP_UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c) +/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define LP_UART_XON_CHAR 0x000000FFU +#define LP_UART_XON_CHAR_M (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S) +#define LP_UART_XON_CHAR_V 0x000000FFU +#define LP_UART_XON_CHAR_S 0 +/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define LP_UART_XOFF_CHAR 0x000000FFU +#define LP_UART_XOFF_CHAR_M (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S) +#define LP_UART_XOFF_CHAR_V 0x000000FFU +#define LP_UART_XOFF_CHAR_S 8 +/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define LP_UART_XON_XOFF_STILL_SEND (BIT(16)) +#define LP_UART_XON_XOFF_STILL_SEND_M (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S) +#define LP_UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define LP_UART_XON_XOFF_STILL_SEND_S 16 +/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define LP_UART_SW_FLOW_CON_EN (BIT(17)) +#define LP_UART_SW_FLOW_CON_EN_M (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S) +#define LP_UART_SW_FLOW_CON_EN_V 0x00000001U +#define LP_UART_SW_FLOW_CON_EN_S 17 +/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define LP_UART_XONOFF_DEL (BIT(18)) +#define LP_UART_XONOFF_DEL_M (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S) +#define LP_UART_XONOFF_DEL_V 0x00000001U +#define LP_UART_XONOFF_DEL_S 18 +/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define LP_UART_FORCE_XON (BIT(19)) +#define LP_UART_FORCE_XON_M (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S) +#define LP_UART_FORCE_XON_V 0x00000001U +#define LP_UART_FORCE_XON_S 19 +/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define LP_UART_FORCE_XOFF (BIT(20)) +#define LP_UART_FORCE_XOFF_M (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S) +#define LP_UART_FORCE_XOFF_V 0x00000001U +#define LP_UART_FORCE_XOFF_S 20 +/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XON (BIT(21)) +#define LP_UART_SEND_XON_M (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S) +#define LP_UART_SEND_XON_V 0x00000001U +#define LP_UART_SEND_XON_S 21 +/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XOFF (BIT(22)) +#define LP_UART_SEND_XOFF_M (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S) +#define LP_UART_SEND_XOFF_V 0x00000001U +#define LP_UART_SEND_XOFF_S 22 + +/** LP_UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40) +/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define LP_UART_XON_THRESHOLD 0x0000001FU +#define LP_UART_XON_THRESHOLD_M (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S) +#define LP_UART_XON_THRESHOLD_V 0x0000001FU +#define LP_UART_XON_THRESHOLD_S 3 +/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define LP_UART_XOFF_THRESHOLD 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_M (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S) +#define LP_UART_XOFF_THRESHOLD_V 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_S 11 + +/** LP_UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44) +/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define LP_UART_TX_BRK_NUM 0x000000FFU +#define LP_UART_TX_BRK_NUM_M (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S) +#define LP_UART_TX_BRK_NUM_V 0x000000FFU +#define LP_UART_TX_BRK_NUM_S 0 + +/** LP_UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48) +/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define LP_UART_RX_IDLE_THRHD 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_M (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S) +#define LP_UART_RX_IDLE_THRHD_V 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_S 0 +/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define LP_UART_TX_IDLE_NUM 0x000003FFU +#define LP_UART_TX_IDLE_NUM_M (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S) +#define LP_UART_TX_IDLE_NUM_V 0x000003FFU +#define LP_UART_TX_IDLE_NUM_S 10 + +/** LP_UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c) +/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL0_EN (BIT(1)) +#define LP_UART_DL0_EN_M (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S) +#define LP_UART_DL0_EN_V 0x00000001U +#define LP_UART_DL0_EN_S 1 +/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL1_EN (BIT(2)) +#define LP_UART_DL1_EN_M (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S) +#define LP_UART_DL1_EN_V 0x00000001U +#define LP_UART_DL1_EN_S 2 + +/** LP_UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50) +/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define LP_UART_PRE_IDLE_NUM 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_M (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S) +#define LP_UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54) +/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define LP_UART_POST_IDLE_NUM 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_M (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S) +#define LP_UART_POST_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58) +/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define LP_UART_RX_GAP_TOUT 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_M (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S) +#define LP_UART_RX_GAP_TOUT_V 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_S 0 + +/** LP_UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c) +/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR 0x000000FFU +#define LP_UART_AT_CMD_CHAR_M (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S) +#define LP_UART_AT_CMD_CHAR_V 0x000000FFU +#define LP_UART_AT_CMD_CHAR_S 0 +/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define LP_UART_CHAR_NUM 0x000000FFU +#define LP_UART_CHAR_NUM_M (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S) +#define LP_UART_CHAR_NUM_V 0x000000FFU +#define LP_UART_CHAR_NUM_S 8 + +/** LP_UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60) +/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define LP_UART_MEM_FORCE_PD (BIT(25)) +#define LP_UART_MEM_FORCE_PD_M (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S) +#define LP_UART_MEM_FORCE_PD_V 0x00000001U +#define LP_UART_MEM_FORCE_PD_S 25 +/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define LP_UART_MEM_FORCE_PU (BIT(26)) +#define LP_UART_MEM_FORCE_PU_M (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S) +#define LP_UART_MEM_FORCE_PU_V 0x00000001U +#define LP_UART_MEM_FORCE_PU_S 26 + +/** LP_UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) +/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define LP_UART_RX_TOUT_EN (BIT(0)) +#define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) +#define LP_UART_RX_TOUT_EN_V 0x00000001U +#define LP_UART_RX_TOUT_EN_S 0 +/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define LP_UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define LP_UART_RX_TOUT_FLOW_DIS_M (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S) +#define LP_UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define LP_UART_RX_TOUT_FLOW_DIS_S 1 +/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define LP_UART_RX_TOUT_THRHD 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_M (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S) +#define LP_UART_RX_TOUT_THRHD_V 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_S 2 + +/** LP_UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68) +/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_WADDR 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_M (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S) +#define LP_UART_TX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_S 3 +/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_RADDR 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_M (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S) +#define LP_UART_TX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_S 12 + +/** LP_UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c) +/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ +#define LP_UART_RX_SRAM_RADDR 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_M (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S) +#define LP_UART_RX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_S 3 +/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ +#define LP_UART_RX_SRAM_WADDR 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_M (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S) +#define LP_UART_RX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_S 12 + +/** LP_UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70) +/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define LP_UART_ST_URX_OUT 0x0000000FU +#define LP_UART_ST_URX_OUT_M (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S) +#define LP_UART_ST_URX_OUT_V 0x0000000FU +#define LP_UART_ST_URX_OUT_S 0 +/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define LP_UART_ST_UTX_OUT 0x0000000FU +#define LP_UART_ST_UTX_OUT_M (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S) +#define LP_UART_ST_UTX_OUT_V 0x0000000FU +#define LP_UART_ST_UTX_OUT_S 4 + +/** LP_UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88) +/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_B 0x0000003FU +#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S) +#define LP_UART_SCLK_DIV_B_V 0x0000003FU +#define LP_UART_SCLK_DIV_B_S 0 +/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_A 0x0000003FU +#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S) +#define LP_UART_SCLK_DIV_A_V 0x0000003FU +#define LP_UART_SCLK_DIV_A_S 6 +/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_NUM 0x000000FFU +#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S) +#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU +#define LP_UART_SCLK_DIV_NUM_S 12 +/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ +#define LP_UART_SCLK_SEL 0x00000003U +#define LP_UART_SCLK_SEL_M (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S) +#define LP_UART_SCLK_SEL_V 0x00000003U +#define LP_UART_SCLK_SEL_S 20 +/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ +#define LP_UART_SCLK_EN (BIT(22)) +#define LP_UART_SCLK_EN_M (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S) +#define LP_UART_SCLK_EN_V 0x00000001U +#define LP_UART_SCLK_EN_S 22 +/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ +#define LP_UART_RST_CORE (BIT(23)) +#define LP_UART_RST_CORE_M (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S) +#define LP_UART_RST_CORE_V 0x00000001U +#define LP_UART_RST_CORE_S 23 +/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define LP_UART_TX_SCLK_EN (BIT(24)) +#define LP_UART_TX_SCLK_EN_M (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S) +#define LP_UART_TX_SCLK_EN_V 0x00000001U +#define LP_UART_TX_SCLK_EN_S 24 +/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define LP_UART_RX_SCLK_EN (BIT(25)) +#define LP_UART_RX_SCLK_EN_M (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S) +#define LP_UART_RX_SCLK_EN_V 0x00000001U +#define LP_UART_RX_SCLK_EN_S 25 +/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define LP_UART_TX_RST_CORE (BIT(26)) +#define LP_UART_TX_RST_CORE_M (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S) +#define LP_UART_TX_RST_CORE_V 0x00000001U +#define LP_UART_TX_RST_CORE_S 26 +/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define LP_UART_RX_RST_CORE (BIT(27)) +#define LP_UART_RX_RST_CORE_M (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S) +#define LP_UART_RX_RST_CORE_V 0x00000001U +#define LP_UART_RX_RST_CORE_S 27 + +/** LP_UART_DATE_REG register + * UART Version register + */ +#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c) +/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ +#define LP_UART_DATE 0xFFFFFFFFU +#define LP_UART_DATE_M (LP_UART_DATE_V << LP_UART_DATE_S) +#define LP_UART_DATE_V 0xFFFFFFFFU +#define LP_UART_DATE_S 0 + +/** LP_UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90) +/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_FULL (BIT(0)) +#define LP_UART_TX_AFIFO_FULL_M (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S) +#define LP_UART_TX_AFIFO_FULL_V 0x00000001U +#define LP_UART_TX_AFIFO_FULL_S 0 +/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_EMPTY (BIT(1)) +#define LP_UART_TX_AFIFO_EMPTY_M (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S) +#define LP_UART_TX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_TX_AFIFO_EMPTY_S 1 +/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_FULL (BIT(2)) +#define LP_UART_RX_AFIFO_FULL_M (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S) +#define LP_UART_RX_AFIFO_FULL_V 0x00000001U +#define LP_UART_RX_AFIFO_FULL_S 2 +/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_EMPTY (BIT(3)) +#define LP_UART_RX_AFIFO_EMPTY_M (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S) +#define LP_UART_RX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_RX_AFIFO_EMPTY_S 3 + +/** LP_UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98) +/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define LP_UART_REG_UPDATE (BIT(0)) +#define LP_UART_REG_UPDATE_M (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S) +#define LP_UART_REG_UPDATE_V 0x00000001U +#define LP_UART_REG_UPDATE_S 0 + +/** LP_UART_ID_REG register + * UART ID register + */ +#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c) +/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define LP_UART_ID 0xFFFFFFFFU +#define LP_UART_ID_M (LP_UART_ID_V << LP_UART_ID_S) +#define LP_UART_ID_V 0xFFFFFFFFU +#define LP_UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/include/soc/lp_uart_struct.h new file mode 100644 index 00000000000..7500b302af4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_uart_struct.h @@ -0,0 +1,1127 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} lp_uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * Configuration register 0 + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + uint32_t reserved_7:5; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + uint32_t reserved_14:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + uint32_t reserved_19:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:5; + uint32_t reserved_8:3; + /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:5; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:5; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} lp_uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + uint32_t reserved_10:3; + /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:5; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** xon_threshold : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:5; + uint32_t reserved_8:3; + /** xoff_threshold : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:5; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ + uint32_t sclk_div_b:6; + /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ + uint32_t sclk_div_a:6; + /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ + uint32_t sclk_div_num:8; + /** sclk_sel : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ + uint32_t sclk_sel:2; + /** sclk_en : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ + uint32_t sclk_en:1; + /** rst_core : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ + uint32_t rst_core:1; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + uint32_t reserved_16:3; + /** txfifo_cnt : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} lp_uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:5; + uint32_t reserved_8:4; + /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:5; + uint32_t reserved_8:4; + /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_char_sync_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} lp_uart_id_reg_t; + + +typedef struct lp_uart_dev_t { + volatile lp_uart_fifo_reg_t fifo; + volatile lp_uart_int_raw_reg_t int_raw; + volatile lp_uart_int_st_reg_t int_st; + volatile lp_uart_int_ena_reg_t int_ena; + volatile lp_uart_int_clr_reg_t int_clr; + volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync; + volatile lp_uart_rx_filt_reg_t rx_filt; + volatile lp_uart_status_reg_t status; + volatile lp_uart_conf0_sync_reg_t conf0_sync; + volatile lp_uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile lp_uart_sleep_conf0_reg_t sleep_conf0; + volatile lp_uart_sleep_conf1_reg_t sleep_conf1; + volatile lp_uart_sleep_conf2_reg_t sleep_conf2; + volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile lp_uart_swfc_conf1_reg_t swfc_conf1; + volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync; + volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile lp_uart_mem_conf_reg_t mem_conf; + volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync; + volatile lp_uart_mem_tx_status_reg_t mem_tx_status; + volatile lp_uart_mem_rx_status_reg_t mem_rx_status; + volatile lp_uart_fsm_status_reg_t fsm_status; + uint32_t reserved_074[5]; + volatile lp_uart_clk_conf_reg_t clk_conf; + volatile lp_uart_date_reg_t date; + volatile lp_uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile lp_uart_reg_update_reg_t reg_update; + volatile lp_uart_id_reg_t id; +} lp_uart_dev_t; + +extern lp_uart_dev_t LP_UART; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/include/soc/lp_wdt_reg.h new file mode 100644 index 00000000000..4f7a3353f30 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_wdt_reg.h @@ -0,0 +1,324 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/include/soc/lp_wdt_struct.h new file mode 100644 index 00000000000..4e0ee847bd7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_wdt_struct.h @@ -0,0 +1,310 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of config0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of config1 register + * need_des + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of config2 register + * need_des + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of config3 register + * need_des + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of config4 register + * need_des + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of swd_config register + * need_des + */ +typedef union { + struct { + /** swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t swd_reset_flag:1; + uint32_t reserved_1:17; + /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t swd_auto_feed_en:1; + /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t swd_rst_flag_clr:1; + /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t swd_signal_width:10; + /** swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t swd_disable:1; + /** swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of swd_wprotect register + * need_des + */ +typedef union { + struct { + /** swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_raw:1; + /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ + uint32_t lp_wdt_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct lp_wdt_dev_t { + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; + uint32_t reserved_034[242]; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lpperi_reg.h b/components/soc/esp32c5/include/soc/lpperi_reg.h new file mode 100644 index 00000000000..d3d5d79bc34 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lpperi_reg.h @@ -0,0 +1,317 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36720720; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lpperi_struct.h b/components/soc/esp32c5/include/soc/lpperi_struct.h new file mode 100644 index 00000000000..06e3e023ca7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lpperi_struct.h @@ -0,0 +1,289 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + uint32_t reserved_24:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + uint32_t reserved_10:14; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 36720720; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct lpperi_dev_t { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_rng_cfg_reg_t rng_cfg; + uint32_t reserved_028[245]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mcpwm_reg.h b/components/soc/esp32c5/include/soc/mcpwm_reg.h new file mode 100644 index 00000000000..2c5d5957a7b --- /dev/null +++ b/components/soc/esp32c5/include/soc/mcpwm_reg.h @@ -0,0 +1,4514 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU +#define MCPWM_CLK_PRESCALE_S 0 + +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer0, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer0 period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control register. + */ +#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer0.\\0: If PWM timer0 starts, then + * stops at TEZ\\1: If timer0 starts, then stops at TEP\\2: PWM timer0 starts and runs + * on\\3: Timer0 starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U +#define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer0.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 + +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER0_SYNCI_EN_S 0 +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer0 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer0 reload on sync event. + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer0's direction when timer0 mode is up-down mode.\\0: + * Increase\\1: Decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer0 counter value. + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer0 counter direction.\\0: Increment\\1: Decrement + */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_DIRECTION_S 16 + +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer1, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer1 period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control register. + */ +#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer1.\\0: If PWM timer1 starts, then + * stops at TEZ\\1: If timer1 starts, then stops at TEP\\2: PWM timer1 starts and runs + * on\\3: Timer1 starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U +#define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer1.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 + +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer1 reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER1_SYNCI_EN_S 0 +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer1 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer1 reload on sync event. + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer1's direction when timer1 mode is up-down mode.\\0: + * Increase\\1: Decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer1 counter value. + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer1 counter direction.\\0: Increment\\1: Decrement + */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_DIRECTION_S 16 + +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer2, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer2 period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control register. + */ +#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer2.\\0: If PWM timer2 starts, then + * stops at TEZ\\1: If timer2 starts, then stops at TEP\\2: PWM timer2 starts and runs + * on\\3: Timer2 starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U +#define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer2.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 + +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer2 reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER2_SYNCI_EN_S 0 +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer2 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer2 reload on sync event. + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer2's direction when timer2 mode is up-down mode.\\0: + * Increase\\1: Decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer2 counter value. + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer2 counter direction.\\0: Increment\\1: Decrement + */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_DIRECTION_S 16 + +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection register for PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 + +/** MCPWM_OPERATOR_TIMERSEL_REG register + * PWM operator's timer select register + */ +#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 + +/** MCPWM_GEN0_STMP_CFG_REG register + * Generator0 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c) +/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 0 time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_M (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S) +#define MCPWM_GEN0_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_S 0 +/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 0 time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_M (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S) +#define MCPWM_GEN0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_S 4 +/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_M (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S) +#define MCPWM_GEN0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_A_SHDW_FULL_S 8 +/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_M (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S) +#define MCPWM_GEN0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_B_SHDW_FULL_S 9 + +/** MCPWM_GEN0_TSTMP_A_REG register + * Generator0 time stamp A's shadow register + */ +#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40) +/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 0 time stamp A's shadow register. + */ +#define MCPWM_GEN0_A 0x0000FFFFU +#define MCPWM_GEN0_A_M (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S) +#define MCPWM_GEN0_A_V 0x0000FFFFU +#define MCPWM_GEN0_A_S 0 + +/** MCPWM_GEN0_TSTMP_B_REG register + * Generator0 time stamp B's shadow register + */ +#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44) +/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 0 time stamp B's shadow register. + */ +#define MCPWM_GEN0_B 0x0000FFFFU +#define MCPWM_GEN0_B_M (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S) +#define MCPWM_GEN0_B_V 0x0000FFFFU +#define MCPWM_GEN0_B_S 0 + +/** MCPWM_GEN0_CFG0_REG register + * Generator0 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 0's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 0 event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 0 event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 + +/** MCPWM_GEN0_FORCE_REG register + * Generator0 output signal force mode register. + */ +#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator0.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM0 A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM0 B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM0 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM0 A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM0 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM0 B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN0_A_REG register + * PWM0 output signal A actions configuration register + */ +#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM0 A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U +#define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM0 A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM0 A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM0 A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM0 A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM0 A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM0 A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM0 A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM0 A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM0 A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM0 A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM0 A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 + +/** MCPWM_GEN0_B_REG register + * PWM0 output signal B actions configuration register + */ +#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM0 B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U +#define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM0 B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM0 B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM0 B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM0 B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM0 B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM0 B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM0 B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM0 B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM0 B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM0 B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM0 B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 + +/** MCPWM_DT0_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58) +/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_M (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S) +#define MCPWM_DT0_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_S 0 +/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_M (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S) +#define MCPWM_DT0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_S 4 +/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT0_DEB_MODE (BIT(8)) +#define MCPWM_DT0_DEB_MODE_M (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S) +#define MCPWM_DT0_DEB_MODE_V 0x00000001U +#define MCPWM_DT0_DEB_MODE_S 8 +/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DT0_A_OUTSWAP (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_M (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S) +#define MCPWM_DT0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_A_OUTSWAP_S 9 +/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DT0_B_OUTSWAP (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_M (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S) +#define MCPWM_DT0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_B_OUTSWAP_S 10 +/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DT0_RED_INSEL (BIT(11)) +#define MCPWM_DT0_RED_INSEL_M (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S) +#define MCPWM_DT0_RED_INSEL_V 0x00000001U +#define MCPWM_DT0_RED_INSEL_S 11 +/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DT0_FED_INSEL (BIT(12)) +#define MCPWM_DT0_FED_INSEL_M (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S) +#define MCPWM_DT0_FED_INSEL_V 0x00000001U +#define MCPWM_DT0_FED_INSEL_S 12 +/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_M (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S) +#define MCPWM_DT0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_RED_OUTINVERT_S 13 +/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_M (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S) +#define MCPWM_DT0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_FED_OUTINVERT_S 14 +/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_M (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S) +#define MCPWM_DT0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_A_OUTBYPASS_S 15 +/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_M (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S) +#define MCPWM_DT0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_B_OUTBYPASS_S 16 +/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 0 clock selection.\\0: PWM_clk\\1: PT_clk + */ +#define MCPWM_DT0_CLK_SEL (BIT(17)) +#define MCPWM_DT0_CLK_SEL_M (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S) +#define MCPWM_DT0_CLK_SEL_V 0x00000001U +#define MCPWM_DT0_CLK_SEL_S 17 + +/** MCPWM_DT0_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c) +/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DT0_FED 0x0000FFFFU +#define MCPWM_DT0_FED_M (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S) +#define MCPWM_DT0_FED_V 0x0000FFFFU +#define MCPWM_DT0_FED_S 0 + +/** MCPWM_DT0_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60) +/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DT0_RED 0x0000FFFFU +#define MCPWM_DT0_RED_M (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S) +#define MCPWM_DT0_RED_V 0x0000FFFFU +#define MCPWM_DT0_RED_S 0 + +/** MCPWM_CARRIER0_CFG_REG register + * Carrier0 configuration register + */ +#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64) +/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier0.\\0: Bypassed\\1: Enabled + */ +#define MCPWM_CARRIER0_EN (BIT(0)) +#define MCPWM_CARRIER0_EN_M (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S) +#define MCPWM_CARRIER0_EN_V 0x00000001U +#define MCPWM_CARRIER0_EN_S 0 +/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier0 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER0_PRESCALE 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_M (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S) +#define MCPWM_CARRIER0_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_S 1 +/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER0_DUTY 0x00000007U +#define MCPWM_CARRIER0_DUTY_M (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S) +#define MCPWM_CARRIER0_DUTY_V 0x00000007U +#define MCPWM_CARRIER0_DUTY_S 5 +/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CARRIER0_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_M (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S) +#define MCPWM_CARRIER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_S 8 +/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM0 A and PWM0 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_M (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S) +#define MCPWM_CARRIER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_OUT_INVERT_S 12 +/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM0 A and PWM0 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_M (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S) +#define MCPWM_CARRIER0_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_IN_INVERT_S 13 + +/** MCPWM_FH0_CFG0_REG register + * PWM0 A and PWM0 B trip events actions configuration register + */ +#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68) +/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_SW_CBC (BIT(0)) +#define MCPWM_FH0_SW_CBC_M (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S) +#define MCPWM_FH0_SW_CBC_V 0x00000001U +#define MCPWM_FH0_SW_CBC_S 0 +/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F2_CBC (BIT(1)) +#define MCPWM_FH0_F2_CBC_M (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S) +#define MCPWM_FH0_F2_CBC_V 0x00000001U +#define MCPWM_FH0_F2_CBC_S 1 +/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F1_CBC (BIT(2)) +#define MCPWM_FH0_F1_CBC_M (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S) +#define MCPWM_FH0_F1_CBC_V 0x00000001U +#define MCPWM_FH0_F1_CBC_S 2 +/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F0_CBC (BIT(3)) +#define MCPWM_FH0_F0_CBC_M (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S) +#define MCPWM_FH0_F0_CBC_V 0x00000001U +#define MCPWM_FH0_F0_CBC_S 3 +/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_SW_OST (BIT(4)) +#define MCPWM_FH0_SW_OST_M (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S) +#define MCPWM_FH0_SW_OST_V 0x00000001U +#define MCPWM_FH0_SW_OST_S 4 +/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F2_OST (BIT(5)) +#define MCPWM_FH0_F2_OST_M (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S) +#define MCPWM_FH0_F2_OST_V 0x00000001U +#define MCPWM_FH0_F2_OST_S 5 +/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F1_OST (BIT(6)) +#define MCPWM_FH0_F1_OST_M (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S) +#define MCPWM_FH0_F1_OST_V 0x00000001U +#define MCPWM_FH0_F1_OST_S 6 +/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F0_OST (BIT(7)) +#define MCPWM_FH0_F0_OST_M (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S) +#define MCPWM_FH0_F0_OST_V 0x00000001U +#define MCPWM_FH0_F0_OST_S 7 +/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_CBC_D 0x00000003U +#define MCPWM_FH0_A_CBC_D_M (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S) +#define MCPWM_FH0_A_CBC_D_V 0x00000003U +#define MCPWM_FH0_A_CBC_D_S 8 +/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_CBC_U 0x00000003U +#define MCPWM_FH0_A_CBC_U_M (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S) +#define MCPWM_FH0_A_CBC_U_V 0x00000003U +#define MCPWM_FH0_A_CBC_U_S 10 +/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM0 A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_OST_D 0x00000003U +#define MCPWM_FH0_A_OST_D_M (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S) +#define MCPWM_FH0_A_OST_D_V 0x00000003U +#define MCPWM_FH0_A_OST_D_S 12 +/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM0 A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_OST_U 0x00000003U +#define MCPWM_FH0_A_OST_U_M (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S) +#define MCPWM_FH0_A_OST_U_V 0x00000003U +#define MCPWM_FH0_A_OST_U_S 14 +/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_CBC_D 0x00000003U +#define MCPWM_FH0_B_CBC_D_M (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S) +#define MCPWM_FH0_B_CBC_D_V 0x00000003U +#define MCPWM_FH0_B_CBC_D_S 16 +/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_CBC_U 0x00000003U +#define MCPWM_FH0_B_CBC_U_M (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S) +#define MCPWM_FH0_B_CBC_U_V 0x00000003U +#define MCPWM_FH0_B_CBC_U_S 18 +/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM0 B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_OST_D 0x00000003U +#define MCPWM_FH0_B_OST_D_M (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S) +#define MCPWM_FH0_B_OST_D_V 0x00000003U +#define MCPWM_FH0_B_OST_D_S 20 +/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM0 B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_OST_U 0x00000003U +#define MCPWM_FH0_B_OST_U_M (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S) +#define MCPWM_FH0_B_OST_U_V 0x00000003U +#define MCPWM_FH0_B_OST_U_S 22 + +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c) +/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_FH0_CLR_OST (BIT(0)) +#define MCPWM_FH0_CLR_OST_M (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S) +#define MCPWM_FH0_CLR_OST_V 0x00000001U +#define MCPWM_FH0_CLR_OST_S 0 +/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ +#define MCPWM_FH0_CBCPULSE 0x00000003U +#define MCPWM_FH0_CBCPULSE_M (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S) +#define MCPWM_FH0_CBCPULSE_V 0x00000003U +#define MCPWM_FH0_CBCPULSE_S 1 +/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_FH0_FORCE_CBC (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_M (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S) +#define MCPWM_FH0_FORCE_CBC_V 0x00000001U +#define MCPWM_FH0_FORCE_CBC_S 3 +/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_FH0_FORCE_OST (BIT(4)) +#define MCPWM_FH0_FORCE_OST_M (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S) +#define MCPWM_FH0_FORCE_OST_V 0x00000001U +#define MCPWM_FH0_FORCE_OST_S 4 + +/** MCPWM_FH0_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70) +/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ +#define MCPWM_FH0_CBC_ON (BIT(0)) +#define MCPWM_FH0_CBC_ON_M (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S) +#define MCPWM_FH0_CBC_ON_V 0x00000001U +#define MCPWM_FH0_CBC_ON_S 0 +/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ +#define MCPWM_FH0_OST_ON (BIT(1)) +#define MCPWM_FH0_OST_ON_M (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S) +#define MCPWM_FH0_OST_ON_V 0x00000001U +#define MCPWM_FH0_OST_ON_S 1 + +/** MCPWM_GEN1_STMP_CFG_REG register + * Generator1 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74) +/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 1 time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_M (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S) +#define MCPWM_GEN1_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_S 0 +/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 1 time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_M (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S) +#define MCPWM_GEN1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_S 4 +/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_M (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S) +#define MCPWM_GEN1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_A_SHDW_FULL_S 8 +/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_M (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S) +#define MCPWM_GEN1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_B_SHDW_FULL_S 9 + +/** MCPWM_GEN1_TSTMP_A_REG register + * Generator1 time stamp A's shadow register + */ +#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78) +/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 1 time stamp A's shadow register. + */ +#define MCPWM_GEN1_A 0x0000FFFFU +#define MCPWM_GEN1_A_M (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S) +#define MCPWM_GEN1_A_V 0x0000FFFFU +#define MCPWM_GEN1_A_S 0 + +/** MCPWM_GEN1_TSTMP_B_REG register + * Generator1 time stamp B's shadow register + */ +#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c) +/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 1 time stamp B's shadow register. + */ +#define MCPWM_GEN1_B 0x0000FFFFU +#define MCPWM_GEN1_B_M (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S) +#define MCPWM_GEN1_B_V 0x0000FFFFU +#define MCPWM_GEN1_B_S 0 + +/** MCPWM_GEN1_CFG0_REG register + * Generator1 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 1's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 1 event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 1 event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 + +/** MCPWM_GEN1_FORCE_REG register + * Generator1 output signal force mode register. + */ +#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator1.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM1 A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM1 B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM1 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM1 A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM1 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM1 B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN1_A_REG register + * PWM1 output signal A actions configuration register + */ +#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM1 A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U +#define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM1 A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM1 A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM1 A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM1 A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM1 A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM1 A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM1 A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM1 A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM1 A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM1 A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM1 A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 + +/** MCPWM_GEN1_B_REG register + * PWM1 output signal B actions configuration register + */ +#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM1 B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U +#define MCPWM_GEN1_B_UTEZ_S 0 +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM1 B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM1 B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM1 B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM1 B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM1 B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM1 B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM1 B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM1 B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM1 B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM1 B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM1 B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 + +/** MCPWM_DT1_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90) +/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_M (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S) +#define MCPWM_DT1_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_S 0 +/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_M (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S) +#define MCPWM_DT1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_S 4 +/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT1_DEB_MODE (BIT(8)) +#define MCPWM_DT1_DEB_MODE_M (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S) +#define MCPWM_DT1_DEB_MODE_V 0x00000001U +#define MCPWM_DT1_DEB_MODE_S 8 +/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DT1_A_OUTSWAP (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_M (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S) +#define MCPWM_DT1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_A_OUTSWAP_S 9 +/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DT1_B_OUTSWAP (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_M (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S) +#define MCPWM_DT1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_B_OUTSWAP_S 10 +/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DT1_RED_INSEL (BIT(11)) +#define MCPWM_DT1_RED_INSEL_M (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S) +#define MCPWM_DT1_RED_INSEL_V 0x00000001U +#define MCPWM_DT1_RED_INSEL_S 11 +/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DT1_FED_INSEL (BIT(12)) +#define MCPWM_DT1_FED_INSEL_M (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S) +#define MCPWM_DT1_FED_INSEL_V 0x00000001U +#define MCPWM_DT1_FED_INSEL_S 12 +/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_M (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S) +#define MCPWM_DT1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_RED_OUTINVERT_S 13 +/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_M (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S) +#define MCPWM_DT1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_FED_OUTINVERT_S 14 +/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_M (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S) +#define MCPWM_DT1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_A_OUTBYPASS_S 15 +/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_M (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S) +#define MCPWM_DT1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_B_OUTBYPASS_S 16 +/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 1 clock selection.\\0: PWM_clk\\1: PT_clk + */ +#define MCPWM_DT1_CLK_SEL (BIT(17)) +#define MCPWM_DT1_CLK_SEL_M (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S) +#define MCPWM_DT1_CLK_SEL_V 0x00000001U +#define MCPWM_DT1_CLK_SEL_S 17 + +/** MCPWM_DT1_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94) +/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DT1_FED 0x0000FFFFU +#define MCPWM_DT1_FED_M (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S) +#define MCPWM_DT1_FED_V 0x0000FFFFU +#define MCPWM_DT1_FED_S 0 + +/** MCPWM_DT1_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98) +/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DT1_RED 0x0000FFFFU +#define MCPWM_DT1_RED_M (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S) +#define MCPWM_DT1_RED_V 0x0000FFFFU +#define MCPWM_DT1_RED_S 0 + +/** MCPWM_CARRIER1_CFG_REG register + * Carrier1 configuration register + */ +#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c) +/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier1.\\0: Bypassed\\1: Enabled + */ +#define MCPWM_CARRIER1_EN (BIT(0)) +#define MCPWM_CARRIER1_EN_M (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S) +#define MCPWM_CARRIER1_EN_V 0x00000001U +#define MCPWM_CARRIER1_EN_S 0 +/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier1 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1) + */ +#define MCPWM_CARRIER1_PRESCALE 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_M (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S) +#define MCPWM_CARRIER1_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_S 1 +/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER1_DUTY / 8 + */ +#define MCPWM_CARRIER1_DUTY 0x00000007U +#define MCPWM_CARRIER1_DUTY_M (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S) +#define MCPWM_CARRIER1_DUTY_V 0x00000007U +#define MCPWM_CARRIER1_DUTY_S 5 +/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CARRIER1_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_M (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S) +#define MCPWM_CARRIER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_S 8 +/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM1 A and PWM1 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_M (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S) +#define MCPWM_CARRIER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_OUT_INVERT_S 12 +/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM1 A and PWM1 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_M (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S) +#define MCPWM_CARRIER1_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_IN_INVERT_S 13 + +/** MCPWM_FH1_CFG0_REG register + * PWM1 A and PWM1 B trip events actions configuration register + */ +#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0) +/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_SW_CBC (BIT(0)) +#define MCPWM_FH1_SW_CBC_M (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S) +#define MCPWM_FH1_SW_CBC_V 0x00000001U +#define MCPWM_FH1_SW_CBC_S 0 +/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F2_CBC (BIT(1)) +#define MCPWM_FH1_F2_CBC_M (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S) +#define MCPWM_FH1_F2_CBC_V 0x00000001U +#define MCPWM_FH1_F2_CBC_S 1 +/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F1_CBC (BIT(2)) +#define MCPWM_FH1_F1_CBC_M (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S) +#define MCPWM_FH1_F1_CBC_V 0x00000001U +#define MCPWM_FH1_F1_CBC_S 2 +/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F0_CBC (BIT(3)) +#define MCPWM_FH1_F0_CBC_M (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S) +#define MCPWM_FH1_F0_CBC_V 0x00000001U +#define MCPWM_FH1_F0_CBC_S 3 +/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_SW_OST (BIT(4)) +#define MCPWM_FH1_SW_OST_M (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S) +#define MCPWM_FH1_SW_OST_V 0x00000001U +#define MCPWM_FH1_SW_OST_S 4 +/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F2_OST (BIT(5)) +#define MCPWM_FH1_F2_OST_M (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S) +#define MCPWM_FH1_F2_OST_V 0x00000001U +#define MCPWM_FH1_F2_OST_S 5 +/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F1_OST (BIT(6)) +#define MCPWM_FH1_F1_OST_M (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S) +#define MCPWM_FH1_F1_OST_V 0x00000001U +#define MCPWM_FH1_F1_OST_S 6 +/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F0_OST (BIT(7)) +#define MCPWM_FH1_F0_OST_M (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S) +#define MCPWM_FH1_F0_OST_V 0x00000001U +#define MCPWM_FH1_F0_OST_S 7 +/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_CBC_D 0x00000003U +#define MCPWM_FH1_A_CBC_D_M (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S) +#define MCPWM_FH1_A_CBC_D_V 0x00000003U +#define MCPWM_FH1_A_CBC_D_S 8 +/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_CBC_U 0x00000003U +#define MCPWM_FH1_A_CBC_U_M (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S) +#define MCPWM_FH1_A_CBC_U_V 0x00000003U +#define MCPWM_FH1_A_CBC_U_S 10 +/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM1 A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_OST_D 0x00000003U +#define MCPWM_FH1_A_OST_D_M (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S) +#define MCPWM_FH1_A_OST_D_V 0x00000003U +#define MCPWM_FH1_A_OST_D_S 12 +/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM1 A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_OST_U 0x00000003U +#define MCPWM_FH1_A_OST_U_M (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S) +#define MCPWM_FH1_A_OST_U_V 0x00000003U +#define MCPWM_FH1_A_OST_U_S 14 +/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_CBC_D 0x00000003U +#define MCPWM_FH1_B_CBC_D_M (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S) +#define MCPWM_FH1_B_CBC_D_V 0x00000003U +#define MCPWM_FH1_B_CBC_D_S 16 +/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_CBC_U 0x00000003U +#define MCPWM_FH1_B_CBC_U_M (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S) +#define MCPWM_FH1_B_CBC_U_V 0x00000003U +#define MCPWM_FH1_B_CBC_U_S 18 +/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM1 B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_OST_D 0x00000003U +#define MCPWM_FH1_B_OST_D_M (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S) +#define MCPWM_FH1_B_OST_D_V 0x00000003U +#define MCPWM_FH1_B_OST_D_S 20 +/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM1 B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_OST_U 0x00000003U +#define MCPWM_FH1_B_OST_U_M (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S) +#define MCPWM_FH1_B_OST_U_V 0x00000003U +#define MCPWM_FH1_B_OST_U_S 22 + +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4) +/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_FH1_CLR_OST (BIT(0)) +#define MCPWM_FH1_CLR_OST_M (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S) +#define MCPWM_FH1_CLR_OST_V 0x00000001U +#define MCPWM_FH1_CLR_OST_S 0 +/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ +#define MCPWM_FH1_CBCPULSE 0x00000003U +#define MCPWM_FH1_CBCPULSE_M (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S) +#define MCPWM_FH1_CBCPULSE_V 0x00000003U +#define MCPWM_FH1_CBCPULSE_S 1 +/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_FH1_FORCE_CBC (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_M (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S) +#define MCPWM_FH1_FORCE_CBC_V 0x00000001U +#define MCPWM_FH1_FORCE_CBC_S 3 +/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_FH1_FORCE_OST (BIT(4)) +#define MCPWM_FH1_FORCE_OST_M (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S) +#define MCPWM_FH1_FORCE_OST_V 0x00000001U +#define MCPWM_FH1_FORCE_OST_S 4 + +/** MCPWM_FH1_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8) +/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ +#define MCPWM_FH1_CBC_ON (BIT(0)) +#define MCPWM_FH1_CBC_ON_M (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S) +#define MCPWM_FH1_CBC_ON_V 0x00000001U +#define MCPWM_FH1_CBC_ON_S 0 +/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ +#define MCPWM_FH1_OST_ON (BIT(1)) +#define MCPWM_FH1_OST_ON_M (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S) +#define MCPWM_FH1_OST_ON_V 0x00000001U +#define MCPWM_FH1_OST_ON_S 1 + +/** MCPWM_GEN2_STMP_CFG_REG register + * Generator2 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac) +/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 2 time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_M (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S) +#define MCPWM_GEN2_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_S 0 +/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 2 time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_M (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S) +#define MCPWM_GEN2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_S 4 +/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_M (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S) +#define MCPWM_GEN2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_A_SHDW_FULL_S 8 +/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_M (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S) +#define MCPWM_GEN2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_B_SHDW_FULL_S 9 + +/** MCPWM_GEN2_TSTMP_A_REG register + * Generator2 time stamp A's shadow register + */ +#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0) +/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 2 time stamp A's shadow register. + */ +#define MCPWM_GEN2_A 0x0000FFFFU +#define MCPWM_GEN2_A_M (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S) +#define MCPWM_GEN2_A_V 0x0000FFFFU +#define MCPWM_GEN2_A_S 0 + +/** MCPWM_GEN2_TSTMP_B_REG register + * Generator2 time stamp B's shadow register + */ +#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4) +/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 2 time stamp B's shadow register. + */ +#define MCPWM_GEN2_B 0x0000FFFFU +#define MCPWM_GEN2_B_M (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S) +#define MCPWM_GEN2_B_V 0x0000FFFFU +#define MCPWM_GEN2_B_S 0 + +/** MCPWM_GEN2_CFG0_REG register + * Generator2 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 2's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 2 event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 2 event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 + +/** MCPWM_GEN2_FORCE_REG register + * Generator2 output signal force mode register. + */ +#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator2.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM2 A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM2 B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM2 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM2 A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM2 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM2 B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN2_A_REG register + * PWM2 output signal A actions configuration register + */ +#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM2 A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U +#define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM2 A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM2 A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM2 A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM2 A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM2 A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM2 A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM2 A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM2 A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM2 A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM2 A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM2 A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 + +/** MCPWM_GEN2_B_REG register + * PWM2 output signal B actions configuration register + */ +#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM2 B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U +#define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM2 B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM2 B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM2 B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM2 B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM2 B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM2 B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM2 B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM2 B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM2 B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM2 B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM2 B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 + +/** MCPWM_DT2_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8) +/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_M (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S) +#define MCPWM_DT2_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_S 0 +/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_M (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S) +#define MCPWM_DT2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_S 4 +/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT2_DEB_MODE (BIT(8)) +#define MCPWM_DT2_DEB_MODE_M (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S) +#define MCPWM_DT2_DEB_MODE_V 0x00000001U +#define MCPWM_DT2_DEB_MODE_S 8 +/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DT2_A_OUTSWAP (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_M (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S) +#define MCPWM_DT2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_A_OUTSWAP_S 9 +/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DT2_B_OUTSWAP (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_M (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S) +#define MCPWM_DT2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_B_OUTSWAP_S 10 +/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DT2_RED_INSEL (BIT(11)) +#define MCPWM_DT2_RED_INSEL_M (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S) +#define MCPWM_DT2_RED_INSEL_V 0x00000001U +#define MCPWM_DT2_RED_INSEL_S 11 +/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DT2_FED_INSEL (BIT(12)) +#define MCPWM_DT2_FED_INSEL_M (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S) +#define MCPWM_DT2_FED_INSEL_V 0x00000001U +#define MCPWM_DT2_FED_INSEL_S 12 +/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_M (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S) +#define MCPWM_DT2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_RED_OUTINVERT_S 13 +/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_M (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S) +#define MCPWM_DT2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_FED_OUTINVERT_S 14 +/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_M (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S) +#define MCPWM_DT2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_A_OUTBYPASS_S 15 +/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_M (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S) +#define MCPWM_DT2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_B_OUTBYPASS_S 16 +/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 2 clock selection.\\0: PWM_clk\\1: PT_clk + */ +#define MCPWM_DT2_CLK_SEL (BIT(17)) +#define MCPWM_DT2_CLK_SEL_M (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S) +#define MCPWM_DT2_CLK_SEL_V 0x00000001U +#define MCPWM_DT2_CLK_SEL_S 17 + +/** MCPWM_DT2_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc) +/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DT2_FED 0x0000FFFFU +#define MCPWM_DT2_FED_M (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S) +#define MCPWM_DT2_FED_V 0x0000FFFFU +#define MCPWM_DT2_FED_S 0 + +/** MCPWM_DT2_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0) +/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DT2_RED 0x0000FFFFU +#define MCPWM_DT2_RED_M (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S) +#define MCPWM_DT2_RED_V 0x0000FFFFU +#define MCPWM_DT2_RED_S 0 + +/** MCPWM_CARRIER2_CFG_REG register + * Carrier2 configuration register + */ +#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4) +/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier2.\\0: Bypassed\\1: Enabled + */ +#define MCPWM_CARRIER2_EN (BIT(0)) +#define MCPWM_CARRIER2_EN_M (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S) +#define MCPWM_CARRIER2_EN_V 0x00000001U +#define MCPWM_CARRIER2_EN_S 0 +/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier2 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1) + */ +#define MCPWM_CARRIER2_PRESCALE 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_M (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S) +#define MCPWM_CARRIER2_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_S 1 +/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER2_DUTY / 8 + */ +#define MCPWM_CARRIER2_DUTY 0x00000007U +#define MCPWM_CARRIER2_DUTY_M (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S) +#define MCPWM_CARRIER2_DUTY_V 0x00000007U +#define MCPWM_CARRIER2_DUTY_S 5 +/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CARRIER2_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_M (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S) +#define MCPWM_CARRIER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_S 8 +/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM2 A and PWM2 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_M (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S) +#define MCPWM_CARRIER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_OUT_INVERT_S 12 +/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM2 A and PWM2 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_M (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S) +#define MCPWM_CARRIER2_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_IN_INVERT_S 13 + +/** MCPWM_FH2_CFG0_REG register + * PWM2 A and PWM2 B trip events actions configuration register + */ +#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8) +/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_SW_CBC (BIT(0)) +#define MCPWM_FH2_SW_CBC_M (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S) +#define MCPWM_FH2_SW_CBC_V 0x00000001U +#define MCPWM_FH2_SW_CBC_S 0 +/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F2_CBC (BIT(1)) +#define MCPWM_FH2_F2_CBC_M (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S) +#define MCPWM_FH2_F2_CBC_V 0x00000001U +#define MCPWM_FH2_F2_CBC_S 1 +/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F1_CBC (BIT(2)) +#define MCPWM_FH2_F1_CBC_M (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S) +#define MCPWM_FH2_F1_CBC_V 0x00000001U +#define MCPWM_FH2_F1_CBC_S 2 +/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F0_CBC (BIT(3)) +#define MCPWM_FH2_F0_CBC_M (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S) +#define MCPWM_FH2_F0_CBC_V 0x00000001U +#define MCPWM_FH2_F0_CBC_S 3 +/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_SW_OST (BIT(4)) +#define MCPWM_FH2_SW_OST_M (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S) +#define MCPWM_FH2_SW_OST_V 0x00000001U +#define MCPWM_FH2_SW_OST_S 4 +/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F2_OST (BIT(5)) +#define MCPWM_FH2_F2_OST_M (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S) +#define MCPWM_FH2_F2_OST_V 0x00000001U +#define MCPWM_FH2_F2_OST_S 5 +/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F1_OST (BIT(6)) +#define MCPWM_FH2_F1_OST_M (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S) +#define MCPWM_FH2_F1_OST_V 0x00000001U +#define MCPWM_FH2_F1_OST_S 6 +/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F0_OST (BIT(7)) +#define MCPWM_FH2_F0_OST_M (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S) +#define MCPWM_FH2_F0_OST_V 0x00000001U +#define MCPWM_FH2_F0_OST_S 7 +/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_CBC_D 0x00000003U +#define MCPWM_FH2_A_CBC_D_M (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S) +#define MCPWM_FH2_A_CBC_D_V 0x00000003U +#define MCPWM_FH2_A_CBC_D_S 8 +/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_CBC_U 0x00000003U +#define MCPWM_FH2_A_CBC_U_M (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S) +#define MCPWM_FH2_A_CBC_U_V 0x00000003U +#define MCPWM_FH2_A_CBC_U_S 10 +/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM2 A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_OST_D 0x00000003U +#define MCPWM_FH2_A_OST_D_M (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S) +#define MCPWM_FH2_A_OST_D_V 0x00000003U +#define MCPWM_FH2_A_OST_D_S 12 +/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM2 A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_OST_U 0x00000003U +#define MCPWM_FH2_A_OST_U_M (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S) +#define MCPWM_FH2_A_OST_U_V 0x00000003U +#define MCPWM_FH2_A_OST_U_S 14 +/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_CBC_D 0x00000003U +#define MCPWM_FH2_B_CBC_D_M (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S) +#define MCPWM_FH2_B_CBC_D_V 0x00000003U +#define MCPWM_FH2_B_CBC_D_S 16 +/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_CBC_U 0x00000003U +#define MCPWM_FH2_B_CBC_U_M (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S) +#define MCPWM_FH2_B_CBC_U_V 0x00000003U +#define MCPWM_FH2_B_CBC_U_S 18 +/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM2 B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_OST_D 0x00000003U +#define MCPWM_FH2_B_OST_D_M (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S) +#define MCPWM_FH2_B_OST_D_V 0x00000003U +#define MCPWM_FH2_B_OST_D_S 20 +/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM2 B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_OST_U 0x00000003U +#define MCPWM_FH2_B_OST_U_M (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S) +#define MCPWM_FH2_B_OST_U_V 0x00000003U +#define MCPWM_FH2_B_OST_U_S 22 + +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc) +/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_FH2_CLR_OST (BIT(0)) +#define MCPWM_FH2_CLR_OST_M (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S) +#define MCPWM_FH2_CLR_OST_V 0x00000001U +#define MCPWM_FH2_CLR_OST_S 0 +/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ +#define MCPWM_FH2_CBCPULSE 0x00000003U +#define MCPWM_FH2_CBCPULSE_M (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S) +#define MCPWM_FH2_CBCPULSE_V 0x00000003U +#define MCPWM_FH2_CBCPULSE_S 1 +/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_FH2_FORCE_CBC (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_M (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S) +#define MCPWM_FH2_FORCE_CBC_V 0x00000001U +#define MCPWM_FH2_FORCE_CBC_S 3 +/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_FH2_FORCE_OST (BIT(4)) +#define MCPWM_FH2_FORCE_OST_M (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S) +#define MCPWM_FH2_FORCE_OST_V 0x00000001U +#define MCPWM_FH2_FORCE_OST_S 4 + +/** MCPWM_FH2_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0) +/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ +#define MCPWM_FH2_CBC_ON (BIT(0)) +#define MCPWM_FH2_CBC_ON_M (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S) +#define MCPWM_FH2_CBC_ON_V 0x00000001U +#define MCPWM_FH2_CBC_ON_S 0 +/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ +#define MCPWM_FH2_OST_ON (BIT(1)) +#define MCPWM_FH2_OST_ON_M (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S) +#define MCPWM_FH2_OST_ON_V 0x00000001U +#define MCPWM_FH2_OST_ON_S 1 + +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status register + */ +#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U +#define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 + +/** MCPWM_CAP_TIMER_CFG_REG register + * Capture timer configuration register + */ +#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U +#define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input.\\0: None\\1: Timer0 + * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: + * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: + * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with + * value in phase register + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 + +/** MCPWM_CAP_TIMER_PHASE_REG register + * Capture timer sync phase register + */ +#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec) +/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ +#define MCPWM_CAP_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration register + */ +#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U +#define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 0 after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAP0. Prescale value = + * PWM_CAP0_PRESCALE + 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 + +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration register + */ +#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U +#define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 1 after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAP1. Prescale value = + * PWM_CAP1_PRESCALE + 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 + +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration register + */ +#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U +#define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 2 after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAP2. Prescale value = + * PWM_CAP2_PRESCALE + 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 + +/** MCPWM_CAP_CH0_REG register + * CAP0 capture value register + */ +#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_S 0 + +/** MCPWM_CAP_CH1_REG register + * CAP1 capture value register + */ +#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_S 0 + +/** MCPWM_CAP_CH2_REG register + * CAP2 capture value register + */ +#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_S 0 + +/** MCPWM_CAP_STATUS_REG register + * Last capture trigger edge information register + */ +#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U +#define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 + +/** MCPWM_UPDATE_CFG_REG register + * Generator Update configuration register + */ +#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module.\\0: Disable\\1: Enable + */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U +#define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 + +/** MCPWM_INT_ENA_REG register + * Interrupt enable register + */ +#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) +#define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ENA_S 24 +/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) +#define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ENA_S 25 +/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) +#define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 + +/** MCPWM_INT_RAW_REG register + * Interrupt raw status register + */ +#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) +#define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_OST_INT_RAW_S 24 +/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) +#define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_OST_INT_RAW_S 25 +/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) +#define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 + +/** MCPWM_INT_ST_REG register + * Interrupt masked status register + */ +#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) +#define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ST_S 21 +/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) +#define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ST_S 22 +/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) +#define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ST_S 23 +/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) +#define MCPWM_TZ0_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ST_S 24 +/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) +#define MCPWM_TZ1_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ST_S 25 +/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) +#define MCPWM_TZ2_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 + +/** MCPWM_INT_CLR_REG register + * Interrupt clear register + */ +#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) +#define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_OST_INT_CLR_S 24 +/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) +#define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_OST_INT_CLR_S 25 +/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) +#define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 + +/** MCPWM_EVT_EN_REG register + * Event enable register + */ +#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120) +/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) +#define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) +#define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_STOP_EN_S 0 +/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) +#define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) +#define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_STOP_EN_S 1 +/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) +#define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) +#define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_STOP_EN_S 2 +/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) +#define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) +#define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEZ_EN_S 3 +/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) +#define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) +#define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEZ_EN_S 4 +/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) +#define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) +#define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEZ_EN_S 5 +/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) +#define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) +#define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEP_EN_S 6 +/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) +#define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) +#define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEP_EN_S 7 +/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) +#define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) +#define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEP_EN_S 8 +/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEA_EN (BIT(9)) +#define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) +#define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEA_EN_S 9 +/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEA_EN (BIT(10)) +#define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) +#define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEA_EN_S 10 +/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEA_EN (BIT(11)) +#define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) +#define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEA_EN_S 11 +/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEB_EN (BIT(12)) +#define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) +#define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEB_EN_S 12 +/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEB_EN (BIT(13)) +#define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) +#define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEB_EN_S 13 +/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEB_EN (BIT(14)) +#define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) +#define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEB_EN_S 14 +/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_F0_EN (BIT(15)) +#define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) +#define MCPWM_EVT_F0_EN_V 0x00000001U +#define MCPWM_EVT_F0_EN_S 15 +/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_F1_EN (BIT(16)) +#define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) +#define MCPWM_EVT_F1_EN_V 0x00000001U +#define MCPWM_EVT_F1_EN_S 16 +/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_F2_EN (BIT(17)) +#define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) +#define MCPWM_EVT_F2_EN_V 0x00000001U +#define MCPWM_EVT_F2_EN_S 17 +/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_F0_CLR_EN (BIT(18)) +#define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) +#define MCPWM_EVT_F0_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F0_CLR_EN_S 18 +/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_F1_CLR_EN (BIT(19)) +#define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) +#define MCPWM_EVT_F1_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F1_CLR_EN_S 19 +/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_F2_CLR_EN (BIT(20)) +#define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) +#define MCPWM_EVT_F2_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F2_CLR_EN_S 20 +/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) +#define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) +#define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_CBC_EN_S 21 +/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) +#define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) +#define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_CBC_EN_S 22 +/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) +#define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) +#define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_CBC_EN_S 23 +/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TZ0_OST_EN (BIT(24)) +#define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) +#define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_OST_EN_S 24 +/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TZ1_OST_EN (BIT(25)) +#define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) +#define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_OST_EN_S 25 +/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TZ2_OST_EN (BIT(26)) +#define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) +#define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_OST_EN_S 26 +/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_CAP0_EN (BIT(27)) +#define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) +#define MCPWM_EVT_CAP0_EN_V 0x00000001U +#define MCPWM_EVT_CAP0_EN_S 27 +/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_CAP1_EN (BIT(28)) +#define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) +#define MCPWM_EVT_CAP1_EN_V 0x00000001U +#define MCPWM_EVT_CAP1_EN_S 28 +/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_CAP2_EN (BIT(29)) +#define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) +#define MCPWM_EVT_CAP2_EN_V 0x00000001U +#define MCPWM_EVT_CAP2_EN_S 29 + +/** MCPWM_TASK_EN_REG register + * Task enable register + */ +#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124) +/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) +#define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) +#define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_A_UP_EN_S 0 +/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) +#define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) +#define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_A_UP_EN_S 1 +/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) +#define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) +#define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_A_UP_EN_S 2 +/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) +#define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) +#define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_B_UP_EN_S 3 +/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) +#define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) +#define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_B_UP_EN_S 4 +/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) +#define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) +#define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_B_UP_EN_S 5 +/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_GEN_STOP_EN (BIT(6)) +#define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) +#define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U +#define MCPWM_TASK_GEN_STOP_EN_S 6 +/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) +#define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) +#define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_SYNC_EN_S 7 +/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) +#define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) +#define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_SYNC_EN_S 8 +/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) +#define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) +#define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_SYNC_EN_S 9 +/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 +/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 +/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 +/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: + * Enable + */ +#define MCPWM_TASK_TZ0_OST_EN (BIT(13)) +#define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) +#define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ0_OST_EN_S 13 +/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: + * Enable + */ +#define MCPWM_TASK_TZ1_OST_EN (BIT(14)) +#define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) +#define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ1_OST_EN_S 14 +/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: + * Enable + */ +#define MCPWM_TASK_TZ2_OST_EN (BIT(15)) +#define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) +#define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ2_OST_EN_S 15 +/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_CLR0_OST_EN (BIT(16)) +#define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) +#define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR0_OST_EN_S 16 +/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_CLR1_OST_EN (BIT(17)) +#define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) +#define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR1_OST_EN_S 17 +/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_CLR2_OST_EN (BIT(18)) +#define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) +#define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR2_OST_EN_S 18 +/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CAP0_EN (BIT(19)) +#define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) +#define MCPWM_TASK_CAP0_EN_V 0x00000001U +#define MCPWM_TASK_CAP0_EN_S 19 +/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CAP1_EN (BIT(20)) +#define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) +#define MCPWM_TASK_CAP1_EN_V 0x00000001U +#define MCPWM_TASK_CAP1_EN_S 20 +/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CAP2_EN (BIT(21)) +#define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) +#define MCPWM_TASK_CAP2_EN_V 0x00000001U +#define MCPWM_TASK_CAP2_EN_S 21 + +/** MCPWM_EVT_EN2_REG register + * Event enable register2 + */ +#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128) +/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEE1_EN (BIT(0)) +#define MCPWM_EVT_OP0_TEE1_EN_M (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S) +#define MCPWM_EVT_OP0_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEE1_EN_S 0 +/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEE1_EN (BIT(1)) +#define MCPWM_EVT_OP1_TEE1_EN_M (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S) +#define MCPWM_EVT_OP1_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEE1_EN_S 1 +/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEE1_EN (BIT(2)) +#define MCPWM_EVT_OP2_TEE1_EN_M (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S) +#define MCPWM_EVT_OP2_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEE1_EN_S 2 +/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEE2_EN (BIT(3)) +#define MCPWM_EVT_OP0_TEE2_EN_M (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S) +#define MCPWM_EVT_OP0_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEE2_EN_S 3 +/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEE2_EN (BIT(4)) +#define MCPWM_EVT_OP1_TEE2_EN_M (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S) +#define MCPWM_EVT_OP1_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEE2_EN_S 4 +/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEE2_EN (BIT(5)) +#define MCPWM_EVT_OP2_TEE2_EN_M (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S) +#define MCPWM_EVT_OP2_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEE2_EN_S 5 + +/** MCPWM_OP0_TSTMP_E1_REG register + * Generator0 timer stamp E1 value register + */ +#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c) +/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator0 timer stamp E1 value register + */ +#define MCPWM_OP0_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E1_M (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S) +#define MCPWM_OP0_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E1_S 0 + +/** MCPWM_OP0_TSTMP_E2_REG register + * Generator0 timer stamp E2 value register + */ +#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130) +/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator0 timer stamp E2 value register + */ +#define MCPWM_OP0_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E2_M (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S) +#define MCPWM_OP0_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E2_S 0 + +/** MCPWM_OP1_TSTMP_E1_REG register + * Generator1 timer stamp E1 value register + */ +#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134) +/** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator1 timer stamp E1 value register + */ +#define MCPWM_OP1_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E1_M (MCPWM_OP1_TSTMP_E1_V << MCPWM_OP1_TSTMP_E1_S) +#define MCPWM_OP1_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E1_S 0 + +/** MCPWM_OP1_TSTMP_E2_REG register + * Generator1 timer stamp E2 value register + */ +#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138) +/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator1 timer stamp E2 value register + */ +#define MCPWM_OP1_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E2_M (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S) +#define MCPWM_OP1_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E2_S 0 + +/** MCPWM_OP2_TSTMP_E1_REG register + * Generator2 timer stamp E1 value register + */ +#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c) +/** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator2 timer stamp E1 value register + */ +#define MCPWM_OP2_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E1_M (MCPWM_OP2_TSTMP_E1_V << MCPWM_OP2_TSTMP_E1_S) +#define MCPWM_OP2_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E1_S 0 + +/** MCPWM_OP2_TSTMP_E2_REG register + * Generator2 timer stamp E2 value register + */ +#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140) +/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator2 timer stamp E2 value register + */ +#define MCPWM_OP2_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E2_M (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S) +#define MCPWM_OP2_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E2_S 0 + +/** MCPWM_CLK_REG register + * Global configuration register + */ +#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U +#define MCPWM_CLK_EN_S 0 + +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU +#define MCPWM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mcpwm_struct.h b/components/soc/esp32c5/include/soc/mcpwm_struct.h new file mode 100644 index 00000000000..dde07979a86 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mcpwm_struct.h @@ -0,0 +1,2031 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration register */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ + uint32_t clk_prescale:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + +/** Type of timern_cfg0 register + * PWM timern period and update method configuration register. + */ +typedef union { + struct { + /** timern_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timern, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMERn_PRESCALE + 1) + */ + uint32_t timern_prescale:8; + /** timern_period : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timern + */ + uint32_t timern_period:16; + /** timern_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timern period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ + uint32_t timern_period_upmethod:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} mcpwm_timern_cfg0_reg_t; + +/** Type of timern_cfg1 register + * PWM timern working mode and start/stop control register. + */ +typedef union { + struct { + /** timern_start : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timern.\\0: If PWM timern starts, then + * stops at TEZ\\1: If timern starts, then stops at TEP\\2: PWM timern starts and runs + * on\\3: Timern starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ + uint32_t timern_start:3; + /** timern_mod : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timern.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ + uint32_t timern_mod:2; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_timern_cfg1_reg_t; + +/** Type of timern_sync register + * PWM timern sync function configuration register. + */ +typedef union { + struct { + /** timern_synci_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timern reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ + uint32_t timern_synci_en:1; + /** timern_sync_sw : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ + uint32_t timern_sync_sw:1; + /** timern_synco_sel : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timern sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ + uint32_t timern_synco_sel:2; + /** timern_phase : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timern reload on sync event. + */ + uint32_t timern_phase:16; + /** timern_phase_direction : R/W; bitpos: [20]; default: 0; + * Configures the PWM timern's direction when timern mode is up-down mode.\\0: + * Increase\\1: Decrease + */ + uint32_t timern_phase_direction:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} mcpwm_timern_sync_reg_t; + +/** Type of timern_status register + * PWM timern status register. + */ +typedef union { + struct { + /** timern_value : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timern counter value. + */ + uint32_t timern_value:16; + /** timern_direction : RO; bitpos: [16]; default: 0; + * Represents current PWM timern counter direction.\\0: Increment\\1: Decrement + */ + uint32_t timern_direction:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} mcpwm_timern_status_reg_t; + +/** Type of timer_synci_cfg register + * Synchronization input selection register for PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer0_syncisel:3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer1_syncisel:3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer2_syncisel:3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci0_invert:1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci1_invert:1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci2_invert:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * PWM operator's timer select register + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator0_timersel:2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator1_timersel:2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator2_timersel:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: cfgrep */ +/** Type of genn_stmp_cfg register + * Generatorn time stamp registers A and B transfer status and update method register + */ +typedef union { + struct { + /** genn_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator n time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t genn_a_upmethod:4; + /** genn_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator n time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t genn_b_upmethod:4; + /** genn_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ + uint32_t genn_a_shdw_full:1; + /** genn_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ + uint32_t genn_b_shdw_full:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_genn_stmp_cfg_reg_t; + +/** Type of genn_tstmp_a register + * Generatorn time stamp A's shadow register + */ +typedef union { + struct { + /** genn_a : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator n time stamp A's shadow register. + */ + uint32_t genn_a:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_tstmp_a_reg_t; + +/** Type of genn_tstmp_b register + * Generatorn time stamp B's shadow register + */ +typedef union { + struct { + /** genn_b : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator n time stamp B's shadow register. + */ + uint32_t genn_b:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_tstmp_b_reg_t; + +/** Type of genn_cfg0 register + * Generatorn fault event T0 and T1 configuration register + */ +typedef union { + struct { + /** genn_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator n's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t genn_cfg_upmethod:4; + /** genn_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator n event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ + uint32_t genn_t0_sel:3; + /** genn_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator n event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ + uint32_t genn_t1_sel:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_genn_cfg0_reg_t; + +/** Type of genn_force register + * Generatorn output signal force mode register. + */ +typedef union { + struct { + /** genn_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generatorn.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ + uint32_t genn_cntuforce_upmethod:6; + /** genn_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWMn A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ + uint32_t genn_a_cntuforce_mode:2; + /** genn_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWMn B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ + uint32_t genn_b_cntuforce_mode:2; + /** genn_a_nciforce : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWMn + * A, a toggle will trigger a force event. + */ + uint32_t genn_a_nciforce:1; + /** genn_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWMn A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ + uint32_t genn_a_nciforce_mode:2; + /** genn_b_nciforce : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWMn + * B, a toggle will trigger a force event. + */ + uint32_t genn_b_nciforce:1; + /** genn_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWMn B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ + uint32_t genn_b_nciforce_mode:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_force_reg_t; + +/** Type of genn_a register + * PWMn output signal A actions configuration register + */ +typedef union { + struct { + /** genn_a_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWMn A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_utez:2; + /** genn_a_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWMn A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_utep:2; + /** genn_a_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWMn A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_utea:2; + /** genn_a_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWMn A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_uteb:2; + /** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWMn A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_ut0:2; + /** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWMn A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_ut1:2; + /** genn_a_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWMn A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dtez:2; + /** genn_a_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWMn A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dtep:2; + /** genn_a_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWMn A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dtea:2; + /** genn_a_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWMn A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dteb:2; + /** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWMn A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dt0:2; + /** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWMn A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_genn_a_reg_t; + +/** Type of genn_b register + * PWMn output signal B actions configuration register + */ +typedef union { + struct { + /** genn_b_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWMn B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_utez:2; + /** genn_b_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWMn B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_utep:2; + /** genn_b_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWMn B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_utea:2; + /** genn_b_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWMn B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_uteb:2; + /** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWMn B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_ut0:2; + /** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWMn B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_ut1:2; + /** genn_b_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWMn B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dtez:2; + /** genn_b_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWMn B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dtep:2; + /** genn_b_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWMn B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dtea:2; + /** genn_b_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWMn B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dteb:2; + /** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWMn B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dt0:2; + /** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWMn B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_genn_b_reg_t; + +/** Type of dtn_cfg register + * Dead time configuration register + */ +typedef union { + struct { + /** dtn_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t dtn_fed_upmethod:4; + /** dtn_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t dtn_red_upmethod:4; + /** dtn_deb_mode : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t dtn_deb_mode:1; + /** dtn_a_outswap : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ + uint32_t dtn_a_outswap:1; + /** dtn_b_outswap : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ + uint32_t dtn_b_outswap:1; + /** dtn_red_insel : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ + uint32_t dtn_red_insel:1; + /** dtn_fed_insel : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ + uint32_t dtn_fed_insel:1; + /** dtn_red_outinvert : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ + uint32_t dtn_red_outinvert:1; + /** dtn_fed_outinvert : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ + uint32_t dtn_fed_outinvert:1; + /** dtn_a_outbypass : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ + uint32_t dtn_a_outbypass:1; + /** dtn_b_outbypass : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ + uint32_t dtn_b_outbypass:1; + /** dtn_clk_sel : R/W; bitpos: [17]; default: 0; + * Configures dead time generator n clock selection.\\0: PWM_clk\\1: PT_clk + */ + uint32_t dtn_clk_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} mcpwm_dtn_cfg_reg_t; + +/** Type of dtn_fed_cfg register + * Falling edge delay (FED) shadow register + */ +typedef union { + struct { + /** dtn_fed : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ + uint32_t dtn_fed:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dtn_fed_cfg_reg_t; + +/** Type of dtn_red_cfg register + * Rising edge delay (RED) shadow register + */ +typedef union { + struct { + /** dtn_red : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ + uint32_t dtn_red:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dtn_red_cfg_reg_t; + +/** Type of carriern_cfg register + * Carriern configuration register + */ +typedef union { + struct { + /** carriern_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carriern.\\0: Bypassed\\1: Enabled + */ + uint32_t carriern_en:1; + /** carriern_prescale : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carriern clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1) + */ + uint32_t carriern_prescale:4; + /** carriern_duty : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8 + */ + uint32_t carriern_duty:3; + /** carriern_oshtwth : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ + uint32_t carriern_oshtwth:4; + /** carriern_out_invert : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWMn A and PWMn B for this + * submodule.\\0: Normal\\1: Invert + */ + uint32_t carriern_out_invert:1; + /** carriern_in_invert : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWMn A and PWMn B for this + * submodule.\\0: Normal\\1: Invert + */ + uint32_t carriern_in_invert:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} mcpwm_carriern_cfg_reg_t; + +/** Type of fhn_cfg0 register + * PWMn A and PWMn B trip events actions configuration register + */ +typedef union { + struct { + /** fhn_sw_cbc : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_sw_cbc:1; + /** fhn_f2_cbc : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f2_cbc:1; + /** fhn_f1_cbc : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f1_cbc:1; + /** fhn_f0_cbc : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f0_cbc:1; + /** fhn_sw_ost : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_sw_ost:1; + /** fhn_f2_ost : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f2_ost:1; + /** fhn_f1_ost : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f1_ost:1; + /** fhn_f0_ost : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f0_ost:1; + /** fhn_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_cbc_d:2; + /** fhn_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_cbc_u:2; + /** fhn_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWMn A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_ost_d:2; + /** fhn_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWMn A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_ost_u:2; + /** fhn_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_cbc_d:2; + /** fhn_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_cbc_u:2; + /** fhn_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWMn B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_ost_d:2; + /** fhn_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWMn B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_ost_u:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_fhn_cfg0_reg_t; + +/** Type of fhn_cfg1 register + * Software triggers for fault handler actions configuration register + */ +typedef union { + struct { + /** fhn_clr_ost : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ + uint32_t fhn_clr_ost:1; + /** fhn_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ + uint32_t fhn_cbcpulse:2; + /** fhn_force_cbc : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ + uint32_t fhn_force_cbc:1; + /** fhn_force_ost : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ + uint32_t fhn_force_ost:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_fhn_cfg1_reg_t; + +/** Type of fhn_status register + * Fault events status register + */ +typedef union { + struct { + /** fhn_cbc_on : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ + uint32_t fhn_cbc_on:1; + /** fhn_ost_on : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ + uint32_t fhn_ost_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mcpwm_fhn_status_reg_t; + + +/** Group: fault det */ +/** Type of fault_detect register + * Fault detection configuration and status register + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + */ + uint32_t f0_en:1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + */ + uint32_t f1_en:1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + */ + uint32_t f2_en:1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f0_pole:1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f1_pole:1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f2_pole:1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + */ + uint32_t event_f0:1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + */ + uint32_t event_f1:1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + */ + uint32_t event_f2:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: sync */ +/** Type of cap_timer_cfg register + * Capture timer configuration register + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + */ + uint32_t cap_timer_en:1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + */ + uint32_t cap_synci_en:1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input.\\0: None\\1: Timer0 + * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: + * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + */ + uint32_t cap_synci_sel:3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: + * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with + * value in phase register + */ + uint32_t cap_sync_sw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + + +/** Group: phase */ +/** Type of cap_timer_phase register + * Capture timer sync phase register + */ +typedef union { + struct { + /** cap_phase : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ + uint32_t cap_phase:32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + + +/** Group: cap_cfg */ +/** Type of cap_chn_cfg register + * Capture channel n configuration register + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable + */ + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel n after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAPn. Prescale value = + * PWM_CAPn_PRESCALE + 1 + */ + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel n + */ + uint32_t capn_sw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + + +/** Group: cap_ch */ +/** Type of cap_chn register + * CAPn capture value register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAPn + */ + uint32_t capn_value:32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + + +/** Group: edge */ +/** Type of cap_status register + * Last capture trigger edge information register + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + */ + uint32_t cap0_edge:1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + */ + uint32_t cap1_edge:1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + */ + uint32_t cap2_edge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: update */ +/** Type of update_cfg register + * Generator Update configuration register + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module.\\0: Disable\\1: Enable + */ + uint32_t global_up_en:1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ + uint32_t global_force_up:1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op0_up_en:1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ + uint32_t op0_force_up:1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op1_up_en:1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ + uint32_t op1_force_up:1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op2_up_en:1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ + uint32_t op2_force_up:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: Interrupt register */ +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena:1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena:1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena:1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena:1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena:1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena:1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena:1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena:1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena:1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_ena:1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_ena:1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_ena:1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_ena:1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_ena:1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_ena:1; + /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ + uint32_t cmpr0_tea_int_ena:1; + /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ + uint32_t cmpr1_tea_int_ena:1; + /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ + uint32_t cmpr2_tea_int_ena:1; + /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ + uint32_t cmpr0_teb_int_ena:1; + /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ + uint32_t cmpr1_teb_int_ena:1; + /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ + uint32_t cmpr2_teb_int_ena:1; + /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ + uint32_t tz0_cbc_int_ena:1; + /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ + uint32_t tz1_cbc_int_ena:1; + /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ + uint32_t tz2_cbc_int_ena:1; + /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_ena:1; + /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_ena:1; + /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_ena:1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_ena:1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_ena:1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ + uint32_t timer0_stop_int_raw:1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ + uint32_t timer1_stop_int_raw:1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ + uint32_t timer2_stop_int_raw:1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ + uint32_t timer0_tez_int_raw:1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ + uint32_t timer1_tez_int_raw:1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ + uint32_t timer2_tez_int_raw:1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ + uint32_t timer0_tep_int_raw:1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ + uint32_t timer1_tep_int_raw:1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ + uint32_t timer2_tep_int_raw:1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ + uint32_t fault0_int_raw:1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ + uint32_t fault1_int_raw:1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ + uint32_t fault2_int_raw:1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ + uint32_t fault0_clr_int_raw:1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ + uint32_t fault1_clr_int_raw:1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ + uint32_t fault2_clr_int_raw:1; + /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_raw:1; + /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_raw:1; + /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_raw:1; + /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_raw:1; + /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_raw:1; + /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_raw:1; + /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_raw:1; + /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_raw:1; + /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_raw:1; + /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ + uint32_t tz0_ost_int_raw:1; + /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ + uint32_t tz1_ost_int_raw:1; + /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ + uint32_t tz2_ost_int_raw:1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ + uint32_t cap0_int_raw:1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ + uint32_t cap1_int_raw:1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ + uint32_t cap2_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ + uint32_t timer0_stop_int_st:1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ + uint32_t timer1_stop_int_st:1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ + uint32_t timer2_stop_int_st:1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st:1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st:1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st:1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ + uint32_t timer0_tep_int_st:1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ + uint32_t timer1_tep_int_st:1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ + uint32_t timer2_tep_int_st:1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ + uint32_t fault0_int_st:1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ + uint32_t fault1_int_st:1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ + uint32_t fault2_int_st:1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ + uint32_t fault0_clr_int_st:1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ + uint32_t fault1_clr_int_st:1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ + uint32_t fault2_clr_int_st:1; + /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_st:1; + /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_st:1; + /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_st:1; + /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_st:1; + /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_st:1; + /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_st:1; + /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_st:1; + /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_st:1; + /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_st:1; + /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_st:1; + /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_st:1; + /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_st:1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ + uint32_t cap0_int_st:1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ + uint32_t cap1_int_st:1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ + uint32_t cap2_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr:1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr:1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr:1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr:1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr:1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr:1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr:1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr:1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr:1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_clr:1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_clr:1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_clr:1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_clr:1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_clr:1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_clr:1; + /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_clr:1; + /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_clr:1; + /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_clr:1; + /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_clr:1; + /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_clr:1; + /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_clr:1; + /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t tz0_cbc_int_clr:1; + /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t tz1_cbc_int_clr:1; + /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t tz2_cbc_int_clr:1; + /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_clr:1; + /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_clr:1; + /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_clr:1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_clr:1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_clr:1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: etm */ +/** Type of evt_en register + * Event enable register + */ +typedef union { + struct { + /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer0_stop_en:1; + /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer1_stop_en:1; + /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer2_stop_en:1; + /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer0_tez_en:1; + /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer1_tez_en:1; + /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer2_tez_en:1; + /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer0_tep_en:1; + /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer1_tep_en:1; + /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer2_tep_en:1; + /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tea_en:1; + /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tea_en:1; + /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tea_en:1; + /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_teb_en:1; + /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_teb_en:1; + /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_teb_en:1; + /** evt_f0_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f0_en:1; + /** evt_f1_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f1_en:1; + /** evt_f2_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f2_en:1; + /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f0_clr_en:1; + /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f1_clr_en:1; + /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f2_clr_en:1; + /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz0_cbc_en:1; + /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz1_cbc_en:1; + /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz2_cbc_en:1; + /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz0_ost_en:1; + /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz1_ost_en:1; + /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz2_ost_en:1; + /** evt_cap0_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap0_en:1; + /** evt_cap1_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap1_en:1; + /** evt_cap2_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap2_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_evt_en_reg_t; + +/** Type of task_en register + * Task enable register + */ +typedef union { + struct { + /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr0_a_up_en:1; + /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr1_a_up_en:1; + /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr2_a_up_en:1; + /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr0_b_up_en:1; + /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr1_b_up_en:1; + /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr2_b_up_en:1; + /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_gen_stop_en:1; + /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_sync_en:1; + /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_sync_en:1; + /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_sync_en:1; + /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer0_period_up_en:1; + /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer1_period_up_en:1; + /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer2_period_up_en:1; + /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz0_ost_en:1; + /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz1_ost_en:1; + /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz2_ost_en:1; + /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr0_ost_en:1; + /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr1_ost_en:1; + /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr2_ost_en:1; + /** task_cap0_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap0_en:1; + /** task_cap1_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap1_en:1; + /** task_cap2_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap2_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} mcpwm_task_en_reg_t; + +/** Type of evt_en2 register + * Event enable register2 + */ +typedef union { + struct { + /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tee1_en:1; + /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tee1_en:1; + /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tee1_en:1; + /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tee2_en:1; + /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tee2_en:1; + /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tee2_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_evt_en2_reg_t; + + +/** Group: tstmp */ +/** Type of opn_tstmp_e1 register + * Generatorn timer stamp E1 value register + */ +typedef union { + struct { + /** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E1 value register + */ + uint32_t opn_tstmp_e1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_opn_tstmp_e1_reg_t; + +/** Type of opn_tstmp_e2 register + * Generatorn timer stamp E2 value register + */ +typedef union { + struct { + /** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E2 value register + */ + uint32_t opn_tstmp_e2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_opn_tstmp_e2_reg_t; + +/** Type of clk register + * Global configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mcpwm_version_reg_t; + + +typedef struct mcpwm_dev_t { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timern_cfg0_reg_t timer0_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer0_cfg1; + volatile mcpwm_timern_sync_reg_t timer0_sync; + volatile mcpwm_timern_status_reg_t timer0_status; + volatile mcpwm_timern_cfg0_reg_t timer1_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer1_cfg1; + volatile mcpwm_timern_sync_reg_t timer1_sync; + volatile mcpwm_timern_status_reg_t timer1_status; + volatile mcpwm_timern_cfg0_reg_t timer2_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer2_cfg1; + volatile mcpwm_timern_sync_reg_t timer2_sync; + volatile mcpwm_timern_status_reg_t timer2_status; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen0_cfg0; + volatile mcpwm_genn_force_reg_t gen0_force; + volatile mcpwm_genn_a_reg_t gen0_a; + volatile mcpwm_genn_b_reg_t gen0_b; + volatile mcpwm_dtn_cfg_reg_t dt0_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier0_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1; + volatile mcpwm_fhn_status_reg_t fh0_status; + volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen1_cfg0; + volatile mcpwm_genn_force_reg_t gen1_force; + volatile mcpwm_genn_a_reg_t gen1_a; + volatile mcpwm_genn_b_reg_t gen1_b; + volatile mcpwm_dtn_cfg_reg_t dt1_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier1_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1; + volatile mcpwm_fhn_status_reg_t fh1_status; + volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen2_cfg0; + volatile mcpwm_genn_force_reg_t gen2_force; + volatile mcpwm_genn_a_reg_t gen2_a; + volatile mcpwm_genn_b_reg_t gen2_b; + volatile mcpwm_dtn_cfg_reg_t dt2_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier2_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1; + volatile mcpwm_fhn_status_reg_t fh2_status; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_evt_en_reg_t evt_en; + volatile mcpwm_task_en_reg_t task_en; + volatile mcpwm_evt_en2_reg_t evt_en2; + volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2; + volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2; + volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/include/soc/mem_monitor_reg.h new file mode 100644 index 00000000000..acda025df21 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mem_monitor_reg.h @@ -0,0 +1,184 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MEM_MONITOR_LOG_SETTING_REG register + * log config regsiter + */ +#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) +/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0; + * enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA + */ +#define MEM_MONITOR_LOG_ENA 0x00000007U +#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S) +#define MEM_MONITOR_LOG_ENA_V 0x00000007U +#define MEM_MONITOR_LOG_ENA_S 0 +/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0; + * Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE + * monitor + */ +#define MEM_MONITOR_LOG_MODE 0x0000000FU +#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) +#define MEM_MONITOR_LOG_MODE_V 0x0000000FU +#define MEM_MONITOR_LOG_MODE_S 3 +/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7)) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7 + +/** MEM_MONITOR_LOG_CHECK_DATA_REG register + * check data regsiter + */ +#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4) +/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ +#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S) +#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_S 0 + +/** MEM_MONITOR_LOG_DATA_MASK_REG register + * check data mask register + */ +#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8) +/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ +#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) +#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_S 0 + +/** MEM_MONITOR_LOG_MIN_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc) +/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ +#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S) +#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_S 0 + +/** MEM_MONITOR_LOG_MAX_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10) +/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ +#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S) +#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_S 0 + +/** MEM_MONITOR_LOG_MEM_START_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14) +/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S) +#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_S 0 + +/** MEM_MONITOR_LOG_MEM_END_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18) +/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S) +#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_S 0 + +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register + * current writing address. + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S) +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 + +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register + * writing address update + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20) +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 + +/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register + * full flag status register + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24) +/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 +/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 + +/** MEM_MONITOR_CLOCK_GATE_REG register + * clock gate force on register + */ +#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28) +/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ +#define MEM_MONITOR_CLK_EN (BIT(0)) +#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) +#define MEM_MONITOR_CLK_EN_V 0x00000001U +#define MEM_MONITOR_CLK_EN_S 0 + +/** MEM_MONITOR_DATE_REG register + * version register + */ +#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc) +/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34632336; + * version register + */ +#define MEM_MONITOR_DATE 0x0FFFFFFFU +#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S) +#define MEM_MONITOR_DATE_V 0x0FFFFFFFU +#define MEM_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/include/soc/mem_monitor_struct.h new file mode 100644 index 00000000000..51f731b5ec5 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mem_monitor_struct.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of log_setting register + * log config regsiter + */ +typedef union { + struct { + /** log_ena : R/W; bitpos: [2:0]; default: 0; + * enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA + */ + uint32_t log_ena:3; + /** log_mode : R/W; bitpos: [6:3]; default: 0; + * Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE + * monitor + */ + uint32_t log_mode:4; + /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ + uint32_t log_mem_loop_enable:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mem_monitor_log_setting_reg_t; + +/** Type of log_check_data register + * check data regsiter + */ +typedef union { + struct { + /** log_check_data : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ + uint32_t log_check_data:32; + }; + uint32_t val; +} mem_monitor_log_check_data_reg_t; + +/** Type of log_data_mask register + * check data mask register + */ +typedef union { + struct { + /** log_data_mask : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ + uint32_t log_data_mask:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} mem_monitor_log_data_mask_reg_t; + +/** Type of log_min register + * log boundary regsiter + */ +typedef union { + struct { + /** log_min : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ + uint32_t log_min:32; + }; + uint32_t val; +} mem_monitor_log_min_reg_t; + +/** Type of log_max register + * log boundary regsiter + */ +typedef union { + struct { + /** log_max : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ + uint32_t log_max:32; + }; + uint32_t val; +} mem_monitor_log_max_reg_t; + +/** Type of log_mem_start register + * log message store range register + */ +typedef union { + struct { + /** log_mem_start : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ + uint32_t log_mem_start:32; + }; + uint32_t val; +} mem_monitor_log_mem_start_reg_t; + +/** Type of log_mem_end register + * log message store range register + */ +typedef union { + struct { + /** log_mem_end : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ + uint32_t log_mem_end:32; + }; + uint32_t val; +} mem_monitor_log_mem_end_reg_t; + +/** Type of log_mem_current_addr register + * current writing address. + */ +typedef union { + struct { + /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ + uint32_t log_mem_current_addr:32; + }; + uint32_t val; +} mem_monitor_log_mem_current_addr_reg_t; + +/** Type of log_mem_addr_update register + * writing address update + */ +typedef union { + struct { + /** log_mem_addr_update : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ + uint32_t log_mem_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_log_mem_addr_update_reg_t; + +/** Type of log_mem_full_flag register + * full flag status register + */ +typedef union { + struct { + /** log_mem_full_flag : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ + uint32_t log_mem_full_flag:1; + /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ + uint32_t clr_log_mem_full_flag:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mem_monitor_log_mem_full_flag_reg_t; + + +/** Group: clk register */ +/** Type of clock_gate register + * clock gate force on register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_clock_gate_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34632336; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mem_monitor_date_reg_t; + + +typedef struct mem_monitor_dev_t { + volatile mem_monitor_log_setting_reg_t log_setting; + volatile mem_monitor_log_check_data_reg_t log_check_data; + volatile mem_monitor_log_data_mask_reg_t log_data_mask; + volatile mem_monitor_log_min_reg_t log_min; + volatile mem_monitor_log_max_reg_t log_max; + volatile mem_monitor_log_mem_start_reg_t log_mem_start; + volatile mem_monitor_log_mem_end_reg_t log_mem_end; + volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr; + volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update; + volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag; + volatile mem_monitor_clock_gate_reg_t clock_gate; + uint32_t reserved_02c[244]; + volatile mem_monitor_date_reg_t date; +} mem_monitor_dev_t; + +extern mem_monitor_dev_t MEM_MONITOR; + +#ifndef __cplusplus +_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/otp_debug_reg.h b/components/soc/esp32c5/include/soc/otp_debug_reg.h new file mode 100644 index 00000000000..7dfe5342f8c --- /dev/null +++ b/components/soc/esp32c5/include/soc/otp_debug_reg.h @@ -0,0 +1,1600 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** OTP_DEBUG_WR_DIS_REG register + * Otp debuger block0 data register1. + */ +#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0) +/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ +#define OTP_DEBUG_BLOCK0_WR_DIS 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_WR_DIS_M (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S) +#define OTP_DEBUG_BLOCK0_WR_DIS_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_WR_DIS_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register + * Otp debuger block0 data register2. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4) +/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register + * Otp debuger block0 data register3. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8) +/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register + * Otp debuger block0 data register4. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc) +/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register + * Otp debuger block0 data register5. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10) +/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register + * Otp debuger block0 data register6. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14) +/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register + * Otp debuger block0 data register7. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18) +/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register + * Otp debuger block0 data register8. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c) +/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register + * Otp debuger block0 data register9. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20) +/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register + * Otp debuger block0 data register10. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24) +/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register + * Otp debuger block0 data register11. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28) +/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register + * Otp debuger block0 data register12. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c) +/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register + * Otp debuger block0 data register13. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30) +/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register + * Otp debuger block0 data register14. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34) +/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register + * Otp debuger block0 data register15. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38) +/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register + * Otp debuger block0 data register16. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c) +/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register + * Otp debuger block0 data register17. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40) +/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register + * Otp debuger block0 data register18. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44) +/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register + * Otp debuger block0 data register19. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48) +/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register + * Otp debuger block0 data register20. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c) +/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register + * Otp debuger block0 data register21. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50) +/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S 0 + +/** OTP_DEBUG_BLK1_W1_REG register + * Otp debuger block1 data register1. + */ +#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54) +/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ +#define OTP_DEBUG_BLOCK1_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W1_M (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S) +#define OTP_DEBUG_BLOCK1_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W1_S 0 + +/** OTP_DEBUG_BLK1_W2_REG register + * Otp debuger block1 data register2. + */ +#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58) +/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ +#define OTP_DEBUG_BLOCK1_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W2_M (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S) +#define OTP_DEBUG_BLOCK1_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W2_S 0 + +/** OTP_DEBUG_BLK1_W3_REG register + * Otp debuger block1 data register3. + */ +#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c) +/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ +#define OTP_DEBUG_BLOCK1_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W3_M (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S) +#define OTP_DEBUG_BLOCK1_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W3_S 0 + +/** OTP_DEBUG_BLK1_W4_REG register + * Otp debuger block1 data register4. + */ +#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60) +/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ +#define OTP_DEBUG_BLOCK1_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W4_M (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S) +#define OTP_DEBUG_BLOCK1_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W4_S 0 + +/** OTP_DEBUG_BLK1_W5_REG register + * Otp debuger block1 data register5. + */ +#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64) +/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ +#define OTP_DEBUG_BLOCK1_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W5_M (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S) +#define OTP_DEBUG_BLOCK1_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W5_S 0 + +/** OTP_DEBUG_BLK1_W6_REG register + * Otp debuger block1 data register6. + */ +#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68) +/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ +#define OTP_DEBUG_BLOCK1_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W6_M (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S) +#define OTP_DEBUG_BLOCK1_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W6_S 0 + +/** OTP_DEBUG_BLK1_W7_REG register + * Otp debuger block1 data register7. + */ +#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c) +/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ +#define OTP_DEBUG_BLOCK1_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W7_M (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S) +#define OTP_DEBUG_BLOCK1_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W7_S 0 + +/** OTP_DEBUG_BLK1_W8_REG register + * Otp debuger block1 data register8. + */ +#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70) +/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ +#define OTP_DEBUG_BLOCK1_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W8_M (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S) +#define OTP_DEBUG_BLOCK1_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W8_S 0 + +/** OTP_DEBUG_BLK1_W9_REG register + * Otp debuger block1 data register9. + */ +#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74) +/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ +#define OTP_DEBUG_BLOCK1_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W9_M (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S) +#define OTP_DEBUG_BLOCK1_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W9_S 0 + +/** OTP_DEBUG_BLK2_W1_REG register + * Otp debuger block2 data register1. + */ +#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78) +/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ +#define OTP_DEBUG_BLOCK2_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W1_M (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S) +#define OTP_DEBUG_BLOCK2_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W1_S 0 + +/** OTP_DEBUG_BLK2_W2_REG register + * Otp debuger block2 data register2. + */ +#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c) +/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ +#define OTP_DEBUG_BLOCK2_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W2_M (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S) +#define OTP_DEBUG_BLOCK2_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W2_S 0 + +/** OTP_DEBUG_BLK2_W3_REG register + * Otp debuger block2 data register3. + */ +#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80) +/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ +#define OTP_DEBUG_BLOCK2_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W3_M (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S) +#define OTP_DEBUG_BLOCK2_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W3_S 0 + +/** OTP_DEBUG_BLK2_W4_REG register + * Otp debuger block2 data register4. + */ +#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84) +/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ +#define OTP_DEBUG_BLOCK2_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W4_M (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S) +#define OTP_DEBUG_BLOCK2_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W4_S 0 + +/** OTP_DEBUG_BLK2_W5_REG register + * Otp debuger block2 data register5. + */ +#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88) +/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ +#define OTP_DEBUG_BLOCK2_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W5_M (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S) +#define OTP_DEBUG_BLOCK2_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W5_S 0 + +/** OTP_DEBUG_BLK2_W6_REG register + * Otp debuger block2 data register6. + */ +#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c) +/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ +#define OTP_DEBUG_BLOCK2_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W6_M (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S) +#define OTP_DEBUG_BLOCK2_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W6_S 0 + +/** OTP_DEBUG_BLK2_W7_REG register + * Otp debuger block2 data register7. + */ +#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90) +/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ +#define OTP_DEBUG_BLOCK2_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W7_M (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S) +#define OTP_DEBUG_BLOCK2_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W7_S 0 + +/** OTP_DEBUG_BLK2_W8_REG register + * Otp debuger block2 data register8. + */ +#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94) +/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ +#define OTP_DEBUG_BLOCK2_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W8_M (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S) +#define OTP_DEBUG_BLOCK2_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W8_S 0 + +/** OTP_DEBUG_BLK2_W9_REG register + * Otp debuger block2 data register9. + */ +#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98) +/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ +#define OTP_DEBUG_BLOCK2_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W9_M (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S) +#define OTP_DEBUG_BLOCK2_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W9_S 0 + +/** OTP_DEBUG_BLK2_W10_REG register + * Otp debuger block2 data register10. + */ +#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c) +/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ +#define OTP_DEBUG_BLOCK2_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W10_M (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S) +#define OTP_DEBUG_BLOCK2_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W10_S 0 + +/** OTP_DEBUG_BLK2_W11_REG register + * Otp debuger block2 data register11. + */ +#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0) +/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ +#define OTP_DEBUG_BLOCK2_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W11_M (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S) +#define OTP_DEBUG_BLOCK2_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W11_S 0 + +/** OTP_DEBUG_BLK3_W1_REG register + * Otp debuger block3 data register1. + */ +#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4) +/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ +#define OTP_DEBUG_BLOCK3_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W1_M (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S) +#define OTP_DEBUG_BLOCK3_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W1_S 0 + +/** OTP_DEBUG_BLK3_W2_REG register + * Otp debuger block3 data register2. + */ +#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8) +/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ +#define OTP_DEBUG_BLOCK3_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W2_M (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S) +#define OTP_DEBUG_BLOCK3_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W2_S 0 + +/** OTP_DEBUG_BLK3_W3_REG register + * Otp debuger block3 data register3. + */ +#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac) +/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ +#define OTP_DEBUG_BLOCK3_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W3_M (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S) +#define OTP_DEBUG_BLOCK3_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W3_S 0 + +/** OTP_DEBUG_BLK3_W4_REG register + * Otp debuger block3 data register4. + */ +#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0) +/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ +#define OTP_DEBUG_BLOCK3_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W4_M (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S) +#define OTP_DEBUG_BLOCK3_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W4_S 0 + +/** OTP_DEBUG_BLK3_W5_REG register + * Otp debuger block3 data register5. + */ +#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4) +/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ +#define OTP_DEBUG_BLOCK3_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W5_M (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S) +#define OTP_DEBUG_BLOCK3_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W5_S 0 + +/** OTP_DEBUG_BLK3_W6_REG register + * Otp debuger block3 data register6. + */ +#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8) +/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ +#define OTP_DEBUG_BLOCK3_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W6_M (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S) +#define OTP_DEBUG_BLOCK3_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W6_S 0 + +/** OTP_DEBUG_BLK3_W7_REG register + * Otp debuger block3 data register7. + */ +#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc) +/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ +#define OTP_DEBUG_BLOCK3_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W7_M (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S) +#define OTP_DEBUG_BLOCK3_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W7_S 0 + +/** OTP_DEBUG_BLK3_W8_REG register + * Otp debuger block3 data register8. + */ +#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0) +/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ +#define OTP_DEBUG_BLOCK3_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W8_M (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S) +#define OTP_DEBUG_BLOCK3_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W8_S 0 + +/** OTP_DEBUG_BLK3_W9_REG register + * Otp debuger block3 data register9. + */ +#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4) +/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ +#define OTP_DEBUG_BLOCK3_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W9_M (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S) +#define OTP_DEBUG_BLOCK3_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W9_S 0 + +/** OTP_DEBUG_BLK3_W10_REG register + * Otp debuger block3 data register10. + */ +#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8) +/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ +#define OTP_DEBUG_BLOCK3_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W10_M (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S) +#define OTP_DEBUG_BLOCK3_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W10_S 0 + +/** OTP_DEBUG_BLK3_W11_REG register + * Otp debuger block3 data register11. + */ +#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc) +/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ +#define OTP_DEBUG_BLOCK3_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W11_M (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S) +#define OTP_DEBUG_BLOCK3_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W11_S 0 + +/** OTP_DEBUG_BLK4_W1_REG register + * Otp debuger block4 data register1. + */ +#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0) +/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ +#define OTP_DEBUG_BLOCK4_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W1_M (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S) +#define OTP_DEBUG_BLOCK4_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W1_S 0 + +/** OTP_DEBUG_BLK4_W2_REG register + * Otp debuger block4 data register2. + */ +#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4) +/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ +#define OTP_DEBUG_BLOCK4_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W2_M (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S) +#define OTP_DEBUG_BLOCK4_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W2_S 0 + +/** OTP_DEBUG_BLK4_W3_REG register + * Otp debuger block4 data register3. + */ +#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8) +/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ +#define OTP_DEBUG_BLOCK4_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W3_M (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S) +#define OTP_DEBUG_BLOCK4_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W3_S 0 + +/** OTP_DEBUG_BLK4_W4_REG register + * Otp debuger block4 data register4. + */ +#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc) +/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ +#define OTP_DEBUG_BLOCK4_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W4_M (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S) +#define OTP_DEBUG_BLOCK4_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W4_S 0 + +/** OTP_DEBUG_BLK4_W5_REG register + * Otp debuger block4 data register5. + */ +#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0) +/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ +#define OTP_DEBUG_BLOCK4_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W5_M (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S) +#define OTP_DEBUG_BLOCK4_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W5_S 0 + +/** OTP_DEBUG_BLK4_W6_REG register + * Otp debuger block4 data register6. + */ +#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4) +/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ +#define OTP_DEBUG_BLOCK4_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W6_M (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S) +#define OTP_DEBUG_BLOCK4_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W6_S 0 + +/** OTP_DEBUG_BLK4_W7_REG register + * Otp debuger block4 data register7. + */ +#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8) +/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ +#define OTP_DEBUG_BLOCK4_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W7_M (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S) +#define OTP_DEBUG_BLOCK4_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W7_S 0 + +/** OTP_DEBUG_BLK4_W8_REG register + * Otp debuger block4 data register8. + */ +#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec) +/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ +#define OTP_DEBUG_BLOCK4_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W8_M (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S) +#define OTP_DEBUG_BLOCK4_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W8_S 0 + +/** OTP_DEBUG_BLK4_W9_REG register + * Otp debuger block4 data register9. + */ +#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0) +/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ +#define OTP_DEBUG_BLOCK4_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W9_M (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S) +#define OTP_DEBUG_BLOCK4_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W9_S 0 + +/** OTP_DEBUG_BLK4_W10_REG register + * Otp debuger block4 data registe10. + */ +#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4) +/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ +#define OTP_DEBUG_BLOCK4_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W10_M (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S) +#define OTP_DEBUG_BLOCK4_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W10_S 0 + +/** OTP_DEBUG_BLK4_W11_REG register + * Otp debuger block4 data register11. + */ +#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8) +/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ +#define OTP_DEBUG_BLOCK4_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W11_M (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S) +#define OTP_DEBUG_BLOCK4_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W11_S 0 + +/** OTP_DEBUG_BLK5_W1_REG register + * Otp debuger block5 data register1. + */ +#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc) +/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ +#define OTP_DEBUG_BLOCK5_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W1_M (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S) +#define OTP_DEBUG_BLOCK5_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W1_S 0 + +/** OTP_DEBUG_BLK5_W2_REG register + * Otp debuger block5 data register2. + */ +#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100) +/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ +#define OTP_DEBUG_BLOCK5_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W2_M (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S) +#define OTP_DEBUG_BLOCK5_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W2_S 0 + +/** OTP_DEBUG_BLK5_W3_REG register + * Otp debuger block5 data register3. + */ +#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104) +/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ +#define OTP_DEBUG_BLOCK5_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W3_M (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S) +#define OTP_DEBUG_BLOCK5_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W3_S 0 + +/** OTP_DEBUG_BLK5_W4_REG register + * Otp debuger block5 data register4. + */ +#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108) +/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ +#define OTP_DEBUG_BLOCK5_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W4_M (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S) +#define OTP_DEBUG_BLOCK5_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W4_S 0 + +/** OTP_DEBUG_BLK5_W5_REG register + * Otp debuger block5 data register5. + */ +#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c) +/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ +#define OTP_DEBUG_BLOCK5_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W5_M (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S) +#define OTP_DEBUG_BLOCK5_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W5_S 0 + +/** OTP_DEBUG_BLK5_W6_REG register + * Otp debuger block5 data register6. + */ +#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110) +/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ +#define OTP_DEBUG_BLOCK5_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W6_M (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S) +#define OTP_DEBUG_BLOCK5_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W6_S 0 + +/** OTP_DEBUG_BLK5_W7_REG register + * Otp debuger block5 data register7. + */ +#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114) +/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ +#define OTP_DEBUG_BLOCK5_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W7_M (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S) +#define OTP_DEBUG_BLOCK5_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W7_S 0 + +/** OTP_DEBUG_BLK5_W8_REG register + * Otp debuger block5 data register8. + */ +#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118) +/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ +#define OTP_DEBUG_BLOCK5_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W8_M (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S) +#define OTP_DEBUG_BLOCK5_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W8_S 0 + +/** OTP_DEBUG_BLK5_W9_REG register + * Otp debuger block5 data register9. + */ +#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c) +/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ +#define OTP_DEBUG_BLOCK5_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W9_M (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S) +#define OTP_DEBUG_BLOCK5_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W9_S 0 + +/** OTP_DEBUG_BLK5_W10_REG register + * Otp debuger block5 data register10. + */ +#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120) +/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ +#define OTP_DEBUG_BLOCK5_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W10_M (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S) +#define OTP_DEBUG_BLOCK5_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W10_S 0 + +/** OTP_DEBUG_BLK5_W11_REG register + * Otp debuger block5 data register11. + */ +#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124) +/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ +#define OTP_DEBUG_BLOCK5_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W11_M (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S) +#define OTP_DEBUG_BLOCK5_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W11_S 0 + +/** OTP_DEBUG_BLK6_W1_REG register + * Otp debuger block6 data register1. + */ +#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128) +/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ +#define OTP_DEBUG_BLOCK6_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W1_M (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S) +#define OTP_DEBUG_BLOCK6_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W1_S 0 + +/** OTP_DEBUG_BLK6_W2_REG register + * Otp debuger block6 data register2. + */ +#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c) +/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ +#define OTP_DEBUG_BLOCK6_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W2_M (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S) +#define OTP_DEBUG_BLOCK6_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W2_S 0 + +/** OTP_DEBUG_BLK6_W3_REG register + * Otp debuger block6 data register3. + */ +#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130) +/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ +#define OTP_DEBUG_BLOCK6_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W3_M (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S) +#define OTP_DEBUG_BLOCK6_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W3_S 0 + +/** OTP_DEBUG_BLK6_W4_REG register + * Otp debuger block6 data register4. + */ +#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134) +/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ +#define OTP_DEBUG_BLOCK6_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W4_M (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S) +#define OTP_DEBUG_BLOCK6_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W4_S 0 + +/** OTP_DEBUG_BLK6_W5_REG register + * Otp debuger block6 data register5. + */ +#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138) +/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ +#define OTP_DEBUG_BLOCK6_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W5_M (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S) +#define OTP_DEBUG_BLOCK6_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W5_S 0 + +/** OTP_DEBUG_BLK6_W6_REG register + * Otp debuger block6 data register6. + */ +#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c) +/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ +#define OTP_DEBUG_BLOCK6_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W6_M (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S) +#define OTP_DEBUG_BLOCK6_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W6_S 0 + +/** OTP_DEBUG_BLK6_W7_REG register + * Otp debuger block6 data register7. + */ +#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140) +/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ +#define OTP_DEBUG_BLOCK6_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W7_M (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S) +#define OTP_DEBUG_BLOCK6_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W7_S 0 + +/** OTP_DEBUG_BLK6_W8_REG register + * Otp debuger block6 data register8. + */ +#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144) +/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ +#define OTP_DEBUG_BLOCK6_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W8_M (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S) +#define OTP_DEBUG_BLOCK6_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W8_S 0 + +/** OTP_DEBUG_BLK6_W9_REG register + * Otp debuger block6 data register9. + */ +#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148) +/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ +#define OTP_DEBUG_BLOCK6_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W9_M (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S) +#define OTP_DEBUG_BLOCK6_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W9_S 0 + +/** OTP_DEBUG_BLK6_W10_REG register + * Otp debuger block6 data register10. + */ +#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c) +/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ +#define OTP_DEBUG_BLOCK6_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W10_M (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S) +#define OTP_DEBUG_BLOCK6_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W10_S 0 + +/** OTP_DEBUG_BLK6_W11_REG register + * Otp debuger block6 data register11. + */ +#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150) +/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ +#define OTP_DEBUG_BLOCK6_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W11_M (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S) +#define OTP_DEBUG_BLOCK6_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W11_S 0 + +/** OTP_DEBUG_BLK7_W1_REG register + * Otp debuger block7 data register1. + */ +#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154) +/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ +#define OTP_DEBUG_BLOCK7_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W1_M (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S) +#define OTP_DEBUG_BLOCK7_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W1_S 0 + +/** OTP_DEBUG_BLK7_W2_REG register + * Otp debuger block7 data register2. + */ +#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158) +/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ +#define OTP_DEBUG_BLOCK7_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W2_M (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S) +#define OTP_DEBUG_BLOCK7_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W2_S 0 + +/** OTP_DEBUG_BLK7_W3_REG register + * Otp debuger block7 data register3. + */ +#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c) +/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ +#define OTP_DEBUG_BLOCK7_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W3_M (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S) +#define OTP_DEBUG_BLOCK7_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W3_S 0 + +/** OTP_DEBUG_BLK7_W4_REG register + * Otp debuger block7 data register4. + */ +#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160) +/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ +#define OTP_DEBUG_BLOCK7_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W4_M (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S) +#define OTP_DEBUG_BLOCK7_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W4_S 0 + +/** OTP_DEBUG_BLK7_W5_REG register + * Otp debuger block7 data register5. + */ +#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164) +/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ +#define OTP_DEBUG_BLOCK7_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W5_M (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S) +#define OTP_DEBUG_BLOCK7_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W5_S 0 + +/** OTP_DEBUG_BLK7_W6_REG register + * Otp debuger block7 data register6. + */ +#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168) +/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ +#define OTP_DEBUG_BLOCK7_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W6_M (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S) +#define OTP_DEBUG_BLOCK7_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W6_S 0 + +/** OTP_DEBUG_BLK7_W7_REG register + * Otp debuger block7 data register7. + */ +#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c) +/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ +#define OTP_DEBUG_BLOCK7_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W7_M (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S) +#define OTP_DEBUG_BLOCK7_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W7_S 0 + +/** OTP_DEBUG_BLK7_W8_REG register + * Otp debuger block7 data register8. + */ +#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170) +/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ +#define OTP_DEBUG_BLOCK7_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W8_M (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S) +#define OTP_DEBUG_BLOCK7_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W8_S 0 + +/** OTP_DEBUG_BLK7_W9_REG register + * Otp debuger block7 data register9. + */ +#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174) +/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ +#define OTP_DEBUG_BLOCK7_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W9_M (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S) +#define OTP_DEBUG_BLOCK7_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W9_S 0 + +/** OTP_DEBUG_BLK7_W10_REG register + * Otp debuger block7 data register10. + */ +#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178) +/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ +#define OTP_DEBUG_BLOCK7_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W10_M (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S) +#define OTP_DEBUG_BLOCK7_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W10_S 0 + +/** OTP_DEBUG_BLK7_W11_REG register + * Otp debuger block7 data register11. + */ +#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c) +/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ +#define OTP_DEBUG_BLOCK7_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W11_M (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S) +#define OTP_DEBUG_BLOCK7_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W11_S 0 + +/** OTP_DEBUG_BLK8_W1_REG register + * Otp debuger block8 data register1. + */ +#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180) +/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ +#define OTP_DEBUG_BLOCK8_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W1_M (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S) +#define OTP_DEBUG_BLOCK8_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W1_S 0 + +/** OTP_DEBUG_BLK8_W2_REG register + * Otp debuger block8 data register2. + */ +#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184) +/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ +#define OTP_DEBUG_BLOCK8_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W2_M (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S) +#define OTP_DEBUG_BLOCK8_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W2_S 0 + +/** OTP_DEBUG_BLK8_W3_REG register + * Otp debuger block8 data register3. + */ +#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188) +/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ +#define OTP_DEBUG_BLOCK8_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W3_M (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S) +#define OTP_DEBUG_BLOCK8_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W3_S 0 + +/** OTP_DEBUG_BLK8_W4_REG register + * Otp debuger block8 data register4. + */ +#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c) +/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ +#define OTP_DEBUG_BLOCK8_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W4_M (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S) +#define OTP_DEBUG_BLOCK8_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W4_S 0 + +/** OTP_DEBUG_BLK8_W5_REG register + * Otp debuger block8 data register5. + */ +#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190) +/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ +#define OTP_DEBUG_BLOCK8_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W5_M (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S) +#define OTP_DEBUG_BLOCK8_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W5_S 0 + +/** OTP_DEBUG_BLK8_W6_REG register + * Otp debuger block8 data register6. + */ +#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194) +/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ +#define OTP_DEBUG_BLOCK8_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W6_M (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S) +#define OTP_DEBUG_BLOCK8_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W6_S 0 + +/** OTP_DEBUG_BLK8_W7_REG register + * Otp debuger block8 data register7. + */ +#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198) +/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ +#define OTP_DEBUG_BLOCK8_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W7_M (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S) +#define OTP_DEBUG_BLOCK8_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W7_S 0 + +/** OTP_DEBUG_BLK8_W8_REG register + * Otp debuger block8 data register8. + */ +#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c) +/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ +#define OTP_DEBUG_BLOCK8_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W8_M (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S) +#define OTP_DEBUG_BLOCK8_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W8_S 0 + +/** OTP_DEBUG_BLK8_W9_REG register + * Otp debuger block8 data register9. + */ +#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0) +/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ +#define OTP_DEBUG_BLOCK8_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W9_M (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S) +#define OTP_DEBUG_BLOCK8_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W9_S 0 + +/** OTP_DEBUG_BLK8_W10_REG register + * Otp debuger block8 data register10. + */ +#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4) +/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ +#define OTP_DEBUG_BLOCK8_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W10_M (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S) +#define OTP_DEBUG_BLOCK8_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W10_S 0 + +/** OTP_DEBUG_BLK8_W11_REG register + * Otp debuger block8 data register11. + */ +#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8) +/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ +#define OTP_DEBUG_BLOCK8_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W11_M (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S) +#define OTP_DEBUG_BLOCK8_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W11_S 0 + +/** OTP_DEBUG_BLK9_W1_REG register + * Otp debuger block9 data register1. + */ +#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac) +/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ +#define OTP_DEBUG_BLOCK9_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W1_M (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S) +#define OTP_DEBUG_BLOCK9_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W1_S 0 + +/** OTP_DEBUG_BLK9_W2_REG register + * Otp debuger block9 data register2. + */ +#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0) +/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ +#define OTP_DEBUG_BLOCK9_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W2_M (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S) +#define OTP_DEBUG_BLOCK9_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W2_S 0 + +/** OTP_DEBUG_BLK9_W3_REG register + * Otp debuger block9 data register3. + */ +#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4) +/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ +#define OTP_DEBUG_BLOCK9_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W3_M (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S) +#define OTP_DEBUG_BLOCK9_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W3_S 0 + +/** OTP_DEBUG_BLK9_W4_REG register + * Otp debuger block9 data register4. + */ +#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8) +/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ +#define OTP_DEBUG_BLOCK9_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W4_M (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S) +#define OTP_DEBUG_BLOCK9_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W4_S 0 + +/** OTP_DEBUG_BLK9_W5_REG register + * Otp debuger block9 data register5. + */ +#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc) +/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ +#define OTP_DEBUG_BLOCK9_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W5_M (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S) +#define OTP_DEBUG_BLOCK9_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W5_S 0 + +/** OTP_DEBUG_BLK9_W6_REG register + * Otp debuger block9 data register6. + */ +#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0) +/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ +#define OTP_DEBUG_BLOCK9_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W6_M (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S) +#define OTP_DEBUG_BLOCK9_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W6_S 0 + +/** OTP_DEBUG_BLK9_W7_REG register + * Otp debuger block9 data register7. + */ +#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4) +/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ +#define OTP_DEBUG_BLOCK9_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W7_M (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S) +#define OTP_DEBUG_BLOCK9_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W7_S 0 + +/** OTP_DEBUG_BLK9_W8_REG register + * Otp debuger block9 data register8. + */ +#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8) +/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ +#define OTP_DEBUG_BLOCK9_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W8_M (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S) +#define OTP_DEBUG_BLOCK9_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W8_S 0 + +/** OTP_DEBUG_BLK9_W9_REG register + * Otp debuger block9 data register9. + */ +#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc) +/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ +#define OTP_DEBUG_BLOCK9_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W9_M (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S) +#define OTP_DEBUG_BLOCK9_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W9_S 0 + +/** OTP_DEBUG_BLK9_W10_REG register + * Otp debuger block9 data register10. + */ +#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0) +/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ +#define OTP_DEBUG_BLOCK9_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W10_M (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S) +#define OTP_DEBUG_BLOCK9_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W10_S 0 + +/** OTP_DEBUG_BLK9_W11_REG register + * Otp debuger block9 data register11. + */ +#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4) +/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ +#define OTP_DEBUG_BLOCK9_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W11_M (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S) +#define OTP_DEBUG_BLOCK9_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W11_S 0 + +/** OTP_DEBUG_BLK10_W1_REG register + * Otp debuger block10 data register1. + */ +#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8) +/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ +#define OTP_DEBUG_BLOCK10_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W1_M (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S) +#define OTP_DEBUG_BLOCK10_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W1_S 0 + +/** OTP_DEBUG_BLK10_W2_REG register + * Otp debuger block10 data register2. + */ +#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc) +/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ +#define OTP_DEBUG_BLOCK10_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W2_M (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S) +#define OTP_DEBUG_BLOCK10_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W2_S 0 + +/** OTP_DEBUG_BLK10_W3_REG register + * Otp debuger block10 data register3. + */ +#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0) +/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ +#define OTP_DEBUG_BLOCK10_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W3_M (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S) +#define OTP_DEBUG_BLOCK10_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W3_S 0 + +/** OTP_DEBUG_BLK10_W4_REG register + * Otp debuger block10 data register4. + */ +#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4) +/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ +#define OTP_DEBUG_BLOCK10_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W4_M (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S) +#define OTP_DEBUG_BLOCK10_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W4_S 0 + +/** OTP_DEBUG_BLK10_W5_REG register + * Otp debuger block10 data register5. + */ +#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8) +/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ +#define OTP_DEBUG_BLOCK10_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W5_M (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S) +#define OTP_DEBUG_BLOCK10_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W5_S 0 + +/** OTP_DEBUG_BLK10_W6_REG register + * Otp debuger block10 data register6. + */ +#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec) +/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ +#define OTP_DEBUG_BLOCK10_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W6_M (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S) +#define OTP_DEBUG_BLOCK10_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W6_S 0 + +/** OTP_DEBUG_BLK10_W7_REG register + * Otp debuger block10 data register7. + */ +#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0) +/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ +#define OTP_DEBUG_BLOCK10_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W7_M (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S) +#define OTP_DEBUG_BLOCK10_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W7_S 0 + +/** OTP_DEBUG_BLK10_W8_REG register + * Otp debuger block10 data register8. + */ +#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4) +/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ +#define OTP_DEBUG_BLOCK10_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W8_M (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S) +#define OTP_DEBUG_BLOCK10_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W8_S 0 + +/** OTP_DEBUG_BLK10_W9_REG register + * Otp debuger block10 data register9. + */ +#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8) +/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ +#define OTP_DEBUG_BLOCK10_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W9_M (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S) +#define OTP_DEBUG_BLOCK10_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W9_S 0 + +/** OTP_DEBUG_BLK10_W10_REG register + * Otp debuger block10 data register10. + */ +#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc) +/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ +#define OTP_DEBUG_BLOCK19_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK19_W10_M (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S) +#define OTP_DEBUG_BLOCK19_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK19_W10_S 0 + +/** OTP_DEBUG_BLK10_W11_REG register + * Otp debuger block10 data register11. + */ +#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200) +/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ +#define OTP_DEBUG_BLOCK10_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W11_M (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S) +#define OTP_DEBUG_BLOCK10_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W11_S 0 + +/** OTP_DEBUG_CLK_REG register + * Otp debuger clk_en configuration register. + */ +#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204) +/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file. + */ +#define OTP_DEBUG_CLK_EN (BIT(0)) +#define OTP_DEBUG_CLK_EN_M (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S) +#define OTP_DEBUG_CLK_EN_V 0x00000001U +#define OTP_DEBUG_CLK_EN_S 0 + +/** OTP_DEBUG_APB2OTP_EN_REG register + * Otp_debuger apb2otp enable configuration register. + */ +#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208) +/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0; + * Debug mode enable signal. + */ +#define OTP_DEBUG_APB2OTP_EN (BIT(0)) +#define OTP_DEBUG_APB2OTP_EN_M (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S) +#define OTP_DEBUG_APB2OTP_EN_V 0x00000001U +#define OTP_DEBUG_APB2OTP_EN_S 0 + +/** OTP_DEBUG_DATE_REG register + * eFuse version register. + */ +#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c) +/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736; + * Stores otp_debug version. + */ +#define OTP_DEBUG_DATE 0x0FFFFFFFU +#define OTP_DEBUG_DATE_M (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S) +#define OTP_DEBUG_DATE_V 0x0FFFFFFFU +#define OTP_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/otp_debug_struct.h b/components/soc/esp32c5/include/soc/otp_debug_struct.h new file mode 100644 index 00000000000..6afed4ae338 --- /dev/null +++ b/components/soc/esp32c5/include/soc/otp_debug_struct.h @@ -0,0 +1,2137 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: OTP_DEBUG Block0 Write Disable Data */ +/** Type of wr_dis register + * Otp debuger block0 data register1. + */ +typedef union { + struct { + /** block0_wr_dis : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ + uint32_t block0_wr_dis:32; + }; + uint32_t val; +} otp_debug_wr_dis_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */ +/** Type of blk0_backup1_w1 register + * Otp debuger block0 data register2. + */ +typedef union { + struct { + /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ + uint32_t block0_backup1_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */ +/** Type of blk0_backup1_w2 register + * Otp debuger block0 data register3. + */ +typedef union { + struct { + /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ + uint32_t block0_backup1_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */ +/** Type of blk0_backup1_w3 register + * Otp debuger block0 data register4. + */ +typedef union { + struct { + /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ + uint32_t block0_backup1_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */ +/** Type of blk0_backup1_w4 register + * Otp debuger block0 data register5. + */ +typedef union { + struct { + /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ + uint32_t block0_backup1_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */ +/** Type of blk0_backup1_w5 register + * Otp debuger block0 data register6. + */ +typedef union { + struct { + /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ + uint32_t block0_backup1_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */ +/** Type of blk0_backup2_w1 register + * Otp debuger block0 data register7. + */ +typedef union { + struct { + /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ + uint32_t block0_backup2_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */ +/** Type of blk0_backup2_w2 register + * Otp debuger block0 data register8. + */ +typedef union { + struct { + /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ + uint32_t block0_backup2_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */ +/** Type of blk0_backup2_w3 register + * Otp debuger block0 data register9. + */ +typedef union { + struct { + /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ + uint32_t block0_backup2_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */ +/** Type of blk0_backup2_w4 register + * Otp debuger block0 data register10. + */ +typedef union { + struct { + /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ + uint32_t block0_backup2_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */ +/** Type of blk0_backup2_w5 register + * Otp debuger block0 data register11. + */ +typedef union { + struct { + /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ + uint32_t block0_backup2_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */ +/** Type of blk0_backup3_w1 register + * Otp debuger block0 data register12. + */ +typedef union { + struct { + /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ + uint32_t block0_backup3_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */ +/** Type of blk0_backup3_w2 register + * Otp debuger block0 data register13. + */ +typedef union { + struct { + /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ + uint32_t block0_backup3_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */ +/** Type of blk0_backup3_w3 register + * Otp debuger block0 data register14. + */ +typedef union { + struct { + /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ + uint32_t block0_backup3_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */ +/** Type of blk0_backup3_w4 register + * Otp debuger block0 data register15. + */ +typedef union { + struct { + /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ + uint32_t block0_backup3_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */ +/** Type of blk0_backup3_w5 register + * Otp debuger block0 data register16. + */ +typedef union { + struct { + /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ + uint32_t block0_backup3_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */ +/** Type of blk0_backup4_w1 register + * Otp debuger block0 data register17. + */ +typedef union { + struct { + /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ + uint32_t block0_backup4_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */ +/** Type of blk0_backup4_w2 register + * Otp debuger block0 data register18. + */ +typedef union { + struct { + /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ + uint32_t block0_backup4_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */ +/** Type of blk0_backup4_w3 register + * Otp debuger block0 data register19. + */ +typedef union { + struct { + /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ + uint32_t block0_backup4_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */ +/** Type of blk0_backup4_w4 register + * Otp debuger block0 data register20. + */ +typedef union { + struct { + /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ + uint32_t block0_backup4_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */ +/** Type of blk0_backup4_w5 register + * Otp debuger block0 data register21. + */ +typedef union { + struct { + /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ + uint32_t block0_backup4_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w5_reg_t; + + +/** Group: OTP_DEBUG Block1 Word1 Data */ +/** Type of blk1_w1 register + * Otp debuger block1 data register1. + */ +typedef union { + struct { + /** block1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ + uint32_t block1_w1:32; + }; + uint32_t val; +} otp_debug_blk1_w1_reg_t; + + +/** Group: OTP_DEBUG Block1 Word2 Data */ +/** Type of blk1_w2 register + * Otp debuger block1 data register2. + */ +typedef union { + struct { + /** block1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ + uint32_t block1_w2:32; + }; + uint32_t val; +} otp_debug_blk1_w2_reg_t; + + +/** Group: OTP_DEBUG Block1 Word3 Data */ +/** Type of blk1_w3 register + * Otp debuger block1 data register3. + */ +typedef union { + struct { + /** block1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ + uint32_t block1_w3:32; + }; + uint32_t val; +} otp_debug_blk1_w3_reg_t; + + +/** Group: OTP_DEBUG Block1 Word4 Data */ +/** Type of blk1_w4 register + * Otp debuger block1 data register4. + */ +typedef union { + struct { + /** block1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ + uint32_t block1_w4:32; + }; + uint32_t val; +} otp_debug_blk1_w4_reg_t; + + +/** Group: OTP_DEBUG Block1 Word5 Data */ +/** Type of blk1_w5 register + * Otp debuger block1 data register5. + */ +typedef union { + struct { + /** block1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ + uint32_t block1_w5:32; + }; + uint32_t val; +} otp_debug_blk1_w5_reg_t; + + +/** Group: OTP_DEBUG Block1 Word6 Data */ +/** Type of blk1_w6 register + * Otp debuger block1 data register6. + */ +typedef union { + struct { + /** block1_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ + uint32_t block1_w6:32; + }; + uint32_t val; +} otp_debug_blk1_w6_reg_t; + + +/** Group: OTP_DEBUG Block1 Word7 Data */ +/** Type of blk1_w7 register + * Otp debuger block1 data register7. + */ +typedef union { + struct { + /** block1_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ + uint32_t block1_w7:32; + }; + uint32_t val; +} otp_debug_blk1_w7_reg_t; + + +/** Group: OTP_DEBUG Block1 Word8 Data */ +/** Type of blk1_w8 register + * Otp debuger block1 data register8. + */ +typedef union { + struct { + /** block1_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ + uint32_t block1_w8:32; + }; + uint32_t val; +} otp_debug_blk1_w8_reg_t; + + +/** Group: OTP_DEBUG Block1 Word9 Data */ +/** Type of blk1_w9 register + * Otp debuger block1 data register9. + */ +typedef union { + struct { + /** block1_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ + uint32_t block1_w9:32; + }; + uint32_t val; +} otp_debug_blk1_w9_reg_t; + + +/** Group: OTP_DEBUG Block2 Word1 Data */ +/** Type of blk2_w1 register + * Otp debuger block2 data register1. + */ +typedef union { + struct { + /** block2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ + uint32_t block2_w1:32; + }; + uint32_t val; +} otp_debug_blk2_w1_reg_t; + + +/** Group: OTP_DEBUG Block2 Word2 Data */ +/** Type of blk2_w2 register + * Otp debuger block2 data register2. + */ +typedef union { + struct { + /** block2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ + uint32_t block2_w2:32; + }; + uint32_t val; +} otp_debug_blk2_w2_reg_t; + + +/** Group: OTP_DEBUG Block2 Word3 Data */ +/** Type of blk2_w3 register + * Otp debuger block2 data register3. + */ +typedef union { + struct { + /** block2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ + uint32_t block2_w3:32; + }; + uint32_t val; +} otp_debug_blk2_w3_reg_t; + + +/** Group: OTP_DEBUG Block2 Word4 Data */ +/** Type of blk2_w4 register + * Otp debuger block2 data register4. + */ +typedef union { + struct { + /** block2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ + uint32_t block2_w4:32; + }; + uint32_t val; +} otp_debug_blk2_w4_reg_t; + + +/** Group: OTP_DEBUG Block2 Word5 Data */ +/** Type of blk2_w5 register + * Otp debuger block2 data register5. + */ +typedef union { + struct { + /** block2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ + uint32_t block2_w5:32; + }; + uint32_t val; +} otp_debug_blk2_w5_reg_t; + + +/** Group: OTP_DEBUG Block2 Word6 Data */ +/** Type of blk2_w6 register + * Otp debuger block2 data register6. + */ +typedef union { + struct { + /** block2_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ + uint32_t block2_w6:32; + }; + uint32_t val; +} otp_debug_blk2_w6_reg_t; + + +/** Group: OTP_DEBUG Block2 Word7 Data */ +/** Type of blk2_w7 register + * Otp debuger block2 data register7. + */ +typedef union { + struct { + /** block2_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ + uint32_t block2_w7:32; + }; + uint32_t val; +} otp_debug_blk2_w7_reg_t; + + +/** Group: OTP_DEBUG Block2 Word8 Data */ +/** Type of blk2_w8 register + * Otp debuger block2 data register8. + */ +typedef union { + struct { + /** block2_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ + uint32_t block2_w8:32; + }; + uint32_t val; +} otp_debug_blk2_w8_reg_t; + + +/** Group: OTP_DEBUG Block2 Word9 Data */ +/** Type of blk2_w9 register + * Otp debuger block2 data register9. + */ +typedef union { + struct { + /** block2_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ + uint32_t block2_w9:32; + }; + uint32_t val; +} otp_debug_blk2_w9_reg_t; + + +/** Group: OTP_DEBUG Block2 Word10 Data */ +/** Type of blk2_w10 register + * Otp debuger block2 data register10. + */ +typedef union { + struct { + /** block2_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ + uint32_t block2_w10:32; + }; + uint32_t val; +} otp_debug_blk2_w10_reg_t; + + +/** Group: OTP_DEBUG Block2 Word11 Data */ +/** Type of blk2_w11 register + * Otp debuger block2 data register11. + */ +typedef union { + struct { + /** block2_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ + uint32_t block2_w11:32; + }; + uint32_t val; +} otp_debug_blk2_w11_reg_t; + +/** Type of blk10_w11 register + * Otp debuger block10 data register11. + */ +typedef union { + struct { + /** block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t block10_w11:32; + }; + uint32_t val; +} otp_debug_blk10_w11_reg_t; + + +/** Group: OTP_DEBUG Block3 Word1 Data */ +/** Type of blk3_w1 register + * Otp debuger block3 data register1. + */ +typedef union { + struct { + /** block3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ + uint32_t block3_w1:32; + }; + uint32_t val; +} otp_debug_blk3_w1_reg_t; + + +/** Group: OTP_DEBUG Block3 Word2 Data */ +/** Type of blk3_w2 register + * Otp debuger block3 data register2. + */ +typedef union { + struct { + /** block3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ + uint32_t block3_w2:32; + }; + uint32_t val; +} otp_debug_blk3_w2_reg_t; + + +/** Group: OTP_DEBUG Block3 Word3 Data */ +/** Type of blk3_w3 register + * Otp debuger block3 data register3. + */ +typedef union { + struct { + /** block3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ + uint32_t block3_w3:32; + }; + uint32_t val; +} otp_debug_blk3_w3_reg_t; + + +/** Group: OTP_DEBUG Block3 Word4 Data */ +/** Type of blk3_w4 register + * Otp debuger block3 data register4. + */ +typedef union { + struct { + /** block3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ + uint32_t block3_w4:32; + }; + uint32_t val; +} otp_debug_blk3_w4_reg_t; + + +/** Group: OTP_DEBUG Block3 Word5 Data */ +/** Type of blk3_w5 register + * Otp debuger block3 data register5. + */ +typedef union { + struct { + /** block3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ + uint32_t block3_w5:32; + }; + uint32_t val; +} otp_debug_blk3_w5_reg_t; + + +/** Group: OTP_DEBUG Block3 Word6 Data */ +/** Type of blk3_w6 register + * Otp debuger block3 data register6. + */ +typedef union { + struct { + /** block3_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ + uint32_t block3_w6:32; + }; + uint32_t val; +} otp_debug_blk3_w6_reg_t; + + +/** Group: OTP_DEBUG Block3 Word7 Data */ +/** Type of blk3_w7 register + * Otp debuger block3 data register7. + */ +typedef union { + struct { + /** block3_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ + uint32_t block3_w7:32; + }; + uint32_t val; +} otp_debug_blk3_w7_reg_t; + + +/** Group: OTP_DEBUG Block3 Word8 Data */ +/** Type of blk3_w8 register + * Otp debuger block3 data register8. + */ +typedef union { + struct { + /** block3_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ + uint32_t block3_w8:32; + }; + uint32_t val; +} otp_debug_blk3_w8_reg_t; + + +/** Group: OTP_DEBUG Block3 Word9 Data */ +/** Type of blk3_w9 register + * Otp debuger block3 data register9. + */ +typedef union { + struct { + /** block3_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ + uint32_t block3_w9:32; + }; + uint32_t val; +} otp_debug_blk3_w9_reg_t; + + +/** Group: OTP_DEBUG Block3 Word10 Data */ +/** Type of blk3_w10 register + * Otp debuger block3 data register10. + */ +typedef union { + struct { + /** block3_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ + uint32_t block3_w10:32; + }; + uint32_t val; +} otp_debug_blk3_w10_reg_t; + + +/** Group: OTP_DEBUG Block3 Word11 Data */ +/** Type of blk3_w11 register + * Otp debuger block3 data register11. + */ +typedef union { + struct { + /** block3_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ + uint32_t block3_w11:32; + }; + uint32_t val; +} otp_debug_blk3_w11_reg_t; + + +/** Group: OTP_DEBUG Block4 Word1 Data */ +/** Type of blk4_w1 register + * Otp debuger block4 data register1. + */ +typedef union { + struct { + /** block4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ + uint32_t block4_w1:32; + }; + uint32_t val; +} otp_debug_blk4_w1_reg_t; + + +/** Group: OTP_DEBUG Block4 Word2 Data */ +/** Type of blk4_w2 register + * Otp debuger block4 data register2. + */ +typedef union { + struct { + /** block4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ + uint32_t block4_w2:32; + }; + uint32_t val; +} otp_debug_blk4_w2_reg_t; + + +/** Group: OTP_DEBUG Block4 Word3 Data */ +/** Type of blk4_w3 register + * Otp debuger block4 data register3. + */ +typedef union { + struct { + /** block4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ + uint32_t block4_w3:32; + }; + uint32_t val; +} otp_debug_blk4_w3_reg_t; + + +/** Group: OTP_DEBUG Block4 Word4 Data */ +/** Type of blk4_w4 register + * Otp debuger block4 data register4. + */ +typedef union { + struct { + /** block4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ + uint32_t block4_w4:32; + }; + uint32_t val; +} otp_debug_blk4_w4_reg_t; + + +/** Group: OTP_DEBUG Block4 Word5 Data */ +/** Type of blk4_w5 register + * Otp debuger block4 data register5. + */ +typedef union { + struct { + /** block4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ + uint32_t block4_w5:32; + }; + uint32_t val; +} otp_debug_blk4_w5_reg_t; + + +/** Group: OTP_DEBUG Block4 Word6 Data */ +/** Type of blk4_w6 register + * Otp debuger block4 data register6. + */ +typedef union { + struct { + /** block4_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ + uint32_t block4_w6:32; + }; + uint32_t val; +} otp_debug_blk4_w6_reg_t; + + +/** Group: OTP_DEBUG Block4 Word7 Data */ +/** Type of blk4_w7 register + * Otp debuger block4 data register7. + */ +typedef union { + struct { + /** block4_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ + uint32_t block4_w7:32; + }; + uint32_t val; +} otp_debug_blk4_w7_reg_t; + + +/** Group: OTP_DEBUG Block4 Word8 Data */ +/** Type of blk4_w8 register + * Otp debuger block4 data register8. + */ +typedef union { + struct { + /** block4_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ + uint32_t block4_w8:32; + }; + uint32_t val; +} otp_debug_blk4_w8_reg_t; + + +/** Group: OTP_DEBUG Block4 Word9 Data */ +/** Type of blk4_w9 register + * Otp debuger block4 data register9. + */ +typedef union { + struct { + /** block4_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ + uint32_t block4_w9:32; + }; + uint32_t val; +} otp_debug_blk4_w9_reg_t; + + +/** Group: OTP_DEBUG Block4 Word10 Data */ +/** Type of blk4_w10 register + * Otp debuger block4 data registe10. + */ +typedef union { + struct { + /** block4_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ + uint32_t block4_w10:32; + }; + uint32_t val; +} otp_debug_blk4_w10_reg_t; + + +/** Group: OTP_DEBUG Block4 Word11 Data */ +/** Type of blk4_w11 register + * Otp debuger block4 data register11. + */ +typedef union { + struct { + /** block4_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ + uint32_t block4_w11:32; + }; + uint32_t val; +} otp_debug_blk4_w11_reg_t; + + +/** Group: OTP_DEBUG Block5 Word1 Data */ +/** Type of blk5_w1 register + * Otp debuger block5 data register1. + */ +typedef union { + struct { + /** block5_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ + uint32_t block5_w1:32; + }; + uint32_t val; +} otp_debug_blk5_w1_reg_t; + + +/** Group: OTP_DEBUG Block5 Word2 Data */ +/** Type of blk5_w2 register + * Otp debuger block5 data register2. + */ +typedef union { + struct { + /** block5_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ + uint32_t block5_w2:32; + }; + uint32_t val; +} otp_debug_blk5_w2_reg_t; + + +/** Group: OTP_DEBUG Block5 Word3 Data */ +/** Type of blk5_w3 register + * Otp debuger block5 data register3. + */ +typedef union { + struct { + /** block5_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ + uint32_t block5_w3:32; + }; + uint32_t val; +} otp_debug_blk5_w3_reg_t; + + +/** Group: OTP_DEBUG Block5 Word4 Data */ +/** Type of blk5_w4 register + * Otp debuger block5 data register4. + */ +typedef union { + struct { + /** block5_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ + uint32_t block5_w4:32; + }; + uint32_t val; +} otp_debug_blk5_w4_reg_t; + + +/** Group: OTP_DEBUG Block5 Word5 Data */ +/** Type of blk5_w5 register + * Otp debuger block5 data register5. + */ +typedef union { + struct { + /** block5_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ + uint32_t block5_w5:32; + }; + uint32_t val; +} otp_debug_blk5_w5_reg_t; + + +/** Group: OTP_DEBUG Block5 Word6 Data */ +/** Type of blk5_w6 register + * Otp debuger block5 data register6. + */ +typedef union { + struct { + /** block5_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ + uint32_t block5_w6:32; + }; + uint32_t val; +} otp_debug_blk5_w6_reg_t; + + +/** Group: OTP_DEBUG Block5 Word7 Data */ +/** Type of blk5_w7 register + * Otp debuger block5 data register7. + */ +typedef union { + struct { + /** block5_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ + uint32_t block5_w7:32; + }; + uint32_t val; +} otp_debug_blk5_w7_reg_t; + + +/** Group: OTP_DEBUG Block5 Word8 Data */ +/** Type of blk5_w8 register + * Otp debuger block5 data register8. + */ +typedef union { + struct { + /** block5_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ + uint32_t block5_w8:32; + }; + uint32_t val; +} otp_debug_blk5_w8_reg_t; + + +/** Group: OTP_DEBUG Block5 Word9 Data */ +/** Type of blk5_w9 register + * Otp debuger block5 data register9. + */ +typedef union { + struct { + /** block5_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ + uint32_t block5_w9:32; + }; + uint32_t val; +} otp_debug_blk5_w9_reg_t; + + +/** Group: OTP_DEBUG Block5 Word10 Data */ +/** Type of blk5_w10 register + * Otp debuger block5 data register10. + */ +typedef union { + struct { + /** block5_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ + uint32_t block5_w10:32; + }; + uint32_t val; +} otp_debug_blk5_w10_reg_t; + + +/** Group: OTP_DEBUG Block5 Word11 Data */ +/** Type of blk5_w11 register + * Otp debuger block5 data register11. + */ +typedef union { + struct { + /** block5_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ + uint32_t block5_w11:32; + }; + uint32_t val; +} otp_debug_blk5_w11_reg_t; + + +/** Group: OTP_DEBUG Block6 Word1 Data */ +/** Type of blk6_w1 register + * Otp debuger block6 data register1. + */ +typedef union { + struct { + /** block6_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ + uint32_t block6_w1:32; + }; + uint32_t val; +} otp_debug_blk6_w1_reg_t; + + +/** Group: OTP_DEBUG Block6 Word2 Data */ +/** Type of blk6_w2 register + * Otp debuger block6 data register2. + */ +typedef union { + struct { + /** block6_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ + uint32_t block6_w2:32; + }; + uint32_t val; +} otp_debug_blk6_w2_reg_t; + + +/** Group: OTP_DEBUG Block6 Word3 Data */ +/** Type of blk6_w3 register + * Otp debuger block6 data register3. + */ +typedef union { + struct { + /** block6_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ + uint32_t block6_w3:32; + }; + uint32_t val; +} otp_debug_blk6_w3_reg_t; + + +/** Group: OTP_DEBUG Block6 Word4 Data */ +/** Type of blk6_w4 register + * Otp debuger block6 data register4. + */ +typedef union { + struct { + /** block6_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ + uint32_t block6_w4:32; + }; + uint32_t val; +} otp_debug_blk6_w4_reg_t; + + +/** Group: OTP_DEBUG Block6 Word5 Data */ +/** Type of blk6_w5 register + * Otp debuger block6 data register5. + */ +typedef union { + struct { + /** block6_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ + uint32_t block6_w5:32; + }; + uint32_t val; +} otp_debug_blk6_w5_reg_t; + + +/** Group: OTP_DEBUG Block6 Word6 Data */ +/** Type of blk6_w6 register + * Otp debuger block6 data register6. + */ +typedef union { + struct { + /** block6_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ + uint32_t block6_w6:32; + }; + uint32_t val; +} otp_debug_blk6_w6_reg_t; + + +/** Group: OTP_DEBUG Block6 Word7 Data */ +/** Type of blk6_w7 register + * Otp debuger block6 data register7. + */ +typedef union { + struct { + /** block6_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ + uint32_t block6_w7:32; + }; + uint32_t val; +} otp_debug_blk6_w7_reg_t; + + +/** Group: OTP_DEBUG Block6 Word8 Data */ +/** Type of blk6_w8 register + * Otp debuger block6 data register8. + */ +typedef union { + struct { + /** block6_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ + uint32_t block6_w8:32; + }; + uint32_t val; +} otp_debug_blk6_w8_reg_t; + + +/** Group: OTP_DEBUG Block6 Word9 Data */ +/** Type of blk6_w9 register + * Otp debuger block6 data register9. + */ +typedef union { + struct { + /** block6_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ + uint32_t block6_w9:32; + }; + uint32_t val; +} otp_debug_blk6_w9_reg_t; + + +/** Group: OTP_DEBUG Block6 Word10 Data */ +/** Type of blk6_w10 register + * Otp debuger block6 data register10. + */ +typedef union { + struct { + /** block6_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ + uint32_t block6_w10:32; + }; + uint32_t val; +} otp_debug_blk6_w10_reg_t; + + +/** Group: OTP_DEBUG Block6 Word11 Data */ +/** Type of blk6_w11 register + * Otp debuger block6 data register11. + */ +typedef union { + struct { + /** block6_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ + uint32_t block6_w11:32; + }; + uint32_t val; +} otp_debug_blk6_w11_reg_t; + + +/** Group: OTP_DEBUG Block7 Word1 Data */ +/** Type of blk7_w1 register + * Otp debuger block7 data register1. + */ +typedef union { + struct { + /** block7_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ + uint32_t block7_w1:32; + }; + uint32_t val; +} otp_debug_blk7_w1_reg_t; + + +/** Group: OTP_DEBUG Block7 Word2 Data */ +/** Type of blk7_w2 register + * Otp debuger block7 data register2. + */ +typedef union { + struct { + /** block7_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ + uint32_t block7_w2:32; + }; + uint32_t val; +} otp_debug_blk7_w2_reg_t; + + +/** Group: OTP_DEBUG Block7 Word3 Data */ +/** Type of blk7_w3 register + * Otp debuger block7 data register3. + */ +typedef union { + struct { + /** block7_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ + uint32_t block7_w3:32; + }; + uint32_t val; +} otp_debug_blk7_w3_reg_t; + + +/** Group: OTP_DEBUG Block7 Word4 Data */ +/** Type of blk7_w4 register + * Otp debuger block7 data register4. + */ +typedef union { + struct { + /** block7_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ + uint32_t block7_w4:32; + }; + uint32_t val; +} otp_debug_blk7_w4_reg_t; + + +/** Group: OTP_DEBUG Block7 Word5 Data */ +/** Type of blk7_w5 register + * Otp debuger block7 data register5. + */ +typedef union { + struct { + /** block7_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ + uint32_t block7_w5:32; + }; + uint32_t val; +} otp_debug_blk7_w5_reg_t; + + +/** Group: OTP_DEBUG Block7 Word6 Data */ +/** Type of blk7_w6 register + * Otp debuger block7 data register6. + */ +typedef union { + struct { + /** block7_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ + uint32_t block7_w6:32; + }; + uint32_t val; +} otp_debug_blk7_w6_reg_t; + + +/** Group: OTP_DEBUG Block7 Word7 Data */ +/** Type of blk7_w7 register + * Otp debuger block7 data register7. + */ +typedef union { + struct { + /** block7_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ + uint32_t block7_w7:32; + }; + uint32_t val; +} otp_debug_blk7_w7_reg_t; + + +/** Group: OTP_DEBUG Block7 Word8 Data */ +/** Type of blk7_w8 register + * Otp debuger block7 data register8. + */ +typedef union { + struct { + /** block7_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ + uint32_t block7_w8:32; + }; + uint32_t val; +} otp_debug_blk7_w8_reg_t; + + +/** Group: OTP_DEBUG Block7 Word9 Data */ +/** Type of blk7_w9 register + * Otp debuger block7 data register9. + */ +typedef union { + struct { + /** block7_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ + uint32_t block7_w9:32; + }; + uint32_t val; +} otp_debug_blk7_w9_reg_t; + + +/** Group: OTP_DEBUG Block7 Word10 Data */ +/** Type of blk7_w10 register + * Otp debuger block7 data register10. + */ +typedef union { + struct { + /** block7_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ + uint32_t block7_w10:32; + }; + uint32_t val; +} otp_debug_blk7_w10_reg_t; + + +/** Group: OTP_DEBUG Block7 Word11 Data */ +/** Type of blk7_w11 register + * Otp debuger block7 data register11. + */ +typedef union { + struct { + /** block7_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ + uint32_t block7_w11:32; + }; + uint32_t val; +} otp_debug_blk7_w11_reg_t; + + +/** Group: OTP_DEBUG Block8 Word1 Data */ +/** Type of blk8_w1 register + * Otp debuger block8 data register1. + */ +typedef union { + struct { + /** block8_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ + uint32_t block8_w1:32; + }; + uint32_t val; +} otp_debug_blk8_w1_reg_t; + + +/** Group: OTP_DEBUG Block8 Word2 Data */ +/** Type of blk8_w2 register + * Otp debuger block8 data register2. + */ +typedef union { + struct { + /** block8_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ + uint32_t block8_w2:32; + }; + uint32_t val; +} otp_debug_blk8_w2_reg_t; + + +/** Group: OTP_DEBUG Block8 Word3 Data */ +/** Type of blk8_w3 register + * Otp debuger block8 data register3. + */ +typedef union { + struct { + /** block8_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ + uint32_t block8_w3:32; + }; + uint32_t val; +} otp_debug_blk8_w3_reg_t; + + +/** Group: OTP_DEBUG Block8 Word4 Data */ +/** Type of blk8_w4 register + * Otp debuger block8 data register4. + */ +typedef union { + struct { + /** block8_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ + uint32_t block8_w4:32; + }; + uint32_t val; +} otp_debug_blk8_w4_reg_t; + + +/** Group: OTP_DEBUG Block8 Word5 Data */ +/** Type of blk8_w5 register + * Otp debuger block8 data register5. + */ +typedef union { + struct { + /** block8_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ + uint32_t block8_w5:32; + }; + uint32_t val; +} otp_debug_blk8_w5_reg_t; + + +/** Group: OTP_DEBUG Block8 Word6 Data */ +/** Type of blk8_w6 register + * Otp debuger block8 data register6. + */ +typedef union { + struct { + /** block8_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ + uint32_t block8_w6:32; + }; + uint32_t val; +} otp_debug_blk8_w6_reg_t; + + +/** Group: OTP_DEBUG Block8 Word7 Data */ +/** Type of blk8_w7 register + * Otp debuger block8 data register7. + */ +typedef union { + struct { + /** block8_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ + uint32_t block8_w7:32; + }; + uint32_t val; +} otp_debug_blk8_w7_reg_t; + + +/** Group: OTP_DEBUG Block8 Word8 Data */ +/** Type of blk8_w8 register + * Otp debuger block8 data register8. + */ +typedef union { + struct { + /** block8_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ + uint32_t block8_w8:32; + }; + uint32_t val; +} otp_debug_blk8_w8_reg_t; + + +/** Group: OTP_DEBUG Block8 Word9 Data */ +/** Type of blk8_w9 register + * Otp debuger block8 data register9. + */ +typedef union { + struct { + /** block8_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ + uint32_t block8_w9:32; + }; + uint32_t val; +} otp_debug_blk8_w9_reg_t; + + +/** Group: OTP_DEBUG Block8 Word10 Data */ +/** Type of blk8_w10 register + * Otp debuger block8 data register10. + */ +typedef union { + struct { + /** block8_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ + uint32_t block8_w10:32; + }; + uint32_t val; +} otp_debug_blk8_w10_reg_t; + + +/** Group: OTP_DEBUG Block8 Word11 Data */ +/** Type of blk8_w11 register + * Otp debuger block8 data register11. + */ +typedef union { + struct { + /** block8_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ + uint32_t block8_w11:32; + }; + uint32_t val; +} otp_debug_blk8_w11_reg_t; + + +/** Group: OTP_DEBUG Block9 Word1 Data */ +/** Type of blk9_w1 register + * Otp debuger block9 data register1. + */ +typedef union { + struct { + /** block9_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ + uint32_t block9_w1:32; + }; + uint32_t val; +} otp_debug_blk9_w1_reg_t; + + +/** Group: OTP_DEBUG Block9 Word2 Data */ +/** Type of blk9_w2 register + * Otp debuger block9 data register2. + */ +typedef union { + struct { + /** block9_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ + uint32_t block9_w2:32; + }; + uint32_t val; +} otp_debug_blk9_w2_reg_t; + + +/** Group: OTP_DEBUG Block9 Word3 Data */ +/** Type of blk9_w3 register + * Otp debuger block9 data register3. + */ +typedef union { + struct { + /** block9_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ + uint32_t block9_w3:32; + }; + uint32_t val; +} otp_debug_blk9_w3_reg_t; + + +/** Group: OTP_DEBUG Block9 Word4 Data */ +/** Type of blk9_w4 register + * Otp debuger block9 data register4. + */ +typedef union { + struct { + /** block9_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ + uint32_t block9_w4:32; + }; + uint32_t val; +} otp_debug_blk9_w4_reg_t; + + +/** Group: OTP_DEBUG Block9 Word5 Data */ +/** Type of blk9_w5 register + * Otp debuger block9 data register5. + */ +typedef union { + struct { + /** block9_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ + uint32_t block9_w5:32; + }; + uint32_t val; +} otp_debug_blk9_w5_reg_t; + + +/** Group: OTP_DEBUG Block9 Word6 Data */ +/** Type of blk9_w6 register + * Otp debuger block9 data register6. + */ +typedef union { + struct { + /** block9_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ + uint32_t block9_w6:32; + }; + uint32_t val; +} otp_debug_blk9_w6_reg_t; + + +/** Group: OTP_DEBUG Block9 Word7 Data */ +/** Type of blk9_w7 register + * Otp debuger block9 data register7. + */ +typedef union { + struct { + /** block9_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ + uint32_t block9_w7:32; + }; + uint32_t val; +} otp_debug_blk9_w7_reg_t; + + +/** Group: OTP_DEBUG Block9 Word8 Data */ +/** Type of blk9_w8 register + * Otp debuger block9 data register8. + */ +typedef union { + struct { + /** block9_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ + uint32_t block9_w8:32; + }; + uint32_t val; +} otp_debug_blk9_w8_reg_t; + + +/** Group: OTP_DEBUG Block9 Word9 Data */ +/** Type of blk9_w9 register + * Otp debuger block9 data register9. + */ +typedef union { + struct { + /** block9_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ + uint32_t block9_w9:32; + }; + uint32_t val; +} otp_debug_blk9_w9_reg_t; + + +/** Group: OTP_DEBUG Block9 Word10 Data */ +/** Type of blk9_w10 register + * Otp debuger block9 data register10. + */ +typedef union { + struct { + /** block9_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ + uint32_t block9_w10:32; + }; + uint32_t val; +} otp_debug_blk9_w10_reg_t; + + +/** Group: OTP_DEBUG Block9 Word11 Data */ +/** Type of blk9_w11 register + * Otp debuger block9 data register11. + */ +typedef union { + struct { + /** block9_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ + uint32_t block9_w11:32; + }; + uint32_t val; +} otp_debug_blk9_w11_reg_t; + + +/** Group: OTP_DEBUG Block10 Word1 Data */ +/** Type of blk10_w1 register + * Otp debuger block10 data register1. + */ +typedef union { + struct { + /** block10_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ + uint32_t block10_w1:32; + }; + uint32_t val; +} otp_debug_blk10_w1_reg_t; + + +/** Group: OTP_DEBUG Block10 Word2 Data */ +/** Type of blk10_w2 register + * Otp debuger block10 data register2. + */ +typedef union { + struct { + /** block10_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ + uint32_t block10_w2:32; + }; + uint32_t val; +} otp_debug_blk10_w2_reg_t; + + +/** Group: OTP_DEBUG Block10 Word3 Data */ +/** Type of blk10_w3 register + * Otp debuger block10 data register3. + */ +typedef union { + struct { + /** block10_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ + uint32_t block10_w3:32; + }; + uint32_t val; +} otp_debug_blk10_w3_reg_t; + + +/** Group: OTP_DEBUG Block10 Word4 Data */ +/** Type of blk10_w4 register + * Otp debuger block10 data register4. + */ +typedef union { + struct { + /** block10_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ + uint32_t block10_w4:32; + }; + uint32_t val; +} otp_debug_blk10_w4_reg_t; + + +/** Group: OTP_DEBUG Block10 Word5 Data */ +/** Type of blk10_w5 register + * Otp debuger block10 data register5. + */ +typedef union { + struct { + /** block10_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ + uint32_t block10_w5:32; + }; + uint32_t val; +} otp_debug_blk10_w5_reg_t; + + +/** Group: OTP_DEBUG Block10 Word6 Data */ +/** Type of blk10_w6 register + * Otp debuger block10 data register6. + */ +typedef union { + struct { + /** block10_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ + uint32_t block10_w6:32; + }; + uint32_t val; +} otp_debug_blk10_w6_reg_t; + + +/** Group: OTP_DEBUG Block10 Word7 Data */ +/** Type of blk10_w7 register + * Otp debuger block10 data register7. + */ +typedef union { + struct { + /** block10_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ + uint32_t block10_w7:32; + }; + uint32_t val; +} otp_debug_blk10_w7_reg_t; + + +/** Group: OTP_DEBUG Block10 Word8 Data */ +/** Type of blk10_w8 register + * Otp debuger block10 data register8. + */ +typedef union { + struct { + /** block10_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ + uint32_t block10_w8:32; + }; + uint32_t val; +} otp_debug_blk10_w8_reg_t; + + +/** Group: OTP_DEBUG Block10 Word9 Data */ +/** Type of blk10_w9 register + * Otp debuger block10 data register9. + */ +typedef union { + struct { + /** block10_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ + uint32_t block10_w9:32; + }; + uint32_t val; +} otp_debug_blk10_w9_reg_t; + + +/** Group: OTP_DEBUG Block10 Word10 Data */ +/** Type of blk10_w10 register + * Otp debuger block10 data register10. + */ +typedef union { + struct { + /** block19_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ + uint32_t block19_w10:32; + }; + uint32_t val; +} otp_debug_blk10_w10_reg_t; + + +/** Group: OTP_DEBUG Clock_en Configuration Register */ +/** Type of clk register + * Otp debuger clk_en configuration register. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} otp_debug_clk_reg_t; + + +/** Group: OTP_DEBUG Apb2otp Enable Singal */ +/** Type of apb2otp_en register + * Otp_debuger apb2otp enable configuration register. + */ +typedef union { + struct { + /** apb2otp_en : R/W; bitpos: [0]; default: 0; + * Debug mode enable signal. + */ + uint32_t apb2otp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} otp_debug_apb2otp_en_reg_t; + + +/** Group: OTP_DEBUG Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 539037736; + * Stores otp_debug version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} otp_debug_date_reg_t; + + +typedef struct otp_debug_dev_t { + volatile otp_debug_wr_dis_reg_t wr_dis; + volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1; + volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2; + volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3; + volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4; + volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5; + volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1; + volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2; + volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3; + volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4; + volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5; + volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1; + volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2; + volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3; + volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4; + volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5; + volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1; + volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2; + volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3; + volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4; + volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5; + volatile otp_debug_blk1_w1_reg_t blk1_w1; + volatile otp_debug_blk1_w2_reg_t blk1_w2; + volatile otp_debug_blk1_w3_reg_t blk1_w3; + volatile otp_debug_blk1_w4_reg_t blk1_w4; + volatile otp_debug_blk1_w5_reg_t blk1_w5; + volatile otp_debug_blk1_w6_reg_t blk1_w6; + volatile otp_debug_blk1_w7_reg_t blk1_w7; + volatile otp_debug_blk1_w8_reg_t blk1_w8; + volatile otp_debug_blk1_w9_reg_t blk1_w9; + volatile otp_debug_blk2_w1_reg_t blk2_w1; + volatile otp_debug_blk2_w2_reg_t blk2_w2; + volatile otp_debug_blk2_w3_reg_t blk2_w3; + volatile otp_debug_blk2_w4_reg_t blk2_w4; + volatile otp_debug_blk2_w5_reg_t blk2_w5; + volatile otp_debug_blk2_w6_reg_t blk2_w6; + volatile otp_debug_blk2_w7_reg_t blk2_w7; + volatile otp_debug_blk2_w8_reg_t blk2_w8; + volatile otp_debug_blk2_w9_reg_t blk2_w9; + volatile otp_debug_blk2_w10_reg_t blk2_w10; + volatile otp_debug_blk2_w11_reg_t blk2_w11; + volatile otp_debug_blk3_w1_reg_t blk3_w1; + volatile otp_debug_blk3_w2_reg_t blk3_w2; + volatile otp_debug_blk3_w3_reg_t blk3_w3; + volatile otp_debug_blk3_w4_reg_t blk3_w4; + volatile otp_debug_blk3_w5_reg_t blk3_w5; + volatile otp_debug_blk3_w6_reg_t blk3_w6; + volatile otp_debug_blk3_w7_reg_t blk3_w7; + volatile otp_debug_blk3_w8_reg_t blk3_w8; + volatile otp_debug_blk3_w9_reg_t blk3_w9; + volatile otp_debug_blk3_w10_reg_t blk3_w10; + volatile otp_debug_blk3_w11_reg_t blk3_w11; + volatile otp_debug_blk4_w1_reg_t blk4_w1; + volatile otp_debug_blk4_w2_reg_t blk4_w2; + volatile otp_debug_blk4_w3_reg_t blk4_w3; + volatile otp_debug_blk4_w4_reg_t blk4_w4; + volatile otp_debug_blk4_w5_reg_t blk4_w5; + volatile otp_debug_blk4_w6_reg_t blk4_w6; + volatile otp_debug_blk4_w7_reg_t blk4_w7; + volatile otp_debug_blk4_w8_reg_t blk4_w8; + volatile otp_debug_blk4_w9_reg_t blk4_w9; + volatile otp_debug_blk4_w10_reg_t blk4_w10; + volatile otp_debug_blk4_w11_reg_t blk4_w11; + volatile otp_debug_blk5_w1_reg_t blk5_w1; + volatile otp_debug_blk5_w2_reg_t blk5_w2; + volatile otp_debug_blk5_w3_reg_t blk5_w3; + volatile otp_debug_blk5_w4_reg_t blk5_w4; + volatile otp_debug_blk5_w5_reg_t blk5_w5; + volatile otp_debug_blk5_w6_reg_t blk5_w6; + volatile otp_debug_blk5_w7_reg_t blk5_w7; + volatile otp_debug_blk5_w8_reg_t blk5_w8; + volatile otp_debug_blk5_w9_reg_t blk5_w9; + volatile otp_debug_blk5_w10_reg_t blk5_w10; + volatile otp_debug_blk5_w11_reg_t blk5_w11; + volatile otp_debug_blk6_w1_reg_t blk6_w1; + volatile otp_debug_blk6_w2_reg_t blk6_w2; + volatile otp_debug_blk6_w3_reg_t blk6_w3; + volatile otp_debug_blk6_w4_reg_t blk6_w4; + volatile otp_debug_blk6_w5_reg_t blk6_w5; + volatile otp_debug_blk6_w6_reg_t blk6_w6; + volatile otp_debug_blk6_w7_reg_t blk6_w7; + volatile otp_debug_blk6_w8_reg_t blk6_w8; + volatile otp_debug_blk6_w9_reg_t blk6_w9; + volatile otp_debug_blk6_w10_reg_t blk6_w10; + volatile otp_debug_blk6_w11_reg_t blk6_w11; + volatile otp_debug_blk7_w1_reg_t blk7_w1; + volatile otp_debug_blk7_w2_reg_t blk7_w2; + volatile otp_debug_blk7_w3_reg_t blk7_w3; + volatile otp_debug_blk7_w4_reg_t blk7_w4; + volatile otp_debug_blk7_w5_reg_t blk7_w5; + volatile otp_debug_blk7_w6_reg_t blk7_w6; + volatile otp_debug_blk7_w7_reg_t blk7_w7; + volatile otp_debug_blk7_w8_reg_t blk7_w8; + volatile otp_debug_blk7_w9_reg_t blk7_w9; + volatile otp_debug_blk7_w10_reg_t blk7_w10; + volatile otp_debug_blk7_w11_reg_t blk7_w11; + volatile otp_debug_blk8_w1_reg_t blk8_w1; + volatile otp_debug_blk8_w2_reg_t blk8_w2; + volatile otp_debug_blk8_w3_reg_t blk8_w3; + volatile otp_debug_blk8_w4_reg_t blk8_w4; + volatile otp_debug_blk8_w5_reg_t blk8_w5; + volatile otp_debug_blk8_w6_reg_t blk8_w6; + volatile otp_debug_blk8_w7_reg_t blk8_w7; + volatile otp_debug_blk8_w8_reg_t blk8_w8; + volatile otp_debug_blk8_w9_reg_t blk8_w9; + volatile otp_debug_blk8_w10_reg_t blk8_w10; + volatile otp_debug_blk8_w11_reg_t blk8_w11; + volatile otp_debug_blk9_w1_reg_t blk9_w1; + volatile otp_debug_blk9_w2_reg_t blk9_w2; + volatile otp_debug_blk9_w3_reg_t blk9_w3; + volatile otp_debug_blk9_w4_reg_t blk9_w4; + volatile otp_debug_blk9_w5_reg_t blk9_w5; + volatile otp_debug_blk9_w6_reg_t blk9_w6; + volatile otp_debug_blk9_w7_reg_t blk9_w7; + volatile otp_debug_blk9_w8_reg_t blk9_w8; + volatile otp_debug_blk9_w9_reg_t blk9_w9; + volatile otp_debug_blk9_w10_reg_t blk9_w10; + volatile otp_debug_blk9_w11_reg_t blk9_w11; + volatile otp_debug_blk10_w1_reg_t blk10_w1; + volatile otp_debug_blk10_w2_reg_t blk10_w2; + volatile otp_debug_blk10_w3_reg_t blk10_w3; + volatile otp_debug_blk10_w4_reg_t blk10_w4; + volatile otp_debug_blk10_w5_reg_t blk10_w5; + volatile otp_debug_blk10_w6_reg_t blk10_w6; + volatile otp_debug_blk10_w7_reg_t blk10_w7; + volatile otp_debug_blk10_w8_reg_t blk10_w8; + volatile otp_debug_blk10_w9_reg_t blk10_w9; + volatile otp_debug_blk10_w10_reg_t blk10_w10; + volatile otp_debug_blk10_w11_reg_t blk10_w11; + volatile otp_debug_clk_reg_t clk; + volatile otp_debug_apb2otp_en_reg_t apb2otp_en; + volatile otp_debug_date_reg_t date; +} otp_debug_dev_t; + +extern otp_debug_dev_t OTP_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/parl_io_reg.h b/components/soc/esp32c5/include/soc/parl_io_reg.h new file mode 100644 index 00000000000..74a528017d9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/parl_io_reg.h @@ -0,0 +1,480 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PARL_IO_RX_MODE_CFG_REG register + * Parallel RX Sampling mode configuration register. + */ +#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0) +/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ +#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S) +#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_S 21 +/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable data sampling by software. + */ +#define PARL_IO_RX_SW_EN (BIT(25)) +#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S) +#define PARL_IO_RX_SW_EN_V 0x00000001U +#define PARL_IO_RX_SW_EN_S 25 +/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0; + * Set this bit to invert the external enable signal. + */ +#define PARL_IO_RX_EXT_EN_INV (BIT(26)) +#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S) +#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U +#define PARL_IO_RX_EXT_EN_INV_S 26 +/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 4'd0: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 4'd1: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 4'd4: positive pulse start(data bit included) && length end + * 4'd5: positive pulse start(data bit excluded) && length end + */ +#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S) +#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27 +/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 2'b00: external level enable mode + * 2'b01: external pulse enable mode + * 2'b10: internal software enable mode + */ +#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S) +#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_S 30 + +/** PARL_IO_RX_DATA_CFG_REG register + * Parallel RX data configuration register. + */ +#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4) +/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ +#define PARL_IO_RX_BITLEN 0x0007FFFFU +#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S) +#define PARL_IO_RX_BITLEN_V 0x0007FFFFU +#define PARL_IO_RX_BITLEN_S 9 +/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + */ +#define PARL_IO_RX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S) +#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_RX_DATA_ORDER_INV_S 28 +/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ +#define PARL_IO_RX_BUS_WID_SEL 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S) +#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_S 29 + +/** PARL_IO_RX_GENRL_CFG_REG register + * Parallel RX general configuration register. + */ +#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8) +/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0; + * Set this bit to enable the clock gating of output rx clock. + */ +#define PARL_IO_RX_GATING_EN (BIT(12)) +#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S) +#define PARL_IO_RX_GATING_EN_V 0x00000001U +#define PARL_IO_RX_GATING_EN_S 12 +/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ +#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S) +#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_S 13 +/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to enable timeout function to generate error eof. + */ +#define PARL_IO_RX_TIMEOUT_EN (BIT(29)) +#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S) +#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U +#define PARL_IO_RX_TIMEOUT_EN_S 29 +/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by external enable signal. + */ +#define PARL_IO_RX_EOF_GEN_SEL (BIT(30)) +#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S) +#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_RX_EOF_GEN_SEL_S 30 + +/** PARL_IO_RX_START_CFG_REG register + * Parallel RX Start configuration register. + */ +#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc) +/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start rx data sampling. + */ +#define PARL_IO_RX_START (BIT(31)) +#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S) +#define PARL_IO_RX_START_V 0x00000001U +#define PARL_IO_RX_START_S 31 + +/** PARL_IO_TX_DATA_CFG_REG register + * Parallel TX data configuration register. + */ +#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10) +/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ +#define PARL_IO_TX_BITLEN 0x0007FFFFU +#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S) +#define PARL_IO_TX_BITLEN_V 0x0007FFFFU +#define PARL_IO_TX_BITLEN_S 9 +/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + */ +#define PARL_IO_TX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S) +#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_TX_DATA_ORDER_INV_S 28 +/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ +#define PARL_IO_TX_BUS_WID_SEL 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S) +#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_S 29 + +/** PARL_IO_TX_START_CFG_REG register + * Parallel TX Start configuration register. + */ +#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14) +/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start tx data transmit. + */ +#define PARL_IO_TX_START (BIT(31)) +#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S) +#define PARL_IO_TX_START_V 0x00000001U +#define PARL_IO_TX_START_S 31 + +/** PARL_IO_TX_GENRL_CFG_REG register + * Parallel TX general configuration register. + */ +#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18) +/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0; + * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by DMA eof. + */ +#define PARL_IO_TX_EOF_GEN_SEL (BIT(13)) +#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S) +#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_TX_EOF_GEN_SEL_S 13 +/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ +#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S) +#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_S 14 +/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0; + * Set this bit to enable the clock gating of output tx clock. + */ +#define PARL_IO_TX_GATING_EN (BIT(30)) +#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S) +#define PARL_IO_TX_GATING_EN_V 0x00000001U +#define PARL_IO_TX_GATING_EN_S 30 +/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable the output of tx data valid signal. + */ +#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31)) +#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S) +#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U +#define PARL_IO_TX_VALID_OUTPUT_EN_S 31 + +/** PARL_IO_FIFO_CFG_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c) +/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; + * Set this bit to reset async fifo in tx module. + */ +#define PARL_IO_TX_FIFO_SRST (BIT(30)) +#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S) +#define PARL_IO_TX_FIFO_SRST_V 0x00000001U +#define PARL_IO_TX_FIFO_SRST_S 30 +/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0; + * Set this bit to reset async fifo in rx module. + */ +#define PARL_IO_RX_FIFO_SRST (BIT(31)) +#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S) +#define PARL_IO_RX_FIFO_SRST_V 0x00000001U +#define PARL_IO_RX_FIFO_SRST_S 31 + +/** PARL_IO_REG_UPDATE_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20) +/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0; + * Set this bit to update rx register configuration. + */ +#define PARL_IO_RX_REG_UPDATE (BIT(31)) +#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S) +#define PARL_IO_RX_REG_UPDATE_V 0x00000001U +#define PARL_IO_RX_REG_UPDATE_S 31 + +/** PARL_IO_ST_REG register + * Parallel IO module status register0. + */ +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24) +/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ +#define PARL_IO_TX_READY (BIT(31)) +#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S) +#define PARL_IO_TX_READY_V 0x00000001U +#define PARL_IO_TX_READY_S 31 + +/** PARL_IO_INT_ENA_REG register + * Parallel IO interrupt enable singal configuration register. + */ +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) +/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1 +/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ENA (BIT(2)) +#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S) +#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ENA_S 2 + +/** PARL_IO_INT_RAW_REG register + * Parallel IO interrupt raw singal status register. + */ +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) +/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1 +/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_RAW (BIT(2)) +#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S) +#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U +#define PARL_IO_TX_EOF_INT_RAW_S 2 + +/** PARL_IO_INT_ST_REG register + * Parallel IO interrupt singal status register. + */ +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) +/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1 +/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ST (BIT(2)) +#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S) +#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ST_S 2 + +/** PARL_IO_INT_CLR_REG register + * Parallel IO interrupt clear singal configuration register. + */ +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) +/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1 +/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_CLR (BIT(2)) +#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S) +#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U +#define PARL_IO_TX_EOF_INT_CLR_S 2 + +/** PARL_IO_RX_ST0_REG register + * Parallel IO RX status register0 + */ +#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38) +/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ +#define PARL_IO_RX_CNT 0x0000001FU +#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S) +#define PARL_IO_RX_CNT_V 0x0000001FU +#define PARL_IO_RX_CNT_S 8 +/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ +#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S) +#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13 + +/** PARL_IO_RX_ST1_REG register + * Parallel IO RX status register1 + */ +#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c) +/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ +#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_TX_ST0_REG register + * Parallel IO TX status register0 + */ +#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40) +/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ +#define PARL_IO_TX_CNT 0x0000007FU +#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S) +#define PARL_IO_TX_CNT_V 0x0000007FU +#define PARL_IO_TX_CNT_S 6 +/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ +#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_RX_CLK_CFG_REG register + * Parallel IO RX clk configuration register + */ +#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44) +/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Rx core clock. + */ +#define PARL_IO_RX_CLK_I_INV (BIT(30)) +#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S) +#define PARL_IO_RX_CLK_I_INV_V 0x00000001U +#define PARL_IO_RX_CLK_I_INV_S 30 +/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Rx core clock. + */ +#define PARL_IO_RX_CLK_O_INV (BIT(31)) +#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S) +#define PARL_IO_RX_CLK_O_INV_V 0x00000001U +#define PARL_IO_RX_CLK_O_INV_S 31 + +/** PARL_IO_TX_CLK_CFG_REG register + * Parallel IO TX clk configuration register + */ +#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48) +/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Tx core clock. + */ +#define PARL_IO_TX_CLK_I_INV (BIT(30)) +#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S) +#define PARL_IO_TX_CLK_I_INV_V 0x00000001U +#define PARL_IO_TX_CLK_I_INV_S 30 +/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Tx core clock. + */ +#define PARL_IO_TX_CLK_O_INV (BIT(31)) +#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S) +#define PARL_IO_TX_CLK_O_INV_V 0x00000001U +#define PARL_IO_TX_CLK_O_INV_S 31 + +/** PARL_IO_CLK_REG register + * Parallel IO clk configuration register + */ +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) +/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ +#define PARL_IO_CLK_EN (BIT(31)) +#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S) +#define PARL_IO_CLK_EN_V 0x00000001U +#define PARL_IO_CLK_EN_S 31 + +/** PARL_IO_VERSION_REG register + * Version register. + */ +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) +/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920; + * Version of this register file + */ +#define PARL_IO_DATE 0x0FFFFFFFU +#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S) +#define PARL_IO_DATE_V 0x0FFFFFFFU +#define PARL_IO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/include/soc/parl_io_struct.h new file mode 100644 index 00000000000..aea2cb383b8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/parl_io_struct.h @@ -0,0 +1,509 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PARL_IO RX Mode Configuration */ +/** Type of rx_mode_cfg register + * Parallel RX Sampling mode configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ + uint32_t rx_ext_en_sel:4; + /** rx_sw_en : R/W; bitpos: [25]; default: 0; + * Set this bit to enable data sampling by software. + */ + uint32_t rx_sw_en:1; + /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0; + * Set this bit to invert the external enable signal. + */ + uint32_t rx_ext_en_inv:1; + /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 4'd0: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 4'd1: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 4'd4: positive pulse start(data bit included) && length end + * 4'd5: positive pulse start(data bit excluded) && length end + */ + uint32_t rx_pulse_submode_sel:3; + /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 2'b00: external level enable mode + * 2'b01: external pulse enable mode + * 2'b10: internal software enable mode + */ + uint32_t rx_smp_mode_sel:2; + }; + uint32_t val; +} parl_io_rx_mode_cfg_reg_t; + + +/** Group: PARL_IO RX Data Configuration */ +/** Type of rx_data_cfg register + * Parallel RX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** rx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ + uint32_t rx_bitlen:19; + /** rx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + */ + uint32_t rx_data_order_inv:1; + /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ + uint32_t rx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_rx_data_cfg_reg_t; + + +/** Group: PARL_IO RX General Configuration */ +/** Type of rx_genrl_cfg register + * Parallel RX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rx_gating_en : R/W; bitpos: [12]; default: 0; + * Set this bit to enable the clock gating of output rx clock. + */ + uint32_t rx_gating_en:1; + /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ + uint32_t rx_timeout_thres:16; + /** rx_timeout_en : R/W; bitpos: [29]; default: 1; + * Set this bit to enable timeout function to generate error eof. + */ + uint32_t rx_timeout_en:1; + /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by external enable signal. + */ + uint32_t rx_eof_gen_sel:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} parl_io_rx_genrl_cfg_reg_t; + + +/** Group: PARL_IO RX Start Configuration */ +/** Type of rx_start_cfg register + * Parallel RX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start rx data sampling. + */ + uint32_t rx_start:1; + }; + uint32_t val; +} parl_io_rx_start_cfg_reg_t; + + +/** Group: PARL_IO TX Data Configuration */ +/** Type of tx_data_cfg register + * Parallel TX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ + uint32_t tx_bitlen:19; + /** tx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + */ + uint32_t tx_data_order_inv:1; + /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ + uint32_t tx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_tx_data_cfg_reg_t; + + +/** Group: PARL_IO TX Start Configuration */ +/** Type of tx_start_cfg register + * Parallel TX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start tx data transmit. + */ + uint32_t tx_start:1; + }; + uint32_t val; +} parl_io_tx_start_cfg_reg_t; + + +/** Group: PARL_IO TX General Configuration */ +/** Type of tx_genrl_cfg register + * Parallel TX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0; + * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by DMA eof. + */ + uint32_t tx_eof_gen_sel:1; + /** tx_idle_value : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ + uint32_t tx_idle_value:16; + /** tx_gating_en : R/W; bitpos: [30]; default: 0; + * Set this bit to enable the clock gating of output tx clock. + */ + uint32_t tx_gating_en:1; + /** tx_valid_output_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable the output of tx data valid signal. + */ + uint32_t tx_valid_output_en:1; + }; + uint32_t val; +} parl_io_tx_genrl_cfg_reg_t; + + +/** Group: PARL_IO FIFO Configuration */ +/** Type of fifo_cfg register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_fifo_srst : R/W; bitpos: [30]; default: 0; + * Set this bit to reset async fifo in tx module. + */ + uint32_t tx_fifo_srst:1; + /** rx_fifo_srst : R/W; bitpos: [31]; default: 0; + * Set this bit to reset async fifo in rx module. + */ + uint32_t rx_fifo_srst:1; + }; + uint32_t val; +} parl_io_fifo_cfg_reg_t; + + +/** Group: PARL_IO Register Update Configuration */ +/** Type of reg_update register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_reg_update : WT; bitpos: [31]; default: 0; + * Set this bit to update rx register configuration. + */ + uint32_t rx_reg_update:1; + }; + uint32_t val; +} parl_io_reg_update_reg_t; + + +/** Group: PARL_IO Status */ +/** Type of st register + * Parallel IO module status register0. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_ready : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ + uint32_t tx_ready:1; + }; + uint32_t val; +} parl_io_st_reg_t; + + +/** Group: PARL_IO Interrupt Configuration and Status */ +/** Type of int_ena register + * Parallel IO interrupt enable singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_ena:1; + /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_ena:1; + /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable TX_EOF_INT. + */ + uint32_t tx_eof_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_ena_reg_t; + +/** Type of int_raw register + * Parallel IO interrupt raw singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_raw:1; + /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_raw:1; + /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_raw_reg_t; + +/** Type of int_st register + * Parallel IO interrupt singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_st:1; + /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_st:1; + /** tx_eof_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_st_reg_t; + +/** Type of int_clr register + * Parallel IO interrupt clear singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_clr:1; + /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_clr:1; + /** tx_eof_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear TX_EOF_INT. + */ + uint32_t tx_eof_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_clr_reg_t; + + +/** Group: PARL_IO Rx Status0 */ +/** Type of rx_st0 register + * Parallel IO RX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** rx_cnt : RO; bitpos: [12:8]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ + uint32_t rx_cnt:5; + /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ + uint32_t rx_fifo_wr_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st0_reg_t; + + +/** Group: PARL_IO Rx Status1 */ +/** Type of rx_st1 register + * Parallel IO RX status register1 + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ + uint32_t rx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st1_reg_t; + + +/** Group: PARL_IO Tx Status0 */ +/** Type of tx_st0 register + * Parallel IO TX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** tx_cnt : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ + uint32_t tx_cnt:7; + /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ + uint32_t tx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_tx_st0_reg_t; + + +/** Group: PARL_IO Rx Clock Configuration */ +/** Type of rx_clk_cfg register + * Parallel IO RX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Rx core clock. + */ + uint32_t rx_clk_i_inv:1; + /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Rx core clock. + */ + uint32_t rx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_rx_clk_cfg_reg_t; + + +/** Group: PARL_IO Tx Clock Configuration */ +/** Type of tx_clk_cfg register + * Parallel IO TX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Tx core clock. + */ + uint32_t tx_clk_i_inv:1; + /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Tx core clock. + */ + uint32_t tx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_tx_clk_cfg_reg_t; + + +/** Group: PARL_IO Clock Configuration */ +/** Type of clk register + * Parallel IO clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + }; + uint32_t val; +} parl_io_clk_reg_t; + + +/** Group: PARL_IO Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725920; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} parl_io_version_reg_t; + + +typedef struct parl_io_dev_t { + volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; + volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; + volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; + volatile parl_io_rx_start_cfg_reg_t rx_start_cfg; + volatile parl_io_tx_data_cfg_reg_t tx_data_cfg; + volatile parl_io_tx_start_cfg_reg_t tx_start_cfg; + volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg; + volatile parl_io_fifo_cfg_reg_t fifo_cfg; + volatile parl_io_reg_update_reg_t reg_update; + volatile parl_io_st_reg_t st; + volatile parl_io_int_ena_reg_t int_ena; + volatile parl_io_int_raw_reg_t int_raw; + volatile parl_io_int_st_reg_t int_st; + volatile parl_io_int_clr_reg_t int_clr; + volatile parl_io_rx_st0_reg_t rx_st0; + volatile parl_io_rx_st1_reg_t rx_st1; + volatile parl_io_tx_st0_reg_t tx_st0; + volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg; + volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg; + uint32_t reserved_04c[53]; + volatile parl_io_clk_reg_t clk; + uint32_t reserved_124[182]; + volatile parl_io_version_reg_t version; +} parl_io_dev_t; + +extern parl_io_dev_t PARL_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pau_reg.h b/components/soc/esp32c5/include/soc/pau_reg.h new file mode 100644 index 00000000000..207f797c026 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pau_reg.h @@ -0,0 +1,332 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PAU_REGDMA_CONF_REG register + * Peri backup control register + */ +#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) +/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; + * backup error type + */ +#define PAU_FLOW_ERR 0x00000007U +#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) +#define PAU_FLOW_ERR_V 0x00000007U +#define PAU_FLOW_ERR_S 0 +/** PAU_START : WT; bitpos: [3]; default: 0; + * backup start signal + */ +#define PAU_START (BIT(3)) +#define PAU_START_M (PAU_START_V << PAU_START_S) +#define PAU_START_V 0x00000001U +#define PAU_START_S 3 +/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM (BIT(4)) +#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) +#define PAU_TO_MEM_V 0x00000001U +#define PAU_TO_MEM_S 4 +/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; + * Link select + */ +#define PAU_LINK_SEL 0x00000003U +#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) +#define PAU_LINK_SEL_V 0x00000003U +#define PAU_LINK_SEL_S 5 +/** PAU_START_MAC : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ +#define PAU_START_MAC (BIT(7)) +#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) +#define PAU_START_MAC_V 0x00000001U +#define PAU_START_MAC_S 7 +/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM_MAC (BIT(8)) +#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) +#define PAU_TO_MEM_MAC_V 0x00000001U +#define PAU_TO_MEM_MAC_S 8 +/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ +#define PAU_SEL_MAC (BIT(9)) +#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) +#define PAU_SEL_MAC_V 0x00000001U +#define PAU_SEL_MAC_S 9 + +/** PAU_REGDMA_CLK_CONF_REG register + * Clock control register + */ +#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) +/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define PAU_CLK_EN (BIT(0)) +#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) +#define PAU_CLK_EN_V 0x00000001U +#define PAU_CLK_EN_S 0 + +/** PAU_REGDMA_ETM_CTRL_REG register + * ETM start ctrl reg + */ +#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) +/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ +#define PAU_ETM_START_0 (BIT(0)) +#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) +#define PAU_ETM_START_0_V 0x00000001U +#define PAU_ETM_START_0_S 0 +/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ +#define PAU_ETM_START_1 (BIT(1)) +#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) +#define PAU_ETM_START_1_V 0x00000001U +#define PAU_ETM_START_1_S 1 +/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ +#define PAU_ETM_START_2 (BIT(2)) +#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) +#define PAU_ETM_START_2_V 0x00000001U +#define PAU_ETM_START_2_S 2 +/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ +#define PAU_ETM_START_3 (BIT(3)) +#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) +#define PAU_ETM_START_3_V 0x00000001U +#define PAU_ETM_START_3_S 3 + +/** PAU_REGDMA_LINK_0_ADDR_REG register + * link_0_addr + */ +#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) +/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ +#define PAU_LINK_ADDR_0 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) +#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_S 0 + +/** PAU_REGDMA_LINK_1_ADDR_REG register + * Link_1_addr + */ +#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) +/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ +#define PAU_LINK_ADDR_1 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) +#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_S 0 + +/** PAU_REGDMA_LINK_2_ADDR_REG register + * Link_2_addr + */ +#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) +/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ +#define PAU_LINK_ADDR_2 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) +#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_S 0 + +/** PAU_REGDMA_LINK_3_ADDR_REG register + * Link_3_addr + */ +#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) +/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ +#define PAU_LINK_ADDR_3 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) +#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_S 0 + +/** PAU_REGDMA_LINK_MAC_ADDR_REG register + * Link_mac_addr + */ +#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) +/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ +#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) +#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_S 0 + +/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register + * current link addr + */ +#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) +/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ +#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) +#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_S 0 + +/** PAU_REGDMA_BACKUP_ADDR_REG register + * Backup addr + */ +#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) +/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ +#define PAU_BACKUP_ADDR 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) +#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_S 0 + +/** PAU_REGDMA_MEM_ADDR_REG register + * mem addr + */ +#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) +/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ +#define PAU_MEM_ADDR 0xFFFFFFFFU +#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) +#define PAU_MEM_ADDR_V 0xFFFFFFFFU +#define PAU_MEM_ADDR_S 0 + +/** PAU_REGDMA_BKP_CONF_REG register + * backup config + */ +#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) +/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ +#define PAU_READ_INTERVAL 0x0000007FU +#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) +#define PAU_READ_INTERVAL_V 0x0000007FU +#define PAU_READ_INTERVAL_S 0 +/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ +#define PAU_LINK_TOUT_THRES 0x000003FFU +#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) +#define PAU_LINK_TOUT_THRES_V 0x000003FFU +#define PAU_LINK_TOUT_THRES_S 7 +/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ +#define PAU_BURST_LIMIT 0x0000001FU +#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) +#define PAU_BURST_LIMIT_V 0x0000001FU +#define PAU_BURST_LIMIT_S 17 +/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ +#define PAU_BACKUP_TOUT_THRES 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) +#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_S 22 + +/** PAU_INT_ENA_REG register + * Read only register for error and done + */ +#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30) +/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ENA (BIT(0)) +#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) +#define PAU_DONE_INT_ENA_V 0x00000001U +#define PAU_DONE_INT_ENA_S 0 +/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ENA (BIT(1)) +#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) +#define PAU_ERROR_INT_ENA_V 0x00000001U +#define PAU_ERROR_INT_ENA_S 1 + +/** PAU_INT_RAW_REG register + * Read only register for error and done + */ +#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34) +/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_RAW (BIT(0)) +#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) +#define PAU_DONE_INT_RAW_V 0x00000001U +#define PAU_DONE_INT_RAW_S 0 +/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_RAW (BIT(1)) +#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) +#define PAU_ERROR_INT_RAW_V 0x00000001U +#define PAU_ERROR_INT_RAW_S 1 + +/** PAU_INT_CLR_REG register + * Read only register for error and done + */ +#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38) +/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_CLR (BIT(0)) +#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) +#define PAU_DONE_INT_CLR_V 0x00000001U +#define PAU_DONE_INT_CLR_S 0 +/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_CLR (BIT(1)) +#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) +#define PAU_ERROR_INT_CLR_V 0x00000001U +#define PAU_ERROR_INT_CLR_S 1 + +/** PAU_INT_ST_REG register + * Read only register for error and done + */ +#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c) +/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ST (BIT(0)) +#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) +#define PAU_DONE_INT_ST_V 0x00000001U +#define PAU_DONE_INT_ST_S 0 +/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ST (BIT(1)) +#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) +#define PAU_ERROR_INT_ST_V 0x00000001U +#define PAU_ERROR_INT_ST_S 1 + +/** PAU_DATE_REG register + * Date register. + */ +#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) +/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608; + * REGDMA date information/ REGDMA version information. + */ +#define PAU_DATE 0x0FFFFFFFU +#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) +#define PAU_DATE_V 0x0FFFFFFFU +#define PAU_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pau_struct.h b/components/soc/esp32c5/include/soc/pau_struct.h new file mode 100644 index 00000000000..16c9c62767e --- /dev/null +++ b/components/soc/esp32c5/include/soc/pau_struct.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of regdma_conf register + * Peri backup control register + */ +typedef union { + struct { + /** flow_err : RO; bitpos: [2:0]; default: 0; + * backup error type + */ + uint32_t flow_err:3; + /** start : WT; bitpos: [3]; default: 0; + * backup start signal + */ + uint32_t start:1; + /** to_mem : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem:1; + /** link_sel : R/W; bitpos: [6:5]; default: 0; + * Link select + */ + uint32_t link_sel:2; + /** start_mac : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ + uint32_t start_mac:1; + /** to_mem_mac : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem_mac:1; + /** sel_mac : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ + uint32_t sel_mac:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pau_regdma_conf_reg_t; + +/** Type of regdma_clk_conf register + * Clock control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pau_regdma_clk_conf_reg_t; + +/** Type of regdma_etm_ctrl register + * ETM start ctrl reg + */ +typedef union { + struct { + /** etm_start_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ + uint32_t etm_start_0:1; + /** etm_start_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ + uint32_t etm_start_1:1; + /** etm_start_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ + uint32_t etm_start_2:1; + /** etm_start_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ + uint32_t etm_start_3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pau_regdma_etm_ctrl_reg_t; + +/** Type of regdma_link_0_addr register + * link_0_addr + */ +typedef union { + struct { + /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ + uint32_t link_addr_0:32; + }; + uint32_t val; +} pau_regdma_link_0_addr_reg_t; + +/** Type of regdma_link_1_addr register + * Link_1_addr + */ +typedef union { + struct { + /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ + uint32_t link_addr_1:32; + }; + uint32_t val; +} pau_regdma_link_1_addr_reg_t; + +/** Type of regdma_link_2_addr register + * Link_2_addr + */ +typedef union { + struct { + /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ + uint32_t link_addr_2:32; + }; + uint32_t val; +} pau_regdma_link_2_addr_reg_t; + +/** Type of regdma_link_3_addr register + * Link_3_addr + */ +typedef union { + struct { + /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ + uint32_t link_addr_3:32; + }; + uint32_t val; +} pau_regdma_link_3_addr_reg_t; + +/** Type of regdma_link_mac_addr register + * Link_mac_addr + */ +typedef union { + struct { + /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ + uint32_t link_addr_mac:32; + }; + uint32_t val; +} pau_regdma_link_mac_addr_reg_t; + +/** Type of regdma_current_link_addr register + * current link addr + */ +typedef union { + struct { + /** current_link_addr : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ + uint32_t current_link_addr:32; + }; + uint32_t val; +} pau_regdma_current_link_addr_reg_t; + +/** Type of regdma_backup_addr register + * Backup addr + */ +typedef union { + struct { + /** backup_addr : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ + uint32_t backup_addr:32; + }; + uint32_t val; +} pau_regdma_backup_addr_reg_t; + +/** Type of regdma_mem_addr register + * mem addr + */ +typedef union { + struct { + /** mem_addr : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ + uint32_t mem_addr:32; + }; + uint32_t val; +} pau_regdma_mem_addr_reg_t; + +/** Type of regdma_bkp_conf register + * backup config + */ +typedef union { + struct { + /** read_interval : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ + uint32_t read_interval:7; + /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ + uint32_t link_tout_thres:10; + /** burst_limit : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ + uint32_t burst_limit:5; + /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ + uint32_t backup_tout_thres:10; + }; + uint32_t val; +} pau_regdma_bkp_conf_reg_t; + +/** Type of int_ena register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_ena:1; + /** error_int_ena : R/W; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_ena_reg_t; + +/** Type of int_raw register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_raw:1; + /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_raw_reg_t; + +/** Type of int_clr register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_clr:1; + /** error_int_clr : WT; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_clr_reg_t; + +/** Type of int_st register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_st:1; + /** error_int_st : RO; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36708608; + * REGDMA date information/ REGDMA version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pau_date_reg_t; + + +typedef struct pau_dev_t { + volatile pau_regdma_conf_reg_t regdma_conf; + volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; + volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; + volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr; + volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr; + volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr; + volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr; + volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr; + volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr; + volatile pau_regdma_backup_addr_reg_t regdma_backup_addr; + volatile pau_regdma_mem_addr_reg_t regdma_mem_addr; + volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf; + volatile pau_int_ena_reg_t int_ena; + volatile pau_int_raw_reg_t int_raw; + volatile pau_int_clr_reg_t int_clr; + volatile pau_int_st_reg_t int_st; + uint32_t reserved_040[239]; + volatile pau_date_reg_t date; +} pau_dev_t; + +extern pau_dev_t PAU; + +#ifndef __cplusplus +_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcnt_reg.h b/components/soc/esp32c5/include/soc/pcnt_reg.h new file mode 100644 index 00000000000..7cbfedda60b --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcnt_reg.h @@ -0,0 +1,1346 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCNT_U0_CONF0_REG register + * Configuration register 0 for unit 0 + */ +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) +/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U0 0x000003FFU +#define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) +#define PCNT_FILTER_THRES_U0_V 0x000003FFU +#define PCNT_FILTER_THRES_U0_S 0 +/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 0's input filter. + */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) +#define PCNT_FILTER_EN_U0_V 0x00000001U +#define PCNT_FILTER_EN_U0_S 10 +/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 0's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) +#define PCNT_THR_ZERO_EN_U0_V 0x00000001U +#define PCNT_THR_ZERO_EN_U0_S 11 +/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) +#define PCNT_THR_H_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U0_S 12 +/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) +#define PCNT_THR_L_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U0_S 13 +/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 0's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) +#define PCNT_THR_THRES0_EN_U0_V 0x00000001U +#define PCNT_THR_THRES0_EN_U0_S 14 +/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 0's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) +#define PCNT_THR_THRES1_EN_U0_V 0x00000001U +#define PCNT_THR_THRES1_EN_U0_S 15 +/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) +#define PCNT_CH0_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_S 16 +/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U0 0x00000003U +#define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) +#define PCNT_CH0_POS_MODE_U0_V 0x00000003U +#define PCNT_CH0_POS_MODE_U0_S 18 +/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) +#define PCNT_CH1_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_S 24 +/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U0 0x00000003U +#define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) +#define PCNT_CH1_POS_MODE_U0_V 0x00000003U +#define PCNT_CH1_POS_MODE_U0_S 26 +/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_S 30 + +/** PCNT_U0_CONF1_REG register + * Configuration register 1 for unit 0 + */ +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) +/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 0. + */ +#define PCNT_CNT_THRES0_U0 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) +#define PCNT_CNT_THRES0_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_S 0 +/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 0. + */ +#define PCNT_CNT_THRES1_U0 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) +#define PCNT_CNT_THRES1_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_S 16 + +/** PCNT_U0_CONF2_REG register + * Configuration register 2 for unit 0 + */ +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) +/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 0. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) +#define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_S 0 +/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 0. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) +#define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_S 16 + +/** PCNT_U1_CONF0_REG register + * Configuration register 0 for unit 1 + */ +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc) +/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U1 0x000003FFU +#define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) +#define PCNT_FILTER_THRES_U1_V 0x000003FFU +#define PCNT_FILTER_THRES_U1_S 0 +/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 1's input filter. + */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) +#define PCNT_FILTER_EN_U1_V 0x00000001U +#define PCNT_FILTER_EN_U1_S 10 +/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 1's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) +#define PCNT_THR_ZERO_EN_U1_V 0x00000001U +#define PCNT_THR_ZERO_EN_U1_S 11 +/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) +#define PCNT_THR_H_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U1_S 12 +/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) +#define PCNT_THR_L_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U1_S 13 +/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 1's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) +#define PCNT_THR_THRES0_EN_U1_V 0x00000001U +#define PCNT_THR_THRES0_EN_U1_S 14 +/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 1's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) +#define PCNT_THR_THRES1_EN_U1_V 0x00000001U +#define PCNT_THR_THRES1_EN_U1_S 15 +/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) +#define PCNT_CH0_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_S 16 +/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U1 0x00000003U +#define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) +#define PCNT_CH0_POS_MODE_U1_V 0x00000003U +#define PCNT_CH0_POS_MODE_U1_S 18 +/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) +#define PCNT_CH1_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_S 24 +/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U1 0x00000003U +#define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) +#define PCNT_CH1_POS_MODE_U1_V 0x00000003U +#define PCNT_CH1_POS_MODE_U1_S 26 +/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_S 30 + +/** PCNT_U1_CONF1_REG register + * Configuration register 1 for unit 1 + */ +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) +/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 1. + */ +#define PCNT_CNT_THRES0_U1 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) +#define PCNT_CNT_THRES0_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_S 0 +/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 1. + */ +#define PCNT_CNT_THRES1_U1 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) +#define PCNT_CNT_THRES1_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_S 16 + +/** PCNT_U1_CONF2_REG register + * Configuration register 2 for unit 1 + */ +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) +/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 1. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) +#define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_S 0 +/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 1. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) +#define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_S 16 + +/** PCNT_U2_CONF0_REG register + * Configuration register 0 for unit 2 + */ +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) +/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U2 0x000003FFU +#define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) +#define PCNT_FILTER_THRES_U2_V 0x000003FFU +#define PCNT_FILTER_THRES_U2_S 0 +/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 2's input filter. + */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) +#define PCNT_FILTER_EN_U2_V 0x00000001U +#define PCNT_FILTER_EN_U2_S 10 +/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 2's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) +#define PCNT_THR_ZERO_EN_U2_V 0x00000001U +#define PCNT_THR_ZERO_EN_U2_S 11 +/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) +#define PCNT_THR_H_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U2_S 12 +/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) +#define PCNT_THR_L_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U2_S 13 +/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 2's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) +#define PCNT_THR_THRES0_EN_U2_V 0x00000001U +#define PCNT_THR_THRES0_EN_U2_S 14 +/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 2's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) +#define PCNT_THR_THRES1_EN_U2_V 0x00000001U +#define PCNT_THR_THRES1_EN_U2_S 15 +/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) +#define PCNT_CH0_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_S 16 +/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U2 0x00000003U +#define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) +#define PCNT_CH0_POS_MODE_U2_V 0x00000003U +#define PCNT_CH0_POS_MODE_U2_S 18 +/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) +#define PCNT_CH1_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_S 24 +/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U2 0x00000003U +#define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) +#define PCNT_CH1_POS_MODE_U2_V 0x00000003U +#define PCNT_CH1_POS_MODE_U2_S 26 +/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_S 30 + +/** PCNT_U2_CONF1_REG register + * Configuration register 1 for unit 2 + */ +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c) +/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 2. + */ +#define PCNT_CNT_THRES0_U2 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) +#define PCNT_CNT_THRES0_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_S 0 +/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 2. + */ +#define PCNT_CNT_THRES1_U2 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) +#define PCNT_CNT_THRES1_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_S 16 + +/** PCNT_U2_CONF2_REG register + * Configuration register 2 for unit 2 + */ +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) +/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 2. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) +#define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_S 0 +/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 2. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) +#define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_S 16 + +/** PCNT_U3_CONF0_REG register + * Configuration register 0 for unit 3 + */ +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) +/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U3 0x000003FFU +#define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) +#define PCNT_FILTER_THRES_U3_V 0x000003FFU +#define PCNT_FILTER_THRES_U3_S 0 +/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 3's input filter. + */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) +#define PCNT_FILTER_EN_U3_V 0x00000001U +#define PCNT_FILTER_EN_U3_S 10 +/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 3's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) +#define PCNT_THR_ZERO_EN_U3_V 0x00000001U +#define PCNT_THR_ZERO_EN_U3_S 11 +/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) +#define PCNT_THR_H_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U3_S 12 +/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) +#define PCNT_THR_L_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U3_S 13 +/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 3's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) +#define PCNT_THR_THRES0_EN_U3_V 0x00000001U +#define PCNT_THR_THRES0_EN_U3_S 14 +/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 3's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) +#define PCNT_THR_THRES1_EN_U3_V 0x00000001U +#define PCNT_THR_THRES1_EN_U3_S 15 +/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) +#define PCNT_CH0_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_S 16 +/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U3 0x00000003U +#define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) +#define PCNT_CH0_POS_MODE_U3_V 0x00000003U +#define PCNT_CH0_POS_MODE_U3_S 18 +/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) +#define PCNT_CH1_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_S 24 +/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U3 0x00000003U +#define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) +#define PCNT_CH1_POS_MODE_U3_V 0x00000003U +#define PCNT_CH1_POS_MODE_U3_S 26 +/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_S 30 + +/** PCNT_U3_CONF1_REG register + * Configuration register 1 for unit 3 + */ +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) +/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 3. + */ +#define PCNT_CNT_THRES0_U3 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) +#define PCNT_CNT_THRES0_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_S 0 +/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 3. + */ +#define PCNT_CNT_THRES1_U3 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) +#define PCNT_CNT_THRES1_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_S 16 + +/** PCNT_U3_CONF2_REG register + * Configuration register 2 for unit 3 + */ +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c) +/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 3. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) +#define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_S 0 +/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 3. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) +#define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_S 16 + +/** PCNT_U0_CNT_REG register + * Counter value for unit 0 + */ +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) +/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 0. + */ +#define PCNT_PULSE_CNT_U0 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) +#define PCNT_PULSE_CNT_U0_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_S 0 + +/** PCNT_U1_CNT_REG register + * Counter value for unit 1 + */ +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) +/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 1. + */ +#define PCNT_PULSE_CNT_U1 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) +#define PCNT_PULSE_CNT_U1_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_S 0 + +/** PCNT_U2_CNT_REG register + * Counter value for unit 2 + */ +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) +/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 2. + */ +#define PCNT_PULSE_CNT_U2 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) +#define PCNT_PULSE_CNT_U2_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_S 0 + +/** PCNT_U3_CNT_REG register + * Counter value for unit 3 + */ +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c) +/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 3. + */ +#define PCNT_PULSE_CNT_U3 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) +#define PCNT_PULSE_CNT_U3_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_S 0 + +/** PCNT_INT_RAW_REG register + * Interrupt raw status register + */ +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) +/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 + +/** PCNT_INT_ST_REG register + * Interrupt status register + */ +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) +/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 + +/** PCNT_INT_ENA_REG register + * Interrupt enable register + */ +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) +/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 + +/** PCNT_INT_CLR_REG register + * Interrupt clear register + */ +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c) +/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 + +/** PCNT_U0_STATUS_REG register + * PNCT UNIT0 status register + */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) +/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U0 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 + +/** PCNT_U1_STATUS_REG register + * PNCT UNIT1 status register + */ +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) +/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U1 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 + +/** PCNT_U2_STATUS_REG register + * PNCT UNIT2 status register + */ +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) +/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U2 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 + +/** PCNT_U3_STATUS_REG register + * PNCT UNIT3 status register + */ +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c) +/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U3 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 + +/** PCNT_CTRL_REG register + * Control register for all counters + */ +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) +/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) +#define PCNT_PULSE_CNT_RST_U0_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U0_S 0 +/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) +#define PCNT_CNT_PAUSE_U0_V 0x00000001U +#define PCNT_CNT_PAUSE_U0_S 1 +/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) +#define PCNT_PULSE_CNT_RST_U1_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U1_S 2 +/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) +#define PCNT_CNT_PAUSE_U1_V 0x00000001U +#define PCNT_CNT_PAUSE_U1_S 3 +/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) +#define PCNT_PULSE_CNT_RST_U2_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U2_S 4 +/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) +#define PCNT_CNT_PAUSE_U2_V 0x00000001U +#define PCNT_CNT_PAUSE_U2_S 5 +/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) +#define PCNT_PULSE_CNT_RST_U3_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U3_S 6 +/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) +#define PCNT_CNT_PAUSE_U3_V 0x00000001U +#define PCNT_CNT_PAUSE_U3_S 7 +/** PCNT_DALTA_CHANGE_EN_U0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U0 (BIT(8)) +#define PCNT_DALTA_CHANGE_EN_U0_M (PCNT_DALTA_CHANGE_EN_U0_V << PCNT_DALTA_CHANGE_EN_U0_S) +#define PCNT_DALTA_CHANGE_EN_U0_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U0_S 8 +/** PCNT_DALTA_CHANGE_EN_U1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U1 (BIT(9)) +#define PCNT_DALTA_CHANGE_EN_U1_M (PCNT_DALTA_CHANGE_EN_U1_V << PCNT_DALTA_CHANGE_EN_U1_S) +#define PCNT_DALTA_CHANGE_EN_U1_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U1_S 9 +/** PCNT_DALTA_CHANGE_EN_U2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U2 (BIT(10)) +#define PCNT_DALTA_CHANGE_EN_U2_M (PCNT_DALTA_CHANGE_EN_U2_V << PCNT_DALTA_CHANGE_EN_U2_S) +#define PCNT_DALTA_CHANGE_EN_U2_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U2_S 10 +/** PCNT_DALTA_CHANGE_EN_U3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U3 (BIT(11)) +#define PCNT_DALTA_CHANGE_EN_U3_M (PCNT_DALTA_CHANGE_EN_U3_V << PCNT_DALTA_CHANGE_EN_U3_S) +#define PCNT_DALTA_CHANGE_EN_U3_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U3_S 11 +/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) +#define PCNT_CLK_EN_V 0x00000001U +#define PCNT_CLK_EN_S 16 + +/** PCNT_U3_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U3_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x64) +/** PCNT_CNT_STEP_U3 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 3. + */ +#define PCNT_CNT_STEP_U3 0x0000FFFFU +#define PCNT_CNT_STEP_U3_M (PCNT_CNT_STEP_U3_V << PCNT_CNT_STEP_U3_S) +#define PCNT_CNT_STEP_U3_V 0x0000FFFFU +#define PCNT_CNT_STEP_U3_S 0 +/** PCNT_CNT_STEP_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 3. + */ +#define PCNT_CNT_STEP_LIM_U3 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U3_M (PCNT_CNT_STEP_LIM_U3_V << PCNT_CNT_STEP_LIM_U3_S) +#define PCNT_CNT_STEP_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U3_S 16 + +/** PCNT_U2_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U2_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x68) +/** PCNT_CNT_STEP_U2 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 2. + */ +#define PCNT_CNT_STEP_U2 0x0000FFFFU +#define PCNT_CNT_STEP_U2_M (PCNT_CNT_STEP_U2_V << PCNT_CNT_STEP_U2_S) +#define PCNT_CNT_STEP_U2_V 0x0000FFFFU +#define PCNT_CNT_STEP_U2_S 0 +/** PCNT_CNT_STEP_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 2. + */ +#define PCNT_CNT_STEP_LIM_U2 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U2_M (PCNT_CNT_STEP_LIM_U2_V << PCNT_CNT_STEP_LIM_U2_S) +#define PCNT_CNT_STEP_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U2_S 16 + +/** PCNT_U1_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U1_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x6c) +/** PCNT_CNT_STEP_U1 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 1. + */ +#define PCNT_CNT_STEP_U1 0x0000FFFFU +#define PCNT_CNT_STEP_U1_M (PCNT_CNT_STEP_U1_V << PCNT_CNT_STEP_U1_S) +#define PCNT_CNT_STEP_U1_V 0x0000FFFFU +#define PCNT_CNT_STEP_U1_S 0 +/** PCNT_CNT_STEP_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 1. + */ +#define PCNT_CNT_STEP_LIM_U1 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U1_M (PCNT_CNT_STEP_LIM_U1_V << PCNT_CNT_STEP_LIM_U1_S) +#define PCNT_CNT_STEP_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U1_S 16 + +/** PCNT_U0_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U0_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x70) +/** PCNT_CNT_STEP_U0 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 0. + */ +#define PCNT_CNT_STEP_U0 0x0000FFFFU +#define PCNT_CNT_STEP_U0_M (PCNT_CNT_STEP_U0_V << PCNT_CNT_STEP_U0_S) +#define PCNT_CNT_STEP_U0_V 0x0000FFFFU +#define PCNT_CNT_STEP_U0_S 0 +/** PCNT_CNT_STEP_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 0. + */ +#define PCNT_CNT_STEP_LIM_U0 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U0_M (PCNT_CNT_STEP_LIM_U0_V << PCNT_CNT_STEP_LIM_U0_S) +#define PCNT_CNT_STEP_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U0_S 16 + +/** PCNT_DATE_REG register + * PCNT version control register + */ +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) +/** PCNT_DATE : R/W; bitpos: [31:0]; default: 571021568; + * This is the PCNT version control register. + */ +#define PCNT_DATE 0xFFFFFFFFU +#define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) +#define PCNT_DATE_V 0xFFFFFFFFU +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/include/soc/pcnt_struct.h new file mode 100644 index 00000000000..ce929f709e4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcnt_struct.h @@ -0,0 +1,442 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres_un : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ + uint32_t filter_thres_un:10; + /** filter_en_un : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en_un:1; + /** thr_zero_en_un : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en_un:1; + /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ + uint32_t thr_h_lim_en_un:1; + /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ + uint32_t thr_l_lim_en_un:1; + /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en_un:1; + /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en_un:1; + /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_neg_mode_un:2; + /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_pos_mode_un:2; + /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode_un:2; + /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode_un:2; + /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_neg_mode_un:2; + /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_pos_mode_un:2; + /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode_un:2; + /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode_un:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit n. + */ + uint32_t cnt_thres0_un:16; + /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit n. + */ + uint32_t cnt_thres1_un:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_h_lim_un:16; + /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_l_lim_un:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ + uint32_t dalta_change_en_u0:1; + /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ + uint32_t dalta_change_en_u1:1; + /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ + uint32_t dalta_change_en_u2:1; + /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ + uint32_t dalta_change_en_u3:1; + uint32_t reserved_12:4; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + +/** Type of change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 3. + */ + uint32_t cnt_step:16; + /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 3. + */ + uint32_t cnt_step_lim:16; + }; + uint32_t val; +} pcnt_un_change_conf_reg_t; + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit n. + */ + uint32_t pulse_cnt_un:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ + uint32_t cnt_thr_zero_mode_un:2; + /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres1_lat_un:1; + /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres0_lat_un:1; + /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ + uint32_t cnt_thr_l_lim_lat_un:1; + /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ + uint32_t cnt_thr_h_lim_lat_un:1; + /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_Un when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ + uint32_t cnt_thr_zero_lat_un:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 571021568; + * This is the PCNT version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + + +typedef struct pcnt_dev_t { + volatile struct { + pcnt_un_conf0_reg_t conf0; + pcnt_un_conf1_reg_t conf1; + pcnt_un_conf2_reg_t conf2; + } conf_unit[4]; + volatile pcnt_un_cnt_reg_t un_cnt[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t un_status[4]; + volatile pcnt_ctrl_reg_t ctrl; + volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210 + uint32_t reserved_074[34]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcr_reg.h b/components/soc/esp32c5/include/soc/pcr_reg.h new file mode 100644 index 00000000000..58cebfed8c6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcr_reg.h @@ -0,0 +1,2462 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(3)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 3 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 +/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; + * set this field to select clock-source. + */ +#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) +#define PCR_MSPI_FUNC_CLK_SEL_V 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_S 8 +/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ +#define PCR_MSPI_FUNC_CLK_EN (BIT(10)) +#define PCR_MSPI_FUNC_CLK_EN_M (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S) +#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U +#define PCR_MSPI_FUNC_CLK_EN_S 10 +/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; + * Set 0 to reset axi_clock domain of mspi module + */ +#define PCR_MSPI_AXI_RST_EN (BIT(11)) +#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) +#define PCR_MSPI_AXI_RST_EN_V 0x00000001U +#define PCR_MSPI_AXI_RST_EN_S 11 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_TWAI1_CONF_REG register + * TWAI1 configuration register + */ +#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ +#define PCR_TWAI1_CLK_EN (BIT(0)) +#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) +#define PCR_TWAI1_CLK_EN_V 0x00000001U +#define PCR_TWAI1_CLK_EN_S 0 +/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ +#define PCR_TWAI1_RST_EN (BIT(1)) +#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) +#define PCR_TWAI1_RST_EN_V 0x00000001U +#define PCR_TWAI1_RST_EN_S 1 +/** PCR_TWAI1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai1 module + */ +#define PCR_TWAI1_READY (BIT(2)) +#define PCR_TWAI1_READY_M (PCR_TWAI1_READY_V << PCR_TWAI1_READY_S) +#define PCR_TWAI1_READY_V 0x00000001U +#define PCR_TWAI1_READY_S 2 + +/** PCR_TWAI1_FUNC_CLK_CONF_REG register + * TWAI1_FUNC_CLK configuration register + */ +#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) +#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_SEL_S 20 +/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ +#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) +#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: XTAL, 1(default): FOSC, 2: 80MHz + */ +#define PCR_RMT_SCLK_SEL 0x00000003U +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000003U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(22)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 22 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(2)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 2 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 +/** PCR_PWM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ +#define PCR_PWM_READY (BIT(2)) +#define PCR_PWM_READY_M (PCR_PWM_READY_V << PCR_PWM_READY_S) +#define PCR_PWM_READY_V 0x00000001U +#define PCR_PWM_READY_S 2 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ +#define PCR_SPI2_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_M (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S) +#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_S 12 +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 +/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ +#define PCR_MEM_MONITOR_READY (BIT(2)) +#define PCR_MEM_MONITOR_READY_M (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S) +#define PCR_MEM_MONITOR_READY_V 0x00000001U +#define PCR_MEM_MONITOR_READY_S 2 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(2)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: FOSC, 2: 160M_PLL, 3: + * 240M_PLL. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_60M_CLK_EN (BIT(4)) +#define PCR_PLL_60M_CLK_EN_M (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S) +#define PCR_PLL_60M_CLK_EN_V 0x00000001U +#define PCR_PLL_60M_CLK_EN_S 4 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(5)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 5 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(6)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 6 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(7)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 7 +/** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_12M_CLK_EN (BIT(8)) +#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) +#define PCR_PLL_12M_CLK_EN_V 0x00000001U +#define PCR_PLL_12M_CLK_EN_S 8 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ +#define PCR_CLK_320M_OEN (BIT(6)) +#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) +#define PCR_CLK_320M_OEN_V 0x00000001U +#define PCR_CLK_320M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; + * Reserved + */ +#define PCR_CLK40X_BB_OEN (BIT(9)) +#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) +#define PCR_CLK40X_BB_OEN_V 0x00000001U +#define PCR_CLK40X_BB_OEN_S 9 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(10)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 10 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [2:0]; default: 7; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000007U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000007U +#define PCR_ROM_FORCE_PU_S 0 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [5:3]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000007U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000007U +#define PCR_ROM_FORCE_PD_S 3 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [8:6]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_S 6 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000000FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000000FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [13:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000000FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000000FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [23:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 20 + +/** PCR_SEC_CONF_REG register + * xxxx + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 +/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset sec module + */ +#define PCR_SEC_RST_EN (BIT(2)) +#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) +#define PCR_SEC_RST_EN_V 0x00000001U +#define PCR_SEC_RST_EN_S 2 + +/** PCR_BUS_CLK_UPDATE_REG register + * xxxx + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * xxxx + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) +#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 +/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_EN (BIT(8)) +#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) +#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U +#define PCR_PWDET_SAR_CLK_EN_S 8 + +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x154) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + +/** PCR_USB_OTG_CONF_REG register + * USB_OTG configuration register + */ +#define PCR_USB_OTG_CONF_REG (DR_REG_PCR_BASE + 0x158) +/** PCR_USB_OTG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_otg bus clock + */ +#define PCR_USB_OTG_CLK_EN (BIT(0)) +#define PCR_USB_OTG_CLK_EN_M (PCR_USB_OTG_CLK_EN_V << PCR_USB_OTG_CLK_EN_S) +#define PCR_USB_OTG_CLK_EN_V 0x00000001U +#define PCR_USB_OTG_CLK_EN_S 0 +/** PCR_USB_OTG_ADP_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_otg core adp + */ +#define PCR_USB_OTG_ADP_RST_EN (BIT(1)) +#define PCR_USB_OTG_ADP_RST_EN_M (PCR_USB_OTG_ADP_RST_EN_V << PCR_USB_OTG_ADP_RST_EN_S) +#define PCR_USB_OTG_ADP_RST_EN_V 0x00000001U +#define PCR_USB_OTG_ADP_RST_EN_S 1 +/** PCR_USB_OTG_MISC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset usb_otg misc + */ +#define PCR_USB_OTG_MISC_RST_EN (BIT(2)) +#define PCR_USB_OTG_MISC_RST_EN_M (PCR_USB_OTG_MISC_RST_EN_V << PCR_USB_OTG_MISC_RST_EN_S) +#define PCR_USB_OTG_MISC_RST_EN_V 0x00000001U +#define PCR_USB_OTG_MISC_RST_EN_S 2 +/** PCR_USB_OTG_GLOBAL_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset usb_otg module + */ +#define PCR_USB_OTG_GLOBAL_RST_EN (BIT(3)) +#define PCR_USB_OTG_GLOBAL_RST_EN_M (PCR_USB_OTG_GLOBAL_RST_EN_V << PCR_USB_OTG_GLOBAL_RST_EN_S) +#define PCR_USB_OTG_GLOBAL_RST_EN_V 0x00000001U +#define PCR_USB_OTG_GLOBAL_RST_EN_S 3 + +/** PCR_USB_OTG_CLK_CONF_REG register + * USB_OTG func clk configuration register + */ +#define PCR_USB_OTG_CLK_CONF_REG (DR_REG_PCR_BASE + 0x15c) +/** PCR_USB_OTG_PHY_REFCLK_SEL : R/W; bitpos: [20]; default: 1; + * Set 1 to sel 12m pll clock, set 0 to sel pad clock + */ +#define PCR_USB_OTG_PHY_REFCLK_SEL (BIT(20)) +#define PCR_USB_OTG_PHY_REFCLK_SEL_M (PCR_USB_OTG_PHY_REFCLK_SEL_V << PCR_USB_OTG_PHY_REFCLK_SEL_S) +#define PCR_USB_OTG_PHY_REFCLK_SEL_V 0x00000001U +#define PCR_USB_OTG_PHY_REFCLK_SEL_S 20 +/** PCR_USB_OTG_PHY_REFCLK_EN : R/W; bitpos: [21]; default: 1; + * Set 1 to enable usb_otg_phy_refclk clock + */ +#define PCR_USB_OTG_PHY_REFCLK_EN (BIT(21)) +#define PCR_USB_OTG_PHY_REFCLK_EN_M (PCR_USB_OTG_PHY_REFCLK_EN_V << PCR_USB_OTG_PHY_REFCLK_EN_S) +#define PCR_USB_OTG_PHY_REFCLK_EN_V 0x00000001U +#define PCR_USB_OTG_PHY_REFCLK_EN_S 21 +/** PCR_USB_OTG_ADP_CLK_SEL : R/W; bitpos: [23:22]; default: 0; + * Set 0 to sel clock from gpio_matrix, set 1 to sel osc32k, set 2 to sel xtal32k, set + * 3 to sel ext32k + */ +#define PCR_USB_OTG_ADP_CLK_SEL 0x00000003U +#define PCR_USB_OTG_ADP_CLK_SEL_M (PCR_USB_OTG_ADP_CLK_SEL_V << PCR_USB_OTG_ADP_CLK_SEL_S) +#define PCR_USB_OTG_ADP_CLK_SEL_V 0x00000003U +#define PCR_USB_OTG_ADP_CLK_SEL_S 22 +/** PCR_USB_OTG_ADP_CLK_EN : R/W; bitpos: [24]; default: 1; + * Set 1 to enable usb_otg_adp_clk clock + */ +#define PCR_USB_OTG_ADP_CLK_EN (BIT(24)) +#define PCR_USB_OTG_ADP_CLK_EN_M (PCR_USB_OTG_ADP_CLK_EN_V << PCR_USB_OTG_ADP_CLK_EN_S) +#define PCR_USB_OTG_ADP_CLK_EN_V 0x00000001U +#define PCR_USB_OTG_ADP_CLK_EN_S 24 + +/** PCR_BS_CONF_REG register + * BS configuration register + */ +#define PCR_BS_CONF_REG (DR_REG_PCR_BASE + 0x160) +/** PCR_BS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable bs clock + */ +#define PCR_BS_CLK_EN (BIT(0)) +#define PCR_BS_CLK_EN_M (PCR_BS_CLK_EN_V << PCR_BS_CLK_EN_S) +#define PCR_BS_CLK_EN_V 0x00000001U +#define PCR_BS_CLK_EN_S 0 +/** PCR_BS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset bs module + */ +#define PCR_BS_RST_EN (BIT(1)) +#define PCR_BS_RST_EN_M (PCR_BS_RST_EN_V << PCR_BS_RST_EN_S) +#define PCR_BS_RST_EN_V 0x00000001U +#define PCR_BS_RST_EN_S 1 + +/** PCR_BS_FUNC_CONF_REG register + * BS_FUNC_CLK configuration register + */ +#define PCR_BS_FUNC_CONF_REG (DR_REG_PCR_BASE + 0x164) +/** PCR_BS_TX_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset bs tx module + */ +#define PCR_BS_TX_RST_EN (BIT(23)) +#define PCR_BS_TX_RST_EN_M (PCR_BS_TX_RST_EN_V << PCR_BS_TX_RST_EN_S) +#define PCR_BS_TX_RST_EN_V 0x00000001U +#define PCR_BS_TX_RST_EN_S 23 +/** PCR_BS_RX_RST_EN : R/W; bitpos: [24]; default: 0; + * Set 0 to reset bs rx module + */ +#define PCR_BS_RX_RST_EN (BIT(24)) +#define PCR_BS_RX_RST_EN_M (PCR_BS_RX_RST_EN_V << PCR_BS_RX_RST_EN_S) +#define PCR_BS_RX_RST_EN_V 0x00000001U +#define PCR_BS_RX_RST_EN_S 24 + +/** PCR_TIMERGROUP_WDT_CONF_REG register + * TIMERGROUP_WDT configuration register + */ +#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x168) +/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_RST_EN (BIT(0)) +#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) +#define PCR_TG0_WDT_RST_EN_V 0x00000001U +#define PCR_TG0_WDT_RST_EN_S 0 +/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_RST_EN (BIT(1)) +#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) +#define PCR_TG1_WDT_RST_EN_V 0x00000001U +#define PCR_TG1_WDT_RST_EN_S 1 + +/** PCR_TIMERGROUP_XTAL_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x16c) +/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 xtal clock domain + */ +#define PCR_TG0_XTAL_RST_EN (BIT(0)) +#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) +#define PCR_TG0_XTAL_RST_EN_V 0x00000001U +#define PCR_TG0_XTAL_RST_EN_S 0 +/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 xtal clock domain + */ +#define PCR_TG1_XTAL_RST_EN (BIT(1)) +#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) +#define PCR_TG1_XTAL_RST_EN_V 0x00000001U +#define PCR_TG1_XTAL_RST_EN_S 1 + +/** PCR_KM_CONF_REG register + * Key Manager configuration register + */ +#define PCR_KM_CONF_REG (DR_REG_PCR_BASE + 0x170) +/** PCR_KM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable km clock + */ +#define PCR_KM_CLK_EN (BIT(0)) +#define PCR_KM_CLK_EN_M (PCR_KM_CLK_EN_V << PCR_KM_CLK_EN_S) +#define PCR_KM_CLK_EN_V 0x00000001U +#define PCR_KM_CLK_EN_S 0 +/** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset km module + */ +#define PCR_KM_RST_EN (BIT(1)) +#define PCR_KM_RST_EN_M (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S) +#define PCR_KM_RST_EN_V 0x00000001U +#define PCR_KM_RST_EN_S 1 +/** PCR_KM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset km module + */ +#define PCR_KM_READY (BIT(2)) +#define PCR_KM_READY_M (PCR_KM_READY_V << PCR_KM_READY_S) +#define PCR_KM_READY_V 0x00000001U +#define PCR_KM_READY_S 2 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 36720976; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/include/soc/pcr_struct.h new file mode 100644 index 00000000000..2f9176a9b11 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcr_struct.h @@ -0,0 +1,2233 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of uart0_conf register + * UART0 configuration register + */ +typedef union { + struct { + /** uart0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ + uint32_t uart0_clk_en:1; + /** uart0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ + uint32_t uart0_rst_en:1; + /** uart0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ + uint32_t uart0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_conf_reg_t; + +/** Type of uart0_sclk_conf register + * UART0_SCLK configuration register + */ +typedef union { + struct { + /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_a:6; + /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_b:6; + /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_num:8; + /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ + uint32_t uart0_sclk_sel:2; + /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart0_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart0_sclk_conf_reg_t; + +/** Type of uart0_pd_ctrl register + * UART0 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ + uint32_t uart0_mem_force_pu:1; + /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ + uint32_t uart0_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_pd_ctrl_reg_t; + +/** Type of uart1_conf register + * UART1 configuration register + */ +typedef union { + struct { + /** uart1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ + uint32_t uart1_clk_en:1; + /** uart1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ + uint32_t uart1_rst_en:1; + /** uart1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ + uint32_t uart1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_conf_reg_t; + +/** Type of uart1_sclk_conf register + * UART1_SCLK configuration register + */ +typedef union { + struct { + /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_a:6; + /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_b:6; + /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_num:8; + /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ + uint32_t uart1_sclk_sel:2; + /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart1_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart1_sclk_conf_reg_t; + +/** Type of uart1_pd_ctrl register + * UART1 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ + uint32_t uart1_mem_force_pu:1; + /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ + uint32_t uart1_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_pd_ctrl_reg_t; + +/** Type of mspi_conf register + * MSPI configuration register + */ +typedef union { + struct { + /** mspi_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ + uint32_t mspi_clk_en:1; + /** mspi_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ + uint32_t mspi_rst_en:1; + /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ + uint32_t mspi_pll_clk_en:1; + /** mspi_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ + uint32_t mspi_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_mspi_conf_reg_t; + +/** Type of mspi_clk_conf register + * MSPI_CLK configuration register + */ +typedef union { + struct { + /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ + uint32_t mspi_fast_div_num:8; + /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; + * set this field to select clock-source. + */ + uint32_t mspi_func_clk_sel:2; + /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ + uint32_t mspi_func_clk_en:1; + /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; + * Set 0 to reset axi_clock domain of mspi module + */ + uint32_t mspi_axi_rst_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} pcr_mspi_clk_conf_reg_t; + +/** Type of i2c_conf register + * I2C configuration register + */ +typedef union { + struct { + /** i2c_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ + uint32_t i2c_clk_en:1; + /** i2c_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ + uint32_t i2c_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_i2c_conf_reg_t; + +/** Type of i2c_sclk_conf register + * I2C_SCLK configuration register + */ +typedef union { + struct { + /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_a:6; + /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_b:6; + /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_num:8; + /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t i2c_sclk_sel:1; + uint32_t reserved_21:1; + /** i2c_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ + uint32_t i2c_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2c_sclk_conf_reg_t; + +/** Type of twai0_conf register + * TWAI0 configuration register + */ +typedef union { + struct { + /** twai0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ + uint32_t twai0_clk_en:1; + /** twai0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ + uint32_t twai0_rst_en:1; + /** twai0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ + uint32_t twai0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_twai0_conf_reg_t; + +/** Type of twai0_func_clk_conf register + * TWAI0_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai0_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ + uint32_t twai0_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai0_func_clk_conf_reg_t; + +/** Type of twai1_conf register + * TWAI1 configuration register + */ +typedef union { + struct { + /** twai1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ + uint32_t twai1_clk_en:1; + /** twai1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ + uint32_t twai1_rst_en:1; + /** twai1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset twai1 module + */ + uint32_t twai1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_twai1_conf_reg_t; + +/** Type of twai1_func_clk_conf register + * TWAI1_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai1_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ + uint32_t twai1_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai1_func_clk_conf_reg_t; + +/** Type of uhci_conf register + * UHCI configuration register + */ +typedef union { + struct { + /** uhci_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ + uint32_t uhci_clk_en:1; + /** uhci_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ + uint32_t uhci_rst_en:1; + /** uhci_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ + uint32_t uhci_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uhci_conf_reg_t; + +/** Type of rmt_conf register + * RMT configuration register + */ +typedef union { + struct { + /** rmt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ + uint32_t rmt_clk_en:1; + /** rmt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ + uint32_t rmt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_rmt_conf_reg_t; + +/** Type of rmt_sclk_conf register + * RMT_SCLK configuration register + */ +typedef union { + struct { + /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_a:6; + /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_b:6; + /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_num:8; + /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: XTAL, 1(default): FOSC, 2: 80MHz + */ + uint32_t rmt_sclk_sel:2; + /** rmt_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ + uint32_t rmt_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_rmt_sclk_conf_reg_t; + +/** Type of ledc_conf register + * LEDC configuration register + */ +typedef union { + struct { + /** ledc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ + uint32_t ledc_clk_en:1; + /** ledc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ + uint32_t ledc_rst_en:1; + /** ledc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ + uint32_t ledc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ledc_conf_reg_t; + +/** Type of ledc_sclk_conf register + * LEDC_SCLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ + uint32_t ledc_sclk_sel:2; + /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ + uint32_t ledc_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_ledc_sclk_conf_reg_t; + +/** Type of timergroup0_conf register + * TIMERGROUP0 configuration register + */ +typedef union { + struct { + /** tg0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ + uint32_t tg0_clk_en:1; + /** tg0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ + uint32_t tg0_rst_en:1; + /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ + uint32_t tg0_wdt_ready:1; + /** tg0_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ + uint32_t tg0_timer0_ready:1; + /** tg0_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg0_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup0_conf_reg_t; + +/** Type of timergroup0_timer_clk_conf register + * TIMERGROUP0_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_timer_clk_sel:2; + /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ + uint32_t tg0_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_timer_clk_conf_reg_t; + +/** Type of timergroup0_wdt_clk_conf register + * TIMERGROUP0_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_wdt_clk_sel:2; + /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg0_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_wdt_clk_conf_reg_t; + +/** Type of timergroup1_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ + uint32_t tg1_clk_en:1; + /** tg1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ + uint32_t tg1_rst_en:1; + /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ + uint32_t tg1_wdt_ready:1; + /** tg1_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ + uint32_t tg1_timer0_ready:1; + /** tg1_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg1_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup1_conf_reg_t; + +/** Type of timergroup1_timer_clk_conf register + * TIMERGROUP1_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_timer_clk_sel:2; + /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ + uint32_t tg1_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_timer_clk_conf_reg_t; + +/** Type of timergroup1_wdt_clk_conf register + * TIMERGROUP1_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_wdt_clk_sel:2; + /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg1_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_wdt_clk_conf_reg_t; + +/** Type of systimer_conf register + * SYSTIMER configuration register + */ +typedef union { + struct { + /** systimer_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ + uint32_t systimer_clk_en:1; + /** systimer_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ + uint32_t systimer_rst_en:1; + /** systimer_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ + uint32_t systimer_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_systimer_conf_reg_t; + +/** Type of systimer_func_clk_conf register + * SYSTIMER_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t systimer_func_clk_sel:1; + uint32_t reserved_21:1; + /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ + uint32_t systimer_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_systimer_func_clk_conf_reg_t; + +/** Type of i2s_conf register + * I2S configuration register + */ +typedef union { + struct { + /** i2s_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ + uint32_t i2s_clk_en:1; + /** i2s_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ + uint32_t i2s_rst_en:1; + /** i2s_rx_ready : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ + uint32_t i2s_rx_ready:1; + /** i2s_tx_ready : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ + uint32_t i2s_tx_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_i2s_conf_reg_t; + +/** Type of i2s_tx_clkm_conf register + * I2S_TX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t i2s_tx_clkm_div_num:8; + /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ + uint32_t i2s_tx_clkm_sel:2; + /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ + uint32_t i2s_tx_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2s_tx_clkm_conf_reg_t; + +/** Type of i2s_tx_clkm_div_conf register + * I2S_TX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_tx_clkm_div_z:9; + /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_tx_clkm_div_y:9; + /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_tx_clkm_div_x:9; + /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_tx_clkm_div_conf_reg_t; + +/** Type of i2s_rx_clkm_conf register + * I2S_RX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ + uint32_t i2s_rx_clkm_div_num:8; + /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ + uint32_t i2s_rx_clkm_sel:2; + /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ + uint32_t i2s_rx_clkm_en:1; + /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ + uint32_t i2s_mclk_sel:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_i2s_rx_clkm_conf_reg_t; + +/** Type of i2s_rx_clkm_div_conf register + * I2S_RX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_rx_clkm_div_z:9; + /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_rx_clkm_div_y:9; + /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_rx_clkm_div_x:9; + /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_rx_clkm_div_conf_reg_t; + +/** Type of saradc_conf register + * SARADC configuration register + */ +typedef union { + struct { + /** saradc_clk_en : R/W; bitpos: [0]; default: 1; + * no use + */ + uint32_t saradc_clk_en:1; + /** saradc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ + uint32_t saradc_rst_en:1; + /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ + uint32_t saradc_reg_clk_en:1; + /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ + uint32_t saradc_reg_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_saradc_conf_reg_t; + +/** Type of saradc_clkm_conf register + * SARADC_CLKM configuration register + */ +typedef union { + struct { + /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t saradc_clkm_sel:2; + /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ + uint32_t saradc_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_saradc_clkm_conf_reg_t; + +/** Type of tsens_clk_conf register + * TSENS_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ + uint32_t tsens_clk_sel:1; + uint32_t reserved_21:1; + /** tsens_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ + uint32_t tsens_clk_en:1; + /** tsens_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ + uint32_t tsens_rst_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_tsens_clk_conf_reg_t; + +/** Type of usb_device_conf register + * USB_DEVICE configuration register + */ +typedef union { + struct { + /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ + uint32_t usb_device_clk_en:1; + /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ + uint32_t usb_device_rst_en:1; + /** usb_device_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ + uint32_t usb_device_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_usb_device_conf_reg_t; + +/** Type of intmtx_conf register + * INTMTX configuration register + */ +typedef union { + struct { + /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ + uint32_t intmtx_clk_en:1; + /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ + uint32_t intmtx_rst_en:1; + /** intmtx_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ + uint32_t intmtx_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_intmtx_conf_reg_t; + +/** Type of pcnt_conf register + * PCNT configuration register + */ +typedef union { + struct { + /** pcnt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ + uint32_t pcnt_clk_en:1; + /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ + uint32_t pcnt_rst_en:1; + /** pcnt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ + uint32_t pcnt_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_pcnt_conf_reg_t; + +/** Type of etm_conf register + * ETM configuration register + */ +typedef union { + struct { + /** etm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ + uint32_t etm_clk_en:1; + /** etm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ + uint32_t etm_rst_en:1; + /** etm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ + uint32_t etm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_etm_conf_reg_t; + +/** Type of pwm_conf register + * PWM configuration register + */ +typedef union { + struct { + /** pwm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ + uint32_t pwm_clk_en:1; + /** pwm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ + uint32_t pwm_rst_en:1; + /** pwm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ + uint32_t pwm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_pwm_conf_reg_t; + +/** Type of pwm_clk_conf register + * PWM_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** pwm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ + uint32_t pwm_div_num:8; + /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ + uint32_t pwm_clkm_sel:2; + /** pwm_clkm_en : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ + uint32_t pwm_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pwm_clk_conf_reg_t; + +/** Type of parl_io_conf register + * PARL_IO configuration register + */ +typedef union { + struct { + /** parl_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ + uint32_t parl_clk_en:1; + /** parl_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ + uint32_t parl_rst_en:1; + /** parl_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ + uint32_t parl_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_parl_io_conf_reg_t; + +/** Type of parl_clk_rx_conf register + * PARL_CLK_RX configuration register + */ +typedef union { + struct { + /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ + uint32_t parl_clk_rx_div_num:16; + /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_rx_sel:2; + /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ + uint32_t parl_clk_rx_en:1; + /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ + uint32_t parl_rx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_rx_conf_reg_t; + +/** Type of parl_clk_tx_conf register + * PARL_CLK_TX configuration register + */ +typedef union { + struct { + /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ + uint32_t parl_clk_tx_div_num:16; + /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_tx_sel:2; + /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ + uint32_t parl_clk_tx_en:1; + /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ + uint32_t parl_tx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_tx_conf_reg_t; + +/** Type of pvt_monitor_conf register + * PVT_MONITOR configuration register + */ +typedef union { + struct { + /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ + uint32_t pvt_monitor_clk_en:1; + /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ + uint32_t pvt_monitor_rst_en:1; + /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ + uint32_t pvt_monitor_site1_clk_en:1; + /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ + uint32_t pvt_monitor_site2_clk_en:1; + /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ + uint32_t pvt_monitor_site3_clk_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_pvt_monitor_conf_reg_t; + +/** Type of pvt_monitor_func_clk_conf register + * PVT_MONITOR function clock configuration register + */ +typedef union { + struct { + /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ + uint32_t pvt_monitor_func_clk_div_num:4; + uint32_t reserved_4:16; + /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ + uint32_t pvt_monitor_func_clk_sel:1; + uint32_t reserved_21:1; + /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ + uint32_t pvt_monitor_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pvt_monitor_func_clk_conf_reg_t; + +/** Type of gdma_conf register + * GDMA configuration register + */ +typedef union { + struct { + /** gdma_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ + uint32_t gdma_clk_en:1; + /** gdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ + uint32_t gdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_gdma_conf_reg_t; + +/** Type of spi2_conf register + * SPI2 configuration register + */ +typedef union { + struct { + /** spi2_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ + uint32_t spi2_clk_en:1; + /** spi2_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ + uint32_t spi2_rst_en:1; + /** spi2_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ + uint32_t spi2_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_spi2_conf_reg_t; + +/** Type of spi2_clkm_conf register + * SPI2_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** spi2_clkm_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ + uint32_t spi2_clkm_div_num:8; + /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t spi2_clkm_sel:2; + /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ + uint32_t spi2_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_spi2_clkm_conf_reg_t; + +/** Type of aes_conf register + * AES configuration register + */ +typedef union { + struct { + /** aes_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ + uint32_t aes_clk_en:1; + /** aes_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ + uint32_t aes_rst_en:1; + /** aes_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ + uint32_t aes_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_aes_conf_reg_t; + +/** Type of sha_conf register + * SHA configuration register + */ +typedef union { + struct { + /** sha_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ + uint32_t sha_clk_en:1; + /** sha_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ + uint32_t sha_rst_en:1; + /** sha_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ + uint32_t sha_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sha_conf_reg_t; + +/** Type of rsa_conf register + * RSA configuration register + */ +typedef union { + struct { + /** rsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ + uint32_t rsa_clk_en:1; + /** rsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ + uint32_t rsa_rst_en:1; + /** rsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ + uint32_t rsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_conf_reg_t; + +/** Type of rsa_pd_ctrl register + * RSA power control register + */ +typedef union { + struct { + /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ + uint32_t rsa_mem_pd:1; + /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ + uint32_t rsa_mem_force_pu:1; + /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ + uint32_t rsa_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_pd_ctrl_reg_t; + +/** Type of ecc_conf register + * ECC configuration register + */ +typedef union { + struct { + /** ecc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ + uint32_t ecc_clk_en:1; + /** ecc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ + uint32_t ecc_rst_en:1; + /** ecc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ + uint32_t ecc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_conf_reg_t; + +/** Type of ecc_pd_ctrl register + * ECC power control register + */ +typedef union { + struct { + /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ + uint32_t ecc_mem_pd:1; + /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ + uint32_t ecc_mem_force_pu:1; + /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ + uint32_t ecc_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_pd_ctrl_reg_t; + +/** Type of ds_conf register + * DS configuration register + */ +typedef union { + struct { + /** ds_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ + uint32_t ds_clk_en:1; + /** ds_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ + uint32_t ds_rst_en:1; + /** ds_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ + uint32_t ds_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ds_conf_reg_t; + +/** Type of hmac_conf register + * HMAC configuration register + */ +typedef union { + struct { + /** hmac_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ + uint32_t hmac_clk_en:1; + /** hmac_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ + uint32_t hmac_rst_en:1; + /** hmac_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ + uint32_t hmac_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_hmac_conf_reg_t; + +/** Type of ecdsa_conf register + * ECDSA configuration register + */ +typedef union { + struct { + /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ + uint32_t ecdsa_clk_en:1; + /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ + uint32_t ecdsa_rst_en:1; + /** ecdsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ + uint32_t ecdsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecdsa_conf_reg_t; + +/** Type of iomux_conf register + * IOMUX configuration register + */ +typedef union { + struct { + /** iomux_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ + uint32_t iomux_clk_en:1; + /** iomux_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ + uint32_t iomux_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_iomux_conf_reg_t; + +/** Type of iomux_clk_conf register + * IOMUX_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t iomux_func_clk_sel:2; + /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ + uint32_t iomux_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_iomux_clk_conf_reg_t; + +/** Type of mem_monitor_conf register + * MEM_MONITOR configuration register + */ +typedef union { + struct { + /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ + uint32_t mem_monitor_clk_en:1; + /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ + uint32_t mem_monitor_rst_en:1; + /** mem_monitor_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ + uint32_t mem_monitor_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_mem_monitor_conf_reg_t; + +/** Type of regdma_conf register + * REGDMA configuration register + */ +typedef union { + struct { + /** regdma_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ + uint32_t regdma_clk_en:1; + /** regdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ + uint32_t regdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_regdma_conf_reg_t; + +/** Type of trace_conf register + * TRACE configuration register + */ +typedef union { + struct { + /** trace_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ + uint32_t trace_clk_en:1; + /** trace_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ + uint32_t trace_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_trace_conf_reg_t; + +/** Type of assist_conf register + * ASSIST configuration register + */ +typedef union { + struct { + /** assist_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ + uint32_t assist_clk_en:1; + /** assist_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ + uint32_t assist_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_assist_conf_reg_t; + +/** Type of cache_conf register + * CACHE configuration register + */ +typedef union { + struct { + /** cache_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ + uint32_t cache_clk_en:1; + /** cache_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ + uint32_t cache_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_cache_conf_reg_t; + +/** Type of modem_conf register + * MODEM_APB configuration register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** modem_rst_en : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ + uint32_t modem_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_modem_conf_reg_t; + +/** Type of timeout_conf register + * TIMEOUT configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ + uint32_t cpu_timeout_rst_en:1; + /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ + uint32_t hp_timeout_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_timeout_conf_reg_t; + +/** Type of sysclk_conf register + * SYSCLK configuration register + */ +typedef union { + struct { + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; + /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: FOSC, 2: 160M_PLL, 3: + * 240M_PLL. + */ + uint32_t soc_clk_sel:2; + uint32_t reserved_18:6; + /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ + uint32_t clk_xtal_freq:7; + uint32_t reserved_31:1; + }; + uint32_t val; +} pcr_sysclk_conf_reg_t; + +/** Type of cpu_waiti_conf register + * CPU_WAITI configuration register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ + uint32_t cpu_wait_mode_force_on:1; + /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ + uint32_t cpu_waiti_delay_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_waiti_conf_reg_t; + +/** Type of cpu_freq_conf register + * CPU_FREQ configuration register + */ +typedef union { + struct { + /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ + uint32_t cpu_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_freq_conf_reg_t; + +/** Type of ahb_freq_conf register + * AHB_FREQ configuration register + */ +typedef union { + struct { + /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ + uint32_t ahb_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_ahb_freq_conf_reg_t; + +/** Type of apb_freq_conf register + * APB_FREQ configuration register + */ +typedef union { + struct { + /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ + uint32_t apb_decrease_div_num:8; + /** apb_div_num : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ + uint32_t apb_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_apb_freq_conf_reg_t; + +/** Type of pll_div_clk_en register + * SPLL DIV clock-gating configuration register + */ +typedef union { + struct { + /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_240m_clk_en:1; + /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_160m_clk_en:1; + /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_120m_clk_en:1; + /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_80m_clk_en:1; + /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_60m_clk_en:1; + /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_48m_clk_en:1; + /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_40m_clk_en:1; + /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_20m_clk_en:1; + /** pll_12m_clk_en : R/W; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_12m_clk_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pll_div_clk_en_reg_t; + +/** Type of ctrl_clk_out_en register + * CLK_OUT_EN configuration register + */ +typedef union { + struct { + /** clk20_oen : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ + uint32_t clk20_oen:1; + /** clk22_oen : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ + uint32_t clk22_oen:1; + /** clk44_oen : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ + uint32_t clk44_oen:1; + /** clk_bb_oen : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ + uint32_t clk_bb_oen:1; + /** clk80_oen : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ + uint32_t clk80_oen:1; + /** clk160_oen : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ + uint32_t clk160_oen:1; + /** clk_320m_oen : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ + uint32_t clk_320m_oen:1; + /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1; + * Reserved + */ + uint32_t clk_adc_inf_oen:1; + /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t clk_dac_cpu_oen:1; + /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t clk40x_bb_oen:1; + /** clk_xtal_oen : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ + uint32_t clk_xtal_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} pcr_ctrl_clk_out_en_reg_t; + +/** Type of ctrl_tick_conf register + * TICK configuration register + */ +typedef union { + struct { + /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ + uint32_t xtal_tick_num:8; + /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ + uint32_t fosc_tick_num:8; + /** tick_enable : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ + uint32_t tick_enable:1; + /** rst_tick_cnt : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ + uint32_t rst_tick_cnt:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_ctrl_tick_conf_reg_t; + +/** Type of ctrl_32k_conf register + * 32KHz clock configuration register + */ +typedef union { + struct { + /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ + uint32_t clk_32k_sel:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_ctrl_32k_conf_reg_t; + +/** Type of sram_power_conf_0 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** rom_force_pu : R/W; bitpos: [2:0]; default: 7; + * Set this bit to force power up ROM + */ + uint32_t rom_force_pu:3; + /** rom_force_pd : R/W; bitpos: [5:3]; default: 0; + * Set this bit to force power down ROM. + */ + uint32_t rom_force_pd:3; + /** rom_clkgate_force_on : R/W; bitpos: [8:6]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ + uint32_t rom_clkgate_force_on:3; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_sram_power_conf_0_reg_t; + +/** Type of sram_power_conf_1 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** sram_force_pu : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ + uint32_t sram_force_pu:4; + uint32_t reserved_4:6; + /** sram_force_pd : R/W; bitpos: [13:10]; default: 0; + * Set this bit to force power down SRAM. + */ + uint32_t sram_force_pd:4; + uint32_t reserved_14:6; + /** sram_clkgate_force_on : R/W; bitpos: [23:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ + uint32_t sram_clkgate_force_on:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_sram_power_conf_1_reg_t; + +/** Type of sec_conf register + * xxxx + */ +typedef union { + struct { + /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ + uint32_t sec_clk_sel:2; + /** sec_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset sec module + */ + uint32_t sec_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sec_conf_reg_t; + +/** Type of bus_clk_update register + * xxxx + */ +typedef union { + struct { + /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t bus_clock_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_bus_clk_update_reg_t; + +/** Type of sar_clk_div register + * xxxx + */ +typedef union { + struct { + /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ + uint32_t sar2_clk_div_num:8; + /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ + uint32_t sar1_clk_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_sar_clk_div_reg_t; + +/** Type of pwdet_sar_clk_conf register + * xxxx + */ +typedef union { + struct { + /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ + uint32_t pwdet_sar_clk_div_num:8; + /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; + * xxxx + */ + uint32_t pwdet_sar_clk_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pwdet_sar_clk_conf_reg_t; + +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register + */ +typedef union { + struct { + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sdio_slave_conf_reg_t; + +/** Type of usb_otg_conf register + * USB_OTG configuration register + */ +typedef union { + struct { + /** usb_otg_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_otg bus clock + */ + uint32_t usb_otg_clk_en:1; + /** usb_otg_adp_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_otg core adp + */ + uint32_t usb_otg_adp_rst_en:1; + /** usb_otg_misc_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset usb_otg misc + */ + uint32_t usb_otg_misc_rst_en:1; + /** usb_otg_global_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset usb_otg module + */ + uint32_t usb_otg_global_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_usb_otg_conf_reg_t; + +/** Type of usb_otg_clk_conf register + * USB_OTG func clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** usb_otg_phy_refclk_sel : R/W; bitpos: [20]; default: 1; + * Set 1 to sel 12m pll clock, set 0 to sel pad clock + */ + uint32_t usb_otg_phy_refclk_sel:1; + /** usb_otg_phy_refclk_en : R/W; bitpos: [21]; default: 1; + * Set 1 to enable usb_otg_phy_refclk clock + */ + uint32_t usb_otg_phy_refclk_en:1; + /** usb_otg_adp_clk_sel : R/W; bitpos: [23:22]; default: 0; + * Set 0 to sel clock from gpio_matrix, set 1 to sel osc32k, set 2 to sel xtal32k, set + * 3 to sel ext32k + */ + uint32_t usb_otg_adp_clk_sel:2; + /** usb_otg_adp_clk_en : R/W; bitpos: [24]; default: 1; + * Set 1 to enable usb_otg_adp_clk clock + */ + uint32_t usb_otg_adp_clk_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} pcr_usb_otg_clk_conf_reg_t; + +/** Type of bs_conf register + * BS configuration register + */ +typedef union { + struct { + /** bs_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable bs clock + */ + uint32_t bs_clk_en:1; + /** bs_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset bs module + */ + uint32_t bs_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_bs_conf_reg_t; + +/** Type of bs_func_conf register + * BS_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bs_tx_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset bs tx module + */ + uint32_t bs_tx_rst_en:1; + /** bs_rx_rst_en : R/W; bitpos: [24]; default: 0; + * Set 0 to reset bs rx module + */ + uint32_t bs_rx_rst_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} pcr_bs_func_conf_reg_t; + +/** Type of timergroup_wdt_conf register + * TIMERGROUP_WDT configuration register + */ +typedef union { + struct { + /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 wdt module + */ + uint32_t tg0_wdt_rst_en:1; + /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 wdt module + */ + uint32_t tg1_wdt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup_wdt_conf_reg_t; + +/** Type of timergroup_xtal_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 xtal clock domain + */ + uint32_t tg0_xtal_rst_en:1; + /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 xtal clock domain + */ + uint32_t tg1_xtal_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup_xtal_conf_reg_t; + +/** Type of km_conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** km_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable km clock + */ + uint32_t km_clk_en:1; + /** km_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset km module + */ + uint32_t km_rst_en:1; + /** km_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset km module + */ + uint32_t km_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_km_conf_reg_t; + + +/** Group: Frequency Statistics Register */ +/** Type of sysclk_freq_query_0 register + * SYSCLK frequency query 0 register + */ +typedef union { + struct { + /** fosc_freq : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ + uint32_t fosc_freq:8; + /** pll_freq : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ + uint32_t pll_freq:10; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_sysclk_freq_query_0_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720976; + * PCR version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_date_reg_t; + + +typedef struct pcr_dev_t { + volatile pcr_uart0_conf_reg_t uart0_conf; + volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; + volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; + volatile pcr_uart1_conf_reg_t uart1_conf; + volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; + volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; + volatile pcr_mspi_conf_reg_t mspi_conf; + volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; + volatile pcr_i2c_conf_reg_t i2c_conf; + volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; + volatile pcr_twai0_conf_reg_t twai0_conf; + volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; + volatile pcr_twai1_conf_reg_t twai1_conf; + volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf; + volatile pcr_uhci_conf_reg_t uhci_conf; + volatile pcr_rmt_conf_reg_t rmt_conf; + volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; + volatile pcr_ledc_conf_reg_t ledc_conf; + volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; + volatile pcr_timergroup0_conf_reg_t timergroup0_conf; + volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; + volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; + volatile pcr_timergroup1_conf_reg_t timergroup1_conf; + volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; + volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; + volatile pcr_systimer_conf_reg_t systimer_conf; + volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; + volatile pcr_i2s_conf_reg_t i2s_conf; + volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; + volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; + volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; + volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; + volatile pcr_saradc_conf_reg_t saradc_conf; + volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; + volatile pcr_usb_device_conf_reg_t usb_device_conf; + volatile pcr_intmtx_conf_reg_t intmtx_conf; + volatile pcr_pcnt_conf_reg_t pcnt_conf; + volatile pcr_etm_conf_reg_t etm_conf; + volatile pcr_pwm_conf_reg_t pwm_conf; + volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf; + volatile pcr_parl_io_conf_reg_t parl_io_conf; + volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf; + volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf; + volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; + volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; + volatile pcr_gdma_conf_reg_t gdma_conf; + volatile pcr_spi2_conf_reg_t spi2_conf; + volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; + volatile pcr_aes_conf_reg_t aes_conf; + volatile pcr_sha_conf_reg_t sha_conf; + volatile pcr_rsa_conf_reg_t rsa_conf; + volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + volatile pcr_ecc_conf_reg_t ecc_conf; + volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; + volatile pcr_ds_conf_reg_t ds_conf; + volatile pcr_hmac_conf_reg_t hmac_conf; + volatile pcr_ecdsa_conf_reg_t ecdsa_conf; + volatile pcr_iomux_conf_reg_t iomux_conf; + volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; + volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf; + volatile pcr_regdma_conf_reg_t regdma_conf; + volatile pcr_trace_conf_reg_t trace_conf; + volatile pcr_assist_conf_reg_t assist_conf; + volatile pcr_cache_conf_reg_t cache_conf; + volatile pcr_modem_conf_reg_t modem_conf; + volatile pcr_timeout_conf_reg_t timeout_conf; + volatile pcr_sysclk_conf_reg_t sysclk_conf; + volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; + volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; + volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; + volatile pcr_apb_freq_conf_reg_t apb_freq_conf; + volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; + volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; + volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; + volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf; + volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; + volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; + volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; + volatile pcr_sec_conf_reg_t sec_conf; + uint32_t reserved_140[2]; + volatile pcr_bus_clk_update_reg_t bus_clk_update; + volatile pcr_sar_clk_div_reg_t sar_clk_div; + volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + volatile pcr_usb_otg_conf_reg_t usb_otg_conf; + volatile pcr_usb_otg_clk_conf_reg_t usb_otg_clk_conf; + volatile pcr_bs_conf_reg_t bs_conf; + volatile pcr_bs_func_conf_reg_t bs_func_conf; + volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf; + volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf; + volatile pcr_km_conf_reg_t km_conf; + uint32_t reserved_174[930]; + volatile pcr_date_reg_t date; +} pcr_dev_t; + +extern pcr_dev_t PCR; + +#ifndef __cplusplus +_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/periph_defs.h b/components/soc/esp32c5/include/soc/periph_defs.h new file mode 100644 index 00000000000..33268bcb1da --- /dev/null +++ b/components/soc/esp32c5/include/soc/periph_defs.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/interrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5-PERIPH] (inherit from C6) + +typedef enum { + /* HP peripherals */ + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, // USB Serial Jtag + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_MSPI0_MODULE, //SPI0 + PERIPH_MSPI1_MODULE, //SPI1 + PERIPH_GPSPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_TWAI1_MODULE, + PERIPH_RNG_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_MCPWM0_MODULE, + PERIPH_ETM_MODULE, + PERIPH_PARLIO_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_TEMPSENSOR_MODULE, + PERIPH_ASSIST_DEBUG_MODULE, + PERIPH_INT_MATRIX_MODULE, + PERIPH_PVT_MONITOR_MODULE, + PERIPH_BITSCRAMBLER_MODULE, + PERIPH_KEY_MANAGE_MODULE, + PERIPH_ECDSA_MODULE, + PERIPH_MEM_MONITOR_MODULE, + PERIPH_TEE_MODULE, + PERIPH_HP_APM_MODULE, + /* LP peripherals */ + PERIPH_LP_I2C0_MODULE, + PERIPH_LP_UART0_MODULE, + PERIPH_LP_TEE_MODULE, + PERIPH_LP_APM_MODULE, + PERIPH_LP_ANA_PERI_MODULE, + PERIPH_LP_PERI_MODULE, + PERIPH_HUK_MODULE, + PERIPH_OTP_DEBUG_MODULE, + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, + PERIPH_ANA_I2C_MASTER_MODULE, + PERIPH_MODEM_ETM_MODULE, + PERIPH_MODEM_ADC_COMMON_FE_MODULE, + PERIPH_MODULE_MAX + /* !!! Don't append soc modules here !!! */ +} periph_module_t; + +#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pmu_reg.h b/components/soc/esp32c5/include/soc/pmu_reg.h new file mode 100644 index 00000000000..0713f07ed40 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pmu_reg.h @@ -0,0 +1,3359 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 27 +/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) +#define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) +#define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 30 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) +#define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_S 26 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) +#define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_S 26 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 26 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 27 +/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) +#define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) +#define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BB_I2C_S 28 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 30 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) +#define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_S 26 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) +#define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_S 26 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 2 +/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) +#define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) +#define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BB_I2C_S 3 +/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 +/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) +#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) +#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_S 5 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(6)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 27 +/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) +#define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) +#define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BB_I2C_S 28 +/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 +/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) +#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_S 9 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_S 16 +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 +/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 6 +/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_PD_MASK 0x0000001FU +#define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) +#define PMU_PD_TOP_PD_MASK_V 0x0000001FU +#define PMU_PD_TOP_PD_MASK_S 27 + +/** PMU_POWER_PD_HPAON_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_RESET (BIT(0)) +#define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) +#define PMU_FORCE_HP_AON_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_RESET_S 0 +/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_ISO (BIT(1)) +#define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) +#define PMU_FORCE_HP_AON_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_ISO_S 1 +/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_PU (BIT(2)) +#define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) +#define PMU_FORCE_HP_AON_PU_V 0x00000001U +#define PMU_FORCE_HP_AON_PU_S 2 +/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) +#define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_RESET_S 3 +/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) +#define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_ISO_S 4 +/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_PD (BIT(5)) +#define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) +#define PMU_FORCE_HP_AON_PD_V 0x00000001U +#define PMU_FORCE_HP_AON_PD_S 5 +/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_MASK 0x0000001FU +#define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) +#define PMU_PD_HP_AON_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_MASK_S 6 +/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_PD_MASK 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) +#define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_S 27 + +/** PMU_POWER_PD_HPCPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 6 +/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_PD_MASK 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) +#define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_S 27 + +/** PMU_POWER_PD_HPWIFI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_RESET (BIT(0)) +#define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) +#define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_RESET_S 0 +/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_ISO (BIT(1)) +#define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) +#define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_ISO_S 1 +/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PU (BIT(2)) +#define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) +#define PMU_FORCE_HP_WIFI_PU_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PU_S 2 +/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) +#define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_RESET_S 3 +/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) +#define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_ISO_S 4 +/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PD (BIT(5)) +#define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) +#define PMU_FORCE_HP_WIFI_PD_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PD_S 5 +/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) +#define PMU_PD_HP_WIFI_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_S 6 +/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) +#define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_S 27 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_MEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_S 0 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_S 4 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_S 24 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_S 28 + +/** PMU_POWER_PD_MEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) +#define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_S 0 +/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) +#define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_S 5 +/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) +#define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_S 10 +/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) +#define PMU_PD_HP_MEM2_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_S 17 +/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) +#define PMU_PD_HP_MEM1_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_S 22 +/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) +#define PMU_PD_HP_MEM0_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_VDD_SPI_CNTL_REG register + * need_des + */ +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; + * need_des + */ +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; + * need_des + */ +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) +#define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_S 0 +/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) +#define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_XPD_TC5G_I2C : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_XPD_TC5G_I2C (BIT(24)) +#define PMU_XPD_TC5G_I2C_M (PMU_XPD_TC5G_I2C_V << PMU_XPD_TC5G_I2C_S) +#define PMU_XPD_TC5G_I2C_V 0x00000001U +#define PMU_XPD_TC5G_I2C_S 24 +/** PMU_XPD_RX5G_I2C : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_XPD_RX5G_I2C (BIT(25)) +#define PMU_XPD_RX5G_I2C_M (PMU_XPD_RX5G_I2C_V << PMU_XPD_RX5G_I2C_S) +#define PMU_XPD_RX5G_I2C_V 0x00000001U +#define PMU_XPD_RX5G_I2C_S 25 +/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_PERIF_I2C_RSTB (BIT(26)) +#define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) +#define PMU_PERIF_I2C_RSTB_V 0x00000001U +#define PMU_PERIF_I2C_RSTB_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_TXRF_I2C (BIT(28)) +#define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) +#define PMU_XPD_TXRF_I2C_V 0x00000001U +#define PMU_XPD_TXRF_I2C_S 28 +/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_PBUS (BIT(29)) +#define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) +#define PMU_XPD_RFRX_PBUS_V 0x00000001U +#define PMU_XPD_RFRX_PBUS_S 29 +/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_CKGEN_I2C (BIT(30)) +#define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) +#define PMU_XPD_CKGEN_I2C_V 0x00000001U +#define PMU_XPD_CKGEN_I2C_S 30 +/** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_XPD_PLL_I2C (BIT(31)) +#define PMU_XPD_PLL_I2C_M (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S) +#define PMU_XPD_PLL_I2C_V 0x00000001U +#define PMU_XPD_PLL_I2C_S 31 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) +#define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) +#define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; + * need_des + */ +#define PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) +#define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) +#define PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_BACKUP_ST_STATE_S 13 +/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) +#define PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_LP_PWR_ST_STATE_S 18 +/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) +#define PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) +#define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) +#define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_BBPLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 1 +/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) +#define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_SYS_CLK_SLP_SEL_STATE_S 15 +/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) +#define PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_S 16 +/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) +#define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_SYS_CLK_NO_DIV_STATE_S 18 +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) +#define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_ICG_SYS_CLK_EN_STATE_S 19 +/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) +#define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_ICG_MODEM_SWITCH_STATE_S 20 +/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_S 21 +/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_ICG_SLP_SEL_STATE (BIT(23)) +#define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) +#define PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_ICG_SLP_SEL_STATE_S 23 +/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) +#define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_XTAL_STATE_S 24 +/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) +#define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_PLL_STATE_S 25 +/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) +#define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_ANA_I2C_ISO_EN_STATE_S 26 +/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) +#define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_ANA_I2C_RETENTION_STATE_S 27 +/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) +#define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) +#define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BB_I2C_STATE_S 28 +/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 +/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) +#define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) +#define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_STATE_S 30 +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) +#define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) +#define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_VDD_SPI_STATUS_REG register + * need_des + */ +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35664432; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h new file mode 100644 index 00000000000..15c140e2c87 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pmu_struct.h @@ -0,0 +1,2787 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_spi_pd_en:1; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_active_dbg_atten:4; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:2; + /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_retention_mode:1; + /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_retention_en:1; + /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2active_retention_en:1; + uint32_t reserved_13:1; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + uint32_t reserved_18:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:3; + /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:3; + uint32_t reserved_26:3; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_modem_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_vdd_spi_pd_en:1; + /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_mem_dslp:1; + /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_mem_pd_en:4; + /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_cpu_pd_en:1; + /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_aon_pd_en:1; + /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_modem_dig_power_reg_t; + +/** Type of hp_modem_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_func_reg_t; + +/** Type of hp_modem_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_apb_reg_t; + +/** Type of hp_modem_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_modem_icg_modem_reg_t; + +/** Type of hp_modem_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_modem_uart_wakeup_en:1; + /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_lp_pad_hold_all:1; + /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_pad_hold_all:1; + /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pad_slp_sel:1; + /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pause_wdt:1; + /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_hp_sys_cntl_reg_t; + +/** Type of hp_modem_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_iso_en:1; + /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_retention:1; + /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bb_i2c:1; + /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll_i2c:1; + /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_modem_hp_ck_power_reg_t; + +/** Type of hp_modem_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bias:1; + /** hp_modem_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_modem_dbg_atten:4; + /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cur:1; + /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_modem_bias_reg_t; + +/** Type of hp_modem_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_modem_clk_code:2; + uint32_t reserved_6:4; + /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_modem_retention_mode:1; + /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_retention_en:1; + uint32_t reserved_12:2; + /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_clk_sel:2; + uint32_t reserved_16:4; + /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_mode:3; + uint32_t reserved_23:6; + /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_backup_reg_t; + +/** Type of hp_modem_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_backup_clk_reg_t; + +/** Type of hp_modem_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_no_div:1; + /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_sys_clock_en:1; + /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_sys_clk_slp_sel:1; + /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_slp_sel:1; + /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_modem_sysclk_reg_t; + +/** Type of hp_modem_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; + /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; + /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_xpd:1; + /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; + /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; + /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_modem_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator0_reg_t; + +/** Type of hp_modem_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator1_reg_t; + +/** Type of hp_modem_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_modem_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_modem_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_spi_pd_en:1; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dbg_atten:4; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_retention_mode:1; + uint32_t reserved_11:1; + /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_retention_en:1; + /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_retention_en:1; + uint32_t reserved_14:2; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + uint32_t reserved_20:3; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:3; + /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:3; + uint32_t reserved_29:1; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t lp_sleep_dbg_atten:4; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + uint32_t reserved_7:18; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 255; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 255; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_vdd_spi_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; + * need_des + */ + uint32_t vdd_spi_pwr_wait:11; + /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; + * need_des + */ + uint32_t vdd_spi_pwr_sw:2; + /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vdd_spi_pwr_sel_sw:1; + }; + uint32_t val; +} pmu_power_vdd_spi_cntl_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** xpd_tc5g_i2c : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t xpd_tc5g_i2c:1; + /** xpd_rx5g_i2c : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t xpd_rx5g_i2c:1; + /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t perif_i2c_rstb:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_txrf_i2c:1; + /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_pbus:1; + /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_ckgen_i2c:1; + /** xpd_pll_i2c : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_pll_i2c:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 1; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 35664432; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +/** Type of vdd_spi_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t stable_vdd_spi_pwr_drv:1; + }; + uint32_t val; +} pmu_vdd_spi_status_reg_t; + + +typedef struct pmu_dev_t { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; + volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; + volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; + volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; + volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; + volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; + volatile pmu_hp_modem_bias_reg_t hp_modem_bias; + volatile pmu_hp_modem_backup_reg_t hp_modem_backup; + volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; + volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; + volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; + volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; + volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + uint32_t reserved_0a4; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + uint32_t reserved_0b0; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + uint32_t reserved_100; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_vdd_spi_status_reg_t vdd_spi_status; + uint32_t reserved_1a4[150]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h new file mode 100644 index 00000000000..c91ef0596e9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/reg_base.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Peripheral 0 Modules + * + */ +#define DR_REG_UART0_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_SPIMEM0_BASE 0x60002000 +#define DR_REG_SPIMEM1_BASE 0x60003000 +#define DR_REG_I2C0_BASE 0x60004000 +#define DR_REG_UHCI_BASE 0x60005000 +#define DR_REG_RMT_BASE 0x60006000 +#define DR_REG_LEDC_BASE 0x60007000 +#define DR_REG_TIMERG0_BASE 0x60008000 +#define DR_REG_TIMERG1_BASE 0x60009000 +#define DR_REG_SYSTIMER_BASE 0x6000A000 +#define DR_REG_TWAI0_BASE 0x6000B000 +#define DR_REG_I2S_BASE 0x6000C000 +#define DR_REG_TWAI1_BASE 0x6000D000 +#define DR_REG_APB_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE +#define DR_REG_I2C1_BASE 0x60011000 +#define DR_REG_PCNT_BASE 0x60012000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_MCPWM_BASE 0x60014000 +#define DR_REG_PARL_IO_BASE 0x60015000 +#define DR_REG_PVT_MONITOR_BASE 0x60019000 + +/** + * @brief Peripheral 1 Modules + * + */ +#define DR_REG_GDMA_BASE 0x60080000 +#define DR_REG_GPSPI2_BASE 0x60081000 +#define DR_REG_BITSCRAMBLER_BASE 0x60082000 +#define DR_REG_KEYMNG_BASE 0x60087000 +#define DR_REG_AES_BASE 0x60088000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_RSA_BASE 0x6008A000 +#define DR_REG_ECC_BASE 0x6008B000 +#define DR_REG_DS_BASE 0x6008C000 +#define DR_REG_HMAC_BASE 0x6008D000 +#define DR_REG_ECDSA_BASE 0x6008E000 + +/** + * @brief HP Top Peripheral Modules + * + */ +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_BASE 0x60098000 +#define DR_REG_HP_APM_BASE 0x60099000 +#define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_MISC_BASE 0x6009F000 + +/** + * @brief Modem Module + * + */ +#define DR_REG_MODEM_BASE 0x600A4000 +#define DR_REG_MODEM_PWR_BASE 0x600AD000 + +/** + * @brief LP System (RTC) Modules + * + */ +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_EFUSE_BASE 0x600B0800 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_UART_BASE 0x600B1400 +#define DR_REG_LP_I2C_BASE 0x600B1800 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LP_IO_BASE 0x600B2000 +#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00 +#define DR_REG_HUK_BASE 0x600B3000 +#define DR_REG_LP_TEE_BASE 0x600B3400 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_OTP_DEBUG_BASE 0x600B3C00 + +/** + * @brief CPU Peripheral Modules + * + */ +#define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 +#define DR_REG_INTPRI_BASE 0x600C5000 +#define DR_REG_CACHE_BASE 0x600C8000 diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h new file mode 100644 index 00000000000..9576fb759f3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/reset_reasons.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +// TODO: [ESP32C5] IDF-8660 (inherit from P4) +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529 + RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset + RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset + RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system + RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system + RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 + RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core + RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core + RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rmt_reg.h b/components/soc/esp32c5/include/soc/rmt_reg.h new file mode 100644 index 00000000000..785086a1ef1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/rmt_reg.h @@ -0,0 +1,1491 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFFU +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFFU +#define RMT_CH0DATA_S 0 + +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFFU +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFFU +#define RMT_CH1DATA_S 0 + +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFFU +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFFU +#define RMT_CH2DATA_S 0 + +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFFU +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFFU +#define RMT_CH3DATA_S 0 + +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) +#define RMT_TX_START_CH0_V 0x00000001U +#define RMT_TX_START_CH0_S 0 +/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) +#define RMT_MEM_RD_RST_CH0_V 0x00000001U +#define RMT_MEM_RD_RST_CH0_S 1 +/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) +#define RMT_APB_MEM_RST_CH0_V 0x00000001U +#define RMT_APB_MEM_RST_CH0_S 2 +/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) +#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH0_S 3 +/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) +#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH0_S 5 +/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) +#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH0_S 6 +/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) +#define RMT_TX_STOP_CH0_V 0x00000001U +#define RMT_TX_STOP_CH0_S 7 +/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_CH0 0x000000FFU +#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) +#define RMT_DIV_CNT_CH0_V 0x000000FFU +#define RMT_DIV_CNT_CH0_S 8 +/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_CH0 0x00000007U +#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) +#define RMT_MEM_SIZE_CH0_V 0x00000007U +#define RMT_MEM_SIZE_CH0_S 16 +/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) +#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) +#define RMT_CARRIER_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EN_CH0_S 21 +/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) +#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S) +#define RMT_CONF_UPDATE_CH0_V 0x00000001U +#define RMT_CONF_UPDATE_CH0_S 24 + +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 1 +/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 2 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 3 +/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 5 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 6 +/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 7 +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_CH1 0x00000007U +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x00000007U +#define RMT_MEM_SIZE_CH1_S 16 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 21 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S) +#define RMT_CONF_UPDATE_CH1_V 0x00000001U +#define RMT_CONF_UPDATE_CH1_S 24 + +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 0 +/** RMT_IDLE_THRES_CH2 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH2 0x00007FFFU +#define RMT_IDLE_THRES_CH2_M (RMT_IDLE_THRES_CH2_V << RMT_IDLE_THRES_CH2_S) +#define RMT_IDLE_THRES_CH2_V 0x00007FFFU +#define RMT_IDLE_THRES_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_CH2 0x00000007U +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x00000007U +#define RMT_MEM_SIZE_CH2_S 23 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 28 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 29 + +/** RMT_CH2CONF1_REG register + * Channel 2 configure register 1 + */ +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_RX_EN_CH2 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL2. + */ +#define RMT_RX_EN_CH2 (BIT(0)) +#define RMT_RX_EN_CH2_M (RMT_RX_EN_CH2_V << RMT_RX_EN_CH2_S) +#define RMT_RX_EN_CH2_V 0x00000001U +#define RMT_RX_EN_CH2_S 0 +/** RMT_MEM_WR_RST_CH2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL2 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH2 (BIT(1)) +#define RMT_MEM_WR_RST_CH2_M (RMT_MEM_WR_RST_CH2_V << RMT_MEM_WR_RST_CH2_S) +#define RMT_MEM_WR_RST_CH2_V 0x00000001U +#define RMT_MEM_WR_RST_CH2_S 1 +/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 2 +/** RMT_MEM_OWNER_CH2 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL2's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH2 (BIT(3)) +#define RMT_MEM_OWNER_CH2_M (RMT_MEM_OWNER_CH2_V << RMT_MEM_OWNER_CH2_S) +#define RMT_MEM_OWNER_CH2_V 0x00000001U +#define RMT_MEM_OWNER_CH2_S 3 +/** RMT_RX_FILTER_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL2. + */ +#define RMT_RX_FILTER_EN_CH2 (BIT(4)) +#define RMT_RX_FILTER_EN_CH2_M (RMT_RX_FILTER_EN_CH2_V << RMT_RX_FILTER_EN_CH2_S) +#define RMT_RX_FILTER_EN_CH2_V 0x00000001U +#define RMT_RX_FILTER_EN_CH2_S 4 +/** RMT_RX_FILTER_THRES_CH2 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH2 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_M (RMT_RX_FILTER_THRES_CH2_V << RMT_RX_FILTER_THRES_CH2_S) +#define RMT_RX_FILTER_THRES_CH2_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_S 5 +/** RMT_MEM_RX_WRAP_EN_CH2 : R/W; bitpos: [13]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH2_M (RMT_MEM_RX_WRAP_EN_CH2_V << RMT_MEM_RX_WRAP_EN_CH2_S) +#define RMT_MEM_RX_WRAP_EN_CH2_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH2_S 13 +/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_CH2 (BIT(15)) +#define RMT_CONF_UPDATE_CH2_M (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S) +#define RMT_CONF_UPDATE_CH2_V 0x00000001U +#define RMT_CONF_UPDATE_CH2_S 15 + +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 0 +/** RMT_IDLE_THRES_CH3 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH3 0x00007FFFU +#define RMT_IDLE_THRES_CH3_M (RMT_IDLE_THRES_CH3_V << RMT_IDLE_THRES_CH3_S) +#define RMT_IDLE_THRES_CH3_V 0x00007FFFU +#define RMT_IDLE_THRES_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_CH3 0x00000007U +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x00000007U +#define RMT_MEM_SIZE_CH3_S 23 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 28 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 29 + +/** RMT_CH3CONF1_REG register + * Channel 3 configure register 1 + */ +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_RX_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL3. + */ +#define RMT_RX_EN_CH3 (BIT(0)) +#define RMT_RX_EN_CH3_M (RMT_RX_EN_CH3_V << RMT_RX_EN_CH3_S) +#define RMT_RX_EN_CH3_V 0x00000001U +#define RMT_RX_EN_CH3_S 0 +/** RMT_MEM_WR_RST_CH3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL3 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH3 (BIT(1)) +#define RMT_MEM_WR_RST_CH3_M (RMT_MEM_WR_RST_CH3_V << RMT_MEM_WR_RST_CH3_S) +#define RMT_MEM_WR_RST_CH3_V 0x00000001U +#define RMT_MEM_WR_RST_CH3_S 1 +/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 2 +/** RMT_MEM_OWNER_CH3 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL3's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH3 (BIT(3)) +#define RMT_MEM_OWNER_CH3_M (RMT_MEM_OWNER_CH3_V << RMT_MEM_OWNER_CH3_S) +#define RMT_MEM_OWNER_CH3_V 0x00000001U +#define RMT_MEM_OWNER_CH3_S 3 +/** RMT_RX_FILTER_EN_CH3 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL3. + */ +#define RMT_RX_FILTER_EN_CH3 (BIT(4)) +#define RMT_RX_FILTER_EN_CH3_M (RMT_RX_FILTER_EN_CH3_V << RMT_RX_FILTER_EN_CH3_S) +#define RMT_RX_FILTER_EN_CH3_V 0x00000001U +#define RMT_RX_FILTER_EN_CH3_S 4 +/** RMT_RX_FILTER_THRES_CH3 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH3 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_M (RMT_RX_FILTER_THRES_CH3_V << RMT_RX_FILTER_THRES_CH3_S) +#define RMT_RX_FILTER_THRES_CH3_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_S 5 +/** RMT_MEM_RX_WRAP_EN_CH3 : R/W; bitpos: [13]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH3_M (RMT_MEM_RX_WRAP_EN_CH3_V << RMT_MEM_RX_WRAP_EN_CH3_S) +#define RMT_MEM_RX_WRAP_EN_CH3_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH3_S 13 +/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_CH3 (BIT(15)) +#define RMT_CONF_UPDATE_CH3_M (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S) +#define RMT_CONF_UPDATE_CH3_V 0x00000001U +#define RMT_CONF_UPDATE_CH3_S 15 + +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH0 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) +#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_STATE_CH0 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_CH0 0x00000007U +#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) +#define RMT_STATE_CH0_V 0x00000007U +#define RMT_STATE_CH0_S 9 +/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH0 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) +#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_S 12 +/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH0 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) +#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH0_S 21 +/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH0 (BIT(22)) +#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) +#define RMT_MEM_EMPTY_CH0_V 0x00000001U +#define RMT_MEM_EMPTY_CH0_S 22 +/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH0_S 23 +/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH0 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) +#define RMT_APB_MEM_RADDR_CH0_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_S 24 + +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH1 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_STATE_CH1 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 9 +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH1 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_S 12 +/** RMT_APB_MEM_RD_ERR_CH1 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH1_M (RMT_APB_MEM_RD_ERR_CH1_V << RMT_APB_MEM_RD_ERR_CH1_S) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH1_S 21 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH1 (BIT(22)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 22 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 23 +/** RMT_APB_MEM_RADDR_CH1 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH1 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_M (RMT_APB_MEM_RADDR_CH1_V << RMT_APB_MEM_RADDR_CH1_S) +#define RMT_APB_MEM_RADDR_CH1_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_S 24 + +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_MEM_WADDR_EX_CH2 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL2 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH2 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_M (RMT_MEM_WADDR_EX_CH2_V << RMT_MEM_WADDR_EX_CH2_S) +#define RMT_MEM_WADDR_EX_CH2_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_S 0 +/** RMT_APB_MEM_RADDR_CH2 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH2 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_M (RMT_APB_MEM_RADDR_CH2_V << RMT_APB_MEM_RADDR_CH2_S) +#define RMT_APB_MEM_RADDR_CH2_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_S 12 +/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 22 +/** RMT_MEM_OWNER_ERR_CH2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH2 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH2_M (RMT_MEM_OWNER_ERR_CH2_V << RMT_MEM_OWNER_ERR_CH2_S) +#define RMT_MEM_OWNER_ERR_CH2_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH2_S 25 +/** RMT_MEM_FULL_CH2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH2 (BIT(26)) +#define RMT_MEM_FULL_CH2_M (RMT_MEM_FULL_CH2_V << RMT_MEM_FULL_CH2_S) +#define RMT_MEM_FULL_CH2_V 0x00000001U +#define RMT_MEM_FULL_CH2_S 26 +/** RMT_APB_MEM_RD_ERR_CH2 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_M (RMT_APB_MEM_RD_ERR_CH2_V << RMT_APB_MEM_RD_ERR_CH2_S) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH2_S 27 + +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_MEM_WADDR_EX_CH3 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL3 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH3 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_M (RMT_MEM_WADDR_EX_CH3_V << RMT_MEM_WADDR_EX_CH3_S) +#define RMT_MEM_WADDR_EX_CH3_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_S 0 +/** RMT_APB_MEM_RADDR_CH3 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH3 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_M (RMT_APB_MEM_RADDR_CH3_V << RMT_APB_MEM_RADDR_CH3_S) +#define RMT_APB_MEM_RADDR_CH3_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_S 12 +/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 22 +/** RMT_MEM_OWNER_ERR_CH3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH3 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH3_M (RMT_MEM_OWNER_ERR_CH3_V << RMT_MEM_OWNER_ERR_CH3_S) +#define RMT_MEM_OWNER_ERR_CH3_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH3_S 25 +/** RMT_MEM_FULL_CH3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH3 (BIT(26)) +#define RMT_MEM_FULL_CH3_M (RMT_MEM_FULL_CH3_V << RMT_MEM_FULL_CH3_S) +#define RMT_MEM_FULL_CH3_V 0x00000001U +#define RMT_MEM_FULL_CH3_S 26 +/** RMT_APB_MEM_RD_ERR_CH3 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_M (RMT_APB_MEM_RD_ERR_CH3_V << RMT_APB_MEM_RD_ERR_CH3_S) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH3_S 27 + +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_RX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ +#define RMT_CH2_RX_END_INT_RAW (BIT(2)) +#define RMT_CH2_RX_END_INT_RAW_M (RMT_CH2_RX_END_INT_RAW_V << RMT_CH2_RX_END_INT_RAW_S) +#define RMT_CH2_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_END_INT_RAW_S 2 +/** RMT_CH3_RX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ +#define RMT_CH3_RX_END_INT_RAW (BIT(3)) +#define RMT_CH3_RX_END_INT_RAW_M (RMT_CH3_RX_END_INT_RAW_V << RMT_CH3_RX_END_INT_RAW_S) +#define RMT_CH3_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001U +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001U +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001U +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001U +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (RMT_CH2_RX_THR_EVENT_INT_RAW_V << RMT_CH2_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (RMT_CH3_RX_THR_EVENT_INT_RAW_V << RMT_CH3_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 + +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001U +#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001U +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_RX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ST (BIT(2)) +#define RMT_CH2_RX_END_INT_ST_M (RMT_CH2_RX_END_INT_ST_V << RMT_CH2_RX_END_INT_ST_S) +#define RMT_CH2_RX_END_INT_ST_V 0x00000001U +#define RMT_CH2_RX_END_INT_ST_S 2 +/** RMT_CH3_RX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ST (BIT(3)) +#define RMT_CH3_RX_END_INT_ST_M (RMT_CH3_RX_END_INT_ST_V << RMT_CH3_RX_END_INT_ST_S) +#define RMT_CH3_RX_END_INT_ST_V 0x00000001U +#define RMT_CH3_RX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001U +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001U +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001U +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001U +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ST_M (RMT_CH2_RX_THR_EVENT_INT_ST_V << RMT_CH2_RX_THR_EVENT_INT_ST_S) +#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ST_M (RMT_CH3_RX_THR_EVENT_INT_ST_V << RMT_CH3_RX_THR_EVENT_INT_ST_S) +#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ST_S 13 + +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_RX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ENA (BIT(2)) +#define RMT_CH2_RX_END_INT_ENA_M (RMT_CH2_RX_END_INT_ENA_V << RMT_CH2_RX_END_INT_ENA_S) +#define RMT_CH2_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_END_INT_ENA_S 2 +/** RMT_CH3_RX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ENA (BIT(3)) +#define RMT_CH3_RX_END_INT_ENA_M (RMT_CH3_RX_END_INT_ENA_V << RMT_CH3_RX_END_INT_ENA_S) +#define RMT_CH3_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001U +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001U +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001U +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001U +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (RMT_CH2_RX_THR_EVENT_INT_ENA_V << RMT_CH2_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (RMT_CH3_RX_THR_EVENT_INT_ENA_V << RMT_CH3_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 + +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_RX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ +#define RMT_CH2_RX_END_INT_CLR (BIT(2)) +#define RMT_CH2_RX_END_INT_CLR_M (RMT_CH2_RX_END_INT_CLR_V << RMT_CH2_RX_END_INT_CLR_S) +#define RMT_CH2_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_END_INT_CLR_S 2 +/** RMT_CH3_RX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ +#define RMT_CH3_RX_END_INT_CLR (BIT(3)) +#define RMT_CH3_RX_END_INT_CLR_M (RMT_CH3_RX_END_INT_CLR_V << RMT_CH3_RX_END_INT_CLR_S) +#define RMT_CH3_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001U +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001U +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001U +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001U +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (RMT_CH2_RX_THR_EVENT_INT_CLR_V << RMT_CH2_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (RMT_CH3_RX_THR_EVENT_INT_CLR_V << RMT_CH3_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 + +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_S 16 + +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 + +/** RMT_CH2_RX_CARRIER_RM_REG register + * Channel 2 carrier remove register + */ +#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_CARRIER_LOW_THRES_CH2 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_M (RMT_CARRIER_LOW_THRES_CH2_V << RMT_CARRIER_LOW_THRES_CH2_S) +#define RMT_CARRIER_LOW_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_S 0 +/** RMT_CARRIER_HIGH_THRES_CH2 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_M (RMT_CARRIER_HIGH_THRES_CH2_V << RMT_CARRIER_HIGH_THRES_CH2_S) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 + +/** RMT_CH3_RX_CARRIER_RM_REG register + * Channel 3 carrier remove register + */ +#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_CARRIER_LOW_THRES_CH3 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_M (RMT_CARRIER_LOW_THRES_CH3_V << RMT_CARRIER_LOW_THRES_CH3_S) +#define RMT_CARRIER_LOW_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_S 0 +/** RMT_CARRIER_HIGH_THRES_CH3 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_M (RMT_CARRIER_HIGH_THRES_CH3_V << RMT_CARRIER_HIGH_THRES_CH3_S) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 + +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FFU +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FFU +#define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL0. + */ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S) +#define RMT_LOOP_STOP_EN_CH0_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH0_S 21 + +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL1. + */ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S) +#define RMT_LOOP_STOP_EN_CH1_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH1_S 21 + +/** RMT_CH2_RX_LIM_REG register + * Channel 2 Rx event configuration register + */ +#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can receive. + */ +#define RMT_RX_LIM_CH2 0x000001FFU +#define RMT_RX_LIM_CH2_M (RMT_RX_LIM_CH2_V << RMT_RX_LIM_CH2_S) +#define RMT_RX_LIM_CH2_V 0x000001FFU +#define RMT_RX_LIM_CH2_S 0 + +/** RMT_CH3_RX_LIM_REG register + * Channel 3 Rx event configuration register + */ +#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_RX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can receive. + */ +#define RMT_RX_LIM_CH3 0x000001FFU +#define RMT_RX_LIM_CH3_M (RMT_RX_LIM_CH3_V << RMT_RX_LIM_CH3_S) +#define RMT_RX_LIM_CH3_V 0x000001FFU +#define RMT_RX_LIM_CH3_S 0 + +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001U +#define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001U +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S) +#define RMT_MEM_FORCE_PD_V 0x00000001U +#define RMT_MEM_FORCE_PD_S 2 +/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S) +#define RMT_MEM_FORCE_PU_V 0x00000001U +#define RMT_MEM_FORCE_PU_S 3 +/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_SCLK_DIV_NUM 0x000000FFU +#define RMT_SCLK_DIV_NUM_M (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S) +#define RMT_SCLK_DIV_NUM_V 0x000000FFU +#define RMT_SCLK_DIV_NUM_S 4 +/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_A 0x0000003FU +#define RMT_SCLK_DIV_A_M (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S) +#define RMT_SCLK_DIV_A_V 0x0000003FU +#define RMT_SCLK_DIV_A_S 12 +/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_B 0x0000003FU +#define RMT_SCLK_DIV_B_M (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S) +#define RMT_SCLK_DIV_B_V 0x0000003FU +#define RMT_SCLK_DIV_B_S 18 +/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ +#define RMT_SCLK_SEL 0x00000003U +#define RMT_SCLK_SEL_M (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S) +#define RMT_SCLK_SEL_V 0x00000003U +#define RMT_SCLK_SEL_S 24 +/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S) +#define RMT_SCLK_ACTIVE_V 0x00000001U +#define RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001U +#define RMT_CLK_EN_S 31 + +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001U +#define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001U +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_EN : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(2)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001U +#define RMT_TX_SIM_EN_S 2 + +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001U +#define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001U +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001U +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001U +#define RMT_REF_CNT_RST_CH3_S 3 + +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_DATE : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ +#define RMT_DATE 0x0FFFFFFFU +#define RMT_DATE_M (RMT_DATE_V << RMT_DATE_S) +#define RMT_DATE_V 0x0FFFFFFFU +#define RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rmt_struct.h b/components/soc/esp32c5/include/soc/rmt_struct.h new file mode 100644 index 00000000000..02d2138a802 --- /dev/null +++ b/components/soc/esp32c5/include/soc/rmt_struct.h @@ -0,0 +1,802 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chndata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata:32; + }; + uint32_t val; +} rmt_chndata_reg_t; + +/** Type of chmdata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chmdata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chmdata:32; + }; + uint32_t val; +} rmt_chmdata_reg_t; + + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_chn : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_chn:1; + /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_chn:1; + /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_chn:1; + /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_chn:1; + /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_chn:1; + /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_chn:1; + /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_chn:1; + /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_chn:1; + /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_chn:8; + /** mem_size_chn : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_chn:3; + uint32_t reserved_19:1; + /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_chn:1; + /** carrier_en_chn : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chn:1; + /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chn:1; + uint32_t reserved_23:1; + /** conf_update_chn : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +/** Type of chmconf0 register + * Channel m configure register 0 + */ +typedef union { + struct { + /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_chm:8; + /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_chm:15; + /** mem_size_chm : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_chm:3; + uint32_t reserved_26:2; + /** carrier_en_chm : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chm:1; + /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chm:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_chmconf0_reg_t; + +/** Type of chmconf1 register + * Channel m configure register 1 + */ +typedef union { + struct { + /** rx_en_chm : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_chm:1; + /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_chm:1; + /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_chm:1; + /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_chm:1; + /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_chm:1; + /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_chm:8; + /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_chm:1; + uint32_t reserved_14:1; + /** conf_update_chm : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_chm:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} rmt_chmconf1_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu:1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ + uint32_t sclk_sel:2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active:1; + uint32_t reserved_27:4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0:1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1:1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2:1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_chn:9; + /** state_chn : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_chn:3; + /** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_chn:9; + /** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ + uint32_t apb_mem_rd_err_chn:1; + /** mem_empty_chn : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_chn:1; + /** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_chn:1; + /** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ + uint32_t apb_mem_raddr_chn:8; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_chm:9; + uint32_t reserved_9:3; + /** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_chm:9; + uint32_t reserved_21:1; + /** state_chm : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_chm:3; + /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_chm:1; + /** mem_full_chm : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_chm:1; + /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_chm:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw:1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw:1; + /** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ + uint32_t ch2_rx_end_int_raw:1; + /** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ + uint32_t ch3_rx_end_int_raw:1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw:1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw:1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw:1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw:1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw:1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw:1; + /** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch2_rx_thr_event_int_raw:1; + /** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch3_rx_thr_event_int_raw:1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw:1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st:1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st:1; + /** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_st:1; + /** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_st:1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_st:1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_st:1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_st:1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_st:1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st:1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st:1; + /** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_st:1; + /** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_st:1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st:1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena:1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena:1; + /** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_ena:1; + /** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_ena:1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_ena:1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_ena:1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_ena:1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_ena:1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena:1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena:1; + /** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_ena:1; + /** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_ena:1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena:1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr:1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr:1; + /** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ + uint32_t ch2_rx_end_int_clr:1; + /** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ + uint32_t ch3_rx_end_int_clr:1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr:1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr:1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr:1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr:1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr:1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr:1; + /** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_rx_thr_event_int_clr:1; + /** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_rx_thr_event_int_clr:1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr:1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_clr_reg_t; + + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn:16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn:16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm:16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm:16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn:9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn:10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn:1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn:1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0:1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1:1; + /** tx_sim_en : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** rx_lim_chm : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t rx_lim_chm:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_date_reg_t; + + +typedef struct rmt_dev_t { + volatile rmt_chndata_reg_t chndata[2]; + volatile rmt_chmdata_reg_t chmdata[2]; + volatile rmt_chnconf0_reg_t chnconf0[2]; + volatile struct { + rmt_chmconf0_reg_t conf0; + rmt_chmconf1_reg_t conf1; + } chmconf[2];; + volatile rmt_chnstatus_reg_t chnstatus[2]; + volatile rmt_chmstatus_reg_t chmstatus[2]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + uint32_t reserved_074[22]; + volatile rmt_date_reg_t date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rsa_reg.h b/components/soc/esp32c5/include/soc/rsa_reg.h new file mode 100644 index 00000000000..542612dbb47 --- /dev/null +++ b/components/soc/esp32c5/include/soc/rsa_reg.h @@ -0,0 +1,233 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RSA_M_MEM register + * Represents M + */ +#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0) +#define RSA_M_MEM_SIZE_BYTES 16 + +/** RSA_Z_MEM register + * Represents Z + */ +#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200) +#define RSA_Z_MEM_SIZE_BYTES 16 + +/** RSA_Y_MEM register + * Represents Y + */ +#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400) +#define RSA_Y_MEM_SIZE_BYTES 16 + +/** RSA_X_MEM register + * Represents X + */ +#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600) +#define RSA_X_MEM_SIZE_BYTES 16 + +/** RSA_M_PRIME_REG register + * Represents M’ + */ +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) +/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Represents M’ + */ +#define RSA_M_PRIME 0xFFFFFFFFU +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFFU +#define RSA_M_PRIME_S 0 + +/** RSA_MODE_REG register + * Configures RSA length + */ +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) +/** RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ +#define RSA_MODE 0x0000007FU +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007FU +#define RSA_MODE_S 0 + +/** RSA_QUERY_CLEAN_REG register + * RSA clean register + */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) +/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ +#define RSA_QUERY_CLEAN (BIT(0)) +#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) +#define RSA_QUERY_CLEAN_V 0x00000001U +#define RSA_QUERY_CLEAN_S 0 + +/** RSA_SET_START_MODEXP_REG register + * Starts modular exponentiation + */ +#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) +/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODEXP (BIT(0)) +#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) +#define RSA_SET_START_MODEXP_V 0x00000001U +#define RSA_SET_START_MODEXP_S 0 + +/** RSA_SET_START_MODMULT_REG register + * Starts modular multiplication + */ +#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) +/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODMULT (BIT(0)) +#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) +#define RSA_SET_START_MODMULT_V 0x00000001U +#define RSA_SET_START_MODMULT_S 0 + +/** RSA_SET_START_MULT_REG register + * Starts multiplication + */ +#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) +/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MULT (BIT(0)) +#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) +#define RSA_SET_START_MULT_V 0x00000001U +#define RSA_SET_START_MULT_S 0 + +/** RSA_QUERY_IDLE_REG register + * Represents the RSA status + */ +#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) +/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ +#define RSA_QUERY_IDLE (BIT(0)) +#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) +#define RSA_QUERY_IDLE_V 0x00000001U +#define RSA_QUERY_IDLE_S 0 + +/** RSA_INT_CLR_REG register + * Clears RSA interrupt + */ +#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c) +/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001U +#define RSA_CLEAR_INTERRUPT_S 0 + +/** RSA_CONSTANT_TIME_REG register + * Configures the constant_time option + */ +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001U +#define RSA_CONSTANT_TIME_S 0 + +/** RSA_SEARCH_ENABLE_REG register + * Configures the search option + */ +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) +/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001U +#define RSA_SEARCH_ENABLE_S 0 + +/** RSA_SEARCH_POS_REG register + * Configures the search position + */ +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) +/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ +#define RSA_SEARCH_POS 0x00000FFFU +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFFU +#define RSA_SEARCH_POS_S 0 + +/** RSA_INT_ENA_REG register + * Enables the RSA interrupt + */ +#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c) +/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ +#define RSA_INT_ENA (BIT(0)) +#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S) +#define RSA_INT_ENA_V 0x00000001U +#define RSA_INT_ENA_S 0 + +/** RSA_DATE_REG register + * Version control register + */ +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) +/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ +#define RSA_DATE 0x3FFFFFFFU +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFFU +#define RSA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rsa_struct.h b/components/soc/esp32c5/include/soc/rsa_struct.h new file mode 100644 index 00000000000..7546b4e713f --- /dev/null +++ b/components/soc/esp32c5/include/soc/rsa_struct.h @@ -0,0 +1,273 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory */ + +/** Group: Control / Configuration Registers */ +/** Type of m_prime register + * Represents M’ + */ +typedef union { + struct { + /** m_prime : R/W; bitpos: [31:0]; default: 0; + * Represents M’ + */ + uint32_t m_prime:32; + }; + uint32_t val; +} rsa_m_prime_reg_t; + +/** Type of mode register + * Configures RSA length + */ +typedef union { + struct { + /** mode : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ + uint32_t mode:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} rsa_mode_reg_t; + +/** Type of set_start_modexp register + * Starts modular exponentiation + */ +typedef union { + struct { + /** set_start_modexp : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modexp:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modexp_reg_t; + +/** Type of set_start_modmult register + * Starts modular multiplication + */ +typedef union { + struct { + /** set_start_modmult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modmult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modmult_reg_t; + +/** Type of set_start_mult register + * Starts multiplication + */ +typedef union { + struct { + /** set_start_mult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_mult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_mult_reg_t; + +/** Type of query_idle register + * Represents the RSA status + */ +typedef union { + struct { + /** query_idle : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ + uint32_t query_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_idle_reg_t; + +/** Type of constant_time register + * Configures the constant_time option + */ +typedef union { + struct { + /** constant_time : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ + uint32_t constant_time:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_constant_time_reg_t; + +/** Type of search_enable register + * Configures the search option + */ +typedef union { + struct { + /** search_enable : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ + uint32_t search_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_search_enable_reg_t; + +/** Type of search_pos register + * Configures the search position + */ +typedef union { + struct { + /** search_pos : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ + uint32_t search_pos:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} rsa_search_pos_reg_t; + + +/** Group: Status Register */ +/** Type of query_clean register + * RSA clean register + */ +typedef union { + struct { + /** query_clean : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ + uint32_t query_clean:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_clean_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_clr register + * Clears RSA interrupt + */ +typedef union { + struct { + /** clear_interrupt : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_clr_reg_t; + +/** Type of int_ena register + * Enables the RSA interrupt + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_ena_reg_t; + + +/** Group: Version Control Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} rsa_date_reg_t; + + +typedef struct rsa_dev_t { + volatile uint32_t m[4]; + uint32_t reserved_010[124]; + volatile uint32_t z[4]; + uint32_t reserved_210[124]; + volatile uint32_t y[4]; + uint32_t reserved_410[124]; + volatile uint32_t x[4]; + uint32_t reserved_610[124]; + volatile rsa_m_prime_reg_t m_prime; + volatile rsa_mode_reg_t mode; + volatile rsa_query_clean_reg_t query_clean; + volatile rsa_set_start_modexp_reg_t set_start_modexp; + volatile rsa_set_start_modmult_reg_t set_start_modmult; + volatile rsa_set_start_mult_reg_t set_start_mult; + volatile rsa_query_idle_reg_t query_idle; + volatile rsa_int_clr_reg_t int_clr; + volatile rsa_constant_time_reg_t constant_time; + volatile rsa_search_enable_reg_t search_enable; + volatile rsa_search_pos_reg_t search_pos; + volatile rsa_int_ena_reg_t int_ena; + volatile rsa_date_reg_t date; +} rsa_dev_t; + +extern rsa_dev_t RSA; + +#ifndef __cplusplus +_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rtc_io_channel.h b/components/soc/esp32c5/include/soc/rtc_io_channel.h new file mode 100644 index 00000000000..f9544599395 --- /dev/null +++ b/components/soc/esp32c5/include/soc/rtc_io_channel.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// TODO: [ESP32C5] IDF-8719 (inherit from C6) +//RTC GPIO channels +#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0 +#define RTCIO_CHANNEL_0_GPIO_NUM 0 + +#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1 +#define RTCIO_CHANNEL_1_GPIO_NUM 1 + +#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2 +#define RTCIO_CHANNEL_2_GPIO_NUM 2 + +#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3 +#define RTCIO_CHANNEL_3_GPIO_NUM 3 + +#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4 +#define RTCIO_CHANNEL_4_GPIO_NUM 4 + +#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5 +#define RTCIO_CHANNEL_5_GPIO_NUM 5 + +#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6 +#define RTCIO_CHANNEL_6_GPIO_NUM 6 + +#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7 +#define RTCIO_CHANNEL_7_GPIO_NUM 7 diff --git a/components/soc/esp32c5/include/soc/sha_reg.h b/components/soc/esp32c5/include/soc/sha_reg.h new file mode 100644 index 00000000000..11181a16e1e --- /dev/null +++ b/components/soc/esp32c5/include/soc/sha_reg.h @@ -0,0 +1,148 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Initial configuration register. + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * DMA configuration register 0. + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Typical SHA configuration register 0. + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_START 0x7FFFFFFFU +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x7FFFFFFFU +#define SHA_START_S 1 + +/** SHA_CONTINUE_REG register + * Typical SHA configuration register 1. + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x7FFFFFFFU +#define SHA_CONTINUE_S 1 + +/** SHA_BUSY_REG register + * Busy register. + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * DMA configuration register 1. + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * DMA configuration register 2. + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * Interrupt clear register. + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * Interrupt enable register. + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Date register. + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or finial hash. + */ +#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 64 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/include/soc/sha_struct.h new file mode 100644 index 00000000000..d65e8e449e0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/sha_struct.h @@ -0,0 +1,188 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of mode register + * Initial configuration register. + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of dma_block_num register + * DMA configuration register 0. + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ + uint32_t dma_block_num:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Typical SHA configuration register 0. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** start : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t start:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Typical SHA configuration register 1. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** continue : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t continue:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * DMA configuration register 1. + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * DMA configuration register 2. + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + + +/** Group: Status Register */ +/** Type of busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Register */ +/** Type of clear_irq register + * Interrupt clear register. + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * Interrupt enable register. + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +typedef struct sha_dev_t { + volatile sha_mode_reg_t mode; + uint32_t reserved_004[2]; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t continue; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + uint32_t reserved_030[4]; + volatile uint32_t h[16]; + volatile uint32_t m[16]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h new file mode 100644 index 00000000000..f7a2ee0a133 --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +/** + * @brief Reg base address for multi-instance peripherals + * @note common multi-instance peripherals includes + * I2C, I2S, UART, UHCI, SPI, SPIMEM, MCPWM, TWAI, TIMER_GROUP + * please check `reg_base.h` and the corresponding `xxx_reg.h` whether the base addresses are match + */ +#define REG_I2C_BASE(i) ((i) == 0 ? DR_REG_I2C0_BASE : DR_REG_I2C1_BASE) // two I2C on C5 +#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 +#define REG_TWAI_BASE(i) ((i) == 0 ? DR_REG_TWAI0_BASE : DR_REG_TWAI1_BASE) // TWAI0 and TWAI1 +#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ ( 40*1000000 ) +#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +#define XTAL_CLK_FREQ (40*1000000) +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8)) +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40050000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40050000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40880000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40880000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C5 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50004000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50004000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50004000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40880000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40880000 + +#define MAP_DRAM_TO_IRAM(addr) (addr) +#define MAP_IRAM_TO_DRAM(addr) (addr) + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40880000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40880000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40880000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40880000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4087e610 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h new file mode 100644 index 00000000000..bd01111d290 --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -0,0 +1,562 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 +// #define SOC_UART_SUPPORTED 1 +// #define SOC_GDMA_SUPPORTED 1 +// #define SOC_AHB_GDMA_SUPPORTED 1 +// #define SOC_GPTIMER_SUPPORTED 1 +// #define SOC_PCNT_SUPPORTED 1 +// #define SOC_MCPWM_SUPPORTED 1 +// #define SOC_TWAI_SUPPORTED 1 +// #define SOC_ETM_SUPPORTED 1 +// #define SOC_PARLIO_SUPPORTED 1 +// #define SOC_BT_SUPPORTED 1 +// #define SOC_IEEE802154_SUPPORTED 1 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 +// #define SOC_WIFI_SUPPORTED 1 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 +// #define SOC_ULP_SUPPORTED 1 +// #define SOC_LP_CORE_SUPPORTED 1 +// #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +// #define SOC_EFUSE_SUPPORTED 1 +// #define SOC_RTC_FAST_MEM_SUPPORTED 1 +// #define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 +// #define SOC_RMT_SUPPORTED 1 +// #define SOC_SDM_SUPPORTED 1 +// #define SOC_GPSPI_SUPPORTED 1 +// #define SOC_LEDC_SUPPORTED 1 +// #define SOC_I2C_SUPPORTED 1 +// #define SOC_SYSTIMER_SUPPORTED 1 +// #define SOC_SUPPORT_COEXISTENCE 1 +// #define SOC_AES_SUPPORTED 1 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 +// #define SOC_HMAC_SUPPORTED 1 +// #define SOC_DIG_SIGN_SUPPORTED 1 +// #define SOC_ECC_SUPPORTED 1 +// #define SOC_FLASH_ENC_SUPPORTED 1 +// #define SOC_SECURE_BOOT_SUPPORTED 1 +// #define SOC_SDIO_SLAVE_SUPPORTED 1 +// #define SOC_BOD_SUPPORTED 1 +// #define SOC_APM_SUPPORTED 1 +// #define SOC_PMU_SUPPORTED 1 +// #define SOC_PAU_SUPPORTED 1 +// #define SOC_LP_TIMER_SUPPORTED 1 +// #define SOC_LP_AON_SUPPORTED 1 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 +// #define SOC_LP_I2C_SUPPORTED 1 +// #define SOC_ULP_LP_UART_SUPPORTED 1 +// #define SOC_CLK_TREE_SUPPORTED 1 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 +// #define SOC_WDT_SUPPORTED 1 +// #define SOC_SPI_FLASH_SUPPORTED 1 +// #define SOC_BITSCRAMBLER_SUPPORTED 1 +// #define SOC_ECDSA_SUPPORTED 1 +// #define SOC_KEY_MANAGER_SUPPORTED 1 +#define SOC_INT_HW_NESTED_SUPPORTED 1 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +// #define SOC_XTAL_SUPPORT_40M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +// #define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +// #define SOC_AES_GDMA (1) + +// #define SOC_AES_SUPPORT_AES_128 (1) +// #define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +// #define SOC_ADC_PERIPH_NUM (1U) +// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +// #define SOC_ADC_MAX_CHANNEL_NUM (7) +// #define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) +// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) +// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +// #define SOC_ADC_DIGI_MONITOR_NUM (2) +// #define SOC_ADC_DIGI_RESULT_BYTES (4) +// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +// #define SOC_ADC_RTC_MIN_BITWIDTH (12) +// #define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +// #define SOC_ADC_SHARED_POWER 1 + +// ESP32C5-TODO: Copy from esp32C5, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +// #define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +// #define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +// #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +// #define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +// #define SOC_CPU_INTR_NUM 32 +// #define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_CLIC_SUPPORTED 1 + +// #define SOC_CPU_BREAKPOINTS_NUM 4 +// #define SOC_CPU_WATCHPOINTS_NUM 4 +// #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes + +// #define SOC_CPU_HAS_PMA 1 +// #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +// #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +// #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +// #define SOC_AHB_GDMA_VERSION 1U +// #define SOC_GDMA_NUM_GROUPS_MAX 1U +// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule + +/*-------------------------- ETM CAPS --------------------------------------*/ +// #define SOC_ETM_GROUPS 1U // Number of ETM groups +// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C5 has 1 GPIO peripheral +// #define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 31 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 +// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 + +// Target has the full LP IO subsystem +// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +// #define SOC_GPIO_VALID_GPIO_MASK ((1U< SPI0/SPI1, host_id = 1 -> SPI2, +// #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// #define SOC_MEMSPI_IS_INDEPENDENT 1 +// #define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +// #define SOC_SPI_MEM_SUPPORT_WRAP (1) + +// #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +// #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +// #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +// #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +// #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +// #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +// #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +// #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +// #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +// #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +// #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +// #define SOC_MWDT_SUPPORT_XTAL (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +// #define SOC_TWAI_CONTROLLER_NUM 2 +// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 +// #define SOC_TWAI_BRP_MIN 2 +// #define SOC_TWAI_BRP_MAX 32768 +// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +// #define SOC_EFUSE_DIS_PAD_JTAG 1 +// #define SOC_EFUSE_DIS_USB_JTAG 1 +// #define SOC_EFUSE_DIS_DIRECT_BOOT 1 +// #define SOC_EFUSE_SOFT_DIS_JTAG 1 +// #define SOC_EFUSE_DIS_ICACHE 1 +// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block + +/*-------------------------- Secure Boot CAPS----------------------------*/ +// #define SOC_SECURE_BOOT_V2_RSA 1 +// #define SOC_SECURE_BOOT_V2_ECC 1 +// #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +// #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +// #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +// #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) +// #define SOC_FLASH_ENCRYPTION_XTS_AES 1 +// #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART) +#define SOC_UART_NUM (3) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_LP_NUM (1U) +// #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +// #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ +// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +// #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +// #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +// #define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +/*-------------------------- Power Management CAPS ----------------------------*/ +// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) +// #define SOC_PM_SUPPORT_BT_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SOC_ETM_CH_ENA_AD0_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED0 (BIT(0)) +#define SOC_ETM_CH_ENABLED0_M (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S) +#define SOC_ETM_CH_ENABLED0_V 0x00000001U +#define SOC_ETM_CH_ENABLED0_S 0 +/** SOC_ETM_CH_ENABLED1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED1 (BIT(1)) +#define SOC_ETM_CH_ENABLED1_M (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S) +#define SOC_ETM_CH_ENABLED1_V 0x00000001U +#define SOC_ETM_CH_ENABLED1_S 1 +/** SOC_ETM_CH_ENABLED2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED2 (BIT(2)) +#define SOC_ETM_CH_ENABLED2_M (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S) +#define SOC_ETM_CH_ENABLED2_V 0x00000001U +#define SOC_ETM_CH_ENABLED2_S 2 +/** SOC_ETM_CH_ENABLED3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED3 (BIT(3)) +#define SOC_ETM_CH_ENABLED3_M (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S) +#define SOC_ETM_CH_ENABLED3_V 0x00000001U +#define SOC_ETM_CH_ENABLED3_S 3 +/** SOC_ETM_CH_ENABLED4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED4 (BIT(4)) +#define SOC_ETM_CH_ENABLED4_M (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S) +#define SOC_ETM_CH_ENABLED4_V 0x00000001U +#define SOC_ETM_CH_ENABLED4_S 4 +/** SOC_ETM_CH_ENABLED5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED5 (BIT(5)) +#define SOC_ETM_CH_ENABLED5_M (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S) +#define SOC_ETM_CH_ENABLED5_V 0x00000001U +#define SOC_ETM_CH_ENABLED5_S 5 +/** SOC_ETM_CH_ENABLED6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED6 (BIT(6)) +#define SOC_ETM_CH_ENABLED6_M (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S) +#define SOC_ETM_CH_ENABLED6_V 0x00000001U +#define SOC_ETM_CH_ENABLED6_S 6 +/** SOC_ETM_CH_ENABLED7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED7 (BIT(7)) +#define SOC_ETM_CH_ENABLED7_M (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S) +#define SOC_ETM_CH_ENABLED7_V 0x00000001U +#define SOC_ETM_CH_ENABLED7_S 7 +/** SOC_ETM_CH_ENABLED8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED8 (BIT(8)) +#define SOC_ETM_CH_ENABLED8_M (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S) +#define SOC_ETM_CH_ENABLED8_V 0x00000001U +#define SOC_ETM_CH_ENABLED8_S 8 +/** SOC_ETM_CH_ENABLED9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED9 (BIT(9)) +#define SOC_ETM_CH_ENABLED9_M (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S) +#define SOC_ETM_CH_ENABLED9_V 0x00000001U +#define SOC_ETM_CH_ENABLED9_S 9 +/** SOC_ETM_CH_ENABLED10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED10 (BIT(10)) +#define SOC_ETM_CH_ENABLED10_M (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S) +#define SOC_ETM_CH_ENABLED10_V 0x00000001U +#define SOC_ETM_CH_ENABLED10_S 10 +/** SOC_ETM_CH_ENABLED11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED11 (BIT(11)) +#define SOC_ETM_CH_ENABLED11_M (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S) +#define SOC_ETM_CH_ENABLED11_V 0x00000001U +#define SOC_ETM_CH_ENABLED11_S 11 +/** SOC_ETM_CH_ENABLED12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED12 (BIT(12)) +#define SOC_ETM_CH_ENABLED12_M (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S) +#define SOC_ETM_CH_ENABLED12_V 0x00000001U +#define SOC_ETM_CH_ENABLED12_S 12 +/** SOC_ETM_CH_ENABLED13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED13 (BIT(13)) +#define SOC_ETM_CH_ENABLED13_M (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S) +#define SOC_ETM_CH_ENABLED13_V 0x00000001U +#define SOC_ETM_CH_ENABLED13_S 13 +/** SOC_ETM_CH_ENABLED14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED14 (BIT(14)) +#define SOC_ETM_CH_ENABLED14_M (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S) +#define SOC_ETM_CH_ENABLED14_V 0x00000001U +#define SOC_ETM_CH_ENABLED14_S 14 +/** SOC_ETM_CH_ENABLED15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED15 (BIT(15)) +#define SOC_ETM_CH_ENABLED15_M (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S) +#define SOC_ETM_CH_ENABLED15_V 0x00000001U +#define SOC_ETM_CH_ENABLED15_S 15 +/** SOC_ETM_CH_ENABLED16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED16 (BIT(16)) +#define SOC_ETM_CH_ENABLED16_M (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S) +#define SOC_ETM_CH_ENABLED16_V 0x00000001U +#define SOC_ETM_CH_ENABLED16_S 16 +/** SOC_ETM_CH_ENABLED17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED17 (BIT(17)) +#define SOC_ETM_CH_ENABLED17_M (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S) +#define SOC_ETM_CH_ENABLED17_V 0x00000001U +#define SOC_ETM_CH_ENABLED17_S 17 +/** SOC_ETM_CH_ENABLED18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED18 (BIT(18)) +#define SOC_ETM_CH_ENABLED18_M (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S) +#define SOC_ETM_CH_ENABLED18_V 0x00000001U +#define SOC_ETM_CH_ENABLED18_S 18 +/** SOC_ETM_CH_ENABLED19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED19 (BIT(19)) +#define SOC_ETM_CH_ENABLED19_M (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S) +#define SOC_ETM_CH_ENABLED19_V 0x00000001U +#define SOC_ETM_CH_ENABLED19_S 19 +/** SOC_ETM_CH_ENABLED20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED20 (BIT(20)) +#define SOC_ETM_CH_ENABLED20_M (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S) +#define SOC_ETM_CH_ENABLED20_V 0x00000001U +#define SOC_ETM_CH_ENABLED20_S 20 +/** SOC_ETM_CH_ENABLED21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED21 (BIT(21)) +#define SOC_ETM_CH_ENABLED21_M (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S) +#define SOC_ETM_CH_ENABLED21_V 0x00000001U +#define SOC_ETM_CH_ENABLED21_S 21 +/** SOC_ETM_CH_ENABLED22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED22 (BIT(22)) +#define SOC_ETM_CH_ENABLED22_M (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S) +#define SOC_ETM_CH_ENABLED22_V 0x00000001U +#define SOC_ETM_CH_ENABLED22_S 22 +/** SOC_ETM_CH_ENABLED23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED23 (BIT(23)) +#define SOC_ETM_CH_ENABLED23_M (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S) +#define SOC_ETM_CH_ENABLED23_V 0x00000001U +#define SOC_ETM_CH_ENABLED23_S 23 +/** SOC_ETM_CH_ENABLED24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED24 (BIT(24)) +#define SOC_ETM_CH_ENABLED24_M (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S) +#define SOC_ETM_CH_ENABLED24_V 0x00000001U +#define SOC_ETM_CH_ENABLED24_S 24 +/** SOC_ETM_CH_ENABLED25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED25 (BIT(25)) +#define SOC_ETM_CH_ENABLED25_M (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S) +#define SOC_ETM_CH_ENABLED25_V 0x00000001U +#define SOC_ETM_CH_ENABLED25_S 25 +/** SOC_ETM_CH_ENABLED26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED26 (BIT(26)) +#define SOC_ETM_CH_ENABLED26_M (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S) +#define SOC_ETM_CH_ENABLED26_V 0x00000001U +#define SOC_ETM_CH_ENABLED26_S 26 +/** SOC_ETM_CH_ENABLED27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED27 (BIT(27)) +#define SOC_ETM_CH_ENABLED27_M (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S) +#define SOC_ETM_CH_ENABLED27_V 0x00000001U +#define SOC_ETM_CH_ENABLED27_S 27 +/** SOC_ETM_CH_ENABLED28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED28 (BIT(28)) +#define SOC_ETM_CH_ENABLED28_M (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S) +#define SOC_ETM_CH_ENABLED28_V 0x00000001U +#define SOC_ETM_CH_ENABLED28_S 28 +/** SOC_ETM_CH_ENABLED29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED29 (BIT(29)) +#define SOC_ETM_CH_ENABLED29_M (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S) +#define SOC_ETM_CH_ENABLED29_V 0x00000001U +#define SOC_ETM_CH_ENABLED29_S 29 +/** SOC_ETM_CH_ENABLED30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED30 (BIT(30)) +#define SOC_ETM_CH_ENABLED30_M (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S) +#define SOC_ETM_CH_ENABLED30_V 0x00000001U +#define SOC_ETM_CH_ENABLED30_S 30 +/** SOC_ETM_CH_ENABLED31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED31 (BIT(31)) +#define SOC_ETM_CH_ENABLED31_M (SOC_ETM_CH_ENABLED31_V << SOC_ETM_CH_ENABLED31_S) +#define SOC_ETM_CH_ENABLED31_V 0x00000001U +#define SOC_ETM_CH_ENABLED31_S 31 + +/** SOC_ETM_CH_ENA_AD0_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE0 (BIT(0)) +#define SOC_ETM_CH_ENABLE0_M (SOC_ETM_CH_ENABLE0_V << SOC_ETM_CH_ENABLE0_S) +#define SOC_ETM_CH_ENABLE0_V 0x00000001U +#define SOC_ETM_CH_ENABLE0_S 0 +/** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE1 (BIT(1)) +#define SOC_ETM_CH_ENABLE1_M (SOC_ETM_CH_ENABLE1_V << SOC_ETM_CH_ENABLE1_S) +#define SOC_ETM_CH_ENABLE1_V 0x00000001U +#define SOC_ETM_CH_ENABLE1_S 1 +/** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE2 (BIT(2)) +#define SOC_ETM_CH_ENABLE2_M (SOC_ETM_CH_ENABLE2_V << SOC_ETM_CH_ENABLE2_S) +#define SOC_ETM_CH_ENABLE2_V 0x00000001U +#define SOC_ETM_CH_ENABLE2_S 2 +/** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE3 (BIT(3)) +#define SOC_ETM_CH_ENABLE3_M (SOC_ETM_CH_ENABLE3_V << SOC_ETM_CH_ENABLE3_S) +#define SOC_ETM_CH_ENABLE3_V 0x00000001U +#define SOC_ETM_CH_ENABLE3_S 3 +/** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE4 (BIT(4)) +#define SOC_ETM_CH_ENABLE4_M (SOC_ETM_CH_ENABLE4_V << SOC_ETM_CH_ENABLE4_S) +#define SOC_ETM_CH_ENABLE4_V 0x00000001U +#define SOC_ETM_CH_ENABLE4_S 4 +/** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE5 (BIT(5)) +#define SOC_ETM_CH_ENABLE5_M (SOC_ETM_CH_ENABLE5_V << SOC_ETM_CH_ENABLE5_S) +#define SOC_ETM_CH_ENABLE5_V 0x00000001U +#define SOC_ETM_CH_ENABLE5_S 5 +/** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE6 (BIT(6)) +#define SOC_ETM_CH_ENABLE6_M (SOC_ETM_CH_ENABLE6_V << SOC_ETM_CH_ENABLE6_S) +#define SOC_ETM_CH_ENABLE6_V 0x00000001U +#define SOC_ETM_CH_ENABLE6_S 6 +/** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE7 (BIT(7)) +#define SOC_ETM_CH_ENABLE7_M (SOC_ETM_CH_ENABLE7_V << SOC_ETM_CH_ENABLE7_S) +#define SOC_ETM_CH_ENABLE7_V 0x00000001U +#define SOC_ETM_CH_ENABLE7_S 7 +/** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE8 (BIT(8)) +#define SOC_ETM_CH_ENABLE8_M (SOC_ETM_CH_ENABLE8_V << SOC_ETM_CH_ENABLE8_S) +#define SOC_ETM_CH_ENABLE8_V 0x00000001U +#define SOC_ETM_CH_ENABLE8_S 8 +/** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE9 (BIT(9)) +#define SOC_ETM_CH_ENABLE9_M (SOC_ETM_CH_ENABLE9_V << SOC_ETM_CH_ENABLE9_S) +#define SOC_ETM_CH_ENABLE9_V 0x00000001U +#define SOC_ETM_CH_ENABLE9_S 9 +/** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE10 (BIT(10)) +#define SOC_ETM_CH_ENABLE10_M (SOC_ETM_CH_ENABLE10_V << SOC_ETM_CH_ENABLE10_S) +#define SOC_ETM_CH_ENABLE10_V 0x00000001U +#define SOC_ETM_CH_ENABLE10_S 10 +/** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE11 (BIT(11)) +#define SOC_ETM_CH_ENABLE11_M (SOC_ETM_CH_ENABLE11_V << SOC_ETM_CH_ENABLE11_S) +#define SOC_ETM_CH_ENABLE11_V 0x00000001U +#define SOC_ETM_CH_ENABLE11_S 11 +/** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE12 (BIT(12)) +#define SOC_ETM_CH_ENABLE12_M (SOC_ETM_CH_ENABLE12_V << SOC_ETM_CH_ENABLE12_S) +#define SOC_ETM_CH_ENABLE12_V 0x00000001U +#define SOC_ETM_CH_ENABLE12_S 12 +/** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE13 (BIT(13)) +#define SOC_ETM_CH_ENABLE13_M (SOC_ETM_CH_ENABLE13_V << SOC_ETM_CH_ENABLE13_S) +#define SOC_ETM_CH_ENABLE13_V 0x00000001U +#define SOC_ETM_CH_ENABLE13_S 13 +/** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE14 (BIT(14)) +#define SOC_ETM_CH_ENABLE14_M (SOC_ETM_CH_ENABLE14_V << SOC_ETM_CH_ENABLE14_S) +#define SOC_ETM_CH_ENABLE14_V 0x00000001U +#define SOC_ETM_CH_ENABLE14_S 14 +/** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE15 (BIT(15)) +#define SOC_ETM_CH_ENABLE15_M (SOC_ETM_CH_ENABLE15_V << SOC_ETM_CH_ENABLE15_S) +#define SOC_ETM_CH_ENABLE15_V 0x00000001U +#define SOC_ETM_CH_ENABLE15_S 15 +/** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE16 (BIT(16)) +#define SOC_ETM_CH_ENABLE16_M (SOC_ETM_CH_ENABLE16_V << SOC_ETM_CH_ENABLE16_S) +#define SOC_ETM_CH_ENABLE16_V 0x00000001U +#define SOC_ETM_CH_ENABLE16_S 16 +/** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE17 (BIT(17)) +#define SOC_ETM_CH_ENABLE17_M (SOC_ETM_CH_ENABLE17_V << SOC_ETM_CH_ENABLE17_S) +#define SOC_ETM_CH_ENABLE17_V 0x00000001U +#define SOC_ETM_CH_ENABLE17_S 17 +/** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE18 (BIT(18)) +#define SOC_ETM_CH_ENABLE18_M (SOC_ETM_CH_ENABLE18_V << SOC_ETM_CH_ENABLE18_S) +#define SOC_ETM_CH_ENABLE18_V 0x00000001U +#define SOC_ETM_CH_ENABLE18_S 18 +/** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE19 (BIT(19)) +#define SOC_ETM_CH_ENABLE19_M (SOC_ETM_CH_ENABLE19_V << SOC_ETM_CH_ENABLE19_S) +#define SOC_ETM_CH_ENABLE19_V 0x00000001U +#define SOC_ETM_CH_ENABLE19_S 19 +/** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE20 (BIT(20)) +#define SOC_ETM_CH_ENABLE20_M (SOC_ETM_CH_ENABLE20_V << SOC_ETM_CH_ENABLE20_S) +#define SOC_ETM_CH_ENABLE20_V 0x00000001U +#define SOC_ETM_CH_ENABLE20_S 20 +/** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE21 (BIT(21)) +#define SOC_ETM_CH_ENABLE21_M (SOC_ETM_CH_ENABLE21_V << SOC_ETM_CH_ENABLE21_S) +#define SOC_ETM_CH_ENABLE21_V 0x00000001U +#define SOC_ETM_CH_ENABLE21_S 21 +/** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE22 (BIT(22)) +#define SOC_ETM_CH_ENABLE22_M (SOC_ETM_CH_ENABLE22_V << SOC_ETM_CH_ENABLE22_S) +#define SOC_ETM_CH_ENABLE22_V 0x00000001U +#define SOC_ETM_CH_ENABLE22_S 22 +/** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE23 (BIT(23)) +#define SOC_ETM_CH_ENABLE23_M (SOC_ETM_CH_ENABLE23_V << SOC_ETM_CH_ENABLE23_S) +#define SOC_ETM_CH_ENABLE23_V 0x00000001U +#define SOC_ETM_CH_ENABLE23_S 23 +/** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE24 (BIT(24)) +#define SOC_ETM_CH_ENABLE24_M (SOC_ETM_CH_ENABLE24_V << SOC_ETM_CH_ENABLE24_S) +#define SOC_ETM_CH_ENABLE24_V 0x00000001U +#define SOC_ETM_CH_ENABLE24_S 24 +/** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE25 (BIT(25)) +#define SOC_ETM_CH_ENABLE25_M (SOC_ETM_CH_ENABLE25_V << SOC_ETM_CH_ENABLE25_S) +#define SOC_ETM_CH_ENABLE25_V 0x00000001U +#define SOC_ETM_CH_ENABLE25_S 25 +/** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE26 (BIT(26)) +#define SOC_ETM_CH_ENABLE26_M (SOC_ETM_CH_ENABLE26_V << SOC_ETM_CH_ENABLE26_S) +#define SOC_ETM_CH_ENABLE26_V 0x00000001U +#define SOC_ETM_CH_ENABLE26_S 26 +/** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE27 (BIT(27)) +#define SOC_ETM_CH_ENABLE27_M (SOC_ETM_CH_ENABLE27_V << SOC_ETM_CH_ENABLE27_S) +#define SOC_ETM_CH_ENABLE27_V 0x00000001U +#define SOC_ETM_CH_ENABLE27_S 27 +/** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE28 (BIT(28)) +#define SOC_ETM_CH_ENABLE28_M (SOC_ETM_CH_ENABLE28_V << SOC_ETM_CH_ENABLE28_S) +#define SOC_ETM_CH_ENABLE28_V 0x00000001U +#define SOC_ETM_CH_ENABLE28_S 28 +/** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE29 (BIT(29)) +#define SOC_ETM_CH_ENABLE29_M (SOC_ETM_CH_ENABLE29_V << SOC_ETM_CH_ENABLE29_S) +#define SOC_ETM_CH_ENABLE29_V 0x00000001U +#define SOC_ETM_CH_ENABLE29_S 29 +/** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE30 (BIT(30)) +#define SOC_ETM_CH_ENABLE30_M (SOC_ETM_CH_ENABLE30_V << SOC_ETM_CH_ENABLE30_S) +#define SOC_ETM_CH_ENABLE30_V 0x00000001U +#define SOC_ETM_CH_ENABLE30_S 30 +/** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE31 (BIT(31)) +#define SOC_ETM_CH_ENABLE31_M (SOC_ETM_CH_ENABLE31_V << SOC_ETM_CH_ENABLE31_S) +#define SOC_ETM_CH_ENABLE31_V 0x00000001U +#define SOC_ETM_CH_ENABLE31_S 31 + +/** SOC_ETM_CH_ENA_AD0_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE0 (BIT(0)) +#define SOC_ETM_CH_DISABLE0_M (SOC_ETM_CH_DISABLE0_V << SOC_ETM_CH_DISABLE0_S) +#define SOC_ETM_CH_DISABLE0_V 0x00000001U +#define SOC_ETM_CH_DISABLE0_S 0 +/** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE1 (BIT(1)) +#define SOC_ETM_CH_DISABLE1_M (SOC_ETM_CH_DISABLE1_V << SOC_ETM_CH_DISABLE1_S) +#define SOC_ETM_CH_DISABLE1_V 0x00000001U +#define SOC_ETM_CH_DISABLE1_S 1 +/** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE2 (BIT(2)) +#define SOC_ETM_CH_DISABLE2_M (SOC_ETM_CH_DISABLE2_V << SOC_ETM_CH_DISABLE2_S) +#define SOC_ETM_CH_DISABLE2_V 0x00000001U +#define SOC_ETM_CH_DISABLE2_S 2 +/** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE3 (BIT(3)) +#define SOC_ETM_CH_DISABLE3_M (SOC_ETM_CH_DISABLE3_V << SOC_ETM_CH_DISABLE3_S) +#define SOC_ETM_CH_DISABLE3_V 0x00000001U +#define SOC_ETM_CH_DISABLE3_S 3 +/** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE4 (BIT(4)) +#define SOC_ETM_CH_DISABLE4_M (SOC_ETM_CH_DISABLE4_V << SOC_ETM_CH_DISABLE4_S) +#define SOC_ETM_CH_DISABLE4_V 0x00000001U +#define SOC_ETM_CH_DISABLE4_S 4 +/** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE5 (BIT(5)) +#define SOC_ETM_CH_DISABLE5_M (SOC_ETM_CH_DISABLE5_V << SOC_ETM_CH_DISABLE5_S) +#define SOC_ETM_CH_DISABLE5_V 0x00000001U +#define SOC_ETM_CH_DISABLE5_S 5 +/** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE6 (BIT(6)) +#define SOC_ETM_CH_DISABLE6_M (SOC_ETM_CH_DISABLE6_V << SOC_ETM_CH_DISABLE6_S) +#define SOC_ETM_CH_DISABLE6_V 0x00000001U +#define SOC_ETM_CH_DISABLE6_S 6 +/** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE7 (BIT(7)) +#define SOC_ETM_CH_DISABLE7_M (SOC_ETM_CH_DISABLE7_V << SOC_ETM_CH_DISABLE7_S) +#define SOC_ETM_CH_DISABLE7_V 0x00000001U +#define SOC_ETM_CH_DISABLE7_S 7 +/** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE8 (BIT(8)) +#define SOC_ETM_CH_DISABLE8_M (SOC_ETM_CH_DISABLE8_V << SOC_ETM_CH_DISABLE8_S) +#define SOC_ETM_CH_DISABLE8_V 0x00000001U +#define SOC_ETM_CH_DISABLE8_S 8 +/** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE9 (BIT(9)) +#define SOC_ETM_CH_DISABLE9_M (SOC_ETM_CH_DISABLE9_V << SOC_ETM_CH_DISABLE9_S) +#define SOC_ETM_CH_DISABLE9_V 0x00000001U +#define SOC_ETM_CH_DISABLE9_S 9 +/** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE10 (BIT(10)) +#define SOC_ETM_CH_DISABLE10_M (SOC_ETM_CH_DISABLE10_V << SOC_ETM_CH_DISABLE10_S) +#define SOC_ETM_CH_DISABLE10_V 0x00000001U +#define SOC_ETM_CH_DISABLE10_S 10 +/** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE11 (BIT(11)) +#define SOC_ETM_CH_DISABLE11_M (SOC_ETM_CH_DISABLE11_V << SOC_ETM_CH_DISABLE11_S) +#define SOC_ETM_CH_DISABLE11_V 0x00000001U +#define SOC_ETM_CH_DISABLE11_S 11 +/** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE12 (BIT(12)) +#define SOC_ETM_CH_DISABLE12_M (SOC_ETM_CH_DISABLE12_V << SOC_ETM_CH_DISABLE12_S) +#define SOC_ETM_CH_DISABLE12_V 0x00000001U +#define SOC_ETM_CH_DISABLE12_S 12 +/** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE13 (BIT(13)) +#define SOC_ETM_CH_DISABLE13_M (SOC_ETM_CH_DISABLE13_V << SOC_ETM_CH_DISABLE13_S) +#define SOC_ETM_CH_DISABLE13_V 0x00000001U +#define SOC_ETM_CH_DISABLE13_S 13 +/** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE14 (BIT(14)) +#define SOC_ETM_CH_DISABLE14_M (SOC_ETM_CH_DISABLE14_V << SOC_ETM_CH_DISABLE14_S) +#define SOC_ETM_CH_DISABLE14_V 0x00000001U +#define SOC_ETM_CH_DISABLE14_S 14 +/** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE15 (BIT(15)) +#define SOC_ETM_CH_DISABLE15_M (SOC_ETM_CH_DISABLE15_V << SOC_ETM_CH_DISABLE15_S) +#define SOC_ETM_CH_DISABLE15_V 0x00000001U +#define SOC_ETM_CH_DISABLE15_S 15 +/** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE16 (BIT(16)) +#define SOC_ETM_CH_DISABLE16_M (SOC_ETM_CH_DISABLE16_V << SOC_ETM_CH_DISABLE16_S) +#define SOC_ETM_CH_DISABLE16_V 0x00000001U +#define SOC_ETM_CH_DISABLE16_S 16 +/** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE17 (BIT(17)) +#define SOC_ETM_CH_DISABLE17_M (SOC_ETM_CH_DISABLE17_V << SOC_ETM_CH_DISABLE17_S) +#define SOC_ETM_CH_DISABLE17_V 0x00000001U +#define SOC_ETM_CH_DISABLE17_S 17 +/** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE18 (BIT(18)) +#define SOC_ETM_CH_DISABLE18_M (SOC_ETM_CH_DISABLE18_V << SOC_ETM_CH_DISABLE18_S) +#define SOC_ETM_CH_DISABLE18_V 0x00000001U +#define SOC_ETM_CH_DISABLE18_S 18 +/** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE19 (BIT(19)) +#define SOC_ETM_CH_DISABLE19_M (SOC_ETM_CH_DISABLE19_V << SOC_ETM_CH_DISABLE19_S) +#define SOC_ETM_CH_DISABLE19_V 0x00000001U +#define SOC_ETM_CH_DISABLE19_S 19 +/** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE20 (BIT(20)) +#define SOC_ETM_CH_DISABLE20_M (SOC_ETM_CH_DISABLE20_V << SOC_ETM_CH_DISABLE20_S) +#define SOC_ETM_CH_DISABLE20_V 0x00000001U +#define SOC_ETM_CH_DISABLE20_S 20 +/** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE21 (BIT(21)) +#define SOC_ETM_CH_DISABLE21_M (SOC_ETM_CH_DISABLE21_V << SOC_ETM_CH_DISABLE21_S) +#define SOC_ETM_CH_DISABLE21_V 0x00000001U +#define SOC_ETM_CH_DISABLE21_S 21 +/** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE22 (BIT(22)) +#define SOC_ETM_CH_DISABLE22_M (SOC_ETM_CH_DISABLE22_V << SOC_ETM_CH_DISABLE22_S) +#define SOC_ETM_CH_DISABLE22_V 0x00000001U +#define SOC_ETM_CH_DISABLE22_S 22 +/** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE23 (BIT(23)) +#define SOC_ETM_CH_DISABLE23_M (SOC_ETM_CH_DISABLE23_V << SOC_ETM_CH_DISABLE23_S) +#define SOC_ETM_CH_DISABLE23_V 0x00000001U +#define SOC_ETM_CH_DISABLE23_S 23 +/** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE24 (BIT(24)) +#define SOC_ETM_CH_DISABLE24_M (SOC_ETM_CH_DISABLE24_V << SOC_ETM_CH_DISABLE24_S) +#define SOC_ETM_CH_DISABLE24_V 0x00000001U +#define SOC_ETM_CH_DISABLE24_S 24 +/** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE25 (BIT(25)) +#define SOC_ETM_CH_DISABLE25_M (SOC_ETM_CH_DISABLE25_V << SOC_ETM_CH_DISABLE25_S) +#define SOC_ETM_CH_DISABLE25_V 0x00000001U +#define SOC_ETM_CH_DISABLE25_S 25 +/** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE26 (BIT(26)) +#define SOC_ETM_CH_DISABLE26_M (SOC_ETM_CH_DISABLE26_V << SOC_ETM_CH_DISABLE26_S) +#define SOC_ETM_CH_DISABLE26_V 0x00000001U +#define SOC_ETM_CH_DISABLE26_S 26 +/** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE27 (BIT(27)) +#define SOC_ETM_CH_DISABLE27_M (SOC_ETM_CH_DISABLE27_V << SOC_ETM_CH_DISABLE27_S) +#define SOC_ETM_CH_DISABLE27_V 0x00000001U +#define SOC_ETM_CH_DISABLE27_S 27 +/** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE28 (BIT(28)) +#define SOC_ETM_CH_DISABLE28_M (SOC_ETM_CH_DISABLE28_V << SOC_ETM_CH_DISABLE28_S) +#define SOC_ETM_CH_DISABLE28_V 0x00000001U +#define SOC_ETM_CH_DISABLE28_S 28 +/** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE29 (BIT(29)) +#define SOC_ETM_CH_DISABLE29_M (SOC_ETM_CH_DISABLE29_V << SOC_ETM_CH_DISABLE29_S) +#define SOC_ETM_CH_DISABLE29_V 0x00000001U +#define SOC_ETM_CH_DISABLE29_S 29 +/** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE30 (BIT(30)) +#define SOC_ETM_CH_DISABLE30_M (SOC_ETM_CH_DISABLE30_V << SOC_ETM_CH_DISABLE30_S) +#define SOC_ETM_CH_DISABLE30_V 0x00000001U +#define SOC_ETM_CH_DISABLE30_S 30 +/** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE31 (BIT(31)) +#define SOC_ETM_CH_DISABLE31_M (SOC_ETM_CH_DISABLE31_V << SOC_ETM_CH_DISABLE31_S) +#define SOC_ETM_CH_DISABLE31_V 0x00000001U +#define SOC_ETM_CH_DISABLE31_S 31 + +/** SOC_ETM_CH_ENA_AD1_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED32 (BIT(0)) +#define SOC_ETM_CH_ENABLED32_M (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S) +#define SOC_ETM_CH_ENABLED32_V 0x00000001U +#define SOC_ETM_CH_ENABLED32_S 0 +/** SOC_ETM_CH_ENABLED33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED33 (BIT(1)) +#define SOC_ETM_CH_ENABLED33_M (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S) +#define SOC_ETM_CH_ENABLED33_V 0x00000001U +#define SOC_ETM_CH_ENABLED33_S 1 +/** SOC_ETM_CH_ENABLED34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED34 (BIT(2)) +#define SOC_ETM_CH_ENABLED34_M (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S) +#define SOC_ETM_CH_ENABLED34_V 0x00000001U +#define SOC_ETM_CH_ENABLED34_S 2 +/** SOC_ETM_CH_ENABLED35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED35 (BIT(3)) +#define SOC_ETM_CH_ENABLED35_M (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S) +#define SOC_ETM_CH_ENABLED35_V 0x00000001U +#define SOC_ETM_CH_ENABLED35_S 3 +/** SOC_ETM_CH_ENABLED36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED36 (BIT(4)) +#define SOC_ETM_CH_ENABLED36_M (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S) +#define SOC_ETM_CH_ENABLED36_V 0x00000001U +#define SOC_ETM_CH_ENABLED36_S 4 +/** SOC_ETM_CH_ENABLED37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED37 (BIT(5)) +#define SOC_ETM_CH_ENABLED37_M (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S) +#define SOC_ETM_CH_ENABLED37_V 0x00000001U +#define SOC_ETM_CH_ENABLED37_S 5 +/** SOC_ETM_CH_ENABLED38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED38 (BIT(6)) +#define SOC_ETM_CH_ENABLED38_M (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S) +#define SOC_ETM_CH_ENABLED38_V 0x00000001U +#define SOC_ETM_CH_ENABLED38_S 6 +/** SOC_ETM_CH_ENABLED39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED39 (BIT(7)) +#define SOC_ETM_CH_ENABLED39_M (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S) +#define SOC_ETM_CH_ENABLED39_V 0x00000001U +#define SOC_ETM_CH_ENABLED39_S 7 +/** SOC_ETM_CH_ENABLED40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED40 (BIT(8)) +#define SOC_ETM_CH_ENABLED40_M (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S) +#define SOC_ETM_CH_ENABLED40_V 0x00000001U +#define SOC_ETM_CH_ENABLED40_S 8 +/** SOC_ETM_CH_ENABLED41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED41 (BIT(9)) +#define SOC_ETM_CH_ENABLED41_M (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S) +#define SOC_ETM_CH_ENABLED41_V 0x00000001U +#define SOC_ETM_CH_ENABLED41_S 9 +/** SOC_ETM_CH_ENABLED42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED42 (BIT(10)) +#define SOC_ETM_CH_ENABLED42_M (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S) +#define SOC_ETM_CH_ENABLED42_V 0x00000001U +#define SOC_ETM_CH_ENABLED42_S 10 +/** SOC_ETM_CH_ENABLED43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED43 (BIT(11)) +#define SOC_ETM_CH_ENABLED43_M (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S) +#define SOC_ETM_CH_ENABLED43_V 0x00000001U +#define SOC_ETM_CH_ENABLED43_S 11 +/** SOC_ETM_CH_ENABLED44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED44 (BIT(12)) +#define SOC_ETM_CH_ENABLED44_M (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S) +#define SOC_ETM_CH_ENABLED44_V 0x00000001U +#define SOC_ETM_CH_ENABLED44_S 12 +/** SOC_ETM_CH_ENABLED45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED45 (BIT(13)) +#define SOC_ETM_CH_ENABLED45_M (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S) +#define SOC_ETM_CH_ENABLED45_V 0x00000001U +#define SOC_ETM_CH_ENABLED45_S 13 +/** SOC_ETM_CH_ENABLED46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED46 (BIT(14)) +#define SOC_ETM_CH_ENABLED46_M (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S) +#define SOC_ETM_CH_ENABLED46_V 0x00000001U +#define SOC_ETM_CH_ENABLED46_S 14 +/** SOC_ETM_CH_ENABLED47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED47 (BIT(15)) +#define SOC_ETM_CH_ENABLED47_M (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S) +#define SOC_ETM_CH_ENABLED47_V 0x00000001U +#define SOC_ETM_CH_ENABLED47_S 15 +/** SOC_ETM_CH_ENABLED48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED48 (BIT(16)) +#define SOC_ETM_CH_ENABLED48_M (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S) +#define SOC_ETM_CH_ENABLED48_V 0x00000001U +#define SOC_ETM_CH_ENABLED48_S 16 +/** SOC_ETM_CH_ENABLED49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED49 (BIT(17)) +#define SOC_ETM_CH_ENABLED49_M (SOC_ETM_CH_ENABLED49_V << SOC_ETM_CH_ENABLED49_S) +#define SOC_ETM_CH_ENABLED49_V 0x00000001U +#define SOC_ETM_CH_ENABLED49_S 17 + +/** SOC_ETM_CH_ENA_AD1_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE32 (BIT(0)) +#define SOC_ETM_CH_ENABLE32_M (SOC_ETM_CH_ENABLE32_V << SOC_ETM_CH_ENABLE32_S) +#define SOC_ETM_CH_ENABLE32_V 0x00000001U +#define SOC_ETM_CH_ENABLE32_S 0 +/** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE33 (BIT(1)) +#define SOC_ETM_CH_ENABLE33_M (SOC_ETM_CH_ENABLE33_V << SOC_ETM_CH_ENABLE33_S) +#define SOC_ETM_CH_ENABLE33_V 0x00000001U +#define SOC_ETM_CH_ENABLE33_S 1 +/** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE34 (BIT(2)) +#define SOC_ETM_CH_ENABLE34_M (SOC_ETM_CH_ENABLE34_V << SOC_ETM_CH_ENABLE34_S) +#define SOC_ETM_CH_ENABLE34_V 0x00000001U +#define SOC_ETM_CH_ENABLE34_S 2 +/** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE35 (BIT(3)) +#define SOC_ETM_CH_ENABLE35_M (SOC_ETM_CH_ENABLE35_V << SOC_ETM_CH_ENABLE35_S) +#define SOC_ETM_CH_ENABLE35_V 0x00000001U +#define SOC_ETM_CH_ENABLE35_S 3 +/** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE36 (BIT(4)) +#define SOC_ETM_CH_ENABLE36_M (SOC_ETM_CH_ENABLE36_V << SOC_ETM_CH_ENABLE36_S) +#define SOC_ETM_CH_ENABLE36_V 0x00000001U +#define SOC_ETM_CH_ENABLE36_S 4 +/** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE37 (BIT(5)) +#define SOC_ETM_CH_ENABLE37_M (SOC_ETM_CH_ENABLE37_V << SOC_ETM_CH_ENABLE37_S) +#define SOC_ETM_CH_ENABLE37_V 0x00000001U +#define SOC_ETM_CH_ENABLE37_S 5 +/** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE38 (BIT(6)) +#define SOC_ETM_CH_ENABLE38_M (SOC_ETM_CH_ENABLE38_V << SOC_ETM_CH_ENABLE38_S) +#define SOC_ETM_CH_ENABLE38_V 0x00000001U +#define SOC_ETM_CH_ENABLE38_S 6 +/** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE39 (BIT(7)) +#define SOC_ETM_CH_ENABLE39_M (SOC_ETM_CH_ENABLE39_V << SOC_ETM_CH_ENABLE39_S) +#define SOC_ETM_CH_ENABLE39_V 0x00000001U +#define SOC_ETM_CH_ENABLE39_S 7 +/** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE40 (BIT(8)) +#define SOC_ETM_CH_ENABLE40_M (SOC_ETM_CH_ENABLE40_V << SOC_ETM_CH_ENABLE40_S) +#define SOC_ETM_CH_ENABLE40_V 0x00000001U +#define SOC_ETM_CH_ENABLE40_S 8 +/** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE41 (BIT(9)) +#define SOC_ETM_CH_ENABLE41_M (SOC_ETM_CH_ENABLE41_V << SOC_ETM_CH_ENABLE41_S) +#define SOC_ETM_CH_ENABLE41_V 0x00000001U +#define SOC_ETM_CH_ENABLE41_S 9 +/** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE42 (BIT(10)) +#define SOC_ETM_CH_ENABLE42_M (SOC_ETM_CH_ENABLE42_V << SOC_ETM_CH_ENABLE42_S) +#define SOC_ETM_CH_ENABLE42_V 0x00000001U +#define SOC_ETM_CH_ENABLE42_S 10 +/** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE43 (BIT(11)) +#define SOC_ETM_CH_ENABLE43_M (SOC_ETM_CH_ENABLE43_V << SOC_ETM_CH_ENABLE43_S) +#define SOC_ETM_CH_ENABLE43_V 0x00000001U +#define SOC_ETM_CH_ENABLE43_S 11 +/** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE44 (BIT(12)) +#define SOC_ETM_CH_ENABLE44_M (SOC_ETM_CH_ENABLE44_V << SOC_ETM_CH_ENABLE44_S) +#define SOC_ETM_CH_ENABLE44_V 0x00000001U +#define SOC_ETM_CH_ENABLE44_S 12 +/** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE45 (BIT(13)) +#define SOC_ETM_CH_ENABLE45_M (SOC_ETM_CH_ENABLE45_V << SOC_ETM_CH_ENABLE45_S) +#define SOC_ETM_CH_ENABLE45_V 0x00000001U +#define SOC_ETM_CH_ENABLE45_S 13 +/** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE46 (BIT(14)) +#define SOC_ETM_CH_ENABLE46_M (SOC_ETM_CH_ENABLE46_V << SOC_ETM_CH_ENABLE46_S) +#define SOC_ETM_CH_ENABLE46_V 0x00000001U +#define SOC_ETM_CH_ENABLE46_S 14 +/** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE47 (BIT(15)) +#define SOC_ETM_CH_ENABLE47_M (SOC_ETM_CH_ENABLE47_V << SOC_ETM_CH_ENABLE47_S) +#define SOC_ETM_CH_ENABLE47_V 0x00000001U +#define SOC_ETM_CH_ENABLE47_S 15 +/** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE48 (BIT(16)) +#define SOC_ETM_CH_ENABLE48_M (SOC_ETM_CH_ENABLE48_V << SOC_ETM_CH_ENABLE48_S) +#define SOC_ETM_CH_ENABLE48_V 0x00000001U +#define SOC_ETM_CH_ENABLE48_S 16 +/** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE49 (BIT(17)) +#define SOC_ETM_CH_ENABLE49_M (SOC_ETM_CH_ENABLE49_V << SOC_ETM_CH_ENABLE49_S) +#define SOC_ETM_CH_ENABLE49_V 0x00000001U +#define SOC_ETM_CH_ENABLE49_S 17 + +/** SOC_ETM_CH_ENA_AD1_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE32 (BIT(0)) +#define SOC_ETM_CH_DISABLE32_M (SOC_ETM_CH_DISABLE32_V << SOC_ETM_CH_DISABLE32_S) +#define SOC_ETM_CH_DISABLE32_V 0x00000001U +#define SOC_ETM_CH_DISABLE32_S 0 +/** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE33 (BIT(1)) +#define SOC_ETM_CH_DISABLE33_M (SOC_ETM_CH_DISABLE33_V << SOC_ETM_CH_DISABLE33_S) +#define SOC_ETM_CH_DISABLE33_V 0x00000001U +#define SOC_ETM_CH_DISABLE33_S 1 +/** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE34 (BIT(2)) +#define SOC_ETM_CH_DISABLE34_M (SOC_ETM_CH_DISABLE34_V << SOC_ETM_CH_DISABLE34_S) +#define SOC_ETM_CH_DISABLE34_V 0x00000001U +#define SOC_ETM_CH_DISABLE34_S 2 +/** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE35 (BIT(3)) +#define SOC_ETM_CH_DISABLE35_M (SOC_ETM_CH_DISABLE35_V << SOC_ETM_CH_DISABLE35_S) +#define SOC_ETM_CH_DISABLE35_V 0x00000001U +#define SOC_ETM_CH_DISABLE35_S 3 +/** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE36 (BIT(4)) +#define SOC_ETM_CH_DISABLE36_M (SOC_ETM_CH_DISABLE36_V << SOC_ETM_CH_DISABLE36_S) +#define SOC_ETM_CH_DISABLE36_V 0x00000001U +#define SOC_ETM_CH_DISABLE36_S 4 +/** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE37 (BIT(5)) +#define SOC_ETM_CH_DISABLE37_M (SOC_ETM_CH_DISABLE37_V << SOC_ETM_CH_DISABLE37_S) +#define SOC_ETM_CH_DISABLE37_V 0x00000001U +#define SOC_ETM_CH_DISABLE37_S 5 +/** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE38 (BIT(6)) +#define SOC_ETM_CH_DISABLE38_M (SOC_ETM_CH_DISABLE38_V << SOC_ETM_CH_DISABLE38_S) +#define SOC_ETM_CH_DISABLE38_V 0x00000001U +#define SOC_ETM_CH_DISABLE38_S 6 +/** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE39 (BIT(7)) +#define SOC_ETM_CH_DISABLE39_M (SOC_ETM_CH_DISABLE39_V << SOC_ETM_CH_DISABLE39_S) +#define SOC_ETM_CH_DISABLE39_V 0x00000001U +#define SOC_ETM_CH_DISABLE39_S 7 +/** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE40 (BIT(8)) +#define SOC_ETM_CH_DISABLE40_M (SOC_ETM_CH_DISABLE40_V << SOC_ETM_CH_DISABLE40_S) +#define SOC_ETM_CH_DISABLE40_V 0x00000001U +#define SOC_ETM_CH_DISABLE40_S 8 +/** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE41 (BIT(9)) +#define SOC_ETM_CH_DISABLE41_M (SOC_ETM_CH_DISABLE41_V << SOC_ETM_CH_DISABLE41_S) +#define SOC_ETM_CH_DISABLE41_V 0x00000001U +#define SOC_ETM_CH_DISABLE41_S 9 +/** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE42 (BIT(10)) +#define SOC_ETM_CH_DISABLE42_M (SOC_ETM_CH_DISABLE42_V << SOC_ETM_CH_DISABLE42_S) +#define SOC_ETM_CH_DISABLE42_V 0x00000001U +#define SOC_ETM_CH_DISABLE42_S 10 +/** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE43 (BIT(11)) +#define SOC_ETM_CH_DISABLE43_M (SOC_ETM_CH_DISABLE43_V << SOC_ETM_CH_DISABLE43_S) +#define SOC_ETM_CH_DISABLE43_V 0x00000001U +#define SOC_ETM_CH_DISABLE43_S 11 +/** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE44 (BIT(12)) +#define SOC_ETM_CH_DISABLE44_M (SOC_ETM_CH_DISABLE44_V << SOC_ETM_CH_DISABLE44_S) +#define SOC_ETM_CH_DISABLE44_V 0x00000001U +#define SOC_ETM_CH_DISABLE44_S 12 +/** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE45 (BIT(13)) +#define SOC_ETM_CH_DISABLE45_M (SOC_ETM_CH_DISABLE45_V << SOC_ETM_CH_DISABLE45_S) +#define SOC_ETM_CH_DISABLE45_V 0x00000001U +#define SOC_ETM_CH_DISABLE45_S 13 +/** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE46 (BIT(14)) +#define SOC_ETM_CH_DISABLE46_M (SOC_ETM_CH_DISABLE46_V << SOC_ETM_CH_DISABLE46_S) +#define SOC_ETM_CH_DISABLE46_V 0x00000001U +#define SOC_ETM_CH_DISABLE46_S 14 +/** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE47 (BIT(15)) +#define SOC_ETM_CH_DISABLE47_M (SOC_ETM_CH_DISABLE47_V << SOC_ETM_CH_DISABLE47_S) +#define SOC_ETM_CH_DISABLE47_V 0x00000001U +#define SOC_ETM_CH_DISABLE47_S 15 +/** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE48 (BIT(16)) +#define SOC_ETM_CH_DISABLE48_M (SOC_ETM_CH_DISABLE48_V << SOC_ETM_CH_DISABLE48_S) +#define SOC_ETM_CH_DISABLE48_V 0x00000001U +#define SOC_ETM_CH_DISABLE48_S 16 +/** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE49 (BIT(17)) +#define SOC_ETM_CH_DISABLE49_M (SOC_ETM_CH_DISABLE49_V << SOC_ETM_CH_DISABLE49_S) +#define SOC_ETM_CH_DISABLE49_V 0x00000001U +#define SOC_ETM_CH_DISABLE49_S 17 + +/** SOC_ETM_CH0_EVT_ID_REG register + * Channel0 event id register + */ +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) +/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_evt_id + */ +#define SOC_ETM_CH0_EVT_ID 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) +#define SOC_ETM_CH0_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_S 0 + +/** SOC_ETM_CH0_TASK_ID_REG register + * Channel0 task id register + */ +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) +/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_task_id + */ +#define SOC_ETM_CH0_TASK_ID 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) +#define SOC_ETM_CH0_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_S 0 + +/** SOC_ETM_CH1_EVT_ID_REG register + * Channel1 event id register + */ +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) +/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_evt_id + */ +#define SOC_ETM_CH1_EVT_ID 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) +#define SOC_ETM_CH1_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_S 0 + +/** SOC_ETM_CH1_TASK_ID_REG register + * Channel1 task id register + */ +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) +/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_task_id + */ +#define SOC_ETM_CH1_TASK_ID 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) +#define SOC_ETM_CH1_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_S 0 + +/** SOC_ETM_CH2_EVT_ID_REG register + * Channel2 event id register + */ +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) +/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_evt_id + */ +#define SOC_ETM_CH2_EVT_ID 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) +#define SOC_ETM_CH2_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_S 0 + +/** SOC_ETM_CH2_TASK_ID_REG register + * Channel2 task id register + */ +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) +/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_task_id + */ +#define SOC_ETM_CH2_TASK_ID 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) +#define SOC_ETM_CH2_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_S 0 + +/** SOC_ETM_CH3_EVT_ID_REG register + * Channel3 event id register + */ +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) +/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_evt_id + */ +#define SOC_ETM_CH3_EVT_ID 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) +#define SOC_ETM_CH3_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_S 0 + +/** SOC_ETM_CH3_TASK_ID_REG register + * Channel3 task id register + */ +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) +/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_task_id + */ +#define SOC_ETM_CH3_TASK_ID 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) +#define SOC_ETM_CH3_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_S 0 + +/** SOC_ETM_CH4_EVT_ID_REG register + * Channel4 event id register + */ +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) +/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_evt_id + */ +#define SOC_ETM_CH4_EVT_ID 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) +#define SOC_ETM_CH4_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_S 0 + +/** SOC_ETM_CH4_TASK_ID_REG register + * Channel4 task id register + */ +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) +/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_task_id + */ +#define SOC_ETM_CH4_TASK_ID 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) +#define SOC_ETM_CH4_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_S 0 + +/** SOC_ETM_CH5_EVT_ID_REG register + * Channel5 event id register + */ +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) +/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_evt_id + */ +#define SOC_ETM_CH5_EVT_ID 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) +#define SOC_ETM_CH5_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_S 0 + +/** SOC_ETM_CH5_TASK_ID_REG register + * Channel5 task id register + */ +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) +/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_task_id + */ +#define SOC_ETM_CH5_TASK_ID 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) +#define SOC_ETM_CH5_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_S 0 + +/** SOC_ETM_CH6_EVT_ID_REG register + * Channel6 event id register + */ +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) +/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_evt_id + */ +#define SOC_ETM_CH6_EVT_ID 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) +#define SOC_ETM_CH6_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_S 0 + +/** SOC_ETM_CH6_TASK_ID_REG register + * Channel6 task id register + */ +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) +/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_task_id + */ +#define SOC_ETM_CH6_TASK_ID 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) +#define SOC_ETM_CH6_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_S 0 + +/** SOC_ETM_CH7_EVT_ID_REG register + * Channel7 event id register + */ +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) +/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_evt_id + */ +#define SOC_ETM_CH7_EVT_ID 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) +#define SOC_ETM_CH7_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_S 0 + +/** SOC_ETM_CH7_TASK_ID_REG register + * Channel7 task id register + */ +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) +/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_task_id + */ +#define SOC_ETM_CH7_TASK_ID 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) +#define SOC_ETM_CH7_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_S 0 + +/** SOC_ETM_CH8_EVT_ID_REG register + * Channel8 event id register + */ +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) +/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_evt_id + */ +#define SOC_ETM_CH8_EVT_ID 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) +#define SOC_ETM_CH8_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_S 0 + +/** SOC_ETM_CH8_TASK_ID_REG register + * Channel8 task id register + */ +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) +/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_task_id + */ +#define SOC_ETM_CH8_TASK_ID 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) +#define SOC_ETM_CH8_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_S 0 + +/** SOC_ETM_CH9_EVT_ID_REG register + * Channel9 event id register + */ +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) +/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_evt_id + */ +#define SOC_ETM_CH9_EVT_ID 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) +#define SOC_ETM_CH9_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_S 0 + +/** SOC_ETM_CH9_TASK_ID_REG register + * Channel9 task id register + */ +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) +/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_task_id + */ +#define SOC_ETM_CH9_TASK_ID 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) +#define SOC_ETM_CH9_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_S 0 + +/** SOC_ETM_CH10_EVT_ID_REG register + * Channel10 event id register + */ +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) +/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_evt_id + */ +#define SOC_ETM_CH10_EVT_ID 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) +#define SOC_ETM_CH10_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_S 0 + +/** SOC_ETM_CH10_TASK_ID_REG register + * Channel10 task id register + */ +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) +/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_task_id + */ +#define SOC_ETM_CH10_TASK_ID 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) +#define SOC_ETM_CH10_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_S 0 + +/** SOC_ETM_CH11_EVT_ID_REG register + * Channel11 event id register + */ +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) +/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_evt_id + */ +#define SOC_ETM_CH11_EVT_ID 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) +#define SOC_ETM_CH11_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_S 0 + +/** SOC_ETM_CH11_TASK_ID_REG register + * Channel11 task id register + */ +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) +/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_task_id + */ +#define SOC_ETM_CH11_TASK_ID 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) +#define SOC_ETM_CH11_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_S 0 + +/** SOC_ETM_CH12_EVT_ID_REG register + * Channel12 event id register + */ +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) +/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_evt_id + */ +#define SOC_ETM_CH12_EVT_ID 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) +#define SOC_ETM_CH12_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_S 0 + +/** SOC_ETM_CH12_TASK_ID_REG register + * Channel12 task id register + */ +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) +/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_task_id + */ +#define SOC_ETM_CH12_TASK_ID 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) +#define SOC_ETM_CH12_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_S 0 + +/** SOC_ETM_CH13_EVT_ID_REG register + * Channel13 event id register + */ +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) +/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_evt_id + */ +#define SOC_ETM_CH13_EVT_ID 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) +#define SOC_ETM_CH13_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_S 0 + +/** SOC_ETM_CH13_TASK_ID_REG register + * Channel13 task id register + */ +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) +/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_task_id + */ +#define SOC_ETM_CH13_TASK_ID 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) +#define SOC_ETM_CH13_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_S 0 + +/** SOC_ETM_CH14_EVT_ID_REG register + * Channel14 event id register + */ +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) +/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_evt_id + */ +#define SOC_ETM_CH14_EVT_ID 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) +#define SOC_ETM_CH14_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_S 0 + +/** SOC_ETM_CH14_TASK_ID_REG register + * Channel14 task id register + */ +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) +/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_task_id + */ +#define SOC_ETM_CH14_TASK_ID 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) +#define SOC_ETM_CH14_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_S 0 + +/** SOC_ETM_CH15_EVT_ID_REG register + * Channel15 event id register + */ +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) +/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_evt_id + */ +#define SOC_ETM_CH15_EVT_ID 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) +#define SOC_ETM_CH15_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_S 0 + +/** SOC_ETM_CH15_TASK_ID_REG register + * Channel15 task id register + */ +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) +/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_task_id + */ +#define SOC_ETM_CH15_TASK_ID 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) +#define SOC_ETM_CH15_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_S 0 + +/** SOC_ETM_CH16_EVT_ID_REG register + * Channel16 event id register + */ +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) +/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_evt_id + */ +#define SOC_ETM_CH16_EVT_ID 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) +#define SOC_ETM_CH16_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_S 0 + +/** SOC_ETM_CH16_TASK_ID_REG register + * Channel16 task id register + */ +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) +/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_task_id + */ +#define SOC_ETM_CH16_TASK_ID 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) +#define SOC_ETM_CH16_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_S 0 + +/** SOC_ETM_CH17_EVT_ID_REG register + * Channel17 event id register + */ +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) +/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_evt_id + */ +#define SOC_ETM_CH17_EVT_ID 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) +#define SOC_ETM_CH17_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_S 0 + +/** SOC_ETM_CH17_TASK_ID_REG register + * Channel17 task id register + */ +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) +/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_task_id + */ +#define SOC_ETM_CH17_TASK_ID 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) +#define SOC_ETM_CH17_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_S 0 + +/** SOC_ETM_CH18_EVT_ID_REG register + * Channel18 event id register + */ +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) +/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_evt_id + */ +#define SOC_ETM_CH18_EVT_ID 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) +#define SOC_ETM_CH18_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_S 0 + +/** SOC_ETM_CH18_TASK_ID_REG register + * Channel18 task id register + */ +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) +/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_task_id + */ +#define SOC_ETM_CH18_TASK_ID 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) +#define SOC_ETM_CH18_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_S 0 + +/** SOC_ETM_CH19_EVT_ID_REG register + * Channel19 event id register + */ +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) +/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_evt_id + */ +#define SOC_ETM_CH19_EVT_ID 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) +#define SOC_ETM_CH19_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_S 0 + +/** SOC_ETM_CH19_TASK_ID_REG register + * Channel19 task id register + */ +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) +/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_task_id + */ +#define SOC_ETM_CH19_TASK_ID 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) +#define SOC_ETM_CH19_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_S 0 + +/** SOC_ETM_CH20_EVT_ID_REG register + * Channel20 event id register + */ +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) +/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_evt_id + */ +#define SOC_ETM_CH20_EVT_ID 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) +#define SOC_ETM_CH20_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_S 0 + +/** SOC_ETM_CH20_TASK_ID_REG register + * Channel20 task id register + */ +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) +/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_task_id + */ +#define SOC_ETM_CH20_TASK_ID 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) +#define SOC_ETM_CH20_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_S 0 + +/** SOC_ETM_CH21_EVT_ID_REG register + * Channel21 event id register + */ +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) +/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_evt_id + */ +#define SOC_ETM_CH21_EVT_ID 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) +#define SOC_ETM_CH21_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_S 0 + +/** SOC_ETM_CH21_TASK_ID_REG register + * Channel21 task id register + */ +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) +/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_task_id + */ +#define SOC_ETM_CH21_TASK_ID 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) +#define SOC_ETM_CH21_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_S 0 + +/** SOC_ETM_CH22_EVT_ID_REG register + * Channel22 event id register + */ +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) +/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_evt_id + */ +#define SOC_ETM_CH22_EVT_ID 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) +#define SOC_ETM_CH22_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_S 0 + +/** SOC_ETM_CH22_TASK_ID_REG register + * Channel22 task id register + */ +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) +/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_task_id + */ +#define SOC_ETM_CH22_TASK_ID 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) +#define SOC_ETM_CH22_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_S 0 + +/** SOC_ETM_CH23_EVT_ID_REG register + * Channel23 event id register + */ +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) +/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_evt_id + */ +#define SOC_ETM_CH23_EVT_ID 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) +#define SOC_ETM_CH23_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_S 0 + +/** SOC_ETM_CH23_TASK_ID_REG register + * Channel23 task id register + */ +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) +/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_task_id + */ +#define SOC_ETM_CH23_TASK_ID 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) +#define SOC_ETM_CH23_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_S 0 + +/** SOC_ETM_CH24_EVT_ID_REG register + * Channel24 event id register + */ +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) +/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_evt_id + */ +#define SOC_ETM_CH24_EVT_ID 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) +#define SOC_ETM_CH24_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_S 0 + +/** SOC_ETM_CH24_TASK_ID_REG register + * Channel24 task id register + */ +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) +/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_task_id + */ +#define SOC_ETM_CH24_TASK_ID 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) +#define SOC_ETM_CH24_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_S 0 + +/** SOC_ETM_CH25_EVT_ID_REG register + * Channel25 event id register + */ +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) +/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_evt_id + */ +#define SOC_ETM_CH25_EVT_ID 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) +#define SOC_ETM_CH25_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_S 0 + +/** SOC_ETM_CH25_TASK_ID_REG register + * Channel25 task id register + */ +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) +/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_task_id + */ +#define SOC_ETM_CH25_TASK_ID 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) +#define SOC_ETM_CH25_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_S 0 + +/** SOC_ETM_CH26_EVT_ID_REG register + * Channel26 event id register + */ +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) +/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_evt_id + */ +#define SOC_ETM_CH26_EVT_ID 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) +#define SOC_ETM_CH26_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_S 0 + +/** SOC_ETM_CH26_TASK_ID_REG register + * Channel26 task id register + */ +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) +/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_task_id + */ +#define SOC_ETM_CH26_TASK_ID 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) +#define SOC_ETM_CH26_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_S 0 + +/** SOC_ETM_CH27_EVT_ID_REG register + * Channel27 event id register + */ +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) +/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_evt_id + */ +#define SOC_ETM_CH27_EVT_ID 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) +#define SOC_ETM_CH27_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_S 0 + +/** SOC_ETM_CH27_TASK_ID_REG register + * Channel27 task id register + */ +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) +/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_task_id + */ +#define SOC_ETM_CH27_TASK_ID 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) +#define SOC_ETM_CH27_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_S 0 + +/** SOC_ETM_CH28_EVT_ID_REG register + * Channel28 event id register + */ +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) +/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_evt_id + */ +#define SOC_ETM_CH28_EVT_ID 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) +#define SOC_ETM_CH28_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_S 0 + +/** SOC_ETM_CH28_TASK_ID_REG register + * Channel28 task id register + */ +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) +/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_task_id + */ +#define SOC_ETM_CH28_TASK_ID 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) +#define SOC_ETM_CH28_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_S 0 + +/** SOC_ETM_CH29_EVT_ID_REG register + * Channel29 event id register + */ +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) +/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_evt_id + */ +#define SOC_ETM_CH29_EVT_ID 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) +#define SOC_ETM_CH29_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_S 0 + +/** SOC_ETM_CH29_TASK_ID_REG register + * Channel29 task id register + */ +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) +/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_task_id + */ +#define SOC_ETM_CH29_TASK_ID 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) +#define SOC_ETM_CH29_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_S 0 + +/** SOC_ETM_CH30_EVT_ID_REG register + * Channel30 event id register + */ +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) +/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_evt_id + */ +#define SOC_ETM_CH30_EVT_ID 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) +#define SOC_ETM_CH30_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_S 0 + +/** SOC_ETM_CH30_TASK_ID_REG register + * Channel30 task id register + */ +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) +/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_task_id + */ +#define SOC_ETM_CH30_TASK_ID 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) +#define SOC_ETM_CH30_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_S 0 + +/** SOC_ETM_CH31_EVT_ID_REG register + * Channel31 event id register + */ +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) +/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_evt_id + */ +#define SOC_ETM_CH31_EVT_ID 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) +#define SOC_ETM_CH31_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_S 0 + +/** SOC_ETM_CH31_TASK_ID_REG register + * Channel31 task id register + */ +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) +/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_task_id + */ +#define SOC_ETM_CH31_TASK_ID 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) +#define SOC_ETM_CH31_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_S 0 + +/** SOC_ETM_CH32_EVT_ID_REG register + * Channel32 event id register + */ +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) +/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_evt_id + */ +#define SOC_ETM_CH32_EVT_ID 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) +#define SOC_ETM_CH32_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_S 0 + +/** SOC_ETM_CH32_TASK_ID_REG register + * Channel32 task id register + */ +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) +/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_task_id + */ +#define SOC_ETM_CH32_TASK_ID 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) +#define SOC_ETM_CH32_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_S 0 + +/** SOC_ETM_CH33_EVT_ID_REG register + * Channel33 event id register + */ +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) +/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_evt_id + */ +#define SOC_ETM_CH33_EVT_ID 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) +#define SOC_ETM_CH33_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_S 0 + +/** SOC_ETM_CH33_TASK_ID_REG register + * Channel33 task id register + */ +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) +/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_task_id + */ +#define SOC_ETM_CH33_TASK_ID 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) +#define SOC_ETM_CH33_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_S 0 + +/** SOC_ETM_CH34_EVT_ID_REG register + * Channel34 event id register + */ +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) +/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_evt_id + */ +#define SOC_ETM_CH34_EVT_ID 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) +#define SOC_ETM_CH34_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_S 0 + +/** SOC_ETM_CH34_TASK_ID_REG register + * Channel34 task id register + */ +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) +/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_task_id + */ +#define SOC_ETM_CH34_TASK_ID 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) +#define SOC_ETM_CH34_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_S 0 + +/** SOC_ETM_CH35_EVT_ID_REG register + * Channel35 event id register + */ +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) +/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_evt_id + */ +#define SOC_ETM_CH35_EVT_ID 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) +#define SOC_ETM_CH35_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_S 0 + +/** SOC_ETM_CH35_TASK_ID_REG register + * Channel35 task id register + */ +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) +/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_task_id + */ +#define SOC_ETM_CH35_TASK_ID 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) +#define SOC_ETM_CH35_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_S 0 + +/** SOC_ETM_CH36_EVT_ID_REG register + * Channel36 event id register + */ +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) +/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_evt_id + */ +#define SOC_ETM_CH36_EVT_ID 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) +#define SOC_ETM_CH36_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_S 0 + +/** SOC_ETM_CH36_TASK_ID_REG register + * Channel36 task id register + */ +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) +/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_task_id + */ +#define SOC_ETM_CH36_TASK_ID 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) +#define SOC_ETM_CH36_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_S 0 + +/** SOC_ETM_CH37_EVT_ID_REG register + * Channel37 event id register + */ +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) +/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_evt_id + */ +#define SOC_ETM_CH37_EVT_ID 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) +#define SOC_ETM_CH37_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_S 0 + +/** SOC_ETM_CH37_TASK_ID_REG register + * Channel37 task id register + */ +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) +/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_task_id + */ +#define SOC_ETM_CH37_TASK_ID 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) +#define SOC_ETM_CH37_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_S 0 + +/** SOC_ETM_CH38_EVT_ID_REG register + * Channel38 event id register + */ +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) +/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_evt_id + */ +#define SOC_ETM_CH38_EVT_ID 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) +#define SOC_ETM_CH38_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_S 0 + +/** SOC_ETM_CH38_TASK_ID_REG register + * Channel38 task id register + */ +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) +/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_task_id + */ +#define SOC_ETM_CH38_TASK_ID 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) +#define SOC_ETM_CH38_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_S 0 + +/** SOC_ETM_CH39_EVT_ID_REG register + * Channel39 event id register + */ +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) +/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_evt_id + */ +#define SOC_ETM_CH39_EVT_ID 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) +#define SOC_ETM_CH39_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_S 0 + +/** SOC_ETM_CH39_TASK_ID_REG register + * Channel39 task id register + */ +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) +/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_task_id + */ +#define SOC_ETM_CH39_TASK_ID 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) +#define SOC_ETM_CH39_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_S 0 + +/** SOC_ETM_CH40_EVT_ID_REG register + * Channel40 event id register + */ +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) +/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_evt_id + */ +#define SOC_ETM_CH40_EVT_ID 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) +#define SOC_ETM_CH40_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_S 0 + +/** SOC_ETM_CH40_TASK_ID_REG register + * Channel40 task id register + */ +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) +/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_task_id + */ +#define SOC_ETM_CH40_TASK_ID 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) +#define SOC_ETM_CH40_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_S 0 + +/** SOC_ETM_CH41_EVT_ID_REG register + * Channel41 event id register + */ +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) +/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_evt_id + */ +#define SOC_ETM_CH41_EVT_ID 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) +#define SOC_ETM_CH41_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_S 0 + +/** SOC_ETM_CH41_TASK_ID_REG register + * Channel41 task id register + */ +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) +/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_task_id + */ +#define SOC_ETM_CH41_TASK_ID 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) +#define SOC_ETM_CH41_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_S 0 + +/** SOC_ETM_CH42_EVT_ID_REG register + * Channel42 event id register + */ +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) +/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_evt_id + */ +#define SOC_ETM_CH42_EVT_ID 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) +#define SOC_ETM_CH42_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_S 0 + +/** SOC_ETM_CH42_TASK_ID_REG register + * Channel42 task id register + */ +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) +/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_task_id + */ +#define SOC_ETM_CH42_TASK_ID 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) +#define SOC_ETM_CH42_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_S 0 + +/** SOC_ETM_CH43_EVT_ID_REG register + * Channel43 event id register + */ +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) +/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_evt_id + */ +#define SOC_ETM_CH43_EVT_ID 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) +#define SOC_ETM_CH43_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_S 0 + +/** SOC_ETM_CH43_TASK_ID_REG register + * Channel43 task id register + */ +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) +/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_task_id + */ +#define SOC_ETM_CH43_TASK_ID 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) +#define SOC_ETM_CH43_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_S 0 + +/** SOC_ETM_CH44_EVT_ID_REG register + * Channel44 event id register + */ +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) +/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_evt_id + */ +#define SOC_ETM_CH44_EVT_ID 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) +#define SOC_ETM_CH44_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_S 0 + +/** SOC_ETM_CH44_TASK_ID_REG register + * Channel44 task id register + */ +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) +/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_task_id + */ +#define SOC_ETM_CH44_TASK_ID 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) +#define SOC_ETM_CH44_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_S 0 + +/** SOC_ETM_CH45_EVT_ID_REG register + * Channel45 event id register + */ +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) +/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_evt_id + */ +#define SOC_ETM_CH45_EVT_ID 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) +#define SOC_ETM_CH45_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_S 0 + +/** SOC_ETM_CH45_TASK_ID_REG register + * Channel45 task id register + */ +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) +/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_task_id + */ +#define SOC_ETM_CH45_TASK_ID 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) +#define SOC_ETM_CH45_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_S 0 + +/** SOC_ETM_CH46_EVT_ID_REG register + * Channel46 event id register + */ +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) +/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_evt_id + */ +#define SOC_ETM_CH46_EVT_ID 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) +#define SOC_ETM_CH46_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_S 0 + +/** SOC_ETM_CH46_TASK_ID_REG register + * Channel46 task id register + */ +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) +/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_task_id + */ +#define SOC_ETM_CH46_TASK_ID 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) +#define SOC_ETM_CH46_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_S 0 + +/** SOC_ETM_CH47_EVT_ID_REG register + * Channel47 event id register + */ +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) +/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_evt_id + */ +#define SOC_ETM_CH47_EVT_ID 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) +#define SOC_ETM_CH47_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_S 0 + +/** SOC_ETM_CH47_TASK_ID_REG register + * Channel47 task id register + */ +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) +/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_task_id + */ +#define SOC_ETM_CH47_TASK_ID 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) +#define SOC_ETM_CH47_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_S 0 + +/** SOC_ETM_CH48_EVT_ID_REG register + * Channel48 event id register + */ +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) +/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_evt_id + */ +#define SOC_ETM_CH48_EVT_ID 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) +#define SOC_ETM_CH48_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_S 0 + +/** SOC_ETM_CH48_TASK_ID_REG register + * Channel48 task id register + */ +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) +/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_task_id + */ +#define SOC_ETM_CH48_TASK_ID 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) +#define SOC_ETM_CH48_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_S 0 + +/** SOC_ETM_CH49_EVT_ID_REG register + * Channel49 event id register + */ +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) +/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_evt_id + */ +#define SOC_ETM_CH49_EVT_ID 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) +#define SOC_ETM_CH49_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_S 0 + +/** SOC_ETM_CH49_TASK_ID_REG register + * Channel49 task id register + */ +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) +/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_task_id + */ +#define SOC_ETM_CH49_TASK_ID 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) +#define SOC_ETM_CH49_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_S 0 + +/** SOC_ETM_EVT_ST0_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_S 25 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST (BIT(26)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S 26 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST (BIT(27)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S 31 + +/** SOC_ETM_EVT_ST0_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_S 25 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S 26 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST1_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST (BIT(0)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S 0 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST (BIT(1)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S 1 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST (BIT(2)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S 2 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST (BIT(3)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S 5 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST (BIT(6)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S 6 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST (BIT(7)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S 7 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST (BIT(8)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S 8 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST (BIT(9)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S 9 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST (BIT(10)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S 10 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST (BIT(11)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S 11 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S 12 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S 13 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST (BIT(14)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S 14 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST (BIT(15)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S 15 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST (BIT(16)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S 16 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST (BIT(17)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S 17 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST (BIT(18)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S 18 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST (BIT(19)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S 19 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST (BIT(20)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S 20 +/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S 21 +/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S 22 +/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S 23 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S 24 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST (BIT(25)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S 25 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST (BIT(26)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S 26 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S 27 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S 28 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S 29 +/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S 30 +/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST (BIT(31)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S 31 + +/** SOC_ETM_EVT_ST1_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S 0 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S 1 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S 2 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S 5 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S 6 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S 7 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S 8 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S 9 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S 10 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S 11 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S 12 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S 13 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(14)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S 14 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(15)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S 15 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(16)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S 16 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(17)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S 17 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR (BIT(18)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S 18 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR (BIT(19)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S 19 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR (BIT(20)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S 24 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S 25 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR (BIT(26)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S 26 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S 27 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S 28 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S 29 +/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S 30 +/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR (BIT(31)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST2_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) +/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST (BIT(0)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S 0 +/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST (BIT(1)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S 1 +/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST (BIT(2)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S 2 +/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST (BIT(3)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S 3 +/** SOC_ETM_MCPWM0_EVT_F0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F0_ST (BIT(4)) +#define SOC_ETM_MCPWM0_EVT_F0_ST_M (SOC_ETM_MCPWM0_EVT_F0_ST_V << SOC_ETM_MCPWM0_EVT_F0_ST_S) +#define SOC_ETM_MCPWM0_EVT_F0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_ST_S 4 +/** SOC_ETM_MCPWM0_EVT_F1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F1_ST (BIT(5)) +#define SOC_ETM_MCPWM0_EVT_F1_ST_M (SOC_ETM_MCPWM0_EVT_F1_ST_V << SOC_ETM_MCPWM0_EVT_F1_ST_S) +#define SOC_ETM_MCPWM0_EVT_F1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_ST_S 5 +/** SOC_ETM_MCPWM0_EVT_F2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F2_ST (BIT(6)) +#define SOC_ETM_MCPWM0_EVT_F2_ST_M (SOC_ETM_MCPWM0_EVT_F2_ST_V << SOC_ETM_MCPWM0_EVT_F2_ST_S) +#define SOC_ETM_MCPWM0_EVT_F2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_ST_S 6 +/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST (BIT(7)) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S 7 +/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST (BIT(8)) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S 8 +/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST (BIT(9)) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S 9 +/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST (BIT(10)) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S 10 +/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST (BIT(11)) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S 11 +/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST (BIT(12)) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S 12 +/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST (BIT(13)) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S 13 +/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST (BIT(14)) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S 14 +/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST (BIT(15)) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S 15 +/** SOC_ETM_MCPWM0_EVT_CAP0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP0_ST (BIT(16)) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_M (SOC_ETM_MCPWM0_EVT_CAP0_ST_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_S 16 +/** SOC_ETM_MCPWM0_EVT_CAP1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP1_ST (BIT(17)) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_M (SOC_ETM_MCPWM0_EVT_CAP1_ST_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_S 17 +/** SOC_ETM_MCPWM0_EVT_CAP2_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP2_ST (BIT(18)) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_M (SOC_ETM_MCPWM0_EVT_CAP2_ST_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_S 18 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST (BIT(19)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S 19 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST (BIT(20)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S 20 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S 21 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S 22 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S 23 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S 24 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST (BIT(25)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S 25 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST (BIT(26)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S 26 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST (BIT(27)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S 27 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST (BIT(28)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S 28 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST (BIT(29)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S 29 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST (BIT(30)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S 30 +/** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST (BIT(31)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_M (SOC_ETM_ADC_EVT_STOPPED0_ST_V << SOC_ETM_ADC_EVT_STOPPED0_ST_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_S 31 + +/** SOC_ETM_EVT_ST2_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) +/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR (BIT(0)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S 0 +/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR (BIT(1)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S 1 +/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR (BIT(2)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S 2 +/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR (BIT(3)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S 3 +/** SOC_ETM_MCPWM0_EVT_F0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S 4 +/** SOC_ETM_MCPWM0_EVT_F1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S 5 +/** SOC_ETM_MCPWM0_EVT_F2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S 6 +/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S 7 +/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S 8 +/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S 9 +/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S 10 +/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S 11 +/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S 12 +/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S 13 +/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S 14 +/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S 15 +/** SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S 16 +/** SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S 17 +/** SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S 18 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S 19 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S 24 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR (BIT(25)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S 25 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR (BIT(26)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S 26 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR (BIT(27)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S 27 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR (BIT(28)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S 28 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR (BIT(29)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S 29 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR (BIT(30)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S 30 +/** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR (BIT(31)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_M (SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V << SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST3_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) +/** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST (BIT(0)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_M (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_S 0 +/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_M (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_S 1 +/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_M (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_S 2 +/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST (BIT(3)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_M (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_S 3 +/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST (BIT(4)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_M (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_S 4 +/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_M (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_S 5 +/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_M (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_S 6 +/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST (BIT(7)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_M (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_S 7 +/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST (BIT(8)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_M (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_S 8 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GDMA_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST (BIT(9)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_S 9 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST (BIT(10)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_S 10 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GDMA_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST (BIT(11)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_S 11 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST (BIT(12)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_S 12 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST (BIT(13)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_S 13 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST (BIT(14)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_S 14 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST (BIT(15)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_S 15 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST (BIT(16)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_S 16 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(17)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_S 17 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST (BIT(18)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_S 18 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST (BIT(19)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_S 19 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST (BIT(20)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_S 20 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GDMA_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST (BIT(21)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_S 21 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GDMA_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST (BIT(22)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_S 22 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GDMA_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST (BIT(23)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_S 23 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST (BIT(24)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_S 24 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GDMA_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST (BIT(25)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_S 25 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GDMA_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST (BIT(26)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_S 26 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST (BIT(27)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_S 27 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST (BIT(28)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_S 28 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(29)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_S 29 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST (BIT(30)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_S 30 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST (BIT(31)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_S 31 + +/** SOC_ETM_EVT_ST3_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) +/** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR (BIT(0)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S 0 +/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S 1 +/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S 2 +/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR (BIT(3)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S 3 +/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR (BIT(4)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S 4 +/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S 5 +/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S 6 +/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR (BIT(7)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S 7 +/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR (BIT(8)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S 8 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR (BIT(9)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_S 9 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR (BIT(10)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_S 10 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR (BIT(11)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_S 11 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_S 12 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_S 13 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_S 14 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(15)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 15 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(16)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 16 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(17)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 17 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(18)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 18 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(19)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 19 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(20)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 20 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR (BIT(21)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_S 21 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR (BIT(22)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_S 22 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR (BIT(23)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_S 23 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR (BIT(24)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_S 24 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR (BIT(25)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_S 25 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR (BIT(26)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_S 26 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(27)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 27 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(28)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 28 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(29)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 29 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 30 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST4_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8) +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(0)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_S 0 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST (BIT(1)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_S 1 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST (BIT(2)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_S 2 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST (BIT(3)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_S 3 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST (BIT(4)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S 4 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST (BIT(5)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_S 5 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST (BIT(6)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_S 6 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST (BIT(7)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S 7 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST (BIT(8)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S 8 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST (BIT(9)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S 9 +/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_HALT_ST (BIT(10)) +#define SOC_ETM_ULP_EVT_HALT_ST_M (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S) +#define SOC_ETM_ULP_EVT_HALT_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_S 10 +/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST (BIT(11)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_M (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_S 11 +/** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_TICK_ST (BIT(12)) +#define SOC_ETM_RTC_EVT_TICK_ST_M (SOC_ETM_RTC_EVT_TICK_ST_V << SOC_ETM_RTC_EVT_TICK_ST_S) +#define SOC_ETM_RTC_EVT_TICK_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_S 12 +/** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_OVF_ST (BIT(13)) +#define SOC_ETM_RTC_EVT_OVF_ST_M (SOC_ETM_RTC_EVT_OVF_ST_V << SOC_ETM_RTC_EVT_OVF_ST_S) +#define SOC_ETM_RTC_EVT_OVF_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_S 13 +/** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_CMP_ST (BIT(14)) +#define SOC_ETM_RTC_EVT_CMP_ST_M (SOC_ETM_RTC_EVT_CMP_ST_V << SOC_ETM_RTC_EVT_CMP_ST_S) +#define SOC_ETM_RTC_EVT_CMP_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_S 14 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST (BIT(15)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S 15 + +/** SOC_ETM_EVT_ST4_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 0 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 1 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(2)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 2 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(3)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 3 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR (BIT(4)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S 4 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR (BIT(5)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S 5 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR (BIT(6)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S 6 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(7)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S 7 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR (BIT(8)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S 8 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR (BIT(9)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S 9 +/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_HALT_ST_CLR (BIT(10)) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S 10 +/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR (BIT(11)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S 11 +/** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_TICK_ST_CLR (BIT(12)) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_M (SOC_ETM_RTC_EVT_TICK_ST_CLR_V << SOC_ETM_RTC_EVT_TICK_ST_CLR_S) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_S 12 +/** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_OVF_ST_CLR (BIT(13)) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_M (SOC_ETM_RTC_EVT_OVF_ST_CLR_V << SOC_ETM_RTC_EVT_OVF_ST_CLR_S) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_S 13 +/** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_CMP_ST_CLR (BIT(14)) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_M (SOC_ETM_RTC_EVT_CMP_ST_CLR_V << SOC_ETM_RTC_EVT_CMP_ST_CLR_S) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_S 14 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR (BIT(15)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S 15 + +/** SOC_ETM_TASK_ST0_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1d0) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S 31 + +/** SOC_ETM_TASK_ST0_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST1_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1d8) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S 1 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S 2 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S 3 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S 4 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S 5 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S 6 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S 11 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S 12 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S 13 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S 14 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S 17 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST (BIT(18)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S 18 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST (BIT(19)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S 19 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST (BIT(20)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S 20 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST (BIT(21)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S 21 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST (BIT(22)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S 22 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST (BIT(23)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S 27 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S 28 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S 29 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S 30 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S 31 + +/** SOC_ETM_TASK_ST1_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S 17 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR (BIT(18)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S 18 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR (BIT(19)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S 19 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR (BIT(20)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S 20 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR (BIT(21)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S 21 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR (BIT(22)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S 22 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR (BIT(23)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST2_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1e0) +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S 0 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S 1 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S 2 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S 15 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST (BIT(16)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S 16 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST (BIT(17)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S 17 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST (BIT(18)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S 18 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST (BIT(19)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S 19 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST (BIT(20)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S 20 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST (BIT(21)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S 21 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST (BIT(22)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S 22 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST (BIT(23)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S 23 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST (BIT(24)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S 24 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST (BIT(25)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S 25 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST (BIT(26)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S 26 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST (BIT(27)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S 27 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST (BIT(28)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S 28 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST (BIT(29)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S 29 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST (BIT(30)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S 30 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST (BIT(31)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S 31 + +/** SOC_ETM_TASK_ST2_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S 15 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR (BIT(16)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S 16 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR (BIT(17)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S 17 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(18)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S 18 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(19)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 19 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(20)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S 20 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR (BIT(21)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S 21 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR (BIT(22)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S 22 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(23)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S 23 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(24)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 24 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(25)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S 25 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR (BIT(26)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S 26 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR (BIT(27)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S 27 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(28)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S 28 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(29)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 29 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(30)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S 30 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR (BIT(31)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST3_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1e8) +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST (BIT(0)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S 0 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST (BIT(1)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S 1 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST (BIT(2)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S 2 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST (BIT(3)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S 3 +/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST (BIT(4)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S 4 +/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST (BIT(5)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S 5 +/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST (BIT(6)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S 6 +/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST (BIT(7)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S 7 +/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST (BIT(8)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S 8 +/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST (BIT(9)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S 9 +/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST (BIT(10)) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_M (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S 10 +/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST (BIT(11)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S 11 +/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST (BIT(12)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S 12 +/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST (BIT(13)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S 13 +/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST (BIT(14)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S 14 +/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST (BIT(15)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S 15 +/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST (BIT(16)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S 16 +/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST (BIT(17)) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S 17 +/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST (BIT(18)) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S 18 +/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST (BIT(19)) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S 19 +/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST (BIT(20)) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S 20 +/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST (BIT(21)) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S 21 +/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST (BIT(22)) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S 22 +/** SOC_ETM_MCPWM0_TASK_CAP0_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP0_ST (BIT(23)) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_M (SOC_ETM_MCPWM0_TASK_CAP0_ST_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_S 23 +/** SOC_ETM_MCPWM0_TASK_CAP1_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP1_ST (BIT(24)) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_M (SOC_ETM_MCPWM0_TASK_CAP1_ST_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_S 24 +/** SOC_ETM_MCPWM0_TASK_CAP2_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP2_ST (BIT(25)) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_M (SOC_ETM_MCPWM0_TASK_CAP2_ST_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_S 25 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST (BIT(26)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 26 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(27)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 27 +/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_START0_ST (BIT(28)) +#define SOC_ETM_ADC_TASK_START0_ST_M (SOC_ETM_ADC_TASK_START0_ST_V << SOC_ETM_ADC_TASK_START0_ST_S) +#define SOC_ETM_ADC_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_S 28 +/** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_STOP0_ST (BIT(29)) +#define SOC_ETM_ADC_TASK_STOP0_ST_M (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_S 29 +/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START0_ST (BIT(30)) +#define SOC_ETM_REGDMA_TASK_START0_ST_M (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_S 30 +/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START1_ST (BIT(31)) +#define SOC_ETM_REGDMA_TASK_START1_ST_M (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_S 31 + +/** SOC_ETM_TASK_ST3_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR (BIT(0)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S 0 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(1)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S 1 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(2)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 2 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(3)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S 3 +/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S 4 +/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S 5 +/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S 6 +/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S 7 +/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S 8 +/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S 9 +/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S 10 +/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S 11 +/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S 12 +/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S 13 +/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S 14 +/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S 15 +/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S 16 +/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S 17 +/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S 18 +/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S 19 +/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S 24 +/** SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S 25 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR (BIT(26)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 26 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(27)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 27 +/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_START0_ST_CLR (BIT(28)) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_M (SOC_ETM_ADC_TASK_START0_ST_CLR_V << SOC_ETM_ADC_TASK_START0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_CLR_S 28 +/** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR (BIT(29)) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S 29 +/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR (BIT(30)) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S 30 +/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR (BIT(31)) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST4_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1f0) +/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START2_ST (BIT(0)) +#define SOC_ETM_REGDMA_TASK_START2_ST_M (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_S 0 +/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START3_ST (BIT(1)) +#define SOC_ETM_REGDMA_TASK_START3_ST_M (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_S 1 +/** SOC_ETM_GDMA_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST (BIT(2)) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_M (SOC_ETM_GDMA_TASK_IN_START_CH0_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH0_ST_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_S 2 +/** SOC_ETM_GDMA_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST (BIT(3)) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_M (SOC_ETM_GDMA_TASK_IN_START_CH1_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH1_ST_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_S 3 +/** SOC_ETM_GDMA_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST (BIT(4)) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_M (SOC_ETM_GDMA_TASK_IN_START_CH2_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_S 4 +/** SOC_ETM_GDMA_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GDMA_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST (BIT(5)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_M (SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_S 5 +/** SOC_ETM_GDMA_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GDMA_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST (BIT(6)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_M (SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_S 6 +/** SOC_ETM_GDMA_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST (BIT(7)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_M (SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_S 7 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST (BIT(8)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S 8 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST (BIT(9)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S 9 +/** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST (BIT(10)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_M (SOC_ETM_I2S0_TASK_START_RX_ST_V << SOC_ETM_I2S0_TASK_START_RX_ST_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_S 10 +/** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST (BIT(11)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_M (SOC_ETM_I2S0_TASK_START_TX_ST_V << SOC_ETM_I2S0_TASK_START_TX_ST_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_S 11 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST (BIT(12)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_S 12 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST (BIT(13)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_S 13 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST (BIT(14)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S 14 +/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST (BIT(15)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_M (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_S 15 +/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_START_ST (BIT(16)) +#define SOC_ETM_RTC_TASK_START_ST_M (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S) +#define SOC_ETM_RTC_TASK_START_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_S 16 +/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_STOP_ST (BIT(17)) +#define SOC_ETM_RTC_TASK_STOP_ST_M (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S) +#define SOC_ETM_RTC_TASK_STOP_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_S 17 +/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_CLR_ST (BIT(18)) +#define SOC_ETM_RTC_TASK_CLR_ST_M (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S) +#define SOC_ETM_RTC_TASK_CLR_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_S 18 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST (BIT(19)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S 19 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST (BIT(20)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S 20 + +/** SOC_ETM_TASK_ST4_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4) +/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR (BIT(0)) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S 0 +/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S 1 +/** SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR (BIT(2)) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_M (SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_S 2 +/** SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR (BIT(3)) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_S 3 +/** SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR (BIT(4)) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_S 4 +/** SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR (BIT(5)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_M (SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_S 5 +/** SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR (BIT(6)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_S 6 +/** SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR (BIT(7)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_S 7 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR (BIT(8)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S 8 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR (BIT(9)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S 9 +/** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR (BIT(10)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S 10 +/** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR (BIT(11)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S 11 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR (BIT(12)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S 12 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR (BIT(13)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S 13 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR (BIT(14)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S 14 +/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR (BIT(15)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S 15 +/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_START_ST_CLR (BIT(16)) +#define SOC_ETM_RTC_TASK_START_ST_CLR_M (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S) +#define SOC_ETM_RTC_TASK_START_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_CLR_S 16 +/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_STOP_ST_CLR (BIT(17)) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S 17 +/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_CLR_ST_CLR (BIT(18)) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S 18 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR (BIT(19)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S 19 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR (BIT(20)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S 20 + +/** SOC_ETM_CLK_EN_REG register + * ETM clock enable register + */ +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1f8) +/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define SOC_ETM_CLK_EN (BIT(0)) +#define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) +#define SOC_ETM_CLK_EN_V 0x00000001U +#define SOC_ETM_CLK_EN_S 0 + +/** SOC_ETM_DATE_REG register + * ETM date register + */ +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1fc) +/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36716929; + * Configures the version. + */ +#define SOC_ETM_DATE 0x0FFFFFFFU +#define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) +#define SOC_ETM_DATE_V 0x0FFFFFFFU +#define SOC_ETM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/soc_etm_struct.h b/components/soc/esp32c5/include/soc/soc_etm_struct.h new file mode 100644 index 00000000000..f575255af7b --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_etm_struct.h @@ -0,0 +1,3649 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status register */ +/** Type of ch_ena_ad0 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_enabled0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled0:1; + /** ch_enabled1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled1:1; + /** ch_enabled2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled2:1; + /** ch_enabled3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled3:1; + /** ch_enabled4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled4:1; + /** ch_enabled5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled5:1; + /** ch_enabled6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled6:1; + /** ch_enabled7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled7:1; + /** ch_enabled8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled8:1; + /** ch_enabled9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled9:1; + /** ch_enabled10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled10:1; + /** ch_enabled11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled11:1; + /** ch_enabled12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled12:1; + /** ch_enabled13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled13:1; + /** ch_enabled14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled14:1; + /** ch_enabled15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled15:1; + /** ch_enabled16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled16:1; + /** ch_enabled17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled17:1; + /** ch_enabled18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled18:1; + /** ch_enabled19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled19:1; + /** ch_enabled20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled20:1; + /** ch_enabled21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled21:1; + /** ch_enabled22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled22:1; + /** ch_enabled23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled23:1; + /** ch_enabled24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled24:1; + /** ch_enabled25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled25:1; + /** ch_enabled26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled26:1; + /** ch_enabled27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled27:1; + /** ch_enabled28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled28:1; + /** ch_enabled29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled29:1; + /** ch_enabled30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled30:1; + /** ch_enabled31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_reg_t; + +/** Type of ch_ena_ad1 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_enabled32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled32:1; + /** ch_enabled33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled33:1; + /** ch_enabled34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled34:1; + /** ch_enabled35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled35:1; + /** ch_enabled36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled36:1; + /** ch_enabled37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled37:1; + /** ch_enabled38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled38:1; + /** ch_enabled39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled39:1; + /** ch_enabled40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled40:1; + /** ch_enabled41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled41:1; + /** ch_enabled42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled42:1; + /** ch_enabled43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled43:1; + /** ch_enabled44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled44:1; + /** ch_enabled45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled45:1; + /** ch_enabled46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled46:1; + /** ch_enabled47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled47:1; + /** ch_enabled48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled48:1; + /** ch_enabled49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_reg_t; + +/** Type of evt_st0 register + * Events trigger status register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_rise_edge_st:1; + /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_rise_edge_st:1; + /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_rise_edge_st:1; + /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_rise_edge_st:1; + /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_rise_edge_st:1; + /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_rise_edge_st:1; + /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_rise_edge_st:1; + /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_rise_edge_st:1; + /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_fall_edge_st:1; + /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_fall_edge_st:1; + /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_fall_edge_st:1; + /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_fall_edge_st:1; + /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_fall_edge_st:1; + /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_fall_edge_st:1; + /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_fall_edge_st:1; + /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_fall_edge_st:1; + /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_any_edge_st:1; + /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_any_edge_st:1; + /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_any_edge_st:1; + /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_any_edge_st:1; + /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_any_edge_st:1; + /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_any_edge_st:1; + /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_any_edge_st:1; + /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_any_edge_st:1; + /** gpio_evt_zero_det_pos_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_pos_st:1; + /** gpio_evt_zero_det_neg_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_neg_st:1; + /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch0_st:1; + /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch1_st:1; + /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch2_st:1; + /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch3_st:1; + /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch4_st:1; + /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch5_st:1; + }; + uint32_t val; +} soc_etm_evt_st0_reg_t; + +/** Type of evt_st1 register + * Events trigger status register + */ +typedef union { + struct { + /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1; + /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1; + /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1; + /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1; + /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1; + /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1; + /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer0_st:1; + /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer1_st:1; + /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer2_st:1; + /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer3_st:1; + /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer0_cmp_st:1; + /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer1_cmp_st:1; + /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer2_cmp_st:1; + /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer3_cmp_st:1; + /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer0_st:1; + /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer1_st:1; + /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer0_st:1; + /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer1_st:1; + /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp0_st:1; + /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp1_st:1; + /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp2_st:1; + /** mcpwm0_evt_timer0_stop_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_stop_st:1; + /** mcpwm0_evt_timer1_stop_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_stop_st:1; + /** mcpwm0_evt_timer2_stop_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_stop_st:1; + /** mcpwm0_evt_timer0_tez_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_tez_st:1; + /** mcpwm0_evt_timer1_tez_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_tez_st:1; + /** mcpwm0_evt_timer2_tez_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_tez_st:1; + /** mcpwm0_evt_timer0_tep_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_tep_st:1; + /** mcpwm0_evt_timer1_tep_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_tep_st:1; + /** mcpwm0_evt_timer2_tep_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_tep_st:1; + /** mcpwm0_evt_op0_tea_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tea_st:1; + /** mcpwm0_evt_op1_tea_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tea_st:1; + }; + uint32_t val; +} soc_etm_evt_st1_reg_t; + +/** Type of evt_st2 register + * Events trigger status register + */ +typedef union { + struct { + /** mcpwm0_evt_op2_tea_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tea_st:1; + /** mcpwm0_evt_op0_teb_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_teb_st:1; + /** mcpwm0_evt_op1_teb_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_teb_st:1; + /** mcpwm0_evt_op2_teb_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_teb_st:1; + /** mcpwm0_evt_f0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f0_st:1; + /** mcpwm0_evt_f1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f1_st:1; + /** mcpwm0_evt_f2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f2_st:1; + /** mcpwm0_evt_f0_clr_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f0_clr_st:1; + /** mcpwm0_evt_f1_clr_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f1_clr_st:1; + /** mcpwm0_evt_f2_clr_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f2_clr_st:1; + /** mcpwm0_evt_tz0_cbc_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz0_cbc_st:1; + /** mcpwm0_evt_tz1_cbc_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz1_cbc_st:1; + /** mcpwm0_evt_tz2_cbc_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz2_cbc_st:1; + /** mcpwm0_evt_tz0_ost_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz0_ost_st:1; + /** mcpwm0_evt_tz1_ost_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz1_ost_st:1; + /** mcpwm0_evt_tz2_ost_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz2_ost_st:1; + /** mcpwm0_evt_cap0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap0_st:1; + /** mcpwm0_evt_cap1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap1_st:1; + /** mcpwm0_evt_cap2_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap2_st:1; + /** mcpwm0_evt_op0_tee1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tee1_st:1; + /** mcpwm0_evt_op1_tee1_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tee1_st:1; + /** mcpwm0_evt_op2_tee1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tee1_st:1; + /** mcpwm0_evt_op0_tee2_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tee2_st:1; + /** mcpwm0_evt_op1_tee2_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tee2_st:1; + /** mcpwm0_evt_op2_tee2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tee2_st:1; + /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_conv_cmplt0_st:1; + /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh0_st:1; + /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh1_st:1; + /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh0_st:1; + /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh1_st:1; + /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_result_done0_st:1; + /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_stopped0_st:1; + }; + uint32_t val; +} soc_etm_evt_st2_reg_t; + +/** Type of evt_st3 register + * Events trigger status register + */ +typedef union { + struct { + /** adc_evt_started0_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_started0_st:1; + /** regdma_evt_done0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done0_st:1; + /** regdma_evt_done1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done1_st:1; + /** regdma_evt_done2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done2_st:1; + /** regdma_evt_done3_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done3_st:1; + /** regdma_evt_err0_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err0_st:1; + /** regdma_evt_err1_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err1_st:1; + /** regdma_evt_err2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err2_st:1; + /** regdma_evt_err3_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err3_st:1; + /** gdma_evt_in_done_ch0_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GDMA_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_done_ch0_st:1; + /** gdma_evt_in_done_ch1_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_done_ch1_st:1; + /** gdma_evt_in_done_ch2_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GDMA_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_done_ch2_st:1; + /** gdma_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_suc_eof_ch0_st:1; + /** gdma_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_suc_eof_ch1_st:1; + /** gdma_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_suc_eof_ch2_st:1; + /** gdma_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_in_fifo_empty_ch0_st:1; + /** gdma_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_in_fifo_empty_ch1_st:1; + /** gdma_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_in_fifo_empty_ch2_st:1; + /** gdma_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_fifo_full_ch0_st:1; + /** gdma_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_fifo_full_ch1_st:1; + /** gdma_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_fifo_full_ch2_st:1; + /** gdma_evt_out_done_ch0_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GDMA_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_done_ch0_st:1; + /** gdma_evt_out_done_ch1_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GDMA_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_done_ch1_st:1; + /** gdma_evt_out_done_ch2_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GDMA_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_done_ch2_st:1; + /** gdma_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_eof_ch0_st:1; + /** gdma_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GDMA_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_eof_ch1_st:1; + /** gdma_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GDMA_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_eof_ch2_st:1; + /** gdma_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_total_eof_ch0_st:1; + /** gdma_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_total_eof_ch1_st:1; + /** gdma_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_total_eof_ch2_st:1; + /** gdma_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_empty_ch0_st:1; + /** gdma_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_empty_ch1_st:1; + }; + uint32_t val; +} soc_etm_evt_st3_reg_t; + +/** Type of evt_st4 register + * Events trigger status register + */ +typedef union { + struct { + /** gdma_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_empty_ch2_st:1; + /** gdma_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_full_ch0_st:1; + /** gdma_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_full_ch1_st:1; + /** gdma_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_full_ch2_st:1; + /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_evt_over_limit_st:1; + /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_rx_done_st:1; + /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_tx_done_st:1; + /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_received_st:1; + /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_sent_st:1; + /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_err_intr_st:1; + /** ulp_evt_halt_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_halt_st:1; + /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_start_intr_st:1; + /** rtc_evt_tick_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_tick_st:1; + /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_ovf_st:1; + /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_cmp_st:1; + /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_evt_sleep_weekup_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} soc_etm_evt_st4_reg_t; + +/** Type of task_st0 register + * Tasks trigger status register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_set_st:1; + /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_set_st:1; + /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_set_st:1; + /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_set_st:1; + /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_set_st:1; + /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_set_st:1; + /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_set_st:1; + /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_set_st:1; + /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_clear_st:1; + /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_clear_st:1; + /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_clear_st:1; + /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_clear_st:1; + /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_clear_st:1; + /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_clear_st:1; + /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_clear_st:1; + /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_clear_st:1; + /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_toggle_st:1; + /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_toggle_st:1; + /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_toggle_st:1; + /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_toggle_st:1; + /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_toggle_st:1; + /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_toggle_st:1; + /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_toggle_st:1; + /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_toggle_st:1; + /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer0_res_update_st:1; + /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer1_res_update_st:1; + /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer2_res_update_st:1; + /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer3_res_update_st:1; + /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch0_st:1; + /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch1_st:1; + /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch2_st:1; + /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch3_st:1; + }; + uint32_t val; +} soc_etm_task_st0_reg_t; + +/** Type of task_st1 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch4_st:1; + /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch5_st:1; + /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_cap_st:1; + /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_cap_st:1; + /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_cap_st:1; + /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_cap_st:1; + /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch0_st:1; + /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch1_st:1; + /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch2_st:1; + /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch3_st:1; + /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch4_st:1; + /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch5_st:1; + /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st:1; + /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st:1; + /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st:1; + /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st:1; + /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st:1; + /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st:1; + /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_rst_st:1; + /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_rst_st:1; + /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_rst_st:1; + /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_rst_st:1; + /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_resume_st:1; + /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_resume_st:1; + /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_resume_st:1; + /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_resume_st:1; + /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_pause_st:1; + /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_pause_st:1; + /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_pause_st:1; + /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_pause_st:1; + /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch0_st:1; + /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch1_st:1; + }; + uint32_t val; +} soc_etm_task_st1_reg_t; + +/** Type of task_st2 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch2_st:1; + /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch3_st:1; + /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch4_st:1; + /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch5_st:1; + /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch0_st:1; + /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch1_st:1; + /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch2_st:1; + /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch3_st:1; + /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch4_st:1; + /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch5_st:1; + /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch0_st:1; + /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch1_st:1; + /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch2_st:1; + /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch3_st:1; + /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch4_st:1; + /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch5_st:1; + /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer0_st:1; + /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer0_st:1; + /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer0_st:1; + /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer0_st:1; + /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer0_st:1; + /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer1_st:1; + /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer1_st:1; + /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer1_st:1; + /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer1_st:1; + /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer1_st:1; + /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer0_st:1; + /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer0_st:1; + /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer0_st:1; + /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer0_st:1; + /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer0_st:1; + /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer1_st:1; + }; + uint32_t val; +} soc_etm_task_st2_reg_t; + +/** Type of task_st3 register + * Tasks trigger status register + */ +typedef union { + struct { + /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer1_st:1; + /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer1_st:1; + /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer1_st:1; + /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer1_st:1; + /** mcpwm0_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr0_a_up_st:1; + /** mcpwm0_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr1_a_up_st:1; + /** mcpwm0_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr2_a_up_st:1; + /** mcpwm0_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr0_b_up_st:1; + /** mcpwm0_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr1_b_up_st:1; + /** mcpwm0_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr2_b_up_st:1; + /** mcpwm0_task_gen_stop_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_gen_stop_st:1; + /** mcpwm0_task_timer0_syn_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer0_syn_st:1; + /** mcpwm0_task_timer1_syn_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer1_syn_st:1; + /** mcpwm0_task_timer2_syn_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer2_syn_st:1; + /** mcpwm0_task_timer0_period_up_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer0_period_up_st:1; + /** mcpwm0_task_timer1_period_up_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer1_period_up_st:1; + /** mcpwm0_task_timer2_period_up_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer2_period_up_st:1; + /** mcpwm0_task_tz0_ost_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz0_ost_st:1; + /** mcpwm0_task_tz1_ost_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz1_ost_st:1; + /** mcpwm0_task_tz2_ost_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz2_ost_st:1; + /** mcpwm0_task_clr0_ost_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr0_ost_st:1; + /** mcpwm0_task_clr1_ost_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr1_ost_st:1; + /** mcpwm0_task_clr2_ost_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr2_ost_st:1; + /** mcpwm0_task_cap0_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap0_st:1; + /** mcpwm0_task_cap1_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap1_st:1; + /** mcpwm0_task_cap2_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap2_st:1; + /** adc_task_sample0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample0_st:1; + /** adc_task_sample1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample1_st:1; + /** adc_task_start0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_start0_st:1; + /** adc_task_stop0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_stop0_st:1; + /** regdma_task_start0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start0_st:1; + /** regdma_task_start1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start1_st:1; + }; + uint32_t val; +} soc_etm_task_st3_reg_t; + +/** Type of task_st4 register + * Tasks trigger status register + */ +typedef union { + struct { + /** regdma_task_start2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start2_st:1; + /** regdma_task_start3_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start3_st:1; + /** gdma_task_in_start_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_in_start_ch0_st:1; + /** gdma_task_in_start_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_in_start_ch1_st:1; + /** gdma_task_in_start_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_in_start_ch2_st:1; + /** gdma_task_out_start_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GDMA_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_out_start_ch0_st:1; + /** gdma_task_out_start_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GDMA_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_out_start_ch1_st:1; + /** gdma_task_out_start_ch2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_out_start_ch2_st:1; + /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_start_sample_st:1; + /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_stop_sample_st:1; + /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_rx_st:1; + /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_tx_st:1; + /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_rx_st:1; + /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_tx_st:1; + /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_wakeup_cpu_st:1; + /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_int_cpu_st:1; + /** rtc_task_start_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_start_st:1; + /** rtc_task_stop_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_stop_st:1; + /** rtc_task_clr_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_clr_st:1; + /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_triggerflw_st:1; + /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_task_sleep_req_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} soc_etm_task_st4_reg_t; + + +/** Group: Configuration Register */ +/** Type of ch_ena_ad0_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_enable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable0:1; + /** ch_enable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable1:1; + /** ch_enable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable2:1; + /** ch_enable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable3:1; + /** ch_enable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable4:1; + /** ch_enable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable5:1; + /** ch_enable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable6:1; + /** ch_enable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable7:1; + /** ch_enable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable8:1; + /** ch_enable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable9:1; + /** ch_enable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable10:1; + /** ch_enable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable11:1; + /** ch_enable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable12:1; + /** ch_enable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable13:1; + /** ch_enable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable14:1; + /** ch_enable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable15:1; + /** ch_enable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable16:1; + /** ch_enable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable17:1; + /** ch_enable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable18:1; + /** ch_enable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable19:1; + /** ch_enable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable20:1; + /** ch_enable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable21:1; + /** ch_enable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable22:1; + /** ch_enable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable23:1; + /** ch_enable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable24:1; + /** ch_enable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable25:1; + /** ch_enable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable26:1; + /** ch_enable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable27:1; + /** ch_enable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable28:1; + /** ch_enable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable29:1; + /** ch_enable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable30:1; + /** ch_enable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_set_reg_t; + +/** Type of ch_ena_ad0_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_disable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable0:1; + /** ch_disable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable1:1; + /** ch_disable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable2:1; + /** ch_disable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable3:1; + /** ch_disable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable4:1; + /** ch_disable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable5:1; + /** ch_disable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable6:1; + /** ch_disable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable7:1; + /** ch_disable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable8:1; + /** ch_disable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable9:1; + /** ch_disable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable10:1; + /** ch_disable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable11:1; + /** ch_disable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable12:1; + /** ch_disable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable13:1; + /** ch_disable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable14:1; + /** ch_disable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable15:1; + /** ch_disable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable16:1; + /** ch_disable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable17:1; + /** ch_disable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable18:1; + /** ch_disable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable19:1; + /** ch_disable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable20:1; + /** ch_disable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable21:1; + /** ch_disable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable22:1; + /** ch_disable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable23:1; + /** ch_disable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable24:1; + /** ch_disable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable25:1; + /** ch_disable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable26:1; + /** ch_disable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable27:1; + /** ch_disable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable28:1; + /** ch_disable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable29:1; + /** ch_disable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable30:1; + /** ch_disable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_clr_reg_t; + +/** Type of ch_ena_ad1_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_enable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable32:1; + /** ch_enable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable33:1; + /** ch_enable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable34:1; + /** ch_enable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable35:1; + /** ch_enable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable36:1; + /** ch_enable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable37:1; + /** ch_enable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable38:1; + /** ch_enable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable39:1; + /** ch_enable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable40:1; + /** ch_enable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable41:1; + /** ch_enable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable42:1; + /** ch_enable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable43:1; + /** ch_enable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable44:1; + /** ch_enable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable45:1; + /** ch_enable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable46:1; + /** ch_enable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable47:1; + /** ch_enable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable48:1; + /** ch_enable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_set_reg_t; + +/** Type of ch_ena_ad1_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_disable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable32:1; + /** ch_disable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable33:1; + /** ch_disable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable34:1; + /** ch_disable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable35:1; + /** ch_disable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable36:1; + /** ch_disable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable37:1; + /** ch_disable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable38:1; + /** ch_disable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable39:1; + /** ch_disable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable40:1; + /** ch_disable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable41:1; + /** ch_disable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable42:1; + /** ch_disable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable43:1; + /** ch_disable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable44:1; + /** ch_disable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable45:1; + /** ch_disable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable46:1; + /** ch_disable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable47:1; + /** ch_disable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable48:1; + /** ch_disable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_clr_reg_t; + +/** Type of evt_id register + * Channel event id register + */ +typedef union { + struct { + /** evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_evt_id + */ + uint32_t evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch_evt_id_reg_t; + +/** Type of task_id register + * Channel task id register + */ +typedef union { + struct { + /** task_id : R/W; bitpos: [7:0]; default: 0; + * Configures task_id + */ + uint32_t task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch_task_id_reg_t; + + +/** Type of evt_st0_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_rise_edge_st_clr:1; + /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_rise_edge_st_clr:1; + /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_rise_edge_st_clr:1; + /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_rise_edge_st_clr:1; + /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_rise_edge_st_clr:1; + /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_rise_edge_st_clr:1; + /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_rise_edge_st_clr:1; + /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_rise_edge_st_clr:1; + /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_fall_edge_st_clr:1; + /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_fall_edge_st_clr:1; + /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_fall_edge_st_clr:1; + /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_fall_edge_st_clr:1; + /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_fall_edge_st_clr:1; + /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_fall_edge_st_clr:1; + /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_fall_edge_st_clr:1; + /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_fall_edge_st_clr:1; + /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_any_edge_st_clr:1; + /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_any_edge_st_clr:1; + /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_any_edge_st_clr:1; + /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_any_edge_st_clr:1; + /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_any_edge_st_clr:1; + /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_any_edge_st_clr:1; + /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_any_edge_st_clr:1; + /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_any_edge_st_clr:1; + /** gpio_evt_zero_det_pos_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_pos_st_clr:1; + /** gpio_evt_zero_det_neg_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_neg_st_clr:1; + /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1; + /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1; + /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1; + /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1; + /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1; + /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st0_clr_reg_t; + +/** Type of evt_st1_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1; + /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer0_st_clr:1; + /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer1_st_clr:1; + /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer2_st_clr:1; + /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer3_st_clr:1; + /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer0_cmp_st_clr:1; + /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer1_cmp_st_clr:1; + /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer2_cmp_st_clr:1; + /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer3_cmp_st_clr:1; + /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1; + /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1; + /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1; + /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1; + /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp0_st_clr:1; + /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp1_st_clr:1; + /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp2_st_clr:1; + /** mcpwm0_evt_timer0_stop_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_stop_st_clr:1; + /** mcpwm0_evt_timer1_stop_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_stop_st_clr:1; + /** mcpwm0_evt_timer2_stop_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_stop_st_clr:1; + /** mcpwm0_evt_timer0_tez_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_tez_st_clr:1; + /** mcpwm0_evt_timer1_tez_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_tez_st_clr:1; + /** mcpwm0_evt_timer2_tez_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_tez_st_clr:1; + /** mcpwm0_evt_timer0_tep_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_tep_st_clr:1; + /** mcpwm0_evt_timer1_tep_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_tep_st_clr:1; + /** mcpwm0_evt_timer2_tep_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_tep_st_clr:1; + /** mcpwm0_evt_op0_tea_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tea_st_clr:1; + /** mcpwm0_evt_op1_tea_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tea_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st1_clr_reg_t; + +/** Type of evt_st2_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** mcpwm0_evt_op2_tea_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tea_st_clr:1; + /** mcpwm0_evt_op0_teb_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_teb_st_clr:1; + /** mcpwm0_evt_op1_teb_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_teb_st_clr:1; + /** mcpwm0_evt_op2_teb_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_teb_st_clr:1; + /** mcpwm0_evt_f0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f0_st_clr:1; + /** mcpwm0_evt_f1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f1_st_clr:1; + /** mcpwm0_evt_f2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f2_st_clr:1; + /** mcpwm0_evt_f0_clr_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f0_clr_st_clr:1; + /** mcpwm0_evt_f1_clr_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f1_clr_st_clr:1; + /** mcpwm0_evt_f2_clr_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f2_clr_st_clr:1; + /** mcpwm0_evt_tz0_cbc_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz0_cbc_st_clr:1; + /** mcpwm0_evt_tz1_cbc_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz1_cbc_st_clr:1; + /** mcpwm0_evt_tz2_cbc_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz2_cbc_st_clr:1; + /** mcpwm0_evt_tz0_ost_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz0_ost_st_clr:1; + /** mcpwm0_evt_tz1_ost_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz1_ost_st_clr:1; + /** mcpwm0_evt_tz2_ost_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz2_ost_st_clr:1; + /** mcpwm0_evt_cap0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap0_st_clr:1; + /** mcpwm0_evt_cap1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap1_st_clr:1; + /** mcpwm0_evt_cap2_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap2_st_clr:1; + /** mcpwm0_evt_op0_tee1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tee1_st_clr:1; + /** mcpwm0_evt_op1_tee1_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tee1_st_clr:1; + /** mcpwm0_evt_op2_tee1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tee1_st_clr:1; + /** mcpwm0_evt_op0_tee2_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tee2_st_clr:1; + /** mcpwm0_evt_op1_tee2_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tee2_st_clr:1; + /** mcpwm0_evt_op2_tee2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tee2_st_clr:1; + /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t adc_evt_conv_cmplt0_st_clr:1; + /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh0_st_clr:1; + /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh1_st_clr:1; + /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh0_st_clr:1; + /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh1_st_clr:1; + /** adc_evt_result_done0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_result_done0_st_clr:1; + /** adc_evt_stopped0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_stopped0_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st2_clr_reg_t; + +/** Type of evt_st3_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** adc_evt_started0_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_started0_st_clr:1; + /** regdma_evt_done0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done0_st_clr:1; + /** regdma_evt_done1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done1_st_clr:1; + /** regdma_evt_done2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done2_st_clr:1; + /** regdma_evt_done3_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done3_st_clr:1; + /** regdma_evt_err0_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err0_st_clr:1; + /** regdma_evt_err1_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err1_st_clr:1; + /** regdma_evt_err2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err2_st_clr:1; + /** regdma_evt_err3_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err3_st_clr:1; + /** gdma_evt_in_done_ch0_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_done_ch0_st_clr:1; + /** gdma_evt_in_done_ch1_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_done_ch1_st_clr:1; + /** gdma_evt_in_done_ch2_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_done_ch2_st_clr:1; + /** gdma_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_suc_eof_ch0_st_clr:1; + /** gdma_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_suc_eof_ch1_st_clr:1; + /** gdma_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_suc_eof_ch2_st_clr:1; + /** gdma_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_empty_ch0_st_clr:1; + /** gdma_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_empty_ch1_st_clr:1; + /** gdma_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_empty_ch2_st_clr:1; + /** gdma_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_full_ch0_st_clr:1; + /** gdma_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_full_ch1_st_clr:1; + /** gdma_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_full_ch2_st_clr:1; + /** gdma_evt_out_done_ch0_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_done_ch0_st_clr:1; + /** gdma_evt_out_done_ch1_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_done_ch1_st_clr:1; + /** gdma_evt_out_done_ch2_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_done_ch2_st_clr:1; + /** gdma_evt_out_eof_ch0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_eof_ch0_st_clr:1; + /** gdma_evt_out_eof_ch1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_eof_ch1_st_clr:1; + /** gdma_evt_out_eof_ch2_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_eof_ch2_st_clr:1; + /** gdma_evt_out_total_eof_ch0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_total_eof_ch0_st_clr:1; + /** gdma_evt_out_total_eof_ch1_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_total_eof_ch1_st_clr:1; + /** gdma_evt_out_total_eof_ch2_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_total_eof_ch2_st_clr:1; + /** gdma_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_empty_ch0_st_clr:1; + /** gdma_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_empty_ch1_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st3_clr_reg_t; + +/** Type of evt_st4_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gdma_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_empty_ch2_st_clr:1; + /** gdma_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_full_ch0_st_clr:1; + /** gdma_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_full_ch1_st_clr:1; + /** gdma_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_full_ch2_st_clr:1; + /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_evt_over_limit_st_clr:1; + /** i2s0_evt_rx_done_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_rx_done_st_clr:1; + /** i2s0_evt_tx_done_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_tx_done_st_clr:1; + /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_received_st_clr:1; + /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_sent_st_clr:1; + /** ulp_evt_err_intr_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_err_intr_st_clr:1; + /** ulp_evt_halt_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_halt_st_clr:1; + /** ulp_evt_start_intr_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_evt_start_intr_st_clr:1; + /** rtc_evt_tick_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_tick_st_clr:1; + /** rtc_evt_ovf_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_ovf_st_clr:1; + /** rtc_evt_cmp_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_cmp_st_clr:1; + /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pmu_evt_sleep_weekup_st_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} soc_etm_evt_st4_clr_reg_t; + +/** Type of task_st0_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_set_st_clr:1; + /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_set_st_clr:1; + /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_set_st_clr:1; + /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_set_st_clr:1; + /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_set_st_clr:1; + /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_set_st_clr:1; + /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_set_st_clr:1; + /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_set_st_clr:1; + /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_clear_st_clr:1; + /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_clear_st_clr:1; + /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_clear_st_clr:1; + /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_clear_st_clr:1; + /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_clear_st_clr:1; + /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_clear_st_clr:1; + /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_clear_st_clr:1; + /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_clear_st_clr:1; + /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch0_toggle_st_clr:1; + /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch1_toggle_st_clr:1; + /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch2_toggle_st_clr:1; + /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch3_toggle_st_clr:1; + /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch4_toggle_st_clr:1; + /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch5_toggle_st_clr:1; + /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch6_toggle_st_clr:1; + /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch7_toggle_st_clr:1; + /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_res_update_st_clr:1; + /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_res_update_st_clr:1; + /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_res_update_st_clr:1; + /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_res_update_st_clr:1; + /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch0_st_clr:1; + /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch1_st_clr:1; + /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch2_st_clr:1; + /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch3_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st0_clr_reg_t; + +/** Type of task_st1_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch4_st_clr:1; + /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch5_st_clr:1; + /** ledc_task_timer0_cap_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_cap_st_clr:1; + /** ledc_task_timer1_cap_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_cap_st_clr:1; + /** ledc_task_timer2_cap_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_cap_st_clr:1; + /** ledc_task_timer3_cap_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_cap_st_clr:1; + /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch0_st_clr:1; + /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch1_st_clr:1; + /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch2_st_clr:1; + /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch3_st_clr:1; + /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch4_st_clr:1; + /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch5_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1; + /** ledc_task_timer0_rst_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_rst_st_clr:1; + /** ledc_task_timer1_rst_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_rst_st_clr:1; + /** ledc_task_timer2_rst_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_rst_st_clr:1; + /** ledc_task_timer3_rst_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_rst_st_clr:1; + /** ledc_task_timer0_resume_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_resume_st_clr:1; + /** ledc_task_timer1_resume_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_resume_st_clr:1; + /** ledc_task_timer2_resume_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_resume_st_clr:1; + /** ledc_task_timer3_resume_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_resume_st_clr:1; + /** ledc_task_timer0_pause_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_pause_st_clr:1; + /** ledc_task_timer1_pause_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_pause_st_clr:1; + /** ledc_task_timer2_pause_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_pause_st_clr:1; + /** ledc_task_timer3_pause_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_pause_st_clr:1; + /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch0_st_clr:1; + /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st1_clr_reg_t; + +/** Type of task_st2_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch2_st_clr:1; + /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch3_st_clr:1; + /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch4_st_clr:1; + /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch5_st_clr:1; + /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch0_st_clr:1; + /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch1_st_clr:1; + /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch2_st_clr:1; + /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch3_st_clr:1; + /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch4_st_clr:1; + /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch5_st_clr:1; + /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch0_st_clr:1; + /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch1_st_clr:1; + /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch2_st_clr:1; + /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch3_st_clr:1; + /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch4_st_clr:1; + /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch5_st_clr:1; + /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer0_st_clr:1; + /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer0_st_clr:1; + /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer0_st_clr:1; + /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer0_st_clr:1; + /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer0_st_clr:1; + /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer1_st_clr:1; + /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer1_st_clr:1; + /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer1_st_clr:1; + /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer1_st_clr:1; + /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer1_st_clr:1; + /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer0_st_clr:1; + /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer0_st_clr:1; + /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer0_st_clr:1; + /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer0_st_clr:1; + /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer0_st_clr:1; + /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st2_clr_reg_t; + +/** Type of task_st3_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer1_st_clr:1; + /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer1_st_clr:1; + /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer1_st_clr:1; + /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer1_st_clr:1; + /** mcpwm0_task_cmpr0_a_up_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr0_a_up_st_clr:1; + /** mcpwm0_task_cmpr1_a_up_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr1_a_up_st_clr:1; + /** mcpwm0_task_cmpr2_a_up_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr2_a_up_st_clr:1; + /** mcpwm0_task_cmpr0_b_up_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr0_b_up_st_clr:1; + /** mcpwm0_task_cmpr1_b_up_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr1_b_up_st_clr:1; + /** mcpwm0_task_cmpr2_b_up_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr2_b_up_st_clr:1; + /** mcpwm0_task_gen_stop_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_gen_stop_st_clr:1; + /** mcpwm0_task_timer0_syn_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer0_syn_st_clr:1; + /** mcpwm0_task_timer1_syn_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer1_syn_st_clr:1; + /** mcpwm0_task_timer2_syn_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer2_syn_st_clr:1; + /** mcpwm0_task_timer0_period_up_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer0_period_up_st_clr:1; + /** mcpwm0_task_timer1_period_up_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer1_period_up_st_clr:1; + /** mcpwm0_task_timer2_period_up_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer2_period_up_st_clr:1; + /** mcpwm0_task_tz0_ost_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz0_ost_st_clr:1; + /** mcpwm0_task_tz1_ost_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz1_ost_st_clr:1; + /** mcpwm0_task_tz2_ost_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz2_ost_st_clr:1; + /** mcpwm0_task_clr0_ost_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr0_ost_st_clr:1; + /** mcpwm0_task_clr1_ost_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr1_ost_st_clr:1; + /** mcpwm0_task_clr2_ost_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr2_ost_st_clr:1; + /** mcpwm0_task_cap0_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap0_st_clr:1; + /** mcpwm0_task_cap1_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap1_st_clr:1; + /** mcpwm0_task_cap2_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap2_st_clr:1; + /** adc_task_sample0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample0_st_clr:1; + /** adc_task_sample1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample1_st_clr:1; + /** adc_task_start0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_start0_st_clr:1; + /** adc_task_stop0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_stop0_st_clr:1; + /** regdma_task_start0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start0_st_clr:1; + /** regdma_task_start1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st3_clr_reg_t; + +/** Type of task_st4_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** regdma_task_start2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start2_st_clr:1; + /** regdma_task_start3_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start3_st_clr:1; + /** gdma_task_in_start_ch0_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_in_start_ch0_st_clr:1; + /** gdma_task_in_start_ch1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_in_start_ch1_st_clr:1; + /** gdma_task_in_start_ch2_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_in_start_ch2_st_clr:1; + /** gdma_task_out_start_ch0_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_out_start_ch0_st_clr:1; + /** gdma_task_out_start_ch1_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_out_start_ch1_st_clr:1; + /** gdma_task_out_start_ch2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_out_start_ch2_st_clr:1; + /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_start_sample_st_clr:1; + /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_stop_sample_st_clr:1; + /** i2s0_task_start_rx_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_rx_st_clr:1; + /** i2s0_task_start_tx_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_tx_st_clr:1; + /** i2s0_task_stop_rx_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_rx_st_clr:1; + /** i2s0_task_stop_tx_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_tx_st_clr:1; + /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_task_wakeup_cpu_st_clr:1; + /** ulp_task_int_cpu_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_task_int_cpu_st_clr:1; + /** rtc_task_start_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_start_st_clr:1; + /** rtc_task_stop_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_stop_st_clr:1; + /** rtc_task_clr_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_clr_st_clr:1; + /** rtc_task_triggerflw_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t rtc_task_triggerflw_st_clr:1; + /** pmu_task_sleep_req_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t pmu_task_sleep_req_st_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} soc_etm_task_st4_clr_reg_t; + +/** Type of clk_en register + * ETM clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} soc_etm_clk_en_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * ETM date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716929; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} soc_etm_date_reg_t; + + +typedef struct soc_etm_dev_t { + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile struct { + soc_etm_chn_evt_id_reg_t evt_id; + soc_etm_chn_task_id_reg_t task_id; + } channel[50]; + volatile soc_etm_evt_st0_reg_t evt_st0; + volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; + volatile soc_etm_evt_st1_reg_t evt_st1; + volatile soc_etm_evt_st1_clr_reg_t evt_st1_clr; + volatile soc_etm_evt_st2_reg_t evt_st2; + volatile soc_etm_evt_st2_clr_reg_t evt_st2_clr; + volatile soc_etm_evt_st3_reg_t evt_st3; + volatile soc_etm_evt_st3_clr_reg_t evt_st3_clr; + volatile soc_etm_evt_st4_reg_t evt_st4; + volatile soc_etm_evt_st4_clr_reg_t evt_st4_clr; + volatile soc_etm_task_st0_reg_t task_st0; + volatile soc_etm_task_st0_clr_reg_t task_st0_clr; + volatile soc_etm_task_st1_reg_t task_st1; + volatile soc_etm_task_st1_clr_reg_t task_st1_clr; + volatile soc_etm_task_st2_reg_t task_st2; + volatile soc_etm_task_st2_clr_reg_t task_st2_clr; + volatile soc_etm_task_st3_reg_t task_st3; + volatile soc_etm_task_st3_clr_reg_t task_st3_clr; + volatile soc_etm_task_st4_reg_t task_st4; + volatile soc_etm_task_st4_clr_reg_t task_st4_clr; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; +} soc_etm_dev_t; + +extern soc_etm_dev_t SOC_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(soc_etm_dev_t) == 0x200, "Invalid size of soc_etm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/soc_pins.h b/components/soc/esp32c5/include/soc/soc_pins.h new file mode 100644 index 00000000000..064950aaaaf --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_pins.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Pin definition header file. The long term plan is to have a single soc_pins.h for all + * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each + * peripheral and include them here to avoid developing conflicts in those header files. + */ + +#pragma once + +#include "soc/gpio_pins.h" +#include "soc/spi_pins.h" diff --git a/components/soc/esp32c5/include/soc/spi1_mem_reg.h b/components/soc/esp32c5/include/soc/spi1_mem_reg.h new file mode 100644 index 00000000000..75ad9765f7d --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi1_mem_reg.h @@ -0,0 +1,1232 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI1_MEM_CMD_REG register + * SPI1 memory command register + */ +#define SPI1_MEM_CMD_REG (DR_REG_SPIMEM1_BASE + 0x0) +/** SPI1_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ +#define SPI1_MEM_MST_ST 0x0000000FU +#define SPI1_MEM_MST_ST_M (SPI1_MEM_MST_ST_V << SPI1_MEM_MST_ST_S) +#define SPI1_MEM_MST_ST_V 0x0000000FU +#define SPI1_MEM_MST_ST_S 0 +/** SPI1_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI1_MEM_SLV_ST 0x0000000FU +#define SPI1_MEM_SLV_ST_M (SPI1_MEM_SLV_ST_V << SPI1_MEM_SLV_ST_S) +#define SPI1_MEM_SLV_ST_V 0x0000000FU +#define SPI1_MEM_SLV_ST_S 4 +/** SPI1_MEM_USR : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_USR (BIT(18)) +#define SPI1_MEM_USR_M (SPI1_MEM_USR_V << SPI1_MEM_USR_S) +#define SPI1_MEM_USR_V 0x00000001U +#define SPI1_MEM_USR_S 18 + +/** SPI1_MEM_ADDR_REG register + * SPI1 address register + */ +#define SPI1_MEM_ADDR_REG (DR_REG_SPIMEM1_BASE + 0x4) +/** SPI1_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ +#define SPI1_MEM_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI1_MEM_USR_ADDR_VALUE_M (SPI1_MEM_USR_ADDR_VALUE_V << SPI1_MEM_USR_ADDR_VALUE_S) +#define SPI1_MEM_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI1_MEM_USR_ADDR_VALUE_S 0 + +/** SPI1_MEM_CTRL_REG register + * SPI1 control register. + */ +#define SPI1_MEM_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x8) +/** SPI1_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_FDUMMY_RIN (BIT(2)) +#define SPI1_MEM_FDUMMY_RIN_M (SPI1_MEM_FDUMMY_RIN_V << SPI1_MEM_FDUMMY_RIN_S) +#define SPI1_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI1_MEM_FDUMMY_RIN_S 2 +/** SPI1_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI1_MEM_FDUMMY_WOUT_M (SPI1_MEM_FDUMMY_WOUT_V << SPI1_MEM_FDUMMY_WOUT_S) +#define SPI1_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI1_MEM_FDUMMY_WOUT_S 3 +/** SPI1_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI1_MEM_FDOUT_OCT (BIT(4)) +#define SPI1_MEM_FDOUT_OCT_M (SPI1_MEM_FDOUT_OCT_V << SPI1_MEM_FDOUT_OCT_S) +#define SPI1_MEM_FDOUT_OCT_V 0x00000001U +#define SPI1_MEM_FDOUT_OCT_S 4 +/** SPI1_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI1_MEM_FDIN_OCT (BIT(5)) +#define SPI1_MEM_FDIN_OCT_M (SPI1_MEM_FDIN_OCT_V << SPI1_MEM_FDIN_OCT_S) +#define SPI1_MEM_FDIN_OCT_V 0x00000001U +#define SPI1_MEM_FDIN_OCT_S 5 +/** SPI1_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI1_MEM_FADDR_OCT (BIT(6)) +#define SPI1_MEM_FADDR_OCT_M (SPI1_MEM_FADDR_OCT_V << SPI1_MEM_FADDR_OCT_S) +#define SPI1_MEM_FADDR_OCT_V 0x00000001U +#define SPI1_MEM_FADDR_OCT_S 6 +/** SPI1_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_FCMD_QUAD (BIT(8)) +#define SPI1_MEM_FCMD_QUAD_M (SPI1_MEM_FCMD_QUAD_V << SPI1_MEM_FCMD_QUAD_S) +#define SPI1_MEM_FCMD_QUAD_V 0x00000001U +#define SPI1_MEM_FCMD_QUAD_S 8 +/** SPI1_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_FCMD_OCT (BIT(9)) +#define SPI1_MEM_FCMD_OCT_M (SPI1_MEM_FCMD_OCT_V << SPI1_MEM_FCMD_OCT_S) +#define SPI1_MEM_FCMD_OCT_V 0x00000001U +#define SPI1_MEM_FCMD_OCT_S 9 +/** SPI1_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. + */ +#define SPI1_MEM_FASTRD_MODE (BIT(13)) +#define SPI1_MEM_FASTRD_MODE_M (SPI1_MEM_FASTRD_MODE_V << SPI1_MEM_FASTRD_MODE_S) +#define SPI1_MEM_FASTRD_MODE_V 0x00000001U +#define SPI1_MEM_FASTRD_MODE_S 13 +/** SPI1_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_FREAD_DUAL (BIT(14)) +#define SPI1_MEM_FREAD_DUAL_M (SPI1_MEM_FREAD_DUAL_V << SPI1_MEM_FREAD_DUAL_S) +#define SPI1_MEM_FREAD_DUAL_V 0x00000001U +#define SPI1_MEM_FREAD_DUAL_S 14 +/** SPI1_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI1_MEM_Q_POL (BIT(18)) +#define SPI1_MEM_Q_POL_M (SPI1_MEM_Q_POL_V << SPI1_MEM_Q_POL_S) +#define SPI1_MEM_Q_POL_V 0x00000001U +#define SPI1_MEM_Q_POL_S 18 +/** SPI1_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI1_MEM_D_POL (BIT(19)) +#define SPI1_MEM_D_POL_M (SPI1_MEM_D_POL_V << SPI1_MEM_D_POL_S) +#define SPI1_MEM_D_POL_V 0x00000001U +#define SPI1_MEM_D_POL_S 19 +/** SPI1_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_FREAD_QUAD (BIT(20)) +#define SPI1_MEM_FREAD_QUAD_M (SPI1_MEM_FREAD_QUAD_V << SPI1_MEM_FREAD_QUAD_S) +#define SPI1_MEM_FREAD_QUAD_V 0x00000001U +#define SPI1_MEM_FREAD_QUAD_S 20 +/** SPI1_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI1_MEM_WP_REG (BIT(21)) +#define SPI1_MEM_WP_REG_M (SPI1_MEM_WP_REG_V << SPI1_MEM_WP_REG_S) +#define SPI1_MEM_WP_REG_V 0x00000001U +#define SPI1_MEM_WP_REG_S 21 +/** SPI1_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_FREAD_DIO (BIT(23)) +#define SPI1_MEM_FREAD_DIO_M (SPI1_MEM_FREAD_DIO_V << SPI1_MEM_FREAD_DIO_S) +#define SPI1_MEM_FREAD_DIO_V 0x00000001U +#define SPI1_MEM_FREAD_DIO_S 23 +/** SPI1_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_FREAD_QIO (BIT(24)) +#define SPI1_MEM_FREAD_QIO_M (SPI1_MEM_FREAD_QIO_V << SPI1_MEM_FREAD_QIO_S) +#define SPI1_MEM_FREAD_QIO_V 0x00000001U +#define SPI1_MEM_FREAD_QIO_S 24 + +/** SPI1_MEM_CTRL1_REG register + * SPI1 control1 register. + */ +#define SPI1_MEM_CTRL1_REG (DR_REG_SPIMEM1_BASE + 0xc) +/** SPI1_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ +#define SPI1_MEM_CLK_MODE 0x00000003U +#define SPI1_MEM_CLK_MODE_M (SPI1_MEM_CLK_MODE_V << SPI1_MEM_CLK_MODE_S) +#define SPI1_MEM_CLK_MODE_V 0x00000003U +#define SPI1_MEM_CLK_MODE_S 0 + +/** SPI1_MEM_CTRL2_REG register + * SPI1 control2 register. + */ +#define SPI1_MEM_CTRL2_REG (DR_REG_SPIMEM1_BASE + 0x10) +/** SPI1_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ +#define SPI1_MEM_SYNC_RESET (BIT(31)) +#define SPI1_MEM_SYNC_RESET_M (SPI1_MEM_SYNC_RESET_V << SPI1_MEM_SYNC_RESET_S) +#define SPI1_MEM_SYNC_RESET_V 0x00000001U +#define SPI1_MEM_SYNC_RESET_S 31 + +/** SPI1_MEM_CLOCK_REG register + * SPI1 clock division control register. + */ +#define SPI1_MEM_CLOCK_REG (DR_REG_SPIMEM1_BASE + 0x14) +/** SPI1_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI1_MEM_CLKCNT_L 0x000000FFU +#define SPI1_MEM_CLKCNT_L_M (SPI1_MEM_CLKCNT_L_V << SPI1_MEM_CLKCNT_L_S) +#define SPI1_MEM_CLKCNT_L_V 0x000000FFU +#define SPI1_MEM_CLKCNT_L_S 0 +/** SPI1_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI1_MEM_CLKCNT_H 0x000000FFU +#define SPI1_MEM_CLKCNT_H_M (SPI1_MEM_CLKCNT_H_V << SPI1_MEM_CLKCNT_H_S) +#define SPI1_MEM_CLKCNT_H_V 0x000000FFU +#define SPI1_MEM_CLKCNT_H_S 8 +/** SPI1_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI1_MEM_CLKCNT_N 0x000000FFU +#define SPI1_MEM_CLKCNT_N_M (SPI1_MEM_CLKCNT_N_V << SPI1_MEM_CLKCNT_N_S) +#define SPI1_MEM_CLKCNT_N_V 0x000000FFU +#define SPI1_MEM_CLKCNT_N_S 16 +/** SPI1_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SPI1_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI1_MEM_CLK_EQU_SYSCLK_M (SPI1_MEM_CLK_EQU_SYSCLK_V << SPI1_MEM_CLK_EQU_SYSCLK_S) +#define SPI1_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI1_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI1_MEM_USER_REG register + * SPI1 user register. + */ +#define SPI1_MEM_USER_REG (DR_REG_SPIMEM1_BASE + 0x18) +/** SPI1_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + */ +#define SPI1_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI1_MEM_CK_OUT_EDGE_M (SPI1_MEM_CK_OUT_EDGE_V << SPI1_MEM_CK_OUT_EDGE_S) +#define SPI1_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI1_MEM_CK_OUT_EDGE_S 9 +/** SPI1_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ +#define SPI1_MEM_FWRITE_DUAL (BIT(12)) +#define SPI1_MEM_FWRITE_DUAL_M (SPI1_MEM_FWRITE_DUAL_V << SPI1_MEM_FWRITE_DUAL_S) +#define SPI1_MEM_FWRITE_DUAL_V 0x00000001U +#define SPI1_MEM_FWRITE_DUAL_S 12 +/** SPI1_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ +#define SPI1_MEM_FWRITE_QUAD (BIT(13)) +#define SPI1_MEM_FWRITE_QUAD_M (SPI1_MEM_FWRITE_QUAD_V << SPI1_MEM_FWRITE_QUAD_S) +#define SPI1_MEM_FWRITE_QUAD_V 0x00000001U +#define SPI1_MEM_FWRITE_QUAD_S 13 +/** SPI1_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ +#define SPI1_MEM_FWRITE_DIO (BIT(14)) +#define SPI1_MEM_FWRITE_DIO_M (SPI1_MEM_FWRITE_DIO_V << SPI1_MEM_FWRITE_DIO_S) +#define SPI1_MEM_FWRITE_DIO_V 0x00000001U +#define SPI1_MEM_FWRITE_DIO_S 14 +/** SPI1_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ +#define SPI1_MEM_FWRITE_QIO (BIT(15)) +#define SPI1_MEM_FWRITE_QIO_M (SPI1_MEM_FWRITE_QIO_V << SPI1_MEM_FWRITE_QIO_S) +#define SPI1_MEM_FWRITE_QIO_V 0x00000001U +#define SPI1_MEM_FWRITE_QIO_S 15 +/** SPI1_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ +#define SPI1_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI1_MEM_USR_DUMMY_IDLE_M (SPI1_MEM_USR_DUMMY_IDLE_V << SPI1_MEM_USR_DUMMY_IDLE_S) +#define SPI1_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI1_MEM_USR_DUMMY_IDLE_S 26 +/** SPI1_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ +#define SPI1_MEM_USR_MOSI (BIT(27)) +#define SPI1_MEM_USR_MOSI_M (SPI1_MEM_USR_MOSI_V << SPI1_MEM_USR_MOSI_S) +#define SPI1_MEM_USR_MOSI_V 0x00000001U +#define SPI1_MEM_USR_MOSI_S 27 +/** SPI1_MEM_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ +#define SPI1_MEM_USR_MISO (BIT(28)) +#define SPI1_MEM_USR_MISO_M (SPI1_MEM_USR_MISO_V << SPI1_MEM_USR_MISO_S) +#define SPI1_MEM_USR_MISO_V 0x00000001U +#define SPI1_MEM_USR_MISO_S 28 +/** SPI1_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI1_MEM_USR_DUMMY (BIT(29)) +#define SPI1_MEM_USR_DUMMY_M (SPI1_MEM_USR_DUMMY_V << SPI1_MEM_USR_DUMMY_S) +#define SPI1_MEM_USR_DUMMY_V 0x00000001U +#define SPI1_MEM_USR_DUMMY_S 29 +/** SPI1_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ +#define SPI1_MEM_USR_ADDR (BIT(30)) +#define SPI1_MEM_USR_ADDR_M (SPI1_MEM_USR_ADDR_V << SPI1_MEM_USR_ADDR_S) +#define SPI1_MEM_USR_ADDR_V 0x00000001U +#define SPI1_MEM_USR_ADDR_S 30 +/** SPI1_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ +#define SPI1_MEM_USR_COMMAND (BIT(31)) +#define SPI1_MEM_USR_COMMAND_M (SPI1_MEM_USR_COMMAND_V << SPI1_MEM_USR_COMMAND_S) +#define SPI1_MEM_USR_COMMAND_V 0x00000001U +#define SPI1_MEM_USR_COMMAND_S 31 + +/** SPI1_MEM_USER1_REG register + * SPI1 user1 register. + */ +#define SPI1_MEM_USER1_REG (DR_REG_SPIMEM1_BASE + 0x1c) +/** SPI1_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI1_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_USR_DUMMY_CYCLELEN_M (SPI1_MEM_USR_DUMMY_CYCLELEN_V << SPI1_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI1_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI1_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI1_MEM_USR_ADDR_BITLEN_M (SPI1_MEM_USR_ADDR_BITLEN_V << SPI1_MEM_USR_ADDR_BITLEN_S) +#define SPI1_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI1_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI1_MEM_USER2_REG register + * SPI1 user2 register. + */ +#define SPI1_MEM_USER2_REG (DR_REG_SPIMEM1_BASE + 0x20) +/** SPI1_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI1_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI1_MEM_USR_COMMAND_VALUE_M (SPI1_MEM_USR_COMMAND_VALUE_V << SPI1_MEM_USR_COMMAND_VALUE_S) +#define SPI1_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI1_MEM_USR_COMMAND_VALUE_S 0 +/** SPI1_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI1_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI1_MEM_USR_COMMAND_BITLEN_M (SPI1_MEM_USR_COMMAND_BITLEN_V << SPI1_MEM_USR_COMMAND_BITLEN_S) +#define SPI1_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI1_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI1_MEM_MOSI_DLEN_REG register + * SPI1 send data bit length control register. + */ +#define SPI1_MEM_MOSI_DLEN_REG (DR_REG_SPIMEM1_BASE + 0x24) +/** SPI1_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_USR_MOSI_DBITLEN 0x000003FFU +#define SPI1_MEM_USR_MOSI_DBITLEN_M (SPI1_MEM_USR_MOSI_DBITLEN_V << SPI1_MEM_USR_MOSI_DBITLEN_S) +#define SPI1_MEM_USR_MOSI_DBITLEN_V 0x000003FFU +#define SPI1_MEM_USR_MOSI_DBITLEN_S 0 + +/** SPI1_MEM_MISO_DLEN_REG register + * SPI1 receive data bit length control register. + */ +#define SPI1_MEM_MISO_DLEN_REG (DR_REG_SPIMEM1_BASE + 0x28) +/** SPI1_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_USR_MISO_DBITLEN 0x000003FFU +#define SPI1_MEM_USR_MISO_DBITLEN_M (SPI1_MEM_USR_MISO_DBITLEN_V << SPI1_MEM_USR_MISO_DBITLEN_S) +#define SPI1_MEM_USR_MISO_DBITLEN_V 0x000003FFU +#define SPI1_MEM_USR_MISO_DBITLEN_S 0 + +/** SPI1_MEM_RD_STATUS_REG register + * SPI1 status register. + */ +#define SPI1_MEM_RD_STATUS_REG (DR_REG_SPIMEM1_BASE + 0x2c) +/** SPI1_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + */ +#define SPI1_MEM_STATUS 0x0000FFFFU +#define SPI1_MEM_STATUS_M (SPI1_MEM_STATUS_V << SPI1_MEM_STATUS_S) +#define SPI1_MEM_STATUS_V 0x0000FFFFU +#define SPI1_MEM_STATUS_S 0 + +/** SPI1_MEM_MISC_REG register + * SPI1 misc register + */ +#define SPI1_MEM_MISC_REG (DR_REG_SPIMEM1_BASE + 0x34) +/** SPI1_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_CS0_DIS (BIT(0)) +#define SPI1_MEM_CS0_DIS_M (SPI1_MEM_CS0_DIS_V << SPI1_MEM_CS0_DIS_S) +#define SPI1_MEM_CS0_DIS_V 0x00000001U +#define SPI1_MEM_CS0_DIS_S 0 +/** SPI1_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_CS1_DIS (BIT(1)) +#define SPI1_MEM_CS1_DIS_M (SPI1_MEM_CS1_DIS_V << SPI1_MEM_CS1_DIS_S) +#define SPI1_MEM_CS1_DIS_V 0x00000001U +#define SPI1_MEM_CS1_DIS_S 1 +/** SPI1_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ +#define SPI1_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI1_MEM_CK_IDLE_EDGE_M (SPI1_MEM_CK_IDLE_EDGE_V << SPI1_MEM_CK_IDLE_EDGE_S) +#define SPI1_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI1_MEM_CK_IDLE_EDGE_S 9 +/** SPI1_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ +#define SPI1_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI1_MEM_CS_KEEP_ACTIVE_M (SPI1_MEM_CS_KEEP_ACTIVE_V << SPI1_MEM_CS_KEEP_ACTIVE_S) +#define SPI1_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI1_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI1_MEM_W0_REG register + * SPI1 memory data buffer0 + */ +#define SPI1_MEM_W0_REG (DR_REG_SPIMEM1_BASE + 0x58) +/** SPI1_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF0 0xFFFFFFFFU +#define SPI1_MEM_BUF0_M (SPI1_MEM_BUF0_V << SPI1_MEM_BUF0_S) +#define SPI1_MEM_BUF0_V 0xFFFFFFFFU +#define SPI1_MEM_BUF0_S 0 + +/** SPI1_MEM_W1_REG register + * SPI1 memory data buffer1 + */ +#define SPI1_MEM_W1_REG (DR_REG_SPIMEM1_BASE + 0x5c) +/** SPI1_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF1 0xFFFFFFFFU +#define SPI1_MEM_BUF1_M (SPI1_MEM_BUF1_V << SPI1_MEM_BUF1_S) +#define SPI1_MEM_BUF1_V 0xFFFFFFFFU +#define SPI1_MEM_BUF1_S 0 + +/** SPI1_MEM_W2_REG register + * SPI1 memory data buffer2 + */ +#define SPI1_MEM_W2_REG (DR_REG_SPIMEM1_BASE + 0x60) +/** SPI1_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF2 0xFFFFFFFFU +#define SPI1_MEM_BUF2_M (SPI1_MEM_BUF2_V << SPI1_MEM_BUF2_S) +#define SPI1_MEM_BUF2_V 0xFFFFFFFFU +#define SPI1_MEM_BUF2_S 0 + +/** SPI1_MEM_W3_REG register + * SPI1 memory data buffer3 + */ +#define SPI1_MEM_W3_REG (DR_REG_SPIMEM1_BASE + 0x64) +/** SPI1_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF3 0xFFFFFFFFU +#define SPI1_MEM_BUF3_M (SPI1_MEM_BUF3_V << SPI1_MEM_BUF3_S) +#define SPI1_MEM_BUF3_V 0xFFFFFFFFU +#define SPI1_MEM_BUF3_S 0 + +/** SPI1_MEM_W4_REG register + * SPI1 memory data buffer4 + */ +#define SPI1_MEM_W4_REG (DR_REG_SPIMEM1_BASE + 0x68) +/** SPI1_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF4 0xFFFFFFFFU +#define SPI1_MEM_BUF4_M (SPI1_MEM_BUF4_V << SPI1_MEM_BUF4_S) +#define SPI1_MEM_BUF4_V 0xFFFFFFFFU +#define SPI1_MEM_BUF4_S 0 + +/** SPI1_MEM_W5_REG register + * SPI1 memory data buffer5 + */ +#define SPI1_MEM_W5_REG (DR_REG_SPIMEM1_BASE + 0x6c) +/** SPI1_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF5 0xFFFFFFFFU +#define SPI1_MEM_BUF5_M (SPI1_MEM_BUF5_V << SPI1_MEM_BUF5_S) +#define SPI1_MEM_BUF5_V 0xFFFFFFFFU +#define SPI1_MEM_BUF5_S 0 + +/** SPI1_MEM_W6_REG register + * SPI1 memory data buffer6 + */ +#define SPI1_MEM_W6_REG (DR_REG_SPIMEM1_BASE + 0x70) +/** SPI1_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF6 0xFFFFFFFFU +#define SPI1_MEM_BUF6_M (SPI1_MEM_BUF6_V << SPI1_MEM_BUF6_S) +#define SPI1_MEM_BUF6_V 0xFFFFFFFFU +#define SPI1_MEM_BUF6_S 0 + +/** SPI1_MEM_W7_REG register + * SPI1 memory data buffer7 + */ +#define SPI1_MEM_W7_REG (DR_REG_SPIMEM1_BASE + 0x74) +/** SPI1_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF7 0xFFFFFFFFU +#define SPI1_MEM_BUF7_M (SPI1_MEM_BUF7_V << SPI1_MEM_BUF7_S) +#define SPI1_MEM_BUF7_V 0xFFFFFFFFU +#define SPI1_MEM_BUF7_S 0 + +/** SPI1_MEM_W8_REG register + * SPI1 memory data buffer8 + */ +#define SPI1_MEM_W8_REG (DR_REG_SPIMEM1_BASE + 0x78) +/** SPI1_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF8 0xFFFFFFFFU +#define SPI1_MEM_BUF8_M (SPI1_MEM_BUF8_V << SPI1_MEM_BUF8_S) +#define SPI1_MEM_BUF8_V 0xFFFFFFFFU +#define SPI1_MEM_BUF8_S 0 + +/** SPI1_MEM_W9_REG register + * SPI1 memory data buffer9 + */ +#define SPI1_MEM_W9_REG (DR_REG_SPIMEM1_BASE + 0x7c) +/** SPI1_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF9 0xFFFFFFFFU +#define SPI1_MEM_BUF9_M (SPI1_MEM_BUF9_V << SPI1_MEM_BUF9_S) +#define SPI1_MEM_BUF9_V 0xFFFFFFFFU +#define SPI1_MEM_BUF9_S 0 + +/** SPI1_MEM_W10_REG register + * SPI1 memory data buffer10 + */ +#define SPI1_MEM_W10_REG (DR_REG_SPIMEM1_BASE + 0x80) +/** SPI1_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF10 0xFFFFFFFFU +#define SPI1_MEM_BUF10_M (SPI1_MEM_BUF10_V << SPI1_MEM_BUF10_S) +#define SPI1_MEM_BUF10_V 0xFFFFFFFFU +#define SPI1_MEM_BUF10_S 0 + +/** SPI1_MEM_W11_REG register + * SPI1 memory data buffer11 + */ +#define SPI1_MEM_W11_REG (DR_REG_SPIMEM1_BASE + 0x84) +/** SPI1_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF11 0xFFFFFFFFU +#define SPI1_MEM_BUF11_M (SPI1_MEM_BUF11_V << SPI1_MEM_BUF11_S) +#define SPI1_MEM_BUF11_V 0xFFFFFFFFU +#define SPI1_MEM_BUF11_S 0 + +/** SPI1_MEM_W12_REG register + * SPI1 memory data buffer12 + */ +#define SPI1_MEM_W12_REG (DR_REG_SPIMEM1_BASE + 0x88) +/** SPI1_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF12 0xFFFFFFFFU +#define SPI1_MEM_BUF12_M (SPI1_MEM_BUF12_V << SPI1_MEM_BUF12_S) +#define SPI1_MEM_BUF12_V 0xFFFFFFFFU +#define SPI1_MEM_BUF12_S 0 + +/** SPI1_MEM_W13_REG register + * SPI1 memory data buffer13 + */ +#define SPI1_MEM_W13_REG (DR_REG_SPIMEM1_BASE + 0x8c) +/** SPI1_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF13 0xFFFFFFFFU +#define SPI1_MEM_BUF13_M (SPI1_MEM_BUF13_V << SPI1_MEM_BUF13_S) +#define SPI1_MEM_BUF13_V 0xFFFFFFFFU +#define SPI1_MEM_BUF13_S 0 + +/** SPI1_MEM_W14_REG register + * SPI1 memory data buffer14 + */ +#define SPI1_MEM_W14_REG (DR_REG_SPIMEM1_BASE + 0x90) +/** SPI1_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF14 0xFFFFFFFFU +#define SPI1_MEM_BUF14_M (SPI1_MEM_BUF14_V << SPI1_MEM_BUF14_S) +#define SPI1_MEM_BUF14_V 0xFFFFFFFFU +#define SPI1_MEM_BUF14_S 0 + +/** SPI1_MEM_W15_REG register + * SPI1 memory data buffer15 + */ +#define SPI1_MEM_W15_REG (DR_REG_SPIMEM1_BASE + 0x94) +/** SPI1_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF15 0xFFFFFFFFU +#define SPI1_MEM_BUF15_M (SPI1_MEM_BUF15_V << SPI1_MEM_BUF15_S) +#define SPI1_MEM_BUF15_V 0xFFFFFFFFU +#define SPI1_MEM_BUF15_S 0 + +/** SPI1_MEM_FLASH_WAITI_CTRL_REG register + * SPI1 wait idle control register + */ +#define SPI1_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x98) +/** SPI1_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ +#define SPI1_MEM_WAITI_EN (BIT(0)) +#define SPI1_MEM_WAITI_EN_M (SPI1_MEM_WAITI_EN_V << SPI1_MEM_WAITI_EN_S) +#define SPI1_MEM_WAITI_EN_V 0x00000001U +#define SPI1_MEM_WAITI_EN_S 0 +/** SPI1_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ +#define SPI1_MEM_WAITI_DUMMY (BIT(1)) +#define SPI1_MEM_WAITI_DUMMY_M (SPI1_MEM_WAITI_DUMMY_V << SPI1_MEM_WAITI_DUMMY_S) +#define SPI1_MEM_WAITI_DUMMY_V 0x00000001U +#define SPI1_MEM_WAITI_DUMMY_S 1 +/** SPI1_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ +#define SPI1_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI1_MEM_WAITI_ADDR_EN_M (SPI1_MEM_WAITI_ADDR_EN_V << SPI1_MEM_WAITI_ADDR_EN_S) +#define SPI1_MEM_WAITI_ADDR_EN_V 0x00000001U +#define SPI1_MEM_WAITI_ADDR_EN_S 2 +/** SPI1_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_WAITI_ADDR_EN is cleared. + */ +#define SPI1_MEM_WAITI_ADDR_CYCLELEN 0x00000003U +#define SPI1_MEM_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_WAITI_ADDR_CYCLELEN_S) +#define SPI1_MEM_WAITI_ADDR_CYCLELEN_V 0x00000003U +#define SPI1_MEM_WAITI_ADDR_CYCLELEN_S 3 +/** SPI1_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ +#define SPI1_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI1_MEM_WAITI_CMD_2B_M (SPI1_MEM_WAITI_CMD_2B_V << SPI1_MEM_WAITI_CMD_2B_S) +#define SPI1_MEM_WAITI_CMD_2B_V 0x00000001U +#define SPI1_MEM_WAITI_CMD_2B_S 9 +/** SPI1_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_M (SPI1_MEM_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_WAITI_DUMMY_CYCLELEN_S) +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/** SPI1_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ +#define SPI1_MEM_WAITI_CMD 0x0000FFFFU +#define SPI1_MEM_WAITI_CMD_M (SPI1_MEM_WAITI_CMD_V << SPI1_MEM_WAITI_CMD_S) +#define SPI1_MEM_WAITI_CMD_V 0x0000FFFFU +#define SPI1_MEM_WAITI_CMD_S 16 + +/** SPI1_MEM_FLASH_SUS_CTRL_REG register + * SPI1 flash suspend control register + */ +#define SPI1_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x9c) +/** SPI1_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_FLASH_PER (BIT(0)) +#define SPI1_MEM_FLASH_PER_M (SPI1_MEM_FLASH_PER_V << SPI1_MEM_FLASH_PER_S) +#define SPI1_MEM_FLASH_PER_V 0x00000001U +#define SPI1_MEM_FLASH_PER_S 0 +/** SPI1_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_FLASH_PES (BIT(1)) +#define SPI1_MEM_FLASH_PES_M (SPI1_MEM_FLASH_PES_V << SPI1_MEM_FLASH_PES_S) +#define SPI1_MEM_FLASH_PES_V 0x00000001U +#define SPI1_MEM_FLASH_PES_S 1 +/** SPI1_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ +#define SPI1_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI1_MEM_FLASH_PER_WAIT_EN_M (SPI1_MEM_FLASH_PER_WAIT_EN_V << SPI1_MEM_FLASH_PER_WAIT_EN_S) +#define SPI1_MEM_FLASH_PER_WAIT_EN_V 0x00000001U +#define SPI1_MEM_FLASH_PER_WAIT_EN_S 2 +/** SPI1_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ +#define SPI1_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI1_MEM_FLASH_PES_WAIT_EN_M (SPI1_MEM_FLASH_PES_WAIT_EN_V << SPI1_MEM_FLASH_PES_WAIT_EN_S) +#define SPI1_MEM_FLASH_PES_WAIT_EN_V 0x00000001U +#define SPI1_MEM_FLASH_PES_WAIT_EN_S 3 +/** SPI1_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ +#define SPI1_MEM_PES_PER_EN (BIT(4)) +#define SPI1_MEM_PES_PER_EN_M (SPI1_MEM_PES_PER_EN_V << SPI1_MEM_PES_PER_EN_S) +#define SPI1_MEM_PES_PER_EN_V 0x00000001U +#define SPI1_MEM_PES_PER_EN_S 4 +/** SPI1_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ +#define SPI1_MEM_FLASH_PES_EN (BIT(5)) +#define SPI1_MEM_FLASH_PES_EN_M (SPI1_MEM_FLASH_PES_EN_V << SPI1_MEM_FLASH_PES_EN_S) +#define SPI1_MEM_FLASH_PES_EN_V 0x00000001U +#define SPI1_MEM_FLASH_PES_EN_S 5 +/** SPI1_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_PESR_END_MSK[15:0]. + */ +#define SPI1_MEM_PESR_END_MSK 0x0000FFFFU +#define SPI1_MEM_PESR_END_MSK_M (SPI1_MEM_PESR_END_MSK_V << SPI1_MEM_PESR_END_MSK_S) +#define SPI1_MEM_PESR_END_MSK_V 0x0000FFFFU +#define SPI1_MEM_PESR_END_MSK_S 6 +/** SPI1_MEM_F_RD_SUS_2B : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ +#define SPI1_MEM_F_RD_SUS_2B (BIT(22)) +#define SPI1_MEM_F_RD_SUS_2B_M (SPI1_MEM_F_RD_SUS_2B_V << SPI1_MEM_F_RD_SUS_2B_S) +#define SPI1_MEM_F_RD_SUS_2B_V 0x00000001U +#define SPI1_MEM_F_RD_SUS_2B_S 22 +/** SPI1_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_PER_END_EN (BIT(23)) +#define SPI1_MEM_PER_END_EN_M (SPI1_MEM_PER_END_EN_V << SPI1_MEM_PER_END_EN_S) +#define SPI1_MEM_PER_END_EN_V 0x00000001U +#define SPI1_MEM_PER_END_EN_S 23 +/** SPI1_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_PES_END_EN (BIT(24)) +#define SPI1_MEM_PES_END_EN_M (SPI1_MEM_PES_END_EN_V << SPI1_MEM_PES_END_EN_S) +#define SPI1_MEM_PES_END_EN_V 0x00000001U +#define SPI1_MEM_PES_END_EN_S 24 +/** SPI1_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. + */ +#define SPI1_MEM_SUS_TIMEOUT_CNT 0x0000007FU +#define SPI1_MEM_SUS_TIMEOUT_CNT_M (SPI1_MEM_SUS_TIMEOUT_CNT_V << SPI1_MEM_SUS_TIMEOUT_CNT_S) +#define SPI1_MEM_SUS_TIMEOUT_CNT_V 0x0000007FU +#define SPI1_MEM_SUS_TIMEOUT_CNT_S 25 + +/** SPI1_MEM_FLASH_SUS_CMD_REG register + * SPI1 flash suspend command register + */ +#define SPI1_MEM_FLASH_SUS_CMD_REG (DR_REG_SPIMEM1_BASE + 0xa0) +/** SPI1_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ +#define SPI1_MEM_FLASH_PES_COMMAND 0x0000FFFFU +#define SPI1_MEM_FLASH_PES_COMMAND_M (SPI1_MEM_FLASH_PES_COMMAND_V << SPI1_MEM_FLASH_PES_COMMAND_S) +#define SPI1_MEM_FLASH_PES_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_FLASH_PES_COMMAND_S 0 +/** SPI1_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ +#define SPI1_MEM_WAIT_PESR_COMMAND 0x0000FFFFU +#define SPI1_MEM_WAIT_PESR_COMMAND_M (SPI1_MEM_WAIT_PESR_COMMAND_V << SPI1_MEM_WAIT_PESR_COMMAND_S) +#define SPI1_MEM_WAIT_PESR_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_WAIT_PESR_COMMAND_S 16 + +/** SPI1_MEM_SUS_STATUS_REG register + * SPI1 flash suspend status register + */ +#define SPI1_MEM_SUS_STATUS_REG (DR_REG_SPIMEM1_BASE + 0xa4) +/** SPI1_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ +#define SPI1_MEM_FLASH_SUS (BIT(0)) +#define SPI1_MEM_FLASH_SUS_M (SPI1_MEM_FLASH_SUS_V << SPI1_MEM_FLASH_SUS_S) +#define SPI1_MEM_FLASH_SUS_V 0x00000001U +#define SPI1_MEM_FLASH_SUS_S 0 +/** SPI1_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ +#define SPI1_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI1_MEM_WAIT_PESR_CMD_2B_M (SPI1_MEM_WAIT_PESR_CMD_2B_V << SPI1_MEM_WAIT_PESR_CMD_2B_S) +#define SPI1_MEM_WAIT_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_WAIT_PESR_CMD_2B_S 1 +/** SPI1_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ +#define SPI1_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI1_MEM_FLASH_HPM_DLY_128_M (SPI1_MEM_FLASH_HPM_DLY_128_V << SPI1_MEM_FLASH_HPM_DLY_128_S) +#define SPI1_MEM_FLASH_HPM_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_HPM_DLY_128_S 2 +/** SPI1_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ +#define SPI1_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI1_MEM_FLASH_RES_DLY_128_M (SPI1_MEM_FLASH_RES_DLY_128_V << SPI1_MEM_FLASH_RES_DLY_128_S) +#define SPI1_MEM_FLASH_RES_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_RES_DLY_128_S 3 +/** SPI1_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ +#define SPI1_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI1_MEM_FLASH_DP_DLY_128_M (SPI1_MEM_FLASH_DP_DLY_128_V << SPI1_MEM_FLASH_DP_DLY_128_S) +#define SPI1_MEM_FLASH_DP_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_DP_DLY_128_S 4 +/** SPI1_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. + */ +#define SPI1_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI1_MEM_FLASH_PER_DLY_128_M (SPI1_MEM_FLASH_PER_DLY_128_V << SPI1_MEM_FLASH_PER_DLY_128_S) +#define SPI1_MEM_FLASH_PER_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_PER_DLY_128_S 5 +/** SPI1_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. + */ +#define SPI1_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI1_MEM_FLASH_PES_DLY_128_M (SPI1_MEM_FLASH_PES_DLY_128_V << SPI1_MEM_FLASH_PES_DLY_128_S) +#define SPI1_MEM_FLASH_PES_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_PES_DLY_128_S 6 +/** SPI1_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ +#define SPI1_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI1_MEM_SPI0_LOCK_EN_M (SPI1_MEM_SPI0_LOCK_EN_V << SPI1_MEM_SPI0_LOCK_EN_S) +#define SPI1_MEM_SPI0_LOCK_EN_V 0x00000001U +#define SPI1_MEM_SPI0_LOCK_EN_S 7 +/** SPI1_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ +#define SPI1_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI1_MEM_FLASH_PESR_CMD_2B_M (SPI1_MEM_FLASH_PESR_CMD_2B_V << SPI1_MEM_FLASH_PESR_CMD_2B_S) +#define SPI1_MEM_FLASH_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_FLASH_PESR_CMD_2B_S 15 +/** SPI1_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ +#define SPI1_MEM_FLASH_PER_COMMAND 0x0000FFFFU +#define SPI1_MEM_FLASH_PER_COMMAND_M (SPI1_MEM_FLASH_PER_COMMAND_V << SPI1_MEM_FLASH_PER_COMMAND_S) +#define SPI1_MEM_FLASH_PER_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_FLASH_PER_COMMAND_S 16 + +/** SPI1_MEM_INT_ENA_REG register + * SPI1 interrupt enable register + */ +#define SPI1_MEM_INT_ENA_REG (DR_REG_SPIMEM1_BASE + 0xc0) +/** SPI1_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_PER_END_INT interrupt. + */ +#define SPI1_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI1_MEM_PER_END_INT_ENA_M (SPI1_MEM_PER_END_INT_ENA_V << SPI1_MEM_PER_END_INT_ENA_S) +#define SPI1_MEM_PER_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_PER_END_INT_ENA_S 0 +/** SPI1_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_PES_END_INT interrupt. + */ +#define SPI1_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI1_MEM_PES_END_INT_ENA_M (SPI1_MEM_PES_END_INT_ENA_V << SPI1_MEM_PES_END_INT_ENA_S) +#define SPI1_MEM_PES_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_PES_END_INT_ENA_S 1 +/** SPI1_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_WPE_END_INT interrupt. + */ +#define SPI1_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI1_MEM_WPE_END_INT_ENA_M (SPI1_MEM_WPE_END_INT_ENA_V << SPI1_MEM_WPE_END_INT_ENA_S) +#define SPI1_MEM_WPE_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_ENA_S 2 +/** SPI1_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_ENA_M (SPI1_MEM_SLV_ST_END_INT_ENA_V << SPI1_MEM_SLV_ST_END_INT_ENA_S) +#define SPI1_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI1_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_ENA_M (SPI1_MEM_MST_ST_END_INT_ENA_V << SPI1_MEM_MST_ST_END_INT_ENA_S) +#define SPI1_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI1_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_ENA_M (SPI1_MEM_BROWN_OUT_INT_ENA_V << SPI1_MEM_BROWN_OUT_INT_ENA_S) +#define SPI1_MEM_BROWN_OUT_INT_ENA_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_ENA_S 10 + +/** SPI1_MEM_INT_CLR_REG register + * SPI1 interrupt clear register + */ +#define SPI1_MEM_INT_CLR_REG (DR_REG_SPIMEM1_BASE + 0xc4) +/** SPI1_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_PER_END_INT interrupt. + */ +#define SPI1_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI1_MEM_PER_END_INT_CLR_M (SPI1_MEM_PER_END_INT_CLR_V << SPI1_MEM_PER_END_INT_CLR_S) +#define SPI1_MEM_PER_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_PER_END_INT_CLR_S 0 +/** SPI1_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_PES_END_INT interrupt. + */ +#define SPI1_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI1_MEM_PES_END_INT_CLR_M (SPI1_MEM_PES_END_INT_CLR_V << SPI1_MEM_PES_END_INT_CLR_S) +#define SPI1_MEM_PES_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_PES_END_INT_CLR_S 1 +/** SPI1_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_WPE_END_INT interrupt. + */ +#define SPI1_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI1_MEM_WPE_END_INT_CLR_M (SPI1_MEM_WPE_END_INT_CLR_V << SPI1_MEM_WPE_END_INT_CLR_S) +#define SPI1_MEM_WPE_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_CLR_S 2 +/** SPI1_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_CLR_M (SPI1_MEM_SLV_ST_END_INT_CLR_V << SPI1_MEM_SLV_ST_END_INT_CLR_S) +#define SPI1_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI1_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_CLR_M (SPI1_MEM_MST_ST_END_INT_CLR_V << SPI1_MEM_MST_ST_END_INT_CLR_S) +#define SPI1_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI1_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_CLR_M (SPI1_MEM_BROWN_OUT_INT_CLR_V << SPI1_MEM_BROWN_OUT_INT_CLR_S) +#define SPI1_MEM_BROWN_OUT_INT_CLR_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_CLR_S 10 + +/** SPI1_MEM_INT_RAW_REG register + * SPI1 interrupt raw register + */ +#define SPI1_MEM_INT_RAW_REG (DR_REG_SPIMEM1_BASE + 0xc8) +/** SPI1_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ +#define SPI1_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI1_MEM_PER_END_INT_RAW_M (SPI1_MEM_PER_END_INT_RAW_V << SPI1_MEM_PER_END_INT_RAW_S) +#define SPI1_MEM_PER_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_PER_END_INT_RAW_S 0 +/** SPI1_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ +#define SPI1_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI1_MEM_PES_END_INT_RAW_M (SPI1_MEM_PES_END_INT_RAW_V << SPI1_MEM_PES_END_INT_RAW_S) +#define SPI1_MEM_PES_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_PES_END_INT_RAW_S 1 +/** SPI1_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ +#define SPI1_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI1_MEM_WPE_END_INT_RAW_M (SPI1_MEM_WPE_END_INT_RAW_V << SPI1_MEM_WPE_END_INT_RAW_S) +#define SPI1_MEM_WPE_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_RAW_S 2 +/** SPI1_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI1_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_RAW_M (SPI1_MEM_SLV_ST_END_INT_RAW_V << SPI1_MEM_SLV_ST_END_INT_RAW_S) +#define SPI1_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI1_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI1_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_RAW_M (SPI1_MEM_MST_ST_END_INT_RAW_V << SPI1_MEM_MST_ST_END_INT_RAW_S) +#define SPI1_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI1_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is loosing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ +#define SPI1_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_RAW_M (SPI1_MEM_BROWN_OUT_INT_RAW_V << SPI1_MEM_BROWN_OUT_INT_RAW_S) +#define SPI1_MEM_BROWN_OUT_INT_RAW_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_RAW_S 10 + +/** SPI1_MEM_INT_ST_REG register + * SPI1 interrupt status register + */ +#define SPI1_MEM_INT_ST_REG (DR_REG_SPIMEM1_BASE + 0xcc) +/** SPI1_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_PER_END_INT interrupt. + */ +#define SPI1_MEM_PER_END_INT_ST (BIT(0)) +#define SPI1_MEM_PER_END_INT_ST_M (SPI1_MEM_PER_END_INT_ST_V << SPI1_MEM_PER_END_INT_ST_S) +#define SPI1_MEM_PER_END_INT_ST_V 0x00000001U +#define SPI1_MEM_PER_END_INT_ST_S 0 +/** SPI1_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_PES_END_INT interrupt. + */ +#define SPI1_MEM_PES_END_INT_ST (BIT(1)) +#define SPI1_MEM_PES_END_INT_ST_M (SPI1_MEM_PES_END_INT_ST_V << SPI1_MEM_PES_END_INT_ST_S) +#define SPI1_MEM_PES_END_INT_ST_V 0x00000001U +#define SPI1_MEM_PES_END_INT_ST_S 1 +/** SPI1_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_WPE_END_INT interrupt. + */ +#define SPI1_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI1_MEM_WPE_END_INT_ST_M (SPI1_MEM_WPE_END_INT_ST_V << SPI1_MEM_WPE_END_INT_ST_S) +#define SPI1_MEM_WPE_END_INT_ST_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_ST_S 2 +/** SPI1_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_ST_M (SPI1_MEM_SLV_ST_END_INT_ST_V << SPI1_MEM_SLV_ST_END_INT_ST_S) +#define SPI1_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI1_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_ST_M (SPI1_MEM_MST_ST_END_INT_ST_V << SPI1_MEM_MST_ST_END_INT_ST_S) +#define SPI1_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_ST_S 4 +/** SPI1_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_ST_M (SPI1_MEM_BROWN_OUT_INT_ST_V << SPI1_MEM_BROWN_OUT_INT_ST_S) +#define SPI1_MEM_BROWN_OUT_INT_ST_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_ST_S 10 + +/** SPI1_MEM_DDR_REG register + * SPI1 DDR control register + */ +#define SPI1_MEM_DDR_REG (DR_REG_SPIMEM1_BASE + 0xd4) +/** SPI1_MEM_F_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ +#define SPI1_MEM_F_DDR_EN (BIT(0)) +#define SPI1_MEM_F_DDR_EN_M (SPI1_MEM_F_DDR_EN_V << SPI1_MEM_F_DDR_EN_S) +#define SPI1_MEM_F_DDR_EN_V 0x00000001U +#define SPI1_MEM_F_DDR_EN_S 0 +/** SPI1_MEM_F_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ +#define SPI1_MEM_F_VAR_DUMMY (BIT(1)) +#define SPI1_MEM_F_VAR_DUMMY_M (SPI1_MEM_F_VAR_DUMMY_V << SPI1_MEM_F_VAR_DUMMY_S) +#define SPI1_MEM_F_VAR_DUMMY_V 0x00000001U +#define SPI1_MEM_F_VAR_DUMMY_S 1 +/** SPI1_MEM_F_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ +#define SPI1_MEM_F_DDR_RDAT_SWP (BIT(2)) +#define SPI1_MEM_F_DDR_RDAT_SWP_M (SPI1_MEM_F_DDR_RDAT_SWP_V << SPI1_MEM_F_DDR_RDAT_SWP_S) +#define SPI1_MEM_F_DDR_RDAT_SWP_V 0x00000001U +#define SPI1_MEM_F_DDR_RDAT_SWP_S 2 +/** SPI1_MEM_F_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ +#define SPI1_MEM_F_DDR_WDAT_SWP (BIT(3)) +#define SPI1_MEM_F_DDR_WDAT_SWP_M (SPI1_MEM_F_DDR_WDAT_SWP_V << SPI1_MEM_F_DDR_WDAT_SWP_S) +#define SPI1_MEM_F_DDR_WDAT_SWP_V 0x00000001U +#define SPI1_MEM_F_DDR_WDAT_SWP_S 3 +/** SPI1_MEM_F_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ +#define SPI1_MEM_F_DDR_CMD_DIS (BIT(4)) +#define SPI1_MEM_F_DDR_CMD_DIS_M (SPI1_MEM_F_DDR_CMD_DIS_V << SPI1_MEM_F_DDR_CMD_DIS_S) +#define SPI1_MEM_F_DDR_CMD_DIS_V 0x00000001U +#define SPI1_MEM_F_DDR_CMD_DIS_S 4 +/** SPI1_MEM_F_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI1_MEM_F_OUTMINBYTELEN 0x0000007FU +#define SPI1_MEM_F_OUTMINBYTELEN_M (SPI1_MEM_F_OUTMINBYTELEN_V << SPI1_MEM_F_OUTMINBYTELEN_S) +#define SPI1_MEM_F_OUTMINBYTELEN_V 0x0000007FU +#define SPI1_MEM_F_OUTMINBYTELEN_S 5 +/** SPI1_MEM_F_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI1_MEM_F_USR_DDR_DQS_THD 0x0000007FU +#define SPI1_MEM_F_USR_DDR_DQS_THD_M (SPI1_MEM_F_USR_DDR_DQS_THD_V << SPI1_MEM_F_USR_DDR_DQS_THD_S) +#define SPI1_MEM_F_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI1_MEM_F_USR_DDR_DQS_THD_S 14 +/** SPI1_MEM_F_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI1_MEM_F_DDR_DQS_LOOP (BIT(21)) +#define SPI1_MEM_F_DDR_DQS_LOOP_M (SPI1_MEM_F_DDR_DQS_LOOP_V << SPI1_MEM_F_DDR_DQS_LOOP_S) +#define SPI1_MEM_F_DDR_DQS_LOOP_V 0x00000001U +#define SPI1_MEM_F_DDR_DQS_LOOP_S 21 +/** SPI1_MEM_F_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI1_MEM_F_CLK_DIFF_EN (BIT(24)) +#define SPI1_MEM_F_CLK_DIFF_EN_M (SPI1_MEM_F_CLK_DIFF_EN_V << SPI1_MEM_F_CLK_DIFF_EN_S) +#define SPI1_MEM_F_CLK_DIFF_EN_V 0x00000001U +#define SPI1_MEM_F_CLK_DIFF_EN_S 24 +/** SPI1_MEM_F_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI1_MEM_F_DQS_CA_IN (BIT(26)) +#define SPI1_MEM_F_DQS_CA_IN_M (SPI1_MEM_F_DQS_CA_IN_V << SPI1_MEM_F_DQS_CA_IN_S) +#define SPI1_MEM_F_DQS_CA_IN_V 0x00000001U +#define SPI1_MEM_F_DQS_CA_IN_S 26 +/** SPI1_MEM_F_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_M (SPI1_MEM_F_HYPERBUS_DUMMY_2X_V << SPI1_MEM_F_HYPERBUS_DUMMY_2X_S) +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_S 27 +/** SPI1_MEM_F_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI1_MEM_F_CLK_DIFF_INV (BIT(28)) +#define SPI1_MEM_F_CLK_DIFF_INV_M (SPI1_MEM_F_CLK_DIFF_INV_V << SPI1_MEM_F_CLK_DIFF_INV_S) +#define SPI1_MEM_F_CLK_DIFF_INV_V 0x00000001U +#define SPI1_MEM_F_CLK_DIFF_INV_S 28 +/** SPI1_MEM_F_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI1_MEM_F_OCTA_RAM_ADDR (BIT(29)) +#define SPI1_MEM_F_OCTA_RAM_ADDR_M (SPI1_MEM_F_OCTA_RAM_ADDR_V << SPI1_MEM_F_OCTA_RAM_ADDR_S) +#define SPI1_MEM_F_OCTA_RAM_ADDR_V 0x00000001U +#define SPI1_MEM_F_OCTA_RAM_ADDR_S 29 +/** SPI1_MEM_F_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI1_MEM_F_HYPERBUS_CA (BIT(30)) +#define SPI1_MEM_F_HYPERBUS_CA_M (SPI1_MEM_F_HYPERBUS_CA_V << SPI1_MEM_F_HYPERBUS_CA_S) +#define SPI1_MEM_F_HYPERBUS_CA_V 0x00000001U +#define SPI1_MEM_F_HYPERBUS_CA_S 30 + +/** SPI1_MEM_TIMING_CALI_REG register + * SPI1 timing control register + */ +#define SPI1_MEM_TIMING_CALI_REG (DR_REG_SPIMEM1_BASE + 0x180) +/** SPI1_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI1_MEM_TIMING_CALI (BIT(1)) +#define SPI1_MEM_TIMING_CALI_M (SPI1_MEM_TIMING_CALI_V << SPI1_MEM_TIMING_CALI_S) +#define SPI1_MEM_TIMING_CALI_V 0x00000001U +#define SPI1_MEM_TIMING_CALI_S 1 +/** SPI1_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI1_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/** SPI1_MEM_CLOCK_GATE_REG register + * SPI1 clk_gate register + */ +#define SPI1_MEM_CLOCK_GATE_REG (DR_REG_SPIMEM1_BASE + 0x200) +/** SPI1_MEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI1_MEM_CLK_EN (BIT(0)) +#define SPI1_MEM_CLK_EN_M (SPI1_MEM_CLK_EN_V << SPI1_MEM_CLK_EN_S) +#define SPI1_MEM_CLK_EN_V 0x00000001U +#define SPI1_MEM_CLK_EN_S 0 + +/** SPI1_MEM_DATE_REG register + * Version control register + */ +#define SPI1_MEM_DATE_REG (DR_REG_SPIMEM1_BASE + 0x3fc) +/** SPI1_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128; + * Version control register + */ +#define SPI1_MEM_DATE 0x0FFFFFFFU +#define SPI1_MEM_DATE_M (SPI1_MEM_DATE_V << SPI1_MEM_DATE_S) +#define SPI1_MEM_DATE_V 0x0FFFFFFFU +#define SPI1_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/include/soc/spi1_mem_struct.h new file mode 100644 index 00000000000..b4e6306ec2f --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi1_mem_struct.h @@ -0,0 +1,1083 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * SPI1 memory command register + */ +typedef union { + struct { + /** mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t slv_st:4; + uint32_t reserved_8:10; + /** usr : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi1_mem_cmd_reg_t; + +/** Type of addr register + * SPI1 address register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi1_mem_addr_reg_t; + +/** Type of user register + * SPI1 user register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + uint32_t fwrite_quad:1; + /** fwrite_dio : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ + uint32_t fwrite_dio:1; + /** fwrite_qio : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ + uint32_t fwrite_qio:1; + uint32_t reserved_16:10; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi1_mem_user_reg_t; + +/** Type of user1 register + * SPI1 user1 register. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t usr_dummy_cyclelen:6; + uint32_t reserved_6:20; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t usr_addr_bitlen:6; + }; + uint32_t val; +} spi1_mem_user1_reg_t; + +/** Type of user2 register + * SPI1 user2 register. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi1_mem_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI1 control register. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_wout:1; + /** fdout_oct : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t fdout_oct:1; + /** fdin_oct : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t fdin_oct:1; + /** faddr_oct : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t faddr_oct:1; + uint32_t reserved_7:1; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_oct:1; + uint32_t reserved_10:3; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. + */ + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t fread_dual:1; + uint32_t reserved_15:3; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t wp_reg:1; + uint32_t reserved_22:1; + /** fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t fread_qio:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi1_mem_ctrl_reg_t; + +/** Type of ctrl1 register + * SPI1 control1 register. + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ + uint32_t clk_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi1_mem_ctrl1_reg_t; + +/** Type of ctrl2 register + * SPI1 control2 register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sync_reset : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ + uint32_t sync_reset:1; + }; + uint32_t val; +} spi1_mem_ctrl2_reg_t; + +/** Type of clock register + * SPI1 clock division control register. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ + uint32_t clkcnt_n:8; + uint32_t reserved_24:7; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi1_mem_clock_reg_t; + +/** Type of mosi_dlen register + * SPI1 send data bit length control register. + */ +typedef union { + struct { + /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + uint32_t usr_mosi_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_mosi_dlen_reg_t; + +/** Type of miso_dlen register + * SPI1 receive data bit length control register. + */ +typedef union { + struct { + /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + uint32_t usr_miso_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_miso_dlen_reg_t; + +/** Type of rd_status register + * SPI1 status register. + */ +typedef union { + struct { + /** status : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + */ + uint32_t status:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi1_mem_rd_status_reg_t; + +/** Type of misc register + * SPI1 misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs1_dis:1; + uint32_t reserved_2:7; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ + uint32_t cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_misc_reg_t; + +/** Type of flash_waiti_ctrl register + * SPI1 wait idle control register + */ +typedef union { + struct { + /** waiti_en : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ + uint32_t waiti_en:1; + /** waiti_dummy : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ + uint32_t waiti_dummy:1; + /** waiti_addr_en : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ + uint32_t waiti_addr_en:1; + /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_WAITI_ADDR_EN is cleared. + */ + uint32_t waiti_addr_cyclelen:2; + uint32_t reserved_5:4; + /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ + uint32_t waiti_cmd_2b:1; + /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ + uint32_t waiti_dummy_cyclelen:6; + /** waiti_cmd : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ + uint32_t waiti_cmd:16; + }; + uint32_t val; +} spi1_mem_flash_waiti_ctrl_reg_t; + +/** Type of flash_sus_ctrl register + * SPI1 flash suspend control register + */ +typedef union { + struct { + /** flash_per : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_per:1; + /** flash_pes : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_pes:1; + /** flash_per_wait_en : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ + uint32_t flash_per_wait_en:1; + /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ + uint32_t flash_pes_wait_en:1; + /** pes_per_en : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ + uint32_t pes_per_en:1; + /** flash_pes_en : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ + uint32_t flash_pes_en:1; + /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_PESR_END_MSK[15:0]. + */ + uint32_t pesr_end_msk:16; + /** f_rd_sus_2b : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ + uint32_t f_rd_sus_2b:1; + /** per_end_en : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ + uint32_t per_end_en:1; + /** pes_end_en : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ + uint32_t pes_end_en:1; + /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. + */ + uint32_t sus_timeout_cnt:7; + }; + uint32_t val; +} spi1_mem_flash_sus_ctrl_reg_t; + +/** Type of flash_sus_cmd register + * SPI1 flash suspend command register + */ +typedef union { + struct { + /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ + uint32_t flash_pes_command:16; + /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ + uint32_t wait_pesr_command:16; + }; + uint32_t val; +} spi1_mem_flash_sus_cmd_reg_t; + +/** Type of sus_status register + * SPI1 flash suspend status register + */ +typedef union { + struct { + /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ + uint32_t flash_sus:1; + /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ + uint32_t wait_pesr_cmd_2b:1; + /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ + uint32_t flash_hpm_dly_128:1; + /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ + uint32_t flash_res_dly_128:1; + /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ + uint32_t flash_dp_dly_128:1; + /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. + */ + uint32_t flash_per_dly_128:1; + /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. + */ + uint32_t flash_pes_dly_128:1; + /** spi0_lock_en : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ + uint32_t spi0_lock_en:1; + uint32_t reserved_8:7; + /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ + uint32_t flash_pesr_cmd_2b:1; + /** flash_per_command : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ + uint32_t flash_per_command:16; + }; + uint32_t val; +} spi1_mem_sus_status_reg_t; + +/** Type of ddr register + * SPI1 DDR control register + */ +typedef union { + struct { + /** f_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ + uint32_t f_ddr_en:1; + /** f_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ + uint32_t f_var_dummy:1; + /** f_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ + uint32_t f_ddr_rdat_swp:1; + /** f_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ + uint32_t f_ddr_wdat_swp:1; + /** f_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ + uint32_t f_ddr_cmd_dis:1; + /** f_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t f_outminbytelen:7; + uint32_t reserved_12:2; + /** f_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t f_usr_ddr_dqs_thd:7; + /** f_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t f_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** f_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t f_clk_diff_en:1; + uint32_t reserved_25:1; + /** f_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t f_dqs_ca_in:1; + /** f_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t f_hyperbus_dummy_2x:1; + /** f_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t f_clk_diff_inv:1; + /** f_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t f_octa_ram_addr:1; + /** f_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t f_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi1_mem_ddr_reg_t; + +/** Type of clock_gate register + * SPI1 clk_gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi1_mem_clock_gate_reg_t; + + +/** Group: Memory data buffer register */ +/** Type of wn register + * SPI1 memory data buffer n + */ +typedef union { + struct { + /** buf : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf:32; + }; + uint32_t val; +} spi1_mem_wn_reg_t; + +/** Type of w1 register + * SPI1 memory data buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi1_mem_w1_reg_t; + +/** Type of w2 register + * SPI1 memory data buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi1_mem_w2_reg_t; + +/** Type of w3 register + * SPI1 memory data buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi1_mem_w3_reg_t; + +/** Type of w4 register + * SPI1 memory data buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi1_mem_w4_reg_t; + +/** Type of w5 register + * SPI1 memory data buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi1_mem_w5_reg_t; + +/** Type of w6 register + * SPI1 memory data buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi1_mem_w6_reg_t; + +/** Type of w7 register + * SPI1 memory data buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi1_mem_w7_reg_t; + +/** Type of w8 register + * SPI1 memory data buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi1_mem_w8_reg_t; + +/** Type of w9 register + * SPI1 memory data buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi1_mem_w9_reg_t; + +/** Type of w10 register + * SPI1 memory data buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi1_mem_w10_reg_t; + +/** Type of w11 register + * SPI1 memory data buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi1_mem_w11_reg_t; + +/** Type of w12 register + * SPI1 memory data buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi1_mem_w12_reg_t; + +/** Type of w13 register + * SPI1 memory data buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi1_mem_w13_reg_t; + +/** Type of w14 register + * SPI1 memory data buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi1_mem_w14_reg_t; + +/** Type of w15 register + * SPI1 memory data buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi1_mem_w15_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena register + * SPI1 interrupt enable register + */ +typedef union { + struct { + /** per_end_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_ena:1; + /** pes_end_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_ena:1; + /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_ena:1; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_ena:1; + uint32_t reserved_5:5; + /** brown_out_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_ena:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_ena_reg_t; + +/** Type of int_clr register + * SPI1 interrupt clear register + */ +typedef union { + struct { + /** per_end_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_clr:1; + /** pes_end_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_clr:1; + /** wpe_end_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_clr:1; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_clr:1; + uint32_t reserved_5:5; + /** brown_out_int_clr : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_clr:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_clr_reg_t; + +/** Type of int_raw register + * SPI1 interrupt raw register + */ +typedef union { + struct { + /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ + uint32_t per_end_int_raw:1; + /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ + uint32_t pes_end_int_raw:1; + /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ + uint32_t wpe_end_int_raw:1; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mst_st_end_int_raw:1; + uint32_t reserved_5:5; + /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is loosing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ + uint32_t brown_out_int_raw:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_raw_reg_t; + +/** Type of int_st register + * SPI1 interrupt status register + */ +typedef union { + struct { + /** per_end_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_st:1; + /** pes_end_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_st:1; + /** wpe_end_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_st:1; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_st:1; + uint32_t reserved_5:5; + /** brown_out_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_st:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_st_reg_t; + + +/** Group: Timing registers */ +/** Type of timing_cali register + * SPI1 timing control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t extra_dummy_cyclelen:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi1_mem_timing_cali_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35660128; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi1_mem_date_reg_t; + + +typedef struct spi1_mem_dev_t { + volatile spi1_mem_cmd_reg_t cmd; + volatile spi1_mem_addr_reg_t addr; + volatile spi1_mem_ctrl_reg_t ctrl; + volatile spi1_mem_ctrl1_reg_t ctrl1; + volatile spi1_mem_ctrl2_reg_t ctrl2; + volatile spi1_mem_clock_reg_t clock; + volatile spi1_mem_user_reg_t user; + volatile spi1_mem_user1_reg_t user1; + volatile spi1_mem_user2_reg_t user2; + volatile spi1_mem_mosi_dlen_reg_t mosi_dlen; + volatile spi1_mem_miso_dlen_reg_t miso_dlen; + volatile spi1_mem_rd_status_reg_t rd_status; + uint32_t reserved_030; + volatile spi1_mem_misc_reg_t misc; + uint32_t reserved_038[8]; + volatile spi1_mem_wn_reg_t data_buf[16]; + volatile spi1_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl; + volatile spi1_mem_flash_sus_ctrl_reg_t flash_sus_ctrl; + volatile spi1_mem_flash_sus_cmd_reg_t flash_sus_cmd; + volatile spi1_mem_sus_status_reg_t sus_status; + uint32_t reserved_0a8[6]; + volatile spi1_mem_int_ena_reg_t int_ena; + volatile spi1_mem_int_clr_reg_t int_clr; + volatile spi1_mem_int_raw_reg_t int_raw; + volatile spi1_mem_int_st_reg_t int_st; + uint32_t reserved_0d0; + volatile spi1_mem_ddr_reg_t ddr; + uint32_t reserved_0d8[42]; + volatile spi1_mem_timing_cali_reg_t timing_cali; + uint32_t reserved_184[31]; + volatile spi1_mem_clock_gate_reg_t clock_gate; + uint32_t reserved_204[126]; + volatile spi1_mem_date_reg_t date; +} spi1_mem_dev_t; + +extern spi1_mem_dev_t SPIMEM1; + +#ifndef __cplusplus +_Static_assert(sizeof(spi1_mem_dev_t) == 0x400, "Invalid size of spi1_mem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_mem_reg.h b/components/soc/esp32c5/include/soc/spi_mem_reg.h new file mode 100644 index 00000000000..57409856241 --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_mem_reg.h @@ -0,0 +1,2737 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_CMD_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_CMD_REG (DR_REG_SPIMEM0_BASE + 0x0) +/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ +#define SPI_MEM_MST_ST 0x0000000FU +#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) +#define SPI_MEM_MST_ST_V 0x0000000FU +#define SPI_MEM_MST_ST_S 0 +/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_SLV_ST 0x0000000FU +#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) +#define SPI_MEM_SLV_ST_V 0x0000000FU +#define SPI_MEM_SLV_ST_S 4 +/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) +#define SPI_MEM_USR_V 0x00000001U +#define SPI_MEM_USR_S 18 + +/** SPI_MEM_CTRL_REG register + * SPI0 control register. + */ +#define SPI_MEM_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x8) +/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) +#define SPI_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_FDUMMY_RIN_S 2 +/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) +#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_FDUMMY_WOUT_S 3 +/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) +#define SPI_MEM_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_FDOUT_OCT_S 4 +/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) +#define SPI_MEM_FDIN_OCT_V 0x00000001U +#define SPI_MEM_FDIN_OCT_S 5 +/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) +#define SPI_MEM_FADDR_OCT_V 0x00000001U +#define SPI_MEM_FADDR_OCT_S 6 +/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) +#define SPI_MEM_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_FCMD_QUAD_S 8 +/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) +#define SPI_MEM_FCMD_OCT_V 0x00000001U +#define SPI_MEM_FCMD_OCT_S 9 +/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) +#define SPI_MEM_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_FASTRD_MODE_S 13 +/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) +#define SPI_MEM_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_FREAD_DUAL_S 14 +/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) +#define SPI_MEM_Q_POL_V 0x00000001U +#define SPI_MEM_Q_POL_S 18 +/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) +#define SPI_MEM_D_POL_V 0x00000001U +#define SPI_MEM_D_POL_S 19 +/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) +#define SPI_MEM_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_FREAD_QUAD_S 20 +/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) +#define SPI_MEM_WP_REG_V 0x00000001U +#define SPI_MEM_WP_REG_S 21 +/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) +#define SPI_MEM_FREAD_DIO_V 0x00000001U +#define SPI_MEM_FREAD_DIO_S 23 +/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) +#define SPI_MEM_FREAD_QIO_V 0x00000001U +#define SPI_MEM_FREAD_QIO_S 24 +/** SPI_MEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_CTRL1_REG register + * SPI0 control1 register. + */ +#define SPI_MEM_CTRL1_REG (DR_REG_SPIMEM0_BASE + 0xc) +/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ +#define SPI_MEM_CLK_MODE 0x00000003U +#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) +#define SPI_MEM_CLK_MODE_V 0x00000003U +#define SPI_MEM_CLK_MODE_S 0 +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ +#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) +#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U +#define SPI_AXI_RDATA_BACK_FAST_S 23 +/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) +#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AR_SPLICE_EN_S 25 +/** SPI_MEM_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) +#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AW_SPLICE_EN_S 26 +/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) +#define SPI_MEM_RAM0_EN_V 0x00000001U +#define SPI_MEM_RAM0_EN_S 27 +/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) +#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_DUAL_RAM_EN_S 28 +/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) +#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_FAST_WRITE_EN_S 29 +/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) +#define SPI_MEM_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_RXFIFO_RST_S 30 +/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) +#define SPI_MEM_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_TXFIFO_RST_S 31 + +/** SPI_MEM_CTRL2_REG register + * SPI0 control2 register. + */ +#define SPI_MEM_CTRL2_REG (DR_REG_SPIMEM0_BASE + 0x10) +/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ +#define SPI_MEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) +#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_S 0 +/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ +#define SPI_MEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) +#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_S 5 +/** SPI_MEM_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) +#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) +#define SPI_MEM_SYNC_RESET_V 0x00000001U +#define SPI_MEM_SYNC_RESET_S 31 + +/** SPI_MEM_CLOCK_REG register + * SPI clock division control register. + */ +#define SPI_MEM_CLOCK_REG (DR_REG_SPIMEM0_BASE + 0x14) +/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_CLKCNT_L 0x000000FFU +#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) +#define SPI_MEM_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_CLKCNT_L_S 0 +/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_CLKCNT_H 0x000000FFU +#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) +#define SPI_MEM_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_CLKCNT_H_S 8 +/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_CLKCNT_N 0x000000FFU +#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) +#define SPI_MEM_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_CLKCNT_N_S 16 +/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_USER_REG register + * SPI0 user register. + */ +#define SPI_MEM_USER_REG (DR_REG_SPIMEM0_BASE + 0x18) +/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) +#define SPI_MEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_CS_HOLD_S 6 +/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) +#define SPI_MEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_CS_SETUP_S 7 +/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) +#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_CK_OUT_EDGE_S 9 +/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) +#define SPI_MEM_USR_DUMMY_V 0x00000001U +#define SPI_MEM_USR_DUMMY_S 29 + +/** SPI_MEM_USER1_REG register + * SPI0 user1 register. + */ +#define SPI_MEM_USER1_REG (DR_REG_SPIMEM0_BASE + 0x1c) +/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ +#define SPI_MEM_USR_DBYTELEN 0x00000007U +#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) +#define SPI_MEM_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_USR_DBYTELEN_S 6 +/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_USER2_REG register + * SPI0 user2 register. + */ +#define SPI_MEM_USER2_REG (DR_REG_SPIMEM0_BASE + 0x20) +/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) +#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_MISC_REG register + * SPI0 misc register + */ +#define SPI_MEM_MISC_REG (DR_REG_SPIMEM0_BASE + 0x34) +/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) +#define SPI_MEM_FSUB_PIN_V 0x00000001U +#define SPI_MEM_FSUB_PIN_S 7 +/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) +#define SPI_MEM_SSUB_PIN_V 0x00000001U +#define SPI_MEM_SSUB_PIN_S 8 +/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) +#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_CACHE_FCTRL_REG register + * SPI0 bit mode control register. + */ +#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPIMEM0_BASE + 0x3c) +/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ +#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ +#define SPI_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_CLOSE_AXI_INF_EN_S 31 + +/** SPI_MEM_SRAM_CMD_REG register + * SPI0 external RAM mode control register + */ +#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPIMEM0_BASE + 0x44) +/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ +#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ +#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_FSM_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_FSM_REG (DR_REG_SPIMEM0_BASE + 0x54) +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_S 7 + +/** SPI_MEM_INT_ENA_REG register + * SPI0 interrupt enable register + */ +#define SPI_MEM_INT_ENA_REG (DR_REG_SPIMEM0_BASE + 0xc0) +/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 + +/** SPI_MEM_INT_CLR_REG register + * SPI0 interrupt clear register + */ +#define SPI_MEM_INT_CLR_REG (DR_REG_SPIMEM0_BASE + 0xc4) +/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 + +/** SPI_MEM_INT_RAW_REG register + * SPI0 interrupt raw register + */ +#define SPI_MEM_INT_RAW_REG (DR_REG_SPIMEM0_BASE + 0xc8) +/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 + +/** SPI_MEM_INT_ST_REG register + * SPI0 interrupt status register + */ +#define SPI_MEM_INT_ST_REG (DR_REG_SPIMEM0_BASE + 0xcc) +/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 + +/** SPI_MEM_DDR_REG register + * SPI0 flash DDR mode control register + */ +#define SPI_MEM_DDR_REG (DR_REG_SPIMEM0_BASE + 0xd4) +/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) +#define SPI_FMEM_DDR_EN_V 0x00000001U +#define SPI_FMEM_DDR_EN_S 0 +/** SPI_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) +#define SPI_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_FMEM_VAR_DUMMY_S 1 +/** SPI_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) +#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) +#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) +#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_FMEM_DDR_CMD_DIS_S 4 +/** SPI_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) +#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_S 5 +/** SPI_FMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ +#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) +#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_TX_DDR_MSK_EN_S 12 +/** SPI_FMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ +#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) +#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_RX_DDR_MSK_EN_S 13 +/** SPI_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) +#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) +#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) +#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_EN_S 24 +/** SPI_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) +#define SPI_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_FMEM_DQS_CA_IN_S 26 +/** SPI_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) +#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_INV_S 28 +/** SPI_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) +#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) +#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_FMEM_HYPERBUS_CA_S 30 + +/** SPI_SMEM_DDR_REG register + * SPI0 external RAM DDR mode control register + */ +#define SPI_SMEM_DDR_REG (DR_REG_SPIMEM0_BASE + 0xd8) +/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) +#define SPI_SMEM_DDR_EN_V 0x00000001U +#define SPI_SMEM_DDR_EN_S 0 +/** SPI_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) +#define SPI_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_SMEM_VAR_DUMMY_S 1 +/** SPI_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) +#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) +#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) +#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_SMEM_DDR_CMD_DIS_S 4 +/** SPI_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ +#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) +#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_S 5 +/** SPI_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) +#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) +#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) +#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) +#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) +#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_EN_S 24 +/** SPI_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) +#define SPI_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_SMEM_DQS_CA_IN_S 26 +/** SPI_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ +#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) +#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_INV_S 28 +/** SPI_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ +#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) +#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) +#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_SMEM_HYPERBUS_CA_S 30 + +/** SPI_FMEM_PMS0_ATTR_REG register + * MSPI flash PMS section 0 attribute register + */ +#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x100) +/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) +#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_RD_ATTR_S 0 +/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) +#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_WR_ATTR_S 1 +/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and + * SPI_FMEM_PMS0_SIZE_REG. + */ +#define SPI_FMEM_PMS0_ECC (BIT(2)) +#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) +#define SPI_FMEM_PMS0_ECC_V 0x00000001U +#define SPI_FMEM_PMS0_ECC_S 2 + +/** SPI_FMEM_PMS1_ATTR_REG register + * MSPI flash PMS section 1 attribute register + */ +#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x104) +/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) +#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_RD_ATTR_S 0 +/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) +#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_WR_ATTR_S 1 +/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and + * SPI_FMEM_PMS1_SIZE_REG. + */ +#define SPI_FMEM_PMS1_ECC (BIT(2)) +#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) +#define SPI_FMEM_PMS1_ECC_V 0x00000001U +#define SPI_FMEM_PMS1_ECC_S 2 + +/** SPI_FMEM_PMS2_ATTR_REG register + * MSPI flash PMS section 2 attribute register + */ +#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x108) +/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) +#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_RD_ATTR_S 0 +/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) +#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_WR_ATTR_S 1 +/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and + * SPI_FMEM_PMS2_SIZE_REG. + */ +#define SPI_FMEM_PMS2_ECC (BIT(2)) +#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) +#define SPI_FMEM_PMS2_ECC_V 0x00000001U +#define SPI_FMEM_PMS2_ECC_S 2 + +/** SPI_FMEM_PMS3_ATTR_REG register + * MSPI flash PMS section 3 attribute register + */ +#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x10c) +/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) +#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_RD_ATTR_S 0 +/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) +#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_WR_ATTR_S 1 +/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and + * SPI_FMEM_PMS3_SIZE_REG. + */ +#define SPI_FMEM_PMS3_ECC (BIT(2)) +#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) +#define SPI_FMEM_PMS3_ECC_V 0x00000001U +#define SPI_FMEM_PMS3_ECC_S 2 + +/** SPI_FMEM_PMS0_ADDR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x110) +/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 0 start address value + */ +#define SPI_FMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) +#define SPI_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_S 0 + +/** SPI_FMEM_PMS1_ADDR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x114) +/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 1 start address value + */ +#define SPI_FMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) +#define SPI_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_S 0 + +/** SPI_FMEM_PMS2_ADDR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x118) +/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 2 start address value + */ +#define SPI_FMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) +#define SPI_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_S 0 + +/** SPI_FMEM_PMS3_ADDR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x11c) +/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 3 start address value + */ +#define SPI_FMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) +#define SPI_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_S 0 + +/** SPI_FMEM_PMS0_SIZE_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x120) +/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, + * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) + */ +#define SPI_FMEM_PMS0_SIZE 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) +#define SPI_FMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE_S 0 + +/** SPI_FMEM_PMS1_SIZE_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x124) +/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, + * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) + */ +#define SPI_FMEM_PMS1_SIZE 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) +#define SPI_FMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE_S 0 + +/** SPI_FMEM_PMS2_SIZE_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x128) +/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, + * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) + */ +#define SPI_FMEM_PMS2_SIZE 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) +#define SPI_FMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE_S 0 + +/** SPI_FMEM_PMS3_SIZE_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x12c) +/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, + * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) + */ +#define SPI_FMEM_PMS3_SIZE 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) +#define SPI_FMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE_S 0 + +/** SPI_SMEM_PMS0_ATTR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x130) +/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) +#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) +#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and + * SPI_SMEM_PMS0_SIZE_REG. + */ +#define SPI_SMEM_PMS0_ECC (BIT(2)) +#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) +#define SPI_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_SMEM_PMS0_ECC_S 2 + +/** SPI_SMEM_PMS1_ATTR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x134) +/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) +#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) +#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and + * SPI_SMEM_PMS1_SIZE_REG. + */ +#define SPI_SMEM_PMS1_ECC (BIT(2)) +#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) +#define SPI_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_SMEM_PMS1_ECC_S 2 + +/** SPI_SMEM_PMS2_ATTR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x138) +/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) +#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) +#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and + * SPI_SMEM_PMS2_SIZE_REG. + */ +#define SPI_SMEM_PMS2_ECC (BIT(2)) +#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) +#define SPI_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_SMEM_PMS2_ECC_S 2 + +/** SPI_SMEM_PMS3_ATTR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x13c) +/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) +#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) +#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and + * SPI_SMEM_PMS3_SIZE_REG. + */ +#define SPI_SMEM_PMS3_ECC (BIT(2)) +#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) +#define SPI_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_SMEM_PMS3_ECC_S 2 + +/** SPI_SMEM_PMS0_ADDR_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x140) +/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 0 start address value + */ +#define SPI_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) +#define SPI_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_S 0 + +/** SPI_SMEM_PMS1_ADDR_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x144) +/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value + */ +#define SPI_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) +#define SPI_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_S 0 + +/** SPI_SMEM_PMS2_ADDR_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x148) +/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value + */ +#define SPI_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) +#define SPI_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_S 0 + +/** SPI_SMEM_PMS3_ADDR_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x14c) +/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value + */ +#define SPI_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) +#define SPI_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_S 0 + +/** SPI_SMEM_PMS0_SIZE_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x150) +/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, + * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) + */ +#define SPI_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) +#define SPI_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE_S 0 + +/** SPI_SMEM_PMS1_SIZE_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x154) +/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, + * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) + */ +#define SPI_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) +#define SPI_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE_S 0 + +/** SPI_SMEM_PMS2_SIZE_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x158) +/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, + * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) + */ +#define SPI_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) +#define SPI_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE_S 0 + +/** SPI_SMEM_PMS3_SIZE_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x15c) +/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, + * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) + */ +#define SPI_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) +#define SPI_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_PMS_REJECT_REG register + * SPI1 access reject register + */ +#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPIMEM0_BASE + 0x164) +/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_REJECT_ADDR 0x07FFFFFFU +#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) +#define SPI_MEM_REJECT_ADDR_V 0x07FFFFFFU +#define SPI_MEM_REJECT_ADDR_S 0 +/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ +#define SPI_MEM_PM_EN (BIT(27)) +#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) +#define SPI_MEM_PM_EN_V 0x00000001U +#define SPI_MEM_PM_EN_S 27 +/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) +#define SPI_MEM_PMS_LD_V 0x00000001U +#define SPI_MEM_PMS_LD_S 28 +/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) +#define SPI_MEM_PMS_ST_V 0x00000001U +#define SPI_MEM_PMS_ST_S 29 +/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) +#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) +#define SPI_MEM_PMS_IVD_V 0x00000001U +#define SPI_MEM_PMS_IVD_S 31 + +/** SPI_MEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x168) +/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) +#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_S 5 +/** SPI_FMEM_ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) +#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 +/** SPI_FMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ +#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) +#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_FMEM_ECC_ERR_INT_EN_S 17 +/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ +#define SPI_FMEM_PAGE_SIZE 0x00000003U +#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) +#define SPI_FMEM_PAGE_SIZE_V 0x00000003U +#define SPI_FMEM_PAGE_SIZE_S 18 +/** SPI_FMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ +#define SPI_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) +#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_FMEM_ECC_ADDR_EN_S 20 +/** SPI_MEM_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_USR_ECC_ADDR_EN_S 21 +/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ +#define SPI_MEM_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) +#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_S 25 + +/** SPI_MEM_ECC_ERR_ADDR_REG register + * MSPI ECC error address register + */ +#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x16c) +/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) +#define SPI_MEM_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +/** SPI_MEM_AXI_ERR_ADDR_REG register + * SPI0 AXI request error address. + */ +#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x170) +/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ +#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) +#define SPI_MEM_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +/** SPI_SMEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x174) +/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ +#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) +#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ +#define SPI_SMEM_PAGE_SIZE 0x00000003U +#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) +#define SPI_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_SMEM_PAGE_SIZE_S 18 +/** SPI_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ +#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) +#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_SMEM_ECC_ADDR_EN_S 20 + +/** SPI_SMEM_AXI_ADDR_CTRL_REG register + * SPI0 AXI address control register + */ +#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x178) +/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 +/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) +#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_RDATA_AFIFO_REMPTY_S 27 +/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) +#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_RADDR_AFIFO_REMPTY_S 28 +/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) +#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_WDATA_AFIFO_REMPTY_S 29 +/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) +#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 + +/** SPI_MEM_AXI_ERR_RESP_EN_REG register + * SPI0 AXI error response enable register + */ +#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPIMEM0_BASE + 0x17c) +/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 + +/** SPI_MEM_TIMING_CALI_REG register + * SPI0 flash timing calibration register + */ +#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPIMEM0_BASE + 0x180) +/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) +#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) +#define SPI_MEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_TIMING_CALI_S 1 +/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) +#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 + +/** SPI_MEM_DIN_MODE_REG register + * MSPI flash input timing delay mode control register + */ +#define SPI_MEM_DIN_MODE_REG (DR_REG_SPIMEM0_BASE + 0x184) +/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN0_MODE 0x00000007U +#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) +#define SPI_MEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_DIN0_MODE_S 0 +/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN1_MODE 0x00000007U +#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) +#define SPI_MEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_DIN1_MODE_S 3 +/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN2_MODE 0x00000007U +#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) +#define SPI_MEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_DIN2_MODE_S 6 +/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN3_MODE 0x00000007U +#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) +#define SPI_MEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_DIN3_MODE_S 9 +/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN4_MODE 0x00000007U +#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) +#define SPI_MEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_DIN4_MODE_S 12 +/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN5_MODE 0x00000007U +#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) +#define SPI_MEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_DIN5_MODE_S 15 +/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN6_MODE 0x00000007U +#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) +#define SPI_MEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_DIN6_MODE_S 18 +/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN7_MODE 0x00000007U +#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) +#define SPI_MEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_DIN7_MODE_S 21 +/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DINS_MODE 0x00000007U +#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) +#define SPI_MEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_DINS_MODE_S 24 + +/** SPI_MEM_DIN_NUM_REG register + * MSPI flash input timing delay number control register + */ +#define SPI_MEM_DIN_NUM_REG (DR_REG_SPIMEM0_BASE + 0x188) +/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN0_NUM 0x00000003U +#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) +#define SPI_MEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_DIN0_NUM_S 0 +/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN1_NUM 0x00000003U +#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) +#define SPI_MEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_DIN1_NUM_S 2 +/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN2_NUM 0x00000003U +#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) +#define SPI_MEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_DIN2_NUM_S 4 +/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN3_NUM 0x00000003U +#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) +#define SPI_MEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_DIN3_NUM_S 6 +/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN4_NUM 0x00000003U +#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) +#define SPI_MEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_DIN4_NUM_S 8 +/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN5_NUM 0x00000003U +#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) +#define SPI_MEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_DIN5_NUM_S 10 +/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN6_NUM 0x00000003U +#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) +#define SPI_MEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_DIN6_NUM_S 12 +/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN7_NUM 0x00000003U +#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) +#define SPI_MEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_DIN7_NUM_S 14 +/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DINS_NUM 0x00000003U +#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) +#define SPI_MEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_DINS_NUM_S 16 + +/** SPI_MEM_DOUT_MODE_REG register + * MSPI flash output timing adjustment control register + */ +#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPIMEM0_BASE + 0x18c) +/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) +#define SPI_MEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_DOUT0_MODE_S 0 +/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) +#define SPI_MEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_DOUT1_MODE_S 1 +/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) +#define SPI_MEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_DOUT2_MODE_S 2 +/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) +#define SPI_MEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_DOUT3_MODE_S 3 +/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) +#define SPI_MEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_DOUT4_MODE_S 4 +/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) +#define SPI_MEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_DOUT5_MODE_S 5 +/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) +#define SPI_MEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_DOUT6_MODE_S 6 +/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) +#define SPI_MEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_DOUT7_MODE_S 7 +/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) +#define SPI_MEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_TIMING_CALI_REG register + * MSPI external RAM timing calibration register + */ +#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPIMEM0_BASE + 0x190) +/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) +#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ +#define SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) +#define SPI_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_TIMING_CALI_S 1 +/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ +#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) +#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_DLL_TIMING_CALI_S 5 + +/** SPI_SMEM_DIN_MODE_REG register + * MSPI external RAM input timing delay mode control register + */ +#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPIMEM0_BASE + 0x194) +/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN0_MODE 0x00000007U +#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) +#define SPI_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_SMEM_DIN0_MODE_S 0 +/** SPI_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN1_MODE 0x00000007U +#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) +#define SPI_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_SMEM_DIN1_MODE_S 3 +/** SPI_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN2_MODE 0x00000007U +#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) +#define SPI_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_SMEM_DIN2_MODE_S 6 +/** SPI_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN3_MODE 0x00000007U +#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) +#define SPI_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_SMEM_DIN3_MODE_S 9 +/** SPI_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN4_MODE 0x00000007U +#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) +#define SPI_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_SMEM_DIN4_MODE_S 12 +/** SPI_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN5_MODE 0x00000007U +#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) +#define SPI_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_SMEM_DIN5_MODE_S 15 +/** SPI_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN6_MODE 0x00000007U +#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) +#define SPI_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_SMEM_DIN6_MODE_S 18 +/** SPI_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN7_MODE 0x00000007U +#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) +#define SPI_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_SMEM_DIN7_MODE_S 21 +/** SPI_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DINS_MODE 0x00000007U +#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) +#define SPI_SMEM_DINS_MODE_V 0x00000007U +#define SPI_SMEM_DINS_MODE_S 24 + +/** SPI_SMEM_DIN_NUM_REG register + * MSPI external RAM input timing delay number control register + */ +#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPIMEM0_BASE + 0x198) +/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN0_NUM 0x00000003U +#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) +#define SPI_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_SMEM_DIN0_NUM_S 0 +/** SPI_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN1_NUM 0x00000003U +#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) +#define SPI_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_SMEM_DIN1_NUM_S 2 +/** SPI_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN2_NUM 0x00000003U +#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) +#define SPI_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_SMEM_DIN2_NUM_S 4 +/** SPI_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN3_NUM 0x00000003U +#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) +#define SPI_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_SMEM_DIN3_NUM_S 6 +/** SPI_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN4_NUM 0x00000003U +#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) +#define SPI_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_SMEM_DIN4_NUM_S 8 +/** SPI_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN5_NUM 0x00000003U +#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) +#define SPI_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_SMEM_DIN5_NUM_S 10 +/** SPI_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN6_NUM 0x00000003U +#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) +#define SPI_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_SMEM_DIN6_NUM_S 12 +/** SPI_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN7_NUM 0x00000003U +#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) +#define SPI_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_SMEM_DIN7_NUM_S 14 +/** SPI_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DINS_NUM 0x00000003U +#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) +#define SPI_SMEM_DINS_NUM_V 0x00000003U +#define SPI_SMEM_DINS_NUM_S 16 + +/** SPI_SMEM_DOUT_MODE_REG register + * MSPI external RAM output timing adjustment control register + */ +#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPIMEM0_BASE + 0x19c) +/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) +#define SPI_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_SMEM_DOUT0_MODE_S 0 +/** SPI_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) +#define SPI_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_SMEM_DOUT1_MODE_S 1 +/** SPI_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) +#define SPI_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_SMEM_DOUT2_MODE_S 2 +/** SPI_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) +#define SPI_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_SMEM_DOUT3_MODE_S 3 +/** SPI_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) +#define SPI_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_SMEM_DOUT4_MODE_S 4 +/** SPI_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) +#define SPI_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_SMEM_DOUT5_MODE_S 5 +/** SPI_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) +#define SPI_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_SMEM_DOUT6_MODE_S 6 +/** SPI_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) +#define SPI_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_SMEM_DOUT7_MODE_S 7 +/** SPI_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) +#define SPI_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_SMEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_AC_REG register + * MSPI external RAM ECC and SPI CS timing control register + */ +#define SPI_SMEM_AC_REG (DR_REG_SPIMEM0_BASE + 0x1a0) +/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ +#define SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) +#define SPI_SMEM_CS_SETUP_V 0x00000001U +#define SPI_SMEM_CS_SETUP_S 0 +/** SPI_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) +#define SPI_SMEM_CS_HOLD_V 0x00000001U +#define SPI_SMEM_CS_HOLD_S 1 +/** SPI_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ +#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) +#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_S 2 +/** SPI_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ +#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) +#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_S 7 +/** SPI_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ +#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ +#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) +#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ +#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) +#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_SMEM_SPLIT_TRANS_EN_S 31 + +/** SPI_MEM_CLOCK_GATE_REG register + * SPI0 clock gate register + */ +#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPIMEM0_BASE + 0x200) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 + +/** SPI_MEM_XTS_PLAIN_BASE_REG register + * The base address of the memory that stores plaintext in Manual Encryption + */ +#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPIMEM0_BASE + 0x300) +/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ +#define SPI_XTS_PLAIN 0xFFFFFFFFU +#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_XTS_PLAIN_S 0 + +/** SPI_MEM_XTS_LINESIZE_REG register + * Manual Encryption Line-Size register + */ +#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPIMEM0_BASE + 0x340) +/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ +#define SPI_XTS_LINESIZE 0x00000003U +#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_XTS_LINESIZE_V 0x00000003U +#define SPI_XTS_LINESIZE_S 0 + +/** SPI_MEM_XTS_DESTINATION_REG register + * Manual Encryption destination register + */ +#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPIMEM0_BASE + 0x344) +/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ +#define SPI_XTS_DESTINATION (BIT(0)) +#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_XTS_DESTINATION_V 0x00000001U +#define SPI_XTS_DESTINATION_S 0 + +/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPIMEM0_BASE + 0x348) +/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ +#define SPI_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) +#define SPI_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_S 0 + +/** SPI_MEM_XTS_TRIGGER_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPIMEM0_BASE + 0x34c) +/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ +#define SPI_XTS_TRIGGER (BIT(0)) +#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) +#define SPI_XTS_TRIGGER_V 0x00000001U +#define SPI_XTS_TRIGGER_S 0 + +/** SPI_MEM_XTS_RELEASE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPIMEM0_BASE + 0x350) +/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ +#define SPI_XTS_RELEASE (BIT(0)) +#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_XTS_RELEASE_V 0x00000001U +#define SPI_XTS_RELEASE_S 0 + +/** SPI_MEM_XTS_DESTROY_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPIMEM0_BASE + 0x354) +/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ +#define SPI_XTS_DESTROY (BIT(0)) +#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_XTS_DESTROY_V 0x00000001U +#define SPI_XTS_DESTROY_S 0 + +/** SPI_MEM_XTS_STATE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_STATE_REG (DR_REG_SPIMEM0_BASE + 0x358) +/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ +#define SPI_XTS_STATE 0x00000003U +#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_XTS_STATE_V 0x00000003U +#define SPI_XTS_STATE_S 0 + +/** SPI_MEM_XTS_DATE_REG register + * Manual Encryption version register + */ +#define SPI_MEM_XTS_DATE_REG (DR_REG_SPIMEM0_BASE + 0x35c) +/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ +#define SPI_XTS_DATE 0x3FFFFFFFU +#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_XTS_DATE_V 0x3FFFFFFFU +#define SPI_XTS_DATE_S 0 + +/** SPI_MEM_MMU_ITEM_CONTENT_REG register + * MSPI-MMU item content register + */ +#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPIMEM0_BASE + 0x37c) +/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ +#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_S 0 + +/** SPI_MEM_MMU_ITEM_INDEX_REG register + * MSPI-MMU item index register + */ +#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPIMEM0_BASE + 0x380) +/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ +#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_S 0 + +/** SPI_MEM_MMU_POWER_CTRL_REG register + * MSPI MMU power control register + */ +#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x384) +/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ +#define SPI_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MMU_MEM_FORCE_ON_S 0 +/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ +#define SPI_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PD_S 1 +/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ +#define SPI_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PU_S 2 +/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MMU_PAGE_SIZE 0x00000003U +#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MMU_PAGE_SIZE_S 3 +/** SPI_MEM_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ +#define SPI_MEM_AUX_CTRL 0x00003FFFU +#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) +#define SPI_MEM_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_AUX_CTRL_S 16 + +/** SPI_MEM_DPA_CTRL_REG register + * SPI memory cryption DPA register + */ +#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x388) +/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ +#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ +#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ +#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 + +/** SPI_MEM_DATE_REG register + * SPI0 version control register + */ +#define SPI_MEM_DATE_REG (DR_REG_SPIMEM0_BASE + 0x3fc) +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712560; + * SPI0 register version. + */ +#define SPI_MEM_DATE 0x0FFFFFFFU +#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) +#define SPI_MEM_DATE_V 0x0FFFFFFFU +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_mem_struct.h b/components/soc/esp32c5/include/soc/spi_mem_struct.h new file mode 100644 index 00000000000..08cd04f909a --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_mem_struct.h @@ -0,0 +1,2029 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status and state control register */ +/** Type of mem_cmd register + * SPI0 FSM status register + */ +typedef union { + struct { + /** mem_mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ + uint32_t mem_mst_st:4; + /** mem_slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t mem_slv_st:4; + uint32_t reserved_8:10; + /** mem_usr : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t mem_usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_cmd_reg_t; + +/** Type of mem_axi_err_addr register + * SPI0 AXI request error address. + */ +typedef union { + struct { + /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ + uint32_t mem_axi_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_axi_err_addr_reg_t; + + +/** Group: Flash Control and configuration registers */ +/** Type of mem_ctrl register + * SPI0 control register. + */ +typedef union { + struct { + /** mem_wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ + uint32_t mem_wdummy_dqs_always_out:1; + /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t mem_wdummy_always_out:1; + /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ + uint32_t mem_fdummy_rin:1; + /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ + uint32_t mem_fdummy_wout:1; + /** mem_fdout_oct : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t mem_fdout_oct:1; + /** mem_fdin_oct : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t mem_fdin_oct:1; + /** mem_faddr_oct : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t mem_faddr_oct:1; + uint32_t reserved_7:1; + /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_quad:1; + /** mem_fcmd_oct : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_oct:1; + uint32_t reserved_10:3; + /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ + uint32_t mem_fastrd_mode:1; + /** mem_fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_dual:1; + uint32_t reserved_15:3; + /** mem_q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t mem_q_pol:1; + /** mem_d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t mem_d_pol:1; + /** mem_fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_quad:1; + /** mem_wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t mem_wp_reg:1; + uint32_t reserved_22:1; + /** mem_fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_dio:1; + /** mem_fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_qio:1; + uint32_t reserved_25:5; + /** mem_dqs_ie_always_on : HRO; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ + uint32_t mem_dqs_ie_always_on:1; + /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ + uint32_t mem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_ctrl_reg_t; + +/** Type of mem_ctrl1 register + * SPI0 control1 register. + */ +typedef union { + struct { + /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ + uint32_t mem_clk_mode:2; + uint32_t reserved_2:19; + /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t ar_size0_1_support_en:1; + /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t aw_size0_1_support_en:1; + /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ + uint32_t axi_rdata_back_fast:1; + /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ + uint32_t mem_rresp_ecc_err_en:1; + /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ + uint32_t mem_ar_splice_en:1; + /** mem_aw_splice_en : HRO; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ + uint32_t mem_aw_splice_en:1; + /** mem_ram0_en : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ + uint32_t mem_ram0_en:1; + /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ + uint32_t mem_dual_ram_en:1; + /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ + uint32_t mem_fast_write_en:1; + /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_rxfifo_rst:1; + /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_txfifo_rst:1; + }; + uint32_t val; +} spi_mem_ctrl1_reg_t; + +/** Type of mem_ctrl2 register + * SPI0 control2 register. + */ +typedef union { + struct { + /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ + uint32_t mem_cs_setup_time:5; + /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ + uint32_t mem_cs_hold_time:5; + /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ + uint32_t mem_ecc_cs_hold_time:3; + /** mem_ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ + uint32_t mem_ecc_skip_page_corner:1; + /** mem_ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ + uint32_t mem_ecc_16to18_byte_en:1; + uint32_t reserved_15:9; + /** mem_split_trans_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ + uint32_t mem_split_trans_en:1; + /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ + uint32_t mem_cs_hold_delay:6; + /** mem_sync_reset : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ + uint32_t mem_sync_reset:1; + }; + uint32_t val; +} spi_mem_ctrl2_reg_t; + +/** Type of mem_misc register + * SPI0 misc register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ + uint32_t mem_fsub_pin:1; + /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ + uint32_t mem_ssub_pin:1; + /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ + uint32_t mem_ck_idle_edge:1; + /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ + uint32_t mem_cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_misc_reg_t; + +/** Type of mem_cache_fctrl register + * SPI0 bit mode control register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ + uint32_t same_aw_ar_addr_chk_en:1; + /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ + uint32_t close_axi_inf_en:1; + }; + uint32_t val; +} spi_mem_cache_fctrl_reg_t; + +/** Type of mem_ddr register + * SPI0 flash DDR mode control register + */ +typedef union { + struct { + /** fmem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + /** fmem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ + uint32_t fmem_tx_ddr_msk_en:1; + /** fmem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ + uint32_t fmem_rx_ddr_msk_en:1; + /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_ddr_reg_t; + + +/** Group: Clock control and configuration registers */ +/** Type of mem_clock register + * SPI clock division control register. + */ +typedef union { + struct { + /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ + uint32_t mem_clkcnt_l:8; + /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t mem_clkcnt_h:8; + /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ + uint32_t mem_clkcnt_n:8; + uint32_t reserved_24:7; + /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ + uint32_t mem_clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_clock_reg_t; + +/** Type of mem_clock_gate register + * SPI0 clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_clock_gate_reg_t; + + +/** Group: Flash User-defined control registers */ +/** Type of mem_user register + * SPI0 user register. + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** mem_cs_hold : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t mem_cs_hold:1; + /** mem_cs_setup : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + uint32_t mem_cs_setup:1; + uint32_t reserved_8:1; + /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ + uint32_t mem_ck_out_edge:1; + uint32_t reserved_10:16; + /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + uint32_t mem_usr_dummy_idle:1; + uint32_t reserved_27:2; + /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t mem_usr_dummy:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_user_reg_t; + +/** Type of mem_user1 register + * SPI0 user1 register. + */ +typedef union { + struct { + /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t mem_usr_dummy_cyclelen:6; + /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ + uint32_t mem_usr_dbytelen:3; + uint32_t reserved_9:17; + /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t mem_usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_user1_reg_t; + +/** Type of mem_user2 register + * SPI0 user2 register. + */ +typedef union { + struct { + /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t mem_usr_command_value:16; + uint32_t reserved_16:12; + /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t mem_usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_user2_reg_t; + + +/** Group: External RAM Control and configuration registers */ +/** Type of mem_sram_cmd register + * SPI0 external RAM mode control register + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ + uint32_t smem_wdummy_dqs_always_out:1; + /** smem_wdummy_always_out : HRO; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t smem_wdummy_always_out:1; + uint32_t reserved_26:4; + /** smem_dqs_ie_always_on : HRO; bitpos: [30]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ + uint32_t smem_dqs_ie_always_on:1; + /** smem_data_ie_always_on : HRO; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ + uint32_t smem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_sram_cmd_reg_t; + +/** Type of smem_ddr register + * SPI0 external RAM DDR mode control register + */ +typedef union { + struct { + /** smem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t smem_ddr_en:1; + /** smem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t smem_var_dummy:1; + /** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_rdat_swp:1; + /** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_wdat_swp:1; + /** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t smem_ddr_cmd_dis:1; + /** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ + uint32_t smem_outminbytelen:7; + /** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ + uint32_t smem_tx_ddr_msk_en:1; + /** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ + uint32_t smem_rx_ddr_msk_en:1; + /** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t smem_usr_ddr_dqs_thd:7; + /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t smem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** smem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t smem_clk_diff_en:1; + uint32_t reserved_25:1; + /** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t smem_dqs_ca_in:1; + /** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t smem_hyperbus_dummy_2x:1; + /** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ + uint32_t smem_clk_diff_inv:1; + /** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ + uint32_t smem_octa_ram_addr:1; + /** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t smem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_smem_ddr_reg_t; + +/** Type of smem_ac register + * MSPI external RAM ECC and SPI CS timing control register + */ +typedef union { + struct { + /** smem_cs_setup : HRO; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ + uint32_t smem_cs_setup:1; + /** smem_cs_hold : HRO; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t smem_cs_hold:1; + /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ + uint32_t smem_cs_setup_time:5; + /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ + uint32_t smem_cs_hold_time:5; + /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ + uint32_t smem_ecc_cs_hold_time:3; + /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ + uint32_t smem_ecc_skip_page_corner:1; + /** smem_ecc_16to18_byte_en : HRO; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ + uint32_t smem_ecc_16to18_byte_en:1; + uint32_t reserved_17:8; + /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ + uint32_t smem_cs_hold_delay:6; + /** smem_split_trans_en : HRO; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ + uint32_t smem_split_trans_en:1; + }; + uint32_t val; +} spi_smem_ac_reg_t; + + +/** Group: State control register */ +/** Type of mem_fsm register + * SPI0 FSM status register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ + uint32_t mem_lock_delay_time:5; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_fsm_reg_t; + + +/** Group: Interrupt registers */ +/** Type of mem_int_ena register + * SPI0 interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_ena:1; + /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_ena:1; + /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_ena:1; + /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_ena:1; + /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_ena:1; + /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_ena:1; + /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int__ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_ena_reg_t; + +/** Type of mem_int_clr register + * SPI0 interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_clr:1; + /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_clr:1; + /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_clr:1; + /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_clr:1; + /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_clr:1; + /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_clr:1; + /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_clr:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_clr_reg_t; + +/** Type of mem_int_raw register + * SPI0 interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t mem_slv_st_end_int_raw:1; + /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mem_mst_st_end_int_raw:1; + /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ + uint32_t mem_ecc_err_int_raw:1; + /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ + uint32_t mem_pms_reject_int_raw:1; + /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_raddr_err_int_raw:1; + /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ + uint32_t mem_axi_wr_flash_err_int_raw:1; + /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_waddr_err_int_raw:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_raw_reg_t; + +/** Type of mem_int_st register + * SPI0 interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_st:1; + /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_st:1; + /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_st:1; + /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_st:1; + /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_st:1; + /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_st:1; + /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_st:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_st_reg_t; + + +/** Group: PMS control and configuration registers */ +/** Type of fmem_pmsn_attr register + * MSPI flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_fmem_pmsn_attr_reg_t; + +/** Type of fmem_pmsn_addr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section n start address value + */ + uint32_t fmem_pmsn_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_fmem_pmsn_addr_reg_t; + +/** Type of fmem_pmsn_size register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, + * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) + */ + uint32_t fmem_pmsn_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_fmem_pmsn_size_reg_t; + +/** Type of smem_pmsn_attr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_rd_attr:1; + /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_wr_attr:1; + /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_smem_pmsn_attr_reg_t; + +/** Type of smem_pmsn_addr register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section n start address value + */ + uint32_t smem_pmsn_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_pmsn_addr_reg_t; + +/** Type of smem_pmsn_size register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) + */ + uint32_t smem_pmsn_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_smem_pmsn_size_reg_t; + +/** Type of mem_pms_reject register + * SPI1 access reject register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:27; + /** mem_pm_en : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ + uint32_t mem_pm_en:1; + /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ld:1; + /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_st:1; + /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_multi_hit:1; + /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ivd:1; + }; + uint32_t val; +} spi_mem_pms_reject_reg_t; + + +/** Group: MSPI ECC registers */ +/** Type of mem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_cnt:6; + /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t fmem_ecc_err_int_num:6; + /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ + uint32_t fmem_ecc_err_int_en:1; + /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + uint32_t fmem_page_size:2; + /** fmem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ + uint32_t fmem_ecc_addr_en:1; + /** mem_usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ + uint32_t mem_usr_ecc_addr_en:1; + uint32_t reserved_22:2; + /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ + uint32_t mem_ecc_continue_record_err_en:1; + /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ + uint32_t mem_ecc_err_bits:7; + }; + uint32_t val; +} spi_mem_ecc_ctrl_reg_t; + +/** Type of mem_ecc_err_addr register + * MSPI ECC error address register + */ +typedef union { + struct { + /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_ecc_err_addr_reg_t; + +/** Type of smem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** smem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ + uint32_t smem_ecc_err_int_en:1; + /** smem_page_size : HRO; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ + uint32_t smem_page_size:2; + /** smem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ + uint32_t smem_ecc_addr_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_smem_ecc_ctrl_reg_t; + + +/** Group: Status and state control registers */ +/** Type of smem_axi_addr_ctrl register + * SPI0 AXI address control register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ + uint32_t mem_all_fifo_empty:1; + /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t rdata_afifo_rempty:1; + /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t raddr_afifo_rempty:1; + /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wdata_afifo_rempty:1; + /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wblen_afifo_rempty:1; + /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ + uint32_t all_axi_trans_afifo_empty:1; + }; + uint32_t val; +} spi_smem_axi_addr_ctrl_reg_t; + +/** Type of mem_axi_err_resp_en register + * SPI0 AXI error response enable register + */ +typedef union { + struct { + /** mem_aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_vld:1; + /** mem_aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_gid:1; + /** mem_aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_size:1; + /** mem_aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_flash:1; + /** mem_aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_ecc:1; + /** mem_aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_sens:1; + /** mem_aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_wstrb:1; + /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_vld:1; + /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_gid:1; + /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_ecc:1; + /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ + uint32_t mem_ar_resp_en_mmu_sens:1; + /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ + uint32_t mem_ar_resp_en_axi_size:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_axi_err_resp_en_reg_t; + + +/** Group: Flash timing registers */ +/** Type of mem_timing_cali register + * SPI0 flash timing calibration register + */ +typedef union { + struct { + /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t mem_timing_clk_ena:1; + /** mem_timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t mem_timing_cali:1; + /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t mem_extra_dummy_cyclelen:3; + /** mem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ + uint32_t mem_dll_timing_cali:1; + /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ + uint32_t mem_timing_cali_update:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} spi_mem_timing_cali_reg_t; + +/** Type of mem_din_mode register + * MSPI flash input timing delay mode control register + */ +typedef union { + struct { + /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din0_mode:3; + /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din1_mode:3; + /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din2_mode:3; + /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din3_mode:3; + /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din4_mode:3; + /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din5_mode:3; + /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din6_mode:3; + /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din7_mode:3; + /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_din_mode_reg_t; + +/** Type of mem_din_num register + * MSPI flash input timing delay number control register + */ +typedef union { + struct { + /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din0_num:2; + /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din1_num:2; + /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din2_num:2; + /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din3_num:2; + /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din4_num:2; + /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din5_num:2; + /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din6_num:2; + /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din7_num:2; + /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_din_num_reg_t; + +/** Type of mem_dout_mode register + * MSPI flash output timing adjustment control register + */ +typedef union { + struct { + /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout0_mode:1; + /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout1_mode:1; + /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout2_mode:1; + /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout3_mode:1; + /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout4_mode:1; + /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout5_mode:1; + /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout6_mode:1; + /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout7_mode:1; + /** mem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_dout_mode_reg_t; + + +/** Group: External RAM timing registers */ +/** Type of smem_timing_cali register + * MSPI external RAM timing calibration register + */ +typedef union { + struct { + /** smem_timing_clk_ena : HRO; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t smem_timing_clk_ena:1; + /** smem_timing_cali : HRO; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ + uint32_t smem_timing_cali:1; + /** smem_extra_dummy_cyclelen : HRO; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t smem_extra_dummy_cyclelen:3; + /** smem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ + uint32_t smem_dll_timing_cali:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} spi_smem_timing_cali_reg_t; + +/** Type of smem_din_mode register + * MSPI external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din0_mode : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din0_mode:3; + /** smem_din1_mode : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din1_mode:3; + /** smem_din2_mode : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din2_mode:3; + /** smem_din3_mode : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din3_mode:3; + /** smem_din4_mode : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din4_mode:3; + /** smem_din5_mode : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din5_mode:3; + /** smem_din6_mode : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din6_mode:3; + /** smem_din7_mode : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din7_mode:3; + /** smem_dins_mode : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_din_mode_reg_t; + +/** Type of smem_din_num register + * MSPI external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din0_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din0_num:2; + /** smem_din1_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din1_num:2; + /** smem_din2_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din2_num:2; + /** smem_din3_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din3_num:2; + /** smem_din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din4_num:2; + /** smem_din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din5_num:2; + /** smem_din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din6_num:2; + /** smem_din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din7_num:2; + /** smem_dins_num : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_smem_din_num_reg_t; + +/** Type of smem_dout_mode register + * MSPI external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout0_mode : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout0_mode:1; + /** smem_dout1_mode : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout1_mode:1; + /** smem_dout2_mode : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout2_mode:1; + /** smem_dout3_mode : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout3_mode:1; + /** smem_dout4_mode : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout4_mode:1; + /** smem_dout5_mode : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout5_mode:1; + /** smem_dout6_mode : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout6_mode:1; + /** smem_dout7_mode : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout7_mode:1; + /** smem_douts_mode : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_smem_dout_mode_reg_t; + + +/** Group: Manual Encryption plaintext Memory */ +/** Type of mem_xts_plain_base register + * The base address of the memory that stores plaintext in Manual Encryption + */ +typedef union { + struct { + /** xts_plain : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ + uint32_t xts_plain:32; + }; + uint32_t val; +} spi_mem_xts_plain_base_reg_t; + + +/** Group: Manual Encryption configuration registers */ +/** Type of mem_xts_linesize register + * Manual Encryption Line-Size register + */ +typedef union { + struct { + /** xts_linesize : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ + uint32_t xts_linesize:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_linesize_reg_t; + +/** Type of mem_xts_destination register + * Manual Encryption destination register + */ +typedef union { + struct { + /** xts_destination : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ + uint32_t xts_destination:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destination_reg_t; + +/** Type of mem_xts_physical_address register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ + uint32_t xts_physical_address:26; + uint32_t reserved_26:6; + }; + uint32_t val; +} spi_mem_xts_physical_address_reg_t; + + +/** Group: Manual Encryption control and status registers */ +/** Type of mem_xts_trigger register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_trigger : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ + uint32_t xts_trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_trigger_reg_t; + +/** Type of mem_xts_release register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_release : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ + uint32_t xts_release:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_release_reg_t; + +/** Type of mem_xts_destroy register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_destroy : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ + uint32_t xts_destroy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destroy_reg_t; + +/** Type of mem_xts_state register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_state : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ + uint32_t xts_state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_state_reg_t; + + +/** Group: Manual Encryption version control register */ +/** Type of mem_xts_date register + * Manual Encryption version register + */ +typedef union { + struct { + /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ + uint32_t xts_date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_xts_date_reg_t; + + +/** Group: MMU access registers */ +/** Type of mem_mmu_item_content register + * MSPI-MMU item content register + */ +typedef union { + struct { + /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ + uint32_t mmu_item_content:32; + }; + uint32_t val; +} spi_mem_mmu_item_content_reg_t; + +/** Type of mem_mmu_item_index register + * MSPI-MMU item index register + */ +typedef union { + struct { + /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ + uint32_t mmu_item_index:32; + }; + uint32_t val; +} spi_mem_mmu_item_index_reg_t; + + +/** Group: MMU power control and configuration registers */ +/** Type of mem_mmu_power_ctrl register + * MSPI MMU power control register + */ +typedef union { + struct { + /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ + uint32_t mmu_mem_force_on:1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ + uint32_t mmu_mem_force_pd:1; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ + uint32_t mmu_mem_force_pu:1; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; + /** mem_aux_ctrl : HRO; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ + uint32_t mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_mmu_power_ctrl_reg_t; + + +/** Group: External mem cryption DPA registers */ +/** Type of mem_dpa_ctrl register + * SPI memory cryption DPA register + */ +typedef union { + struct { + /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ + uint32_t crypt_security_level:3; + /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ + uint32_t crypt_calc_d_dpa_en:1; + /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ + uint32_t crypt_dpa_select_register:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_dpa_ctrl_reg_t; + + +/** Group: Version control register */ +/** Type of mem_date register + * SPI0 version control register + */ +typedef union { + struct { + /** mem_date : R/W; bitpos: [27:0]; default: 36712560; + * SPI0 register version. + */ + uint32_t mem_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_date_reg_t; + + +typedef struct spi_mem_dev_t { + volatile spi_mem_cmd_reg_t mem_cmd; + uint32_t reserved_004; + volatile spi_mem_ctrl_reg_t mem_ctrl; + volatile spi_mem_ctrl1_reg_t mem_ctrl1; + volatile spi_mem_ctrl2_reg_t mem_ctrl2; + volatile spi_mem_clock_reg_t mem_clock; + volatile spi_mem_user_reg_t mem_user; + volatile spi_mem_user1_reg_t mem_user1; + volatile spi_mem_user2_reg_t mem_user2; + uint32_t reserved_024[4]; + volatile spi_mem_misc_reg_t mem_misc; + uint32_t reserved_038; + volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; + uint32_t reserved_040; + volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; + uint32_t reserved_048[3]; + volatile spi_mem_fsm_reg_t mem_fsm; + uint32_t reserved_058[26]; + volatile spi_mem_int_ena_reg_t mem_int_ena; + volatile spi_mem_int_clr_reg_t mem_int_clr; + volatile spi_mem_int_raw_reg_t mem_int_raw; + volatile spi_mem_int_st_reg_t mem_int_st; + uint32_t reserved_0d0; + volatile spi_mem_ddr_reg_t mem_ddr; + volatile spi_smem_ddr_reg_t smem_ddr; + uint32_t reserved_0dc[9]; + volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; + uint32_t reserved_160; + volatile spi_mem_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; + volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; + volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; + volatile spi_mem_timing_cali_reg_t mem_timing_cali; + volatile spi_mem_din_mode_reg_t mem_din_mode; + volatile spi_mem_din_num_reg_t mem_din_num; + volatile spi_mem_dout_mode_reg_t mem_dout_mode; + volatile spi_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_smem_din_mode_reg_t smem_din_mode; + volatile spi_smem_din_num_reg_t smem_din_num; + volatile spi_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_smem_ac_reg_t smem_ac; + uint32_t reserved_1a4[23]; + volatile spi_mem_clock_gate_reg_t mem_clock_gate; + uint32_t reserved_204[63]; + volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; + uint32_t reserved_304[15]; + volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; + volatile spi_mem_xts_destination_reg_t mem_xts_destination; + volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; + volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; + volatile spi_mem_xts_release_reg_t mem_xts_release; + volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; + volatile spi_mem_xts_state_reg_t mem_xts_state; + volatile spi_mem_xts_date_reg_t mem_xts_date; + uint32_t reserved_360[7]; + volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; + volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; + volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; + volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; + uint32_t reserved_38c[28]; + volatile spi_mem_date_reg_t mem_date; +} spi_mem_dev_t; + +extern spi_mem_dev_t SPIMEM0; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_pins.h b/components/soc/esp32c5/include/soc/spi_pins.h new file mode 100644 index 00000000000..e50f1b1c43a --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_pins.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// TODO: [ESP32C5] IDF-8698 (inherit from C6) + +#define SPI_FUNC_NUM 0 +#define SPI_IOMUX_PIN_NUM_CS 24 +#define SPI_IOMUX_PIN_NUM_CLK 29 +#define SPI_IOMUX_PIN_NUM_MOSI 30 +#define SPI_IOMUX_PIN_NUM_MISO 25 +#define SPI_IOMUX_PIN_NUM_WP 26 +#define SPI_IOMUX_PIN_NUM_HD 28 + +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 16 diff --git a/components/soc/esp32c5/include/soc/spi_reg.h b/components/soc/esp32c5/include/soc/spi_reg.h new file mode 100644 index 00000000000..a778b96d352 --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_reg.h @@ -0,0 +1,2116 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_CMD_REG register + * Command control register + */ +#define SPI_CMD_REG (DR_REG_GPSPI2_BASE + 0x0) +/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ +#define SPI_CONF_BITLEN 0x0003FFFFU +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFFU +#define SPI_CONF_BITLEN_S 0 +/** SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001U +#define SPI_UPDATE_S 23 +/** SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001U +#define SPI_USR_S 24 + +/** SPI_ADDR_REG register + * Address value register + */ +#define SPI_ADDR_REG (DR_REG_GPSPI2_BASE + 0x4) +/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_S 0 + +/** SPI_CTRL_REG register + * SPI control register + */ +#define SPI_CTRL_REG (DR_REG_GPSPI2_BASE + 0x8) +/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001U +#define SPI_DUMMY_OUT_S 3 +/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001U +#define SPI_FADDR_DUAL_S 5 +/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001U +#define SPI_FADDR_QUAD_S 6 +/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001U +#define SPI_FADDR_OCT_S 7 +/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001U +#define SPI_FCMD_DUAL_S 8 +/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001U +#define SPI_FCMD_QUAD_S 9 +/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001U +#define SPI_FCMD_OCT_S 10 +/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001U +#define SPI_FREAD_DUAL_S 14 +/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001U +#define SPI_FREAD_QUAD_S 15 +/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001U +#define SPI_FREAD_OCT_S 16 +/** SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001U +#define SPI_Q_POL_S 18 +/** SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001U +#define SPI_D_POL_S 19 +/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001U +#define SPI_HOLD_POL_S 20 +/** SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001U +#define SPI_WP_POL_S 21 +/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ +#define SPI_RD_BIT_ORDER 0x00000003U +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000003U +#define SPI_RD_BIT_ORDER_S 23 +/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ +#define SPI_WR_BIT_ORDER 0x00000003U +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000003U +#define SPI_WR_BIT_ORDER_S 25 + +/** SPI_CLOCK_REG register + * SPI clock control register + */ +#define SPI_CLOCK_REG (DR_REG_GPSPI2_BASE + 0xc) +/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_L 0x0000003FU +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003FU +#define SPI_CLKCNT_L_S 0 +/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_H 0x0000003FU +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003FU +#define SPI_CLKCNT_H_S 6 +/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ +#define SPI_CLKCNT_N 0x0000003FU +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003FU +#define SPI_CLKCNT_N_S 12 +/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ +#define SPI_CLKDIV_PRE 0x0000000FU +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000FU +#define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_CLK_EQU_SYSCLK_S 31 + +/** SPI_USER_REG register + * SPI USER control register + */ +#define SPI_USER_REG (DR_REG_GPSPI2_BASE + 0x10) +/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001U +#define SPI_DOUTDIN_S 0 +/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001U +#define SPI_QPI_MODE_S 3 +/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001U +#define SPI_OPI_MODE_S 4 +/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001U +#define SPI_TSCK_I_EDGE_S 5 +/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001U +#define SPI_CS_HOLD_S 6 +/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001U +#define SPI_CS_SETUP_S 7 +/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001U +#define SPI_RSCK_I_EDGE_S 8 +/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001U +#define SPI_CK_OUT_EDGE_S 9 +/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001U +#define SPI_FWRITE_DUAL_S 12 +/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001U +#define SPI_FWRITE_QUAD_S 13 +/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001U +#define SPI_FWRITE_OCT_S 14 +/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001U +#define SPI_USR_CONF_NXT_S 15 +/** SPI_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001U +#define SPI_SIO_S 17 +/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_USR_MISO_HIGHPART_S 24 +/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_USR_MOSI_HIGHPART_S 25 +/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_USR_DUMMY_IDLE_S 26 +/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001U +#define SPI_USR_MOSI_S 27 +/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001U +#define SPI_USR_MISO_S 28 +/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001U +#define SPI_USR_DUMMY_S 29 +/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001U +#define SPI_USR_ADDR_S 30 +/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001U +#define SPI_USR_COMMAND_S 31 + +/** SPI_USER1_REG register + * SPI USER control register 1 + */ +#define SPI_USER1_REG (DR_REG_GPSPI2_BASE + 0x14) +/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001U +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ +#define SPI_CS_SETUP_TIME 0x0000001FU +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001FU +#define SPI_CS_SETUP_TIME_S 17 +/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ +#define SPI_CS_HOLD_TIME 0x0000001FU +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001FU +#define SPI_CS_HOLD_TIME_S 22 +/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_ADDR_BITLEN 0x0000001FU +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001FU +#define SPI_USR_ADDR_BITLEN_S 27 + +/** SPI_USER2_REG register + * SPI USER control register 2 + */ +#define SPI_USER2_REG (DR_REG_GPSPI2_BASE + 0x18) +/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_S 0 +/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_S 28 + +/** SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define SPI_MS_DLEN_REG (DR_REG_GPSPI2_BASE + 0x1c) +/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ +#define SPI_MS_DATA_BITLEN 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_S 0 + +/** SPI_MISC_REG register + * SPI misc register + */ +#define SPI_MISC_REG (DR_REG_GPSPI2_BASE + 0x20) +/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001U +#define SPI_CS0_DIS_S 0 +/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001U +#define SPI_CS1_DIS_S 1 +/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001U +#define SPI_CS2_DIS_S 2 +/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001U +#define SPI_CS3_DIS_S 3 +/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001U +#define SPI_CS4_DIS_S 4 +/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001U +#define SPI_CS5_DIS_S 5 +/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001U +#define SPI_CK_DIS_S 6 +/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ +#define SPI_MASTER_CS_POL 0x0000003FU +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003FU +#define SPI_MASTER_CS_POL_S 7 +/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S) +#define SPI_CLK_DATA_DTR_EN_V 0x00000001U +#define SPI_CLK_DATA_DTR_EN_S 16 +/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S) +#define SPI_DATA_DTR_EN_V 0x00000001U +#define SPI_DATA_DTR_EN_S 17 +/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S) +#define SPI_ADDR_DTR_EN_V 0x00000001U +#define SPI_ADDR_DTR_EN_S 18 +/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S) +#define SPI_CMD_DTR_EN_V 0x00000001U +#define SPI_CMD_DTR_EN_S 19 +/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001U +#define SPI_SLAVE_CS_POL_S 23 +/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001U +#define SPI_DQS_IDLE_EDGE_S 24 +/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001U +#define SPI_CK_IDLE_EDGE_S 29 +/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_CS_KEEP_ACTIVE_S 30 +/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001U +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/** SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define SPI_DIN_MODE_REG (DR_REG_GPSPI2_BASE + 0x24) +/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN0_MODE 0x00000003U +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003U +#define SPI_DIN0_MODE_S 0 +/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN1_MODE 0x00000003U +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003U +#define SPI_DIN1_MODE_S 2 +/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN2_MODE 0x00000003U +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003U +#define SPI_DIN2_MODE_S 4 +/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN3_MODE 0x00000003U +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003U +#define SPI_DIN3_MODE_S 6 +/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN4_MODE 0x00000003U +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000003U +#define SPI_DIN4_MODE_S 8 +/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN5_MODE 0x00000003U +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000003U +#define SPI_DIN5_MODE_S 10 +/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN6_MODE 0x00000003U +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000003U +#define SPI_DIN6_MODE_S 12 +/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN7_MODE 0x00000003U +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000003U +#define SPI_DIN7_MODE_S 14 +/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001U +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/** SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define SPI_DIN_NUM_REG (DR_REG_GPSPI2_BASE + 0x28) +/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN0_NUM 0x00000003U +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003U +#define SPI_DIN0_NUM_S 0 +/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN1_NUM 0x00000003U +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003U +#define SPI_DIN1_NUM_S 2 +/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN2_NUM 0x00000003U +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003U +#define SPI_DIN2_NUM_S 4 +/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN3_NUM 0x00000003U +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003U +#define SPI_DIN3_NUM_S 6 +/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN4_NUM 0x00000003U +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003U +#define SPI_DIN4_NUM_S 8 +/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN5_NUM 0x00000003U +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003U +#define SPI_DIN5_NUM_S 10 +/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN6_NUM 0x00000003U +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003U +#define SPI_DIN6_NUM_S 12 +/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN7_NUM 0x00000003U +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003U +#define SPI_DIN7_NUM_S 14 + +/** SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define SPI_DOUT_MODE_REG (DR_REG_GPSPI2_BASE + 0x2c) +/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001U +#define SPI_DOUT0_MODE_S 0 +/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001U +#define SPI_DOUT1_MODE_S 1 +/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001U +#define SPI_DOUT2_MODE_S 2 +/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001U +#define SPI_DOUT3_MODE_S 3 +/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000001U +#define SPI_DOUT4_MODE_S 4 +/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000001U +#define SPI_DOUT5_MODE_S 5 +/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000001U +#define SPI_DOUT6_MODE_S 6 +/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000001U +#define SPI_DOUT7_MODE_S 7 +/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000001U +#define SPI_D_DQS_MODE_S 8 + +/** SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define SPI_DMA_CONF_REG (DR_REG_GPSPI2_BASE + 0x30) +/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_S 0 +/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_S 1 +/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001U +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001U +#define SPI_RX_EOF_EN_S 21 +/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001U +#define SPI_DMA_RX_ENA_S 27 +/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001U +#define SPI_DMA_TX_ENA_S 28 +/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001U +#define SPI_RX_AFIFO_RST_S 29 +/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001U +#define SPI_BUF_AFIFO_RST_S 30 +/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001U +#define SPI_DMA_AFIFO_RST_S 31 + +/** SPI_DMA_INT_ENA_REG register + * SPI interrupt enable register + */ +#define SPI_DMA_INT_ENA_REG (DR_REG_GPSPI2_BASE + 0x34) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD7_INT_ENA_S 4 +/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD8_INT_ENA_S 5 +/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD9_INT_ENA_S 6 +/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001U +#define SPI_SLV_CMDA_INT_ENA_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_TRANS_DONE_INT_ENA_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001U +#define SPI_APP2_INT_ENA_S 19 +/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001U +#define SPI_APP1_INT_ENA_S 20 + +/** SPI_DMA_INT_CLR_REG register + * SPI interrupt clear register + */ +#define SPI_DMA_INT_CLR_REG (DR_REG_GPSPI2_BASE + 0x38) +/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD7_INT_CLR_S 4 +/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD8_INT_CLR_S 5 +/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD9_INT_CLR_S 6 +/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001U +#define SPI_SLV_CMDA_INT_CLR_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_TRANS_DONE_INT_CLR_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001U +#define SPI_APP2_INT_CLR_S 19 +/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001U +#define SPI_APP1_INT_CLR_S 20 + +/** SPI_DMA_INT_RAW_REG register + * SPI interrupt raw register + */ +#define SPI_DMA_INT_RAW_REG (DR_REG_GPSPI2_BASE + 0x3c) +/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD7_INT_RAW_S 4 +/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD8_INT_RAW_S 5 +/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD9_INT_RAW_S 6 +/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001U +#define SPI_SLV_CMDA_INT_RAW_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_TRANS_DONE_INT_RAW_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001U +#define SPI_APP2_INT_RAW_S 19 +/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001U +#define SPI_APP1_INT_RAW_S 20 + +/** SPI_DMA_INT_ST_REG register + * SPI interrupt status register + */ +#define SPI_DMA_INT_ST_REG (DR_REG_GPSPI2_BASE + 0x40) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001U +#define SPI_SLV_CMD7_INT_ST_S 4 +/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001U +#define SPI_SLV_CMD8_INT_ST_S 5 +/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001U +#define SPI_SLV_CMD9_INT_ST_S 6 +/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001U +#define SPI_SLV_CMDA_INT_ST_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_TRANS_DONE_INT_ST_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001U +#define SPI_APP2_INT_ST_S 19 +/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001U +#define SPI_APP1_INT_ST_S 20 + +/** SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define SPI_DMA_INT_SET_REG (DR_REG_GPSPI2_BASE + 0x44) +/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S) +#define SPI_SLV_EX_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S) +#define SPI_SLV_EN_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S) +#define SPI_SLV_CMD7_INT_SET_V 0x00000001U +#define SPI_SLV_CMD7_INT_SET_S 4 +/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S) +#define SPI_SLV_CMD8_INT_SET_V 0x00000001U +#define SPI_SLV_CMD8_INT_SET_S 5 +/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S) +#define SPI_SLV_CMD9_INT_SET_V 0x00000001U +#define SPI_SLV_CMD9_INT_SET_S 6 +/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S) +#define SPI_SLV_CMDA_INT_SET_V 0x00000001U +#define SPI_SLV_CMDA_INT_SET_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S) +#define SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_TRANS_DONE_INT_SET_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S) +#define SPI_APP2_INT_SET_V 0x00000001U +#define SPI_APP2_INT_SET_S 19 +/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S) +#define SPI_APP1_INT_SET_V 0x00000001U +#define SPI_APP1_INT_SET_S 20 + +/** SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define SPI_W0_REG (DR_REG_GPSPI2_BASE + 0x98) +/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF0 0xFFFFFFFFU +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFFU +#define SPI_BUF0_S 0 + +/** SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define SPI_W1_REG (DR_REG_GPSPI2_BASE + 0x9c) +/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF1 0xFFFFFFFFU +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFFU +#define SPI_BUF1_S 0 + +/** SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define SPI_W2_REG (DR_REG_GPSPI2_BASE + 0xa0) +/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF2 0xFFFFFFFFU +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFFU +#define SPI_BUF2_S 0 + +/** SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define SPI_W3_REG (DR_REG_GPSPI2_BASE + 0xa4) +/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF3 0xFFFFFFFFU +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFFU +#define SPI_BUF3_S 0 + +/** SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define SPI_W4_REG (DR_REG_GPSPI2_BASE + 0xa8) +/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF4 0xFFFFFFFFU +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFFU +#define SPI_BUF4_S 0 + +/** SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define SPI_W5_REG (DR_REG_GPSPI2_BASE + 0xac) +/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF5 0xFFFFFFFFU +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFFU +#define SPI_BUF5_S 0 + +/** SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define SPI_W6_REG (DR_REG_GPSPI2_BASE + 0xb0) +/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF6 0xFFFFFFFFU +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFFU +#define SPI_BUF6_S 0 + +/** SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define SPI_W7_REG (DR_REG_GPSPI2_BASE + 0xb4) +/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF7 0xFFFFFFFFU +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFFU +#define SPI_BUF7_S 0 + +/** SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define SPI_W8_REG (DR_REG_GPSPI2_BASE + 0xb8) +/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF8 0xFFFFFFFFU +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFFU +#define SPI_BUF8_S 0 + +/** SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define SPI_W9_REG (DR_REG_GPSPI2_BASE + 0xbc) +/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF9 0xFFFFFFFFU +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFFU +#define SPI_BUF9_S 0 + +/** SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define SPI_W10_REG (DR_REG_GPSPI2_BASE + 0xc0) +/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF10 0xFFFFFFFFU +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFFU +#define SPI_BUF10_S 0 + +/** SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define SPI_W11_REG (DR_REG_GPSPI2_BASE + 0xc4) +/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF11 0xFFFFFFFFU +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFFU +#define SPI_BUF11_S 0 + +/** SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define SPI_W12_REG (DR_REG_GPSPI2_BASE + 0xc8) +/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF12 0xFFFFFFFFU +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFFU +#define SPI_BUF12_S 0 + +/** SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define SPI_W13_REG (DR_REG_GPSPI2_BASE + 0xcc) +/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF13 0xFFFFFFFFU +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFFU +#define SPI_BUF13_S 0 + +/** SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define SPI_W14_REG (DR_REG_GPSPI2_BASE + 0xd0) +/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF14 0xFFFFFFFFU +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFFU +#define SPI_BUF14_S 0 + +/** SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define SPI_W15_REG (DR_REG_GPSPI2_BASE + 0xd4) +/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF15 0xFFFFFFFFU +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFFU +#define SPI_BUF15_S 0 + +/** SPI_SLAVE_REG register + * SPI slave control register + */ +#define SPI_SLAVE_REG (DR_REG_GPSPI2_BASE + 0xe0) +/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ +#define SPI_CLK_MODE 0x00000003U +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003U +#define SPI_CLK_MODE_S 0 +/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001U +#define SPI_CLK_MODE_13_S 2 +/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001U +#define SPI_RSCK_DATA_OUT_S 3 +/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ +#define SPI_SLV_LAST_BYTE_STRB 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_M (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S) +#define SPI_SLV_LAST_BYTE_STRB_V 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_S 12 +/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001U +#define SPI_SLAVE_MODE_S 26 +/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001U +#define SPI_SOFT_RESET_S 27 +/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001U +#define SPI_USR_CONF_S 28 +/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ +#define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_V 0x00000001U +#define SPI_MST_FD_WAIT_DMA_TX_DATA_S 29 + +/** SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define SPI_SLAVE1_REG (DR_REG_GPSPI2_BASE + 0xe4) +/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ +#define SPI_SLV_DATA_BITLEN 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_S 0 +/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ +#define SPI_SLV_LAST_COMMAND 0x000000FFU +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FFU +#define SPI_SLV_LAST_COMMAND_S 18 +/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ +#define SPI_SLV_LAST_ADDR 0x0000003FU +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003FU +#define SPI_SLV_LAST_ADDR_S 26 + +/** SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define SPI_CLK_GATE_REG (DR_REG_GPSPI2_BASE + 0xe8) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001U +#define SPI_MST_CLK_ACTIVE_S 1 +/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001U +#define SPI_MST_CLK_SEL_S 2 + +/** SPI_DATE_REG register + * Version control + */ +#define SPI_DATE_REG (DR_REG_GPSPI2_BASE + 0xf0) +/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931; + * SPI register version. + */ +#define SPI_DATE 0x0FFFFFFFU +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFFU +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_struct.h b/components/soc/esp32c5/include/soc/spi_struct.h new file mode 100644 index 00000000000..6ff9c1e942d --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_struct.h @@ -0,0 +1,1600 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ + uint32_t slv_last_byte_strb:8; + uint32_t reserved_20:2; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + + +/** Group: CPU-controlled data buffer */ +/** Type of wn register + * SPI CPU-controlled buffer n + */ +typedef union { + struct { + /** buf : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf:32; + }; + uint32_t val; +} spi_wn_reg_t; + +/** Type of w1 register + * SPI CPU-controlled buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi_w1_reg_t; + +/** Type of w2 register + * SPI CPU-controlled buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi_w2_reg_t; + +/** Type of w3 register + * SPI CPU-controlled buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi_w3_reg_t; + +/** Type of w4 register + * SPI CPU-controlled buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi_w4_reg_t; + +/** Type of w5 register + * SPI CPU-controlled buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi_w5_reg_t; + +/** Type of w6 register + * SPI CPU-controlled buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi_w6_reg_t; + +/** Type of w7 register + * SPI CPU-controlled buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi_w7_reg_t; + +/** Type of w8 register + * SPI CPU-controlled buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi_w8_reg_t; + +/** Type of w9 register + * SPI CPU-controlled buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi_w9_reg_t; + +/** Type of w10 register + * SPI CPU-controlled buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi_w10_reg_t; + +/** Type of w11 register + * SPI CPU-controlled buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi_w11_reg_t; + +/** Type of w12 register + * SPI CPU-controlled buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi_w12_reg_t; + +/** Type of w13 register + * SPI CPU-controlled buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi_w13_reg_t; + +/** Type of w14 register + * SPI CPU-controlled buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi_w14_reg_t; + +/** Type of w15 register + * SPI CPU-controlled buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi_w15_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716931; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct spi_dev_t { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_wn_reg_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/systimer_reg.h b/components/soc/esp32c5/include/soc/systimer_reg.h new file mode 100644 index 00000000000..07b67111f5f --- /dev/null +++ b/components/soc/esp32c5/include/soc/systimer_reg.h @@ -0,0 +1,630 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ +#define SYSTIMER_ETM_EN (BIT(1)) +#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) +#define SYSTIMER_ETM_EN_V 0x00000001U +#define SYSTIMER_ETM_EN_S 1 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/systimer_struct.h b/components/soc/esp32c5/include/soc/systimer_struct.h new file mode 100644 index 00000000000..4a987c104fd --- /dev/null +++ b/components/soc/esp32c5/include/soc/systimer_struct.h @@ -0,0 +1,683 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** etm_en : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_2:20; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en:1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en:1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en:1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en:1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en:1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en:1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en:1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en:1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en:1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit0_op register + * system timer unit0 value update register + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit0_value_valid:1; + /** timer_unit0_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit0_update:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} systimer_unit0_op_reg_t; + +/** Type of unit0_load_hi register + * system timer unit0 value high load register + */ +typedef union { + struct { + /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ + uint32_t timer_unit0_load_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit0_load_hi_reg_t; + +/** Type of unit0_load_lo register + * system timer unit0 value low load register + */ +typedef union { + struct { + /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ + uint32_t timer_unit0_load_lo:32; + }; + uint32_t val; +} systimer_unit0_load_lo_reg_t; + +/** Type of unit0_value_hi register + * system timer unit0 value high register + */ +typedef union { + struct { + /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ + uint32_t timer_unit0_value_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit0_value_hi_reg_t; + +/** Type of unit0_value_lo register + * system timer unit0 value low register + */ +typedef union { + struct { + /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ + uint32_t timer_unit0_value_lo:32; + }; + uint32_t val; +} systimer_unit0_value_lo_reg_t; + +/** Type of unit0_load register + * system timer unit0 conf sync register + */ +typedef union { + struct { + /** timer_unit0_load : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ + uint32_t timer_unit0_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_unit0_load_reg_t; + + +/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit1_op register + * system timer unit1 value update register + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit1_value_valid:1; + /** timer_unit1_update : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ + uint32_t timer_unit1_update:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} systimer_unit1_op_reg_t; + +/** Type of unit1_load_hi register + * system timer unit1 value high load register + */ +typedef union { + struct { + /** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ + uint32_t timer_unit1_load_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit1_load_hi_reg_t; + +/** Type of unit1_load_lo register + * system timer unit1 value low load register + */ +typedef union { + struct { + /** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ + uint32_t timer_unit1_load_lo:32; + }; + uint32_t val; +} systimer_unit1_load_lo_reg_t; + +/** Type of unit1_value_hi register + * system timer unit1 value high register + */ +typedef union { + struct { + /** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ + uint32_t timer_unit1_value_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit1_value_hi_reg_t; + +/** Type of unit1_value_lo register + * system timer unit1 value low register + */ +typedef union { + struct { + /** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ + uint32_t timer_unit1_value_lo:32; + }; + uint32_t val; +} systimer_unit1_value_lo_reg_t; + +/** Type of unit1_load register + * system timer unit1 conf sync register + */ +typedef union { + struct { + /** timer_unit1_load : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ + uint32_t timer_unit1_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_unit1_load_reg_t; + + +/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target0_hi register + * system timer comp0 value high register + */ +typedef union { + struct { + /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ + uint32_t timer_target0_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target0_hi_reg_t; + +/** Type of target0_lo register + * system timer comp0 value low register + */ +typedef union { + struct { + /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ + uint32_t timer_target0_lo:32; + }; + uint32_t val; +} systimer_target0_lo_reg_t; + +/** Type of target0_conf register + * system timer comp0 target mode register + */ +typedef union { + struct { + /** target0_period : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ + uint32_t target0_period:26; + uint32_t reserved_26:4; + /** target0_period_mode : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ + uint32_t target0_period_mode:1; + /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target0_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target0_conf_reg_t; + +/** Type of comp0_load register + * system timer comp0 conf sync register + */ +typedef union { + struct { + /** timer_comp0_load : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ + uint32_t timer_comp0_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp0_load_reg_t; + + +/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target1_hi register + * system timer comp1 value high register + */ +typedef union { + struct { + /** timer_target1_hi : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ + uint32_t timer_target1_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target1_hi_reg_t; + +/** Type of target1_lo register + * system timer comp1 value low register + */ +typedef union { + struct { + /** timer_target1_lo : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ + uint32_t timer_target1_lo:32; + }; + uint32_t val; +} systimer_target1_lo_reg_t; + +/** Type of target1_conf register + * system timer comp1 target mode register + */ +typedef union { + struct { + /** target1_period : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ + uint32_t target1_period:26; + uint32_t reserved_26:4; + /** target1_period_mode : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ + uint32_t target1_period_mode:1; + /** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target1_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target1_conf_reg_t; + +/** Type of comp1_load register + * system timer comp1 conf sync register + */ +typedef union { + struct { + /** timer_comp1_load : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ + uint32_t timer_comp1_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp1_load_reg_t; + + +/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target2_hi register + * system timer comp2 value high register + */ +typedef union { + struct { + /** timer_target2_hi : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ + uint32_t timer_target2_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target2_hi_reg_t; + +/** Type of target2_lo register + * system timer comp2 value low register + */ +typedef union { + struct { + /** timer_target2_lo : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ + uint32_t timer_target2_lo:32; + }; + uint32_t val; +} systimer_target2_lo_reg_t; + +/** Type of target2_conf register + * system timer comp2 target mode register + */ +typedef union { + struct { + /** target2_period : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ + uint32_t target2_period:26; + uint32_t reserved_26:4; + /** target2_period_mode : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ + uint32_t target2_period_mode:1; + /** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target2_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target2_conf_reg_t; + +/** Type of comp2_load register + * system timer comp2 conf sync register + */ +typedef union { + struct { + /** timer_comp2_load : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ + uint32_t timer_comp2_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp2_load_reg_t; + + +/** Group: SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena:1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena:1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw:1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw:1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr:1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr:1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st:1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st:1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */ +/** Type of real_target0_lo register + * system timer comp0 actual target value low register + */ +typedef union { + struct { + /** target0_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target0_lo_ro:32; + }; + uint32_t val; +} systimer_real_target0_lo_reg_t; + +/** Type of real_target0_hi register + * system timer comp0 actual target value high register + */ +typedef union { + struct { + /** target0_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target0_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target0_hi_reg_t; + + +/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */ +/** Type of real_target1_lo register + * system timer comp1 actual target value low register + */ +typedef union { + struct { + /** target1_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target1_lo_ro:32; + }; + uint32_t val; +} systimer_real_target1_lo_reg_t; + +/** Type of real_target1_hi register + * system timer comp1 actual target value high register + */ +typedef union { + struct { + /** target1_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target1_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target1_hi_reg_t; + + +/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */ +/** Type of real_target2_lo register + * system timer comp2 actual target value low register + */ +typedef union { + struct { + /** target2_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target2_lo_ro:32; + }; + uint32_t val; +} systimer_real_target2_lo_reg_t; + +/** Type of real_target2_hi register + * system timer comp2 actual target value high register + */ +typedef union { + struct { + /** target2_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target2_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target2_hi_reg_t; + + +/** Group: VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ + uint32_t date:32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct systimer_dev_t { + volatile systimer_conf_reg_t conf; + volatile systimer_unit0_op_reg_t unit0_op; + volatile systimer_unit1_op_reg_t unit1_op; + volatile systimer_unit0_load_hi_reg_t unit0_load_hi; + volatile systimer_unit0_load_lo_reg_t unit0_load_lo; + volatile systimer_unit1_load_hi_reg_t unit1_load_hi; + volatile systimer_unit1_load_lo_reg_t unit1_load_lo; + volatile systimer_target0_hi_reg_t target0_hi; + volatile systimer_target0_lo_reg_t target0_lo; + volatile systimer_target1_hi_reg_t target1_hi; + volatile systimer_target1_lo_reg_t target1_lo; + volatile systimer_target2_hi_reg_t target2_hi; + volatile systimer_target2_lo_reg_t target2_lo; + volatile systimer_target0_conf_reg_t target0_conf; + volatile systimer_target1_conf_reg_t target1_conf; + volatile systimer_target2_conf_reg_t target2_conf; + volatile systimer_unit0_value_hi_reg_t unit0_value_hi; + volatile systimer_unit0_value_lo_reg_t unit0_value_lo; + volatile systimer_unit1_value_hi_reg_t unit1_value_hi; + volatile systimer_unit1_value_lo_reg_t unit1_value_lo; + volatile systimer_comp0_load_reg_t comp0_load; + volatile systimer_comp1_load_reg_t comp1_load; + volatile systimer_comp2_load_reg_t comp2_load; + volatile systimer_unit0_load_reg_t unit0_load; + volatile systimer_unit1_load_reg_t unit1_load; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target0_lo_reg_t real_target0_lo; + volatile systimer_real_target0_hi_reg_t real_target0_hi; + volatile systimer_real_target1_lo_reg_t real_target1_lo; + volatile systimer_real_target1_hi_reg_t real_target1_hi; + volatile systimer_real_target2_lo_reg_t real_target2_lo; + volatile systimer_real_target2_hi_reg_t real_target2_hi; + uint32_t reserved_08c[28]; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/tee_reg.h b/components/soc/esp32c5/include/soc/tee_reg.h new file mode 100644 index 00000000000..3e083c2e239 --- /dev/null +++ b/components/soc/esp32c5/include/soc/tee_reg.h @@ -0,0 +1,680 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 +/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M0_LOCK (BIT(2)) +#define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) +#define TEE_M0_LOCK_V 0x00000001U +#define TEE_M0_LOCK_S 2 + +/** TEE_M1_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 +/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m1 tee configuration + */ +#define TEE_M1_LOCK (BIT(2)) +#define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) +#define TEE_M1_LOCK_V 0x00000001U +#define TEE_M1_LOCK_S 2 + +/** TEE_M2_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 +/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m2 tee configuration + */ +#define TEE_M2_LOCK (BIT(2)) +#define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) +#define TEE_M2_LOCK_V 0x00000001U +#define TEE_M2_LOCK_S 2 + +/** TEE_M3_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 +/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m3 tee configuration + */ +#define TEE_M3_LOCK (BIT(2)) +#define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) +#define TEE_M3_LOCK_V 0x00000001U +#define TEE_M3_LOCK_S 2 + +/** TEE_M4_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 +/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m4 tee configuration + */ +#define TEE_M4_LOCK (BIT(2)) +#define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) +#define TEE_M4_LOCK_V 0x00000001U +#define TEE_M4_LOCK_S 2 + +/** TEE_M5_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 +/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m5 tee configuration + */ +#define TEE_M5_LOCK (BIT(2)) +#define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) +#define TEE_M5_LOCK_V 0x00000001U +#define TEE_M5_LOCK_S 2 + +/** TEE_M6_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 +/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m6 tee configuration + */ +#define TEE_M6_LOCK (BIT(2)) +#define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) +#define TEE_M6_LOCK_V 0x00000001U +#define TEE_M6_LOCK_S 2 + +/** TEE_M7_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 +/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m7 tee configuration + */ +#define TEE_M7_LOCK (BIT(2)) +#define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) +#define TEE_M7_LOCK_V 0x00000001U +#define TEE_M7_LOCK_S 2 + +/** TEE_M8_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 +/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m8 tee configuration + */ +#define TEE_M8_LOCK (BIT(2)) +#define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) +#define TEE_M8_LOCK_V 0x00000001U +#define TEE_M8_LOCK_S 2 + +/** TEE_M9_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 +/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m9 tee configuration + */ +#define TEE_M9_LOCK (BIT(2)) +#define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) +#define TEE_M9_LOCK_V 0x00000001U +#define TEE_M9_LOCK_S 2 + +/** TEE_M10_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 +/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m10 tee configuration + */ +#define TEE_M10_LOCK (BIT(2)) +#define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) +#define TEE_M10_LOCK_V 0x00000001U +#define TEE_M10_LOCK_S 2 + +/** TEE_M11_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 +/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m11 tee configuration + */ +#define TEE_M11_LOCK (BIT(2)) +#define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) +#define TEE_M11_LOCK_V 0x00000001U +#define TEE_M11_LOCK_S 2 + +/** TEE_M12_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 +/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m12 tee configuration + */ +#define TEE_M12_LOCK (BIT(2)) +#define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) +#define TEE_M12_LOCK_V 0x00000001U +#define TEE_M12_LOCK_S 2 + +/** TEE_M13_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 +/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m13 tee configuration + */ +#define TEE_M13_LOCK (BIT(2)) +#define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) +#define TEE_M13_LOCK_V 0x00000001U +#define TEE_M13_LOCK_S 2 + +/** TEE_M14_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 +/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m14 tee configuration + */ +#define TEE_M14_LOCK (BIT(2)) +#define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) +#define TEE_M14_LOCK_V 0x00000001U +#define TEE_M14_LOCK_S 2 + +/** TEE_M15_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 +/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m15 tee configuration + */ +#define TEE_M15_LOCK (BIT(2)) +#define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) +#define TEE_M15_LOCK_V 0x00000001U +#define TEE_M15_LOCK_S 2 + +/** TEE_M16_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 +/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m16 tee configuration + */ +#define TEE_M16_LOCK (BIT(2)) +#define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) +#define TEE_M16_LOCK_V 0x00000001U +#define TEE_M16_LOCK_S 2 + +/** TEE_M17_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 +/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m17 tee configuration + */ +#define TEE_M17_LOCK (BIT(2)) +#define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) +#define TEE_M17_LOCK_V 0x00000001U +#define TEE_M17_LOCK_S 2 + +/** TEE_M18_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 +/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m18 tee configuration + */ +#define TEE_M18_LOCK (BIT(2)) +#define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) +#define TEE_M18_LOCK_V 0x00000001U +#define TEE_M18_LOCK_S 2 + +/** TEE_M19_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 +/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m19 tee configuration + */ +#define TEE_M19_LOCK (BIT(2)) +#define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) +#define TEE_M19_LOCK_V 0x00000001U +#define TEE_M19_LOCK_S 2 + +/** TEE_M20_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 +/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m20 tee configuration + */ +#define TEE_M20_LOCK (BIT(2)) +#define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) +#define TEE_M20_LOCK_V 0x00000001U +#define TEE_M20_LOCK_S 2 + +/** TEE_M21_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 +/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m21 tee configuration + */ +#define TEE_M21_LOCK (BIT(2)) +#define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) +#define TEE_M21_LOCK_V 0x00000001U +#define TEE_M21_LOCK_S 2 + +/** TEE_M22_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 +/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m22 tee configuration + */ +#define TEE_M22_LOCK (BIT(2)) +#define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) +#define TEE_M22_LOCK_V 0x00000001U +#define TEE_M22_LOCK_S 2 + +/** TEE_M23_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 +/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m23 tee configuration + */ +#define TEE_M23_LOCK (BIT(2)) +#define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) +#define TEE_M23_LOCK_V 0x00000001U +#define TEE_M23_LOCK_S 2 + +/** TEE_M24_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 +/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m24 tee configuration + */ +#define TEE_M24_LOCK (BIT(2)) +#define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) +#define TEE_M24_LOCK_V 0x00000001U +#define TEE_M24_LOCK_S 2 + +/** TEE_M25_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 +/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m25 tee configuration + */ +#define TEE_M25_LOCK (BIT(2)) +#define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) +#define TEE_M25_LOCK_V 0x00000001U +#define TEE_M25_LOCK_S 2 + +/** TEE_M26_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 +/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m26 tee configuration + */ +#define TEE_M26_LOCK (BIT(2)) +#define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) +#define TEE_M26_LOCK_V 0x00000001U +#define TEE_M26_LOCK_S 2 + +/** TEE_M27_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 +/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m27 tee configuration + */ +#define TEE_M27_LOCK (BIT(2)) +#define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) +#define TEE_M27_LOCK_V 0x00000001U +#define TEE_M27_LOCK_S 2 + +/** TEE_M28_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 +/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m28 tee configuration + */ +#define TEE_M28_LOCK (BIT(2)) +#define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) +#define TEE_M28_LOCK_V 0x00000001U +#define TEE_M28_LOCK_S 2 + +/** TEE_M29_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 +/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m29 tee configuration + */ +#define TEE_M29_LOCK (BIT(2)) +#define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) +#define TEE_M29_LOCK_V 0x00000001U +#define TEE_M29_LOCK_S 2 + +/** TEE_M30_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 +/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m30 tee configuration + */ +#define TEE_M30_LOCK (BIT(2)) +#define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) +#define TEE_M30_LOCK_V 0x00000001U +#define TEE_M30_LOCK_S 2 + +/** TEE_M31_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 +/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m31 tee configuration + */ +#define TEE_M31_LOCK (BIT(2)) +#define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) +#define TEE_M31_LOCK_V 0x00000001U +#define TEE_M31_LOCK_S 2 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ +#define TEE_DATE_REG 0x0FFFFFFFU +#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) +#define TEE_DATE_REG_V 0x0FFFFFFFU +#define TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/tee_struct.h b/components/soc/esp32c5/include/soc/tee_struct.h new file mode 100644 index 00000000000..4cdb85c39cc --- /dev/null +++ b/components/soc/esp32c5/include/soc/tee_struct.h @@ -0,0 +1,701 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + /** m0_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t m0_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m0_mode_ctrl_reg_t; + +/** Type of m1_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m1_mode : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m1_mode:2; + /** m1_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m1 tee configuration + */ + uint32_t m1_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m1_mode_ctrl_reg_t; + +/** Type of m2_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m2_mode : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m2_mode:2; + /** m2_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m2 tee configuration + */ + uint32_t m2_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m2_mode_ctrl_reg_t; + +/** Type of m3_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m3_mode : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m3_mode:2; + /** m3_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m3 tee configuration + */ + uint32_t m3_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m3_mode_ctrl_reg_t; + +/** Type of m4_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m4_mode : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m4_mode:2; + /** m4_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m4 tee configuration + */ + uint32_t m4_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m4_mode_ctrl_reg_t; + +/** Type of m5_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m5_mode : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m5_mode:2; + /** m5_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m5 tee configuration + */ + uint32_t m5_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m5_mode_ctrl_reg_t; + +/** Type of m6_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m6_mode : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m6_mode:2; + /** m6_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m6 tee configuration + */ + uint32_t m6_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m6_mode_ctrl_reg_t; + +/** Type of m7_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m7_mode : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m7_mode:2; + /** m7_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m7 tee configuration + */ + uint32_t m7_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m7_mode_ctrl_reg_t; + +/** Type of m8_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m8_mode : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m8_mode:2; + /** m8_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m8 tee configuration + */ + uint32_t m8_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m8_mode_ctrl_reg_t; + +/** Type of m9_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m9_mode : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m9_mode:2; + /** m9_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m9 tee configuration + */ + uint32_t m9_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m9_mode_ctrl_reg_t; + +/** Type of m10_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m10_mode : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m10_mode:2; + /** m10_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m10 tee configuration + */ + uint32_t m10_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m10_mode_ctrl_reg_t; + +/** Type of m11_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m11_mode : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m11_mode:2; + /** m11_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m11 tee configuration + */ + uint32_t m11_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m11_mode_ctrl_reg_t; + +/** Type of m12_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m12_mode : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m12_mode:2; + /** m12_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m12 tee configuration + */ + uint32_t m12_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m12_mode_ctrl_reg_t; + +/** Type of m13_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m13_mode : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m13_mode:2; + /** m13_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m13 tee configuration + */ + uint32_t m13_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m13_mode_ctrl_reg_t; + +/** Type of m14_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m14_mode : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m14_mode:2; + /** m14_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m14 tee configuration + */ + uint32_t m14_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m14_mode_ctrl_reg_t; + +/** Type of m15_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m15_mode : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m15_mode:2; + /** m15_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m15 tee configuration + */ + uint32_t m15_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m15_mode_ctrl_reg_t; + +/** Type of m16_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m16_mode : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m16_mode:2; + /** m16_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m16 tee configuration + */ + uint32_t m16_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m16_mode_ctrl_reg_t; + +/** Type of m17_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m17_mode : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m17_mode:2; + /** m17_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m17 tee configuration + */ + uint32_t m17_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m17_mode_ctrl_reg_t; + +/** Type of m18_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m18_mode : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m18_mode:2; + /** m18_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m18 tee configuration + */ + uint32_t m18_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m18_mode_ctrl_reg_t; + +/** Type of m19_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m19_mode : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m19_mode:2; + /** m19_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m19 tee configuration + */ + uint32_t m19_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m19_mode_ctrl_reg_t; + +/** Type of m20_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m20_mode : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m20_mode:2; + /** m20_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m20 tee configuration + */ + uint32_t m20_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m20_mode_ctrl_reg_t; + +/** Type of m21_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m21_mode : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m21_mode:2; + /** m21_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m21 tee configuration + */ + uint32_t m21_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m21_mode_ctrl_reg_t; + +/** Type of m22_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m22_mode : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m22_mode:2; + /** m22_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m22 tee configuration + */ + uint32_t m22_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m22_mode_ctrl_reg_t; + +/** Type of m23_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m23_mode : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m23_mode:2; + /** m23_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m23 tee configuration + */ + uint32_t m23_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m23_mode_ctrl_reg_t; + +/** Type of m24_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m24_mode : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m24_mode:2; + /** m24_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m24 tee configuration + */ + uint32_t m24_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m24_mode_ctrl_reg_t; + +/** Type of m25_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m25_mode : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m25_mode:2; + /** m25_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m25 tee configuration + */ + uint32_t m25_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m25_mode_ctrl_reg_t; + +/** Type of m26_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m26_mode : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m26_mode:2; + /** m26_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m26 tee configuration + */ + uint32_t m26_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m26_mode_ctrl_reg_t; + +/** Type of m27_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m27_mode : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m27_mode:2; + /** m27_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m27 tee configuration + */ + uint32_t m27_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m27_mode_ctrl_reg_t; + +/** Type of m28_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m28_mode : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m28_mode:2; + /** m28_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m28 tee configuration + */ + uint32_t m28_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m28_mode_ctrl_reg_t; + +/** Type of m29_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m29_mode : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m29_mode:2; + /** m29_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m29 tee configuration + */ + uint32_t m29_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m29_mode_ctrl_reg_t; + +/** Type of m30_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m30_mode : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m30_mode:2; + /** m30_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m30 tee configuration + */ + uint32_t m30_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m30_mode_ctrl_reg_t; + +/** Type of m31_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m31_mode : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m31_mode:2; + /** m31_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m31 tee configuration + */ + uint32_t m31_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m31_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct tee_dev_t { + volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl; + volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl; + volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl; + volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl; + volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl; + volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl; + volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl; + volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl; + volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl; + volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl; + volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl; + volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl; + volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl; + volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl; + volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl; + volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl; + volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl; + volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl; + volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl; + volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl; + volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl; + volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl; + volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl; + volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl; + volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl; + volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl; + volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl; + volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl; + volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl; + volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl; + volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl; + volatile tee_clock_gate_reg_t clock_gate; + uint32_t reserved_084[990]; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/timer_group_reg.h b/components/soc/esp32c5/include/soc/timer_group_reg.h new file mode 100644 index 00000000000..97a10ff9f0e --- /dev/null +++ b/components/soc/esp32c5/include/soc/timer_group_reg.h @@ -0,0 +1,538 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 2 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 2 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 2 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 2 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/timer_group_struct.h b/components/soc/esp32c5/include/soc/timer_group_struct.h new file mode 100644 index 00000000000..19793e100af --- /dev/null +++ b/components/soc/esp32c5/include/soc/timer_group_struct.h @@ -0,0 +1,552 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length:3; + uint32_t reserved_21:1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en:1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3:2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2:2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1:2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0:2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale:16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed:32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling:1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel:2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy:1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max:15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start:1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value:25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena:1; + uint32_t reserved_1:1; + /** wdt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw:1; + uint32_t reserved_1:1; + /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st:1; + uint32_t reserved_1:1; + /** wdt_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr:1; + uint32_t reserved_1:1; + /** wdt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_29:2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} timg_regclk_reg_t; + + +typedef struct timg_dev_t { + volatile timg_txconfig_reg_t t0config; + volatile timg_txlo_reg_t t0lo; + volatile timg_txhi_reg_t t0hi; + volatile timg_txupdate_reg_t t0update; + volatile timg_txalarmlo_reg_t t0alarmlo; + volatile timg_txalarmhi_reg_t t0alarmhi; + volatile timg_txloadlo_reg_t t0loadlo; + volatile timg_txloadhi_reg_t t0loadhi; + volatile timg_txload_reg_t t0load; + uint32_t reserved_024[9]; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/trace_reg.h b/components/soc/esp32c5/include/soc/trace_reg.h new file mode 100644 index 00000000000..c0f45143e9a --- /dev/null +++ b/components/soc/esp32c5/include/soc/trace_reg.h @@ -0,0 +1,463 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * mem start addr + */ +#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ +#define TRACE_MEM_START_ADDR 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S) +#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * mem end addr + */ +#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * mem current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * mem addr update + */ +#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * fifo status register + */ +#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. \\1: empty \\0: not empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due + * to hart halted or havereset \\3: lost state + */ +#define TRACE_WORK_STATUS 0x00000003U +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000003U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * interrupt enable register + */ +#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * interrupt status register + */ +#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * interrupt clear register + */ +#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * trigger register + */ +#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace.\\1: start trace \\0: invalid\\ + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_CONFIG_REG register + * trace configuration register + */ +#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24) +/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + */ +#define TRACE_DM_TRIGGER_ENA (BIT(0)) +#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S) +#define TRACE_DM_TRIGGER_ENA_V 0x00000001U +#define TRACE_DM_TRIGGER_ENA_S 0 +/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * disabled\\ + */ +#define TRACE_RESET_ENA (BIT(1)) +#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S) +#define TRACE_RESET_ENA_V 0x00000001U +#define TRACE_RESET_ENA_S 1 +/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + */ +#define TRACE_HALT_ENA (BIT(2)) +#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) +#define TRACE_HALT_ENA_V 0x00000001U +#define TRACE_HALT_ENA_S 2 +/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo.\\1: + * enabled.\\0: disabled\\ + */ +#define TRACE_STALL_ENA (BIT(3)) +#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S) +#define TRACE_STALL_ENA_V 0x00000001U +#define TRACE_STALL_ENA_S 3 +/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta + * address mode\\ + */ +#define TRACE_FULL_ADDRESS (BIT(4)) +#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S) +#define TRACE_FULL_ADDRESS_V 0x00000001U +#define TRACE_FULL_ADDRESS_S 4 +/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ +#define TRACE_IMPLICIT_EXCEPT (BIT(5)) +#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S) +#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U +#define TRACE_IMPLICIT_EXCEPT_S 5 + +/** TRACE_FILTER_CONTROL_REG register + * filter control register + */ +#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28) +/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + */ +#define TRACE_FILTER_EN (BIT(0)) +#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S) +#define TRACE_FILTER_EN_V 0x00000001U +#define TRACE_FILTER_EN_S 0 +/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ +#define TRACE_MATCH_COMP (BIT(1)) +#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S) +#define TRACE_MATCH_COMP_V 0x00000001U +#define TRACE_MATCH_COMP_S 1 +/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ +#define TRACE_MATCH_PRIVILEGE (BIT(2)) +#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S) +#define TRACE_MATCH_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_PRIVILEGE_S 2 +/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ +#define TRACE_MATCH_ECAUSE (BIT(3)) +#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S) +#define TRACE_MATCH_ECAUSE_V 0x00000001U +#define TRACE_MATCH_ECAUSE_S 3 +/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ +#define TRACE_MATCH_INTERRUPT (BIT(4)) +#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S) +#define TRACE_MATCH_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_INTERRUPT_S 4 + +/** TRACE_FILTER_MATCH_CONTROL_REG register + * filter match control register + */ +#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c) +/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: + * machine mode. \\0: user mode + */ +#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0)) +#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S) +#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0 +/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match + * itype of 2. \\0: match itype or 1. + */ +#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1)) +#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S) +#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_VALUE_INTERRUPT_S 1 +/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ +#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S) +#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_S 2 + +/** TRACE_FILTER_COMPARATOR_CONTROL_REG register + * filter comparator match control register + */ +#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30) +/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: + * tval. + */ +#define TRACE_P_INPUT (BIT(0)) +#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S) +#define TRACE_P_INPUT_V 0x00000001U +#define TRACE_P_INPUT_S 0 +/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, + * \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: + * always match + */ +#define TRACE_P_FUNCTION 0x00000007U +#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S) +#define TRACE_P_FUNCTION_V 0x00000007U +#define TRACE_P_FUNCTION_S 2 +/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ +#define TRACE_P_NOTIFY (BIT(5)) +#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S) +#define TRACE_P_NOTIFY_V 0x00000001U +#define TRACE_P_NOTIFY_S 5 +/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, \\0: iaddr, + * \\1: tval. + */ +#define TRACE_S_INPUT (BIT(8)) +#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S) +#define TRACE_S_INPUT_V 0x00000001U +#define TRACE_S_INPUT_S 8 +/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less + * than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, + * \\other: always match + */ +#define TRACE_S_FUNCTION 0x00000007U +#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S) +#define TRACE_S_FUNCTION_V 0x00000007U +#define TRACE_S_FUNCTION_S 10 +/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ +#define TRACE_S_NOTIFY (BIT(13)) +#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S) +#define TRACE_S_NOTIFY_V 0x00000001U +#define TRACE_S_NOTIFY_S 13 +/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, \\1: primary and secondary comparator both + * matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: + * set when primary matches and continue to match until after secondary comparator + * matches + */ +#define TRACE_MATCH_MODE 0x00000003U +#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S) +#define TRACE_MATCH_MODE_V 0x00000003U +#define TRACE_MATCH_MODE_S 16 + +/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register + * primary comparator match value + */ +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34) +/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ +#define TRACE_P_MATCH 0xFFFFFFFFU +#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S) +#define TRACE_P_MATCH_V 0xFFFFFFFFU +#define TRACE_P_MATCH_S 0 + +/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register + * secondary comparator match value + */ +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38) +/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ +#define TRACE_S_MATCH 0xFFFFFFFFU +#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S) +#define TRACE_S_MATCH_V 0xFFFFFFFFU +#define TRACE_S_MATCH_S 0 + +/** TRACE_RESYNC_PROLONGED_REG register + * resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + */ +#define TRACE_RESYNC_MODE 0x00000003U +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000003U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_AHB_CONFIG_REG register + * AHB config register + */ +#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) +/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ +#define TRACE_HBURST 0x00000007U +#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S) +#define TRACE_HBURST_V 0x00000007U +#define TRACE_HBURST_S 0 +/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ +#define TRACE_MAX_INCR 0x00000007U +#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S) +#define TRACE_MAX_INCR_V 0x00000007U +#define TRACE_MAX_INCR_S 3 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/trace_struct.h b/components/soc/esp32c5/include/soc/trace_struct.h new file mode 100644 index 00000000000..66d28f93ce6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/trace_struct.h @@ -0,0 +1,462 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Trace memory configuration registers */ +/** Type of mem_start_addr register + * mem start addr + */ +typedef union { + struct { + /** mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ + uint32_t mem_start_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * mem end addr + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * mem current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * mem addr update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * fifo status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. \\1: empty \\0: not empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due + * to hart halted or havereset \\3: lost state + */ + uint32_t work_status:2; + uint32_t reserved_3:29; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Trace interrupt configuration registers */ +/** Type of intr_ena register + * interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * interrupt status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * trigger register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace.\\1: start trace \\0: invalid\\ + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of config register + * trace configuration register + */ +typedef union { + struct { + /** dm_trigger_ena : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + */ + uint32_t dm_trigger_ena:1; + /** reset_ena : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * disabled\\ + */ + uint32_t reset_ena:1; + /** halt_ena : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + */ + uint32_t halt_ena:1; + /** stall_ena : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo.\\1: + * enabled.\\0: disabled\\ + */ + uint32_t stall_ena:1; + /** full_address : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta + * address mode\\ + */ + uint32_t full_address:1; + /** implicit_except : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ + uint32_t implicit_except:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_config_reg_t; + +/** Type of filter_control register + * filter control register + */ +typedef union { + struct { + /** filter_en : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + */ + uint32_t filter_en:1; + /** match_comp : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ + uint32_t match_comp:1; + /** match_privilege : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ + uint32_t match_privilege:1; + /** match_ecause : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ + uint32_t match_ecause:1; + /** match_interrupt : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ + uint32_t match_interrupt:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} trace_filter_control_reg_t; + +/** Type of filter_match_control register + * filter match control register + */ +typedef union { + struct { + /** match_choice_privilege : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: + * machine mode. \\0: user mode + */ + uint32_t match_choice_privilege:1; + /** match_value_interrupt : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match + * itype of 2. \\0: match itype or 1. + */ + uint32_t match_value_interrupt:1; + /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ + uint32_t match_choice_ecause:6; + uint32_t reserved_8:24; + }; + uint32_t val; +} trace_filter_match_control_reg_t; + +/** Type of filter_comparator_control register + * filter comparator match control register + */ +typedef union { + struct { + /** p_input : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: + * tval. + */ + uint32_t p_input:1; + uint32_t reserved_1:1; + /** p_function : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, + * \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: + * always match + */ + uint32_t p_function:3; + /** p_notify : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ + uint32_t p_notify:1; + uint32_t reserved_6:2; + /** s_input : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, \\0: iaddr, + * \\1: tval. + */ + uint32_t s_input:1; + uint32_t reserved_9:1; + /** s_function : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less + * than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, + * \\other: always match + */ + uint32_t s_function:3; + /** s_notify : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ + uint32_t s_notify:1; + uint32_t reserved_14:2; + /** match_mode : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, \\1: primary and secondary comparator both + * matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: + * set when primary matches and continue to match until after secondary comparator + * matches + */ + uint32_t match_mode:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} trace_filter_comparator_control_reg_t; + +/** Type of filter_p_comparator_match register + * primary comparator match value + */ +typedef union { + struct { + /** p_match : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ + uint32_t p_match:32; + }; + uint32_t val; +} trace_filter_p_comparator_match_reg_t; + +/** Type of filter_s_comparator_match register + * secondary comparator match value + */ +typedef union { + struct { + /** s_match : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ + uint32_t s_match:32; + }; + uint32_t val; +} trace_filter_s_comparator_match_reg_t; + +/** Type of resync_prolonged register + * resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + */ + uint32_t resync_mode:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + +/** Type of ahb_config register + * AHB config register + */ +typedef union { + struct { + /** hburst : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ + uint32_t hburst:3; + /** max_incr : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ + uint32_t max_incr:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_ahb_config_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct trace_dev_t { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_config_reg_t config; + volatile trace_filter_control_reg_t filter_control; + volatile trace_filter_match_control_reg_t filter_match_control; + volatile trace_filter_comparator_control_reg_t filter_comparator_control; + volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match; + volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_ahb_config_reg_t ahb_config; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_048[237]; + volatile trace_date_reg_t date; +} trace_dev_t; + +extern trace_dev_t TRACE; + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/twai_reg.h b/components/soc/esp32c5/include/soc/twai_reg.h new file mode 100644 index 00000000000..2301765cafb --- /dev/null +++ b/components/soc/esp32c5/include/soc/twai_reg.h @@ -0,0 +1,791 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TWAI_MODE_REG register + * TWAI mode register. + */ +#define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0) +/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ +#define TWAI_RESET_MODE (BIT(0)) +#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) +#define TWAI_RESET_MODE_V 0x00000001U +#define TWAI_RESET_MODE_S 0 +/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ +#define TWAI_LISTEN_ONLY_MODE (BIT(1)) +#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) +#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U +#define TWAI_LISTEN_ONLY_MODE_S 1 +/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ +#define TWAI_SELF_TEST_MODE (BIT(2)) +#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) +#define TWAI_SELF_TEST_MODE_V 0x00000001U +#define TWAI_SELF_TEST_MODE_S 2 +/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ +#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3)) +#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S) +#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U +#define TWAI_ACCEPTANCE_FILTER_MODE_S 3 + +/** TWAI_CMD_REG register + * TWAI command register. + */ +#define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4) +/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ +#define TWAI_TX_REQUEST (BIT(0)) +#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S) +#define TWAI_TX_REQUEST_V 0x00000001U +#define TWAI_TX_REQUEST_S 0 +/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ +#define TWAI_ABORT_TX (BIT(1)) +#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) +#define TWAI_ABORT_TX_V 0x00000001U +#define TWAI_ABORT_TX_S 1 +/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ +#define TWAI_RELEASE_BUFFER (BIT(2)) +#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S) +#define TWAI_RELEASE_BUFFER_V 0x00000001U +#define TWAI_RELEASE_BUFFER_S 2 +/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ +#define TWAI_CLEAR_DATA_OVERRUN (BIT(3)) +#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S) +#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U +#define TWAI_CLEAR_DATA_OVERRUN_S 3 +/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ +#define TWAI_SELF_RX_REQUEST (BIT(4)) +#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S) +#define TWAI_SELF_RX_REQUEST_V 0x00000001U +#define TWAI_SELF_RX_REQUEST_S 4 + +/** TWAI_STATUS_REG register + * TWAI status register. + */ +#define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8) +/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ +#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0)) +#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S) +#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U +#define TWAI_STATUS_RECEIVE_BUFFER_S 0 +/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ +#define TWAI_STATUS_OVERRUN (BIT(1)) +#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S) +#define TWAI_STATUS_OVERRUN_V 0x00000001U +#define TWAI_STATUS_OVERRUN_S 1 +/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ +#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2)) +#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S) +#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_BUFFER_S 2 +/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ +#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3)) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U +#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3 +/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ +#define TWAI_STATUS_RECEIVE (BIT(4)) +#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S) +#define TWAI_STATUS_RECEIVE_V 0x00000001U +#define TWAI_STATUS_RECEIVE_S 4 +/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ +#define TWAI_STATUS_TRANSMIT (BIT(5)) +#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S) +#define TWAI_STATUS_TRANSMIT_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_S 5 +/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ +#define TWAI_STATUS_ERR (BIT(6)) +#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S) +#define TWAI_STATUS_ERR_V 0x00000001U +#define TWAI_STATUS_ERR_S 6 +/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ +#define TWAI_STATUS_NODE_BUS_OFF (BIT(7)) +#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S) +#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U +#define TWAI_STATUS_NODE_BUS_OFF_S 7 +/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ +#define TWAI_STATUS_MISS (BIT(8)) +#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S) +#define TWAI_STATUS_MISS_V 0x00000001U +#define TWAI_STATUS_MISS_S 8 + +/** TWAI_INTERRUPT_REG register + * Interrupt signals' register. + */ +#define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc) +/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ +#define TWAI_RECEIVE_INT_ST (BIT(0)) +#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S) +#define TWAI_RECEIVE_INT_ST_V 0x00000001U +#define TWAI_RECEIVE_INT_ST_S 0 +/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_TRANSMIT_INT_ST (BIT(1)) +#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S) +#define TWAI_TRANSMIT_INT_ST_V 0x00000001U +#define TWAI_TRANSMIT_INT_ST_S 1 +/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ +#define TWAI_ERR_WARNING_INT_ST (BIT(2)) +#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S) +#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U +#define TWAI_ERR_WARNING_INT_ST_S 2 +/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_DATA_OVERRUN_INT_ST (BIT(3)) +#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S) +#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U +#define TWAI_DATA_OVERRUN_INT_ST_S 3 +/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ +#define TWAI_TS_COUNTER_OVFL_INT_ST (BIT(4)) +#define TWAI_TS_COUNTER_OVFL_INT_ST_M (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S) +#define TWAI_TS_COUNTER_OVFL_INT_ST_V 0x00000001U +#define TWAI_TS_COUNTER_OVFL_INT_ST_S 4 +/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) +#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ST_S 5 +/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S) +#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ST_S 6 +/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_BUS_ERR_INT_ST (BIT(7)) +#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) +#define TWAI_BUS_ERR_INT_ST_V 0x00000001U +#define TWAI_BUS_ERR_INT_ST_S 7 +/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_IDLE_INT_ST (BIT(8)) +#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S) +#define TWAI_IDLE_INT_ST_V 0x00000001U +#define TWAI_IDLE_INT_ST_S 8 + +/** TWAI_INTERRUPT_ENABLE_REG register + * Interrupt enable register. + */ +#define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10) +/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ +#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0)) +#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S) +#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U +#define TWAI_EXT_RECEIVE_INT_ENA_S 0 +/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ +#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1)) +#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S) +#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U +#define TWAI_EXT_TRANSMIT_INT_ENA_S 1 +/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2)) +#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S) +#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U +#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2 +/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3)) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3 +/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ +#define TWAI_TS_COUNTER_OVFL_INT_ENA (BIT(4)) +#define TWAI_TS_COUNTER_OVFL_INT_ENA_M (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S) +#define TWAI_TS_COUNTER_OVFL_INT_ENA_V 0x00000001U +#define TWAI_TS_COUNTER_OVFL_INT_ENA_S 4 +/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ +#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) +#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ENA_S 5 +/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ +#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S) +#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ENA_S 6 +/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_BUS_ERR_INT_ENA (BIT(7)) +#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) +#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U +#define TWAI_BUS_ERR_INT_ENA_S 7 +/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_IDLE_INT_ENA (BIT(8)) +#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S) +#define TWAI_IDLE_INT_ENA_V 0x00000001U +#define TWAI_IDLE_INT_ENA_S 8 + +/** TWAI_BUS_TIMING_0_REG register + * Bit timing configuration register 0. + */ +#define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18) +/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ +#define TWAI_BAUD_PRESC 0x00003FFFU +#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) +#define TWAI_BAUD_PRESC_V 0x00003FFFU +#define TWAI_BAUD_PRESC_S 0 +/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ +#define TWAI_SYNC_JUMP_WIDTH 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) +#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_S 14 + +/** TWAI_BUS_TIMING_1_REG register + * Bit timing configuration register 1. + */ +#define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c) +/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT1 0x0000000FU +#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S) +#define TWAI_TIME_SEGMENT1_V 0x0000000FU +#define TWAI_TIME_SEGMENT1_S 0 +/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT2 0x00000007U +#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S) +#define TWAI_TIME_SEGMENT2_V 0x00000007U +#define TWAI_TIME_SEGMENT2_S 4 +/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TIME_SAMPLING (BIT(7)) +#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S) +#define TWAI_TIME_SAMPLING_V 0x00000001U +#define TWAI_TIME_SAMPLING_S 7 + +/** TWAI_ARB_LOST_CAP_REG register + * TWAI arbiter lost capture register. + */ +#define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c) +/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ +#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S) +#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_S 0 + +/** TWAI_ERR_CODE_CAP_REG register + * TWAI error info capture register. + */ +#define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30) +/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ +#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S) +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0 +/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ +#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5)) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5 +/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ +#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S) +#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6 + +/** TWAI_ERR_WARNING_LIMIT_REG register + * TWAI error threshold configuration register. + */ +#define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34) +/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_ERR_WARNING_LIMIT 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) +#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_S 0 + +/** TWAI_RX_ERR_CNT_REG register + * Rx error counter register. + */ +#define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38) +/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_RX_ERR_CNT 0x000000FFU +#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) +#define TWAI_RX_ERR_CNT_V 0x000000FFU +#define TWAI_RX_ERR_CNT_S 0 + +/** TWAI_TX_ERR_CNT_REG register + * Tx error counter register. + */ +#define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c) +/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TX_ERR_CNT 0x000000FFU +#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) +#define TWAI_TX_ERR_CNT_V 0x000000FFU +#define TWAI_TX_ERR_CNT_S 0 + +/** TWAI_DATA_0_REG register + * Data register 0. + */ +#define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40) +/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ +#define TWAI_DATA_0 0x000000FFU +#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S) +#define TWAI_DATA_0_V 0x000000FFU +#define TWAI_DATA_0_S 0 + +/** TWAI_DATA_1_REG register + * Data register 1. + */ +#define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44) +/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ +#define TWAI_DATA_1 0x000000FFU +#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S) +#define TWAI_DATA_1_V 0x000000FFU +#define TWAI_DATA_1_S 0 + +/** TWAI_DATA_2_REG register + * Data register 2. + */ +#define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48) +/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ +#define TWAI_DATA_2 0x000000FFU +#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S) +#define TWAI_DATA_2_V 0x000000FFU +#define TWAI_DATA_2_S 0 + +/** TWAI_DATA_3_REG register + * Data register 3. + */ +#define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c) +/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ +#define TWAI_DATA_3 0x000000FFU +#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S) +#define TWAI_DATA_3_V 0x000000FFU +#define TWAI_DATA_3_S 0 + +/** TWAI_DATA_4_REG register + * Data register 4. + */ +#define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50) +/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ +#define TWAI_DATA_4 0x000000FFU +#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S) +#define TWAI_DATA_4_V 0x000000FFU +#define TWAI_DATA_4_S 0 + +/** TWAI_DATA_5_REG register + * Data register 5. + */ +#define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54) +/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ +#define TWAI_DATA_5 0x000000FFU +#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S) +#define TWAI_DATA_5_V 0x000000FFU +#define TWAI_DATA_5_S 0 + +/** TWAI_DATA_6_REG register + * Data register 6. + */ +#define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58) +/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ +#define TWAI_DATA_6 0x000000FFU +#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S) +#define TWAI_DATA_6_V 0x000000FFU +#define TWAI_DATA_6_S 0 + +/** TWAI_DATA_7_REG register + * Data register 7. + */ +#define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c) +/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ +#define TWAI_DATA_7 0x000000FFU +#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S) +#define TWAI_DATA_7_V 0x000000FFU +#define TWAI_DATA_7_S 0 + +/** TWAI_DATA_8_REG register + * Data register 8. + */ +#define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60) +/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ +#define TWAI_DATA_8 0x000000FFU +#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S) +#define TWAI_DATA_8_V 0x000000FFU +#define TWAI_DATA_8_S 0 + +/** TWAI_DATA_9_REG register + * Data register 9. + */ +#define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64) +/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ +#define TWAI_DATA_9 0x000000FFU +#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S) +#define TWAI_DATA_9_V 0x000000FFU +#define TWAI_DATA_9_S 0 + +/** TWAI_DATA_10_REG register + * Data register 10. + */ +#define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68) +/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ +#define TWAI_DATA_10 0x000000FFU +#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S) +#define TWAI_DATA_10_V 0x000000FFU +#define TWAI_DATA_10_S 0 + +/** TWAI_DATA_11_REG register + * Data register 11. + */ +#define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c) +/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ +#define TWAI_DATA_11 0x000000FFU +#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S) +#define TWAI_DATA_11_V 0x000000FFU +#define TWAI_DATA_11_S 0 + +/** TWAI_DATA_12_REG register + * Data register 12. + */ +#define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70) +/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ +#define TWAI_DATA_12 0x000000FFU +#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S) +#define TWAI_DATA_12_V 0x000000FFU +#define TWAI_DATA_12_S 0 + +/** TWAI_RX_MESSAGE_COUNTER_REG register + * Received message counter register. + */ +#define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74) +/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ +#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) +#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_S 0 + +/** TWAI_CLOCK_DIVIDER_REG register + * Clock divider register. + */ +#define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c) +/** TWAI_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ +#define TWAI_CD 0x000000FFU +#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) +#define TWAI_CD_V 0x000000FFU +#define TWAI_CD_S 0 +/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_CLOCK_OFF (BIT(8)) +#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) +#define TWAI_CLOCK_OFF_V 0x00000001U +#define TWAI_CLOCK_OFF_S 8 + +/** TWAI_SW_STANDBY_CFG_REG register + * Software configure standby pin directly. + */ +#define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80) +/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ +#define TWAI_SW_STANDBY_EN (BIT(0)) +#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S) +#define TWAI_SW_STANDBY_EN_V 0x00000001U +#define TWAI_SW_STANDBY_EN_S 0 +/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ +#define TWAI_SW_STANDBY_CLR (BIT(1)) +#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S) +#define TWAI_SW_STANDBY_CLR_V 0x00000001U +#define TWAI_SW_STANDBY_CLR_S 1 + +/** TWAI_HW_CFG_REG register + * Hardware configure standby pin. + */ +#define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84) +/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ +#define TWAI_HW_STANDBY_EN (BIT(0)) +#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S) +#define TWAI_HW_STANDBY_EN_V 0x00000001U +#define TWAI_HW_STANDBY_EN_S 0 + +/** TWAI_HW_STANDBY_CNT_REG register + * Configure standby counter. + */ +#define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88) +/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ +#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S) +#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_S 0 + +/** TWAI_IDLE_INTR_CNT_REG register + * Configure idle interrupt counter. + */ +#define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c) +/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ +#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S) +#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_S 0 + +/** TWAI_ECO_CFG_REG register + * ECO configuration register. + */ +#define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90) +/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ +#define TWAI_RDN_ENA (BIT(0)) +#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S) +#define TWAI_RDN_ENA_V 0x00000001U +#define TWAI_RDN_ENA_S 0 +/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ +#define TWAI_RDN_RESULT (BIT(1)) +#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S) +#define TWAI_RDN_RESULT_V 0x00000001U +#define TWAI_RDN_RESULT_S 1 + +/** TWAI_TIMESTAMP_DATA_REG register + * Timestamp data register + */ +#define TWAI_TIMESTAMP_DATA_REG(i) (REG_TWAI_BASE(i) + 0x94) +/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ +#define TWAI_TIMESTAMP_DATA 0xFFFFFFFFU +#define TWAI_TIMESTAMP_DATA_M (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S) +#define TWAI_TIMESTAMP_DATA_V 0xFFFFFFFFU +#define TWAI_TIMESTAMP_DATA_S 0 + +/** TWAI_TIMESTAMP_PRESCALER_REG register + * Timestamp configuration register + */ +#define TWAI_TIMESTAMP_PRESCALER_REG(i) (REG_TWAI_BASE(i) + 0x98) +/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ +#define TWAI_TS_DIV_NUM 0x0000FFFFU +#define TWAI_TS_DIV_NUM_M (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S) +#define TWAI_TS_DIV_NUM_V 0x0000FFFFU +#define TWAI_TS_DIV_NUM_S 0 + +/** TWAI_TIMESTAMP_CFG_REG register + * Timestamp configuration register + */ +#define TWAI_TIMESTAMP_CFG_REG(i) (REG_TWAI_BASE(i) + 0x9c) +/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ +#define TWAI_TS_ENABLE (BIT(0)) +#define TWAI_TS_ENABLE_M (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S) +#define TWAI_TS_ENABLE_V 0x00000001U +#define TWAI_TS_ENABLE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/twai_struct.h b/components/soc/esp32c5/include/soc/twai_struct.h new file mode 100644 index 00000000000..bc3be7f3f41 --- /dev/null +++ b/components/soc/esp32c5/include/soc/twai_struct.h @@ -0,0 +1,614 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ + uint32_t ts_counter_ovfl_int_st:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ + uint32_t ts_counter_ovfl_int_ena:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of tx_rx_buffer register + * Data register. + */ +typedef union { + struct { + /** byte : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_rx_buffer_reg_t; + + +/** Group: Timestamp Register */ +/** Type of timestamp_data register + * Timestamp data register + */ +typedef union { + struct { + /** timestamp_data : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ + uint32_t timestamp_data:32; + }; + uint32_t val; +} twai_timestamp_data_reg_t; + +/** Type of timestamp_prescaler register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_div_num : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ + uint32_t ts_div_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_timestamp_prescaler_reg_t; + +/** Type of timestamp_cfg register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_enable : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ + uint32_t ts_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_timestamp_cfg_reg_t; + +typedef struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved_60[5]; +} acceptance_filter_reg_t; + +typedef struct twai_dev_t { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_reg_t interrupt; + volatile twai_interrupt_enable_reg_t interrupt_enable; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile union { + acceptance_filter_reg_t acceptance_filter; + twai_tx_rx_buffer_reg_t tx_rx_buffer[13]; + }; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; + volatile twai_timestamp_data_reg_t timestamp_data; + volatile twai_timestamp_prescaler_reg_t timestamp_prescaler; + volatile twai_timestamp_cfg_reg_t timestamp_cfg; +} twai_dev_t; + +extern twai_dev_t TWAI0; +extern twai_dev_t TWAI1; + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uart_reg.h b/components/soc/esp32c5/include/soc/uart_reg.h new file mode 100644 index 00000000000..ac864940d82 --- /dev/null +++ b/components/soc/esp32c5/include/soc/uart_reg.h @@ -0,0 +1,1579 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UART_FIFO_REG register + * FIFO data register + */ +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG register + * Raw interrupt status + */ +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG register + * Masked interrupt status + */ +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG register + * UART status register + */ +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG register + * a + */ +#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG register + * Configuration register 1 + */ +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG register + * UART Version register + */ +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848; + * This is the version register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG register + * UART ID register + */ +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uart_struct.h b/components/soc/esp32c5/include/soc/uart_struct.h new file mode 100644 index 00000000000..6e3b262d6e1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/uart_struct.h @@ -0,0 +1,1271 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err_int_raw:1; + /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err_int_raw:1; + /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash_int_raw:1; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err_int_st:1; + /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err_int_st:1; + /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash_int_st:1; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err_int_ena:1; + /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err_int_ena:1; + /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash_int_ena:1; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err_int_clr:1; + /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err_int_clr:1; + /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash_int_clr:1; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35680848; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct uart_dev_t { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uhci_reg.h b/components/soc/esp32c5/include/soc/uhci_reg.h new file mode 100644 index 00000000000..af115318323 --- /dev/null +++ b/components/soc/esp32c5/include/soc/uhci_reg.h @@ -0,0 +1,966 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UHCI_CONF0_REG register + * UHCI Configuration Register0 + */ +#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0) +/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S) +#define UHCI_TX_RST_V 0x00000001U +#define UHCI_TX_RST_S 0 +/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S) +#define UHCI_RX_RST_V 0x00000001U +#define UHCI_RX_RST_S 1 +/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7; + * Select which uart to connect with GDMA. + */ +#define UHCI_UART_SEL 0x00000007U +#define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S) +#define UHCI_UART_SEL_V 0x00000007U +#define UHCI_UART_SEL_S 2 +/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001U +#define UHCI_SEPER_EN_S 5 +/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001U +#define UHCI_HEAD_EN_S 6 +/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001U +#define UHCI_CRC_REC_EN_S 7 +/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U +#define UHCI_UART_IDLE_EOF_EN_S 8 +/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001U +#define UHCI_LEN_EOF_EN_S 9 +/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001U +#define UHCI_ENCODE_CRC_EN_S 10 +/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001U +#define UHCI_CLK_EN_S 11 +/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U +#define UHCI_UART_RX_BRK_EOF_EN_S 12 + +/** UHCI_INT_RAW_REG register + * UHCI Interrupt Raw Register + */ +#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4) +/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001U +#define UHCI_RX_START_INT_RAW_S 0 +/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001U +#define UHCI_TX_START_INT_RAW_S 1 +/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_RX_HUNG_INT_RAW_S 2 +/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_TX_HUNG_INT_RAW_S 3 +/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ +#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S) +#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_RAW_S 4 +/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ +#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S) +#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_RAW_S 5 +/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ +#define UHCI_OUT_EOF_INT_RAW (BIT(6)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U +#define UHCI_OUT_EOF_INT_RAW_S 6 +/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S) +#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S) +#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL1_INT_RAW_S 8 + +/** UHCI_INT_ST_REG register + * UHCI Interrupt Status Register + */ +#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8) +/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001U +#define UHCI_RX_START_INT_ST_S 0 +/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001U +#define UHCI_TX_START_INT_ST_S 1 +/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001U +#define UHCI_RX_HUNG_INT_ST_S 2 +/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001U +#define UHCI_TX_HUNG_INT_ST_S 3 +/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S) +#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ST_S 4 +/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S) +#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ST_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S) +#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ST_S 7 +/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S) +#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ST_S 8 + +/** UHCI_INT_ENA_REG register + * UHCI Interrupt Enable Register + */ +#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc) +/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001U +#define UHCI_RX_START_INT_ENA_S 0 +/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001U +#define UHCI_TX_START_INT_ENA_S 1 +/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_RX_HUNG_INT_ENA_S 2 +/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_TX_HUNG_INT_ENA_S 3 +/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S) +#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ENA_S 4 +/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S) +#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ENA_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S) +#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S) +#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ENA_S 8 + +/** UHCI_INT_CLR_REG register + * UHCI Interrupt Clear Register + */ +#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10) +/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001U +#define UHCI_RX_START_INT_CLR_S 0 +/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001U +#define UHCI_TX_START_INT_CLR_S 1 +/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_RX_HUNG_INT_CLR_S 2 +/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_TX_HUNG_INT_CLR_S 3 +/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S) +#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_CLR_S 4 +/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S) +#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_CLR_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S) +#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S) +#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL1_INT_CLR_S 8 + +/** UHCI_CONF1_REG register + * UHCI Configuration Register1 + */ +#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14) +/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001U +#define UHCI_CHECK_SUM_EN_S 0 +/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001U +#define UHCI_CHECK_SEQ_EN_S 1 +/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001U +#define UHCI_CRC_DISABLE_S 2 +/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001U +#define UHCI_SAVE_HEAD_S 3 +/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U +#define UHCI_TX_CHECK_SUM_RE_S 4 +/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001U +#define UHCI_TX_ACK_NUM_RE_S 5 +/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001U +#define UHCI_WAIT_SW_START_S 7 +/** UHCI_SW_START : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001U +#define UHCI_SW_START_S 8 + +/** UHCI_STATE0_REG register + * UHCI Receive Status Register + */ +#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18) +/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ +#define UHCI_RX_ERR_CAUSE 0x00000007U +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007U +#define UHCI_RX_ERR_CAUSE_S 0 +/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ +#define UHCI_DECODE_STATE 0x00000007U +#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S) +#define UHCI_DECODE_STATE_V 0x00000007U +#define UHCI_DECODE_STATE_S 3 + +/** UHCI_STATE1_REG register + * UHCI Transmit Status Register + */ +#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c) +/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ +#define UHCI_ENCODE_STATE 0x00000007U +#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S) +#define UHCI_ENCODE_STATE_V 0x00000007U +#define UHCI_ENCODE_STATE_S 0 + +/** UHCI_ESCAPE_CONF_REG register + * UHCI Escapes Configuration Register0 + */ +#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20) +/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001U +#define UHCI_TX_C0_ESC_EN_S 0 +/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001U +#define UHCI_TX_DB_ESC_EN_S 1 +/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001U +#define UHCI_TX_11_ESC_EN_S 2 +/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001U +#define UHCI_TX_13_ESC_EN_S 3 +/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001U +#define UHCI_RX_C0_ESC_EN_S 4 +/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001U +#define UHCI_RX_DB_ESC_EN_S 5 +/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001U +#define UHCI_RX_11_ESC_EN_S 6 +/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001U +#define UHCI_RX_13_ESC_EN_S 7 + +/** UHCI_HUNG_CONF_REG register + * UHCI Hung Configuration Register0 + */ +#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24) +/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_S 0 +/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_S 12 +/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/** UHCI_ACK_NUM_REG register + * UHCI Ack Value Configuration Register0 + */ +#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28) +/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ +#define UHCI_ACK_NUM 0x00000007U +#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S) +#define UHCI_ACK_NUM_V 0x00000007U +#define UHCI_ACK_NUM_S 0 +/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) +#define UHCI_ACK_NUM_LOAD_V 0x00000001U +#define UHCI_ACK_NUM_LOAD_S 3 + +/** UHCI_RX_HEAD_REG register + * UHCI Head Register + */ +#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c) +/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ +#define UHCI_RX_HEAD 0xFFFFFFFFU +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFFU +#define UHCI_RX_HEAD_S 0 + +/** UHCI_QUICK_SENT_REG register + * UCHI Quick send Register + */ +#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30) +/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ +#define UHCI_SINGLE_SEND_NUM 0x00000007U +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007U +#define UHCI_SINGLE_SEND_NUM_S 0 +/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001U +#define UHCI_SINGLE_SEND_EN_S 3 +/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_S 4 +/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001U +#define UHCI_ALWAYS_SEND_EN_S 7 + +/** UHCI_REG_Q0_WORD0_REG register + * UHCI Q0_WORD0 Quick Send Register + */ +#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34) +/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_S 0 + +/** UHCI_REG_Q0_WORD1_REG register + * UHCI Q0_WORD1 Quick Send Register + */ +#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38) +/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_S 0 + +/** UHCI_REG_Q1_WORD0_REG register + * UHCI Q1_WORD0 Quick Send Register + */ +#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c) +/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_S 0 + +/** UHCI_REG_Q1_WORD1_REG register + * UHCI Q1_WORD1 Quick Send Register + */ +#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40) +/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_S 0 + +/** UHCI_REG_Q2_WORD0_REG register + * UHCI Q2_WORD0 Quick Send Register + */ +#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44) +/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_S 0 + +/** UHCI_REG_Q2_WORD1_REG register + * UHCI Q2_WORD1 Quick Send Register + */ +#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48) +/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_S 0 + +/** UHCI_REG_Q3_WORD0_REG register + * UHCI Q3_WORD0 Quick Send Register + */ +#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c) +/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_S 0 + +/** UHCI_REG_Q3_WORD1_REG register + * UHCI Q3_WORD1 Quick Send Register + */ +#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50) +/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_S 0 + +/** UHCI_REG_Q4_WORD0_REG register + * UHCI Q4_WORD0 Quick Send Register + */ +#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54) +/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_S 0 + +/** UHCI_REG_Q4_WORD1_REG register + * UHCI Q4_WORD1 Quick Send Register + */ +#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58) +/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_S 0 + +/** UHCI_REG_Q5_WORD0_REG register + * UHCI Q5_WORD0 Quick Send Register + */ +#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c) +/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_S 0 + +/** UHCI_REG_Q5_WORD1_REG register + * UHCI Q5_WORD1 Quick Send Register + */ +#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60) +/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_S 0 + +/** UHCI_REG_Q6_WORD0_REG register + * UHCI Q6_WORD0 Quick Send Register + */ +#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64) +/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_S 0 + +/** UHCI_REG_Q6_WORD1_REG register + * UHCI Q6_WORD1 Quick Send Register + */ +#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68) +/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_S 0 + +/** UHCI_ESC_CONF0_REG register + * UHCI Escapes Sequence Configuration Register0 + */ +#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c) +/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ +#define UHCI_SEPER_CHAR 0x000000FFU +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FFU +#define UHCI_SEPER_CHAR_S 0 +/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_S 8 +/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/** UHCI_ESC_CONF1_REG register + * UHCI Escapes Sequence Configuration Register1 + */ +#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70) +/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ +#define UHCI_ESC_SEQ0 0x000000FFU +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FFU +#define UHCI_ESC_SEQ0_S 0 +/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/** UHCI_ESC_CONF2_REG register + * UHCI Escapes Sequence Configuration Register2 + */ +#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74) +/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ +#define UHCI_ESC_SEQ1 0x000000FFU +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FFU +#define UHCI_ESC_SEQ1_S 0 +/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/** UHCI_ESC_CONF3_REG register + * UHCI Escapes Sequence Configuration Register3 + */ +#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78) +/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ +#define UHCI_ESC_SEQ2 0x000000FFU +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FFU +#define UHCI_ESC_SEQ2_S 0 +/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/** UHCI_PKT_THRES_REG register + * UCHI Packet Length Configuration Register + */ +#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c) +/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ +#define UHCI_PKT_THRS 0x00001FFFU +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFFU +#define UHCI_PKT_THRS_S 0 + +/** UHCI_DATE_REG register + * UHCI Version Register + */ +#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80) +/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ +#define UHCI_DATE 0xFFFFFFFFU +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFFU +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uhci_struct.h b/components/soc/esp32c5/include/soc/uhci_struct.h new file mode 100644 index 00000000000..1d0fa4129f9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/uhci_struct.h @@ -0,0 +1,666 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of conf0 register + * UHCI Configuration Register0 + */ +typedef union { + struct { + /** tx_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ + uint32_t tx_rst:1; + /** rx_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ + uint32_t rx_rst:1; + /** uart_sel : R/W; bitpos: [4:2]; default: 7; + * Select which uart to connect with GDMA. + */ + uint32_t uart_sel:3; + /** seper_en : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ + uint32_t seper_en:1; + /** head_en : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ + uint32_t head_en:1; + /** crc_rec_en : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ + uint32_t crc_rec_en:1; + /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ + uint32_t uart_idle_eof_en:1; + /** len_eof_en : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ + uint32_t len_eof_en:1; + /** encode_crc_en : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ + uint32_t encode_crc_en:1; + /** clk_en : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ + uint32_t uart_rx_brk_eof_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_conf0_reg_t; + +/** Type of conf1 register + * UHCI Configuration Register1 + */ +typedef union { + struct { + /** check_sum_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ + uint32_t check_sum_en:1; + /** check_seq_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ + uint32_t check_seq_en:1; + /** crc_disable : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ + uint32_t crc_disable:1; + /** save_head : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ + uint32_t save_head:1; + /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ + uint32_t tx_check_sum_re:1; + /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ + uint32_t tx_ack_num_re:1; + uint32_t reserved_6:1; + /** wait_sw_start : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ + uint32_t wait_sw_start:1; + /** sw_start : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ + uint32_t sw_start:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_conf1_reg_t; + +/** Type of escape_conf register + * UHCI Escapes Configuration Register0 + */ +typedef union { + struct { + /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ + uint32_t tx_c0_esc_en:1; + /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ + uint32_t tx_db_esc_en:1; + /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ + uint32_t tx_11_esc_en:1; + /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ + uint32_t tx_13_esc_en:1; + /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ + uint32_t rx_c0_esc_en:1; + /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ + uint32_t rx_db_esc_en:1; + /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ + uint32_t rx_11_esc_en:1; + /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ + uint32_t rx_13_esc_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_escape_conf_reg_t; + +/** Type of hung_conf register + * UHCI Hung Configuration Register0 + */ +typedef union { + struct { + /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ + uint32_t txfifo_timeout:8; + /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ + uint32_t txfifo_timeout_shift:3; + /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ + uint32_t txfifo_timeout_ena:1; + /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ + uint32_t rxfifo_timeout:8; + /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ + uint32_t rxfifo_timeout_shift:3; + /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ + uint32_t rxfifo_timeout_ena:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_hung_conf_reg_t; + +/** Type of ack_num register + * UHCI Ack Value Configuration Register0 + */ +typedef union { + struct { + /** ack_num : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ + uint32_t ack_num:3; + /** ack_num_load : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ + uint32_t ack_num_load:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uhci_ack_num_reg_t; + +/** Type of quick_sent register + * UCHI Quick send Register + */ +typedef union { + struct { + /** single_send_num : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ + uint32_t single_send_num:3; + /** single_send_en : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ + uint32_t single_send_en:1; + /** always_send_num : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ + uint32_t always_send_num:3; + /** always_send_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ + uint32_t always_send_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_quick_sent_reg_t; + +/** Type of reg_qn_word0 register + * UHCI QN_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_word0:32; + }; + uint32_t val; +} uhci_reg_qn_word0_reg_t; + +/** Type of reg_qn_word1 register + * UHCI QN_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_word1:32; + }; + uint32_t val; +} uhci_reg_qn_word1_reg_t; + +/** Type of esc_conf0 register + * UHCI Escapes Sequence Configuration Register0 + */ +typedef union { + struct { + /** seper_char : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ + uint32_t seper_char:8; + /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t seper_esc_char0:8; + /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ + uint32_t seper_esc_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf0_reg_t; + +/** Type of esc_conf1 register + * UHCI Escapes Sequence Configuration Register1 + */ +typedef union { + struct { + /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ + uint32_t esc_seq0:8; + /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq0_char0:8; + /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ + uint32_t esc_seq0_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf1_reg_t; + +/** Type of esc_conf2 register + * UHCI Escapes Sequence Configuration Register2 + */ +typedef union { + struct { + /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ + uint32_t esc_seq1:8; + /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq1_char0:8; + /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ + uint32_t esc_seq1_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf2_reg_t; + +/** Type of esc_conf3 register + * UHCI Escapes Sequence Configuration Register3 + */ +typedef union { + struct { + /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ + uint32_t esc_seq2:8; + /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq2_char0:8; + /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ + uint32_t esc_seq2_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf3_reg_t; + +/** Type of pkt_thres register + * UCHI Packet Length Configuration Register + */ +typedef union { + struct { + /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ + uint32_t pkt_thrs:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_pkt_thres_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * UHCI Interrupt Raw Register + */ +typedef union { + struct { + /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ + uint32_t rx_start_int_raw:1; + /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ + uint32_t tx_start_int_raw:1; + /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ + uint32_t tx_hung_int_raw:1; + /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ + uint32_t send_s_reg_q_int_raw:1; + /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ + uint32_t send_a_reg_q_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ + uint32_t out_eof_int_raw:1; + /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ + uint32_t app_ctrl0_int_raw:1; + /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ + uint32_t app_ctrl1_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_raw_reg_t; + +/** Type of int_st register + * UHCI Interrupt Status Register + */ +typedef union { + struct { + /** rx_start_int_st : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_st:1; + /** tx_start_int_st : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_st:1; + /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_st:1; + /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_st:1; + /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_st:1; + /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_st:1; + /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_st_reg_t; + +/** Type of int_ena register + * UHCI Interrupt Enable Register + */ +typedef union { + struct { + /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_ena:1; + /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_ena:1; + /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_ena:1; + /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_ena:1; + /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_ena:1; + /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_ena:1; + /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_ena_reg_t; + +/** Type of int_clr register + * UHCI Interrupt Clear Register + */ +typedef union { + struct { + /** rx_start_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_clr:1; + /** tx_start_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_clr:1; + /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_clr:1; + /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_clr:1; + /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_clr:1; + /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_clr:1; + /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_clr_reg_t; + + +/** Group: UHCI Status Register */ +/** Type of state0 register + * UHCI Receive Status Register + */ +typedef union { + struct { + /** rx_err_cause : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ + uint32_t rx_err_cause:3; + /** decode_state : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ + uint32_t decode_state:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} uhci_state0_reg_t; + +/** Type of state1 register + * UHCI Transmit Status Register + */ +typedef union { + struct { + /** encode_state : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ + uint32_t encode_state:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} uhci_state1_reg_t; + +/** Type of rx_head register + * UHCI Head Register + */ +typedef union { + struct { + /** rx_head : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ + uint32_t rx_head:32; + }; + uint32_t val; +} uhci_rx_head_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UHCI Version Register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ + uint32_t date:32; + }; + uint32_t val; +} uhci_date_reg_t; + + +typedef struct uhci_dev_t { + volatile uhci_conf0_reg_t conf0; + volatile uhci_int_raw_reg_t int_raw; + volatile uhci_int_st_reg_t int_st; + volatile uhci_int_ena_reg_t int_ena; + volatile uhci_int_clr_reg_t int_clr; + volatile uhci_conf1_reg_t conf1; + volatile uhci_state0_reg_t state0; + volatile uhci_state1_reg_t state1; + volatile uhci_escape_conf_reg_t escape_conf; + volatile uhci_hung_conf_reg_t hung_conf; + volatile uhci_ack_num_reg_t ack_num; + volatile uhci_rx_head_reg_t rx_head; + volatile uhci_quick_sent_reg_t quick_sent; + volatile struct { + uhci_reg_qn_word0_reg_t word0; + uhci_reg_qn_word1_reg_t word1; + } q_data[7]; + volatile uhci_esc_conf0_reg_t esc_conf0; + volatile uhci_esc_conf1_reg_t esc_conf1; + volatile uhci_esc_conf2_reg_t esc_conf2; + volatile uhci_esc_conf3_reg_t esc_conf3; + volatile uhci_pkt_thres_reg_t pkt_thres; + volatile uhci_date_reg_t date; +} uhci_dev_t; + +extern uhci_dev_t UHCI0; + +#ifndef __cplusplus +_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 00000000000..5bc71a9d1b9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1188 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 00000000000..3c87b7a8137 --- /dev/null +++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,941 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t test_enable:1; + /** test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t test_usb_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t usb_mem_pd:1; + /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t rts:1; + /** dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t dtr:1; + /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bdata_bits:8; + /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bparity_type:8; + /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_in_afifo_reset_wr:1; + /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_in_afifo_reset_rd:1; + /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_out_afifo_reset_wr:1; + /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_out_afifo_reset_rd:1; + /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_out_afifo_rempty:1; + /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t jtag_in_flush_int_raw:1; + /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t sof_int_raw:1; + /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_out_recv_pkt_int_raw:1; + /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_in_empty_int_raw:1; + /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t pid_err_int_raw:1; + /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t crc5_err_int_raw:1; + /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t crc16_err_int_raw:1; + /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t stuff_err_int_raw:1; + /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t in_token_rec_in_ep1_int_raw:1; + /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t usb_bus_reset_int_raw:1; + /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t out_ep1_zero_payload_int_raw:1; + /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t out_ep2_zero_payload_int_raw:1; + /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t rts_chg_int_raw:1; + /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t dtr_chg_int_raw:1; + /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t get_line_code_int_raw:1; + /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_st:1; + /** sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_st:1; + /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ + uint32_t serial_out_recv_pkt_int_st:1; + /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_st:1; + /** pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_st:1; + /** crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_st:1; + /** crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_st:1; + /** stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_st:1; + /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ + uint32_t in_token_rec_in_ep1_int_st:1; + /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_st:1; + /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep1_zero_payload_int_st:1; + /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep2_zero_payload_int_st:1; + /** rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_st:1; + /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_st:1; + /** get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_st:1; + /** set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_ena:1; + /** sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_ena:1; + /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_ena:1; + /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_ena:1; + /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_ena:1; + /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_ena:1; + /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_ena:1; + /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_ena:1; + /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_ena:1; + /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_ena:1; + /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_ena:1; + /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_ena:1; + /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_ena:1; + /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_ena:1; + /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_ena:1; + /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_clr:1; + /** sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_clr:1; + /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_clr:1; + /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_clr:1; + /** pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_clr:1; + /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_clr:1; + /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_clr:1; + /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_clr:1; + /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_clr:1; + /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_clr:1; + /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_clr:1; + /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_clr:1; + /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_clr:1; + /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_clr:1; + /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_clr:1; + /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t in_fifo_cnt:2; + /** in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t in_fifo_empty:1; + /** in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t in_fifo_full:1; + /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t out_fifo_cnt:2; + /** out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t out_fifo_empty:1; + /** out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t out_fifo_full:1; + /** in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t in_fifo_reset:1; + /** out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t in_ep0_state:2; + /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t in_ep0_wr_addr:7; + /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t in_ep1_state:2; + /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t in_ep1_wr_addr:7; + /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t in_ep2_state:2; + /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t in_ep2_wr_addr:7; + /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t in_ep3_state:2; + /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t in_ep3_wr_addr:7; + /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t out_ep0_state:2; + /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t out_ep0_wr_addr:7; + /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t out_ep1_state:2; + /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t out_ep1_wr_addr:7; + /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t out_ep1_rd_addr:7; + /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t out_ep2_state:2; + /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t out_ep2_wr_addr:7; + /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t bchar_format:8; + /** bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t bparity_type:8; + /** bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct usb_serial_jtag_dev_t { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + uint32_t reserved_06c[5]; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/interrupts.c b/components/soc/esp32c5/interrupts.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld new file mode 100644 index 00000000000..2228855965a --- /dev/null +++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C0 = 0x60004000 ); +PROVIDE ( UHCI0 = 0x60005000 ); +PROVIDE ( RMT = 0x60006000 ); +PROVIDE ( LEDC = 0x60007000 ); +PROVIDE ( TIMERG0 = 0x60008000 ); +PROVIDE ( TIMERG1 = 0x60009000 ); +PROVIDE ( SYSTIMER = 0x6000A000 ); +PROVIDE ( TWAI0 = 0x6000B000 ); +PROVIDE ( I2S = 0x6000C000 ); +PROVIDE ( TWAI1 = 0x6000D000 ); +PROVIDE ( APB_SARADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( I2C1 = 0x60011000 ); +PROVIDE ( PCNT = 0x60012000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( MCPWM = 0x60014000 ); +PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( PVT_MONITOR = 0x60019000 ); + +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); +PROVIDE ( BITSCRAMBLER = 0x60082000 ); +PROVIDE ( KEYMNG = 0x60087000 ); +PROVIDE ( AES = 0x60088000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( RSA = 0x6008A000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( DS = 0x6008C000 ); +PROVIDE ( HMAC = 0x6008D000 ); +PROVIDE ( ECDSA = 0x6008E000 ); + +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091f00 ); +PROVIDE ( SDM = 0x60091f00 ); +PROVIDE ( GLITCH_FILTER = 0x60091f30 ); +PROVIDE ( GPIO_ETM = 0x60091f60 ); +PROVIDE ( MEM_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( LP_APM0 = 0x60099800 ); +PROVIDE ( MISC = 0x6009F000 ); + +PROVIDE ( MODEM = 0x600A4000 ); +PROVIDE ( MODEM_PWR = 0x600AD000 ); + +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( EFUSE = 0x600B0800 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_UART = 0x600B1400 ); +PROVIDE ( LP_I2C = 0x600B1800 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( LP_IO = 0x600B2000 ); +PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 ); +PROVIDE ( LPPERI = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( HUK = 0x600B3000 ); +PROVIDE ( LP_TEE = 0x600B3400 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( OTP_DEBUG = 0x600B3C00 ); + +PROVIDE ( TRACE = 0x600C0000 ); +PROVIDE ( ASSIST_DEBUG = 0x600C2000 ); +PROVIDE ( INTPRI = 0x600C5000 ); +PROVIDE ( CACHE = 0x600C8000 ); diff --git a/components/soc/esp32c5/uart_periph.c b/components/soc/esp32c5/uart_periph.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index fbca618fb76..010768937b5 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -219,6 +219,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_RNG_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y @@ -375,7 +379,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 4 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE hex default 0x80000000 @@ -459,6 +463,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y +config SOC_GPIO_IN_RANGE_MAX + int + default 30 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 30 + config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 diff --git a/components/soc/esp32c6/include/soc/ieee802154_reg.h b/components/soc/esp32c6/include/soc/ieee802154_reg.h index 978ef141bc7..db8e6e12bfe 100644 --- a/components/soc/esp32c6/include/soc/ieee802154_reg.h +++ b/components/soc/esp32c6/include/soc/ieee802154_reg.h @@ -471,32 +471,32 @@ extern "C" { #define IEEE802154_SFD_TIMEOUT_CNT_CLEAR_S 14 #define IEEE802154_CRC_ERROR_CNT_CLEAR (BIT(13)) #define IEEE802154_CRC_ERROR_CNT_CLEAR_S 13 -#define IEEE802154_ED_ABORT_CNT_CLEAR (BIT(12)) -#define IEEE802154_ED_ABORT_CNT_CLEAR_S 12 -#define IEEE802154_CCA_FAIL_CNT_CLEAR (BIT(11)) -#define IEEE802154_CCA_FAIL_CNT_CLEAR_S 11 -#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR (BIT(10)) -#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR_S 10 -#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR (BIT(9)) -#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR_S 9 -#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR (BIT(8)) -#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR_S 8 -#define IEEE802154_RX_RESTART_CNT_CLEAR (BIT(7)) -#define IEEE802154_RX_RESTART_CNT_CLEAR_S 7 +#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR (BIT(12)) +#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR_S 12 +#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR (BIT(11)) +#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR_S 11 +#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR (BIT(10)) +#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR_S 10 +#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR (BIT(9)) +#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR_S 9 +#define IEEE802154_RX_RESTART_CNT_CLEAR (BIT(8)) +#define IEEE802154_RX_RESTART_CNT_CLEAR_S 8 +#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR (BIT(7)) +#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR_S 7 #define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR (BIT(6)) #define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR_S 6 -#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR (BIT(5)) -#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR_S 5 -#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR (BIT(4)) -#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR_S 4 -#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR (BIT(3)) -#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR_S 3 -#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR (BIT(2)) -#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR_S 2 -#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR (BIT(1)) -#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR_S 1 -#define IEEE802154_CCA_BUSY_CNT_CLEAR (BIT(0)) -#define IEEE802154_CCA_BUSY_CNT_CLEAR_S 0 +#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR (BIT(5)) +#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR_S 5 +#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR (BIT(4)) +#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR_S 4 +#define IEEE802154_ED_ABORT_CNT_CLEAR (BIT(3)) +#define IEEE802154_ED_ABORT_CNT_CLEAR_S 3 +#define IEEE802154_CCA_FAIL_CNT_CLEAR (BIT(2)) +#define IEEE802154_CCA_FAIL_CNT_CLEAR_S 2 +#define IEEE802154_CCA_BUSY_CNT_CLEAR (BIT(1)) +#define IEEE802154_CCA_BUSY_CNT_CLEAR_S 1 +#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR (BIT(0)) +#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR_S 0 #define IEEE802154_MAC_DATE_REG (IEEE802154_REG_BASE + 0x0184) #define IEEE802154_MAC_DATE 0xFFFFFFFF diff --git a/components/soc/esp32c6/include/soc/interrupts.h b/components/soc/esp32c6/include/soc/interrupts.h index 495f1d9fc11..5448dfeece6 100644 --- a/components/soc/esp32c6/include/soc/interrupts.h +++ b/components/soc/esp32c6/include/soc/interrupts.h @@ -61,8 +61,8 @@ typedef enum { ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ - ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/ + ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/ ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ diff --git a/components/soc/esp32c6/include/soc/lpperi_reg.h b/components/soc/esp32c6/include/soc/lpperi_reg.h index 80b4d32f865..b39b2f353f6 100644 --- a/components/soc/esp32c6/include/soc/lpperi_reg.h +++ b/components/soc/esp32c6/include/soc/lpperi_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -137,13 +137,13 @@ extern "C" { * need_des */ #define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) -/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; +/** LPPERI_RNG_DATA : RO; bitpos: [31:0]; default: 0; * need_des */ -#define LPPERI_RND_DATA 0xFFFFFFFFU -#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) -#define LPPERI_RND_DATA_V 0xFFFFFFFFU -#define LPPERI_RND_DATA_S 0 +#define LPPERI_RNG_DATA 0xFFFFFFFFU +#define LPPERI_RNG_DATA_M (LPPERI_RNG_DATA_V << LPPERI_RNG_DATA_S) +#define LPPERI_RNG_DATA_V 0xFFFFFFFFU +#define LPPERI_RNG_DATA_S 0 /** LPPERI_CPU_REG register * need_des diff --git a/components/soc/esp32c6/include/soc/lpperi_struct.h b/components/soc/esp32c6/include/soc/lpperi_struct.h index 278301712c2..8dc3cde04fc 100644 --- a/components/soc/esp32c6/include/soc/lpperi_struct.h +++ b/components/soc/esp32c6/include/soc/lpperi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -101,10 +101,10 @@ typedef union { */ typedef union { struct { - /** rnd_data : RO; bitpos: [31:0]; default: 0; + /** rng_data : RO; bitpos: [31:0]; default: 0; * need_des */ - uint32_t rnd_data:32; + uint32_t rng_data:32; }; uint32_t val; } lpperi_rng_data_reg_t; diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 97fe076c6f3..2641a8feaf7 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -23,10 +23,10 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6 +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 -#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index d82e4dba855..8d8054ca1db 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -4,11 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The long term plan is to have a single soc_caps.h for each peripheral. -// During the refactoring and multichip support development process, we -// seperate these information into periph_caps.h for each peripheral and -// include them here. - /* * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` @@ -16,11 +11,8 @@ * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py -d 'components/soc/esp32c6/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` - * -*/ + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ #pragma once @@ -79,6 +71,7 @@ #define SOC_ASSIST_DEBUG_SUPPORTED 1 #define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 +#define SOC_RNG_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 @@ -149,9 +142,9 @@ #define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller -#define SOC_CPU_BREAKPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes #define SOC_CPU_HAS_PMA 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 @@ -198,6 +191,10 @@ #define SOC_GPIO_VALID_GPIO_MASK ((1U<=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 #define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000) #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000) -#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) @@ -225,7 +225,7 @@ #define SOC_DEBUG_HIGH 0x28000000 // Start (highest address) of ROM boot stack, only relevant during early boot -#define SOC_ROM_STACK_START 0x4ff5abd0 +#define SOC_ROM_STACK_START 0x4ff3cfc0 #define SOC_ROM_STACK_SIZE 0x2000 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 835e1c354c3..1356308ff8f 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -4,11 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The long term plan is to have a single soc_caps.h for each peripheral. -// During the refactoring and multichip support development process, we -// seperate these information into periph_caps.h for each peripheral and -// include them here. - /* * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` @@ -16,11 +11,8 @@ * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32p4/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` - * -*/ + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ #pragma once @@ -32,8 +24,11 @@ #define SOC_GDMA_SUPPORTED 1 #define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_AXI_GDMA_SUPPORTED 1 +#define SOC_DW_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 #define SOC_PCNT_SUPPORTED 1 +// #define SOC_LCDCAM_SUPPORTED 1 // TODO: IDF-7465 +// #define SOC_MIPI_DSI_SUPPORTED 1 // TODO: IDF-7085 #define SOC_MCPWM_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_ETM_SUPPORTED 1 @@ -43,18 +38,18 @@ // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: IDF-7496 // #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: IDF-7482 #define SOC_SUPPORTS_SECURE_DL_MODE 1 -// #define SOC_RISCV_COPROC_SUPPORTED 1 +#define SOC_ULP_SUPPORTED 1 +#define SOC_LP_CORE_SUPPORTED 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_I2S_SUPPORTED 1 -// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476 -// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551 +#define SOC_SDM_SUPPORTED 1 #define SOC_GPSPI_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1 -#define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491 +#define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // #define SOC_AES_SUPPORTED 1 //TODO: IDF-6519 #define SOC_MPI_SUPPORTED 1 @@ -71,7 +66,7 @@ // #define SOC_APM_SUPPORTED 1 //TODO: IDF-7542 // #define SOC_PMU_SUPPORTED 1 //TODO: IDF-7531 // #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531 -// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: IDF-7532 +#define SOC_LP_TIMER_SUPPORTED 1 // #define SOC_ULP_LP_UART_SUPPORTED 1 //TODO: IDF-7533 #define SOC_LP_GPIO_MATRIX_SUPPORTED 1 #define SOC_LP_PERIPHERALS_SUPPORTED 1 @@ -83,6 +78,9 @@ // #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: IDF-7565 #define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 +// #define SOC_TOUCH_SENSOR_SUPPORTED 1 //TODO: IDF-7477 +// #define SOC_RNG_SUPPORTED 1 //TODO: IDF-6522 +#define SOC_MULTI_USAGE_LDO_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 @@ -152,10 +150,11 @@ #define SOC_CPU_HAS_FPU 1 #define SOC_CPU_HAS_FPU_EXT_ILL_BUG 1 // EXT_ILL CSR doesn't support FLW/FSW #define SOC_CPU_COPROC_NUM 2 +#define SOC_HP_CPU_HAS_MULTIPLE_CORES 1 // Convenience boolean macro used to determine if a target has multiple cores. -#define SOC_CPU_BREAKPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 3 +#define SOC_CPU_WATCHPOINTS_NUM 3 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100 // bytes #define SOC_CPU_HAS_PMA 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 @@ -177,7 +176,7 @@ #define SOC_GDMA_NUM_GROUPS_MAX 2 #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 #define SOC_AXI_GDMA_SUPPORT_PSRAM 1 -// #define SOC_GDMA_SUPPORT_ETM 1 +#define SOC_GDMA_SUPPORT_ETM 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups @@ -186,7 +185,7 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-P4 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U -#define SOC_GPIO_PIN_COUNT 57 +#define SOC_GPIO_PIN_COUNT 55 // #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: IDF-7481 // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: IDF-7481 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 @@ -202,12 +201,16 @@ // GPIO0~15 on ESP32P4 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) -#define SOC_GPIO_VALID_GPIO_MASK (0x01FFFFFFFFFFFFFF) +#define SOC_GPIO_VALID_GPIO_MASK (0x007FFFFFFFFFFFFF) #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK + +#define SOC_GPIO_IN_RANGE_MAX 54 +#define SOC_GPIO_OUT_RANGE_MAX 54 + #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF) -// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_56) -#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x01FFFFFFFFFF0000ULL +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) @@ -321,6 +324,16 @@ // #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */ #define SOC_RMT_SUPPORT_DMA 1 /*!< RMT peripheral can connect to DMA channel */ +/*-------------------------- LCD CAPS ----------------------------------------*/ +/* I80 bus and RGB timing generator can't work at the same time */ +// #define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */ // TODO: IDF-7465 +// #define SOC_LCD_RGB_SUPPORTED (1) /*!< RGB LCD is supported */ // TODO: IDF-7465 +#define SOC_LCD_I80_BUSES (1U) /*!< Has one LCD Intel 8080 bus */ +#define SOC_LCD_RGB_PANELS (1U) /*!< Support one RGB LCD panel */ +#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */ +#define SOC_LCD_RGB_DATA_WIDTH (24) /*!< Number of LCD data lines */ +#define SOC_LCD_SUPPORT_RGB_YUV_CONV (1) /*!< Support color format conversion between RGB and YUV */ + /*-------------------------- MCPWM CAPS --------------------------------------*/ #define SOC_MCPWM_GROUPS (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has @@ -395,7 +408,7 @@ /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_GROUPS 1U -#define SOC_SDM_CHANNELS_PER_GROUP 4 +#define SOC_SDM_CHANNELS_PER_GROUP 8 #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1 #define SOC_SDM_CLK_SUPPORT_XTAL 1 @@ -445,7 +458,7 @@ #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) -// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event //TODO: IDF-7486 +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part @@ -463,6 +476,13 @@ /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ #define SOC_MWDT_SUPPORT_XTAL (1) +/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ +#define SOC_TOUCH_SENSOR_VERSION (3) // Hardware version of touch sensor +#define SOC_TOUCH_SENSOR_NUM (14) // Touch available channel number. Actually there are 15 Touch channels, but channel 14 is not pinned out, limit to 14 channels +#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) // Sopport touch proximity channel number. +#define SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED (1) // Sopport touch proximity channel measure done interrupt type. +#define SOC_TOUCH_SAMPLER_NUM (3) // The sampler number in total, each sampler can be used to sample on one frequency + /*-------------------------- TWAI CAPS ---------------------------------------*/ #define SOC_TWAI_CONTROLLER_NUM 3 #define SOC_TWAI_CLK_SUPPORT_XTAL 1 @@ -471,11 +491,12 @@ #define SOC_TWAI_SUPPORTS_RX_STATUS 1 /*-------------------------- eFuse CAPS----------------------------*/ -#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 #define SOC_EFUSE_DIS_PAD_JTAG 1 #define SOC_EFUSE_DIS_USB_JTAG 1 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 #define SOC_EFUSE_SOFT_DIS_JTAG 1 +/* Capability to disable the MSPI access in download mode */ +#define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1 /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 @@ -487,7 +508,9 @@ /*-------------------------- Flash Encryption CAPS----------------------------*/ #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) #define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 /*-------------------------- MEMPROT CAPS ------------------------------------*/ @@ -540,6 +563,7 @@ #define SOC_MODEM_CLOCK_IS_INDEPENDENT (0) #define SOC_CLK_APLL_SUPPORTED (1) /*!< Support Audio PLL */ +#define SOC_CLK_MPLL_SUPPORTED (1) /*!< Support MSPI PLL */ #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */ #define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ diff --git a/components/soc/esp32p4/include/soc/touch_sensor_channel.h b/components/soc/esp32p4/include/soc/touch_sensor_channel.h new file mode 100644 index 00000000000..77643a5742b --- /dev/null +++ b/components/soc/esp32p4/include/soc/touch_sensor_channel.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//Touch channels + +/* Note: T14 is an internal channel that does not have a corresponding external GPIO. */ + +#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM0 +#define TOUCH_PAD_NUM0_GPIO_NUM 2 + +#define TOUCH_PAD_GPIO3_CHANNEL TOUCH_PAD_NUM1 +#define TOUCH_PAD_NUM1_GPIO_NUM 3 + +#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM2 +#define TOUCH_PAD_NUM2_GPIO_NUM 4 + +#define TOUCH_PAD_GPIO5_CHANNEL TOUCH_PAD_NUM3 +#define TOUCH_PAD_NUM3_GPIO_NUM 5 + +#define TOUCH_PAD_GPIO6_CHANNEL TOUCH_PAD_NUM4 +#define TOUCH_PAD_NUM4_GPIO_NUM 6 + +#define TOUCH_PAD_GPIO7_CHANNEL TOUCH_PAD_NUM5 +#define TOUCH_PAD_NUM5_GPIO_NUM 7 + +#define TOUCH_PAD_GPIO8_CHANNEL TOUCH_PAD_NUM6 +#define TOUCH_PAD_NUM6_GPIO_NUM 8 + +#define TOUCH_PAD_GPIO9_CHANNEL TOUCH_PAD_NUM7 +#define TOUCH_PAD_NUM7_GPIO_NUM 9 + +#define TOUCH_PAD_GPIO10_CHANNEL TOUCH_PAD_NUM8 +#define TOUCH_PAD_NUM8_GPIO_NUM 10 + +#define TOUCH_PAD_GPIO11_CHANNEL TOUCH_PAD_NUM9 +#define TOUCH_PAD_NUM9_GPIO_NUM 11 + +#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM10 +#define TOUCH_PAD_NUM10_GPIO_NUM 12 + +#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM11 +#define TOUCH_PAD_NUM11_GPIO_NUM 13 + +#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM12 +#define TOUCH_PAD_NUM12_GPIO_NUM 14 + +#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM13 +#define TOUCH_PAD_NUM13_GPIO_NUM 15 diff --git a/components/soc/esp32p4/include/soc/touch_struct.h b/components/soc/esp32p4/include/soc/touch_struct.h index d94b69cfe6f..4c330430219 100644 --- a/components/soc/esp32p4/include/soc/touch_struct.h +++ b/components/soc/esp32p4/include/soc/touch_struct.h @@ -148,7 +148,7 @@ typedef union { } rtc_touch_int_clr_reg_t; /** Type of chn_status register - * need_des + * Latched channel status */ typedef union { struct { @@ -169,337 +169,29 @@ typedef union { uint32_t val; } rtc_touch_chn_status_reg_t; -/** Type of status_0 register - * need_des - */ -typedef union { - struct { - /** pad0_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad0_data:16; - /** pad0_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad0_debounce_cnt:3; - /** pad0_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad0_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_0_reg_t; - -/** Type of status_1 register - * need_des - */ -typedef union { - struct { - /** pad1_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad1_data:16; - /** pad1_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad1_debounce_cnt:3; - /** pad1_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad1_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_1_reg_t; - -/** Type of status_2 register - * need_des - */ -typedef union { - struct { - /** pad2_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad2_data:16; - /** pad2_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad2_debounce_cnt:3; - /** pad2_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad2_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_2_reg_t; - -/** Type of status_3 register - * need_des - */ -typedef union { - struct { - /** pad3_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad3_data:16; - /** pad3_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad3_debounce_cnt:3; - /** pad3_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad3_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_3_reg_t; - -/** Type of status_4 register - * need_des - */ -typedef union { - struct { - /** pad4_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad4_data:16; - /** pad4_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad4_debounce_cnt:3; - /** pad4_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad4_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_4_reg_t; - -/** Type of status_5 register - * need_des - */ -typedef union { - struct { - /** pad5_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad5_data:16; - /** pad5_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad5_debounce_cnt:3; - /** pad5_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad5_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_5_reg_t; - -/** Type of status_6 register - * need_des - */ -typedef union { - struct { - /** pad6_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad6_data:16; - /** pad6_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad6_debounce_cnt:3; - /** pad6_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad6_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_6_reg_t; - -/** Type of status_7 register +/** Type of chn_data register * need_des */ typedef union { struct { - /** pad7_data : RO; bitpos: [15:0]; default: 0; + /** pad_data : RO; bitpos: [15:0]; default: 0; * need_des */ - uint32_t pad7_data:16; - /** pad7_debounce_cnt : RO; bitpos: [18:16]; default: 0; + uint32_t pad_data:16; + /** pad_debounce_cnt : RO; bitpos: [18:16]; default: 0; * need_des */ - uint32_t pad7_debounce_cnt:3; - /** pad7_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + uint32_t pad_debounce_cnt:3; + /** pad_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; * need_des */ - uint32_t pad7_neg_noise_cnt:4; + uint32_t pad_neg_noise_cnt:4; uint32_t reserved_23:9; }; uint32_t val; -} rtc_touch_status_7_reg_t; +} rtc_touch_chn_data_reg_t; -/** Type of status_8 register - * need_des - */ -typedef union { - struct { - /** pad8_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad8_data:16; - /** pad8_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad8_debounce_cnt:3; - /** pad8_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad8_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_8_reg_t; - -/** Type of status_9 register - * need_des - */ -typedef union { - struct { - /** pad9_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad9_data:16; - /** pad9_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad9_debounce_cnt:3; - /** pad9_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad9_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_9_reg_t; - -/** Type of status_10 register - * need_des - */ -typedef union { - struct { - /** pad10_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad10_data:16; - /** pad10_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad10_debounce_cnt:3; - /** pad10_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad10_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_10_reg_t; - -/** Type of status_11 register - * need_des - */ -typedef union { - struct { - /** pad11_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad11_data:16; - /** pad11_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad11_debounce_cnt:3; - /** pad11_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad11_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_11_reg_t; - -/** Type of status_12 register - * need_des - */ -typedef union { - struct { - /** pad12_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad12_data:16; - /** pad12_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad12_debounce_cnt:3; - /** pad12_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad12_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_12_reg_t; - -/** Type of status_13 register - * need_des - */ -typedef union { - struct { - /** pad13_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad13_data:16; - /** pad13_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad13_debounce_cnt:3; - /** pad13_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad13_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_13_reg_t; - -/** Type of status_14 register - * need_des - */ -typedef union { - struct { - /** pad14_data : RO; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t pad14_data:16; - /** pad14_debounce_cnt : RO; bitpos: [18:16]; default: 0; - * need_des - */ - uint32_t pad14_debounce_cnt:3; - /** pad14_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t pad14_neg_noise_cnt:4; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_touch_status_14_reg_t; - -/** Type of status_15 register +/** Type of slp_ch_data register * need_des */ typedef union { @@ -519,9 +211,9 @@ typedef union { uint32_t reserved_23:9; }; uint32_t val; -} rtc_touch_status_15_reg_t; +} rtc_touch_slp_ch_data_reg_t; -/** Type of status_16 register +/** Type of aprch_ch_data register * need_des */ typedef union { @@ -544,9 +236,9 @@ typedef union { uint32_t slp_approach_cnt:8; }; uint32_t val; -} rtc_touch_status_16_reg_t; +} rtc_touch_aprch_ch_data_reg_t; -/** Type of status_17 register +/** Type of config register * need_des */ typedef union { @@ -578,10 +270,10 @@ typedef union { uint32_t reserved_25:7; }; uint32_t val; -} rtc_touch_status_17_reg_t; +} rtc_touch_sampler_status_reg_t; /** Type of chn_tmp_status register - * need_des + * Realtime channel status */ typedef union { struct { @@ -625,29 +317,16 @@ typedef struct { volatile rtc_touch_int_ena_reg_t int_ena; volatile rtc_touch_int_clr_reg_t int_clr; volatile rtc_touch_chn_status_reg_t chn_status; - volatile rtc_touch_status_0_reg_t status_0; - volatile rtc_touch_status_1_reg_t status_1; - volatile rtc_touch_status_2_reg_t status_2; - volatile rtc_touch_status_3_reg_t status_3; - volatile rtc_touch_status_4_reg_t status_4; - volatile rtc_touch_status_5_reg_t status_5; - volatile rtc_touch_status_6_reg_t status_6; - volatile rtc_touch_status_7_reg_t status_7; - volatile rtc_touch_status_8_reg_t status_8; - volatile rtc_touch_status_9_reg_t status_9; - volatile rtc_touch_status_10_reg_t status_10; - volatile rtc_touch_status_11_reg_t status_11; - volatile rtc_touch_status_12_reg_t status_12; - volatile rtc_touch_status_13_reg_t status_13; - volatile rtc_touch_status_14_reg_t status_14; - volatile rtc_touch_status_15_reg_t status_15; - volatile rtc_touch_status_16_reg_t status_16; - volatile rtc_touch_status_17_reg_t status_17; + volatile rtc_touch_chn_data_reg_t chn_data[15]; + volatile rtc_touch_slp_ch_data_reg_t slp_ch_data; + volatile rtc_touch_aprch_ch_data_reg_t aprch_ch_data; + volatile rtc_touch_sampler_status_reg_t sampler_status; volatile rtc_touch_chn_tmp_status_reg_t chn_tmp_status; uint32_t reserved_060[40]; volatile rtc_touch_date_reg_t date; } rtc_touch_dev_t; +extern rtc_touch_dev_t LP_TOUCH; #ifndef __cplusplus _Static_assert(sizeof(rtc_touch_dev_t) == 0x104, "Invalid size of rtc_touch_dev_t structure"); diff --git a/components/soc/esp32p4/lcd_periph.c b/components/soc/esp32p4/lcd_periph.c new file mode 100644 index 00000000000..a45836dc7cd --- /dev/null +++ b/components/soc/esp32p4/lcd_periph.c @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/lcd_periph.h" +#include "soc/gpio_sig_map.h" + +const lcd_signal_conn_t lcd_periph_signals = { + .buses = { + [0] = { + .module = PERIPH_LCD_CAM_MODULE, + .irq_id = ETS_LCD_CAM_INTR_SOURCE, + .data_sigs = { + LCD_DATA_OUT_PAD_OUT0_IDX, + LCD_DATA_OUT_PAD_OUT1_IDX, + LCD_DATA_OUT_PAD_OUT2_IDX, + LCD_DATA_OUT_PAD_OUT3_IDX, + LCD_DATA_OUT_PAD_OUT4_IDX, + LCD_DATA_OUT_PAD_OUT5_IDX, + LCD_DATA_OUT_PAD_OUT6_IDX, + LCD_DATA_OUT_PAD_OUT7_IDX, + LCD_DATA_OUT_PAD_OUT8_IDX, + LCD_DATA_OUT_PAD_OUT9_IDX, + LCD_DATA_OUT_PAD_OUT10_IDX, + LCD_DATA_OUT_PAD_OUT11_IDX, + LCD_DATA_OUT_PAD_OUT12_IDX, + LCD_DATA_OUT_PAD_OUT13_IDX, + LCD_DATA_OUT_PAD_OUT14_IDX, + LCD_DATA_OUT_PAD_OUT15_IDX, + LCD_DATA_OUT_PAD_OUT16_IDX, + LCD_DATA_OUT_PAD_OUT17_IDX, + LCD_DATA_OUT_PAD_OUT18_IDX, + LCD_DATA_OUT_PAD_OUT19_IDX, + LCD_DATA_OUT_PAD_OUT20_IDX, + LCD_DATA_OUT_PAD_OUT21_IDX, + LCD_DATA_OUT_PAD_OUT22_IDX, + LCD_DATA_OUT_PAD_OUT23_IDX, + }, + .cs_sig = LCD_CS_PAD_OUT_IDX, + .dc_sig = LCD_DC_PAD_OUT_IDX, + .wr_sig = LCD_PCLK_PAD_OUT_IDX + } + }, + .panels = { + [0] = { + .module = PERIPH_LCD_CAM_MODULE, + .irq_id = ETS_LCD_CAM_INTR_SOURCE, + .data_sigs = { + LCD_DATA_OUT_PAD_OUT0_IDX, + LCD_DATA_OUT_PAD_OUT1_IDX, + LCD_DATA_OUT_PAD_OUT2_IDX, + LCD_DATA_OUT_PAD_OUT3_IDX, + LCD_DATA_OUT_PAD_OUT4_IDX, + LCD_DATA_OUT_PAD_OUT5_IDX, + LCD_DATA_OUT_PAD_OUT6_IDX, + LCD_DATA_OUT_PAD_OUT7_IDX, + LCD_DATA_OUT_PAD_OUT8_IDX, + LCD_DATA_OUT_PAD_OUT9_IDX, + LCD_DATA_OUT_PAD_OUT10_IDX, + LCD_DATA_OUT_PAD_OUT11_IDX, + LCD_DATA_OUT_PAD_OUT12_IDX, + LCD_DATA_OUT_PAD_OUT13_IDX, + LCD_DATA_OUT_PAD_OUT14_IDX, + LCD_DATA_OUT_PAD_OUT15_IDX, + LCD_DATA_OUT_PAD_OUT16_IDX, + LCD_DATA_OUT_PAD_OUT17_IDX, + LCD_DATA_OUT_PAD_OUT18_IDX, + LCD_DATA_OUT_PAD_OUT19_IDX, + LCD_DATA_OUT_PAD_OUT20_IDX, + LCD_DATA_OUT_PAD_OUT21_IDX, + LCD_DATA_OUT_PAD_OUT22_IDX, + LCD_DATA_OUT_PAD_OUT23_IDX, + }, + .hsync_sig = LCD_H_SYNC_PAD_OUT_IDX, + .vsync_sig = LCD_V_SYNC_PAD_OUT_IDX, + .pclk_sig = LCD_PCLK_PAD_OUT_IDX, + .de_sig = LCD_H_ENABLE_PAD_OUT_IDX, + } + } +}; diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index dd04e11bb3a..c9ade62618b 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -76,6 +76,7 @@ PROVIDE ( LP_I2C = 0x50122000 ); PROVIDE ( LP_SPI = 0x50123000 ); PROVIDE ( LP_WDT = 0x50116000 ); PROVIDE ( LP_I2S = 0x50125000 ); +PROVIDE ( LP_TOUCH = 0x50128000 ); PROVIDE ( LP_GPIO = 0x5012A000 ); PROVIDE ( LP_I2C_ANA_MST = 0x50124000 ); PROVIDE ( LP_ANA_PERI = 0x50113000 ); diff --git a/components/soc/esp32p4/rtc_io_periph.c b/components/soc/esp32p4/rtc_io_periph.c index 2e1bd96cd33..41285055e49 100644 --- a/components/soc/esp32p4/rtc_io_periph.c +++ b/components/soc/esp32p4/rtc_io_periph.c @@ -62,6 +62,4 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { -1,//GPIO52 -1,//GPIO53 -1,//GPIO54 - -1,//GPIO55 - -1,//GPIO56 }; diff --git a/components/soc/esp32p4/sdm_periph.c b/components/soc/esp32p4/sdm_periph.c index da3f711ad8a..42e2b60d7c7 100644 --- a/components/soc/esp32p4/sdm_periph.c +++ b/components/soc/esp32p4/sdm_periph.c @@ -8,5 +8,30 @@ #include "soc/gpio_sig_map.h" const sigma_delta_signal_conn_t sigma_delta_periph_signals = { - + .channels = { + [0] = { + GPIO_SD0_OUT_IDX + }, + [1] = { + GPIO_SD1_OUT_IDX + }, + [2] = { + GPIO_SD2_OUT_IDX + }, + [3] = { + GPIO_SD3_OUT_IDX + }, + [4] = { + GPIO_SD4_OUT_IDX + }, + [5] = { + GPIO_SD5_OUT_IDX + }, + [6] = { + GPIO_SD6_OUT_IDX + }, + [7] = { + GPIO_SD7_OUT_IDX + } + } }; diff --git a/components/soc/esp32p4/touch_sensor_periph.c b/components/soc/esp32p4/touch_sensor_periph.c new file mode 100644 index 00000000000..03768e697e2 --- /dev/null +++ b/components/soc/esp32p4/touch_sensor_periph.c @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/touch_sensor_periph.h" + +/* Store IO number corresponding to the Touch Sensor channel number. */ +/* Note: T14 is an internal channel that does not have a corresponding external GPIO. */ +const int touch_sensor_channel_io_map[] = { + TOUCH_PAD_NUM0_GPIO_NUM, + TOUCH_PAD_NUM1_GPIO_NUM, + TOUCH_PAD_NUM2_GPIO_NUM, + TOUCH_PAD_NUM3_GPIO_NUM, + TOUCH_PAD_NUM4_GPIO_NUM, + TOUCH_PAD_NUM5_GPIO_NUM, + TOUCH_PAD_NUM6_GPIO_NUM, + TOUCH_PAD_NUM7_GPIO_NUM, + TOUCH_PAD_NUM8_GPIO_NUM, + TOUCH_PAD_NUM9_GPIO_NUM, + TOUCH_PAD_NUM10_GPIO_NUM, + TOUCH_PAD_NUM11_GPIO_NUM, + TOUCH_PAD_NUM12_GPIO_NUM, + TOUCH_PAD_NUM13_GPIO_NUM, + -1, +}; diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index f5813cc2132..e611214dd18 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -191,6 +191,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_RNG_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y @@ -323,7 +327,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE int default 64 @@ -363,6 +367,14 @@ config SOC_GPIO_VALID_GPIO_MASK hex default 0x7FFFFFFFFFFF +config SOC_GPIO_IN_RANGE_MAX + int + default 46 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 45 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x00007FFFFC000000 @@ -739,9 +751,9 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS int default 4 -config SOC_TOUCH_VERSION_2 - bool - default y +config SOC_TOUCH_SENSOR_VERSION + int + default 2 config SOC_TOUCH_SENSOR_NUM int @@ -751,13 +763,9 @@ config SOC_TOUCH_PROXIMITY_CHANNEL_NUM int default 3 -config SOC_TOUCH_PAD_THRESHOLD_MAX - hex - default 0x1FFFFF - -config SOC_TOUCH_PAD_MEASURE_WAIT_MAX - hex - default 0xFF +config SOC_TOUCH_SAMPLER_NUM + int + default 1 config SOC_TWAI_CONTROLLER_NUM int @@ -815,9 +823,9 @@ config SOC_SPIRAM_XIP_SUPPORTED bool default y -config SOC_USB_PERIPH_NUM - bool - default y +config SOC_USB_OTG_PERIPH_NUM + int + default 1 config SOC_SHA_DMA_MAX_BUFFER_SIZE int diff --git a/components/soc/esp32s2/include/soc/reg_base.h b/components/soc/esp32s2/include/soc/reg_base.h index dbc2d2a5ccf..0a809c6ebf7 100644 --- a/components/soc/esp32s2/include/soc/reg_base.h +++ b/components/soc/esp32s2/include/soc/reg_base.h @@ -56,7 +56,6 @@ #define DR_REG_SYSCON_BASE 0x3f426000 #define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ #define DR_REG_I2C1_EXT_BASE 0x3f427000 -#define DR_REG_SPI4_BASE 0x3f437000 #define DR_REG_USB_WRAP_BASE 0x3f439000 #define DR_REG_APB_SARADC_BASE 0x3f440000 #define DR_REG_USB_BASE 0x60080000 diff --git a/components/soc/esp32s2/include/soc/regi2c_defs.h b/components/soc/esp32s2/include/soc/regi2c_defs.h index cc6a05b85aa..034e8569b02 100644 --- a/components/soc/esp32s2/include/soc/regi2c_defs.h +++ b/components/soc/esp32s2/include/soc/regi2c_defs.h @@ -24,7 +24,7 @@ /** * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips + * This is a workaround for calibration error when waking up from light sleep */ #define REGI2C_ANA_CALI_PD_WORKAROUND 1 #define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 37bf49554bf..6d59f416326 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,14 +18,15 @@ #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects //consume this file diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 575df03bf6f..d27ce9eebff 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -31,9 +31,7 @@ * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32s2/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` */ #pragma once @@ -86,6 +84,7 @@ #define SOC_MPU_SUPPORTED 1 #define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 +#define SOC_RNG_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 @@ -142,9 +141,9 @@ #define SOC_CPU_CORES_NUM (1U) #define SOC_CPU_INTR_NUM 32 -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_CHAN_NUM 2 @@ -168,6 +167,9 @@ // GPIO 46 is input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46)) +#define SOC_GPIO_IN_RANGE_MAX 46 +#define SOC_GPIO_OUT_RANGE_MAX 45 + // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_46) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00007FFFFC000000ULL @@ -320,12 +322,11 @@ #define SOC_TIMER_GROUP_TOTAL_TIMERS (4) /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ -#define SOC_TOUCH_VERSION_2 (1) /*!3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 ))) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) /* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s2/include/soc/syscon_reg.h b/components/soc/esp32s2/include/soc/syscon_reg.h index 91d9e153754..62e031b55bb 100644 --- a/components/soc/esp32s2/include/soc/syscon_reg.h +++ b/components/soc/esp32s2/include/soc/syscon_reg.h @@ -443,7 +443,8 @@ extern "C" { #define DPORT_WIFI_CLK_BT_EN_V 0x61 #define DPORT_WIFI_CLK_BT_EN_S 11 /* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ -#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 +#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 +#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M /* Digital team to check */ //bluetooth baseband bit11 diff --git a/components/soc/esp32s2/include/soc/usb_dwc_cfg.h b/components/soc/esp32s2/include/soc/usb_dwc_cfg.h new file mode 100644 index 00000000000..37cdcdf4bf7 --- /dev/null +++ b/components/soc/esp32s2/include/soc/usb_dwc_cfg.h @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* +Configuration Set ID: 1 +*/ + +/* 3.1 Basic Config Parameters */ +#define OTG_MODE 0 +#define OTG_ARCHITECTURE 2 +#define OTG_SINGLE_POINT 1 +#define OTG_ENABLE_LPM 0 +#define OTG_EN_DED_TX_FIFO 1 +#define OTG_EN_DESC_DMA 1 +#define OTG_MULTI_PROC_INTRPT 0 + +/* 3.2 USB Physical Layer Interface Parameters */ +#define OTG_HSPHY_INTERFACE 0 +#define OTG_FSPHY_INTERFACE 1 +#define OTG_ENABLE_IC_USB 0 +#define OTG_I2C_INTERFACE 0 +#define OTG_ADP_SUPPORT 0 +#define OTG_BC_SUPPORT 0 + +/* 3.3 Device Endpoint Configuration Parameters */ +#define OTG_NUM_EPS 6 +#define OTG_NUM_IN_EPS 5 +#define OTG_NUM_CRL_EPS 0 + +/* 3.4 Host Endpoint Configuration Parameters */ +#define OTG_NUM_HOST_CHAN 8 +#define OTG_EN_PERIO_HOST 1 + +/* 3.5 Endpoint Channel FIFO Configuration Parameters */ +#define OTG_DFIFO_DEPTH 256 +#define OTG_DFIFO_DYNAMIC 1 +#define OTG_RX_DFIFO_DEPTH 256 +#define OTG_TX_HNPERIO_DFIFO_DEPTH 256 +#define OTG_TX_NPERIO_DFIFO_DEPTH 256 +#define OTG_TX_HPERIO_DFIFO_DEPTH 256 +#define OTG_NPERIO_TX_QUEUE_DEPTH 4 +#define OTG_PERIO_TX_QUEUE_DEPTH 8 + +/* 3.6 Additional Configuration Options Parameters */ +#define OTG_TRANS_COUNT_WIDTH 16 +#define OTG_PACKET_COUNT_WIDTH 7 +#define OTG_RM_OPT_FEATURES 1 +#define OTG_EN_PWROPT 1 +#define OTG_SYNC_RESET_TYPE 0 +#define OTG_EN_IDDIG_FILTER 1 +#define OTG_EN_VBUSVALID_FILTER 1 +#define OTG_EN_A_VALID_FILTER 1 +#define OTG_EN_B_VALID_FILTER 1 +#define OTG_EN_SESSIONEND_FILTER 1 +#define OTG_EXCP_CNTL_XFER_FLOW 1 +#define OTG_PWR_CLAMP 0 +#define OTG_PWR_SWITCH_POLARITY 0 + +/* 3.7 Endpoint Direction Parameters */ +#define OTG_EP_DIR_1 0 +#define OTG_EP_DIR_2 0 +#define OTG_EP_DIR_3 0 +#define OTG_EP_DIR_4 0 +#define OTG_EP_DIR_5 0 +#define OTG_EP_DIR_6 0 + +/* 3.8 Device Periodic FIFO Depth Parameters */ + +/* 3.9 Device IN Endpoint FIFO Depth Parameters */ +#define OTG_TX_DINEP_DFIFO_DEPTH_1 256 +#define OTG_TX_DINEP_DFIFO_DEPTH_2 256 +#define OTG_TX_DINEP_DFIFO_DEPTH_3 256 +#define OTG_TX_DINEP_DFIFO_DEPTH_4 256 + +/* 3.10 UTMI-To-UTMI Bridge Component Parameters */ +#define U2UB_EN 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2/include/soc/usb_dwc_struct.h b/components/soc/esp32s2/include/soc/usb_dwc_struct.h index 0402c4a83ed..7c9ca381c39 100644 --- a/components/soc/esp32s2/include/soc/usb_dwc_struct.h +++ b/components/soc/esp32s2/include/soc/usb_dwc_struct.h @@ -1,16 +1,21 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include + #ifdef __cplusplus extern "C" { #endif -#include +/* +Registers and fields were generated based on a set of configuration options. +See the ESP32-S2 "usb_dwc_cfg.h" for more details. +*/ /* ---------------------------- Register Types ------------------------------ */ @@ -29,7 +34,7 @@ typedef union { uint32_t hstsethnpen: 1; uint32_t devhnpen: 1; uint32_t ehen: 1; - uint32_t reserved2: 2; + uint32_t reserved_13: 2; uint32_t dbncefltrbypass: 1; uint32_t conidsts: 1; uint32_t dbnctime: 1; @@ -37,23 +42,26 @@ typedef union { uint32_t bsesvld: 1; uint32_t otgver: 1; uint32_t curmod: 1; - uint32_t reserved10: 10; + uint32_t reserved_22: 5; + uint32_t reserved_27: 1; + uint32_t reserved_28: 4; }; uint32_t val; } usb_dwc_gotgctl_reg_t; typedef union { struct { - uint32_t reserved2: 2; + uint32_t reserved_0: 2; uint32_t sesenddet: 1; - uint32_t reserved5: 5; + uint32_t reserved_3: 5; uint32_t sesreqsucstschng: 1; uint32_t hstnegsucstschng: 1; - uint32_t reserved7: 7; + uint32_t reserved_10: 7; uint32_t hstnegdet: 1; uint32_t adevtoutchg: 1; uint32_t dbncedone: 1; - uint32_t reserved12: 12; + uint32_t reserved_20: 1; + uint32_t reserved_21: 11; }; uint32_t val; } usb_dwc_gotgint_reg_t; @@ -63,34 +71,44 @@ typedef union { uint32_t glbllntrmsk: 1; uint32_t hbstlen: 4; uint32_t dmaen: 1; - uint32_t reserved1: 1; + uint32_t reserved_6: 1; uint32_t nptxfemplvl: 1; uint32_t ptxfemplvl: 1; - uint32_t reserved12: 12; + uint32_t reserved_9: 12; uint32_t remmemsupp: 1; uint32_t notialldmawrit: 1; uint32_t ahbsingle: 1; uint32_t invdescendianess: 1; - uint32_t reserved7: 7; + uint32_t reserved_25: 7; }; uint32_t val; - //Checked } usb_dwc_gahbcfg_reg_t; typedef union { struct { uint32_t toutcal: 3; uint32_t phyif: 1; - uint32_t reserved1a: 1; + uint32_t reserved_4: 1; uint32_t fsintf: 1; uint32_t physel: 1; - uint32_t reserved1b: 1; + uint32_t reserved_7: 1; uint32_t srpcap: 1; uint32_t hnpcap: 1; uint32_t usbtrdtim: 4; - uint32_t reserved8: 8; + uint32_t reserved_14: 1; + uint32_t phylpwrclksel: 1; + uint32_t reserved_16: 1; + uint32_t reserved_17: 1; + uint32_t reserved_18: 1; + uint32_t reserved_19: 1; + uint32_t reserved_20: 1; + uint32_t reserved_21: 1; uint32_t termseldlpulse: 1; - uint32_t reserved5: 5; + uint32_t reserved_23: 1; + uint32_t reserved_24: 1; + uint32_t reserved_25: 1; + uint32_t icusbcap: 1; + uint32_t reserved_27: 1; uint32_t txenddelay: 1; uint32_t forcehstmode: 1; uint32_t forcedevmode: 1; @@ -104,11 +122,11 @@ typedef union { uint32_t csftrst: 1; uint32_t piufssftrst: 1; uint32_t frmcntrrst: 1; - uint32_t reserved1: 1; + uint32_t reserved_3: 1; uint32_t rxfflsh: 1; uint32_t txfflsh: 1; uint32_t txfnum: 5; - uint32_t reserved19: 19; + uint32_t reserved_11: 19; uint32_t dmareq: 1; uint32_t ahbidle: 1; }; @@ -117,22 +135,23 @@ typedef union { typedef union { struct { - uint32_t curmod_int: 1; + uint32_t curmod: 1; uint32_t modemis: 1; uint32_t otgint: 1; uint32_t sof: 1; - uint32_t rxflvi: 1; + uint32_t rxflvl: 1; uint32_t nptxfemp: 1; uint32_t ginnakeff: 1; uint32_t goutnakeff: 1; - uint32_t reserved2: 2; + uint32_t reserved_8: 1; + uint32_t reserved_9: 1; uint32_t erlysusp: 1; uint32_t usbsusp: 1; uint32_t usbrst: 1; uint32_t enumdone: 1; uint32_t isooutdrop: 1; uint32_t eopf: 1; - uint32_t reserved1a: 1; + uint32_t reserved_16: 1; uint32_t epmis: 1; uint32_t iepint: 1; uint32_t oepint: 1; @@ -140,10 +159,10 @@ typedef union { uint32_t incompip: 1; uint32_t fetsusp: 1; uint32_t resetdet: 1; - uint32_t prtlnt: 1; - uint32_t hchlnt: 1; + uint32_t prtint: 1; + uint32_t hchint: 1; uint32_t ptxfemp: 1; - uint32_t reserved1b: 1; + uint32_t reserved_27: 1; uint32_t conidstschng: 1; uint32_t disconnint: 1; uint32_t sessreqint: 1; @@ -154,22 +173,23 @@ typedef union { typedef union { struct { - uint32_t reserved1a: 1; + uint32_t reserved_0: 1; uint32_t modemismsk: 1; uint32_t otgintmsk: 1; uint32_t sofmsk: 1; - uint32_t rxflvimsk: 1; + uint32_t rxflvlmsk: 1; uint32_t nptxfempmsk: 1; uint32_t ginnakeffmsk: 1; uint32_t goutnackeffmsk: 1; - uint32_t reserved2: 2; + uint32_t reserved_8: 1; + uint32_t reserved_9: 1; uint32_t erlysuspmsk: 1; uint32_t usbsuspmsk: 1; uint32_t usbrstmsk: 1; uint32_t enumdonemsk: 1; uint32_t isooutdropmsk: 1; uint32_t eopfmsk: 1; - uint32_t reserved1b: 1; + uint32_t reserved_16: 1; uint32_t epmismsk: 1; uint32_t iepintmsk: 1; uint32_t oepintmsk: 1; @@ -177,10 +197,10 @@ typedef union { uint32_t incompipmsk: 1; uint32_t fetsuspmsk: 1; uint32_t resetdetmsk: 1; - uint32_t prtlntmsk: 1; + uint32_t prtintmsk: 1; uint32_t hchintmsk: 1; uint32_t ptxfempmsk: 1; - uint32_t reserved1c: 1; + uint32_t reserved_27: 1; uint32_t conidstschngmsk: 1; uint32_t disconnintmsk: 1; uint32_t sessreqintmsk: 1; @@ -191,12 +211,13 @@ typedef union { typedef union { struct { - uint32_t g_chnum: 4; - uint32_t g_bcnt: 11; - uint32_t g_dpid: 2; - uint32_t g_pktsts: 4; - uint32_t g_fn: 4; - uint32_t reserved7: 7; + uint32_t chnum: 4; + uint32_t bcnt: 11; + uint32_t dpid: 2; + uint32_t pktsts: 4; + uint32_t fn: 4; + uint32_t reserved_25: 6; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_grxstsr_reg_t; @@ -208,7 +229,8 @@ typedef union { uint32_t dpid: 2; uint32_t pktsts: 4; uint32_t fn: 4; - uint32_t reserved7: 7; + uint32_t reserved_25: 6; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_grxstsp_reg_t; @@ -216,7 +238,7 @@ typedef union { typedef union { struct { uint32_t rxfdep: 16; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_grxfsiz_reg_t; @@ -232,10 +254,9 @@ typedef union { typedef union { struct { uint32_t nptxfspcavail: 16; - uint32_t nptxqspcavail: 4; - uint32_t reserved4: 4; + uint32_t nptxqspcavail: 8; uint32_t nptxqtop: 7; - uint32_t reserved1: 1; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_gnptxsts_reg_t; @@ -266,11 +287,11 @@ typedef union { uint32_t periosupport: 1; uint32_t dynfifosizing: 1; uint32_t multiprocintrpt: 1; - uint32_t reserved1a: 1; + uint32_t reserved_21: 1; uint32_t nptxqdepth: 2; uint32_t ptxqdepth: 2; uint32_t tknqdepth: 5; - uint32_t reserved1b: 1; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_ghwcfg2_reg_t; @@ -295,25 +316,25 @@ typedef union { typedef union { struct { - uint32_t g_numdevperioeps: 4; - uint32_t g_partialpwrdn: 1; - uint32_t g_ahbfreq: 1; - uint32_t g_hibernation: 1; - uint32_t g_extendedhibernation: 1; - uint32_t reserved4: 4; - uint32_t g_acgsupt: 1; - uint32_t g_enhancedlpmsupt: 1; - uint32_t g_phydatawidth: 2; - uint32_t g_numctleps: 4; - uint32_t g_iddqfltr: 1; - uint32_t g_vbusvalidfltr: 1; - uint32_t g_avalidfltr: 1; - uint32_t g_bvalidfltr: 1; - uint32_t g_sessendfltr: 1; - uint32_t g_dedfifomode: 1; - uint32_t g_ineps: 4; - uint32_t g_descdmaenabled: 1; - uint32_t g_descdma: 1; + uint32_t numdevperioeps: 4; + uint32_t partialpwrdn: 1; + uint32_t ahbfreq: 1; + uint32_t hibernation: 1; + uint32_t extendedhibernation: 1; + uint32_t reserved_8: 4; + uint32_t acgsupt: 1; + uint32_t enhancedlpmsupt: 1; + uint32_t phydatawidth: 2; + uint32_t numctleps: 4; + uint32_t iddqfltr: 1; + uint32_t vbusvalidfltr: 1; + uint32_t avalidfltr: 1; + uint32_t bvalidfltr: 1; + uint32_t sessendfltr: 1; + uint32_t dedfifomode: 1; + uint32_t ineps: 4; + uint32_t descdmaenabled: 1; + uint32_t descdma: 1; }; uint32_t val; } usb_dwc_ghwcfg4_reg_t; @@ -337,8 +358,8 @@ typedef union { typedef union { struct { - uint32_t inepitxfstaddr: 16; - uint32_t inep1txfdep: 16; + uint32_t inepntxfstaddr: 16; + uint32_t inepntxfdep: 16; }; uint32_t val; } usb_dwc_dieptxfi_reg_t; @@ -347,15 +368,15 @@ typedef union { struct { uint32_t fslspclksel: 2; uint32_t fslssupp: 1; - uint32_t reserved4a: 4; + uint32_t reserved_3: 4; uint32_t ena32khzs: 1; uint32_t resvalid: 8; - uint32_t reserved1: 1; - uint32_t reserved6: 6; + uint32_t reserved_16: 1; + uint32_t reserved_17: 6; uint32_t descdma: 1; uint32_t frlisten: 2; uint32_t perschedena: 1; - uint32_t reserved4b: 4; + uint32_t reserved_27: 4; uint32_t modechtimen: 1; }; uint32_t val; @@ -365,15 +386,14 @@ typedef union { struct { uint32_t frint: 16; uint32_t hfirrldctrl: 1; - uint32_t reserved15: 15; + uint32_t reserved_17: 15; }; uint32_t val; } usb_dwc_hfir_reg_t; typedef union { struct { - uint32_t frnum: 14; - uint32_t reserved: 2; + uint32_t frnum: 16; uint32_t frrem: 16; }; uint32_t val; @@ -382,8 +402,7 @@ typedef union { typedef union { struct { uint32_t ptxfspcavail: 16; - uint32_t ptxqspcavail: 5; - uint32_t reserved: 3; + uint32_t ptxqspcavail: 8; uint32_t ptxqtop: 8; }; uint32_t val; @@ -392,7 +411,7 @@ typedef union { typedef union { struct { uint32_t haint: 8; - uint32_t reserved24: 24; + uint32_t reserved_8: 24; }; uint32_t val; } usb_dwc_haint_reg_t; @@ -400,7 +419,7 @@ typedef union { typedef union { struct { uint32_t haintmsk: 8; - uint32_t reserved24: 24; + uint32_t reserved_8: 24; }; uint32_t val; } usb_dwc_haintmsk_reg_t; @@ -423,12 +442,12 @@ typedef union { uint32_t prtres: 1; uint32_t prtsusp: 1; uint32_t prtrst: 1; - uint32_t reserved1: 1; + uint32_t reserved_9: 1; uint32_t prtlnsts: 2; uint32_t prtpwr: 1; uint32_t prttstctl: 4; uint32_t prtspd: 2; - uint32_t reserved13: 13; + uint32_t reserved_19: 13; }; uint32_t val; } usb_dwc_hprt_reg_t; @@ -438,7 +457,7 @@ typedef union { uint32_t mps: 11; uint32_t epnum: 4; uint32_t epdir: 1; - uint32_t reserved: 1; + uint32_t reserved_16: 1; uint32_t lspddev: 1; uint32_t eptype: 2; uint32_t ec: 2; @@ -466,7 +485,7 @@ typedef union { uint32_t bnaintr: 1; uint32_t xcs_xact_err: 1; uint32_t desc_lst_rollintr: 1; - uint32_t reserved18: 18; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_hcint_reg_t; @@ -476,28 +495,26 @@ typedef union { uint32_t xfercomplmsk: 1; uint32_t chhltdmsk: 1; uint32_t ahberrmsk: 1; - uint32_t stallmsk: 1; - uint32_t nakmsk: 1; - uint32_t ackmsk: 1; - uint32_t nyetmsk: 1; - uint32_t xacterrmsk: 1; - uint32_t bblerrmsk: 1; - uint32_t frmovrunmsk: 1; - uint32_t datatglerrmsk: 1; + uint32_t reserved_3: 1; + uint32_t reserved_4: 1; + uint32_t reserved_5: 1; + uint32_t reserved_6: 1; + uint32_t reserved_7: 1; + uint32_t reserved_8: 1; + uint32_t reserved_9: 1; + uint32_t reserved_10: 1; uint32_t bnaintrmsk: 1; - uint32_t reserved1: 1; + uint32_t reserved_12: 1; uint32_t desc_lst_rollintrmsk: 1; - uint32_t reserved18: 18; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_hcintmsk_reg_t; typedef union { struct { - uint32_t sched_info: 8; - uint32_t ntd: 8; - uint32_t reserved3: 3; - uint32_t reserved10: 10; + uint32_t xfersize: 19; // Note: Width depends on OTG_TRANS_COUNT_WIDTH (see databook). + uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook). uint32_t pid: 2; uint32_t dopng: 1; }; @@ -506,14 +523,8 @@ typedef union { typedef union { struct { - uint32_t reserved3: 3; - uint32_t ctd: 6; - uint32_t dmaaddr: 23; - } non_iso; - struct { - uint32_t reserved3: 3; - uint32_t dmaaddr_ctd: 29; - } iso; + uint32_t dmaaddr; + }; uint32_t val; } usb_dwc_hcdma_reg_t; @@ -526,16 +537,16 @@ typedef union { typedef union { struct { - uint32_t reserved2a: 2; + uint32_t devspd: 2; uint32_t nzstsouthshk: 1; - uint32_t reserved1: 1; + uint32_t ena32khzsusp: 1; uint32_t devaddr: 7; - uint32_t perfrlint: 2; + uint32_t perfrint: 2; uint32_t endevoutnak: 1; uint32_t xcvrdly: 1; uint32_t erraticintmsk: 1; - uint32_t reserved2b: 2; - uint32_t epmiscnt: 5; + uint32_t reserved_16: 2; + uint32_t reserved_18: 5; uint32_t descdma: 1; uint32_t perschintvl: 2; uint32_t resvalid: 6; @@ -555,13 +566,13 @@ typedef union { uint32_t sgoutnak: 1; uint32_t cgoutnak: 1; uint32_t pwronprgdone: 1; - uint32_t reserved1: 1; + uint32_t reserved_12: 1; uint32_t gmc: 2; uint32_t ignrfrmnum: 1; uint32_t nakonbble: 1; - uint32_t encountonbna: 1; - uint32_t deepsleepbeslreject: 1; - uint32_t reserved3: 13; + uint32_t encontonbna: 1; + uint32_t reserved_18: 1; + uint32_t reserved_19: 13; }; uint32_t val; } usb_dwc_dctl_reg_t; @@ -571,29 +582,29 @@ typedef union { uint32_t suspsts: 1; uint32_t enumspd: 2; uint32_t errticerr: 1; - uint32_t reserved4: 4; + uint32_t reserved_4: 4; uint32_t soffn: 14; uint32_t devlnsts: 2; - uint32_t reserved8: 8; + uint32_t reserved_24: 8; }; uint32_t val; } usb_dwc_dsts_reg_t; typedef union { struct { - uint32_t di_xfercomplmsk: 1; - uint32_t di_epdisbldmsk: 1; - uint32_t di_ahbermsk: 1; + uint32_t xfercomplmsk: 1; + uint32_t epdisbldmsk: 1; + uint32_t ahberrmsk: 1; uint32_t timeoutmsk: 1; uint32_t intkntxfempmsk: 1; uint32_t intknepmismsk: 1; uint32_t inepnakeffmsk: 1; - uint32_t reserved1: 1; + uint32_t reserved_7: 1; uint32_t txfifoundrnmsk: 1; uint32_t bnainintrmsk: 1; - uint32_t reserved3: 3; - uint32_t di_nakmsk: 1; - uint32_t reserved18: 18; + uint32_t reserved_10: 3; + uint32_t nakmsk: 1; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_diepmsk_reg_t; @@ -602,19 +613,19 @@ typedef union { struct { uint32_t xfercomplmsk: 1; uint32_t epdisbldmsk: 1; - uint32_t ahbermsk: 1; + uint32_t ahberrmsk: 1; uint32_t setupmsk: 1; uint32_t outtknepdismsk: 1; uint32_t stsphsercvdmsk: 1; uint32_t back2backsetup: 1; - uint32_t reserved1: 1; + uint32_t reserved_7: 1; uint32_t outpkterrmsk: 1; uint32_t bnaoutintrmsk: 1; - uint32_t reserved2: 2; + uint32_t reserved_10: 2; uint32_t bbleerrmsk: 1; uint32_t nakmsk: 1; uint32_t nyetmsk: 1; - uint32_t reserved17: 17; + uint32_t reserved_15: 17; }; uint32_t val; } usb_dwc_doepmsk_reg_t; @@ -628,7 +639,7 @@ typedef union { uint32_t inepint4: 1; uint32_t inepint5: 1; uint32_t inepint6: 1; - uint32_t reserved9a: 9; + uint32_t reserved_7: 9; uint32_t outepint0: 1; uint32_t outepint1: 1; uint32_t outepint2: 1; @@ -636,7 +647,7 @@ typedef union { uint32_t outepint4: 1; uint32_t outepint5: 1; uint32_t outepint6: 1; - uint32_t reserved9b: 9; + uint32_t reserved_24: 9; }; uint32_t val; } usb_dwc_daint_reg_t; @@ -650,7 +661,7 @@ typedef union { uint32_t inepmsk4: 1; uint32_t inepmsk5: 1; uint32_t inepmsk6: 1; - uint32_t reserved9a: 9; + uint32_t reserved_7: 9; uint32_t outepmsk0: 1; uint32_t outepmsk1: 1; uint32_t outepmsk2: 1; @@ -658,7 +669,7 @@ typedef union { uint32_t outepmsk4: 1; uint32_t outepmsk5: 1; uint32_t outepmsk6: 1; - uint32_t reserved9b: 9; + uint32_t reserved_24: 9; }; uint32_t val; } usb_dwc_daintmsk_reg_t; @@ -666,7 +677,7 @@ typedef union { typedef union { struct { uint32_t dvbusdis: 16; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_dvbusdis_reg_t; @@ -674,7 +685,7 @@ typedef union { typedef union { struct { uint32_t dvbuspulse: 12; - uint32_t reserved20: 20; + uint32_t reserved_12: 20; }; uint32_t val; } usb_dwc_dvbuspulse_reg_t; @@ -685,109 +696,108 @@ typedef union { uint32_t isothren: 1; uint32_t txthrlen: 9; uint32_t ahbthrratio: 2; - uint32_t reserved3: 3; + uint32_t reserved_13: 3; uint32_t rxthren: 1; uint32_t rxthrlen: 9; - uint32_t reserved1: 1; + uint32_t reserved_26: 1; uint32_t arbprken: 1; - uint32_t reserved4: 4; + uint32_t reserved_28: 4; }; uint32_t val; } usb_dwc_dthrctl_reg_t; typedef union { struct { - uint32_t ineptxfernpmsk: 16; - uint32_t reserved16: 16; + uint32_t ineptxfempmsk: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_diepempmsk_reg_t; typedef union { struct { - uint32_t mps0: 2; - uint32_t reserved9: 9; - uint32_t reserved4: 4; - uint32_t usbactep0: 1; - uint32_t reserved1a: 1; - uint32_t naksts0: 1; - uint32_t eptype0: 2; - uint32_t reserved1b: 1; - uint32_t stall0: 1; - uint32_t txfnum0: 4; - uint32_t cnak0: 1; - uint32_t snak0: 1; - uint32_t reserved2: 2; - uint32_t epdis0: 1; - uint32_t epena0: 1; + uint32_t mps: 2; + uint32_t reserved_2: 9; + uint32_t reserved_11: 4; + uint32_t usbactep: 1; + uint32_t reserved_16: 1; + uint32_t naksts: 1; + uint32_t eptype: 2; + uint32_t reserved_20: 1; + uint32_t stall: 1; + uint32_t txfnum: 4; + uint32_t cnak: 1; + uint32_t snak: 1; + uint32_t reserved_28: 2; + uint32_t epdis: 1; + uint32_t epena: 1; }; uint32_t val; } usb_dwc_diepctl0_reg_t; typedef union { struct { - uint32_t xfercompl0: 1; - uint32_t epdisbld0: 1; - uint32_t ahberr0: 1; - uint32_t timeout0: 1; - uint32_t intkntxfemp0: 1; - uint32_t intknepmis0: 1; - uint32_t inepnakeff0: 1; - uint32_t txfemp0: 1; - uint32_t txfifoundrn0: 1; - uint32_t bnaintr0: 1; - uint32_t reserved1: 1; - uint32_t pktdrpsts0: 1; - uint32_t bbleerr0: 1; - uint32_t nakintrpt0: 1; - uint32_t nyetintrpt0: 1; - uint32_t reserved17: 17; + uint32_t xfercompl: 1; + uint32_t epdisbld: 1; + uint32_t ahberr: 1; + uint32_t timeout: 1; + uint32_t intkntxfemp: 1; + uint32_t intknepmis: 1; + uint32_t inepnakeff: 1; + uint32_t txfemp: 1; + uint32_t txfifoundrn: 1; + uint32_t bnaintr: 1; + uint32_t reserved_10: 1; + uint32_t pktdrpsts: 1; + uint32_t bbleerr: 1; + uint32_t nakintrpt: 1; + uint32_t nyetintrpt: 1; + uint32_t reserved_15: 17; }; uint32_t val; } usb_dwc_diepint0_reg_t; typedef union { struct { - uint32_t xfersize0: 7; - uint32_t reserved12: 12; - uint32_t pktcnt0: 2; - uint32_t reserved11: 11; + uint32_t xfersize: 7; + uint32_t reserved_7: 12; + uint32_t pktcnt: 2; + uint32_t reserved_21: 11; }; uint32_t val; } usb_dwc_dieptsiz0_reg_t; typedef union { struct { - uint32_t dmaaddr0; + uint32_t dmaaddr; }; uint32_t val; } usb_dwc_diepdma0_reg_t; typedef union { struct { - uint32_t ineptxfspcavail0: 16; - uint32_t reserved16: 16; + uint32_t ineptxfspcavail: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_dtxfsts0_reg_t; typedef union { struct { - uint32_t dmabufferaddr0; + uint32_t dmabufferaddr; }; uint32_t val; } usb_dwc_diepdmab0_reg_t; typedef union { struct { - uint32_t mps: 2; - uint32_t reserved9: 9; - uint32_t reserved4: 4; + uint32_t mps: 11; + uint32_t reserved_11: 4; uint32_t usbactep: 1; - uint32_t reserved1a: 1; + uint32_t dpid: 1; uint32_t naksts: 1; uint32_t eptype: 2; - uint32_t reserved1b: 1; + uint32_t reserved_20: 1; uint32_t stall: 1; uint32_t txfnum: 4; uint32_t cnak: 1; @@ -812,29 +822,29 @@ typedef union { uint32_t txfemp: 1; uint32_t txfifoundrn: 1; uint32_t bnaintr: 1; - uint32_t reserved1: 1; + uint32_t reserved_10: 1; uint32_t pktdrpsts: 1; uint32_t bbleerr: 1; uint32_t nakintrpt: 1; uint32_t nyetintrpt: 1; - uint32_t reserved15: 17; + uint32_t reserved_15: 17; }; uint32_t val; } usb_dwc_diepint_reg_t; typedef union { struct { - uint32_t xfersize: 7; - uint32_t reserved12: 12; - uint32_t pktcnt: 2; - uint32_t reserved11: 11; + uint32_t xfersize: 19; // Note: Width depends on OTG_TRANS_COUNT_WIDTH (see databook). + uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook). + uint32_t mc: 2; + uint32_t reserved: 1; }; uint32_t val; } usb_dwc_dieptsiz_reg_t; typedef union { struct { - uint32_t dmaddr1; + uint32_t dmaddr; }; uint32_t val; } usb_dwc_diepdma_reg_t; @@ -842,83 +852,83 @@ typedef union { typedef union { struct { uint32_t ineptxfspcavail: 16; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_dtxfsts_reg_t; typedef union { struct { - uint32_t dmabufferaddr1; + uint32_t dmabufferaddr; }; uint32_t val; } usb_dwc_diepdmab_reg_t; typedef union { struct { - uint32_t mps0: 2; - uint32_t reserved13: 13; - uint32_t usbactep0: 1; - uint32_t reserved1: 1; - uint32_t naksts0: 1; - uint32_t eptype0: 2; - uint32_t snp0: 1; - uint32_t stall0: 1; - uint32_t reserved4: 4; - uint32_t cnak0: 1; - uint32_t snak0: 1; - uint32_t reserved2: 2; - uint32_t epdis0: 1; - uint32_t epena0: 1; + uint32_t mps: 2; + uint32_t reserved_2: 13; + uint32_t usbactep: 1; + uint32_t reserved_16: 1; + uint32_t naksts: 1; + uint32_t eptype: 2; + uint32_t snp: 1; + uint32_t stall: 1; + uint32_t reserved_22: 4; + uint32_t cnak: 1; + uint32_t snak: 1; + uint32_t reserved_28: 2; + uint32_t epdis: 1; + uint32_t epena: 1; }; uint32_t val; } usb_dwc_doepctl0_reg_t; typedef union { struct { - uint32_t xfercompl0: 1; - uint32_t epdisbld0: 1; - uint32_t ahberr0: 1; - uint32_t setup0: 1; - uint32_t outtknepdis0: 1; - uint32_t stsphsercvd0: 1; - uint32_t back2backsetup0: 1; - uint32_t reserved1a: 1; - uint32_t outpkterr0: 1; - uint32_t bnaintr0: 1; - uint32_t reserved1b: 1; - uint32_t pktdrpsts0: 1; - uint32_t bbleerr0: 1; - uint32_t nakintrpt0: 1; - uint32_t nyepintrpt0: 1; - uint32_t stuppktrcvd0: 1; - uint32_t reserved16: 16; + uint32_t xfercompl: 1; + uint32_t epdisbld: 1; + uint32_t ahberr: 1; + uint32_t setup: 1; + uint32_t outtknepdis: 1; + uint32_t stsphsercvd: 1; + uint32_t back2backsetup: 1; + uint32_t reserved_7: 1; + uint32_t outpkterr: 1; + uint32_t bnaintr: 1; + uint32_t reserved_10: 1; + uint32_t pktdrpsts: 1; + uint32_t bbleerr: 1; + uint32_t nakintrpt: 1; + uint32_t nyepintrpt: 1; + uint32_t stuppktrcvd: 1; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_doepint0_reg_t; typedef union { struct { - uint32_t xfersize0: 7; - uint32_t reserved12: 12; - uint32_t pktcnt0: 1; - uint32_t reserved9: 9; - uint32_t supcnt0: 2; - uint32_t reserved1: 1; + uint32_t xfersize: 7; + uint32_t reserved_7: 12; + uint32_t pktcnt: 1; + uint32_t reserved_20: 9; + uint32_t supcnt: 2; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_doeptsiz0_reg_t; typedef union { struct { - uint32_t dmaaddr0; + uint32_t dmaaddr; }; uint32_t val; } usb_dwc_doepdma0_reg_t; typedef union { struct { - uint32_t dmabufferaddr0; + uint32_t dmabufferaddr; }; uint32_t val; } usb_dwc_doepdmab0_reg_t; @@ -926,14 +936,14 @@ typedef union { typedef union { struct { uint32_t mps: 11; - uint32_t reserved4a: 4; + uint32_t reserved_11: 4; uint32_t usbactep: 1; - uint32_t reserved1: 1; + uint32_t dpid: 1; uint32_t naksts: 1; uint32_t eptype: 2; uint32_t snp: 1; uint32_t stall: 1; - uint32_t reserved4b: 4; + uint32_t reserved_22: 4; uint32_t cnak: 1; uint32_t snak: 1; uint32_t setd0pid: 1; @@ -953,28 +963,26 @@ typedef union { uint32_t outtknepdis: 1; uint32_t stsphsercvd: 1; uint32_t back2backsetup: 1; - uint32_t reserved1a: 1; + uint32_t reserved_7: 1; uint32_t outpkterr: 1; uint32_t bnaintr: 1; - uint32_t reserved1b: 1; + uint32_t reserved_10: 1; uint32_t pktdrpsts: 1; uint32_t bbleerr: 1; uint32_t nakintrpt: 1; - uint32_t nyepintrpt: 1; + uint32_t nyetintrpt: 1; uint32_t stuppktrcvd: 1; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_doepint_reg_t; typedef union { struct { - uint32_t xfersize: 7; - uint32_t reserved12: 12; - uint32_t pktcnt: 1; - uint32_t reserved9: 9; - uint32_t supcnt: 2; - uint32_t reserved1: 1; + uint32_t xfersize: 19; // Note: Width depends on OTG_TRANS_COUNT_WIDTH (see databook). + uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook). + uint32_t rxdpid: 2; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_doeptsiz_reg_t; @@ -999,11 +1007,17 @@ typedef union { uint32_t gatehclk: 1; uint32_t pwrclmp: 1; uint32_t rstpdwnmodule: 1; - uint32_t reserved2: 2; + uint32_t reserved_4: 1; + uint32_t reserved_5: 1; uint32_t physleep: 1; uint32_t l1suspended: 1; uint32_t resetaftersusp: 1; - uint32_t reserved23: 23; + uint32_t reserved_9: 1; + uint32_t reserved_10: 1; + uint32_t reserved_11: 1; + uint32_t reserved_12: 1; + uint32_t reserved_13: 1; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_pcgcctl_reg_t; @@ -1012,21 +1026,21 @@ typedef union { typedef struct { volatile usb_dwc_hcchar_reg_t hcchar_reg; // 0x00 - uint32_t reserved_0x04_0x08[1]; // 0x04 + uint32_t reserved_0x04[1]; // 0x04 volatile usb_dwc_hcint_reg_t hcint_reg; // 0x08 volatile usb_dwc_hcintmsk_reg_t hcintmsk_reg; // 0x0c volatile usb_dwc_hctsiz_reg_t hctsiz_reg; // 0x10 volatile usb_dwc_hcdma_reg_t hcdma_reg; // 0x14 - uint32_t reserved_0x14_0x14[1]; // 0x18 + uint32_t reserved_0x18[1]; // 0x18 volatile usb_dwc_hcdmab_reg_t hcdmab_reg; // 0x1c } usb_dwc_host_chan_regs_t; typedef struct { volatile usb_dwc_diepctl_reg_t diepctl_reg; // 0x00 - uint32_t reserved_0x04_0x08[1]; // 0x04 + uint32_t reserved_0x04[1]; // 0x04 volatile usb_dwc_diepint_reg_t diepint_reg; // 0x08 - uint32_t reserved_0x0c_0x10[1]; // 0x0c - volatile usb_dwc_dieptsiz_reg_t dieptsiz_reg; // 0x010 + uint32_t reserved_0x0c[1]; // 0x0c + volatile usb_dwc_dieptsiz_reg_t dieptsiz_reg; // 0x10 volatile usb_dwc_diepdma_reg_t diepdma_reg; // 0x14 volatile usb_dwc_dtxfsts_reg_t dtxfsts_reg; // 0x18 volatile usb_dwc_diepdmab_reg_t diepdmab_reg; // 0x1c @@ -1034,19 +1048,19 @@ typedef struct { typedef struct { volatile usb_dwc_doepctl_reg_t doepctl_reg; // 0x00 - uint32_t reserved_0x04_0x08[1]; // 0x04 + uint32_t reserved_0x04[1]; // 0x04 volatile usb_dwc_doepint_reg_t doepint_reg; // 0x08 - uint32_t reserved_0x0c_0x10[1]; // 0x0c + uint32_t reserved_0x0c[1]; // 0x0c volatile usb_dwc_doeptsiz_reg_t doeptsiz_reg; // 0x10 volatile usb_dwc_doepdma_reg_t doepdma_reg; // 0x14 - uint32_t reserved_0x18_0x1c[1]; // 0x18 + uint32_t reserved_0x18[1]; // 0x18 volatile usb_dwc_doepdmab_reg_t doepdmab_reg; // 0x1c } usb_dwc_out_ep_regs_t; /* --------------------------- Register Layout ------------------------------ */ typedef struct { - //Global Registers + // Global Registers volatile usb_dwc_gotgctl_reg_t gotgctl_reg; // 0x0000 volatile usb_dwc_gotgint_reg_t gotgint_reg; // 0x0004 volatile usb_dwc_gahbcfg_reg_t gahbcfg_reg; // 0x0008 @@ -1059,94 +1073,106 @@ typedef struct { volatile usb_dwc_grxfsiz_reg_t grxfsiz_reg; // 0x0024 volatile usb_dwc_gnptxfsiz_reg_t gnptxfsiz_reg; // 0x0028 volatile usb_dwc_gnptxsts_reg_t gnptxsts_reg; // 0x002c - uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040 + uint32_t reserved_0x0030; // 0x0030 + uint32_t reserved_0x0034; // 0x0034 + uint32_t reserved_0x0038; // 0x0038 + uint32_t reserved_0x003c; // 0x003c volatile usb_dwc_gsnpsid_reg_t gsnpsid_reg; // 0x0040 volatile usb_dwc_ghwcfg1_reg_t ghwcfg1_reg; // 0x0044 volatile usb_dwc_ghwcfg2_reg_t ghwcfg2_reg; // 0x0048 volatile usb_dwc_ghwcfg3_reg_t ghwcfg3_reg; // 0x004c volatile usb_dwc_ghwcfg4_reg_t ghwcfg4_reg; // 0x0050 - uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c - - //FIFO Configurations + uint32_t reserved_0x0054; // 0x0054 + uint32_t reserved_0x0058; // 0x0058 volatile usb_dwc_gdfifocfg_reg_t gdfifocfg_reg; // 0x005c - uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100 + uint32_t reserved_0x0060; // 0x0060 + uint32_t reserved_0x0064_0x0100[39]; // 0x0064 to 0x0100 volatile usb_dwc_hptxfsiz_reg_t hptxfsiz_reg; // 0x0100 - volatile usb_dwc_dieptxfi_reg_t dieptxfi_regs[4]; // 0x0104 to 0x0114 - usb_dwc_dieptxfi_reg_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140 - uint32_t reserved_0x140_0x400[176]; // 0x0140 to 0x0400 + volatile usb_dwc_dieptxfi_reg_t dieptxf_regs[4]; // 0x0104 to 0x0110 (depends on OTG_NUM_IN_EPS) + usb_dwc_dieptxfi_reg_t reserved_0x0114_0x013c[11]; // 0x0114 to 0x013c (depends on OTG_NUM_IN_EPS) + uint32_t reserved_0x140_0x3fc[176]; // 0x0140 to 0x03fc - //Host Mode Registers + // Host Mode Registers volatile usb_dwc_hcfg_reg_t hcfg_reg; // 0x0400 volatile usb_dwc_hfir_reg_t hfir_reg; // 0x0404 volatile usb_dwc_hfnum_reg_t hfnum_reg; // 0x0408 - uint32_t reserved_0x40c_0x410[1]; // 0x040c to 0x0410 + uint32_t reserved_0x40c[1]; // 0x040c volatile usb_dwc_hptxsts_reg_t hptxsts_reg; // 0x0410 volatile usb_dwc_haint_reg_t haint_reg; // 0x0414 volatile usb_dwc_haintmsk_reg_t haintmsk_reg; // 0x0418 volatile usb_dwc_hflbaddr_reg_t hflbaddr_reg; // 0x041c - uint32_t reserved_0x420_0x440[8]; // 0x0420 to 0x0440 + uint32_t reserved_0x420_0x43c[8]; // 0x0420 to 0x043c volatile usb_dwc_hprt_reg_t hprt_reg; // 0x0440 - uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500 - usb_dwc_host_chan_regs_t host_chans[8]; // 0x0500 to 0x0600 - usb_dwc_host_chan_regs_t reserved_0x0600_0x0700[8]; // 0x0600 to 0x0700 - uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800 + uint32_t reserved_0x0444_0x04fc[47]; // 0x0444 to 0x04fc + + // Host Channel Registers + usb_dwc_host_chan_regs_t host_chans[8]; // 0x0500 to 0x05fc (depends on OTG_NUM_HOST_CHAN) + usb_dwc_host_chan_regs_t reserved_0x0600_0x06fc[8]; // 0x0600 to 0x06fc (depends on OTG_NUM_HOST_CHAN) + uint32_t reserved_0x0700_0x07fc[64]; // 0x0700 to 0x07fc + + // Device Mode Registers volatile usb_dwc_dcfg_reg_t dcfg_reg; // 0x0800 volatile usb_dwc_dctl_reg_t dctl_reg; // 0x0804 volatile usb_dwc_dsts_reg_t dsts_reg; // 0x0808 - uint32_t reserved_0x080c_0x0810[1]; // 0x080c to 0x0810 - - //Device Mode Registers - volatile usb_dwc_diepmsk_reg_t diepmsk_reg; // 0x810 + uint32_t reserved_0x080c[1]; // 0x080c + volatile usb_dwc_diepmsk_reg_t diepmsk_reg; // 0x0810 volatile usb_dwc_doepmsk_reg_t doepmsk_reg; // 0x0814 volatile usb_dwc_daint_reg_t daint_reg; // 0x0818 volatile usb_dwc_daintmsk_reg_t daintmsk_reg; // 0x081c - uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828 + uint32_t reserved_0x0820; // 0x0820 + uint32_t reserved_0x0824; // 0x0824 volatile usb_dwc_dvbusdis_reg_t dvbusdis_reg; // 0x0828 volatile usb_dwc_dvbuspulse_reg_t dvbuspulse_reg; // 0x082c volatile usb_dwc_dthrctl_reg_t dthrctl_reg; // 0x0830 volatile usb_dwc_diepempmsk_reg_t diepempmsk_reg; // 0x0834 - uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900 - - //Deivce: IN EP0 reigsters + uint32_t reserved_0x0838; // 0x0838 + uint32_t reserved_0x083c; // 0x083c + uint32_t reserved_0x0840; // 0x0840 + uint32_t reserved_0x0844_0x087c[15]; // 0x0844 to 0x087c (depends on OTG_NUM_EPS) + uint32_t reserved_0x0880; // 0x0880 + uint32_t reserved_0x0884_0x08c0[15]; // 0x0884 to 0x08c0 (depends on OTG_NUM_EPS) + uint32_t reserved_0x08c4_0x08fc[16]; // 0x08c4 to 0x08fc + + // Device: IN EP0 registers volatile usb_dwc_diepctl0_reg_t diepctl0_reg; // 0x0900 - uint32_t reserved_0x0904_0x0908[1]; // 0x0904 to 0x0908 + uint32_t reserved_0x0904[1]; // 0x0904 volatile usb_dwc_diepint0_reg_t diepint0_reg; // 0x0908 - uint32_t reserved_0x090c_0x0910[1]; // 0x090c to 0x0910 + uint32_t reserved_0x090c[1]; // 0x090c volatile usb_dwc_dieptsiz0_reg_t dieptsiz0_reg; // 0x0910 volatile usb_dwc_diepdma0_reg_t diepdma0_reg; // 0x0914 volatile usb_dwc_dtxfsts0_reg_t dtxfsts0_reg; // 0x0918 volatile usb_dwc_diepdmab0_reg_t diepdmab0_reg; // 0x091c - //Deivce: IN EP registers - usb_dwc_in_ep_regs_t in_eps[6]; // 0x0920 to 0x09e0 - usb_dwc_in_ep_regs_t reserved_0x09e0_0x0b00[9]; // 0x09e0 to 0x0b00 + // Device: IN EP registers + usb_dwc_in_ep_regs_t in_eps[6]; // 0x0920 to 0x09dc (depends on OTG_NUM_EPS) + usb_dwc_in_ep_regs_t reserved_0x09e0_0x0afc[9]; // 0x09e0 to 0x0afc (depends on OTG_NUM_EPS) - //Device: OUT EP0 reigsters + // Device: OUT EP0 registers volatile usb_dwc_doepctl0_reg_t doepctl0_reg; // 0x0b00 - uint32_t reserved_0x0b04_0x0b08[1]; // 0x0b04 to 0x0b08 + uint32_t reserved_0x0b04[1]; // 0x0b04 volatile usb_dwc_doepint0_reg_t doepint0_reg; // 0b0b08 - uint32_t reserved_0x0b0c_0x0b10[1]; // 0x0b0c to 0x0b10 + uint32_t reserved_0x0b0c[1]; // 0x0b0c volatile usb_dwc_doeptsiz0_reg_t doeptsiz0_reg; // 0x0b10 volatile usb_dwc_doepdma0_reg_t doepdma0_reg; // 0x0b14 - uint32_t reserved_0x0b18_0x0b1c[1]; // 0x0b18 to 0x0b1c + uint32_t reserved_0x0b18[1]; // 0x0b18 volatile usb_dwc_doepdmab0_reg_t doepdmab0_reg; // 0x0b1c - //Deivce: OUT EP registers - usb_dwc_out_ep_regs_t out_eps[6]; // 0xb1c - usb_dwc_out_ep_regs_t reserved_0x0be0_0x0d00[9]; // 0x0be0 to 0x0d00 - uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00 + // Device: OUT EP registers + usb_dwc_out_ep_regs_t out_eps[6]; // 0x0b20 to 0x0bdc (depends on OTG_NUM_EPS) + usb_dwc_out_ep_regs_t reserved_0x0be0_0x0d00[9]; // 0x0be0 to 0x0cfc (depends on OTG_NUM_EPS) + uint32_t reserved_0x0d00_0x0dfc[64]; // 0x0d00 to 0x0dfc + + // Power and Clock Gating volatile usb_dwc_pcgcctl_reg_t pcgcctl_reg; // 0x0e00 - uint32_t reserved_0x0e04_0x0e08[1]; // 0x0d00 to 0x0e00 + uint32_t reserved_0x0e04[1]; // 0x0e04 } usb_dwc_dev_t; - #ifndef __cplusplus _Static_assert(sizeof(usb_dwc_dev_t) == 0xe08, "Invalid size of usb_dwc_dev_t structure"); #endif extern usb_dwc_dev_t USB_DWC; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/spi_periph.c b/components/soc/esp32s2/spi_periph.c index a897f40c8d8..0ba96136021 100644 --- a/components/soc/esp32s2/spi_periph.c +++ b/components/soc/esp32s2/spi_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ */ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { { + // MSPI has dedicated iomux pins .spiclk_out = SPICLK_OUT_MUX_IDX, .spiclk_in = 0,/* SPI clock is not an input signal*/ .spid_out = SPID_OUT_IDX, @@ -35,6 +36,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .module = PERIPH_SPI_MODULE, .hw = (spi_dev_t *) &SPIMEM1, .func = SPI_FUNC_NUM, + }, { .spiclk_out = FSPICLK_OUT_MUX_IDX, .spiclk_in = FSPICLK_IN_IDX, diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index aa9945311df..0b2ce618156 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -231,6 +231,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_RNG_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y @@ -363,6 +367,10 @@ config SOC_CPU_HAS_FPU bool default y +config SOC_HP_CPU_HAS_MULTIPLE_CORES + bool + default y + config SOC_CPU_BREAKPOINTS_NUM int default 2 @@ -371,7 +379,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE int default 64 @@ -395,6 +403,10 @@ config SOC_GDMA_NUM_GROUPS_MAX int default 1 +config SOC_GDMA_PAIRS_PER_GROUP + int + default 5 + config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 5 @@ -431,6 +443,14 @@ config SOC_GPIO_VALID_GPIO_MASK hex default 0x1FFFFFFFFFFFF +config SOC_GPIO_IN_RANGE_MAX + int + default 48 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 48 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x0001FFFFFC000000 @@ -887,9 +907,9 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS int default 4 -config SOC_TOUCH_VERSION_2 - bool - default y +config SOC_TOUCH_SENSOR_VERSION + int + default 2 config SOC_TOUCH_SENSOR_NUM int @@ -903,13 +923,9 @@ config SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED bool default y -config SOC_TOUCH_PAD_THRESHOLD_MAX - hex - default 0x1FFFFF - -config SOC_TOUCH_PAD_MEASURE_WAIT_MAX - hex - default 0xFF +config SOC_TOUCH_SAMPLER_NUM + int + default 1 config SOC_TWAI_CONTROLLER_NUM int @@ -967,13 +983,9 @@ config SOC_UART_SUPPORT_XTAL_CLK bool default y -config SOC_UART_REQUIRE_CORE_RESET - bool - default y - -config SOC_USB_PERIPH_NUM - bool - default y +config SOC_USB_OTG_PERIPH_NUM + int + default 1 config SOC_SHA_DMA_MAX_BUFFER_SIZE int diff --git a/components/soc/esp32s3/include/soc/regi2c_defs.h b/components/soc/esp32s3/include/soc/regi2c_defs.h index 8b90a70b6c0..e6a6e9cb72e 100644 --- a/components/soc/esp32s3/include/soc/regi2c_defs.h +++ b/components/soc/esp32s3/include/soc/regi2c_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,7 +27,7 @@ /** * Restore regi2c analog calibration related configuration registers. - * This is a workaround, and is fixed on later chips + * This is a workaround for calibration error when waking up from light sleep */ #define REGI2C_ANA_CALI_PD_WORKAROUND 1 #define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 37c0cb2502d..d465da64d47 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,14 +27,15 @@ #define DR_REG_EXT_MEM_ENC 0x600CC000 -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects //consume this file @@ -168,7 +169,7 @@ /* Overall memory map */ #define SOC_DROM_LOW 0x3C000000 -#define SOC_DROM_HIGH 0x3D000000 +#define SOC_DROM_HIGH 0x3E000000 #define SOC_IROM_LOW 0x42000000 #define SOC_IROM_HIGH 0x44000000 #define SOC_IRAM_LOW 0x40370000 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index bffb9694938..4a8d731fe7b 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -16,11 +16,8 @@ * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32s3/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` - * -*/ + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ #pragma once @@ -77,6 +74,7 @@ #define SOC_MPU_SUPPORTED 1 #define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 +#define SOC_RNG_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 @@ -136,10 +134,11 @@ #define SOC_CPU_CORES_NUM 2 #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FPU 1 +#define SOC_HP_CPU_HAS_MULTIPLE_CORES 1 // Convenience boolean macro used to determine if a target has multiple cores. -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /** The maximum length of a Digital Signature in bits. */ @@ -155,7 +154,8 @@ /*-------------------------- GDMA CAPS ---------------------------------------*/ #define SOC_AHB_GDMA_VERSION 1U #define SOC_GDMA_NUM_GROUPS_MAX 1U -#define SOC_GDMA_PAIRS_PER_GROUP_MAX 5 +#define SOC_GDMA_PAIRS_PER_GROUP 5 // esp32s3 has only one kind of GDMA, which is AHB GDMA, and it has 5 pairs in total. +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 5 // when there're multiple GDMA instances, this macro represents the maximum number of GDMA pairs in the same group. #define SOC_AHB_GDMA_SUPPORT_PSRAM 1 /*-------------------------- GPIO CAPS ---------------------------------------*/ @@ -174,6 +174,10 @@ #define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) // No GPIO is input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK) + +#define SOC_GPIO_IN_RANGE_MAX 48 +#define SOC_GPIO_OUT_RANGE_MAX 48 + // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL @@ -353,13 +357,12 @@ #define SOC_TIMER_GROUP_TOTAL_TIMERS (4) /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ -#define SOC_TOUCH_VERSION_2 (1) // Hardware version of touch sensor +#define SOC_TOUCH_SENSOR_VERSION (2) // Hardware version of touch sensor #define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */ #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */ #define SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED (1) /*Sopport touch proximity channel measure done interrupt type. */ -#define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*! + #ifdef __cplusplus extern "C" { #endif -#include +/* +Registers and fields were generated based on a set of configuration options. +See the ESP32-S3 "usb_dwc_cfg.h" for more details. +*/ /* ---------------------------- Register Types ------------------------------ */ @@ -29,7 +34,7 @@ typedef union { uint32_t hstsethnpen: 1; uint32_t devhnpen: 1; uint32_t ehen: 1; - uint32_t reserved2: 2; + uint32_t reserved_13: 2; uint32_t dbncefltrbypass: 1; uint32_t conidsts: 1; uint32_t dbnctime: 1; @@ -37,23 +42,26 @@ typedef union { uint32_t bsesvld: 1; uint32_t otgver: 1; uint32_t curmod: 1; - uint32_t reserved10: 10; + uint32_t reserved_22: 5; + uint32_t reserved_27: 1; + uint32_t reserved_28: 4; }; uint32_t val; } usb_dwc_gotgctl_reg_t; typedef union { struct { - uint32_t reserved2: 2; + uint32_t reserved_0: 2; uint32_t sesenddet: 1; - uint32_t reserved5: 5; + uint32_t reserved_3: 5; uint32_t sesreqsucstschng: 1; uint32_t hstnegsucstschng: 1; - uint32_t reserved7: 7; + uint32_t reserved_10: 7; uint32_t hstnegdet: 1; uint32_t adevtoutchg: 1; uint32_t dbncedone: 1; - uint32_t reserved12: 12; + uint32_t reserved_20: 1; + uint32_t reserved_21: 11; }; uint32_t val; } usb_dwc_gotgint_reg_t; @@ -63,34 +71,44 @@ typedef union { uint32_t glbllntrmsk: 1; uint32_t hbstlen: 4; uint32_t dmaen: 1; - uint32_t reserved1: 1; + uint32_t reserved_6: 1; uint32_t nptxfemplvl: 1; uint32_t ptxfemplvl: 1; - uint32_t reserved12: 12; + uint32_t reserved_9: 12; uint32_t remmemsupp: 1; uint32_t notialldmawrit: 1; uint32_t ahbsingle: 1; uint32_t invdescendianess: 1; - uint32_t reserved7: 7; + uint32_t reserved_25: 7; }; uint32_t val; - //Checked } usb_dwc_gahbcfg_reg_t; typedef union { struct { uint32_t toutcal: 3; uint32_t phyif: 1; - uint32_t reserved1a: 1; + uint32_t reserved_4: 1; uint32_t fsintf: 1; uint32_t physel: 1; - uint32_t reserved1b: 1; + uint32_t reserved_7: 1; uint32_t srpcap: 1; uint32_t hnpcap: 1; uint32_t usbtrdtim: 4; - uint32_t reserved8: 8; + uint32_t reserved_14: 1; + uint32_t phylpwrclksel: 1; + uint32_t reserved_16: 1; + uint32_t reserved_17: 1; + uint32_t reserved_18: 1; + uint32_t reserved_19: 1; + uint32_t reserved_20: 1; + uint32_t reserved_21: 1; uint32_t termseldlpulse: 1; - uint32_t reserved5: 5; + uint32_t reserved_23: 1; + uint32_t reserved_24: 1; + uint32_t reserved_25: 1; + uint32_t icusbcap: 1; + uint32_t reserved_27: 1; uint32_t txenddelay: 1; uint32_t forcehstmode: 1; uint32_t forcedevmode: 1; @@ -104,11 +122,11 @@ typedef union { uint32_t csftrst: 1; uint32_t piufssftrst: 1; uint32_t frmcntrrst: 1; - uint32_t reserved1: 1; + uint32_t reserved_3: 1; uint32_t rxfflsh: 1; uint32_t txfflsh: 1; uint32_t txfnum: 5; - uint32_t reserved19: 19; + uint32_t reserved_11: 19; uint32_t dmareq: 1; uint32_t ahbidle: 1; }; @@ -117,22 +135,23 @@ typedef union { typedef union { struct { - uint32_t curmod_int: 1; + uint32_t curmod: 1; uint32_t modemis: 1; uint32_t otgint: 1; uint32_t sof: 1; - uint32_t rxflvi: 1; + uint32_t rxflvl: 1; uint32_t nptxfemp: 1; uint32_t ginnakeff: 1; uint32_t goutnakeff: 1; - uint32_t reserved2: 2; + uint32_t reserved_8: 1; + uint32_t reserved_9: 1; uint32_t erlysusp: 1; uint32_t usbsusp: 1; uint32_t usbrst: 1; uint32_t enumdone: 1; uint32_t isooutdrop: 1; uint32_t eopf: 1; - uint32_t reserved1a: 1; + uint32_t reserved_16: 1; uint32_t epmis: 1; uint32_t iepint: 1; uint32_t oepint: 1; @@ -140,10 +159,10 @@ typedef union { uint32_t incompip: 1; uint32_t fetsusp: 1; uint32_t resetdet: 1; - uint32_t prtlnt: 1; - uint32_t hchlnt: 1; + uint32_t prtint: 1; + uint32_t hchint: 1; uint32_t ptxfemp: 1; - uint32_t reserved1b: 1; + uint32_t reserved_27: 1; uint32_t conidstschng: 1; uint32_t disconnint: 1; uint32_t sessreqint: 1; @@ -154,22 +173,23 @@ typedef union { typedef union { struct { - uint32_t reserved1a: 1; + uint32_t reserved_0: 1; uint32_t modemismsk: 1; uint32_t otgintmsk: 1; uint32_t sofmsk: 1; - uint32_t rxflvimsk: 1; + uint32_t rxflvlmsk: 1; uint32_t nptxfempmsk: 1; uint32_t ginnakeffmsk: 1; uint32_t goutnackeffmsk: 1; - uint32_t reserved2: 2; + uint32_t reserved_8: 1; + uint32_t reserved_9: 1; uint32_t erlysuspmsk: 1; uint32_t usbsuspmsk: 1; uint32_t usbrstmsk: 1; uint32_t enumdonemsk: 1; uint32_t isooutdropmsk: 1; uint32_t eopfmsk: 1; - uint32_t reserved1b: 1; + uint32_t reserved_16: 1; uint32_t epmismsk: 1; uint32_t iepintmsk: 1; uint32_t oepintmsk: 1; @@ -177,10 +197,10 @@ typedef union { uint32_t incompipmsk: 1; uint32_t fetsuspmsk: 1; uint32_t resetdetmsk: 1; - uint32_t prtlntmsk: 1; + uint32_t prtintmsk: 1; uint32_t hchintmsk: 1; uint32_t ptxfempmsk: 1; - uint32_t reserved1c: 1; + uint32_t reserved_27: 1; uint32_t conidstschngmsk: 1; uint32_t disconnintmsk: 1; uint32_t sessreqintmsk: 1; @@ -191,12 +211,13 @@ typedef union { typedef union { struct { - uint32_t g_chnum: 4; - uint32_t g_bcnt: 11; - uint32_t g_dpid: 2; - uint32_t g_pktsts: 4; - uint32_t g_fn: 4; - uint32_t reserved7: 7; + uint32_t chnum: 4; + uint32_t bcnt: 11; + uint32_t dpid: 2; + uint32_t pktsts: 4; + uint32_t fn: 4; + uint32_t reserved_25: 6; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_grxstsr_reg_t; @@ -208,7 +229,8 @@ typedef union { uint32_t dpid: 2; uint32_t pktsts: 4; uint32_t fn: 4; - uint32_t reserved7: 7; + uint32_t reserved_25: 6; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_grxstsp_reg_t; @@ -216,7 +238,7 @@ typedef union { typedef union { struct { uint32_t rxfdep: 16; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_grxfsiz_reg_t; @@ -232,10 +254,9 @@ typedef union { typedef union { struct { uint32_t nptxfspcavail: 16; - uint32_t nptxqspcavail: 4; - uint32_t reserved4: 4; + uint32_t nptxqspcavail: 8; uint32_t nptxqtop: 7; - uint32_t reserved1: 1; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_gnptxsts_reg_t; @@ -266,11 +287,11 @@ typedef union { uint32_t periosupport: 1; uint32_t dynfifosizing: 1; uint32_t multiprocintrpt: 1; - uint32_t reserved1a: 1; + uint32_t reserved_21: 1; uint32_t nptxqdepth: 2; uint32_t ptxqdepth: 2; uint32_t tknqdepth: 5; - uint32_t reserved1b: 1; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_ghwcfg2_reg_t; @@ -295,25 +316,25 @@ typedef union { typedef union { struct { - uint32_t g_numdevperioeps: 4; - uint32_t g_partialpwrdn: 1; - uint32_t g_ahbfreq: 1; - uint32_t g_hibernation: 1; - uint32_t g_extendedhibernation: 1; - uint32_t reserved4: 4; - uint32_t g_acgsupt: 1; - uint32_t g_enhancedlpmsupt: 1; - uint32_t g_phydatawidth: 2; - uint32_t g_numctleps: 4; - uint32_t g_iddqfltr: 1; - uint32_t g_vbusvalidfltr: 1; - uint32_t g_avalidfltr: 1; - uint32_t g_bvalidfltr: 1; - uint32_t g_sessendfltr: 1; - uint32_t g_dedfifomode: 1; - uint32_t g_ineps: 4; - uint32_t g_descdmaenabled: 1; - uint32_t g_descdma: 1; + uint32_t numdevperioeps: 4; + uint32_t partialpwrdn: 1; + uint32_t ahbfreq: 1; + uint32_t hibernation: 1; + uint32_t extendedhibernation: 1; + uint32_t reserved_8: 4; + uint32_t acgsupt: 1; + uint32_t enhancedlpmsupt: 1; + uint32_t phydatawidth: 2; + uint32_t numctleps: 4; + uint32_t iddqfltr: 1; + uint32_t vbusvalidfltr: 1; + uint32_t avalidfltr: 1; + uint32_t bvalidfltr: 1; + uint32_t sessendfltr: 1; + uint32_t dedfifomode: 1; + uint32_t ineps: 4; + uint32_t descdmaenabled: 1; + uint32_t descdma: 1; }; uint32_t val; } usb_dwc_ghwcfg4_reg_t; @@ -337,8 +358,8 @@ typedef union { typedef union { struct { - uint32_t inepitxfstaddr: 16; - uint32_t inep1txfdep: 16; + uint32_t inepntxfstaddr: 16; + uint32_t inepntxfdep: 16; }; uint32_t val; } usb_dwc_dieptxfi_reg_t; @@ -347,15 +368,15 @@ typedef union { struct { uint32_t fslspclksel: 2; uint32_t fslssupp: 1; - uint32_t reserved4a: 4; + uint32_t reserved_3: 4; uint32_t ena32khzs: 1; uint32_t resvalid: 8; - uint32_t reserved1: 1; - uint32_t reserved6: 6; + uint32_t reserved_16: 1; + uint32_t reserved_17: 6; uint32_t descdma: 1; uint32_t frlisten: 2; uint32_t perschedena: 1; - uint32_t reserved4b: 4; + uint32_t reserved_27: 4; uint32_t modechtimen: 1; }; uint32_t val; @@ -365,15 +386,14 @@ typedef union { struct { uint32_t frint: 16; uint32_t hfirrldctrl: 1; - uint32_t reserved15: 15; + uint32_t reserved_17: 15; }; uint32_t val; } usb_dwc_hfir_reg_t; typedef union { struct { - uint32_t frnum: 14; - uint32_t reserved: 2; + uint32_t frnum: 16; uint32_t frrem: 16; }; uint32_t val; @@ -382,8 +402,7 @@ typedef union { typedef union { struct { uint32_t ptxfspcavail: 16; - uint32_t ptxqspcavail: 5; - uint32_t reserved: 3; + uint32_t ptxqspcavail: 8; uint32_t ptxqtop: 8; }; uint32_t val; @@ -392,7 +411,7 @@ typedef union { typedef union { struct { uint32_t haint: 8; - uint32_t reserved24: 24; + uint32_t reserved_8: 24; }; uint32_t val; } usb_dwc_haint_reg_t; @@ -400,7 +419,7 @@ typedef union { typedef union { struct { uint32_t haintmsk: 8; - uint32_t reserved24: 24; + uint32_t reserved_8: 24; }; uint32_t val; } usb_dwc_haintmsk_reg_t; @@ -423,12 +442,12 @@ typedef union { uint32_t prtres: 1; uint32_t prtsusp: 1; uint32_t prtrst: 1; - uint32_t reserved1: 1; + uint32_t reserved_9: 1; uint32_t prtlnsts: 2; uint32_t prtpwr: 1; uint32_t prttstctl: 4; uint32_t prtspd: 2; - uint32_t reserved13: 13; + uint32_t reserved_19: 13; }; uint32_t val; } usb_dwc_hprt_reg_t; @@ -438,7 +457,7 @@ typedef union { uint32_t mps: 11; uint32_t epnum: 4; uint32_t epdir: 1; - uint32_t reserved: 1; + uint32_t reserved_16: 1; uint32_t lspddev: 1; uint32_t eptype: 2; uint32_t ec: 2; @@ -466,7 +485,7 @@ typedef union { uint32_t bnaintr: 1; uint32_t xcs_xact_err: 1; uint32_t desc_lst_rollintr: 1; - uint32_t reserved18: 18; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_hcint_reg_t; @@ -476,28 +495,26 @@ typedef union { uint32_t xfercomplmsk: 1; uint32_t chhltdmsk: 1; uint32_t ahberrmsk: 1; - uint32_t stallmsk: 1; - uint32_t nakmsk: 1; - uint32_t ackmsk: 1; - uint32_t nyetmsk: 1; - uint32_t xacterrmsk: 1; - uint32_t bblerrmsk: 1; - uint32_t frmovrunmsk: 1; - uint32_t datatglerrmsk: 1; + uint32_t reserved_3: 1; + uint32_t reserved_4: 1; + uint32_t reserved_5: 1; + uint32_t reserved_6: 1; + uint32_t reserved_7: 1; + uint32_t reserved_8: 1; + uint32_t reserved_9: 1; + uint32_t reserved_10: 1; uint32_t bnaintrmsk: 1; - uint32_t reserved1: 1; + uint32_t reserved_12: 1; uint32_t desc_lst_rollintrmsk: 1; - uint32_t reserved18: 18; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_hcintmsk_reg_t; typedef union { struct { - uint32_t sched_info: 8; - uint32_t ntd: 8; - uint32_t reserved3: 3; - uint32_t reserved10: 10; + uint32_t xfersize: 19; // Note: Width depends on OTG_TRANS_COUNT_WIDTH (see databook). + uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook). uint32_t pid: 2; uint32_t dopng: 1; }; @@ -506,14 +523,8 @@ typedef union { typedef union { struct { - uint32_t reserved3: 3; - uint32_t ctd: 6; - uint32_t dmaaddr: 23; - } non_iso; - struct { - uint32_t reserved3: 3; - uint32_t dmaaddr_ctd: 29; - } iso; + uint32_t dmaaddr; + }; uint32_t val; } usb_dwc_hcdma_reg_t; @@ -526,16 +537,16 @@ typedef union { typedef union { struct { - uint32_t reserved2a: 2; + uint32_t devspd: 2; uint32_t nzstsouthshk: 1; - uint32_t reserved1: 1; + uint32_t ena32khzsusp: 1; uint32_t devaddr: 7; - uint32_t perfrlint: 2; + uint32_t perfrint: 2; uint32_t endevoutnak: 1; uint32_t xcvrdly: 1; uint32_t erraticintmsk: 1; - uint32_t reserved2b: 2; - uint32_t epmiscnt: 5; + uint32_t reserved_16: 2; + uint32_t reserved_18: 5; uint32_t descdma: 1; uint32_t perschintvl: 2; uint32_t resvalid: 6; @@ -555,13 +566,13 @@ typedef union { uint32_t sgoutnak: 1; uint32_t cgoutnak: 1; uint32_t pwronprgdone: 1; - uint32_t reserved1: 1; + uint32_t reserved_12: 1; uint32_t gmc: 2; uint32_t ignrfrmnum: 1; uint32_t nakonbble: 1; - uint32_t encountonbna: 1; - uint32_t deepsleepbeslreject: 1; - uint32_t reserved3: 13; + uint32_t encontonbna: 1; + uint32_t reserved_18: 1; + uint32_t reserved_19: 13; }; uint32_t val; } usb_dwc_dctl_reg_t; @@ -571,29 +582,29 @@ typedef union { uint32_t suspsts: 1; uint32_t enumspd: 2; uint32_t errticerr: 1; - uint32_t reserved4: 4; + uint32_t reserved_4: 4; uint32_t soffn: 14; uint32_t devlnsts: 2; - uint32_t reserved8: 8; + uint32_t reserved_24: 8; }; uint32_t val; } usb_dwc_dsts_reg_t; typedef union { struct { - uint32_t di_xfercomplmsk: 1; - uint32_t di_epdisbldmsk: 1; - uint32_t di_ahbermsk: 1; + uint32_t xfercomplmsk: 1; + uint32_t epdisbldmsk: 1; + uint32_t ahberrmsk: 1; uint32_t timeoutmsk: 1; uint32_t intkntxfempmsk: 1; uint32_t intknepmismsk: 1; uint32_t inepnakeffmsk: 1; - uint32_t reserved1: 1; + uint32_t reserved_7: 1; uint32_t txfifoundrnmsk: 1; uint32_t bnainintrmsk: 1; - uint32_t reserved3: 3; - uint32_t di_nakmsk: 1; - uint32_t reserved18: 18; + uint32_t reserved_10: 3; + uint32_t nakmsk: 1; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_diepmsk_reg_t; @@ -602,19 +613,19 @@ typedef union { struct { uint32_t xfercomplmsk: 1; uint32_t epdisbldmsk: 1; - uint32_t ahbermsk: 1; + uint32_t ahberrmsk: 1; uint32_t setupmsk: 1; uint32_t outtknepdismsk: 1; uint32_t stsphsercvdmsk: 1; uint32_t back2backsetup: 1; - uint32_t reserved1: 1; + uint32_t reserved_7: 1; uint32_t outpkterrmsk: 1; uint32_t bnaoutintrmsk: 1; - uint32_t reserved2: 2; + uint32_t reserved_10: 2; uint32_t bbleerrmsk: 1; uint32_t nakmsk: 1; uint32_t nyetmsk: 1; - uint32_t reserved17: 17; + uint32_t reserved_15: 17; }; uint32_t val; } usb_dwc_doepmsk_reg_t; @@ -628,7 +639,7 @@ typedef union { uint32_t inepint4: 1; uint32_t inepint5: 1; uint32_t inepint6: 1; - uint32_t reserved9a: 9; + uint32_t reserved_7: 9; uint32_t outepint0: 1; uint32_t outepint1: 1; uint32_t outepint2: 1; @@ -636,7 +647,7 @@ typedef union { uint32_t outepint4: 1; uint32_t outepint5: 1; uint32_t outepint6: 1; - uint32_t reserved9b: 9; + uint32_t reserved_24: 9; }; uint32_t val; } usb_dwc_daint_reg_t; @@ -650,7 +661,7 @@ typedef union { uint32_t inepmsk4: 1; uint32_t inepmsk5: 1; uint32_t inepmsk6: 1; - uint32_t reserved9a: 9; + uint32_t reserved_7: 9; uint32_t outepmsk0: 1; uint32_t outepmsk1: 1; uint32_t outepmsk2: 1; @@ -658,7 +669,7 @@ typedef union { uint32_t outepmsk4: 1; uint32_t outepmsk5: 1; uint32_t outepmsk6: 1; - uint32_t reserved9b: 9; + uint32_t reserved_24: 9; }; uint32_t val; } usb_dwc_daintmsk_reg_t; @@ -666,7 +677,7 @@ typedef union { typedef union { struct { uint32_t dvbusdis: 16; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_dvbusdis_reg_t; @@ -674,7 +685,7 @@ typedef union { typedef union { struct { uint32_t dvbuspulse: 12; - uint32_t reserved20: 20; + uint32_t reserved_12: 20; }; uint32_t val; } usb_dwc_dvbuspulse_reg_t; @@ -685,109 +696,108 @@ typedef union { uint32_t isothren: 1; uint32_t txthrlen: 9; uint32_t ahbthrratio: 2; - uint32_t reserved3: 3; + uint32_t reserved_13: 3; uint32_t rxthren: 1; uint32_t rxthrlen: 9; - uint32_t reserved1: 1; + uint32_t reserved_26: 1; uint32_t arbprken: 1; - uint32_t reserved4: 4; + uint32_t reserved_28: 4; }; uint32_t val; } usb_dwc_dthrctl_reg_t; typedef union { struct { - uint32_t ineptxfernpmsk: 16; - uint32_t reserved16: 16; + uint32_t ineptxfempmsk: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_diepempmsk_reg_t; typedef union { struct { - uint32_t mps0: 2; - uint32_t reserved9: 9; - uint32_t reserved4: 4; - uint32_t usbactep0: 1; - uint32_t reserved1a: 1; - uint32_t naksts0: 1; - uint32_t eptype0: 2; - uint32_t reserved1b: 1; - uint32_t stall0: 1; - uint32_t txfnum0: 4; - uint32_t cnak0: 1; - uint32_t snak0: 1; - uint32_t reserved2: 2; - uint32_t epdis0: 1; - uint32_t epena0: 1; + uint32_t mps: 2; + uint32_t reserved_2: 9; + uint32_t reserved_11: 4; + uint32_t usbactep: 1; + uint32_t reserved_16: 1; + uint32_t naksts: 1; + uint32_t eptype: 2; + uint32_t reserved_20: 1; + uint32_t stall: 1; + uint32_t txfnum: 4; + uint32_t cnak: 1; + uint32_t snak: 1; + uint32_t reserved_28: 2; + uint32_t epdis: 1; + uint32_t epena: 1; }; uint32_t val; } usb_dwc_diepctl0_reg_t; typedef union { struct { - uint32_t xfercompl0: 1; - uint32_t epdisbld0: 1; - uint32_t ahberr0: 1; - uint32_t timeout0: 1; - uint32_t intkntxfemp0: 1; - uint32_t intknepmis0: 1; - uint32_t inepnakeff0: 1; - uint32_t txfemp0: 1; - uint32_t txfifoundrn0: 1; - uint32_t bnaintr0: 1; - uint32_t reserved1: 1; - uint32_t pktdrpsts0: 1; - uint32_t bbleerr0: 1; - uint32_t nakintrpt0: 1; - uint32_t nyetintrpt0: 1; - uint32_t reserved17: 17; + uint32_t xfercompl: 1; + uint32_t epdisbld: 1; + uint32_t ahberr: 1; + uint32_t timeout: 1; + uint32_t intkntxfemp: 1; + uint32_t intknepmis: 1; + uint32_t inepnakeff: 1; + uint32_t txfemp: 1; + uint32_t txfifoundrn: 1; + uint32_t bnaintr: 1; + uint32_t reserved_10: 1; + uint32_t pktdrpsts: 1; + uint32_t bbleerr: 1; + uint32_t nakintrpt: 1; + uint32_t nyetintrpt: 1; + uint32_t reserved_15: 17; }; uint32_t val; } usb_dwc_diepint0_reg_t; typedef union { struct { - uint32_t xfersize0: 7; - uint32_t reserved12: 12; - uint32_t pktcnt0: 2; - uint32_t reserved11: 11; + uint32_t xfersize: 7; + uint32_t reserved_7: 12; + uint32_t pktcnt: 2; + uint32_t reserved_21: 11; }; uint32_t val; } usb_dwc_dieptsiz0_reg_t; typedef union { struct { - uint32_t dmaaddr0; + uint32_t dmaaddr; }; uint32_t val; } usb_dwc_diepdma0_reg_t; typedef union { struct { - uint32_t ineptxfspcavail0: 16; - uint32_t reserved16: 16; + uint32_t ineptxfspcavail: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_dtxfsts0_reg_t; typedef union { struct { - uint32_t dmabufferaddr0; + uint32_t dmabufferaddr; }; uint32_t val; } usb_dwc_diepdmab0_reg_t; typedef union { struct { - uint32_t mps: 2; - uint32_t reserved9: 9; - uint32_t reserved4: 4; + uint32_t mps: 11; + uint32_t reserved_11: 4; uint32_t usbactep: 1; - uint32_t reserved1a: 1; + uint32_t dpid: 1; uint32_t naksts: 1; uint32_t eptype: 2; - uint32_t reserved1b: 1; + uint32_t reserved_20: 1; uint32_t stall: 1; uint32_t txfnum: 4; uint32_t cnak: 1; @@ -812,29 +822,29 @@ typedef union { uint32_t txfemp: 1; uint32_t txfifoundrn: 1; uint32_t bnaintr: 1; - uint32_t reserved1: 1; + uint32_t reserved_10: 1; uint32_t pktdrpsts: 1; uint32_t bbleerr: 1; uint32_t nakintrpt: 1; uint32_t nyetintrpt: 1; - uint32_t reserved15: 17; + uint32_t reserved_15: 17; }; uint32_t val; } usb_dwc_diepint_reg_t; typedef union { struct { - uint32_t xfersize: 7; - uint32_t reserved12: 12; - uint32_t pktcnt: 2; - uint32_t reserved11: 11; + uint32_t xfersize: 19; // Note: Width depends on OTG_TRANS_COUNT_WIDTH (see databook). + uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook). + uint32_t mc: 2; + uint32_t reserved: 1; }; uint32_t val; } usb_dwc_dieptsiz_reg_t; typedef union { struct { - uint32_t dmaddr1; + uint32_t dmaddr; }; uint32_t val; } usb_dwc_diepdma_reg_t; @@ -842,83 +852,83 @@ typedef union { typedef union { struct { uint32_t ineptxfspcavail: 16; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_dtxfsts_reg_t; typedef union { struct { - uint32_t dmabufferaddr1; + uint32_t dmabufferaddr; }; uint32_t val; } usb_dwc_diepdmab_reg_t; typedef union { struct { - uint32_t mps0: 2; - uint32_t reserved13: 13; - uint32_t usbactep0: 1; - uint32_t reserved1: 1; - uint32_t naksts0: 1; - uint32_t eptype0: 2; - uint32_t snp0: 1; - uint32_t stall0: 1; - uint32_t reserved4: 4; - uint32_t cnak0: 1; - uint32_t snak0: 1; - uint32_t reserved2: 2; - uint32_t epdis0: 1; - uint32_t epena0: 1; + uint32_t mps: 2; + uint32_t reserved_2: 13; + uint32_t usbactep: 1; + uint32_t reserved_16: 1; + uint32_t naksts: 1; + uint32_t eptype: 2; + uint32_t snp: 1; + uint32_t stall: 1; + uint32_t reserved_22: 4; + uint32_t cnak: 1; + uint32_t snak: 1; + uint32_t reserved_28: 2; + uint32_t epdis: 1; + uint32_t epena: 1; }; uint32_t val; } usb_dwc_doepctl0_reg_t; typedef union { struct { - uint32_t xfercompl0: 1; - uint32_t epdisbld0: 1; - uint32_t ahberr0: 1; - uint32_t setup0: 1; - uint32_t outtknepdis0: 1; - uint32_t stsphsercvd0: 1; - uint32_t back2backsetup0: 1; - uint32_t reserved1a: 1; - uint32_t outpkterr0: 1; - uint32_t bnaintr0: 1; - uint32_t reserved1b: 1; - uint32_t pktdrpsts0: 1; - uint32_t bbleerr0: 1; - uint32_t nakintrpt0: 1; - uint32_t nyepintrpt0: 1; - uint32_t stuppktrcvd0: 1; - uint32_t reserved16: 16; + uint32_t xfercompl: 1; + uint32_t epdisbld: 1; + uint32_t ahberr: 1; + uint32_t setup: 1; + uint32_t outtknepdis: 1; + uint32_t stsphsercvd: 1; + uint32_t back2backsetup: 1; + uint32_t reserved_7: 1; + uint32_t outpkterr: 1; + uint32_t bnaintr: 1; + uint32_t reserved_10: 1; + uint32_t pktdrpsts: 1; + uint32_t bbleerr: 1; + uint32_t nakintrpt: 1; + uint32_t nyepintrpt: 1; + uint32_t stuppktrcvd: 1; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_doepint0_reg_t; typedef union { struct { - uint32_t xfersize0: 7; - uint32_t reserved12: 12; - uint32_t pktcnt0: 1; - uint32_t reserved9: 9; - uint32_t supcnt0: 2; - uint32_t reserved1: 1; + uint32_t xfersize: 7; + uint32_t reserved_7: 12; + uint32_t pktcnt: 1; + uint32_t reserved_20: 9; + uint32_t supcnt: 2; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_doeptsiz0_reg_t; typedef union { struct { - uint32_t dmaaddr0; + uint32_t dmaaddr; }; uint32_t val; } usb_dwc_doepdma0_reg_t; typedef union { struct { - uint32_t dmabufferaddr0; + uint32_t dmabufferaddr; }; uint32_t val; } usb_dwc_doepdmab0_reg_t; @@ -926,14 +936,14 @@ typedef union { typedef union { struct { uint32_t mps: 11; - uint32_t reserved4a: 4; + uint32_t reserved_11: 4; uint32_t usbactep: 1; - uint32_t reserved1: 1; + uint32_t dpid: 1; uint32_t naksts: 1; uint32_t eptype: 2; uint32_t snp: 1; uint32_t stall: 1; - uint32_t reserved4b: 4; + uint32_t reserved_22: 4; uint32_t cnak: 1; uint32_t snak: 1; uint32_t setd0pid: 1; @@ -953,28 +963,26 @@ typedef union { uint32_t outtknepdis: 1; uint32_t stsphsercvd: 1; uint32_t back2backsetup: 1; - uint32_t reserved1a: 1; + uint32_t reserved_7: 1; uint32_t outpkterr: 1; uint32_t bnaintr: 1; - uint32_t reserved1b: 1; + uint32_t reserved_10: 1; uint32_t pktdrpsts: 1; uint32_t bbleerr: 1; uint32_t nakintrpt: 1; - uint32_t nyepintrpt: 1; + uint32_t nyetintrpt: 1; uint32_t stuppktrcvd: 1; - uint32_t reserved16: 16; + uint32_t reserved_16: 16; }; uint32_t val; } usb_dwc_doepint_reg_t; typedef union { struct { - uint32_t xfersize: 7; - uint32_t reserved12: 12; - uint32_t pktcnt: 1; - uint32_t reserved9: 9; - uint32_t supcnt: 2; - uint32_t reserved1: 1; + uint32_t xfersize: 19; // Note: Width depends on OTG_TRANS_COUNT_WIDTH (see databook). + uint32_t pktcnt: 10; // Note: Width depends on OTG_PACKET_COUNT_WIDTH (see databook). + uint32_t rxdpid: 2; + uint32_t reserved_31: 1; }; uint32_t val; } usb_dwc_doeptsiz_reg_t; @@ -999,11 +1007,17 @@ typedef union { uint32_t gatehclk: 1; uint32_t pwrclmp: 1; uint32_t rstpdwnmodule: 1; - uint32_t reserved2: 2; + uint32_t reserved_4: 1; + uint32_t reserved_5: 1; uint32_t physleep: 1; uint32_t l1suspended: 1; uint32_t resetaftersusp: 1; - uint32_t reserved23: 23; + uint32_t reserved_9: 1; + uint32_t reserved_10: 1; + uint32_t reserved_11: 1; + uint32_t reserved_12: 1; + uint32_t reserved_13: 1; + uint32_t reserved_14: 18; }; uint32_t val; } usb_dwc_pcgcctl_reg_t; @@ -1012,21 +1026,21 @@ typedef union { typedef struct { volatile usb_dwc_hcchar_reg_t hcchar_reg; // 0x00 - uint32_t reserved_0x04_0x08[1]; // 0x04 + uint32_t reserved_0x04[1]; // 0x04 volatile usb_dwc_hcint_reg_t hcint_reg; // 0x08 volatile usb_dwc_hcintmsk_reg_t hcintmsk_reg; // 0x0c volatile usb_dwc_hctsiz_reg_t hctsiz_reg; // 0x10 volatile usb_dwc_hcdma_reg_t hcdma_reg; // 0x14 - uint32_t reserved_0x14_0x14[1]; // 0x18 + uint32_t reserved_0x18[1]; // 0x18 volatile usb_dwc_hcdmab_reg_t hcdmab_reg; // 0x1c } usb_dwc_host_chan_regs_t; typedef struct { volatile usb_dwc_diepctl_reg_t diepctl_reg; // 0x00 - uint32_t reserved_0x04_0x08[1]; // 0x04 + uint32_t reserved_0x04[1]; // 0x04 volatile usb_dwc_diepint_reg_t diepint_reg; // 0x08 - uint32_t reserved_0x0c_0x10[1]; // 0x0c - volatile usb_dwc_dieptsiz_reg_t dieptsiz_reg; // 0x010 + uint32_t reserved_0x0c[1]; // 0x0c + volatile usb_dwc_dieptsiz_reg_t dieptsiz_reg; // 0x10 volatile usb_dwc_diepdma_reg_t diepdma_reg; // 0x14 volatile usb_dwc_dtxfsts_reg_t dtxfsts_reg; // 0x18 volatile usb_dwc_diepdmab_reg_t diepdmab_reg; // 0x1c @@ -1034,19 +1048,19 @@ typedef struct { typedef struct { volatile usb_dwc_doepctl_reg_t doepctl_reg; // 0x00 - uint32_t reserved_0x04_0x08[1]; // 0x04 + uint32_t reserved_0x04[1]; // 0x04 volatile usb_dwc_doepint_reg_t doepint_reg; // 0x08 - uint32_t reserved_0x0c_0x10[1]; // 0x0c + uint32_t reserved_0x0c[1]; // 0x0c volatile usb_dwc_doeptsiz_reg_t doeptsiz_reg; // 0x10 volatile usb_dwc_doepdma_reg_t doepdma_reg; // 0x14 - uint32_t reserved_0x18_0x1c[1]; // 0x18 + uint32_t reserved_0x18[1]; // 0x18 volatile usb_dwc_doepdmab_reg_t doepdmab_reg; // 0x1c } usb_dwc_out_ep_regs_t; /* --------------------------- Register Layout ------------------------------ */ typedef struct { - //Global Registers + // Global Registers volatile usb_dwc_gotgctl_reg_t gotgctl_reg; // 0x0000 volatile usb_dwc_gotgint_reg_t gotgint_reg; // 0x0004 volatile usb_dwc_gahbcfg_reg_t gahbcfg_reg; // 0x0008 @@ -1059,94 +1073,106 @@ typedef struct { volatile usb_dwc_grxfsiz_reg_t grxfsiz_reg; // 0x0024 volatile usb_dwc_gnptxfsiz_reg_t gnptxfsiz_reg; // 0x0028 volatile usb_dwc_gnptxsts_reg_t gnptxsts_reg; // 0x002c - uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040 + uint32_t reserved_0x0030; // 0x0030 + uint32_t reserved_0x0034; // 0x0034 + uint32_t reserved_0x0038; // 0x0038 + uint32_t reserved_0x003c; // 0x003c volatile usb_dwc_gsnpsid_reg_t gsnpsid_reg; // 0x0040 volatile usb_dwc_ghwcfg1_reg_t ghwcfg1_reg; // 0x0044 volatile usb_dwc_ghwcfg2_reg_t ghwcfg2_reg; // 0x0048 volatile usb_dwc_ghwcfg3_reg_t ghwcfg3_reg; // 0x004c volatile usb_dwc_ghwcfg4_reg_t ghwcfg4_reg; // 0x0050 - uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c - - //FIFO Configurations + uint32_t reserved_0x0054; // 0x0054 + uint32_t reserved_0x0058; // 0x0058 volatile usb_dwc_gdfifocfg_reg_t gdfifocfg_reg; // 0x005c - uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100 + uint32_t reserved_0x0060; // 0x0060 + uint32_t reserved_0x0064_0x0100[39]; // 0x0064 to 0x0100 volatile usb_dwc_hptxfsiz_reg_t hptxfsiz_reg; // 0x0100 - volatile usb_dwc_dieptxfi_reg_t dieptxfi_regs[4]; // 0x0104 to 0x0114 - usb_dwc_dieptxfi_reg_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140 - uint32_t reserved_0x140_0x400[176]; // 0x0140 to 0x0400 + volatile usb_dwc_dieptxfi_reg_t dieptxf_regs[4]; // 0x0104 to 0x0110 (depends on OTG_NUM_IN_EPS) + usb_dwc_dieptxfi_reg_t reserved_0x0114_0x013c[11]; // 0x0114 to 0x013c (depends on OTG_NUM_IN_EPS) + uint32_t reserved_0x140_0x3fc[176]; // 0x0140 to 0x03fc - //Host Mode Registers + // Host Mode Registers volatile usb_dwc_hcfg_reg_t hcfg_reg; // 0x0400 volatile usb_dwc_hfir_reg_t hfir_reg; // 0x0404 volatile usb_dwc_hfnum_reg_t hfnum_reg; // 0x0408 - uint32_t reserved_0x40c_0x410[1]; // 0x040c to 0x0410 + uint32_t reserved_0x40c[1]; // 0x040c volatile usb_dwc_hptxsts_reg_t hptxsts_reg; // 0x0410 volatile usb_dwc_haint_reg_t haint_reg; // 0x0414 volatile usb_dwc_haintmsk_reg_t haintmsk_reg; // 0x0418 volatile usb_dwc_hflbaddr_reg_t hflbaddr_reg; // 0x041c - uint32_t reserved_0x420_0x440[8]; // 0x0420 to 0x0440 + uint32_t reserved_0x420_0x43c[8]; // 0x0420 to 0x043c volatile usb_dwc_hprt_reg_t hprt_reg; // 0x0440 - uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500 - usb_dwc_host_chan_regs_t host_chans[8]; // 0x0500 to 0x0600 - usb_dwc_host_chan_regs_t reserved_0x0600_0x0700[8]; // 0x0600 to 0x0700 - uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800 + uint32_t reserved_0x0444_0x04fc[47]; // 0x0444 to 0x04fc + + // Host Channel Registers + usb_dwc_host_chan_regs_t host_chans[8]; // 0x0500 to 0x05fc (depends on OTG_NUM_HOST_CHAN) + usb_dwc_host_chan_regs_t reserved_0x0600_0x06fc[8]; // 0x0600 to 0x06fc (depends on OTG_NUM_HOST_CHAN) + uint32_t reserved_0x0700_0x07fc[64]; // 0x0700 to 0x07fc + + // Device Mode Registers volatile usb_dwc_dcfg_reg_t dcfg_reg; // 0x0800 volatile usb_dwc_dctl_reg_t dctl_reg; // 0x0804 volatile usb_dwc_dsts_reg_t dsts_reg; // 0x0808 - uint32_t reserved_0x080c_0x0810[1]; // 0x080c to 0x0810 - - //Device Mode Registers - volatile usb_dwc_diepmsk_reg_t diepmsk_reg; // 0x810 + uint32_t reserved_0x080c[1]; // 0x080c + volatile usb_dwc_diepmsk_reg_t diepmsk_reg; // 0x0810 volatile usb_dwc_doepmsk_reg_t doepmsk_reg; // 0x0814 volatile usb_dwc_daint_reg_t daint_reg; // 0x0818 volatile usb_dwc_daintmsk_reg_t daintmsk_reg; // 0x081c - uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828 + uint32_t reserved_0x0820; // 0x0820 + uint32_t reserved_0x0824; // 0x0824 volatile usb_dwc_dvbusdis_reg_t dvbusdis_reg; // 0x0828 volatile usb_dwc_dvbuspulse_reg_t dvbuspulse_reg; // 0x082c volatile usb_dwc_dthrctl_reg_t dthrctl_reg; // 0x0830 volatile usb_dwc_diepempmsk_reg_t diepempmsk_reg; // 0x0834 - uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900 - - //Deivce: IN EP0 reigsters + uint32_t reserved_0x0838; // 0x0838 + uint32_t reserved_0x083c; // 0x083c + uint32_t reserved_0x0840; // 0x0840 + uint32_t reserved_0x0844_0x087c[15]; // 0x0844 to 0x087c (depends on OTG_NUM_EPS) + uint32_t reserved_0x0880; // 0x0880 + uint32_t reserved_0x0884_0x08c0[15]; // 0x0884 to 0x08c0 (depends on OTG_NUM_EPS) + uint32_t reserved_0x08c4_0x08fc[16]; // 0x08c4 to 0x08fc + + // Device: IN EP0 registers volatile usb_dwc_diepctl0_reg_t diepctl0_reg; // 0x0900 - uint32_t reserved_0x0904_0x0908[1]; // 0x0904 to 0x0908 + uint32_t reserved_0x0904[1]; // 0x0904 volatile usb_dwc_diepint0_reg_t diepint0_reg; // 0x0908 - uint32_t reserved_0x090c_0x0910[1]; // 0x090c to 0x0910 + uint32_t reserved_0x090c[1]; // 0x090c volatile usb_dwc_dieptsiz0_reg_t dieptsiz0_reg; // 0x0910 volatile usb_dwc_diepdma0_reg_t diepdma0_reg; // 0x0914 volatile usb_dwc_dtxfsts0_reg_t dtxfsts0_reg; // 0x0918 volatile usb_dwc_diepdmab0_reg_t diepdmab0_reg; // 0x091c - //Deivce: IN EP registers - usb_dwc_in_ep_regs_t in_eps[6]; // 0x0920 to 0x09e0 - usb_dwc_in_ep_regs_t reserved_0x09e0_0x0b00[9]; // 0x09e0 to 0x0b00 + // Device: IN EP registers + usb_dwc_in_ep_regs_t in_eps[6]; // 0x0920 to 0x09dc (depends on OTG_NUM_EPS) + usb_dwc_in_ep_regs_t reserved_0x09e0_0x0afc[9]; // 0x09e0 to 0x0afc (depends on OTG_NUM_EPS) - //Device: OUT EP0 reigsters + // Device: OUT EP0 registers volatile usb_dwc_doepctl0_reg_t doepctl0_reg; // 0x0b00 - uint32_t reserved_0x0b04_0x0b08[1]; // 0x0b04 to 0x0b08 + uint32_t reserved_0x0b04[1]; // 0x0b04 volatile usb_dwc_doepint0_reg_t doepint0_reg; // 0b0b08 - uint32_t reserved_0x0b0c_0x0b10[1]; // 0x0b0c to 0x0b10 + uint32_t reserved_0x0b0c[1]; // 0x0b0c volatile usb_dwc_doeptsiz0_reg_t doeptsiz0_reg; // 0x0b10 volatile usb_dwc_doepdma0_reg_t doepdma0_reg; // 0x0b14 - uint32_t reserved_0x0b18_0x0b1c[1]; // 0x0b18 to 0x0b1c + uint32_t reserved_0x0b18[1]; // 0x0b18 volatile usb_dwc_doepdmab0_reg_t doepdmab0_reg; // 0x0b1c - //Deivce: OUT EP registers - usb_dwc_out_ep_regs_t out_eps[6]; // 0xb1c - usb_dwc_out_ep_regs_t reserved_0x0be0_0x0d00[9]; // 0x0be0 to 0x0d00 - uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00 + // Device: OUT EP registers + usb_dwc_out_ep_regs_t out_eps[6]; // 0x0b20 to 0x0bdc (depends on OTG_NUM_EPS) + usb_dwc_out_ep_regs_t reserved_0x0be0_0x0d00[9]; // 0x0be0 to 0x0cfc (depends on OTG_NUM_EPS) + uint32_t reserved_0x0d00_0x0dfc[64]; // 0x0d00 to 0x0dfc + + // Power and Clock Gating volatile usb_dwc_pcgcctl_reg_t pcgcctl_reg; // 0x0e00 - uint32_t reserved_0x0e04_0x0e08[1]; // 0x0d00 to 0x0e00 + uint32_t reserved_0x0e04[1]; // 0x0e04 } usb_dwc_dev_t; - #ifndef __cplusplus _Static_assert(sizeof(usb_dwc_dev_t) == 0xe08, "Invalid size of usb_dwc_dev_t structure"); #endif extern usb_dwc_dev_t USB_DWC; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld index f75bc70beda..0b6d8881a23 100644 --- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld @@ -38,7 +38,6 @@ PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( I2C1 = 0x60027000 ); PROVIDE ( SDMMC = 0x60028000 ); PROVIDE ( TWAI = 0x6002B000 ); -PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( UART2 = 0x6002E000 ); PROVIDE ( DMA = 0x6003F000 ); diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c index fb7417ba6db..a1098d035fe 100644 --- a/components/soc/esp32s3/spi_periph.c +++ b/components/soc/esp32s3/spi_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,29 +12,30 @@ */ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { { - .spiclk_out = SPICLK_OUT_IDX, - .spiclk_in = 0,/* SPI clock is not an input signal*/ - .spid_out = SPID_OUT_IDX, - .spiq_out = SPIQ_OUT_IDX, - .spiwp_out = SPIWP_OUT_IDX, - .spihd_out = SPIHD_OUT_IDX, - .spid_in = SPID_IN_IDX, - .spiq_in = SPIQ_IN_IDX, - .spiwp_in = SPIWP_IN_IDX, - .spihd_in = SPIHD_IN_IDX, - .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ - .spics_in = 0,/* SPI cs is not an input signal*/ - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, - .irq = ETS_SPI1_INTR_SOURCE, + // MSPI has dedicated iomux pins + .spiclk_out = -1, + .spiclk_in = -1, + .spid_out = -1, + .spiq_out = -1, + .spiwp_out = -1, + .spihd_out = -1, + .spid_in = -1, + .spiq_in = -1, + .spiwp_in = -1, + .spihd_in = -1, + .spics_out = {-1}, + .spics_in = -1, + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = -1, .irq_dma = -1, - .module = PERIPH_SPI_MODULE, - .hw = (spi_dev_t *) &SPIMEM1, - .func = SPI_FUNC_NUM, + .module = -1, + .hw = NULL, + .func = -1, }, { .spiclk_out = FSPICLK_OUT_IDX, .spiclk_in = FSPICLK_IN_IDX, diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h index 80fd7187e1a..6c9b06dd496 100644 --- a/components/soc/include/soc/rtc_cntl_periph.h +++ b/components/soc/include/soc/rtc_cntl_periph.h @@ -9,7 +9,7 @@ #include "sdkconfig.h" // TODO: IDF-5645 -#if CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 #include "soc/lp_io_reg.h" #include "soc/lp_io_struct.h" #include "soc/lp_aon_reg.h" @@ -25,7 +25,7 @@ #endif // TODO: IDF-5645 -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 #include "soc/lp_analog_peri_reg.h" #include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" diff --git a/components/soc/linux/include/soc/Kconfig.soc_caps.in b/components/soc/linux/include/soc/Kconfig.soc_caps.in index 51b3aa0d109..a4bd2261593 100644 --- a/components/soc/linux/include/soc/Kconfig.soc_caps.in +++ b/components/soc/linux/include/soc/Kconfig.soc_caps.in @@ -2,3 +2,19 @@ # This file is auto-generated from SoC caps # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### + +config SOC_GPIO_IN_RANGE_MAX + int + default 65535 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 65535 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_10BIT_ADDR + bool + default y diff --git a/components/soc/linux/include/soc/clk_tree_defs.h b/components/soc/linux/include/soc/clk_tree_defs.h new file mode 100644 index 00000000000..a3accf30b52 --- /dev/null +++ b/components/soc/linux/include/soc/clk_tree_defs.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/** + * Mock definitions for running on the host. + */ + +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + SOC_MOD_CLK_APB = 1, +} soc_module_clk_t; + +/** + * @brief Type of SPI clock source. + */ +typedef enum { + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, + SPI_CLK_SRC_APB = SOC_MOD_CLK_APB, +} soc_periph_spi_clk_src_t; diff --git a/components/soc/linux/include/soc/gpio_pins.h b/components/soc/linux/include/soc/gpio_pins.h new file mode 100644 index 00000000000..59894c0862c --- /dev/null +++ b/components/soc/linux/include/soc/gpio_pins.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * NOTE: this is a stripped-down copy to support building on host when using mocking (CMock). + */ diff --git a/components/soc/linux/include/soc/soc_caps.h b/components/soc/linux/include/soc/soc_caps.h index 899a604ce05..43211af9d40 100644 --- a/components/soc/linux/include/soc/soc_caps.h +++ b/components/soc/linux/include/soc/soc_caps.h @@ -1,14 +1,9 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// The long term plan is to have a single soc_caps.h for each peripheral. -// During the refactoring and multichip support development process, we -// seperate these information into periph_caps.h for each peripheral and -// include them here. - /* * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` @@ -16,10 +11,20 @@ * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c3/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` - * -*/ + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +/* + * NOTE: These definitions are only meant to allow host-based unit testing of some features using CMock. + * They DO NOT imply any functionality on the host. + */ #pragma once + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +#define SOC_GPIO_IN_RANGE_MAX (65535) +#define SOC_GPIO_OUT_RANGE_MAX (65535) + +/*-------------------------- I2C CAPS ----------------------------------------*/ +#define SOC_I2C_SUPPORT_SLAVE (1) +#define SOC_I2C_SUPPORT_10BIT_ADDR (1) diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 0133cf45aae..af29e02de5a 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -49,7 +49,7 @@ else() list(APPEND srcs ${cache_srcs}) set(priv_requires bootloader_support app_update soc esp_mm - driver esp_driver_gpio # TODO: IDF-8503 move spi_bus_lock to esp_hw_support component + esp_driver_gpio ) endif() diff --git a/components/spi_flash/esp_flash_api.c b/components/spi_flash/esp_flash_api.c index f639a37fcb0..bb35e9021d9 100644 --- a/components/spi_flash/esp_flash_api.c +++ b/components/spi_flash/esp_flash_api.c @@ -1122,6 +1122,21 @@ esp_err_t IRAM_ATTR esp_flash_write(esp_flash_t *chip, const void *buffer, uint3 return err; } +FORCE_INLINE_ATTR esp_err_t s_encryption_write_lock(esp_flash_t *chip) { +#if CONFIG_IDF_TARGET_ESP32S2 + esp_crypto_dma_lock_acquire(); +#endif //CONFIG_IDF_TARGET_ESP32S2 + return rom_spiflash_api_funcs->start(chip); +} + +FORCE_INLINE_ATTR esp_err_t s_encryption_write_unlock(esp_flash_t *chip) { + esp_err_t err = rom_spiflash_api_funcs->end(chip, ESP_OK); +#if CONFIG_IDF_TARGET_ESP32S2 + esp_crypto_dma_lock_release(); +#endif //CONFIG_IDF_TARGET_ESP32S2 + return err; +} + esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t address, const void *buffer, uint32_t length) { esp_err_t ret = ESP_FAIL; @@ -1141,7 +1156,7 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres } if ((address % 16) != 0) { - ESP_EARLY_LOGE(TAG, "flash encrypted write address must be 16 bytes aligned"); + ESP_DRAM_LOGE(TAG, "flash encrypted write address must be 16 bytes aligned"); return ESP_ERR_INVALID_ARG; } @@ -1150,14 +1165,22 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres } if ((length % 16) != 0) { - ESP_EARLY_LOGE(TAG, "flash encrypted write length must be multiple of 16"); + ESP_DRAM_LOGE(TAG, "flash encrypted write length must be multiple of 16"); return ESP_ERR_INVALID_SIZE; } bool bus_acquired = false; + bool lock_once = true; const uint8_t *ssrc = (const uint8_t *)buffer; + /* For buffer in internal RAM already, we only need to lock only once. + While for buffer in flash, we need to copy data from flash to internal RAM before + encrypted write every time. That means we need to lock/unlock before/after encrypted + write every time. + */ + lock_once = esp_ptr_in_dram(buffer); + COUNTER_START(); /* On ESP32, write_encrypted encrypts data in RAM as it writes, @@ -1175,6 +1198,27 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres */ uint8_t encrypt_buf[64] __attribute__((aligned(4))); uint32_t row_size_length; +#if CONFIG_IDF_TARGET_ESP32 + uint8_t pre_buf[16] = {0}; + uint8_t post_buf[16] = {0}; + + if((address % 32) != 0) { + esp_flash_read_encrypted(chip, address - 16, pre_buf, 16); + } + if(((address + length) % 32) != 0) { + esp_flash_read_encrypted(chip, address + length, post_buf, 16); + } +#endif + + if (lock_once == true) { + err = s_encryption_write_lock(chip); + if (err != ESP_OK) { + ESP_DRAM_LOGE(TAG, "flash acquire lock failed"); + return err; + } + bus_acquired = true; + } + for (size_t i = 0; i < length; i += row_size_length) { uint32_t row_addr = address + i; uint8_t row_size; @@ -1187,14 +1231,14 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres /* copy to second block in buffer */ memcpy(encrypt_buf + 16, ssrc + i, row_size); /* decrypt the first block from flash, will reencrypt to same bytes */ - esp_flash_read_encrypted(chip, row_addr, encrypt_buf, 16); + memcpy(encrypt_buf, pre_buf, 16); } else if (length - i == 16) { /* 16 bytes left, is first block of a 32 byte row */ row_size = 16; /* copy to first block in buffer */ memcpy(encrypt_buf, ssrc + i, row_size); /* decrypt the second block from flash, will reencrypt to same bytes */ - esp_flash_read_encrypted(chip, row_addr + 16, encrypt_buf + 16, 16); + memcpy(encrypt_buf + 16, post_buf, 16); } else { /* Writing a full 32 byte row (2 blocks) */ row_size = 32; @@ -1220,46 +1264,39 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres #if CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE err = s_check_setting_zero_to_one(chip, row_addr, encrypt_byte, NULL, is_encrypted); if (err != ESP_OK) { - //Error happens, we end flash operation. Re-enable cache and flush it - goto restore_cache; - } -#endif //#if CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE - -#if CONFIG_IDF_TARGET_ESP32S2 - esp_crypto_dma_lock_acquire(); -#endif //CONFIG_IDF_TARGET_ESP32S2 - err = rom_spiflash_api_funcs->start(chip); - - if (err != ESP_OK) { + rom_spiflash_api_funcs->end(chip, ESP_OK); #if CONFIG_IDF_TARGET_ESP32S2 esp_crypto_dma_lock_release(); #endif //CONFIG_IDF_TARGET_ESP32S2 //Error happens, we end flash operation. Re-enable cache and flush it goto restore_cache; } - bus_acquired = true; +#endif //#if CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE + + if (lock_once == false) { + err = s_encryption_write_lock(chip); + if (err != ESP_OK) { + goto restore_cache; + } + bus_acquired = true; + } err = chip->chip_drv->write_encrypted(chip, (uint32_t *)encrypt_buf, row_addr, encrypt_byte); if (err!= ESP_OK) { -#if CONFIG_IDF_TARGET_ESP32S2 - esp_crypto_dma_lock_release(); -#endif //CONFIG_IDF_TARGET_ESP32S2 - bus_acquired = false; - assert(bus_acquired); //Error happens, we end flash operation. Re-enable cache and flush it goto restore_cache; } - err = rom_spiflash_api_funcs->end(chip, ESP_OK); - COUNTER_ADD_BYTES(write, encrypt_byte); -#if CONFIG_IDF_TARGET_ESP32S2 - esp_crypto_dma_lock_release(); -#endif //CONFIG_IDF_TARGET_ESP32S2 - if (err != ESP_OK) { + if (lock_once == false) { + err = s_encryption_write_unlock(chip); + if (err != ESP_OK) { + bus_acquired = false; + //Error happens, we end flash operation. Re-enable cache and flush it + goto restore_cache; + } bus_acquired = false; - //Error happens, we end flash operation. Re-enable cache and flush it - goto restore_cache; } - bus_acquired = false; + + COUNTER_ADD_BYTES(write, encrypt_byte); #if CONFIG_SPI_FLASH_VERIFY_WRITE err = s_verify_write(chip, row_addr, encrypt_byte, (uint32_t *)encrypt_buf, is_encrypted); @@ -1270,12 +1307,25 @@ esp_err_t IRAM_ATTR esp_flash_write_encrypted(esp_flash_t *chip, uint32_t addres #endif //CONFIG_SPI_FLASH_VERIFY_WRITE } + if (lock_once == true) { + err = s_encryption_write_unlock(chip); + if (err != ESP_OK) { + bus_acquired = false; + //Error happens, we end flash operation. Re-enable cache and flush it + goto restore_cache; + } + } + + bus_acquired = false; + COUNTER_STOP(write); err = rom_spiflash_api_funcs->flash_end_flush_cache(chip, err, bus_acquired, address, length); return err; restore_cache: + s_encryption_write_unlock(chip); + bus_acquired = false; COUNTER_STOP(write); ret = rom_spiflash_api_funcs->flash_end_flush_cache(chip, err, bus_acquired, address, length); if (ret != ESP_OK) { diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 65407c70c36..f6ddb52b936 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -14,7 +14,7 @@ #include "esp_log.h" #include "esp_heap_caps.h" #include "hal/spi_types.h" -#include "esp_private/spi_common_internal.h" +#include "esp_private/spi_share_hw_ctrl.h" #include "hal/spi_flash_hal.h" #include "hal/gpio_hal.h" #include "esp_flash_internal.h" @@ -165,6 +165,17 @@ static bool use_bus_lock(int host_id) #endif } +static bool bus_using_iomux(spi_host_device_t host) +{ +#define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false + + CHECK_IOMUX_PIN(host, spid); + CHECK_IOMUX_PIN(host, spiq); + CHECK_IOMUX_PIN(host, spiwp); + CHECK_IOMUX_PIN(host, spihd); + return true; +} + static esp_err_t acquire_spi_device(const esp_flash_spi_device_config_t *config, int* out_dev_id, spi_bus_lock_dev_handle_t* out_dev_handle) { esp_err_t ret = ESP_OK; @@ -246,7 +257,7 @@ esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_d //avoid conflicts with main flash assert(config->host_id != SPI1_HOST || dev_id != 0); - bool use_iomux = spicommon_bus_using_iomux(config->host_id); + bool use_iomux = bus_using_iomux(config->host_id); memspi_host_config_t host_cfg = { .host_id = config->host_id, .cs_num = dev_id, diff --git a/components/spi_flash/include/esp_flash_internal.h b/components/spi_flash/include/esp_flash_internal.h index e329b4d5f02..e7d35b0dfb2 100644 --- a/components/spi_flash/include/esp_flash_internal.h +++ b/components/spi_flash/include/esp_flash_internal.h @@ -8,7 +8,7 @@ #include "esp_err.h" #include #include -#include "esp_private/spi_common_internal.h" +#include "esp_private/spi_share_hw_ctrl.h" #include "sdkconfig.h" #include "esp_flash.h" diff --git a/components/spi_flash/spi_flash_os_func_app.c b/components/spi_flash/spi_flash_os_func_app.c index 31aa11b8a98..1cae3872813 100644 --- a/components/spi_flash/spi_flash_os_func_app.c +++ b/components/spi_flash/spi_flash_os_func_app.c @@ -20,7 +20,7 @@ #include "esp_private/spi_flash_os.h" #include "esp_private/cache_utils.h" -#include "esp_private/spi_common_internal.h" +#include "esp_private/spi_share_hw_ctrl.h" #define SPI_FLASH_CACHE_NO_DISABLE (CONFIG_SPI_FLASH_AUTO_SUSPEND || (CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA) || CONFIG_APP_BUILD_TYPE_RAM) static const char TAG[] = "spi_flash"; @@ -326,7 +326,7 @@ esp_err_t esp_flash_init_main_bus_lock(void) * is set. Thus, we must not call them if the macro is not defined, else the linker * would trigger errors. */ #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS - spi_bus_lock_init_main_bus(); + /* bus_lock is registered by `spi_bus_lock_init_main_bus` constructor in spi_common.c */ spi_bus_lock_set_bg_control(g_main_spi_bus_lock, cache_enable, cache_disable, NULL); esp_err_t err = spi_bus_lock_init_main_dev(); diff --git a/components/spi_flash/test_apps/.build-test-rules.yml b/components/spi_flash/test_apps/.build-test-rules.yml index ba39b0d3573..873efbdf708 100644 --- a/components/spi_flash/test_apps/.build-test-rules.yml +++ b/components/spi_flash/test_apps/.build-test-rules.yml @@ -6,24 +6,21 @@ components/spi_flash/test_apps/esp_flash: temporary: true reason: target esp32p4 is not supported yet # TODO: IDF-7499 depends_filepatterns: - - components/driver/spi/**/* - components/bootloader_support/bootloader_flash/**/* depends_components: - esp_mm - esp_psram - spi_flash - esp_driver_gpio + - esp_driver_spi - esptool_py # Some flash related kconfigs are listed here. components/spi_flash/test_apps/flash_encryption: disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32s2", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32s2", "esp32c6", "esp32h2", "esp32p4"] temporary: true reason: No runners # IDF-5634 - disable: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: target esp32p4 is not supported yet # TODO: IDF-7545 + depends_components: - esp_mm - spi_flash @@ -53,11 +50,11 @@ components/spi_flash/test_apps/mspi_test: temporary: true reason: not supported yet #TODO: IDF-7556 for p4 depends_filepatterns: - - components/driver/spi/**/* - components/bootloader_support/bootloader_flash/**/* depends_components: - esp_mm - esp_psram - spi_flash - esp_driver_gpio + - esp_driver_spi - esptool_py # Some flash related kconfigs are listed here. diff --git a/components/spi_flash/test_apps/flash_encryption/CMakeLists.txt b/components/spi_flash/test_apps/flash_encryption/CMakeLists.txt index 941d38b996d..660c0194c3f 100644 --- a/components/spi_flash/test_apps/flash_encryption/CMakeLists.txt +++ b/components/spi_flash/test_apps/flash_encryption/CMakeLists.txt @@ -7,4 +7,9 @@ include($ENV{IDF_PATH}/tools/cmake/project.cmake) # and esptool_py as we set CONFIG_SPIRAM_... and CONFIG_ESPTOOLPY_... options. set(COMPONENTS main esp_psram esptool_py) +set(EXTRA_COMPONENT_DIRS + "$ENV{IDF_PATH}/tools/unit-test-app/components" + "$ENV{IDF_PATH}/components/spi_flash/test_apps/components" +) + project(test_flash_encryption) diff --git a/components/spi_flash/test_apps/flash_encryption/README.md b/components/spi_flash/test_apps/flash_encryption/README.md index 304c4d955a1..5e87c92c2a8 100644 --- a/components/spi_flash/test_apps/flash_encryption/README.md +++ b/components/spi_flash/test_apps/flash_encryption/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ## Prepare runner diff --git a/components/spi_flash/test_apps/flash_encryption/main/CMakeLists.txt b/components/spi_flash/test_apps/flash_encryption/main/CMakeLists.txt index 578f8a60b67..59721a4c583 100644 --- a/components/spi_flash/test_apps/flash_encryption/main/CMakeLists.txt +++ b/components/spi_flash/test_apps/flash_encryption/main/CMakeLists.txt @@ -2,5 +2,5 @@ set(srcs "test_app_main.c" "test_flash_encryption.c") idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity spi_flash bootloader_support esp_partition + PRIV_REQUIRES unity spi_flash bootloader_support esp_partition test_utils test_flash_utils WHOLE_ARCHIVE) diff --git a/components/spi_flash/test_apps/flash_encryption/main/idf_component.yml b/components/spi_flash/test_apps/flash_encryption/main/idf_component.yml new file mode 100644 index 00000000000..2ae836a9359 --- /dev/null +++ b/components/spi_flash/test_apps/flash_encryption/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + ccomp_timer: "^1.0.0" diff --git a/components/spi_flash/test_apps/flash_encryption/main/test_app_main.c b/components/spi_flash/test_apps/flash_encryption/main/test_app_main.c index 9d62df53034..3990c390433 100644 --- a/components/spi_flash/test_apps/flash_encryption/main/test_app_main.c +++ b/components/spi_flash/test_apps/flash_encryption/main/test_app_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,8 @@ #include "unity.h" #include "unity_test_runner.h" #include "esp_heap_caps.h" +#include "esp_partition.h" +#include "memory_checks.h" // Some resources are lazy allocated in flash encryption, the threadhold is left for that case #define TEST_MEMORY_LEAK_THRESHOLD (-400) @@ -23,6 +25,12 @@ static void check_leak(size_t before_free, size_t after_free, const char *type) void setUp(void) { + // Calling esp_partition_find_first ensures that the paritions have been loaded + // and subsequent calls to esp_partition_find_first from the tests would not + // load partitions which otherwise gets considered as a memory leak. + esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, NULL); + + test_utils_record_free_mem(); before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); } diff --git a/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c b/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c index c28c4998752..a84305c20c9 100644 --- a/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c +++ b/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c @@ -16,6 +16,10 @@ #include "esp_log.h" #include "esp_partition.h" #include "esp_heap_caps.h" +#include "esp_cpu.h" +#include "test_utils.h" +#include "ccomp_timer.h" +#include "test_flash_utils.h" /*-------------------- For running this test, some configurations are necessary -------------------*/ /* ESP32 | CONFIG_SECURE_FLASH_ENC_ENABLED | SET */ @@ -33,15 +37,6 @@ static void verify_erased_flash(size_t offset, size_t length); static size_t start; -const esp_partition_t *get_test_data_partition(void) -{ - /* This finds "flash_test" partition defined in partition_table_unit_test_app.csv */ - const esp_partition_t *result = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, - ESP_PARTITION_SUBTYPE_ANY, "flash_test"); - TEST_ASSERT_NOT_NULL(result); /* means partition table set wrong */ - return result; -} - static void setup_tests(void) { const esp_partition_t *part = get_test_data_partition(); @@ -261,7 +256,7 @@ TEST_CASE("test read & write encrypted data(32 bytes alianed address)", "[flash_ start = (start + 31) & (~31); // round up to 32 byte boundary ESP_LOG_BUFFER_HEXDUMP(TAG, plainttext_data, sizeof(plainttext_data), ESP_LOG_INFO); - printf("Encrypteed writting......\n"); + printf("Encrypted writing......\n"); TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, plainttext_data, sizeof(plainttext_data))); uint8_t *cmp_encrypt_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); @@ -293,7 +288,7 @@ TEST_CASE("test read & write encrypted data(16 bytes alianed but 32 bytes unalig printf("Write data partition @ 0x%" PRIx32 "\n", (uint32_t) start); ESP_LOG_BUFFER_HEXDUMP(TAG, plainttext_data, sizeof(plainttext_data), ESP_LOG_INFO); - printf("Encrypteed writting......\n"); + printf("Encrypted writing......\n"); TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, plainttext_data, sizeof(plainttext_data))); uint8_t *cmp_encrypt_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); @@ -330,14 +325,50 @@ TEST_CASE("test read & write encrypted data with large buffer(n*64+32+16)", "[fl // The tested buffer should be n*64(or n*32)+16 bytes. setup_tests(); TEST_ESP_OK(esp_flash_erase_region(NULL, start, 5 * 4096)); - printf("Encrypteed writting......\n"); + printf("Encrypted writing......\n"); + TEST_ESP_OK(ccomp_timer_start()); TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, large_const_buffer, sizeof(large_const_buffer))); - uint8_t *buf = (uint8_t*)heap_caps_malloc(sizeof(large_const_buffer), MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + int64_t write_time = ccomp_timer_stop(); + IDF_LOG_PERFORMANCE(TAG, "Writing speed: %.2f us/KB", (double)(write_time/sizeof(large_const_buffer))*1024); + + uint8_t *buf = (uint8_t*)heap_caps_malloc(sizeof(large_const_buffer), MALLOC_CAP_8BIT); TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, buf, sizeof(large_const_buffer))); TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, large_const_buffer, sizeof(large_const_buffer)); free(buf); } +static DRAM_ATTR const uint8_t large_const_buffer_dram[16432] = { + 203, // first byte + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, + [50 ... 99] = 2, + [108 ... 1520] = 0x9b, + [1600 ... 2000] = 0x3d, + [8000 ... 9000] = 0xf7, + [15000 ... 16398] = 0xe8, + 43, 0x7f, + [16401 ... 16430] = 0xd1, + 202, // last byte +}; + +TEST_CASE("test read & write encrypted data with large buffer in ram", "[flash_encryption]") +{ + // The tested buffer should be n*64(or n*32)+16 bytes. + setup_tests(); + TEST_ESP_OK(esp_flash_erase_region(NULL, start, 5 * 4096)); + printf("Encrypted writing......\n"); + + TEST_ESP_OK(ccomp_timer_start()); + TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, large_const_buffer_dram, sizeof(large_const_buffer_dram))); + int64_t write_time = ccomp_timer_stop(); + IDF_LOG_PERFORMANCE(TAG, "Writing speed: %.2f us/KB", (double)(write_time/sizeof(large_const_buffer_dram))*1024); + uint8_t *buf = (uint8_t*)heap_caps_malloc(sizeof(large_const_buffer_dram), MALLOC_CAP_32BIT | MALLOC_CAP_8BIT); + + TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, buf, sizeof(large_const_buffer_dram))); + TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, large_const_buffer_dram, sizeof(large_const_buffer_dram)); + free(buf); +} + #endif // CONFIG_SECURE_FLASH_ENC_ENABLED diff --git a/components/tcp_transport/host_test/main/CMakeLists.txt b/components/tcp_transport/host_test/main/CMakeLists.txt index acceea95484..561a14335b7 100644 --- a/components/tcp_transport/host_test/main/CMakeLists.txt +++ b/components/tcp_transport/host_test/main/CMakeLists.txt @@ -1,4 +1,4 @@ -idf_component_register(SRCS "test_socks_transport.cpp" "catch_main.cpp" +idf_component_register(SRCS "test_socks_transport.cpp" REQUIRES tcp_transport mocked_transport INCLUDE_DIRS "$ENV{IDF_PATH}/tools" WHOLE_ARCHIVE) @@ -9,4 +9,7 @@ idf_component_get_property(tcp_transport_component tcp_transport COMPONENT_LIB) target_link_libraries(${tcp_transport_component} PUBLIC ${lwip_component} ${esp_timer_component}) target_compile_options(${COMPONENT_LIB} PUBLIC -fsanitize=address -fconcepts) target_link_options(${COMPONENT_LIB} PUBLIC -fsanitize=address) -set_property(TARGET ${COMPONENT_LIB} PROPERTY CXX_STANDARD 20) + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/tcp_transport/host_test/main/idf_component.yml b/components/tcp_transport/host_test/main/idf_component.yml index 7bad6ab6b4b..77ad273fe30 100644 --- a/components/tcp_transport/host_test/main/idf_component.yml +++ b/components/tcp_transport/host_test/main/idf_component.yml @@ -1,4 +1,3 @@ dependencies: espressif/fmt: "^9.1.0" - idf: - version: ">=4.1.0" + espressif/catch2: "^3.4.0" diff --git a/components/tcp_transport/host_test/main/test_socks_transport.cpp b/components/tcp_transport/host_test/main/test_socks_transport.cpp index fbd7f151280..c2a09b2d167 100644 --- a/components/tcp_transport/host_test/main/test_socks_transport.cpp +++ b/components/tcp_transport/host_test/main/test_socks_transport.cpp @@ -16,7 +16,8 @@ #include #include "fmt/core.h" #include "fmt/ranges.h" -#include "catch/catch.hpp" +#include +#include #include "esp_transport.h" #include "esp_transport_socks_proxy.h" diff --git a/components/tcp_transport/include/esp_transport_ssl.h b/components/tcp_transport/include/esp_transport_ssl.h index 00a76e043b1..ca2355a11d1 100644 --- a/components/tcp_transport/include/esp_transport_ssl.h +++ b/components/tcp_transport/include/esp_transport_ssl.h @@ -166,7 +166,7 @@ void esp_transport_ssl_set_common_name(esp_transport_handle_t t, const char *com /** * @brief Set the ssl context to use secure element (atecc608a) for client(device) private key and certificate * - * @note Recommended to be used with ESP32-WROOM-32SE (which has inbuilt ATECC608A a.k.a Secure Element) + * @note Recommended to be used with ESP32 interfaced to ATECC608A based secure element * * @param t ssl transport */ @@ -211,6 +211,28 @@ void esp_transport_ssl_set_keep_alive(esp_transport_handle_t t, esp_transport_ke */ void esp_transport_ssl_set_interface_name(esp_transport_handle_t t, struct ifreq *if_name); +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS +/** + * @brief Session ticket operation + */ +typedef enum { + ESP_TRANSPORT_SESSION_TICKET_INIT, /*!< Allocate and initialize a TLS session */ + ESP_TRANSPORT_SESSION_TICKET_SAVE, /*!< Save TLS session so it can be restored for the next handshake */ + ESP_TRANSPORT_SESSION_TICKET_USE, /*!< Use already saved session to reconnect faster */ + ESP_TRANSPORT_SESSION_TICKET_FREE /*!< Deallocate and deinit the TLS session */ +} esp_transport_session_ticket_operation_t; + +/** + * @brief Perform desired session ticket operation (init, save, use) + * + * @param[in] t The transport handle + * @param[in] operation Operation to perform with TLS session + * + * @note This operation is only available if CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS=y + */ +esp_err_t esp_transport_ssl_session_ticket_operation(esp_transport_handle_t t, esp_transport_session_ticket_operation_t operation); +#endif // CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + #ifdef __cplusplus } #endif diff --git a/components/tcp_transport/transport_ssl.c b/components/tcp_transport/transport_ssl.c index 0d5228442c5..547c82f4846 100644 --- a/components/tcp_transport/transport_ssl.c +++ b/components/tcp_transport/transport_ssl.c @@ -38,6 +38,9 @@ typedef struct transport_esp_tls { bool ssl_initialized; transport_ssl_conn_state_t conn_state; int sockfd; +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + esp_tls_client_session_t *session_ticket; +#endif } transport_esp_tls_t; /** @@ -523,6 +526,9 @@ esp_transport_handle_t esp_transport_ssl_init(void) void esp_transport_esp_tls_destroy(struct transport_esp_tls *transport_esp_tls) { +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS + esp_tls_free_client_session(transport_esp_tls->session_ticket); +#endif free(transport_esp_tls); } @@ -548,3 +554,32 @@ void esp_transport_tcp_set_interface_name(esp_transport_handle_t t, struct ifreq { return esp_transport_ssl_set_interface_name(t, if_name); } + +#ifdef CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS +esp_err_t esp_transport_ssl_session_ticket_operation(esp_transport_handle_t t, esp_transport_session_ticket_operation_t operation) +{ + transport_esp_tls_t *ssl = ssl_get_context_data(t); + if (!ssl) { + return ESP_FAIL; + } + switch (operation) { + case ESP_TRANSPORT_SESSION_TICKET_INIT: + break; + case ESP_TRANSPORT_SESSION_TICKET_SAVE: + esp_tls_free_client_session(ssl->session_ticket); + ssl->session_ticket = esp_tls_get_client_session(ssl->tls); + break; + case ESP_TRANSPORT_SESSION_TICKET_USE: + if (ssl->session_ticket == NULL) { + return ESP_ERR_INVALID_STATE; + } + ssl->cfg.client_session = ssl->session_ticket; + break; + case ESP_TRANSPORT_SESSION_TICKET_FREE: + esp_tls_free_client_session(ssl->session_ticket); + ssl->session_ticket = NULL; + break; + } + return ESP_OK; +} +#endif // CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS diff --git a/components/ulp/CMakeLists.txt b/components/ulp/CMakeLists.txt index 42b55d7b43b..b70819676a0 100644 --- a/components/ulp/CMakeLists.txt +++ b/components/ulp/CMakeLists.txt @@ -55,8 +55,12 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE) "lp_core/lp_core.c" "lp_core/shared/ulp_lp_core_memory_shared.c" "lp_core/shared/ulp_lp_core_lp_timer_shared.c" - "lp_core/lp_core_i2c.c" "lp_core/lp_core_uart.c") + + if(CONFIG_IDF_TARGET_ESP32C6) + # Add to P4 TODO IDF-7540 + list(APPEND srcs "lp_core/lp_core_i2c.c") + endif() endif() idf_component_register(SRCS ${srcs} diff --git a/components/ulp/Kconfig b/components/ulp/Kconfig index 9ed9c430065..fd144a4087a 100644 --- a/components/ulp/Kconfig +++ b/components/ulp/Kconfig @@ -34,6 +34,7 @@ menu "Ultra Low Power (ULP) Co-processor" default 4096 if !IDF_TARGET_ESP32 range 32 8176 if !IDF_TARGET_ESP32C6 range 32 16352 if IDF_TARGET_ESP32C6 + range 32 32768 if IDF_TARGET_ESP32P4 help Bytes of memory to reserve for ULP Co-processor firmware & data. Data is reserved at the beginning of RTC slow memory. diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt index 08b5af497f9..f2a5ec89ae6 100644 --- a/components/ulp/cmake/CMakeLists.txt +++ b/components/ulp/cmake/CMakeLists.txt @@ -86,11 +86,12 @@ elseif(ULP_COCPU_IS_LP_CORE) "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c" "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_startup.c" "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_utils.c" - "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c" + "${IDF_PATH}/components/hal/uart_hal_iram.c" "${IDF_PATH}/components/hal/uart_hal.c" "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_uart.c" - "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_print.c") + "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_print.c" + "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c") target_link_options(${ULP_APP_NAME} PRIVATE "-nostartfiles") target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments") @@ -98,6 +99,16 @@ elseif(ULP_COCPU_IS_LP_CORE) target_link_options(${ULP_APP_NAME} PRIVATE -Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map) target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${IDF_PATH}/components/soc/${IDF_TARGET}/ld/${IDF_TARGET}.peripherals.ld) + + if(CONFIG_ESP_ROM_HAS_LP_ROM) + target_link_options(${ULP_APP_NAME} + PRIVATE SHELL:-T ${IDF_PATH}/components/esp_rom/${IDF_TARGET}/ld/${IDF_TARGET}lp.rom.ld) + target_link_options(${ULP_APP_NAME} + PRIVATE SHELL:-T ${IDF_PATH}/components/esp_rom/${IDF_TARGET}/ld/${IDF_TARGET}lp.rom.newlib.ld) + target_link_options(${ULP_APP_NAME} + PRIVATE SHELL:-T ${IDF_PATH}/components/esp_rom/${IDF_TARGET}/ld/${IDF_TARGET}lp.rom.version.ld) + endif() + target_sources(${ULP_APP_NAME} PRIVATE ${ULP_S_SOURCES}) target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/lp_core/lp_core/include" "${IDF_PATH}/components/ulp/lp_core/shared/include") diff --git a/components/ulp/ld/lp_core_riscv.ld b/components/ulp/ld/lp_core_riscv.ld index ee4371fe33f..a3a069c892d 100644 --- a/components/ulp/ld/lp_core_riscv.ld +++ b/components/ulp/ld/lp_core_riscv.ld @@ -4,14 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "sdkconfig.h" +#include "soc/soc.h" ENTRY(reset_vector) MEMORY { /*first 128byte for exception/interrupt vectors*/ - vector_table(RX) : ORIGIN = 0x50000000, LENGTH = 0x80 - ram(RWX) : ORIGIN = 0x50000080, LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM - 0x80 - CONFIG_ULP_SHARED_MEM + vector_table(RX) : ORIGIN = SOC_RTC_DRAM_LOW, LENGTH = 0x80 + ram(RWX) : ORIGIN = SOC_RTC_DRAM_LOW + 0x80, LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM - 0x80 - CONFIG_ULP_SHARED_MEM } SECTIONS diff --git a/components/ulp/lp_core/lp_core.c b/components/ulp/lp_core/lp_core.c index 8513880bb93..08bffc7be78 100644 --- a/components/ulp/lp_core/lp_core.c +++ b/components/ulp/lp_core/lp_core.c @@ -5,18 +5,49 @@ */ #include "sdkconfig.h" +#include "esp_rom_caps.h" #include "esp_log.h" +#include "esp_assert.h" #include "soc/pmu_reg.h" -#include "soc/lp_aon_reg.h" -#include "soc/lpperi_reg.h" #include "hal/misc.h" +#include "esp_private/periph_ctrl.h" #include "ulp_common.h" #include "ulp_lp_core.h" #include "ulp_lp_core_memory_shared.h" #include "ulp_lp_core_lp_timer_shared.h" +#include "hal/lp_core_ll.h" + +#if CONFIG_IDF_TARGET_ESP32P4 +#define LP_CORE_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define LP_CORE_RCC_ATOMIC() +#endif const static char* TAG = "ulp-lp-core"; +#define WAKEUP_SOURCE_MAX_NUMBER 5 + +/* Maps the flags defined in ulp_lp_core.h e.g. ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU to their actual HW values */ +static uint32_t wakeup_src_sw_to_hw_flag_lookup[WAKEUP_SOURCE_MAX_NUMBER] = { + LP_CORE_LL_WAKEUP_SOURCE_HP_CPU, + LP_CORE_LL_WAKEUP_SOURCE_LP_UART, + LP_CORE_LL_WAKEUP_SOURCE_LP_IO, + LP_CORE_LL_WAKEUP_SOURCE_ETM, + LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER, +}; + +/* Convert the wake-up sources defined in ulp_lp_core.h to the actual HW wake-up source values */ +static uint32_t lp_core_get_wakeup_source_hw_flags(uint32_t flags) +{ + uint32_t hw_flags = 0; + for(int i = 0; i < WAKEUP_SOURCE_MAX_NUMBER; i++) { + if (flags & (1 << i)) { + hw_flags |= wakeup_src_sw_to_hw_flag_lookup[i]; + } + } + return hw_flags; +} + esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg) { if (!cfg->wakeup_source) { @@ -26,27 +57,36 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg) ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get(); - /* Enable LP-Core */ - REG_CLR_BIT(LP_AON_LPCORE_REG, LP_AON_LPCORE_DISABLE); +#if ESP_ROM_HAS_LP_ROM + /* If we have a LP ROM we boot from it, before jumping to the app code */ + lp_core_ll_set_boot_address(SOC_LP_ROM_LOW); + lp_core_ll_set_app_boot_address(RTC_SLOW_MEM); +#endif //ESP_ROM_HAS_LP_ROM + + LP_CORE_RCC_ATOMIC() { + lp_core_ll_reset_register(); + lp_core_ll_enable_bus_clock(true); + } - /* Allow LP core to access LP memory during sleep */ - REG_CLR_BIT(LP_AON_LPBUS_REG, LP_AON_FAST_MEM_MUX_SEL); - REG_SET_BIT(LP_AON_LPBUS_REG, LP_AON_FAST_MEM_MUX_SEL_UPDATE); +#if CONFIG_IDF_TARGET_ESP32C6 + /* Disable fast LP mem access to allow LP core to access LP memory during sleep */ + lp_core_ll_fast_lp_mem_enable(false); +#endif //CONFIG_IDF_TARGET_ESP32C6 /* Enable stall at sleep request*/ - REG_SET_FIELD(PMU_LP_CPU_PWR0_REG, PMU_LP_CPU_SLP_STALL_EN, 1); + lp_core_ll_stall_at_sleep_request(true); - /* Enable reset after wake-up */ - REG_SET_BIT(PMU_LP_CPU_PWR0_REG, PMU_LP_CPU_SLP_RESET_EN); + /* Enable reset CPU when going to sleep */ + lp_core_ll_rst_at_sleep_enable(true); /* Set wake-up sources */ - REG_SET_FIELD(PMU_LP_CPU_PWR1_REG, PMU_LP_CPU_WAKEUP_EN, cfg->wakeup_source); + lp_core_ll_set_wakeup_source(lp_core_get_wakeup_source_hw_flags(cfg->wakeup_source)); /* Enable JTAG debugging */ - REG_CLR_BIT(LPPERI_CPU_REG, LPPERI_LPCORE_DBGM_UNAVALIABLE); + lp_core_ll_debug_module_enable(true); if (cfg->wakeup_source & ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU) { - REG_SET_FIELD(PMU_HP_LP_CPU_COMM_REG, PMU_HP_TRIGGER_LP, 1); + lp_core_ll_hp_wake_lp(); } if (cfg->wakeup_source & ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER) { diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h index 00788397312..bee3d6c574f 100644 --- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h +++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h @@ -13,6 +13,19 @@ extern "C" { #include #include +/** + * @brief Traverse all possible wake-up sources and update the wake-up cause so that + * ulp_lp_core_get_wakeup_cause can obtain the bitmap of the wake-up reasons. + */ +void ulp_lp_core_update_wakeup_cause(void); + +/** + * @brief Get the wakeup source which caused LP_CPU to wakeup from sleep + * + * @return Wakeup cause in bit map, for the meaning of each bit, refer + * to the definition of wakeup source in lp_core_ll.h + */ +uint32_t ulp_lp_core_get_wakeup_cause(void); /** * @brief Wakeup main CPU from sleep or deep sleep. diff --git a/components/ulp/lp_core/lp_core/lp_core_i2c.c b/components/ulp/lp_core/lp_core/lp_core_i2c.c index 730618db3bf..f0ed0134729 100644 --- a/components/ulp/lp_core/lp_core/lp_core_i2c.c +++ b/components/ulp/lp_core/lp_core/lp_core_i2c.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "ulp_lp_core_i2c.h" #include "ulp_lp_core_utils.h" #include "soc/lp_i2c_reg.h" @@ -18,6 +19,8 @@ #define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#if !CONFIG_IDF_TARGET_ESP32P4 // # Add to P4 TODO IDF-7540 + /* I2C LL context */ i2c_dev_t *dev = I2C_LL_GET_HW(LP_I2C_NUM_0); @@ -475,3 +478,5 @@ esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t d return ret; } + +#endif //!CONFIG_IDF_TARGET_ESP32P4 diff --git a/components/ulp/lp_core/lp_core/lp_core_startup.c b/components/ulp/lp_core/lp_core/lp_core_startup.c index e094848e5ae..a5cf8855b92 100644 --- a/components/ulp/lp_core/lp_core/lp_core_startup.c +++ b/components/ulp/lp_core/lp_core/lp_core_startup.c @@ -14,6 +14,8 @@ extern void main(); /* Initialize lp core related system functions before calling user's main*/ void lp_core_startup() { + ulp_lp_core_update_wakeup_cause(); + main(); ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get(); diff --git a/components/ulp/lp_core/lp_core/lp_core_utils.c b/components/ulp/lp_core/lp_core/lp_core_utils.c index cfdc68d4f4f..5ed302ba315 100644 --- a/components/ulp/lp_core/lp_core/lp_core_utils.c +++ b/components/ulp/lp_core/lp_core/lp_core_utils.c @@ -9,9 +9,60 @@ #include "riscv/csr.h" #include "soc/soc.h" #include "soc/pmu_reg.h" +#include "hal/misc.h" +#include "hal/lp_core_ll.h" +#include "hal/etm_ll.h" +#include "hal/lp_timer_ll.h" +#include "hal/pmu_ll.h" +#include "hal/uart_ll.h" +#include "hal/rtc_io_ll.h" /* LP_FAST_CLK is not very accurate, for now use a rough estimate */ +#if CONFIG_IDF_TARGET_ESP32C6 #define LP_CORE_CPU_FREQUENCY_HZ 16000000 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define LP_CORE_CPU_FREQUENCY_HZ 20000000 +#endif + +static uint32_t lp_wakeup_cause = 0; + +void ulp_lp_core_update_wakeup_cause(void) +{ + if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_HP_CPU) \ + && (pmu_ll_lp_get_interrupt_raw(&PMU) & PMU_HP_SW_TRIGGER_INT_RAW)) { + lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_HP_CPU; + pmu_ll_lp_clear_intsts_mask(&PMU, PMU_HP_SW_TRIGGER_INT_CLR); + } + + if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_UART) \ + && (uart_ll_get_intraw_mask(&LP_UART) & LP_UART_WAKEUP_INT_RAW)) { + lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_UART; + uart_ll_clr_intsts_mask(&LP_UART, LP_UART_WAKEUP_INT_CLR); + } + + if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_IO) \ + && rtcio_ll_get_interrupt_status()) { + lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_IO; + rtcio_ll_clear_interrupt_status(); + } + + if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_ETM) \ + && etm_ll_is_lpcore_wakeup_triggered()) { + lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_ETM; + etm_ll_clear_lpcore_wakeup_status(); + } + + if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER) \ + && (lp_timer_ll_get_lp_intr_raw(&LP_TIMER) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) { + lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER; + lp_timer_ll_clear_lp_intsts_mask(&LP_TIMER, LP_TIMER_MAIN_TIMER_LP_INT_CLR); + } +} + +uint32_t ulp_lp_core_get_wakeup_cause() +{ + return lp_wakeup_cause; +} /** * @brief Wakeup main CPU from sleep or deep sleep. diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c index 4a4fad93a18..eba6bbc2d59 100644 --- a/components/ulp/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core_uart.c @@ -13,7 +13,7 @@ #include "hal/rtc_io_types.h" #include "esp_clk_tree.h" #include "esp_private/periph_ctrl.h" -#include "esp_private/uart_private.h" +#include "esp_private/uart_share_hw_ctrl.h" #define LP_UART_PORT_NUM LP_UART_NUM_0 #define LP_UART_TX_IDLE_NUM_DEFAULT (0U) diff --git a/components/ulp/test_apps/lp_core/README.md b/components/ulp/test_apps/lp_core/README.md index 65eeecb079e..b3864443558 100644 --- a/components/ulp/test_apps/lp_core/README.md +++ b/components/ulp/test_apps/lp_core/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32-C6 | -| ----------------- | -------- | +| Supported Targets | ESP32-C6 | ESP32-P4 | +| ----------------- | -------- | -------- | diff --git a/components/ulp/test_apps/lp_core/main/CMakeLists.txt b/components/ulp/test_apps/lp_core/main/CMakeLists.txt index 7920347468d..38b91b8d46d 100644 --- a/components/ulp/test_apps/lp_core/main/CMakeLists.txt +++ b/components/ulp/test_apps/lp_core/main/CMakeLists.txt @@ -1,10 +1,19 @@ -set(app_sources "test_app_main.c" "test_lp_core.c" "test_lp_core_i2c.c") +set(app_sources "test_app_main.c" "test_lp_core.c") + +# Add to P4 TODO IDF-7540 +if(CONFIG_IDF_TARGET_ESP32C6) + list(APPEND app_sources "test_lp_core_i2c.c") +endif() set(lp_core_sources "lp_core/test_main.c") set(lp_core_sources_counter "lp_core/test_main_counter.c") set(lp_core_sources_set_timer_wakeup "lp_core/test_main_set_timer_wakeup.c") set(lp_core_sources_gpio "lp_core/test_main_gpio.c") -set(lp_core_sources_i2c "lp_core/test_main_i2c.c") + +# Add to P4 TODO IDF-7540 +if(CONFIG_IDF_TARGET_ESP32C6) + set(lp_core_sources_i2c "lp_core/test_main_i2c.c") +endif() idf_component_register(SRCS ${app_sources} INCLUDE_DIRS "lp_core" @@ -17,4 +26,8 @@ ulp_embed_binary(lp_core_test_app "${lp_core_sources}" "${lp_core_exp_dep_srcs}" ulp_embed_binary(lp_core_test_app_counter "${lp_core_sources_counter}" "${lp_core_exp_dep_srcs}") ulp_embed_binary(lp_core_test_app_set_timer_wakeup "${lp_core_sources_set_timer_wakeup}" "${lp_core_exp_dep_srcs}") ulp_embed_binary(lp_core_test_app_gpio "${lp_core_sources_gpio}" "${lp_core_exp_dep_srcs}") -ulp_embed_binary(lp_core_test_app_i2c "${lp_core_sources_i2c}" "${lp_core_exp_dep_srcs}") + +# Add to P4 TODO IDF-7540 +if(CONFIG_IDF_TARGET_ESP32C6) + ulp_embed_binary(lp_core_test_app_i2c "${lp_core_sources_i2c}" "${lp_core_exp_dep_srcs}") +endif() diff --git a/components/ulp/test_apps/lp_core/main/test_lp_core.c b/components/ulp/test_apps/lp_core/main/test_lp_core.c index 2729e8da1ac..c43b815332f 100644 --- a/components/ulp/test_apps/lp_core/main/test_lp_core.c +++ b/components/ulp/test_apps/lp_core/main/test_lp_core.c @@ -112,6 +112,10 @@ TEST_CASE("Test LP core delay", "[lp_core]") ulp_command_resp = LP_CORE_NO_COMMAND; } +#define LP_TIMER_TEST_DURATION_S (5) +#define LP_TIMER_TEST_SLEEP_DURATION_US (20000) + +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) static void do_ulp_wakeup_deepsleep(lp_core_test_commands_t ulp_cmd) { @@ -158,31 +162,6 @@ TEST_CASE_MULTIPLE_STAGES("LP-core is able to wakeup main CPU from deep sleep af do_ulp_wakeup_after_long_delay_deepsleep, check_reset_reason_ulp_wakeup); - -#define LP_TIMER_TEST_DURATION_S (5) -#define LP_TIMER_TEST_SLEEP_DURATION_US (20000) - -TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]") -{ - int64_t start, test_duration; - /* Load ULP firmware and start the coprocessor */ - ulp_lp_core_cfg_t cfg = { - .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER, - .lp_timer_sleep_duration_us = LP_TIMER_TEST_SLEEP_DURATION_US, - }; - - load_and_start_lp_core_firmware(&cfg, lp_core_main_counter_bin_start, lp_core_main_counter_bin_end); - - start = esp_timer_get_time(); - vTaskDelay(pdMS_TO_TICKS(LP_TIMER_TEST_DURATION_S*1000)); - - test_duration = esp_timer_get_time() - start; - uint32_t expected_run_count = test_duration / LP_TIMER_TEST_SLEEP_DURATION_US; - printf("LP core ran %"PRIu32" times in %"PRIi64" ms, expected it to run approx %"PRIu32" times\n", ulp_counter, test_duration/1000, expected_run_count); - - TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_counter, "LP Core did not wake up the expected number of times"); -} - RTC_FAST_ATTR static struct timeval tv_start; #define ULP_COUNTER_WAKEUP_LIMIT_CNT 50 @@ -229,6 +208,31 @@ TEST_CASE_MULTIPLE_STAGES("LP Timer can wakeup lp core periodically during deep do_ulp_wakeup_with_lp_timer_deepsleep, check_reset_reason_and_sleep_duration); +#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) + + +TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]") +{ + int64_t start, test_duration; + /* Load ULP firmware and start the coprocessor */ + ulp_lp_core_cfg_t cfg = { + .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER, + .lp_timer_sleep_duration_us = LP_TIMER_TEST_SLEEP_DURATION_US, + }; + + load_and_start_lp_core_firmware(&cfg, lp_core_main_counter_bin_start, lp_core_main_counter_bin_end); + + start = esp_timer_get_time(); + vTaskDelay(pdMS_TO_TICKS(LP_TIMER_TEST_DURATION_S*1000)); + + test_duration = esp_timer_get_time() - start; + uint32_t expected_run_count = test_duration / LP_TIMER_TEST_SLEEP_DURATION_US; + printf("LP core ran %"PRIu32" times in %"PRIi64" ms, expected it to run approx %"PRIu32" times\n", ulp_counter, test_duration/1000, expected_run_count); + + TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_counter, "LP Core did not wake up the expected number of times"); +} + + static bool ulp_is_running(uint32_t *counter_variable) { uint32_t start_cnt = *counter_variable; diff --git a/tools/mocks/soc/include/soc/clk_tree_defs.h b/components/ulp/ulp_common/include/esp32p4/ulp_common_defs.h similarity index 54% rename from tools/mocks/soc/include/soc/clk_tree_defs.h rename to components/ulp/ulp_common/include/esp32p4/ulp_common_defs.h index ac56598a4b7..8cbd68ee851 100644 --- a/tools/mocks/soc/include/soc/clk_tree_defs.h +++ b/components/ulp/ulp_common/include/esp32p4/ulp_common_defs.h @@ -3,17 +3,17 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#pragma once +#ifndef __ULP_COMMON_DEFS_H__ +#define __ULP_COMMON_DEFS_H__ #ifdef __cplusplus extern "C" { #endif -/** - * @brief Type of SPI clock source. - */ -typedef int soc_periph_spi_clk_src_t; +#define RTC_SLOW_MEM (0x50108000) /*!< LP memory, 32k size */ #ifdef __cplusplus } #endif + +#endif // __ULP_COMMON_DEFS_H__ diff --git a/components/unity/CMakeLists.txt b/components/unity/CMakeLists.txt index c70df0fad64..ef7ee00cd23 100644 --- a/components/unity/CMakeLists.txt +++ b/components/unity/CMakeLists.txt @@ -1,7 +1,9 @@ idf_build_get_property(target IDF_TARGET) set(srcs - "unity/src/unity.c") + "unity/src/unity.c" + "unity_compat.c" +) set(includes "include" diff --git a/components/unity/include/unity_config.h b/components/unity/include/unity_config.h index 32f97190087..0d75508f918 100644 --- a/components/unity/include/unity_config.h +++ b/components/unity/include/unity_config.h @@ -7,6 +7,7 @@ #include #include +#include #include "sdkconfig.h" #ifdef CONFIG_UNITY_ENABLE_FLOAT @@ -29,6 +30,18 @@ #define UNITY_OUTPUT_COLOR #endif +#ifndef __cplusplus +#define UNITY_IS_NAN isnan +#define UNITY_IS_INF isinf +#else +#define UNITY_IS_NAN std::isnan +#define UNITY_IS_INF std::isinf +#endif + +// Note, using __noreturn__ rather than noreturn +// https://github.com/espressif/esp-idf/issues/11339 +#define UNITY_NORETURN __attribute__((__noreturn__)) + #define UNITY_EXCLUDE_TIME_H void unity_flush(void); @@ -51,6 +64,10 @@ uint32_t unity_exec_time_get_ms(void); #endif //CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER #ifdef CONFIG_UNITY_ENABLE_FIXTURE +// Two separate "extras" options here: +// 1. Disable memory allocation wrappers in Unity Fixture +#define UNITY_FIXTURE_NO_EXTRAS +// 2. Add IDF-specific additions to Unity Fixture #include "unity_fixture_extras.h" #endif // CONFIG_UNITY_ENABLE_FIXTURE diff --git a/components/unity/unity b/components/unity/unity index 7d2bf62b7e6..bf560290f60 160000 --- a/components/unity/unity +++ b/components/unity/unity @@ -1 +1 @@ -Subproject commit 7d2bf62b7e6afaf38153041a9d53c21aeeca9a25 +Subproject commit bf560290f6020737eafaa8b5cbd2177c3956c03f diff --git a/components/unity/unity_compat.c b/components/unity/unity_compat.c new file mode 100644 index 00000000000..0cc215d09ab --- /dev/null +++ b/components/unity/unity_compat.c @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "unity.h" + +// Unity 2.6.0 has removed weak definitions of setUp, tearDown, suiteSetUp and suiteTearDown. +// (https://github.com/ThrowTheSwitch/Unity/pull/454) +// We need to provide them here to avoid breaking the existing test applications. + +__attribute__((weak)) void setUp(void) +{ +} + +__attribute__((weak)) void tearDown(void) +{ +} + + +__attribute__((weak)) void suiteSetUp(void) +{ +} + +__attribute__((weak)) int suiteTearDown(int num_failures) +{ + return num_failures; +} diff --git a/components/unity/unity_utils_freertos.c b/components/unity/unity_utils_freertos.c index 26155a2ca99..009acbf2438 100644 --- a/components/unity/unity_utils_freertos.c +++ b/components/unity/unity_utils_freertos.c @@ -49,7 +49,7 @@ void unity_utils_task_delete(TaskHandle_t thandle) #if CONFIG_FREERTOS_UNICORE vTaskDelete(thandle); #else // CONFIG_FREERTOS_UNICORE - const BaseType_t tsk_affinity = xTaskGetAffinity(thandle); + const BaseType_t tsk_affinity = xTaskGetCoreID(thandle); const BaseType_t core_id = xPortGetCoreID(); printf("Task_affinity: 0x%x, current_core: %d\n", tsk_affinity, core_id); diff --git a/components/unity/unity_utils_memory.c b/components/unity/unity_utils_memory.c index dd2b3bcaa3b..79e69a2ba01 100644 --- a/components/unity/unity_utils_memory.c +++ b/components/unity/unity_utils_memory.c @@ -32,11 +32,13 @@ void unity_utils_check_leak(unsigned int before_free, unsigned int leaked = (size_t)(free_delta * -1); - printf("MALLOC_CAP_%s %s leak: Before %u bytes free, After %u bytes free (delta %u)\n", - type, - leaked <= threshold ? "potential" : "critical", - before_free, after_free, leaked); - fflush(stdout); + if (leaked > 0) { + printf("MALLOC_CAP_%s %s leak: Before %u bytes free, After %u bytes free (delta %u)\n", + type, + leaked <= threshold ? "potential" : "critical", + before_free, after_free, leaked); + fflush(stdout); + } TEST_ASSERT_MESSAGE(leaked <= threshold, "The test leaked too much memory"); } diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index d38d775fc45..bbfe59cf1c2 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -12,14 +12,11 @@ #include "freertos/semphr.h" #include "esp_heap_caps.h" #include "esp_intr_alloc.h" +#include "soc/interrupts.h" // For interrupt index #include "esp_err.h" #include "esp_log.h" -#include "esp_rom_gpio.h" #include "hal/usb_dwc_hal.h" -#include "hal/usb_types_private.h" -#include "soc/gpio_pins.h" -#include "soc/gpio_sig_map.h" -#include "esp_private/periph_ctrl.h" +#include "hal/usb_dwc_types.h" #include "hcd.h" #include "usb_private.h" #include "usb/usb_types_ch9.h" @@ -36,108 +33,18 @@ #define RESUME_RECOVERY_MS 20 // Resume recovery of at least 10ms. Make it 20 ms to be safe. This will include the 3 LS bit times of the EOP #define CTRL_EP_MAX_MPS_LS 8 // Largest Maximum Packet Size for Low Speed control endpoints -#define CTRL_EP_MAX_MPS_FS 64 // Largest Maximum Packet Size for Full Speed control endpoints +#define CTRL_EP_MAX_MPS_HSFS 64 // Largest Maximum Packet Size for High & Full Speed control endpoints #define NUM_PORTS 1 // The controller only has one port. // ----------------------- Configs ------------------------- -typedef struct { - int in_mps; - int non_periodic_out_mps; - int periodic_out_mps; -} fifo_mps_limits_t; - -/** - * @brief Default FIFO sizes (see 2.1.2.4 for programming guide) - * - * RXFIFO - * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104 - * - Worst case can accommodate two packets of 204 bytes, or one packet of 408 - * NPTXFIFO - * - Recommended: (LPS/4) * 2 - * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48 - * - Worst case can accommodate three packets of 64 bytes or one packet of 192 - * PTXFIFO - * - Recommended: (LPS/4) * 2 - * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48 - * - Worst case can accommodate three packets of 64 bytes or one packet of 192 - */ -const usb_dwc_hal_fifo_config_t fifo_config_default = { - .rx_fifo_lines = 104, - .nptx_fifo_lines = 48, - .ptx_fifo_lines = 48, -}; - -const fifo_mps_limits_t mps_limits_default = { - .in_mps = 408, - .non_periodic_out_mps = 192, - .periodic_out_mps = 192, -}; - -/** - * @brief FIFO sizes that bias to giving RX FIFO more capacity - * - * RXFIFO - * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152 - * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes - * NPTXFIFO - * - Recommended: (LPS/4) * 2 - * - Actual: Assume LPS is 64, and 1 packets: (64/4) * 1 = 16 - * - Worst case can accommodate one packet of 64 bytes - * PTXFIFO - * - Recommended: (LPS/4) * 2 - * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 2 = 32 - * - Worst case can accommodate two packets of 64 bytes or one packet of 128 - */ -const usb_dwc_hal_fifo_config_t fifo_config_bias_rx = { - .rx_fifo_lines = 152, - .nptx_fifo_lines = 16, - .ptx_fifo_lines = 32, -}; - -const fifo_mps_limits_t mps_limits_bias_rx = { - .in_mps = 600, - .non_periodic_out_mps = 64, - .periodic_out_mps = 128, -}; - -/** - * @brief FIFO sizes that bias to giving Periodic TX FIFO more capacity (i.e., ISOC OUT) - * - * RXFIFO - * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Assume LPS is 64, and 2 packets: ((64/4) * 2) + 2 = 34 - * - Worst case can accommodate two packets of 64 bytes or one packet of 128 - * NPTXFIFO - * - Recommended: (LPS/4) * 2 - * - Actual: Assume LPS is 64, and 1 packets: (64/4) * 1 = 16 - * - Worst case can accommodate one packet of 64 bytes - * PTXFIFO - * - Recommended: (LPS/4) * 2 - * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150 - * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes - */ -const usb_dwc_hal_fifo_config_t fifo_config_bias_ptx = { - .rx_fifo_lines = 34, - .nptx_fifo_lines = 16, - .ptx_fifo_lines = 150, -}; - -const fifo_mps_limits_t mps_limits_bias_ptx = { - .in_mps = 128, - .non_periodic_out_mps = 64, - .periodic_out_mps = 600, -}; - #define FRAME_LIST_LEN USB_HAL_FRAME_LIST_LEN_32 #define NUM_BUFFERS 2 #define XFER_LIST_LEN_CTRL 3 // One descriptor for each stage #define XFER_LIST_LEN_BULK 2 // One descriptor for transfer, one to support an extra zero length packet -#define XFER_LIST_LEN_INTR 32 +#define XFER_LIST_LEN_INTR FRAME_LIST_LEN #define XFER_LIST_LEN_ISOC FRAME_LIST_LEN // Same length as the frame list makes it easier to schedule. Must be power of 2 // ------------------------ Flags -------------------------- @@ -307,8 +214,7 @@ struct port_obj { } flags; bool initialized; // FIFO biasing related - const usb_dwc_hal_fifo_config_t *fifo_config; - const fifo_mps_limits_t *fifo_mps_limits; + usb_hal_fifo_bias_t fifo_bias; // Bias is saved so it can be reconfigured upon reset // Port callback and context hcd_port_callback_t callback; void *callback_arg; @@ -401,7 +307,7 @@ static void _buffer_exec(pipe_t *pipe); */ static inline bool _buffer_check_done(pipe_t *pipe) { - if (pipe->ep_char.type != USB_PRIV_XFER_TYPE_CTRL) { + if (pipe->ep_char.type != USB_DWC_XFER_TYPE_CTRL) { return true; } // Only control transfers need to be continued @@ -757,6 +663,28 @@ static bool _internal_pipe_event_notify(pipe_t *pipe, bool from_isr) return ret; } +// ----------------- HAL <-> USB helpers -------------------- + +static usb_speed_t get_usb_port_speed(usb_dwc_speed_t priv) +{ + switch (priv) { + case USB_DWC_SPEED_LOW: return USB_SPEED_LOW; + case USB_DWC_SPEED_FULL: return USB_SPEED_FULL; + case USB_DWC_SPEED_HIGH: return USB_SPEED_HIGH; + default: abort(); + } +} + +static usb_hal_fifo_bias_t get_hal_fifo_bias(hcd_port_fifo_bias_t public) +{ + switch (public) { + case HCD_PORT_FIFO_BIAS_BALANCED: return USB_HAL_FIFO_BIAS_DEFAULT; + case HCD_PORT_FIFO_BIAS_RX: return USB_HAL_FIFO_BIAS_RX; + case HCD_PORT_FIFO_BIAS_PTX: return USB_HAL_FIFO_BIAS_PTX; + default: abort(); + } +} + // ----------------- Interrupt Handlers -------------------- /** @@ -784,7 +712,7 @@ static hcd_port_event_t _intr_hdlr_hprt(port_t *port, usb_dwc_hal_port_event_t h } case USB_DWC_HAL_PORT_EVENT_ENABLED: { usb_dwc_hal_port_enable(port->hal); // Initialize remaining host port registers - port->speed = (usb_dwc_hal_port_get_conn_speed(port->hal) == USB_PRIV_SPEED_FULL) ? USB_SPEED_FULL : USB_SPEED_LOW; + port->speed = get_usb_port_speed(usb_dwc_hal_port_get_conn_speed(port->hal)); port->state = HCD_PORT_STATE_ENABLED; port->flags.conn_dev_ena = 1; // This was triggered by a command, so no event needs to be propagated. @@ -963,7 +891,7 @@ static port_t *port_obj_alloc(void) { port_t *port = calloc(1, sizeof(port_t)); usb_dwc_hal_context_t *hal = malloc(sizeof(usb_dwc_hal_context_t)); - void *frame_list = heap_caps_aligned_calloc(USB_DWC_HAL_FRAME_LIST_MEM_ALIGN, FRAME_LIST_LEN, sizeof(uint32_t), MALLOC_CAP_DMA); + void *frame_list = heap_caps_aligned_calloc(USB_DWC_FRAME_LIST_MEM_ALIGN, FRAME_LIST_LEN, sizeof(uint32_t), MALLOC_CAP_DMA); SemaphoreHandle_t port_mux = xSemaphoreCreateMutex(); if (port == NULL || hal == NULL || frame_list == NULL || port_mux == NULL) { free(port); @@ -1210,7 +1138,7 @@ static esp_err_t _port_cmd_reset(port_t *port) goto bailout; } // Set FIFO sizes based on the selected biasing - usb_dwc_hal_set_fifo_size(port->hal, port->fifo_config); + usb_dwc_hal_set_fifo_bias(port->hal, port->fifo_bias); // We start periodic scheduling only after a RESET command since SOFs only start after a reset usb_dwc_hal_port_set_frame_list(port->hal, port->frame_list, FRAME_LIST_LEN); usb_dwc_hal_port_periodic_enable(port->hal); @@ -1307,29 +1235,6 @@ esp_err_t hcd_port_init(int port_number, const hcd_port_config_t *port_config, h HCD_CHECK(port_number > 0 && port_config != NULL && port_hdl != NULL, ESP_ERR_INVALID_ARG); HCD_CHECK(port_number <= NUM_PORTS, ESP_ERR_NOT_FOUND); - // Get a pointer to the correct FIFO bias constant values - const usb_dwc_hal_fifo_config_t *fifo_config; - const fifo_mps_limits_t *mps_limits; - switch (port_config->fifo_bias) { - case HCD_PORT_FIFO_BIAS_BALANCED: - fifo_config = &fifo_config_default; - mps_limits = &mps_limits_default; - break; - case HCD_PORT_FIFO_BIAS_RX: - fifo_config = &fifo_config_bias_rx; - mps_limits = &mps_limits_bias_rx; - break; - case HCD_PORT_FIFO_BIAS_PTX: - fifo_config = &fifo_config_bias_ptx; - mps_limits = &mps_limits_bias_ptx; - break; - default: - fifo_config = NULL; - mps_limits = NULL; - abort(); - break; - } - HCD_ENTER_CRITICAL(); HCD_CHECK_FROM_CRIT(s_hcd_obj != NULL && !s_hcd_obj->port_obj->initialized, ESP_ERR_INVALID_STATE); // Port object memory and resources (such as the mutex) already be allocated. Just need to initialize necessary fields only @@ -1338,8 +1243,7 @@ esp_err_t hcd_port_init(int port_number, const hcd_port_config_t *port_config, h TAILQ_INIT(&port_obj->pipes_active_tailq); port_obj->state = HCD_PORT_STATE_NOT_POWERED; port_obj->last_event = HCD_PORT_EVENT_NONE; - port_obj->fifo_config = fifo_config; - port_obj->fifo_mps_limits = mps_limits; + port_obj->fifo_bias = get_hal_fifo_bias(port_config->fifo_bias); port_obj->callback = port_config->callback; port_obj->callback_arg = port_config->callback_arg; port_obj->context = port_config->context; @@ -1431,12 +1335,7 @@ esp_err_t hcd_port_get_speed(hcd_port_handle_t port_hdl, usb_speed_t *speed) HCD_ENTER_CRITICAL(); // Device speed is only valid if there is device connected to the port that has been reset HCD_CHECK_FROM_CRIT(port->flags.conn_dev_ena, ESP_ERR_INVALID_STATE); - usb_priv_speed_t hal_speed = usb_dwc_hal_port_get_conn_speed(port->hal); - if (hal_speed == USB_PRIV_SPEED_FULL) { - *speed = USB_SPEED_FULL; - } else { - *speed = USB_SPEED_LOW; - } + *speed = get_usb_port_speed(usb_dwc_hal_port_get_conn_speed(port->hal)); HCD_EXIT_CRITICAL(); return ESP_OK; } @@ -1512,37 +1411,16 @@ void *hcd_port_get_context(hcd_port_handle_t port_hdl) esp_err_t hcd_port_set_fifo_bias(hcd_port_handle_t port_hdl, hcd_port_fifo_bias_t bias) { esp_err_t ret; - // Get a pointer to the correct FIFO bias constant values - const usb_dwc_hal_fifo_config_t *fifo_config; - const fifo_mps_limits_t *mps_limits; - switch (bias) { - case HCD_PORT_FIFO_BIAS_BALANCED: - fifo_config = &fifo_config_default; - mps_limits = &mps_limits_default; - break; - case HCD_PORT_FIFO_BIAS_RX: - fifo_config = &fifo_config_bias_rx; - mps_limits = &mps_limits_bias_rx; - break; - case HCD_PORT_FIFO_BIAS_PTX: - fifo_config = &fifo_config_bias_ptx; - mps_limits = &mps_limits_bias_ptx; - break; - default: - fifo_config = NULL; - mps_limits = NULL; - abort(); - break; - } + usb_hal_fifo_bias_t hal_bias = get_hal_fifo_bias(bias); + // Configure the new FIFO sizes and store the pointers port_t *port = (port_t *)port_hdl; xSemaphoreTake(port->port_mux, portMAX_DELAY); HCD_ENTER_CRITICAL(); // Check that port is in the correct state to update FIFO sizes if (port->initialized && !port->flags.event_pending && port->num_pipes_idle == 0 && port->num_pipes_queued == 0) { - usb_dwc_hal_set_fifo_size(port->hal, fifo_config); - port->fifo_config = fifo_config; - port->fifo_mps_limits = mps_limits; + usb_dwc_hal_set_fifo_bias(port->hal, hal_bias); + port->fifo_bias = hal_bias; ret = ESP_OK; } else { ret = ESP_ERR_INVALID_STATE; @@ -1594,7 +1472,7 @@ static dma_buffer_block_t *buffer_block_alloc(usb_transfer_type_t type) break; } dma_buffer_block_t *buffer = calloc(1, sizeof(dma_buffer_block_t)); - void *xfer_desc_list = heap_caps_aligned_calloc(USB_DWC_HAL_DMA_MEM_ALIGN, desc_list_len, sizeof(usb_dwc_ll_dma_qtd_t), MALLOC_CAP_DMA); + void *xfer_desc_list = heap_caps_aligned_calloc(USB_DWC_QTD_LIST_MEM_ALIGN, desc_list_len, sizeof(usb_dwc_ll_dma_qtd_t), MALLOC_CAP_DMA); if (buffer == NULL || xfer_desc_list == NULL) { free(buffer); heap_caps_free(xfer_desc_list); @@ -1629,10 +1507,14 @@ static bool pipe_args_usb_compliance_verification(const hcd_pipe_config_t *pipe_ return true; } -static bool pipe_alloc_hcd_support_verification(const usb_ep_desc_t *ep_desc, const fifo_mps_limits_t *mps_limits) +static bool pipe_alloc_hcd_support_verification(usb_dwc_hal_context_t *hal, const usb_ep_desc_t * ep_desc) { + assert(hal != NULL); assert(ep_desc != NULL); - usb_transfer_type_t type = USB_EP_DESC_GET_XFERTYPE(ep_desc); + + usb_hal_fifo_mps_limits_t mps_limits = {0}; + usb_dwc_hal_get_mps_limits(hal, &mps_limits); + const usb_transfer_type_t type = USB_EP_DESC_GET_XFERTYPE(ep_desc); // Check the pipe's interval is not zero if ((type == USB_TRANSFER_TYPE_INTR || type == USB_TRANSFER_TYPE_ISOCHRONOUS) && @@ -1642,37 +1524,21 @@ static bool pipe_alloc_hcd_support_verification(const usb_ep_desc_t *ep_desc, co return false; } - // Check if the pipe's interval is compatible with the periodic frame list's length - if (type == USB_TRANSFER_TYPE_INTR && - (ep_desc->bInterval > FRAME_LIST_LEN)) { - ESP_LOGE(HCD_DWC_TAG, "bInterval value (%d) of Interrupt pipe exceeds max supported limit", - ep_desc->bInterval); - return false; - } - - if (type == USB_TRANSFER_TYPE_ISOCHRONOUS && - ((1 << (ep_desc->bInterval - 1)) > FRAME_LIST_LEN)) { - // (where 0 < 2^(bInterval - 1) <= FRAME_LIST_LEN) - ESP_LOGE(HCD_DWC_TAG, "bInterval value (%d) of Isochronous pipe exceeds max supported limit", - ep_desc->bInterval); - return false; - } - // Check if pipe MPS exceeds HCD MPS limits (due to DWC FIFO sizing) int limit; if (USB_EP_DESC_GET_EP_DIR(ep_desc)) { // IN - limit = mps_limits->in_mps; + limit = mps_limits.in_mps; } else { // OUT if (type == USB_TRANSFER_TYPE_CTRL || type == USB_TRANSFER_TYPE_BULK) { - limit = mps_limits->non_periodic_out_mps; + limit = mps_limits.non_periodic_out_mps; } else { - limit = mps_limits->periodic_out_mps; + limit = mps_limits.periodic_out_mps; } } - if (ep_desc->wMaxPacketSize > limit) { + if (USB_EP_DESC_GET_MPS(ep_desc) > limit) { ESP_LOGE(HCD_DWC_TAG, "EP MPS (%d) exceeds supported limit (%d)", - ep_desc->wMaxPacketSize, + USB_EP_DESC_GET_MPS(ep_desc), limit); return false; } @@ -1683,57 +1549,61 @@ static bool pipe_alloc_hcd_support_verification(const usb_ep_desc_t *ep_desc, co static void pipe_set_ep_char(const hcd_pipe_config_t *pipe_config, usb_transfer_type_t type, bool is_default_pipe, int pipe_idx, usb_speed_t port_speed, usb_dwc_hal_ep_char_t *ep_char) { // Initialize EP characteristics - usb_priv_xfer_type_t hal_xfer_type; + usb_dwc_xfer_type_t hal_xfer_type; switch (type) { case USB_TRANSFER_TYPE_CTRL: - hal_xfer_type = USB_PRIV_XFER_TYPE_CTRL; + hal_xfer_type = USB_DWC_XFER_TYPE_CTRL; break; case USB_TRANSFER_TYPE_ISOCHRONOUS: - hal_xfer_type = USB_PRIV_XFER_TYPE_ISOCHRONOUS; + hal_xfer_type = USB_DWC_XFER_TYPE_ISOCHRONOUS; break; case USB_TRANSFER_TYPE_BULK: - hal_xfer_type = USB_PRIV_XFER_TYPE_BULK; + hal_xfer_type = USB_DWC_XFER_TYPE_BULK; break; default: // USB_TRANSFER_TYPE_INTR - hal_xfer_type = USB_PRIV_XFER_TYPE_INTR; + hal_xfer_type = USB_DWC_XFER_TYPE_INTR; break; } ep_char->type = hal_xfer_type; if (is_default_pipe) { ep_char->bEndpointAddress = 0; // Set the default pipe's MPS to the worst case MPS for the device's speed - ep_char->mps = (pipe_config->dev_speed == USB_SPEED_FULL) ? CTRL_EP_MAX_MPS_FS : CTRL_EP_MAX_MPS_LS; + ep_char->mps = (pipe_config->dev_speed == USB_SPEED_LOW) ? CTRL_EP_MAX_MPS_LS : CTRL_EP_MAX_MPS_HSFS; } else { ep_char->bEndpointAddress = pipe_config->ep_desc->bEndpointAddress; - ep_char->mps = pipe_config->ep_desc->wMaxPacketSize; + ep_char->mps = USB_EP_DESC_GET_MPS(pipe_config->ep_desc); } ep_char->dev_addr = pipe_config->dev_addr; ep_char->ls_via_fs_hub = (port_speed == USB_SPEED_FULL && pipe_config->dev_speed == USB_SPEED_LOW); // Calculate the pipe's interval in terms of USB frames + // @see USB-OTG programming guide chapter 6.5 for more information if (type == USB_TRANSFER_TYPE_INTR || type == USB_TRANSFER_TYPE_ISOCHRONOUS) { - int interval_frames; - if (type == USB_TRANSFER_TYPE_INTR) { - interval_frames = pipe_config->ep_desc->bInterval; + // Convert bInterval field to real value + // @see USB 2.0 specs, Table 9-13 + unsigned int interval_value; + if (type == USB_TRANSFER_TYPE_INTR && pipe_config->dev_speed != USB_SPEED_HIGH) { + interval_value = pipe_config->ep_desc->bInterval; } else { - interval_frames = (1 << (pipe_config->ep_desc->bInterval - 1)); + interval_value = (1 << (pipe_config->ep_desc->bInterval - 1)); } // Round down interval to nearest power of 2 - if (interval_frames >= 32) { - interval_frames = 32; - } else if (interval_frames >= 16) { - interval_frames = 16; - } else if (interval_frames >= 8) { - interval_frames = 8; - } else if (interval_frames >= 4) { - interval_frames = 4; - } else if (interval_frames >= 2) { - interval_frames = 2; - } else if (interval_frames >= 1) { - interval_frames = 1; + if (interval_value >= 32) { + interval_value = 32; + } else if (interval_value >= 16) { + interval_value = 16; + } else if (interval_value >= 8) { + interval_value = 8; + } else if (interval_value >= 4) { + interval_value = 4; + } else if (interval_value >= 2) { + interval_value = 2; + } else if (interval_value >= 1) { + interval_value = 1; } - ep_char->periodic.interval = interval_frames; + ep_char->periodic.interval = interval_value; // We are the Nth pipe to be allocated. Use N as a phase offset - ep_char->periodic.phase_offset_frames = pipe_idx & (XFER_LIST_LEN_ISOC - 1); + unsigned int xfer_list_len = (type == USB_TRANSFER_TYPE_INTR) ? XFER_LIST_LEN_INTR : XFER_LIST_LEN_ISOC; + ep_char->periodic.phase_offset_frames = pipe_idx & (xfer_list_len - 1); } else { ep_char->periodic.interval = 0; ep_char->periodic.phase_offset_frames = 0; @@ -1792,7 +1662,7 @@ static esp_err_t _pipe_cmd_flush(pipe_t *pipe) // URBs were never executed, Update the actual_num_bytes and status urb->transfer.actual_num_bytes = 0; urb->transfer.status = (canceled) ? USB_TRANSFER_STATUS_CANCELED : USB_TRANSFER_STATUS_NO_DEVICE; - if (pipe->ep_char.type == USB_PRIV_XFER_TYPE_ISOCHRONOUS) { + if (pipe->ep_char.type == USB_DWC_XFER_TYPE_ISOCHRONOUS) { // Update the URB's isoc packet descriptors as well for (int pkt_idx = 0; pkt_idx < urb->transfer.num_isoc_packets; pkt_idx++) { urb->transfer.isoc_packet_desc[pkt_idx].actual_num_bytes = 0; @@ -1852,7 +1722,6 @@ esp_err_t hcd_pipe_alloc(hcd_port_handle_t port_hdl, const hcd_pipe_config_t *pi // Can only allocate a pipe if the target port is initialized and connected to an enabled device HCD_CHECK_FROM_CRIT(port->initialized && port->flags.conn_dev_ena, ESP_ERR_INVALID_STATE); usb_speed_t port_speed = port->speed; - const fifo_mps_limits_t *mps_limits = port->fifo_mps_limits; int pipe_idx = port->num_pipes_idle + port->num_pipes_queued; HCD_EXIT_CRITICAL(); @@ -1873,7 +1742,7 @@ esp_err_t hcd_pipe_alloc(hcd_port_handle_t port_hdl, const hcd_pipe_config_t *pi return ESP_ERR_NOT_SUPPORTED; } // Default pipes have a NULL ep_desc thus should skip the HCD support verification - if (!is_default && !pipe_alloc_hcd_support_verification(pipe_config->ep_desc, mps_limits)) { + if (!is_default && !pipe_alloc_hcd_support_verification(port->hal, pipe_config->ep_desc)) { return ESP_ERR_NOT_SUPPORTED; } // Allocate the pipe resources @@ -2242,11 +2111,11 @@ static void _buffer_fill(pipe_t *pipe) int mps = pipe->ep_char.mps; usb_transfer_t *transfer = &urb->transfer; switch (pipe->ep_char.type) { - case USB_PRIV_XFER_TYPE_CTRL: { + case USB_DWC_XFER_TYPE_CTRL: { _buffer_fill_ctrl(buffer_to_fill, transfer); break; } - case USB_PRIV_XFER_TYPE_ISOCHRONOUS: { + case USB_DWC_XFER_TYPE_ISOCHRONOUS: { uint32_t start_idx; if (pipe->multi_buffer_control.buffer_num_to_exec == 0) { // There are no more previously filled buffers to execute. We need to calculate a new start index based on HFNUM and the pipe's schedule @@ -2261,7 +2130,7 @@ static void _buffer_fill(pipe_t *pipe) start_idx = (next_interval_idx_no_offset + pipe->ep_char.periodic.phase_offset_frames) & (XFER_LIST_LEN_ISOC - 1); } else { // Not enough time until the next schedule, add another interval to it. - start_idx = (next_interval_idx_no_offset + pipe->ep_char.periodic.interval + pipe->ep_char.periodic.phase_offset_frames) & (XFER_LIST_LEN_ISOC - 1); + start_idx = (next_interval_idx_no_offset + pipe->ep_char.periodic.interval + pipe->ep_char.periodic.phase_offset_frames) & (XFER_LIST_LEN_ISOC - 1); } } else { // Start index is based on previously filled buffer @@ -2272,11 +2141,11 @@ static void _buffer_fill(pipe_t *pipe) _buffer_fill_isoc(buffer_to_fill, transfer, is_in, mps, (int)pipe->ep_char.periodic.interval, start_idx); break; } - case USB_PRIV_XFER_TYPE_BULK: { + case USB_DWC_XFER_TYPE_BULK: { _buffer_fill_bulk(buffer_to_fill, transfer, is_in, mps); break; } - case USB_PRIV_XFER_TYPE_INTR: { + case USB_DWC_XFER_TYPE_INTR: { _buffer_fill_intr(buffer_to_fill, transfer, is_in, mps); break; } @@ -2302,7 +2171,7 @@ static void _buffer_exec(pipe_t *pipe) uint32_t start_idx; int desc_list_len; switch (pipe->ep_char.type) { - case USB_PRIV_XFER_TYPE_CTRL: { + case USB_DWC_XFER_TYPE_CTRL: { start_idx = 0; desc_list_len = XFER_LIST_LEN_CTRL; // Set the channel's direction to OUT and PID to 0 respectively for the the setup stage @@ -2310,17 +2179,17 @@ static void _buffer_exec(pipe_t *pipe) usb_dwc_hal_chan_set_pid(pipe->chan_obj, 0); // Setup stage always has a PID of DATA0 break; } - case USB_PRIV_XFER_TYPE_ISOCHRONOUS: { + case USB_DWC_XFER_TYPE_ISOCHRONOUS: { start_idx = buffer_to_exec->flags.isoc.start_idx; desc_list_len = XFER_LIST_LEN_ISOC; break; } - case USB_PRIV_XFER_TYPE_BULK: { + case USB_DWC_XFER_TYPE_BULK: { start_idx = 0; desc_list_len = (buffer_to_exec->flags.bulk.zero_len_packet) ? XFER_LIST_LEN_BULK : 1; break; } - case USB_PRIV_XFER_TYPE_INTR: { + case USB_DWC_XFER_TYPE_INTR: { start_idx = 0; desc_list_len = (buffer_to_exec->flags.intr.zero_len_packet) ? buffer_to_exec->flags.intr.num_qtds + 1 : buffer_to_exec->flags.intr.num_qtds; break; @@ -2341,7 +2210,7 @@ static void _buffer_exec(pipe_t *pipe) static void _buffer_exec_cont(pipe_t *pipe) { // This should only ever be called on control transfers - assert(pipe->ep_char.type == USB_PRIV_XFER_TYPE_CTRL); + assert(pipe->ep_char.type == USB_DWC_XFER_TYPE_CTRL); dma_buffer_block_t *buffer_inflight = pipe->buffers[pipe->multi_buffer_control.rd_idx]; bool next_dir_is_in; int next_pid; @@ -2525,19 +2394,19 @@ static void _buffer_parse(pipe_t *pipe) if (buffer_to_parse->status_flags.pipe_event == HCD_PIPE_EVENT_URB_DONE) { // URB was successful switch (pipe->ep_char.type) { - case USB_PRIV_XFER_TYPE_CTRL: { + case USB_DWC_XFER_TYPE_CTRL: { _buffer_parse_ctrl(buffer_to_parse); break; } - case USB_PRIV_XFER_TYPE_ISOCHRONOUS: { + case USB_DWC_XFER_TYPE_ISOCHRONOUS: { _buffer_parse_isoc(buffer_to_parse, is_in); break; } - case USB_PRIV_XFER_TYPE_BULK: { + case USB_DWC_XFER_TYPE_BULK: { _buffer_parse_bulk(buffer_to_parse); break; } - case USB_PRIV_XFER_TYPE_INTR: { + case USB_DWC_XFER_TYPE_INTR: { _buffer_parse_intr(buffer_to_parse, is_in, mps); break; } diff --git a/components/usb/hub.c b/components/usb/hub.c index 40e2ae1b046..7f24a60a6d9 100644 --- a/components/usb/hub.c +++ b/components/usb/hub.c @@ -449,9 +449,16 @@ static bool enum_stage_transfer_check(enum_ctrl_t *enum_ctrl) return false; } // Check IN transfer returned the expected correct number of bytes - if (enum_ctrl->expect_num_bytes != 0 && enum_ctrl->expect_num_bytes != transfer->actual_num_bytes) { - ESP_LOGE(HUB_DRIVER_TAG, "Incorrect number of bytes returned %d: %s", transfer->actual_num_bytes, enum_stage_strings[enum_ctrl->stage]); - return false; + if (enum_ctrl->expect_num_bytes != 0 && transfer->actual_num_bytes != enum_ctrl->expect_num_bytes) { + if (transfer->actual_num_bytes > enum_ctrl->expect_num_bytes) { + // The device returned more bytes than requested. + // This violates the USB specs chapter 9.3.5, but we can continue + ESP_LOGW(HUB_DRIVER_TAG, "Incorrect number of bytes returned %d: %s", transfer->actual_num_bytes, enum_stage_strings[enum_ctrl->stage]); + } else { + // The device returned less bytes than requested. We cannot continue. + ESP_LOGE(HUB_DRIVER_TAG, "Incorrect number of bytes returned %d: %s", transfer->actual_num_bytes, enum_stage_strings[enum_ctrl->stage]); + return false; + } } // Stage specific checks and updates @@ -931,7 +938,7 @@ esp_err_t hub_install(hub_config_t *hub_config) HUB_DRIVER_EXIT_CRITICAL(); // Allocate Hub driver object hub_driver_t *hub_driver_obj = heap_caps_calloc(1, sizeof(hub_driver_t), MALLOC_CAP_DEFAULT); - urb_t *enum_urb = urb_alloc(sizeof(usb_setup_packet_t) + ENUM_CTRL_TRANSFER_MAX_DATA_LEN, 0, 0); + urb_t *enum_urb = urb_alloc(sizeof(usb_setup_packet_t) + ENUM_CTRL_TRANSFER_MAX_DATA_LEN, 0); if (hub_driver_obj == NULL || enum_urb == NULL) { return ESP_ERR_NO_MEM; } diff --git a/components/usb/include/usb/usb_types_ch9.h b/components/usb/include/usb/usb_types_ch9.h index 36c4391ccbd..8054d91f82c 100644 --- a/components/usb/include/usb/usb_types_ch9.h +++ b/components/usb/include/usb/usb_types_ch9.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -435,6 +435,12 @@ ESP_STATIC_ASSERT(sizeof(usb_ep_desc_t) == USB_EP_DESC_SIZE, "Size of usb_ep_des #define USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK 0x0f #define USB_B_ENDPOINT_ADDRESS_EP_DIR_MASK 0x80 +/** + * @brief Bit masks belonging to the wMaxPacketSize field of endpoint descriptor + */ +#define USB_W_MAX_PACKET_SIZE_MPS_MASK 0x07ff +#define USB_W_MAX_PACKET_SIZE_MULT_MASK 0x1800 + /** * @brief Bit masks belonging to the bmAttributes field of an endpoint descriptor */ @@ -459,7 +465,8 @@ ESP_STATIC_ASSERT(sizeof(usb_ep_desc_t) == USB_EP_DESC_SIZE, "Size of usb_ep_des #define USB_EP_DESC_GET_XFERTYPE(desc_ptr) ((usb_transfer_type_t) ((desc_ptr)->bmAttributes & USB_BM_ATTRIBUTES_XFERTYPE_MASK)) #define USB_EP_DESC_GET_EP_NUM(desc_ptr) ((desc_ptr)->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK) #define USB_EP_DESC_GET_EP_DIR(desc_ptr) (((desc_ptr)->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_DIR_MASK) ? 1 : 0) -#define USB_EP_DESC_GET_MPS(desc_ptr) ((desc_ptr)->wMaxPacketSize & 0x7FF) +#define USB_EP_DESC_GET_MPS(desc_ptr) ((desc_ptr)->wMaxPacketSize & USB_W_MAX_PACKET_SIZE_MPS_MASK) +#define USB_EP_DESC_GET_MULT(desc_ptr) (((desc_ptr)->wMaxPacketSize & USB_W_MAX_PACKET_SIZE_MULT_MASK) >> 11) // ------------------ String Descriptor -------------------- diff --git a/components/usb/include/usb/usb_types_stack.h b/components/usb/include/usb/usb_types_stack.h index 94ab481ee9b..00af897182c 100644 --- a/components/usb/include/usb/usb_types_stack.h +++ b/components/usb/include/usb/usb_types_stack.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,7 @@ extern "C" { typedef enum { USB_SPEED_LOW = 0, /**< USB Low Speed (1.5 Mbit/s) */ USB_SPEED_FULL, /**< USB Full Speed (12 Mbit/s) */ + USB_SPEED_HIGH, /**< USB High Speed (480 Mbit/s) */ } usb_speed_t; /** diff --git a/components/usb/private_include/usb_private.h b/components/usb/private_include/usb_private.h index ccdcd44a23c..4fb25cc4ee6 100644 --- a/components/usb/private_include/usb_private.h +++ b/components/usb/private_include/usb_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,7 +43,6 @@ struct urb_s { uint32_t hcd_var; // Host Lib Layer: void *usb_host_client; // Currently only used when submitted to shared pipes (i.e., Device default pipes) - size_t usb_host_header_size; // USB Host may need the data buffer to have a transparent header bool usb_host_inflight; // Debugging variable, used to prevent re-submitting URBs already inflight // Public transfer structure. Must be last due to variable length array usb_transfer_t transfer; @@ -76,15 +75,13 @@ typedef bool (*usb_proc_req_cb_t)(usb_proc_req_source_t source, bool in_isr, voi * * - Data buffer is allocated in DMA capable memory * - The constant fields of the URB are also set - * - The data_buffer field of the URB is set to point to start of the allocated data buffer AFTER the header. To access - * the header, users need a negative offset from data_buffer. + * - The data_buffer field of the URB is set to point to start of the allocated data buffer. * * @param data_buffer_size Size of the URB's data buffer - * @param header_size Size of header to put in front of URB's data buffer * @param num_isoc_packets Number of isochronous packet descriptors * @return urb_t* URB object */ -urb_t *urb_alloc(size_t data_buffer_size, size_t header_size, int num_isoc_packets); +urb_t *urb_alloc(size_t data_buffer_size, int num_isoc_packets); /** * @brief Free a URB diff --git a/components/usb/test_apps/common/test_usb_mock_msc.c b/components/usb/test_apps/common/test_usb_mock_msc.c index 6307ddd9262..db61ec10b7f 100644 --- a/components/usb/test_apps/common/test_usb_mock_msc.c +++ b/components/usb/test_apps/common/test_usb_mock_msc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -137,21 +137,21 @@ void mock_msc_scsi_init_reference_descriptors(void) // String descriptors const char *str = MOCK_MSC_SCSI_STRING_1; uint8_t chr_count = strlen(str); - mock_msc_scsi_str_desc_manu[0] = (USB_B_DESCRIPTOR_TYPE_STRING << 8 ) | (2 * chr_count + 2); // first byte is length (including header), second byte is string type + mock_msc_scsi_str_desc_manu[0] = (USB_B_DESCRIPTOR_TYPE_STRING << 8) | (2 * chr_count + 2); // first byte is length (including header), second byte is string type for (uint8_t i = 0; i < chr_count; i++) { mock_msc_scsi_str_desc_manu[1 + i] = str[i]; } str = MOCK_MSC_SCSI_STRING_2; chr_count = strlen(str); - mock_msc_scsi_str_desc_prod[0] = (USB_B_DESCRIPTOR_TYPE_STRING << 8 ) | (2 * chr_count + 2); // first byte is length (including header), second byte is string type + mock_msc_scsi_str_desc_prod[0] = (USB_B_DESCRIPTOR_TYPE_STRING << 8) | (2 * chr_count + 2); // first byte is length (including header), second byte is string type for (uint8_t i = 0; i < chr_count; i++) { mock_msc_scsi_str_desc_prod[1 + i] = str[i]; } str = MOCK_MSC_SCSI_STRING_3; chr_count = strlen(str); - mock_msc_scsi_str_desc_ser_num[0] = (USB_B_DESCRIPTOR_TYPE_STRING << 8 ) | (2 * chr_count + 2); // first byte is length (including header), second byte is string type + mock_msc_scsi_str_desc_ser_num[0] = (USB_B_DESCRIPTOR_TYPE_STRING << 8) | (2 * chr_count + 2); // first byte is length (including header), second byte is string type for (uint8_t i = 0; i < chr_count; i++) { mock_msc_scsi_str_desc_ser_num[1 + i] = str[i]; } diff --git a/components/usb/test_apps/common/test_usb_mock_msc.h b/components/usb/test_apps/common/test_usb_mock_msc.h index 4d5685d56e8..accd78e82e2 100644 --- a/components/usb/test_apps/common/test_usb_mock_msc.h +++ b/components/usb/test_apps/common/test_usb_mock_msc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -112,7 +112,8 @@ extern const usb_ep_desc_t mock_msc_scsi_bulk_in_ep_desc; (setup_pkt_ptr)->wLength = 0; \ }) -typedef struct __attribute__((packed)) { +typedef struct __attribute__((packed)) +{ uint8_t opcode; //0x28 = read(10), 0x2A=write(10) uint8_t flags; uint8_t lba_3; @@ -125,7 +126,8 @@ typedef struct __attribute__((packed)) { uint8_t control; } mock_scsi_cmd10_t; -typedef struct __attribute__((packed)) { +typedef struct __attribute__((packed)) +{ uint32_t dCBWSignature; uint32_t dCBWTag; uint32_t dCBWDataTransferLength; @@ -137,7 +139,8 @@ typedef struct __attribute__((packed)) { } mock_msc_bulk_cbw_t; // USB Bulk Transfer Command Status Wrapper data -typedef struct __attribute__((packed)) { +typedef struct __attribute__((packed)) +{ uint32_t dCSWSignature; uint32_t dCSWTag; uint32_t dCSWDataResidue; @@ -180,7 +183,6 @@ ISOC, transferring to a non-existent endpoint should work. The non-existent endp #define MOCK_ISOC_EP_NUM 2 #define MOCK_ISOC_EP_MPS 512 - static const usb_ep_desc_t mock_isoc_out_ep_desc = { .bLength = sizeof(usb_ep_desc_t), .bDescriptorType = USB_B_DESCRIPTOR_TYPE_ENDPOINT, @@ -190,7 +192,6 @@ static const usb_ep_desc_t mock_isoc_out_ep_desc = { .bInterval = 1, //Isoc interval is (2 ^ (bInterval - 1)) which means an interval of 1ms }; - #ifdef __cplusplus } #endif diff --git a/components/usb/test_apps/hcd/main/test_hcd_bulk.c b/components/usb/test_apps/hcd/main/test_hcd_bulk.c index c425c5b2d3d..b22273752a1 100644 --- a/components/usb/test_apps/hcd/main/test_hcd_bulk.c +++ b/components/usb/test_apps/hcd/main/test_hcd_bulk.c @@ -68,10 +68,11 @@ TEST_CASE("Test HCD bulk pipe URBs", "[bulk][full_speed]") //Create URBs for CBW, Data, and CSW transport. IN Buffer sizes are rounded up to nearest MPS urb_t *urb_cbw = test_hcd_alloc_urb(0, sizeof(mock_msc_bulk_cbw_t)); urb_t *urb_data = test_hcd_alloc_urb(0, TEST_NUM_SECTORS_PER_XFER * MOCK_MSC_SCSI_SECTOR_SIZE); - urb_t *urb_csw = test_hcd_alloc_urb(0, sizeof(mock_msc_bulk_csw_t) + (mock_msc_scsi_bulk_in_ep_desc.wMaxPacketSize - (sizeof(mock_msc_bulk_csw_t) % mock_msc_scsi_bulk_in_ep_desc.wMaxPacketSize))); + const uint16_t mps = USB_EP_DESC_GET_MPS(&mock_msc_scsi_bulk_in_ep_desc) ; + urb_t *urb_csw = test_hcd_alloc_urb(0, sizeof(mock_msc_bulk_csw_t) + (mps - (sizeof(mock_msc_bulk_csw_t) % mps))); urb_cbw->transfer.num_bytes = sizeof(mock_msc_bulk_cbw_t); urb_data->transfer.num_bytes = TEST_NUM_SECTORS_PER_XFER * MOCK_MSC_SCSI_SECTOR_SIZE; - urb_csw->transfer.num_bytes = sizeof(mock_msc_bulk_csw_t) + (mock_msc_scsi_bulk_in_ep_desc.wMaxPacketSize - (sizeof(mock_msc_bulk_csw_t) % mock_msc_scsi_bulk_in_ep_desc.wMaxPacketSize)); + urb_csw->transfer.num_bytes = sizeof(mock_msc_bulk_csw_t) + (mps - (sizeof(mock_msc_bulk_csw_t) % mps)); for (int block_num = 0; block_num < TEST_NUM_SECTORS_TOTAL; block_num += TEST_NUM_SECTORS_PER_XFER) { //Initialize CBW URB, then send it on the BULK OUT pipe diff --git a/components/usb/test_apps/hcd/main/test_hcd_ctrl.c b/components/usb/test_apps/hcd/main/test_hcd_ctrl.c index 9f66a2afc94..789d8b3c662 100644 --- a/components/usb/test_apps/hcd/main/test_hcd_ctrl.c +++ b/components/usb/test_apps/hcd/main/test_hcd_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,7 +68,7 @@ TEST_CASE("Test HCD control pipe URBs", "[ctrl][low_speed][full_speed]") TEST_ASSERT_GREATER_OR_EQUAL(sizeof(usb_setup_packet_t), urb->transfer.actual_num_bytes); TEST_ASSERT_LESS_OR_EQUAL(urb->transfer.num_bytes, urb->transfer.actual_num_bytes); usb_config_desc_t *config_desc = (usb_config_desc_t *)(urb->transfer.data_buffer + sizeof(usb_setup_packet_t)); - TEST_ASSERT_EQUAL(USB_B_DESCRIPTOR_TYPE_CONFIGURATION , config_desc->bDescriptorType); + TEST_ASSERT_EQUAL(USB_B_DESCRIPTOR_TYPE_CONFIGURATION, config_desc->bDescriptorType); printf("Config Desc wTotalLength %d\n", config_desc->wTotalLength); } @@ -201,7 +201,7 @@ TEST_CASE("Test HCD control pipe STALL", "[ctrl][full_speed]") TEST_ASSERT_GREATER_OR_EQUAL(sizeof(usb_setup_packet_t), urb->transfer.actual_num_bytes); TEST_ASSERT_LESS_OR_EQUAL(urb->transfer.num_bytes, urb->transfer.actual_num_bytes); usb_config_desc_t *config_desc = (usb_config_desc_t *)(urb->transfer.data_buffer + sizeof(usb_setup_packet_t)); - TEST_ASSERT_EQUAL(USB_B_DESCRIPTOR_TYPE_CONFIGURATION , config_desc->bDescriptorType); + TEST_ASSERT_EQUAL(USB_B_DESCRIPTOR_TYPE_CONFIGURATION, config_desc->bDescriptorType); printf("Config Desc wTotalLength %d\n", config_desc->wTotalLength); } @@ -270,11 +270,11 @@ TEST_CASE("Test HCD control pipe runtime halt and clear", "[ctrl][low_speed][ful TEST_ASSERT_EQUAL_PTR(urb_list[i], urb); TEST_ASSERT(urb->transfer.status == USB_TRANSFER_STATUS_COMPLETED || urb->transfer.status == USB_TRANSFER_STATUS_CANCELED); if (urb->transfer.status == USB_TRANSFER_STATUS_COMPLETED) { - //We must have transmitted at least the setup packet, but device may return less than bytes requested + //We must have transmitted at least the setup packet, but device may return less than bytes requested TEST_ASSERT_GREATER_OR_EQUAL(sizeof(usb_setup_packet_t), urb->transfer.actual_num_bytes); TEST_ASSERT_LESS_OR_EQUAL(urb->transfer.num_bytes, urb->transfer.actual_num_bytes); usb_config_desc_t *config_desc = (usb_config_desc_t *)(urb->transfer.data_buffer + sizeof(usb_setup_packet_t)); - TEST_ASSERT_EQUAL(USB_B_DESCRIPTOR_TYPE_CONFIGURATION , config_desc->bDescriptorType); + TEST_ASSERT_EQUAL(USB_B_DESCRIPTOR_TYPE_CONFIGURATION, config_desc->bDescriptorType); printf("Config Desc wTotalLength %d\n", config_desc->wTotalLength); } else { //A failed transfer should 0 actual number of bytes transmitted diff --git a/components/usb/test_apps/usb_host/main/ctrl_client_async_seq.c b/components/usb/test_apps/usb_host/main/ctrl_client_async_seq.c index 6c2ca51788a..b163dc20fbc 100644 --- a/components/usb/test_apps/usb_host/main/ctrl_client_async_seq.c +++ b/components/usb/test_apps/usb_host/main/ctrl_client_async_seq.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -76,14 +76,14 @@ static void ctrl_client_event_cb(const usb_host_client_event_msg_t *event_msg, v { ctrl_client_obj_t *ctrl_obj = (ctrl_client_obj_t *)arg; switch (event_msg->event) { - case USB_HOST_CLIENT_EVENT_NEW_DEV: - TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, ctrl_obj->cur_stage); - ctrl_obj->next_stage = TEST_STAGE_DEV_OPEN; - ctrl_obj->dev_addr_to_open = event_msg->new_dev.address; - break; - default: - abort(); //Should never occur in this test - break; + case USB_HOST_CLIENT_EVENT_NEW_DEV: + TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, ctrl_obj->cur_stage); + ctrl_obj->next_stage = TEST_STAGE_DEV_OPEN; + ctrl_obj->dev_addr_to_open = event_msg->new_dev.address; + break; + default: + abort(); //Should never occur in this test + break; } } @@ -100,7 +100,7 @@ void ctrl_client_async_seq_task(void *arg) .max_num_event_msg = CTRL_CLIENT_MAX_EVENT_MSGS, .async = { .client_event_callback = ctrl_client_event_cb, - .callback_arg = (void *)&ctrl_obj, + .callback_arg = (void *) &ctrl_obj, }, }; TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_register(&client_config, &ctrl_obj.client_hdl)); @@ -130,52 +130,52 @@ void ctrl_client_async_seq_task(void *arg) ctrl_obj.cur_stage = ctrl_obj.next_stage; switch (ctrl_obj.next_stage) { - case TEST_STAGE_DEV_OPEN: { - ESP_LOGD(CTRL_CLIENT_TAG, "Open"); - //Open the device - TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, usb_host_device_open(ctrl_obj.client_hdl, ctrl_obj.dev_addr_to_open, &ctrl_obj.dev_hdl), "Failed to open the device"); - //Target our transfers to the device - for (int i = 0; i < NUM_TRANSFER_OBJ; i++) { - ctrl_xfer[i]->device_handle = ctrl_obj.dev_hdl; - } - //Check the VID/PID of the opened device - const usb_device_desc_t *device_desc; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(ctrl_obj.dev_hdl, &device_desc)); - TEST_ASSERT_EQUAL(ctrl_obj.test_param.idVendor, device_desc->idVendor); - TEST_ASSERT_EQUAL(ctrl_obj.test_param.idProduct, device_desc->idProduct); - //Cache the active configuration descriptor for later comparison - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_active_config_descriptor(ctrl_obj.dev_hdl, &ctrl_obj.config_desc_cached)); - ctrl_obj.next_stage = TEST_STAGE_CTRL_XFER; - skip_event_handling = true; - break; - } - case TEST_STAGE_CTRL_XFER: { - ESP_LOGD(CTRL_CLIENT_TAG, "Transfer"); - //Send a control transfer to get the device's configuration descriptor - usb_transfer_t *transfer = ctrl_xfer[ctrl_obj.num_xfer_sent % NUM_TRANSFER_OBJ]; - USB_SETUP_PACKET_INIT_GET_CONFIG_DESC((usb_setup_packet_t *)transfer->data_buffer, 0, MAX_TRANSFER_BYTES); - transfer->num_bytes = sizeof(usb_setup_packet_t) + MAX_TRANSFER_BYTES; - transfer->bEndpointAddress = 0x80; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit_control(ctrl_obj.client_hdl, transfer)); - ctrl_obj.num_xfer_sent++; - ctrl_obj.next_stage = TEST_STAGE_CTRL_XFER_WAIT; - skip_event_handling = true; - break; + case TEST_STAGE_DEV_OPEN: { + ESP_LOGD(CTRL_CLIENT_TAG, "Open"); + //Open the device + TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, usb_host_device_open(ctrl_obj.client_hdl, ctrl_obj.dev_addr_to_open, &ctrl_obj.dev_hdl), "Failed to open the device"); + //Target our transfers to the device + for (int i = 0; i < NUM_TRANSFER_OBJ; i++) { + ctrl_xfer[i]->device_handle = ctrl_obj.dev_hdl; } - case TEST_STAGE_CTRL_XFER_WAIT: { - //Nothing to do but wait - break; - } - case TEST_STAGE_DEV_CLOSE: { - ESP_LOGD(CTRL_CLIENT_TAG, "Close"); - vTaskDelay(10); // Give USB Host Lib some time to process all trnsfers - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(ctrl_obj.client_hdl, ctrl_obj.dev_hdl)); - exit_loop = true; - break; - } - default: - abort(); - break; + //Check the VID/PID of the opened device + const usb_device_desc_t *device_desc; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(ctrl_obj.dev_hdl, &device_desc)); + TEST_ASSERT_EQUAL(ctrl_obj.test_param.idVendor, device_desc->idVendor); + TEST_ASSERT_EQUAL(ctrl_obj.test_param.idProduct, device_desc->idProduct); + //Cache the active configuration descriptor for later comparison + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_active_config_descriptor(ctrl_obj.dev_hdl, &ctrl_obj.config_desc_cached)); + ctrl_obj.next_stage = TEST_STAGE_CTRL_XFER; + skip_event_handling = true; + break; + } + case TEST_STAGE_CTRL_XFER: { + ESP_LOGD(CTRL_CLIENT_TAG, "Transfer"); + //Send a control transfer to get the device's configuration descriptor + usb_transfer_t *transfer = ctrl_xfer[ctrl_obj.num_xfer_sent % NUM_TRANSFER_OBJ]; + USB_SETUP_PACKET_INIT_GET_CONFIG_DESC((usb_setup_packet_t *)transfer->data_buffer, 0, MAX_TRANSFER_BYTES); + transfer->num_bytes = sizeof(usb_setup_packet_t) + MAX_TRANSFER_BYTES; + transfer->bEndpointAddress = 0x80; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit_control(ctrl_obj.client_hdl, transfer)); + ctrl_obj.num_xfer_sent++; + ctrl_obj.next_stage = TEST_STAGE_CTRL_XFER_WAIT; + skip_event_handling = true; + break; + } + case TEST_STAGE_CTRL_XFER_WAIT: { + //Nothing to do but wait + break; + } + case TEST_STAGE_DEV_CLOSE: { + ESP_LOGD(CTRL_CLIENT_TAG, "Close"); + vTaskDelay(10); // Give USB Host Lib some time to process all trnsfers + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(ctrl_obj.client_hdl, ctrl_obj.dev_hdl)); + exit_loop = true; + break; + } + default: + abort(); + break; } } //Free transfers and deregister client diff --git a/components/usb/test_apps/usb_host/main/msc_client_async_dconn.c b/components/usb/test_apps/usb_host/main/msc_client_async_dconn.c index 6e98e2b2299..4f1e96b8d99 100644 --- a/components/usb/test_apps/usb_host/main/msc_client_async_dconn.c +++ b/components/usb/test_apps/usb_host/main/msc_client_async_dconn.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -64,15 +64,15 @@ static void msc_reset_cbw_transfer_cb(usb_transfer_t *transfer) TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); TEST_ASSERT_EQUAL(transfer->num_bytes, transfer->actual_num_bytes); switch (msc_obj->cur_stage) { - case TEST_STAGE_MSC_RESET: - msc_obj->next_stage = TEST_STAGE_MSC_CBW; - break; - case TEST_STAGE_MSC_CBW: - msc_obj->next_stage = TEST_STAGE_MSC_DATA_DCONN; - break; - default: - abort(); - break; + case TEST_STAGE_MSC_RESET: + msc_obj->next_stage = TEST_STAGE_MSC_CBW; + break; + case TEST_STAGE_MSC_CBW: + msc_obj->next_stage = TEST_STAGE_MSC_DATA_DCONN; + break; + default: + abort(); + break; } } @@ -97,21 +97,21 @@ static void msc_client_event_cb(const usb_host_client_event_msg_t *event_msg, vo { msc_client_obj_t *msc_obj = (msc_client_obj_t *)arg; switch (event_msg->event) { - case USB_HOST_CLIENT_EVENT_NEW_DEV: - TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, msc_obj->cur_stage); - msc_obj->next_stage = TEST_STAGE_DEV_OPEN; - msc_obj->dev_addr_to_open = event_msg->new_dev.address; - break; - case USB_HOST_CLIENT_EVENT_DEV_GONE: - msc_obj->event_count++; - //If all transfers dequeued and device gone event occurred. Go to next stage - if (msc_obj->event_count >= msc_obj->num_data_transfers + 1) { - msc_obj->next_stage = TEST_STAGE_DEV_CLOSE; - } - break; - default: - abort(); //Should never occur in this test - break; + case USB_HOST_CLIENT_EVENT_NEW_DEV: + TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, msc_obj->cur_stage); + msc_obj->next_stage = TEST_STAGE_DEV_OPEN; + msc_obj->dev_addr_to_open = event_msg->new_dev.address; + break; + case USB_HOST_CLIENT_EVENT_DEV_GONE: + msc_obj->event_count++; + //If all transfers dequeued and device gone event occurred. Go to next stage + if (msc_obj->event_count >= msc_obj->num_data_transfers + 1) { + msc_obj->next_stage = TEST_STAGE_DEV_CLOSE; + } + break; + default: + abort(); //Should never occur in this test + break; } } @@ -133,7 +133,7 @@ void msc_client_async_dconn_task(void *arg) .max_num_event_msg = MSC_ASYNC_CLIENT_MAX_EVENT_MSGS, .async = { .client_event_callback = msc_client_event_cb, - .callback_arg = (void *)&msc_obj, + .callback_arg = (void *) &msc_obj, }, }; TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_register(&client_config, &msc_obj.client_hdl)); @@ -168,85 +168,85 @@ void msc_client_async_dconn_task(void *arg) msc_obj.cur_stage = msc_obj.next_stage; switch (msc_obj.cur_stage) { - case TEST_STAGE_WAIT_CONN: { - //Nothing to do while waiting for connection - break; - } - case TEST_STAGE_DEV_OPEN: { - ESP_LOGD(MSC_CLIENT_TAG, "Open"); - //Open the device - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_open(msc_obj.client_hdl, msc_obj.dev_addr_to_open, &msc_obj.dev_hdl)); - //Target our transfers to the device - xfer_out->device_handle = msc_obj.dev_hdl; - xfer_out->callback = msc_reset_cbw_transfer_cb; - for (int i = 0; i < msc_obj.num_data_transfers; i++) { - xfer_in[i]->device_handle = msc_obj.dev_hdl; - xfer_in[i]->callback = msc_data_transfer_cb; - } - //Check the VID/PID of the opened device - const usb_device_desc_t *device_desc; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(msc_obj.dev_hdl, &device_desc)); - TEST_ASSERT_EQUAL(msc_obj.test_param.idVendor, device_desc->idVendor); - TEST_ASSERT_EQUAL(msc_obj.test_param.idProduct, device_desc->idProduct); - //Claim the MSC interface - TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_claim(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER, MOCK_MSC_SCSI_INTF_ALT_SETTING)); - msc_obj.next_stage = TEST_STAGE_MSC_RESET; - skip_event_handling = true; //Need to execute TEST_STAGE_MSC_RESET - break; - } - case TEST_STAGE_MSC_RESET: { - ESP_LOGD(MSC_CLIENT_TAG, "MSC Reset"); - //Send an MSC SCSI interface reset - MOCK_MSC_SCSI_REQ_INIT_RESET((usb_setup_packet_t *)xfer_out->data_buffer, MOCK_MSC_SCSI_INTF_NUMBER); - xfer_out->num_bytes = sizeof(usb_setup_packet_t); - xfer_out->bEndpointAddress = 0; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit_control(msc_obj.client_hdl, xfer_out)); - //Next stage set from transfer callback - break; + case TEST_STAGE_WAIT_CONN: { + //Nothing to do while waiting for connection + break; + } + case TEST_STAGE_DEV_OPEN: { + ESP_LOGD(MSC_CLIENT_TAG, "Open"); + //Open the device + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_open(msc_obj.client_hdl, msc_obj.dev_addr_to_open, &msc_obj.dev_hdl)); + //Target our transfers to the device + xfer_out->device_handle = msc_obj.dev_hdl; + xfer_out->callback = msc_reset_cbw_transfer_cb; + for (int i = 0; i < msc_obj.num_data_transfers; i++) { + xfer_in[i]->device_handle = msc_obj.dev_hdl; + xfer_in[i]->callback = msc_data_transfer_cb; } - case TEST_STAGE_MSC_CBW: { - ESP_LOGD(MSC_CLIENT_TAG, "CBW"); - mock_msc_scsi_init_cbw((mock_msc_bulk_cbw_t *)xfer_out->data_buffer, true, 0, msc_obj.test_param.num_sectors_per_xfer, msc_obj.test_param.msc_scsi_xfer_tag); - xfer_out->num_bytes = sizeof(mock_msc_bulk_cbw_t); - xfer_out->bEndpointAddress = MOCK_MSC_SCSI_BULK_OUT_EP_ADDR; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_out)); - //Next stage set from transfer callback - break; + //Check the VID/PID of the opened device + const usb_device_desc_t *device_desc; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(msc_obj.dev_hdl, &device_desc)); + TEST_ASSERT_EQUAL(msc_obj.test_param.idVendor, device_desc->idVendor); + TEST_ASSERT_EQUAL(msc_obj.test_param.idProduct, device_desc->idProduct); + //Claim the MSC interface + TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_claim(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER, MOCK_MSC_SCSI_INTF_ALT_SETTING)); + msc_obj.next_stage = TEST_STAGE_MSC_RESET; + skip_event_handling = true; //Need to execute TEST_STAGE_MSC_RESET + break; + } + case TEST_STAGE_MSC_RESET: { + ESP_LOGD(MSC_CLIENT_TAG, "MSC Reset"); + //Send an MSC SCSI interface reset + MOCK_MSC_SCSI_REQ_INIT_RESET((usb_setup_packet_t *)xfer_out->data_buffer, MOCK_MSC_SCSI_INTF_NUMBER); + xfer_out->num_bytes = sizeof(usb_setup_packet_t); + xfer_out->bEndpointAddress = 0; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit_control(msc_obj.client_hdl, xfer_out)); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_MSC_CBW: { + ESP_LOGD(MSC_CLIENT_TAG, "CBW"); + mock_msc_scsi_init_cbw((mock_msc_bulk_cbw_t *)xfer_out->data_buffer, true, 0, msc_obj.test_param.num_sectors_per_xfer, msc_obj.test_param.msc_scsi_xfer_tag); + xfer_out->num_bytes = sizeof(mock_msc_bulk_cbw_t); + xfer_out->bEndpointAddress = MOCK_MSC_SCSI_BULK_OUT_EP_ADDR; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_out)); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_MSC_DATA_DCONN: { + ESP_LOGD(MSC_CLIENT_TAG, "Data and disconnect"); + //Setup the Data IN transfers + for (int i = 0; i < msc_obj.num_data_transfers; i++) { + xfer_in[i]->num_bytes = usb_round_up_to_mps(MOCK_MSC_SCSI_SECTOR_SIZE, MOCK_MSC_SCSI_BULK_EP_MPS); + xfer_in[i]->bEndpointAddress = MOCK_MSC_SCSI_BULK_IN_EP_ADDR; } - case TEST_STAGE_MSC_DATA_DCONN: { - ESP_LOGD(MSC_CLIENT_TAG, "Data and disconnect"); - //Setup the Data IN transfers - for (int i = 0; i < msc_obj.num_data_transfers; i++) { - xfer_in[i]->num_bytes = usb_round_up_to_mps(MOCK_MSC_SCSI_SECTOR_SIZE, MOCK_MSC_SCSI_BULK_EP_MPS); - xfer_in[i]->bEndpointAddress = MOCK_MSC_SCSI_BULK_IN_EP_ADDR; - } - //Submit those transfers - for (int i = 0; i < msc_obj.num_data_transfers; i++) { - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_in[i])); - } - //Trigger a disconnect - test_usb_set_phy_state(false, 0); - //Next stage set from transfer callback - break; + //Submit those transfers + for (int i = 0; i < msc_obj.num_data_transfers; i++) { + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_in[i])); } - case TEST_STAGE_DEV_CLOSE: { - ESP_LOGD(MSC_CLIENT_TAG, "Close"); - TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_release(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER)); - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(msc_obj.client_hdl, msc_obj.dev_hdl)); - dconn_iter++; - if (dconn_iter < TEST_DCONN_ITERATIONS) { - //Start the next test iteration by going back to TEST_STAGE_WAIT_CONN and reenabling connections - msc_obj.next_stage = TEST_STAGE_WAIT_CONN; - skip_event_handling = true; //Need to execute TEST_STAGE_WAIT_CONN - test_usb_set_phy_state(true, 0); - } else { - exit_loop = true; - } - break; + //Trigger a disconnect + test_usb_set_phy_state(false, 0); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_DEV_CLOSE: { + ESP_LOGD(MSC_CLIENT_TAG, "Close"); + TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_release(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER)); + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(msc_obj.client_hdl, msc_obj.dev_hdl)); + dconn_iter++; + if (dconn_iter < TEST_DCONN_ITERATIONS) { + //Start the next test iteration by going back to TEST_STAGE_WAIT_CONN and reenabling connections + msc_obj.next_stage = TEST_STAGE_WAIT_CONN; + skip_event_handling = true; //Need to execute TEST_STAGE_WAIT_CONN + test_usb_set_phy_state(true, 0); + } else { + exit_loop = true; } - default: - abort(); - break; + break; + } + default: + abort(); + break; } } //Free transfers diff --git a/components/usb/test_apps/usb_host/main/msc_client_async_enum.c b/components/usb/test_apps/usb_host/main/msc_client_async_enum.c index 82100133126..f0a72bd69c5 100644 --- a/components/usb/test_apps/usb_host/main/msc_client_async_enum.c +++ b/components/usb/test_apps/usb_host/main/msc_client_async_enum.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -54,14 +54,14 @@ static void msc_client_event_cb(const usb_host_client_event_msg_t *event_msg, vo { msc_client_obj_t *msc_obj = (msc_client_obj_t *)arg; switch (event_msg->event) { - case USB_HOST_CLIENT_EVENT_NEW_DEV: - TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, msc_obj->cur_stage); - msc_obj->next_stage = TEST_STAGE_DEV_OPEN; - msc_obj->dev_addr_to_open = event_msg->new_dev.address; - break; - default: - abort(); //Should never occur in this test - break; + case USB_HOST_CLIENT_EVENT_NEW_DEV: + TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, msc_obj->cur_stage); + msc_obj->next_stage = TEST_STAGE_DEV_OPEN; + msc_obj->dev_addr_to_open = event_msg->new_dev.address; + break; + default: + abort(); //Should never occur in this test + break; } } @@ -81,7 +81,7 @@ void msc_client_async_enum_task(void *arg) .max_num_event_msg = MSC_ASYNC_CLIENT_MAX_EVENT_MSGS, .async = { .client_event_callback = msc_client_event_cb, - .callback_arg = (void *)&msc_obj, + .callback_arg = (void *) &msc_obj, }, }; TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_register(&client_config, &msc_obj.client_hdl)); @@ -104,78 +104,78 @@ void msc_client_async_enum_task(void *arg) msc_obj.cur_stage = msc_obj.next_stage; switch (msc_obj.cur_stage) { - case TEST_STAGE_WAIT_CONN: { - //Wait for connection, nothing to do - break; - } - case TEST_STAGE_DEV_OPEN: { - ESP_LOGD(MSC_CLIENT_TAG, "Open"); - //Open the device - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_open(msc_obj.client_hdl, msc_obj.dev_addr_to_open, &msc_obj.dev_hdl)); - msc_obj.next_stage = TEST_STAGE_CHECK_DEV_DESC; - skip_event_handling = true; //Need to execute TEST_STAGE_CHECK_DEV_DESC - break; - } - case TEST_STAGE_CHECK_DEV_DESC: { - //Check the device descriptor - const usb_device_desc_t *device_desc; - const usb_device_desc_t *device_desc_ref = &mock_msc_scsi_dev_desc; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(msc_obj.dev_hdl, &device_desc)); - TEST_ASSERT_EQUAL(device_desc_ref->bLength, device_desc->bLength); - TEST_ASSERT_EQUAL_MEMORY_MESSAGE(device_desc_ref, device_desc, device_desc_ref->bLength, "Device descriptors do not match."); - msc_obj.next_stage = TEST_STAGE_CHECK_CONFIG_DESC; - skip_event_handling = true; //Need to execute TEST_STAGE_CHECK_CONFIG_DESC - break; - } + case TEST_STAGE_WAIT_CONN: { + //Wait for connection, nothing to do + break; + } + case TEST_STAGE_DEV_OPEN: { + ESP_LOGD(MSC_CLIENT_TAG, "Open"); + //Open the device + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_open(msc_obj.client_hdl, msc_obj.dev_addr_to_open, &msc_obj.dev_hdl)); + msc_obj.next_stage = TEST_STAGE_CHECK_DEV_DESC; + skip_event_handling = true; //Need to execute TEST_STAGE_CHECK_DEV_DESC + break; + } + case TEST_STAGE_CHECK_DEV_DESC: { + //Check the device descriptor + const usb_device_desc_t *device_desc; + const usb_device_desc_t *device_desc_ref = &mock_msc_scsi_dev_desc; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(msc_obj.dev_hdl, &device_desc)); + TEST_ASSERT_EQUAL(device_desc_ref->bLength, device_desc->bLength); + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(device_desc_ref, device_desc, device_desc_ref->bLength, "Device descriptors do not match."); + msc_obj.next_stage = TEST_STAGE_CHECK_CONFIG_DESC; + skip_event_handling = true; //Need to execute TEST_STAGE_CHECK_CONFIG_DESC + break; + } - case TEST_STAGE_CHECK_CONFIG_DESC: { - //Check the configuration descriptor - const usb_config_desc_t *config_desc; - const usb_config_desc_t *config_desc_ref = (const usb_config_desc_t *)mock_msc_scsi_config_desc; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_active_config_descriptor(msc_obj.dev_hdl, &config_desc)); - TEST_ASSERT_EQUAL_MESSAGE(config_desc_ref->wTotalLength, config_desc->wTotalLength, "Incorrent length of CFG descriptor"); - TEST_ASSERT_EQUAL_MEMORY_MESSAGE(config_desc_ref, config_desc, config_desc_ref->wTotalLength, "Configuration descriptors do not match"); - msc_obj.next_stage = TEST_STAGE_CHECK_STR_DESC; - skip_event_handling = true; //Need to execute TEST_STAGE_CHECK_STR_DESC - break; - } - case TEST_STAGE_CHECK_STR_DESC: { - usb_device_info_t dev_info; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_info(msc_obj.dev_hdl, &dev_info)); - //Check manufacturer string descriptors - const usb_str_desc_t *manu_str_desc_ref = (const usb_str_desc_t *)mock_msc_scsi_str_desc_manu; - const usb_str_desc_t *product_str_desc_ref = (const usb_str_desc_t *)mock_msc_scsi_str_desc_prod; - const usb_str_desc_t *ser_num_str_desc_ref = (const usb_str_desc_t *)mock_msc_scsi_str_desc_ser_num; - TEST_ASSERT_EQUAL(manu_str_desc_ref->bLength, dev_info.str_desc_manufacturer->bLength); - TEST_ASSERT_EQUAL(product_str_desc_ref->bLength, dev_info.str_desc_product->bLength); - TEST_ASSERT_EQUAL(ser_num_str_desc_ref->bLength, dev_info.str_desc_serial_num->bLength); - TEST_ASSERT_EQUAL_MEMORY_MESSAGE(manu_str_desc_ref, dev_info.str_desc_manufacturer , manu_str_desc_ref->bLength, "Manufacturer string descriptors do not match."); - TEST_ASSERT_EQUAL_MEMORY_MESSAGE(product_str_desc_ref, dev_info.str_desc_product , manu_str_desc_ref->bLength, "Product string descriptors do not match."); - //TEST_ASSERT_EQUAL_MEMORY_MESSAGE(ser_num_str_desc_ref, dev_info.str_desc_serial_num , manu_str_desc_ref->bLength, "Serial number string descriptors do not match."); - //Get dev info and compare - msc_obj.next_stage = TEST_STAGE_DEV_CLOSE; - skip_event_handling = true; //Need to execute TEST_STAGE_DEV_CLOSE - break; - } + case TEST_STAGE_CHECK_CONFIG_DESC: { + //Check the configuration descriptor + const usb_config_desc_t *config_desc; + const usb_config_desc_t *config_desc_ref = (const usb_config_desc_t *)mock_msc_scsi_config_desc; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_active_config_descriptor(msc_obj.dev_hdl, &config_desc)); + TEST_ASSERT_EQUAL_MESSAGE(config_desc_ref->wTotalLength, config_desc->wTotalLength, "Incorrent length of CFG descriptor"); + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(config_desc_ref, config_desc, config_desc_ref->wTotalLength, "Configuration descriptors do not match"); + msc_obj.next_stage = TEST_STAGE_CHECK_STR_DESC; + skip_event_handling = true; //Need to execute TEST_STAGE_CHECK_STR_DESC + break; + } + case TEST_STAGE_CHECK_STR_DESC: { + usb_device_info_t dev_info; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_info(msc_obj.dev_hdl, &dev_info)); + //Check manufacturer string descriptors + const usb_str_desc_t *manu_str_desc_ref = (const usb_str_desc_t *)mock_msc_scsi_str_desc_manu; + const usb_str_desc_t *product_str_desc_ref = (const usb_str_desc_t *)mock_msc_scsi_str_desc_prod; + const usb_str_desc_t *ser_num_str_desc_ref = (const usb_str_desc_t *)mock_msc_scsi_str_desc_ser_num; + TEST_ASSERT_EQUAL(manu_str_desc_ref->bLength, dev_info.str_desc_manufacturer->bLength); + TEST_ASSERT_EQUAL(product_str_desc_ref->bLength, dev_info.str_desc_product->bLength); + TEST_ASSERT_EQUAL(ser_num_str_desc_ref->bLength, dev_info.str_desc_serial_num->bLength); + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(manu_str_desc_ref, dev_info.str_desc_manufacturer, manu_str_desc_ref->bLength, "Manufacturer string descriptors do not match."); + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(product_str_desc_ref, dev_info.str_desc_product, manu_str_desc_ref->bLength, "Product string descriptors do not match."); + //TEST_ASSERT_EQUAL_MEMORY_MESSAGE(ser_num_str_desc_ref, dev_info.str_desc_serial_num , manu_str_desc_ref->bLength, "Serial number string descriptors do not match."); + //Get dev info and compare + msc_obj.next_stage = TEST_STAGE_DEV_CLOSE; + skip_event_handling = true; //Need to execute TEST_STAGE_DEV_CLOSE + break; + } - case TEST_STAGE_DEV_CLOSE: { - ESP_LOGD(MSC_CLIENT_TAG, "Close"); - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(msc_obj.client_hdl, msc_obj.dev_hdl)); - enum_iter++; - if (enum_iter < TEST_ENUM_ITERATIONS) { - //Start the next test iteration by disconnecting the device, then going back to TEST_STAGE_WAIT_CONN stage - test_usb_set_phy_state(false, 0); - test_usb_set_phy_state(true, 0); - msc_obj.next_stage = TEST_STAGE_WAIT_CONN; - skip_event_handling = true; //Need to execute TEST_STAGE_WAIT_CONN - } else { - exit_loop = true; - } - break; + case TEST_STAGE_DEV_CLOSE: { + ESP_LOGD(MSC_CLIENT_TAG, "Close"); + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(msc_obj.client_hdl, msc_obj.dev_hdl)); + enum_iter++; + if (enum_iter < TEST_ENUM_ITERATIONS) { + //Start the next test iteration by disconnecting the device, then going back to TEST_STAGE_WAIT_CONN stage + test_usb_set_phy_state(false, 0); + test_usb_set_phy_state(true, 0); + msc_obj.next_stage = TEST_STAGE_WAIT_CONN; + skip_event_handling = true; //Need to execute TEST_STAGE_WAIT_CONN + } else { + exit_loop = true; } - default: - abort(); - break; + break; + } + default: + abort(); + break; } } //Free transfers and deregister the client diff --git a/components/usb/test_apps/usb_host/main/msc_client_async_seq.c b/components/usb/test_apps/usb_host/main/msc_client_async_seq.c index 3375adf4c00..6eff7d3d3d3 100644 --- a/components/usb/test_apps/usb_host/main/msc_client_async_seq.c +++ b/components/usb/test_apps/usb_host/main/msc_client_async_seq.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -59,43 +59,43 @@ static void msc_transfer_cb(usb_transfer_t *transfer) { msc_client_obj_t *msc_obj = (msc_client_obj_t *)transfer->context; switch (msc_obj->cur_stage) { - case TEST_STAGE_MSC_RESET: { - //Check MSC SCSI interface reset - TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); - TEST_ASSERT_EQUAL(transfer->num_bytes, transfer->actual_num_bytes); + case TEST_STAGE_MSC_RESET: { + //Check MSC SCSI interface reset + TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); + TEST_ASSERT_EQUAL(transfer->num_bytes, transfer->actual_num_bytes); + msc_obj->next_stage = TEST_STAGE_MSC_CBW; + break; + } + case TEST_STAGE_MSC_CBW: { + //Check MSC SCSI CBW transfer + TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); + TEST_ASSERT_EQUAL(sizeof(mock_msc_bulk_cbw_t), transfer->actual_num_bytes); + msc_obj->next_stage = TEST_STAGE_MSC_DATA; + break; + } + case TEST_STAGE_MSC_DATA: { + //Check MSC SCSI data IN transfer + TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); + TEST_ASSERT_EQUAL(MOCK_MSC_SCSI_SECTOR_SIZE * msc_obj->test_param.num_sectors_per_xfer, transfer->actual_num_bytes); + msc_obj->next_stage = TEST_STAGE_MSC_CSW; + break; + } + case TEST_STAGE_MSC_CSW: { + //Check MSC SCSI CSW transfer + TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); + TEST_ASSERT_TRUE(mock_msc_scsi_check_csw((mock_msc_bulk_csw_t *)transfer->data_buffer, msc_obj->test_param.msc_scsi_xfer_tag)); + msc_obj->num_sectors_read += msc_obj->test_param.num_sectors_per_xfer; + if (msc_obj->num_sectors_read < msc_obj->test_param.num_sectors_to_read) { msc_obj->next_stage = TEST_STAGE_MSC_CBW; - break; - } - case TEST_STAGE_MSC_CBW: { - //Check MSC SCSI CBW transfer - TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); - TEST_ASSERT_EQUAL(sizeof(mock_msc_bulk_cbw_t), transfer->actual_num_bytes); - msc_obj->next_stage = TEST_STAGE_MSC_DATA; - break; - } - case TEST_STAGE_MSC_DATA: { - //Check MSC SCSI data IN transfer - TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); - TEST_ASSERT_EQUAL(MOCK_MSC_SCSI_SECTOR_SIZE * msc_obj->test_param.num_sectors_per_xfer, transfer->actual_num_bytes); - msc_obj->next_stage = TEST_STAGE_MSC_CSW; - break; - } - case TEST_STAGE_MSC_CSW: { - //Check MSC SCSI CSW transfer - TEST_ASSERT_EQUAL_MESSAGE(USB_TRANSFER_STATUS_COMPLETED, transfer->status, "Transfer NOT completed"); - TEST_ASSERT_TRUE(mock_msc_scsi_check_csw((mock_msc_bulk_csw_t *)transfer->data_buffer, msc_obj->test_param.msc_scsi_xfer_tag)); - msc_obj->num_sectors_read += msc_obj->test_param.num_sectors_per_xfer; - if (msc_obj->num_sectors_read < msc_obj->test_param.num_sectors_to_read) { - msc_obj->next_stage = TEST_STAGE_MSC_CBW; - } else { - msc_obj->next_stage = TEST_STAGE_DEV_CLOSE; - } - break; - } - default: { - abort(); - break; + } else { + msc_obj->next_stage = TEST_STAGE_DEV_CLOSE; } + break; + } + default: { + abort(); + break; + } } } @@ -103,14 +103,14 @@ static void msc_client_event_cb(const usb_host_client_event_msg_t *event_msg, vo { msc_client_obj_t *msc_obj = (msc_client_obj_t *)arg; switch (event_msg->event) { - case USB_HOST_CLIENT_EVENT_NEW_DEV: - TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, msc_obj->cur_stage); - msc_obj->next_stage = TEST_STAGE_DEV_OPEN; - msc_obj->dev_addr_to_open = event_msg->new_dev.address; - break; - default: - abort(); //Should never occur in this test - break; + case USB_HOST_CLIENT_EVENT_NEW_DEV: + TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, msc_obj->cur_stage); + msc_obj->next_stage = TEST_STAGE_DEV_OPEN; + msc_obj->dev_addr_to_open = event_msg->new_dev.address; + break; + default: + abort(); //Should never occur in this test + break; } } @@ -132,7 +132,7 @@ void msc_client_async_seq_task(void *arg) .max_num_event_msg = MSC_ASYNC_CLIENT_MAX_EVENT_MSGS, .async = { .client_event_callback = msc_client_event_cb, - .callback_arg = (void *)&msc_obj, + .callback_arg = (void *) &msc_obj, }, }; TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_register(&client_config, &msc_obj.client_hdl)); @@ -166,77 +166,77 @@ void msc_client_async_seq_task(void *arg) msc_obj.cur_stage = msc_obj.next_stage; switch (msc_obj.cur_stage) { - case TEST_STAGE_DEV_OPEN: { - ESP_LOGD(MSC_CLIENT_TAG, "Open"); - //Open the device - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_open(msc_obj.client_hdl, msc_obj.dev_addr_to_open, &msc_obj.dev_hdl)); - //Target our transfers to the device - xfer_out->device_handle = msc_obj.dev_hdl; - xfer_in->device_handle = msc_obj.dev_hdl; - //Check the VID/PID of the opened device - const usb_device_desc_t *device_desc; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(msc_obj.dev_hdl, &device_desc)); - TEST_ASSERT_EQUAL(msc_obj.test_param.idVendor, device_desc->idVendor); - TEST_ASSERT_EQUAL(msc_obj.test_param.idProduct, device_desc->idProduct); - //Claim the MSC interface - TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_claim(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER, MOCK_MSC_SCSI_INTF_ALT_SETTING)); - msc_obj.next_stage = TEST_STAGE_MSC_RESET; - skip_event_handling = true; //Need to execute TEST_STAGE_MSC_RESET - break; - } - case TEST_STAGE_MSC_RESET: { - ESP_LOGD(MSC_CLIENT_TAG, "MSC Reset"); - //Send an MSC SCSI interface reset - MOCK_MSC_SCSI_REQ_INIT_RESET((usb_setup_packet_t *)xfer_out->data_buffer, MOCK_MSC_SCSI_INTF_NUMBER); - xfer_out->num_bytes = sizeof(usb_setup_packet_t); - xfer_out->bEndpointAddress = 0; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit_control(msc_obj.client_hdl, xfer_out)); - //Test that an inflight control transfer cannot be resubmitted - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit_control(msc_obj.client_hdl, xfer_out)); - //Next stage set from transfer callback - break; - } - case TEST_STAGE_MSC_CBW: { - ESP_LOGD(MSC_CLIENT_TAG, "CBW"); - mock_msc_scsi_init_cbw((mock_msc_bulk_cbw_t *)xfer_out->data_buffer, true, msc_obj.next_stage, msc_obj.test_param.num_sectors_per_xfer, msc_obj.test_param.msc_scsi_xfer_tag); - xfer_out->num_bytes = sizeof(mock_msc_bulk_cbw_t); - xfer_out->bEndpointAddress = MOCK_MSC_SCSI_BULK_OUT_EP_ADDR; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_out)); - //Test that an inflight transfer cannot be resubmitted - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit(xfer_out)); - //Next stage set from transfer callback - break; - } - case TEST_STAGE_MSC_DATA: { - ESP_LOGD(MSC_CLIENT_TAG, "Data"); - xfer_in->num_bytes = usb_round_up_to_mps(MOCK_MSC_SCSI_SECTOR_SIZE * msc_obj.test_param.num_sectors_per_xfer, MOCK_MSC_SCSI_BULK_EP_MPS); - xfer_in->bEndpointAddress = MOCK_MSC_SCSI_BULK_IN_EP_ADDR; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_in)); - //Test that an inflight transfer cannot be resubmitted - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit(xfer_in)); - //Next stage set from transfer callback - break; - } - case TEST_STAGE_MSC_CSW: { - ESP_LOGD(MSC_CLIENT_TAG, "CSW"); - xfer_in->num_bytes = usb_round_up_to_mps(sizeof(mock_msc_bulk_csw_t), MOCK_MSC_SCSI_BULK_EP_MPS); - xfer_in->bEndpointAddress = MOCK_MSC_SCSI_BULK_IN_EP_ADDR; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_in)); - //Test that an inflight transfer cannot be resubmitted - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit(xfer_in)); - //Next stage set from transfer callback - break; - } - case TEST_STAGE_DEV_CLOSE: { - ESP_LOGD(MSC_CLIENT_TAG, "Close"); - TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_release(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER)); - TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(msc_obj.client_hdl, msc_obj.dev_hdl)); - exit_loop = true; - break; - } - default: - abort(); - break; + case TEST_STAGE_DEV_OPEN: { + ESP_LOGD(MSC_CLIENT_TAG, "Open"); + //Open the device + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_open(msc_obj.client_hdl, msc_obj.dev_addr_to_open, &msc_obj.dev_hdl)); + //Target our transfers to the device + xfer_out->device_handle = msc_obj.dev_hdl; + xfer_in->device_handle = msc_obj.dev_hdl; + //Check the VID/PID of the opened device + const usb_device_desc_t *device_desc; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(msc_obj.dev_hdl, &device_desc)); + TEST_ASSERT_EQUAL(msc_obj.test_param.idVendor, device_desc->idVendor); + TEST_ASSERT_EQUAL(msc_obj.test_param.idProduct, device_desc->idProduct); + //Claim the MSC interface + TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_claim(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER, MOCK_MSC_SCSI_INTF_ALT_SETTING)); + msc_obj.next_stage = TEST_STAGE_MSC_RESET; + skip_event_handling = true; //Need to execute TEST_STAGE_MSC_RESET + break; + } + case TEST_STAGE_MSC_RESET: { + ESP_LOGD(MSC_CLIENT_TAG, "MSC Reset"); + //Send an MSC SCSI interface reset + MOCK_MSC_SCSI_REQ_INIT_RESET((usb_setup_packet_t *)xfer_out->data_buffer, MOCK_MSC_SCSI_INTF_NUMBER); + xfer_out->num_bytes = sizeof(usb_setup_packet_t); + xfer_out->bEndpointAddress = 0; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit_control(msc_obj.client_hdl, xfer_out)); + //Test that an inflight control transfer cannot be resubmitted + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit_control(msc_obj.client_hdl, xfer_out)); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_MSC_CBW: { + ESP_LOGD(MSC_CLIENT_TAG, "CBW"); + mock_msc_scsi_init_cbw((mock_msc_bulk_cbw_t *)xfer_out->data_buffer, true, msc_obj.next_stage, msc_obj.test_param.num_sectors_per_xfer, msc_obj.test_param.msc_scsi_xfer_tag); + xfer_out->num_bytes = sizeof(mock_msc_bulk_cbw_t); + xfer_out->bEndpointAddress = MOCK_MSC_SCSI_BULK_OUT_EP_ADDR; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_out)); + //Test that an inflight transfer cannot be resubmitted + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit(xfer_out)); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_MSC_DATA: { + ESP_LOGD(MSC_CLIENT_TAG, "Data"); + xfer_in->num_bytes = usb_round_up_to_mps(MOCK_MSC_SCSI_SECTOR_SIZE * msc_obj.test_param.num_sectors_per_xfer, MOCK_MSC_SCSI_BULK_EP_MPS); + xfer_in->bEndpointAddress = MOCK_MSC_SCSI_BULK_IN_EP_ADDR; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_in)); + //Test that an inflight transfer cannot be resubmitted + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit(xfer_in)); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_MSC_CSW: { + ESP_LOGD(MSC_CLIENT_TAG, "CSW"); + xfer_in->num_bytes = usb_round_up_to_mps(sizeof(mock_msc_bulk_csw_t), MOCK_MSC_SCSI_BULK_EP_MPS); + xfer_in->bEndpointAddress = MOCK_MSC_SCSI_BULK_IN_EP_ADDR; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_transfer_submit(xfer_in)); + //Test that an inflight transfer cannot be resubmitted + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_transfer_submit(xfer_in)); + //Next stage set from transfer callback + break; + } + case TEST_STAGE_DEV_CLOSE: { + ESP_LOGD(MSC_CLIENT_TAG, "Close"); + TEST_ASSERT_EQUAL(ESP_OK, usb_host_interface_release(msc_obj.client_hdl, msc_obj.dev_hdl, MOCK_MSC_SCSI_INTF_NUMBER)); + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(msc_obj.client_hdl, msc_obj.dev_hdl)); + exit_loop = true; + break; + } + default: + abort(); + break; } } //Free transfers and deregister the client diff --git a/components/usb/test_apps/usb_host/main/test_usb_host_async.c b/components/usb/test_apps/usb_host/main/test_usb_host_async.c index 5fa653b886e..6e5b9cef0ef 100644 --- a/components/usb/test_apps/usb_host/main/test_usb_host_async.c +++ b/components/usb/test_apps/usb_host/main/test_usb_host_async.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -169,20 +169,20 @@ static void test_async_client_cb(const usb_host_client_event_msg_t *event_msg, v client_test_stage_t *stage = (client_test_stage_t *)arg; switch (event_msg->event) { - case USB_HOST_CLIENT_EVENT_NEW_DEV: - if (dev_addr == 0) { - dev_addr = event_msg->new_dev.address; - } else { - TEST_ASSERT_EQUAL(dev_addr, event_msg->new_dev.address); - } - *stage = CLIENT_TEST_STAGE_CONN; - break; - case USB_HOST_CLIENT_EVENT_DEV_GONE: - *stage = CLIENT_TEST_STAGE_DCONN; - break; - default: - abort(); - break; + case USB_HOST_CLIENT_EVENT_NEW_DEV: + if (dev_addr == 0) { + dev_addr = event_msg->new_dev.address; + } else { + TEST_ASSERT_EQUAL(dev_addr, event_msg->new_dev.address); + } + *stage = CLIENT_TEST_STAGE_CONN; + break; + case USB_HOST_CLIENT_EVENT_DEV_GONE: + *stage = CLIENT_TEST_STAGE_DCONN; + break; + default: + abort(); + break; } } @@ -197,7 +197,7 @@ TEST_CASE("Test USB Host async API", "[usb_host][full_speed][low_speed]") .max_num_event_msg = 5, .async = { .client_event_callback = test_async_client_cb, - .callback_arg = (void *)&client0_stage, + .callback_arg = (void *) &client0_stage, }, }; usb_host_client_handle_t client0_hdl; diff --git a/components/usb/usb_helpers.c b/components/usb/usb_helpers.c index 0c06d57f8aa..08c50e3b87d 100644 --- a/components/usb/usb_helpers.c +++ b/components/usb/usb_helpers.c @@ -198,7 +198,7 @@ static void print_ep_desc(const usb_ep_desc_t *ep_desc) USB_EP_DESC_GET_EP_NUM(ep_desc), USB_EP_DESC_GET_EP_DIR(ep_desc) ? "IN" : "OUT"); printf("\t\tbmAttributes 0x%x\t%s\n", ep_desc->bmAttributes, ep_type_str); - printf("\t\twMaxPacketSize %d\n", ep_desc->wMaxPacketSize); + printf("\t\twMaxPacketSize %d\n", USB_EP_DESC_GET_MPS(ep_desc)); printf("\t\tbInterval %d\n", ep_desc->bInterval); } diff --git a/components/usb/usb_host.c b/components/usb/usb_host.c index e0182d56609..cfea392a432 100644 --- a/components/usb/usb_host.c +++ b/components/usb/usb_host.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -94,11 +94,9 @@ struct client_s { TAILQ_HEAD(tailhead_done_ctrl_xfers, urb_s) done_ctrl_xfer_tailq; union { struct { - uint32_t events_pending: 1; uint32_t handling_events: 1; - uint32_t blocked: 1; uint32_t taking_mux: 1; - uint32_t reserved4: 4; + uint32_t reserved6: 6; uint32_t num_intf_claimed: 8; uint32_t reserved16: 16; }; @@ -128,10 +126,8 @@ typedef struct { uint32_t lib_event_flags; union { struct { - uint32_t process_pending: 1; uint32_t handling_events: 1; - uint32_t blocked: 1; - uint32_t reserved5: 5; + uint32_t reserved7: 7; uint32_t num_clients: 8; uint32_t reserved16: 16; }; @@ -176,24 +172,16 @@ static inline bool _check_client_opened_device(client_t *client_obj, uint8_t dev static bool _unblock_client(client_t *client_obj, bool in_isr) { - bool send_sem; - if (!client_obj->dynamic.flags.events_pending && !client_obj->dynamic.flags.handling_events) { - client_obj->dynamic.flags.events_pending = 1; - send_sem = true; - } else { - send_sem = false; - } + bool yield; HOST_EXIT_CRITICAL_SAFE(); - bool yield = false; - if (send_sem) { - if (in_isr) { - BaseType_t xTaskWoken = pdFALSE; - xSemaphoreGiveFromISR(client_obj->constant.event_sem, &xTaskWoken); - yield = (xTaskWoken == pdTRUE); - } else { - xSemaphoreGive(client_obj->constant.event_sem); - } + if (in_isr) { + BaseType_t xTaskWoken = pdFALSE; + xSemaphoreGiveFromISR(client_obj->constant.event_sem, &xTaskWoken); + yield = (xTaskWoken == pdTRUE); + } else { + xSemaphoreGive(client_obj->constant.event_sem); + yield = false; } HOST_ENTER_CRITICAL_SAFE(); @@ -202,24 +190,16 @@ static bool _unblock_client(client_t *client_obj, bool in_isr) static bool _unblock_lib(bool in_isr) { - bool send_sem; - if (!p_host_lib_obj->dynamic.flags.process_pending && !p_host_lib_obj->dynamic.flags.handling_events) { - p_host_lib_obj->dynamic.flags.process_pending = 1; - send_sem = true; - } else { - send_sem = false; - } + bool yield; HOST_EXIT_CRITICAL_SAFE(); - bool yield = false; - if (send_sem) { - if (in_isr) { - BaseType_t xTaskWoken = pdFALSE; - xSemaphoreGiveFromISR(p_host_lib_obj->constant.event_sem, &xTaskWoken); - yield = (xTaskWoken == pdTRUE); - } else { - xSemaphoreGive(p_host_lib_obj->constant.event_sem); - } + if (in_isr) { + BaseType_t xTaskWoken = pdFALSE; + xSemaphoreGiveFromISR(p_host_lib_obj->constant.event_sem, &xTaskWoken); + yield = (xTaskWoken == pdTRUE); + } else { + xSemaphoreGive(p_host_lib_obj->constant.event_sem); + yield = false; } HOST_ENTER_CRITICAL_SAFE(); @@ -515,45 +495,49 @@ esp_err_t usb_host_uninstall(void) esp_err_t usb_host_lib_handle_events(TickType_t timeout_ticks, uint32_t *event_flags_ret) { - esp_err_t ret; - uint32_t event_flags = 0; + // Check arguments and state + HOST_CHECK(p_host_lib_obj != NULL, ESP_ERR_INVALID_STATE); + + esp_err_t ret = (timeout_ticks == 0) ? ESP_OK : ESP_ERR_TIMEOUT; // We don't want to return ESP_ERR_TIMEOUT if we aren't blocking + uint32_t event_flags; HOST_ENTER_CRITICAL(); - if (!p_host_lib_obj->dynamic.flags.process_pending) { - // There is currently processing that needs to be done. Wait for some processing - HOST_EXIT_CRITICAL(); - BaseType_t sem_ret = xSemaphoreTake(p_host_lib_obj->constant.event_sem, timeout_ticks); - if (sem_ret == pdFALSE) { - ret = ESP_ERR_TIMEOUT; - goto exit; + // Set handling_events flag. This prevents the host library from being uninstalled + p_host_lib_obj->dynamic.flags.handling_events = 1; + HOST_EXIT_CRITICAL(); + + while (1) { + // Loop until there are no more events + if (xSemaphoreTake(p_host_lib_obj->constant.event_sem, timeout_ticks) == pdFALSE) { + // Timed out waiting for semaphore or currently no events + break; } + + // Read and clear process pending flags HOST_ENTER_CRITICAL(); - } - // Read and clear process pending flags - uint32_t process_pending_flags = p_host_lib_obj->dynamic.process_pending_flags; - p_host_lib_obj->dynamic.process_pending_flags = 0; - p_host_lib_obj->dynamic.flags.handling_events = 1; - while (process_pending_flags) { + uint32_t process_pending_flags = p_host_lib_obj->dynamic.process_pending_flags; + p_host_lib_obj->dynamic.process_pending_flags = 0; HOST_EXIT_CRITICAL(); + if (process_pending_flags & PROCESS_REQUEST_PENDING_FLAG_USBH) { ESP_ERROR_CHECK(usbh_process()); } if (process_pending_flags & PROCESS_REQUEST_PENDING_FLAG_HUB) { ESP_ERROR_CHECK(hub_process()); } - HOST_ENTER_CRITICAL(); - // Read and clear process pending flags again, and loop back if there is more to process - process_pending_flags = p_host_lib_obj->dynamic.process_pending_flags; - p_host_lib_obj->dynamic.process_pending_flags = 0; + + ret = ESP_OK; + // Set timeout_ticks to 0 so that we can check for events again without blocking + timeout_ticks = 0; } - p_host_lib_obj->dynamic.flags.process_pending = 0; + + HOST_ENTER_CRITICAL(); p_host_lib_obj->dynamic.flags.handling_events = 0; + // Read and clear any event flags event_flags = p_host_lib_obj->dynamic.lib_event_flags; p_host_lib_obj->dynamic.lib_event_flags = 0; HOST_EXIT_CRITICAL(); - ret = ESP_OK; -exit: if (event_flags_ret != NULL) { *event_flags_ret = event_flags; } @@ -709,7 +693,6 @@ esp_err_t usb_host_client_deregister(usb_host_client_handle_t client_hdl) !TAILQ_EMPTY(&client_obj->dynamic.idle_ep_tailq) || !TAILQ_EMPTY(&client_obj->dynamic.done_ctrl_xfer_tailq) || client_obj->dynamic.flags.handling_events || - client_obj->dynamic.flags.blocked || client_obj->dynamic.flags.taking_mux || client_obj->dynamic.flags.num_intf_claimed != 0 || client_obj->dynamic.num_done_ctrl_xfer != 0 || @@ -746,28 +729,26 @@ esp_err_t usb_host_client_deregister(usb_host_client_handle_t client_hdl) esp_err_t usb_host_client_handle_events(usb_host_client_handle_t client_hdl, TickType_t timeout_ticks) { + // Check arguments and state HOST_CHECK(client_hdl != NULL, ESP_ERR_INVALID_ARG); - esp_err_t ret; + HOST_CHECK(p_host_lib_obj != NULL, ESP_ERR_INVALID_STATE); + + esp_err_t ret = (timeout_ticks == 0) ? ESP_OK : ESP_ERR_TIMEOUT; // We don't want to return ESP_ERR_TIMEOUT if we aren't blocking client_t *client_obj = (client_t *)client_hdl; HOST_ENTER_CRITICAL(); - if (!client_obj->dynamic.flags.events_pending) { - // There are currently no events, wait for one to occur - client_obj->dynamic.flags.blocked = 1; - HOST_EXIT_CRITICAL(); - BaseType_t sem_ret = xSemaphoreTake(client_obj->constant.event_sem, timeout_ticks); - HOST_ENTER_CRITICAL(); - client_obj->dynamic.flags.blocked = 0; - if (sem_ret == pdFALSE) { - HOST_EXIT_CRITICAL(); - // Timed out waiting for semaphore - ret = ESP_ERR_TIMEOUT; - goto exit; - } - } - // Mark that we're processing events + // Set handling_events flag. This prevents the client from being deregistered client_obj->dynamic.flags.handling_events = 1; - while (client_obj->dynamic.flags.handling_events) { + HOST_EXIT_CRITICAL(); + + while (1) { + // Loop until there are no more events + if (xSemaphoreTake(client_obj->constant.event_sem, timeout_ticks) == pdFALSE) { + // Timed out waiting for semaphore or currently no events + break; + } + + HOST_ENTER_CRITICAL(); // Handle pending endpoints if (!TAILQ_EMPTY(&client_obj->dynamic.pending_ep_tailq)) { _handle_pending_ep(client_obj); @@ -784,29 +765,26 @@ esp_err_t usb_host_client_handle_events(usb_host_client_handle_t client_hdl, Tic urb->transfer.callback(&urb->transfer); HOST_ENTER_CRITICAL(); } + HOST_EXIT_CRITICAL(); + // Handle event messages while (uxQueueMessagesWaiting(client_obj->constant.event_msg_queue) > 0) { - HOST_EXIT_CRITICAL(); // Dequeue the event message and call the client event callback usb_host_client_event_msg_t event_msg; BaseType_t queue_ret = xQueueReceive(client_obj->constant.event_msg_queue, &event_msg, 0); assert(queue_ret == pdTRUE); client_obj->constant.event_callback(&event_msg, client_obj->constant.callback_arg); - HOST_ENTER_CRITICAL(); - } - // Check each event again to see any new events occurred - if (TAILQ_EMPTY(&client_obj->dynamic.pending_ep_tailq) && - client_obj->dynamic.num_done_ctrl_xfer == 0 && - uxQueueMessagesWaiting(client_obj->constant.event_msg_queue) == 0) { - // All pending endpoints and event messages handled - client_obj->dynamic.flags.events_pending = 0; - client_obj->dynamic.flags.handling_events = 0; } + + ret = ESP_OK; + // Set timeout_ticks to 0 so that we can check for events again without blocking + timeout_ticks = 0; } + + HOST_ENTER_CRITICAL(); + client_obj->dynamic.flags.handling_events = 0; HOST_EXIT_CRITICAL(); - ret = ESP_OK; -exit: return ret; } @@ -1245,7 +1223,7 @@ esp_err_t usb_host_endpoint_clear(usb_device_handle_t dev_hdl, uint8_t bEndpoint esp_err_t usb_host_transfer_alloc(size_t data_buffer_size, int num_isoc_packets, usb_transfer_t **transfer) { - urb_t *urb = urb_alloc(data_buffer_size, 0, num_isoc_packets); + urb_t *urb = urb_alloc(data_buffer_size, num_isoc_packets); if (urb == NULL) { return ESP_ERR_NO_MEM; } diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c index 2ba62112bf6..457769eb175 100644 --- a/components/usb/usb_phy.c +++ b/components/usb/usb_phy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,8 +17,15 @@ #include "esp_rom_gpio.h" #include "driver/gpio.h" #include "hal/gpio_ll.h" +#include "soc/soc_caps.h" #include "soc/usb_pins.h" +#if !SOC_RCC_IS_INDEPENDENT +#define USB_WRAP_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define USB_WRAP_RCC_ATOMIC() +#endif + static const char *USBPHY_TAG = "usb_phy"; #define USBPHY_NOT_INIT_ERR_STR "USB_PHY is not initialized" @@ -140,13 +147,7 @@ esp_err_t usb_phy_otg_dev_set_speed(usb_phy_handle_t handle, usb_phy_speed_t spe USBPHY_TAG, "set speed not supported"); handle->otg_speed = speed; - usb_priv_speed_t hal_speed = 0; - if (speed == USB_PHY_SPEED_LOW) { - hal_speed = USB_PRIV_SPEED_LOW; - } else if (speed == USB_PHY_SPEED_FULL) { - hal_speed = USB_PRIV_SPEED_FULL; - } - usb_phy_hal_int_load_conf_dev(&(handle->hal_context), hal_speed); + usb_phy_hal_int_load_conf_dev(&(handle->hal_context), speed); return ESP_OK; } @@ -219,9 +220,12 @@ static esp_err_t usb_phy_install(void) portEXIT_CRITICAL(&phy_spinlock); goto cleanup; } + // Enable USB peripheral and reset the register portEXIT_CRITICAL(&phy_spinlock); - periph_module_enable(usb_otg_periph_signal.module); - periph_module_reset(usb_otg_periph_signal.module); + USB_WRAP_RCC_ATOMIC() { + usb_phy_ll_usb_wrap_enable_bus_clock(true); + usb_phy_ll_usb_wrap_reset_register(); + } return ESP_OK; cleanup: @@ -311,8 +315,10 @@ static void phy_uninstall(void) if (p_phy_ctrl_obj->ref_count == 0) { p_phy_ctrl_obj_free = p_phy_ctrl_obj; p_phy_ctrl_obj = NULL; - // Disable USB peripheral - periph_module_disable(usb_otg_periph_signal.module); + USB_WRAP_RCC_ATOMIC() { + // Disable USB peripheral without reset the module + usb_phy_ll_usb_wrap_enable_bus_clock(false); + } } portEXIT_CRITICAL(&phy_spinlock); free(p_phy_ctrl_obj_free); @@ -327,8 +333,9 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle) if (handle->target == USB_PHY_TARGET_EXT) { p_phy_ctrl_obj->external_phy = NULL; } else { - // Clear pullup and pulldown loads on D+ / D- + // Clear pullup and pulldown loads on D+ / D-, and disable the pads usb_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false); + usb_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false); p_phy_ctrl_obj->internal_phy = NULL; } portEXIT_CRITICAL(&phy_spinlock); diff --git a/components/usb/usb_private.c b/components/usb/usb_private.c index 95085976413..5d082c19d04 100644 --- a/components/usb/usb_private.c +++ b/components/usb/usb_private.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,17 +8,16 @@ #include "usb_private.h" #include "usb/usb_types_ch9.h" -urb_t *urb_alloc(size_t data_buffer_size, size_t header_size, int num_isoc_packets) +urb_t *urb_alloc(size_t data_buffer_size, int num_isoc_packets) { urb_t *urb = heap_caps_calloc(1, sizeof(urb_t) + (sizeof(usb_isoc_packet_desc_t) * num_isoc_packets), MALLOC_CAP_DEFAULT); - uint8_t *data_buffer = heap_caps_malloc(data_buffer_size + header_size, MALLOC_CAP_DMA); + uint8_t *data_buffer = heap_caps_malloc(data_buffer_size, MALLOC_CAP_DMA); if (urb == NULL || data_buffer == NULL) { goto err; } - urb->usb_host_header_size = header_size; // Indicate that this URB's data_buffer has a header in front of it. - // Case as dummy transfer to write to initialize const fields + // Cast as dummy transfer so that we can assign to const fields usb_transfer_dummy_t *dummy_transfer = (usb_transfer_dummy_t *)&urb->transfer; - dummy_transfer->data_buffer = (uint8_t *)(data_buffer + header_size); + dummy_transfer->data_buffer = data_buffer; dummy_transfer->data_buffer_size = data_buffer_size; dummy_transfer->num_isoc_packets = num_isoc_packets; return urb; @@ -33,6 +32,6 @@ void urb_free(urb_t *urb) if (urb == NULL) { return; } - heap_caps_free((uint8_t *)(urb->transfer.data_buffer - urb->usb_host_header_size)); + heap_caps_free(urb->transfer.data_buffer); heap_caps_free(urb); } diff --git a/components/usb/usbh.c b/components/usb/usbh.c index a23f57467c2..dbc23e6e334 100644 --- a/components/usb/usbh.c +++ b/components/usb/usbh.c @@ -1081,11 +1081,11 @@ esp_err_t usbh_ep_enqueue_urb(usbh_ep_handle_t ep_hdl, urb_t *urb) endpoint_t *ep_obj = (endpoint_t *)ep_hdl; - USBH_CHECK( transfer_check_usb_compliance(&(urb->transfer), - USB_EP_DESC_GET_XFERTYPE(ep_obj->constant.ep_desc), - USB_EP_DESC_GET_MPS(ep_obj->constant.ep_desc), - USB_EP_DESC_GET_EP_DIR(ep_obj->constant.ep_desc)), - ESP_ERR_INVALID_ARG); + USBH_CHECK(transfer_check_usb_compliance(&(urb->transfer), + USB_EP_DESC_GET_XFERTYPE(ep_obj->constant.ep_desc), + USB_EP_DESC_GET_MPS(ep_obj->constant.ep_desc), + USB_EP_DESC_GET_EP_DIR(ep_obj->constant.ep_desc)), + ESP_ERR_INVALID_ARG); // Check that the EP's underlying pipe is in the active state before submitting the URB if (hcd_pipe_get_state(ep_obj->constant.pipe_hdl) != HCD_PIPE_STATE_ACTIVE) { return ESP_ERR_INVALID_STATE; diff --git a/components/vfs/CMakeLists.txt b/components/vfs/CMakeLists.txt index d056cd8b0da..1a090fa1e90 100644 --- a/components/vfs/CMakeLists.txt +++ b/components/vfs/CMakeLists.txt @@ -6,12 +6,15 @@ endif() list(APPEND sources "vfs.c" "vfs_eventfd.c" - "vfs_uart.c" "vfs_semihost.c" - "vfs_console.c") + "vfs_console.c" + ) list(APPEND pr driver - esp_timer) + esp_timer + # for backwards compatibility (TODO: IDF-8799) + esp_driver_uart + ) idf_component_register(SRCS ${sources} LDFRAGMENTS "linker.lf" @@ -30,3 +33,8 @@ endif() # Some newlib syscalls are implemented in vfs.c, make sure these are always # seen by the linker target_link_libraries(${COMPONENT_LIB} INTERFACE "-u vfs_include_syscalls_impl") + +if(CONFIG_VFS_SUPPORT_IO) + # Make sure esp_vfs_console_register gets called at startup stage + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_vfs_include_console_register") +endif() diff --git a/components/vfs/include/esp_private/esp_vfs_console.h b/components/vfs/include/esp_private/esp_vfs_console.h new file mode 100644 index 00000000000..4196c451f38 --- /dev/null +++ b/components/vfs/include/esp_private/esp_vfs_console.h @@ -0,0 +1,41 @@ + +/* + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" +#include "esp_vfs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_VFS_SUPPORT_IO +/** + * @brief Set the pointer of primary dev vfs. + * + * This function is called in each vfs dev driver as a system initialization function registered via ESP_SYSTEM_INIT_FN + * + * @param vfs pointer to structure esp_vfs_t + */ +void esp_vfs_set_primary_dev_vfs_def_struct(const esp_vfs_t *vfs); + +#if CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG +/** + * @brief Set the pointer of secondary dev vfs. + * + * This function is called in each vfs dev driver as a system initialization function registered via ESP_SYSTEM_INIT_FN + * + * @param vfs pointer to structure esp_vfs_t + */ +void esp_vfs_set_secondary_dev_vfs_def_struct(const esp_vfs_t *vfs); +#endif //CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG +#endif // CONFIG_VFS_SUPPORT_IO + +#ifdef __cplusplus +} +#endif diff --git a/components/vfs/include/esp_vfs.h b/components/vfs/include/esp_vfs.h index ac0029e3f1d..f3358d50761 100644 --- a/components/vfs/include/esp_vfs.h +++ b/components/vfs/include/esp_vfs.h @@ -336,7 +336,8 @@ esp_err_t esp_vfs_unregister_with_id(esp_vfs_id_t vfs_id); /** * Special function for registering another file descriptor for a VFS registered - * by esp_vfs_register_with_id. + * by esp_vfs_register_with_id. This function should only be used to register + * permanent file descriptors (socket fd) that are not removed after being closed. * * @param vfs_id VFS identificator returned by esp_vfs_register_with_id. * @param fd The registered file descriptor will be written to this address. diff --git a/components/vfs/include/esp_vfs_console.h b/components/vfs/include/esp_vfs_console.h index 3ac6e31adde..4b24a537227 100644 --- a/components/vfs/include/esp_vfs_console.h +++ b/components/vfs/include/esp_vfs_console.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,12 +8,12 @@ #include "esp_err.h" -#define ESP_VFS_DEV_CONSOLE "/dev/console" - #ifdef __cplusplus extern "C" { #endif +#define ESP_VFS_DEV_CONSOLE "/dev/console" + /** * @brief add uart/usb_serial_jtag/usb_otg_acmcdc virtual filesystem driver * diff --git a/components/vfs/include/esp_vfs_dev.h b/components/vfs/include/esp_vfs_dev.h index 6eed6afc871..a6513ca27f9 100644 --- a/components/vfs/include/esp_vfs_dev.h +++ b/components/vfs/include/esp_vfs_dev.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,12 +13,15 @@ extern "C" { #endif -/** - * @brief add /dev/uart virtual filesystem driver - * - * This function is called from startup code to enable serial output - */ -void esp_vfs_dev_uart_register(void); +void esp_vfs_dev_uart_register(void) __attribute__((deprecated("Please use uart_vfs_dev_register() instead"))); + +void esp_vfs_dev_uart_use_nonblocking(int uart_num) __attribute__((deprecated("Please use uart_vfs_dev_use_nonblocking() instead"))); + +void esp_vfs_dev_uart_use_driver(int uart_num) __attribute__((deprecated("Please use uart_vfs_dev_use_driver() instead"))); + +int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode) __attribute__((deprecated("Please use uart_vfs_dev_port_set_rx_line_endings() instead"))); + +int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode) __attribute__((deprecated("Please use uart_vfs_dev_port_set_tx_line_endings() instead"))); /** * @brief Set the line endings expected to be received on UART @@ -34,7 +37,7 @@ void esp_vfs_dev_uart_register(void); * * @param mode line endings expected on UART */ -void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) __attribute__((deprecated("Please use esp_vfs_dev_uart_port_set_rx_line_endings"))); +void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) __attribute__((deprecated("Please use uart_vfs_dev_port_set_rx_line_endings() instead"))); /** * @brief Set the line endings to sent to UART @@ -50,61 +53,7 @@ void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) __attribute__ * * @param mode line endings to send to UART */ -void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) __attribute__((deprecated("Please use esp_vfs_dev_uart_port_set_tx_line_endings"))); - -/** - * @brief Set the line endings expected to be received on specified UART - * - * This specifies the conversion between line endings received on UART and - * newlines ('\n', LF) passed into stdin: - * - * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF - * - ESP_LINE_ENDINGS_CR: convert CR to LF - * - ESP_LINE_ENDINGS_LF: no modification - * - * @note this function is not thread safe w.r.t. reading from UART - * - * @param uart_num the UART number - * @param mode line endings to send to UART - * @return 0 if successed, or -1 - * when an error (specified by errno) have occurred. - */ -int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode); - -/** - * @brief Set the line endings to sent to specified UART - * - * This specifies the conversion between newlines ('\n', LF) on stdout and line - * endings sent over UART: - * - * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF - * - ESP_LINE_ENDINGS_CR: convert LF to CR - * - ESP_LINE_ENDINGS_LF: no modification - * - * @note this function is not thread safe w.r.t. writing to UART - * - * @param uart_num the UART number - * @param mode line endings to send to UART - * @return 0 if successed, or -1 - * when an error (specified by errno) have occurred. - */ -int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode); - -/** - * @brief set VFS to use simple functions for reading and writing UART - * Read is non-blocking, write is busy waiting until TX FIFO has enough space. - * These functions are used by default. - * @param uart_num UART peripheral number - */ -void esp_vfs_dev_uart_use_nonblocking(int uart_num); - -/** - * @brief set VFS to use UART driver for reading and writing - * @note application must configure UART driver before calling these functions - * With these functions, read and write are blocking and interrupt-driven. - * @param uart_num UART peripheral number - */ -void esp_vfs_dev_uart_use_driver(int uart_num); +void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) __attribute__((deprecated("Please use uart_vfs_dev_port_set_tx_line_endings() instead"))); /** * @brief set VFS to use USB-SERIAL-JTAG driver for reading and writing diff --git a/components/vfs/linker.lf b/components/vfs/linker.lf index 9c8e69b5f79..90d1d43f205 100644 --- a/components/vfs/linker.lf +++ b/components/vfs/linker.lf @@ -3,4 +3,3 @@ archive: libvfs.a entries: if VFS_SELECT_IN_RAM = y: vfs:esp_vfs_select_triggered_isr (noflash) - vfs_uart:select_notif_callback_isr (noflash) diff --git a/components/vfs/private_include/esp_vfs_private.h b/components/vfs/private_include/esp_vfs_private.h index 7a3f9e1e657..8122717314d 100644 --- a/components/vfs/private_include/esp_vfs_private.h +++ b/components/vfs/private_include/esp_vfs_private.h @@ -1,9 +1,10 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "esp_vfs.h" #include "esp_vfs_common.h" @@ -11,6 +12,12 @@ extern "C" { #endif +#if CONFIG_VFS_SELECT_IN_RAM +#define VFS_MALLOC_FLAGS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) +#else +#define VFS_MALLOC_FLAGS MALLOC_CAP_DEFAULT +#endif + typedef struct vfs_entry_ { esp_vfs_t vfs; // contains pointers to VFS functions char path_prefix[ESP_VFS_PATH_MAX]; // path prefix mapped to this VFS @@ -19,17 +26,6 @@ typedef struct vfs_entry_ { int offset; // index of this structure in s_vfs array } vfs_entry_t; - -/** - * @brief get pointer of uart vfs. - * - * This function is called in vfs_console in order to get the vfs implementation - * of uart. - * - * @return pointer to structure esp_vfs_t - */ -const esp_vfs_t *esp_vfs_uart_get_vfs(void); - /** * @brief get pointer of cdcacm vfs. * diff --git a/components/vfs/test_apps/main/CMakeLists.txt b/components/vfs/test_apps/main/CMakeLists.txt index d0d0f826d29..f9a5e774c90 100644 --- a/components/vfs/test_apps/main/CMakeLists.txt +++ b/components/vfs/test_apps/main/CMakeLists.txt @@ -2,11 +2,12 @@ set(src "test_app_main.c" "test_vfs_access.c" "test_vfs_append.c" "test_vfs_eventfd.c" "test_vfs_fd.c" "test_vfs_lwip.c" "test_vfs_open.c" "test_vfs_paths.c" - "test_vfs_select.c" "test_vfs_uart.c" + "test_vfs_select.c" ) idf_component_register(SRCS ${src} PRIV_INCLUDE_DIRS . PRIV_REQUIRES test_utils vfs fatfs spiffs unity lwip wear_levelling cmock + esp_driver_gptimer esp_driver_uart WHOLE_ARCHIVE ) diff --git a/components/vfs/test_apps/main/test_vfs_select.c b/components/vfs/test_apps/main/test_vfs_select.c index 3e8c04596d1..80f7720cca1 100644 --- a/components/vfs/test_apps/main/test_vfs_select.c +++ b/components/vfs/test_apps/main/test_vfs_select.c @@ -10,10 +10,9 @@ #include #include "unity.h" #include "freertos/FreeRTOS.h" -#include "soc/uart_struct.h" #include "driver/uart.h" #include "esp_vfs.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "esp_vfs_fat.h" #include "lwip/sockets.h" #include "lwip/netdb.h" @@ -144,14 +143,14 @@ static void init(int *uart_fd, int *socket_fd) *uart_fd = open("/dev/uart/1", O_RDWR); TEST_ASSERT_NOT_EQUAL_MESSAGE(*uart_fd, -1, "Cannot open UART"); - esp_vfs_dev_uart_use_driver(1); + uart_vfs_dev_use_driver(1); *socket_fd = socket_init(); } static void deinit(int uart_fd, int socket_fd) { - esp_vfs_dev_uart_use_nonblocking(1); + uart_vfs_dev_use_nonblocking(1); close(uart_fd); uart_driver_delete(UART_NUM_1); diff --git a/components/vfs/vfs.c b/components/vfs/vfs.c index 9b2c7887c85..ef66a543234 100644 --- a/components/vfs/vfs.c +++ b/components/vfs/vfs.c @@ -87,7 +87,7 @@ esp_err_t esp_vfs_register_common(const char* base_path, size_t len, const esp_v return ESP_ERR_INVALID_ARG; } } - vfs_entry_t *entry = (vfs_entry_t*) malloc(sizeof(vfs_entry_t)); + vfs_entry_t *entry = (vfs_entry_t*) heap_caps_malloc(sizeof(vfs_entry_t), VFS_MALLOC_FLAGS); if (entry == NULL) { return ESP_ERR_NO_MEM; } @@ -970,7 +970,7 @@ int esp_vfs_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds // because that could block the registration of new driver. const size_t vfs_count = s_vfs_count; fds_triple_t *vfs_fds_triple; - if ((vfs_fds_triple = calloc(vfs_count, sizeof(fds_triple_t))) == NULL) { + if ((vfs_fds_triple = heap_caps_calloc(vfs_count, sizeof(fds_triple_t), VFS_MALLOC_FLAGS)) == NULL) { __errno_r(r) = ENOMEM; ESP_LOGD(TAG, "calloc is unsuccessful"); return -1; @@ -1047,7 +1047,7 @@ int esp_vfs_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds } } - void **driver_args = calloc(vfs_count, sizeof(void *)); + void **driver_args = heap_caps_calloc(vfs_count, sizeof(void *), VFS_MALLOC_FLAGS); if (driver_args == NULL) { free(vfs_fds_triple); @@ -1381,5 +1381,5 @@ void rewinddir(DIR* pdir) void vfs_include_syscalls_impl(void) { - // Linker hook function, exists to make the linker examine this fine + // Linker hook function, exists to make the linker examine this file } diff --git a/components/vfs/vfs_console.c b/components/vfs/vfs_console.c index 1360be33cc6..336feed706f 100644 --- a/components/vfs/vfs_console.c +++ b/components/vfs/vfs_console.c @@ -1,24 +1,26 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_vfs_console.h" +#include "esp_err.h" #include "esp_rom_sys.h" #include "esp_vfs_cdcacm.h" #include "esp_vfs_private.h" #include "esp_vfs_usb_serial_jtag.h" -#include "esp_vfs_dev.h" #include "esp_private/usb_console.h" +#include "esp_vfs_console.h" +#include "esp_private/esp_vfs_console.h" #include "sdkconfig.h" +#include "esp_private/startup_internal.h" #define STRINGIFY(s) STRINGIFY2(s) #define STRINGIFY2(s) #s /** * This file is to concentrate all the vfs(UART, USB_SERIAL_JTAG, CDCACM) console into one single file. - * Get the vfs information from their component (i.e. vfs_uart.c) through `esp_vfs_usb_xxx_get_console()`, + * Get the vfs information from their component (i.e. uart_vfs.c), * which can help us to output some string to two different ports(i.e both through uart and usb_serial_jtag). * Usually, we set a port as primary and another as secondary. For primary, it is used for all the features supported by each vfs implementation, * while the secondary is only used for output. @@ -43,9 +45,11 @@ const static char *primary_path = "/dev/cdcacm"; #if CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG const static char *secondary_path = "/dev/secondary"; static int secondary_vfs_index; +const static esp_vfs_t *secondary_vfs = NULL; #endif // Secondary part static int primary_vfs_index; +const static esp_vfs_t *primary_vfs = NULL; static vfs_console_context_t vfs_console= {0}; @@ -186,7 +190,7 @@ static const esp_vfs_t vfs = { #endif // CONFIG_VFS_SUPPORT_TERMIOS }; -esp_err_t esp_vfs_dev_console_register(void) +static esp_err_t esp_vfs_dev_console_register(void) { return esp_vfs_register(ESP_VFS_DEV_CONSOLE, &vfs, NULL); } @@ -196,27 +200,25 @@ esp_err_t esp_vfs_console_register(void) esp_err_t err = ESP_OK; // Primary register part. #ifdef CONFIG_ESP_CONSOLE_UART - const esp_vfs_t *uart_vfs = esp_vfs_uart_get_vfs(); - err = esp_vfs_register_common(primary_path, strlen(primary_path), uart_vfs, NULL, &primary_vfs_index); + assert(primary_vfs); #elif CONFIG_ESP_CONSOLE_USB_CDC - const esp_vfs_t *cdcacm_vfs = esp_vfs_cdcacm_get_vfs(); + primary_vfs = esp_vfs_cdcacm_get_vfs(); err = esp_usb_console_init(); if (err != ESP_OK) { return err; } - err = esp_vfs_register_common(primary_path, strlen(primary_path), cdcacm_vfs, NULL, &primary_vfs_index); #elif CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG - const esp_vfs_t *usb_serial_jtag_vfs = esp_vfs_usb_serial_jtag_get_vfs(); - err = esp_vfs_register_common(primary_path, strlen(primary_path), usb_serial_jtag_vfs, NULL, &primary_vfs_index); + primary_vfs = esp_vfs_usb_serial_jtag_get_vfs(); #endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG + err = esp_vfs_register_common(primary_path, strlen(primary_path), primary_vfs, NULL, &primary_vfs_index); if (err != ESP_OK) { return err; } // Secondary register part. #if CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG - const esp_vfs_t *usb_serial_jtag_vfs = esp_vfs_usb_serial_jtag_get_vfs(); - err = esp_vfs_register_common(secondary_path, strlen(secondary_path), usb_serial_jtag_vfs, NULL, &secondary_vfs_index); + secondary_vfs = esp_vfs_usb_serial_jtag_get_vfs(); + err = esp_vfs_register_common(secondary_path, strlen(secondary_path), secondary_vfs, NULL, &secondary_vfs_index); if(err != ESP_OK) { return err; } @@ -225,4 +227,26 @@ esp_err_t esp_vfs_console_register(void) return err; } +void esp_vfs_set_primary_dev_vfs_def_struct(const esp_vfs_t *vfs) +{ + primary_vfs = vfs; +} + +#if CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG +void esp_vfs_set_secondary_dev_vfs_def_struct(const esp_vfs_t *vfs) +{ + secondary_vfs = vfs; +} +#endif + +ESP_SYSTEM_INIT_FN(init_vfs_console, CORE, BIT(0), 114) +{ + return esp_vfs_console_register(); +} + #endif // CONFIG_VFS_SUPPORT_IO + +void esp_vfs_include_console_register(void) +{ + // Linker hook function, exists to make the linker examine this file +} diff --git a/components/vfs/vfs_usb_serial_jtag.c b/components/vfs/vfs_usb_serial_jtag.c index d17a2a4d6c7..afbb9dccd00 100644 --- a/components/vfs/vfs_usb_serial_jtag.c +++ b/components/vfs/vfs_usb_serial_jtag.c @@ -270,6 +270,10 @@ static int usb_serial_jtag_fsync(int fd) while ((esp_timer_get_time() - s_ctx.last_tx_ts) < TX_FLUSH_TIMEOUT_US) { if (usb_serial_jtag_ll_txfifo_writable()) { s_ctx.last_tx_ts = esp_timer_get_time(); + //The last transfer may have been a 64-byte one. Flush again in order to + //send a 0-byte packet to indicate the end of the USB transfer, otherwise + //those 64 bytes will get stuck in the hosts buffer. + usb_serial_jtag_ll_txfifo_flush(); break; } } diff --git a/components/wear_levelling/host_test/CMakeLists.txt b/components/wear_levelling/host_test/CMakeLists.txt index a40e7fc5b6e..fbc57301315 100644 --- a/components/wear_levelling/host_test/CMakeLists.txt +++ b/components/wear_levelling/host_test/CMakeLists.txt @@ -2,9 +2,7 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -# Freertos is included via common components. However, CATCH isn't compatible with the FreeRTOS component yet, hence -# using the FreeRTOS mock component. -# target. +# This test app doesn't require FreeRTOS, using mock instead list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") project(wear_levelling_host_test) diff --git a/components/wear_levelling/host_test/main/CMakeLists.txt b/components/wear_levelling/host_test/main/CMakeLists.txt index 92fb22c7bd1..51cd93762eb 100644 --- a/components/wear_levelling/host_test/main/CMakeLists.txt +++ b/components/wear_levelling/host_test/main/CMakeLists.txt @@ -1,8 +1,10 @@ -idf_component_register(SRCS "main.cpp" - "test_wl.cpp" - INCLUDE_DIRS "$ENV{IDF_PATH}/tools/catch" +idf_component_register(SRCS "test_wl.cpp" PRIV_INCLUDE_DIRS "../../private_include" "../.." REQUIRES wear_levelling WHOLE_ARCHIVE ) + +# Currently 'main' for IDF_TARGET=linux is defined in freertos component. +# Since we are using a freertos mock here, need to let Catch2 provide 'main'. +target_link_libraries(${COMPONENT_LIB} PRIVATE Catch2WithMain) diff --git a/components/wear_levelling/host_test/main/esp_error_check_stub.cpp b/components/wear_levelling/host_test/main/esp_error_check_stub.cpp deleted file mode 100644 index fe407ad079b..00000000000 --- a/components/wear_levelling/host_test/main/esp_error_check_stub.cpp +++ /dev/null @@ -1,19 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "catch.hpp" -#include "esp_err.h" -#include "sdkconfig.h" - -void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression) -{ - printf("ESP_ERROR_CHECK failed: esp_err_t 0x%x", rc); -#ifdef CONFIG_ESP_ERR_TO_NAME_LOOKUP - printf(" (%s)", esp_err_to_name(rc)); -#endif //CONFIG_ESP_ERR_TO_NAME_LOOKUP - printf(" at %p\n", __builtin_return_address(0)); - printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression); - abort(); -} diff --git a/components/wear_levelling/host_test/main/idf_component.yml b/components/wear_levelling/host_test/main/idf_component.yml new file mode 100644 index 00000000000..f7982136b97 --- /dev/null +++ b/components/wear_levelling/host_test/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/catch2: "^3.4.0" diff --git a/components/wear_levelling/host_test/main/main.cpp b/components/wear_levelling/host_test/main/main.cpp deleted file mode 100644 index 42286b7501e..00000000000 --- a/components/wear_levelling/host_test/main/main.cpp +++ /dev/null @@ -1,7 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#define CATCH_CONFIG_MAIN -#include "catch.hpp" diff --git a/components/wear_levelling/host_test/main/test_wl.cpp b/components/wear_levelling/host_test/main/test_wl.cpp index 4b25b99c65f..ebf23830a04 100644 --- a/components/wear_levelling/host_test/main/test_wl.cpp +++ b/components/wear_levelling/host_test/main/test_wl.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,7 +15,7 @@ #include "crc32.h" -#include "catch.hpp" +#include #include "sdkconfig.h" @@ -34,7 +34,6 @@ TEST_CASE("write and read back data", "[wear_levelling]") esp_err_t result; wl_handle_t wl_handle; - int flash_handle; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); // Mount wear-levelled partition @@ -105,7 +104,6 @@ TEST_CASE("power down test", "[wear_levelling]") esp_err_t result; wl_handle_t wl_handle; - int flash_handle; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); // Disable power down failure counting @@ -295,7 +293,6 @@ TEST_CASE("power down during WL status 1 update", "[wear_levelling]") esp_err_t result; wl_handle_t wl_handle; - int flash_handle; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); size_t offset_state_1, offset_state_2, size_state = 0; @@ -339,7 +336,6 @@ TEST_CASE("power down during WL status 2 update", "[wear_levelling]") esp_err_t result; wl_handle_t wl_handle; - int flash_handle; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); size_t offset_state_1, offset_state_2, size_state = 0; @@ -383,7 +379,6 @@ TEST_CASE("power down between WL status 1 and WL status 2 update", "[wear_levell esp_err_t result; wl_handle_t wl_handle; - int flash_handle; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); size_t offset_state_1, offset_state_2, size_state = 0; diff --git a/components/wifi_provisioning/include/wifi_provisioning/manager.h b/components/wifi_provisioning/include/wifi_provisioning/manager.h index e6cfa5dbedf..b8780762f61 100644 --- a/components/wifi_provisioning/include/wifi_provisioning/manager.h +++ b/components/wifi_provisioning/include/wifi_provisioning/manager.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -283,15 +283,11 @@ void wifi_prov_mgr_deinit(void); esp_err_t wifi_prov_mgr_is_provisioned(bool *provisioned); /** - * @brief Checks if prov mgr is stopped + * @brief Checks whether the provisioning state machine is idle * - * This checks if prov_ctx->prov_state == WIFI_PROV_STATE_IDLE - * - * @return - * - ture : prov mgr state is idle - * - false : prov mgr is not idle + * @return True if state machine is idle, else false */ -bool wifi_prov_mgr_is_stopped(); +bool wifi_prov_mgr_is_sm_idle(void); /** * @brief Start provisioning service diff --git a/components/wifi_provisioning/src/manager.c b/components/wifi_provisioning/src/manager.c index b39ba83a93a..6b2e3254726 100644 --- a/components/wifi_provisioning/src/manager.c +++ b/components/wifi_provisioning/src/manager.c @@ -1214,7 +1214,7 @@ esp_err_t wifi_prov_mgr_is_provisioned(bool *provisioned) return ESP_OK; } -bool wifi_prov_mgr_is_stopped() +bool wifi_prov_mgr_is_sm_idle(void) { return (prov_ctx->prov_state == WIFI_PROV_STATE_IDLE); } diff --git a/components/wpa_supplicant/esp_supplicant/include/esp_dpp.h b/components/wpa_supplicant/esp_supplicant/include/esp_dpp.h index f932c327ff6..6bcd846ef3c 100644 --- a/components/wpa_supplicant/esp_supplicant/include/esp_dpp.h +++ b/components/wpa_supplicant/esp_supplicant/include/esp_dpp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,10 +15,12 @@ extern "C" { #endif +#define ESP_DPP_AUTH_TIMEOUT_SECS 1 + #define ESP_ERR_DPP_FAILURE (ESP_ERR_WIFI_BASE + 151) /*!< Generic failure during DPP Operation */ #define ESP_ERR_DPP_TX_FAILURE (ESP_ERR_WIFI_BASE + 152) /*!< DPP Frame Tx failed OR not Acked */ #define ESP_ERR_DPP_INVALID_ATTR (ESP_ERR_WIFI_BASE + 153) /*!< Encountered invalid DPP Attribute */ - +#define ESP_ERR_DPP_AUTH_TIMEOUT (ESP_ERR_WIFI_BASE + 154) /*!< DPP Auth response was not recieved in time */ /** @brief Types of Bootstrap Methods for DPP. */ typedef enum dpp_bootstrap_type { DPP_BOOTSTRAP_QR_CODE, /**< QR Code Method */ diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_dpp.c b/components/wpa_supplicant/esp_supplicant/src/esp_dpp.c index aee399df901..83ef62caa22 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_dpp.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_dpp.c @@ -6,6 +6,7 @@ #include "utils/includes.h" #include "utils/common.h" +#include "utils/eloop.h" #include "common/defs.h" #include "esp_dpp_i.h" @@ -14,14 +15,14 @@ #include "esp_event.h" #include "esp_wifi.h" #include "common/ieee802_11_defs.h" +#include "esp_wps_i.h" #ifdef CONFIG_DPP static void *s_dpp_task_hdl = NULL; static void *s_dpp_evt_queue = NULL; static void *s_dpp_api_lock = NULL; -static bool s_dpp_stop_listening; -static int s_dpp_auth_retries; +static bool s_dpp_listen_in_progress; static struct esp_dpp_context_t s_dpp_ctx; static wifi_action_rx_cb_t s_action_rx_cb = esp_supp_rx_action; @@ -36,6 +37,7 @@ struct action_rx_param { struct ieee80211_action *action_frm; }; + static int esp_dpp_post_evt(uint32_t evt_id, uint32_t data) { dpp_event_t *evt = os_zalloc(sizeof(dpp_event_t)); @@ -72,9 +74,27 @@ static int esp_dpp_post_evt(uint32_t evt_id, uint32_t data) static void esp_dpp_call_cb(esp_supp_dpp_event_t evt, void *data) { + if ( evt == ESP_SUPP_DPP_FAIL && s_dpp_ctx.dpp_auth) { + dpp_auth_deinit(s_dpp_ctx.dpp_auth); + s_dpp_ctx.dpp_auth = NULL; + } s_dpp_ctx.dpp_event_cb(evt, data); } +static void esp_dpp_auth_conf_wait_timeout(void *eloop_ctx, void *timeout_ctx) +{ + if (!s_dpp_ctx.dpp_auth || !s_dpp_ctx.dpp_auth->waiting_auth_conf) + return; + + wpa_printf(MSG_DEBUG, + "DPP: Terminate authentication exchange due to Auth Confirm timeout"); + if (s_dpp_ctx.dpp_auth) { + dpp_auth_deinit(s_dpp_ctx.dpp_auth); + s_dpp_ctx.dpp_auth = NULL; + } + esp_dpp_call_cb(ESP_SUPP_DPP_FAIL, (void *)ESP_ERR_DPP_AUTH_TIMEOUT); +} + void esp_send_action_frame(uint8_t *dest_mac, const uint8_t *buf, uint32_t len, uint8_t channel, uint32_t wait_time_ms) { @@ -140,15 +160,20 @@ static void esp_dpp_rx_auth_req(struct action_rx_param *rx_param, uint8_t *dpp_d rc = ESP_ERR_DPP_INVALID_ATTR; goto fail; } - + if (s_dpp_ctx.dpp_auth) { + wpa_printf(MSG_DEBUG, "DPP: Already in DPP authentication exchange - ignore new one"); + return; + } s_dpp_ctx.dpp_auth = dpp_auth_req_rx(NULL, DPP_CAPAB_ENROLLEE, 0, NULL, own_bi, rx_param->channel, (const u8 *)&rx_param->action_frm->u.public_action.v, dpp_data, len); os_memcpy(s_dpp_ctx.dpp_auth->peer_mac_addr, rx_param->sa, ETH_ALEN); - esp_send_action_frame(rx_param->sa, wpabuf_head(s_dpp_ctx.dpp_auth->resp_msg), wpabuf_len(s_dpp_ctx.dpp_auth->resp_msg), rx_param->channel, OFFCHAN_TX_WAIT_TIME); + eloop_cancel_timeout(esp_dpp_auth_conf_wait_timeout, NULL,NULL); + eloop_register_timeout(ESP_DPP_AUTH_TIMEOUT_SECS, 0, esp_dpp_auth_conf_wait_timeout,NULL, NULL); + return; fail: esp_dpp_call_cb(ESP_SUPP_DPP_FAIL, (void *)rc); @@ -202,7 +227,7 @@ static int esp_dpp_handle_config_obj(struct dpp_authentication *auth, wpa_printf(MSG_INFO, DPP_EVENT_CONNECTOR "%s", conf->connector); } - s_dpp_stop_listening = false; + s_dpp_listen_in_progress = true; esp_wifi_action_tx_req(WIFI_OFFCHAN_TX_CANCEL, 0, 0, NULL); esp_dpp_call_cb(ESP_SUPP_DPP_CFG_RECVD, wifi_cfg); @@ -233,6 +258,8 @@ static void esp_dpp_rx_auth_conf(struct action_rx_param *rx_param, uint8_t *dpp_ goto fail; } + eloop_cancel_timeout(esp_dpp_auth_conf_wait_timeout, NULL, NULL); + if (dpp_auth_conf_rx(auth, (const u8 *)&public_action->v, dpp_data, len) < 0) { wpa_printf(MSG_DEBUG, "DPP: Authentication failed"); @@ -282,7 +309,7 @@ static void gas_query_resp_rx(struct action_rx_param *rx_param) int i, res; if (pos[1] == WLAN_EID_VENDOR_SPECIFIC && pos[2] == 5 && - WPA_GET_BE24(&pos[3]) == OUI_WFA && pos[6] == 0x1a && pos[7] == 1) { + WPA_GET_BE24(&pos[3]) == OUI_WFA && pos[6] == 0x1a && pos[7] == 1 && auth) { if (dpp_conf_resp_rx(auth, resp, rx_param->vendor_data_len - 2) < 0) { wpa_printf(MSG_DEBUG, "DPP: Configuration attempt failed"); goto fail; @@ -318,7 +345,7 @@ static void esp_dpp_rx_action(struct action_rx_param *rx_param) (size_t)(public_action->v.pa_vendor_spec.vendor_data - (u8 *)rx_param->action_frm); - if (!s_dpp_stop_listening) { + if (s_dpp_listen_in_progress) { esp_supp_dpp_stop_listen(); } @@ -355,6 +382,21 @@ static void esp_dpp_task(void *pvParameters ) switch (evt->id) { case SIG_DPP_DEL_TASK: + struct dpp_bootstrap_params_t *params = &s_dpp_ctx.bootstrap_params; + eloop_cancel_timeout(esp_dpp_auth_conf_wait_timeout, NULL, NULL); + if (params->info) { + os_free(params->info); + params->info = NULL; + } + + if (s_dpp_ctx.dpp_global) { + dpp_global_deinit(s_dpp_ctx.dpp_global); + s_dpp_ctx.dpp_global = NULL; + } + if (s_dpp_ctx.dpp_auth) { + dpp_auth_deinit(s_dpp_ctx.dpp_auth); + s_dpp_ctx.dpp_auth = NULL; + } task_del = true; break; @@ -379,14 +421,20 @@ static void esp_dpp_task(void *pvParameters ) struct dpp_bootstrap_params_t *p = &s_dpp_ctx.bootstrap_params; static int counter; int channel; + esp_err_t ret = 0; if (p->num_chan <= 0) { wpa_printf(MSG_ERROR, "Listen channel not set"); break; } channel = p->chan_list[counter++ % p->num_chan]; - esp_wifi_remain_on_channel(WIFI_IF_STA, WIFI_ROC_REQ, channel, + ret = esp_wifi_remain_on_channel(WIFI_IF_STA, WIFI_ROC_REQ, channel, BOOTSTRAP_ROC_WAIT_TIME, s_action_rx_cb); + if (ret != ESP_OK) { + wpa_printf(MSG_ERROR, "Failed ROC. error : 0x%x", ret); + break; + } + s_dpp_listen_in_progress = true; } break; @@ -459,13 +507,14 @@ static void offchan_event_handler(void *arg, esp_event_base_t event_base, evt->status, (uint32_t)evt->context); if (evt->status) { + eloop_cancel_timeout(esp_dpp_auth_conf_wait_timeout, NULL, NULL); esp_dpp_call_cb(ESP_SUPP_DPP_FAIL, (void *)ESP_ERR_DPP_TX_FAILURE); } } else if (event_id == WIFI_EVENT_ROC_DONE) { wifi_event_roc_done_t *evt = (wifi_event_roc_done_t *)event_data; - if (!s_dpp_stop_listening && evt->context == (uint32_t)s_action_rx_cb) { + if (s_dpp_listen_in_progress && evt->context == (uint32_t)s_action_rx_cb) { esp_dpp_post_evt(SIG_DPP_LISTEN_NEXT_CHANNEL, 0); } } @@ -590,6 +639,11 @@ esp_supp_dpp_bootstrap_gen(const char *chan_list, enum dpp_bootstrap_type type, esp_err_t esp_supp_dpp_start_listen(void) { + if (s_dpp_listen_in_progress) { + wpa_printf(MSG_ERROR, "DPP: Failed to start listen as listen is already in progress."); + return ESP_FAIL; + } + if (!s_dpp_ctx.dpp_global || s_dpp_ctx.id < 1) { wpa_printf(MSG_ERROR, "DPP: failed to start listen as dpp not initialized or bootstrapped."); return ESP_FAIL; @@ -600,51 +654,72 @@ esp_err_t esp_supp_dpp_start_listen(void) return ESP_ERR_INVALID_STATE; } - s_dpp_stop_listening = false; return esp_dpp_post_evt(SIG_DPP_LISTEN_NEXT_CHANNEL, 0); } void esp_supp_dpp_stop_listen(void) { - s_dpp_stop_listening = true; + s_dpp_listen_in_progress = false; esp_wifi_remain_on_channel(WIFI_IF_STA, WIFI_ROC_CANCEL, 0, 0, NULL); } +bool is_dpp_enabled(void) +{ + return (s_dpp_ctx.dpp_global ? true : false); +} + esp_err_t esp_supp_dpp_init(esp_supp_dpp_event_cb_t cb) { + esp_err_t ret = ESP_OK; wifi_mode_t mode = 0; if (esp_wifi_get_mode(&mode) || ((mode != WIFI_MODE_STA) && (mode != WIFI_MODE_APSTA))) { wpa_printf(MSG_ERROR, "DPP: failed to init as not in station mode."); return ESP_FAIL; } + + if (is_wps_enabled()) { + wpa_printf(MSG_ERROR, "DPP: failed to init since WPS is enabled"); + return ESP_FAIL; + } if (s_dpp_ctx.dpp_global) { wpa_printf(MSG_ERROR, "DPP: failed to init as init already done."); return ESP_FAIL; } - struct dpp_global_config cfg = {0}; - int ret; os_bzero(&s_dpp_ctx, sizeof(s_dpp_ctx)); - s_dpp_ctx.dpp_event_cb = cb; - + struct dpp_global_config cfg = {0}; cfg.cb_ctx = &s_dpp_ctx; cfg.msg_ctx = &s_dpp_ctx; s_dpp_ctx.dpp_global = dpp_global_init(&cfg); + if (!s_dpp_ctx.dpp_global) { + wpa_printf(MSG_ERROR, "DPP: failed to allocate memory for dpp_global"); + ret = ESP_ERR_NO_MEM; + goto init_fail; + } + + s_dpp_api_lock = os_recursive_mutex_create(); + if (!s_dpp_api_lock) { + wpa_printf(MSG_ERROR, "DPP: dpp_init: failed to create DPP API lock"); + ret = ESP_ERR_NO_MEM; + goto init_fail; + } - s_dpp_stop_listening = false; s_dpp_evt_queue = os_queue_create(3, sizeof(dpp_event_t)); + if (!s_dpp_evt_queue) { + wpa_printf(MSG_ERROR, "DPP: dpp_init: failed to create DPP API queue"); + ret = ESP_ERR_NO_MEM; + goto init_fail; + } + ret = os_task_create(esp_dpp_task, "dppT", DPP_TASK_STACK_SIZE, NULL, 2, &s_dpp_task_hdl); if (ret != TRUE) { wpa_printf(MSG_ERROR, "DPP: failed to create task"); - return ESP_FAIL; + ret = ESP_ERR_NO_MEM; + goto init_fail; } - s_dpp_api_lock = os_recursive_mutex_create(); - if (!s_dpp_api_lock) { - esp_supp_dpp_deinit(); - wpa_printf(MSG_ERROR, "DPP: dpp_init: failed to create DPP API lock"); - return ESP_ERR_NO_MEM; - } + s_dpp_listen_in_progress = false; + s_dpp_ctx.dpp_event_cb = cb; esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_ACTION_TX_STATUS, &offchan_event_handler, NULL); @@ -654,25 +729,32 @@ esp_err_t esp_supp_dpp_init(esp_supp_dpp_event_cb_t cb) wpa_printf(MSG_INFO, "esp_dpp_task prio:%d, stack:%d", 2, DPP_TASK_STACK_SIZE); return ESP_OK; +init_fail: + if (s_dpp_ctx.dpp_global) { + dpp_global_deinit(s_dpp_ctx.dpp_global); + s_dpp_ctx.dpp_global = NULL; + } + if (s_dpp_api_lock) { + os_mutex_delete(s_dpp_api_lock); + s_dpp_api_lock = NULL; + } + if (s_dpp_evt_queue) { + os_queue_delete(s_dpp_evt_queue); + s_dpp_evt_queue = NULL; + } + return ret; } - void esp_supp_dpp_deinit(void) { - struct dpp_bootstrap_params_t *params = &s_dpp_ctx.bootstrap_params; - if (params->info) { - os_free(params->info); - params->info = NULL; - } esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_ACTION_TX_STATUS, &offchan_event_handler); esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_ROC_DONE, &offchan_event_handler); - s_dpp_auth_retries = 0; if (s_dpp_ctx.dpp_global) { - dpp_global_deinit(s_dpp_ctx.dpp_global); - s_dpp_ctx.dpp_global = NULL; - esp_dpp_post_evt(SIG_DPP_DEL_TASK, 0); + if (esp_dpp_post_evt(SIG_DPP_DEL_TASK, 0)) { + wpa_printf(MSG_ERROR, "DPP Deinit Failed"); + } } } #endif diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_dpp_i.h b/components/wpa_supplicant/esp_supplicant/src/esp_dpp_i.h index 3646d1866c2..2e97d1aa39c 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_dpp_i.h +++ b/components/wpa_supplicant/esp_supplicant/src/esp_dpp_i.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -55,4 +55,12 @@ struct esp_dpp_context_t { int esp_supp_rx_action(uint8_t *hdr, uint8_t *payload, size_t len, uint8_t channel); +#ifdef CONFIG_ESP_WIFI_DPP_SUPPORT +bool is_dpp_enabled(void); +#else +static inline bool is_dpp_enabled(void) +{ + return false; +} +#endif #endif /* ESP_DPP_I_H */ diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c index de43583afac..51f743e1636 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c @@ -26,6 +26,7 @@ #include "esp_err.h" #include "esp_private/wifi.h" #include "esp_wps_i.h" +#include "esp_dpp_i.h" #include "esp_wps.h" #include "eap_common/eap_wsc_common.h" #include "esp_wpas_glue.h" @@ -157,9 +158,11 @@ void wps_task(void *pvParameters ) if (e->sig == SIG_WPS_ENABLE) { param->ret = wifi_wps_enable_internal((esp_wps_config_t *)(param->arg)); } else if (e->sig == SIG_WPS_DISABLE) { + DATA_MUTEX_TAKE(); param->ret = wifi_wps_disable_internal(); del_task = true; s_wps_task_hdl = NULL; + DATA_MUTEX_GIVE(); } else { param->ret = wifi_station_wps_start(); } @@ -220,6 +223,12 @@ int wps_post(uint32_t sig, uint32_t par) wpa_printf(MSG_DEBUG, "wps post: sig=%" PRId32 " cnt=%d", sig, s_wps_sig_cnt[sig]); DATA_MUTEX_TAKE(); + + if (!s_wps_task_hdl) { + wpa_printf(MSG_DEBUG, "wps post: sig=%" PRId32 " failed as wps task has been deinited", sig); + DATA_MUTEX_GIVE(); + return ESP_FAIL; + } if (s_wps_sig_cnt[sig]) { wpa_printf(MSG_DEBUG, "wps post: sig=%" PRId32 " processing", sig); DATA_MUTEX_GIVE(); @@ -1709,12 +1718,6 @@ int wps_task_deinit(void) wps_rxq_deinit(); } - if (s_wps_data_lock) { - os_semphr_delete(s_wps_data_lock); - s_wps_data_lock = NULL; - wpa_printf(MSG_DEBUG, "wps task deinit: free data lock"); - } - return ESP_OK; } @@ -1726,10 +1729,12 @@ int wps_task_init(void) */ wps_task_deinit(); - s_wps_data_lock = os_recursive_mutex_create(); if (!s_wps_data_lock) { - wpa_printf(MSG_ERROR, "wps task init: failed to alloc data lock"); - goto _wps_no_mem; + s_wps_data_lock = os_recursive_mutex_create(); + if (!s_wps_data_lock) { + wpa_printf(MSG_ERROR, "wps task init: failed to alloc data lock"); + goto _wps_no_mem; + } } s_wps_api_sem = os_semphr_create(1, 0); @@ -1826,6 +1831,11 @@ int esp_wifi_wps_enable(const esp_wps_config_t *config) return ESP_ERR_WIFI_MODE; } + if (is_dpp_enabled()) { + wpa_printf(MSG_ERROR, "wps enabled failed since DPP is initialized"); + return ESP_FAIL; + } + API_MUTEX_TAKE(); if (s_wps_enabled) { if (sm && os_memcmp(sm->identity, WSC_ID_REGISTRAR, sm->identity_len) == 0) { @@ -1863,6 +1873,11 @@ int esp_wifi_wps_enable(const esp_wps_config_t *config) #endif } +bool is_wps_enabled(void) +{ + return s_wps_enabled; +} + int wifi_wps_enable_internal(const esp_wps_config_t *config) { int ret = 0; @@ -1873,7 +1888,6 @@ int wifi_wps_enable_internal(const esp_wps_config_t *config) wpa_printf(MSG_ERROR, "wps enable: invalid wps type"); return ESP_ERR_WIFI_WPS_TYPE; } - wpa_printf(MSG_DEBUG, "Set factory information."); ret = wps_set_factory_info(config); if (ret != 0) { @@ -1899,6 +1913,11 @@ int wifi_wps_enable_internal(const esp_wps_config_t *config) int wifi_wps_disable_internal(void) { wps_set_status(WPS_STATUS_DISABLE); + + /* Call wps_delete_timer to delete all WPS timer, no timer will call wps_post() + * to post message to wps_task once this function returns. + */ + wps_delete_timer(); wifi_station_wps_deinit(); return ESP_OK; } @@ -1926,11 +1945,6 @@ int esp_wifi_wps_disable(void) wpa_printf(MSG_INFO, "wifi_wps_disable"); wps_set_type(WPS_TYPE_DISABLE); /* Notify WiFi task */ - /* Call wps_delete_timer to delete all WPS timer, no timer will call wps_post() - * to post message to wps_task once this function returns. - */ - wps_delete_timer(); - #ifdef USE_WPS_TASK ret = wps_post_block(SIG_WPS_DISABLE, 0); #else diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h b/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h index 5dd055ad4d6..8b0f87cc486 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h @@ -125,5 +125,7 @@ static inline int wps_set_status(uint32_t status) { return esp_wifi_set_wps_status_internal(status); } + +bool is_wps_enabled(void); int wps_init_cfg_pin(struct wps_config *cfg); void wifi_station_wps_eapol_start_handle(void *data, void *user_ctx); diff --git a/components/wpa_supplicant/src/ap/wpa_auth.c b/components/wpa_supplicant/src/ap/wpa_auth.c index 5b0b4ae9013..9b380a4b1ab 100644 --- a/components/wpa_supplicant/src/ap/wpa_auth.c +++ b/components/wpa_supplicant/src/ap/wpa_auth.c @@ -217,10 +217,10 @@ int wpa_auth_for_each_sta(struct wpa_authenticator *wpa_auth, } static void wpa_sta_disconnect(struct wpa_authenticator *wpa_auth, - const u8 *addr) + const u8 *addr, u16 reason) { wpa_printf(MSG_DEBUG, "wpa_sta_disconnect STA " MACSTR, MAC2STR(addr)); - esp_wifi_ap_deauth_internal((uint8_t*)addr, WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT); + esp_wifi_ap_deauth_internal((uint8_t*)addr, reason); return; } @@ -797,7 +797,8 @@ void wpa_receive(struct wpa_authenticator *wpa_auth, struct wpa_state_machine *s "collect more entropy for random number " "generation"); random_mark_pool_ready(); - wpa_sta_disconnect(wpa_auth, sm->addr); + wpa_sta_disconnect(wpa_auth, sm->addr, + WLAN_REASON_PREV_AUTH_NOT_VALID); return; } if (wpa_parse_kde_ies((u8 *) (key + 1), key_data_length, @@ -824,12 +825,14 @@ void wpa_receive(struct wpa_authenticator *wpa_auth, struct wpa_state_machine *s wpa_hexdump(MSG_DEBUG, "WPA IE in msg 2/4", eapol_key_ie, eapol_key_ie_len); /* MLME-DEAUTHENTICATE.request */ - wpa_sta_disconnect(wpa_auth, sm->addr); + wpa_sta_disconnect(wpa_auth, sm->addr, + WLAN_REASON_PREV_AUTH_NOT_VALID); return; } #ifdef CONFIG_IEEE80211R_AP if (ft && ft_check_msg_2_of_4(wpa_auth, sm, &kde) < 0) { - wpa_sta_disconnect(wpa_auth, sm->addr); + wpa_sta_disconnect(wpa_auth, sm->addr, + WLAN_REASON_PREV_AUTH_NOT_VALID); return; } #endif /* CONFIG_IEEE80211R_AP */ @@ -863,6 +866,8 @@ void wpa_receive(struct wpa_authenticator *wpa_auth, struct wpa_state_machine *s if (sm->PTK_valid && !sm->update_snonce) { if (wpa_verify_key_mic(sm->wpa_key_mgmt, &sm->PTK, data, data_len)) { + wpa_printf(MSG_INFO, + "received EAPOL-Key with invalid MIC"); return; } sm->MICVerified = TRUE; @@ -876,6 +881,8 @@ void wpa_receive(struct wpa_authenticator *wpa_auth, struct wpa_state_machine *s memcpy(sm->req_replay_counter, key->replay_counter, WPA_REPLAY_COUNTER_LEN); } else { + wpa_printf(MSG_INFO, + "received EAPOL-Key request with invalid MIC"); return; } @@ -1359,9 +1366,14 @@ SM_STATE(WPA_PTK, INITIALIZE) SM_STATE(WPA_PTK, DISCONNECT) { + u16 reason = sm->disconnect_reason; + SM_ENTRY_MA(WPA_PTK, DISCONNECT, wpa_ptk); sm->Disconnect = FALSE; - wpa_sta_disconnect(sm->wpa_auth, sm->addr); + sm->disconnect_reason = 0; + if (!reason) + reason = WLAN_REASON_PREV_AUTH_NOT_VALID; + wpa_sta_disconnect(sm->wpa_auth, sm->addr, reason); } @@ -1431,7 +1443,7 @@ SM_STATE(WPA_PTK, AUTHENTICATION2) if (os_get_random(sm->ANonce, WPA_NONCE_LEN)) { wpa_printf( MSG_ERROR, "WPA: Failed to get random data for " "ANonce."); - wpa_sta_disconnect(sm->wpa_auth, sm->addr); + sm->Disconnect = true; return; } wpa_hexdump(MSG_DEBUG, "WPA: Assign ANonce", sm->ANonce, @@ -1645,11 +1657,8 @@ SM_STATE(WPA_PTK, PTKCALCNEGOTIATING) if (wpa_verify_key_mic(sm->wpa_key_mgmt, &PTK, sm->last_rx_eapol_key, sm->last_rx_eapol_key_len) == 0) { - wpa_printf( MSG_DEBUG, "mic verify ok, pmk=%p", pmk); ok = 1; break; - } else { - wpa_printf( MSG_DEBUG, "mic verify fail, pmk=%p", pmk); } if (!wpa_key_mgmt_wpa_psk(sm->wpa_key_mgmt) || @@ -1660,6 +1669,7 @@ SM_STATE(WPA_PTK, PTKCALCNEGOTIATING) } if (!ok) { + wpa_printf(MSG_INFO, "invalid MIC in msg 2/4 of 4-Way Handshake"); return; } @@ -1705,7 +1715,8 @@ SM_STATE(WPA_PTK, PTKCALCNEGOTIATING) sm->rsnxe, sm->rsnxe_len); wpa_hexdump(MSG_DEBUG, "RSNXE in EAPOL-Key msg 2/4", kde.rsnxe, kde.rsnxe_len); - wpa_sta_disconnect(sm->wpa_auth, sm->addr); + wpa_sta_disconnect(sm->wpa_auth, sm->addr, + WLAN_REASON_PREV_AUTH_NOT_VALID); return; } @@ -1950,7 +1961,8 @@ SM_STATE(WPA_PTK, PTKINITDONE) int klen = wpa_cipher_key_len(sm->pairwise); if (wpa_auth_set_key(sm->wpa_auth, 0, alg, sm->addr, 0, sm->PTK.tk, klen)) { - wpa_sta_disconnect(sm->wpa_auth, sm->addr); + wpa_sta_disconnect(sm->wpa_auth, sm->addr, + WLAN_REASON_PREV_AUTH_NOT_VALID); return; } /* FIX: MLME-SetProtection.Request(TA, Tx_Rx) */ @@ -2062,6 +2074,8 @@ SM_STEP(WPA_PTK) SM_ENTER(WPA_PTK, PTKCALCNEGOTIATING); else if (sm->TimeoutCtr > (int) dot11RSNAConfigPairwiseUpdateCount) { + sm->disconnect_reason = + WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT; SM_ENTER(WPA_PTK, DISCONNECT); } else if (sm->TimeoutEvt) SM_ENTER(WPA_PTK, PTKSTART); @@ -2086,6 +2100,8 @@ SM_STEP(WPA_PTK) SM_ENTER(WPA_PTK, PTKINITDONE); else if (sm->TimeoutCtr > (int) dot11RSNAConfigPairwiseUpdateCount) { + sm->disconnect_reason = + WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT; SM_ENTER(WPA_PTK, DISCONNECT); } else if (sm->TimeoutEvt) SM_ENTER(WPA_PTK, PTKINITNEGOTIATING); @@ -2191,6 +2207,7 @@ SM_STATE(WPA_PTK_GROUP, KEYERROR) sm->group->GKeyDoneStations--; sm->GUpdateStationKeys = FALSE; sm->Disconnect = TRUE; + sm->disconnect_reason = WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT; } diff --git a/components/wpa_supplicant/src/ap/wpa_auth_i.h b/components/wpa_supplicant/src/ap/wpa_auth_i.h index 672cc09425c..2516b34f695 100644 --- a/components/wpa_supplicant/src/ap/wpa_auth_i.h +++ b/components/wpa_supplicant/src/ap/wpa_auth_i.h @@ -47,6 +47,7 @@ struct wpa_state_machine { Boolean AuthenticationRequest; Boolean ReAuthenticationRequest; Boolean Disconnect; + u16 disconnect_reason; /* specific reason code to use with Disconnect */ int TimeoutCtr; int GTimeoutCtr; Boolean TimeoutEvt; diff --git a/components/wpa_supplicant/src/rsn_supp/wpa.c b/components/wpa_supplicant/src/rsn_supp/wpa.c index 94cfa95fbc0..a3c380ca815 100644 --- a/components/wpa_supplicant/src/rsn_supp/wpa.c +++ b/components/wpa_supplicant/src/rsn_supp/wpa.c @@ -1011,37 +1011,37 @@ int wpa_supplicant_pairwise_gtk(struct wpa_sm *sm, static int wpa_supplicant_install_igtk(struct wpa_sm *sm, const wifi_wpa_igtk_t *igtk) { - size_t len = wpa_cipher_key_len(sm->mgmt_group_cipher); - u16 keyidx = WPA_GET_LE16(igtk->keyid); - - /* Detect possible key reinstallation */ - if (sm->igtk.igtk_len == len && - os_memcmp(sm->igtk.igtk, igtk->igtk, sm->igtk.igtk_len) == 0) { - wpa_printf(MSG_DEBUG, - "WPA: Not reinstalling already in-use IGTK to the driver (keyidx=%d)", - keyidx); - return 0; - } - - wpa_printf(MSG_DEBUG, - "WPA: IGTK keyid %d pn %02x%02x%02x%02x%02x%02x", - keyidx, MAC2STR(igtk->pn)); - wpa_hexdump_key(MSG_DEBUG, "WPA: IGTK", igtk->igtk, len); - if (keyidx > 4095) { - wpa_printf(MSG_WARNING, - "WPA: Invalid IGTK KeyID %d", keyidx); - return -1; - } - if (esp_wifi_set_igtk_internal(WIFI_IF_STA, igtk) < 0) { - wpa_printf(MSG_WARNING, - "WPA: Failed to configure IGTK to the driver"); - return -1; - } - - sm->igtk.igtk_len = len; - os_memcpy(sm->igtk.igtk, igtk->igtk, sm->igtk.igtk_len); - - return 0; + size_t len = wpa_cipher_key_len(sm->mgmt_group_cipher); + u16 keyidx = WPA_GET_LE16(igtk->keyid); + + /* Detect possible key reinstallation */ + if (sm->igtk.igtk_len == len && + os_memcmp(sm->igtk.igtk, igtk->igtk, sm->igtk.igtk_len) == 0) { + wpa_printf(MSG_DEBUG, + "WPA: Not reinstalling already in-use IGTK to the driver (keyidx=%d)", + keyidx); + return 0; + } + + wpa_printf(MSG_DEBUG, + "WPA: IGTK keyid %d pn %02x%02x%02x%02x%02x%02x", + keyidx, MAC2STR(igtk->pn)); + wpa_hexdump_key(MSG_DEBUG, "WPA: IGTK", igtk->igtk, len); + + if (esp_wifi_set_igtk_internal(WIFI_IF_STA, igtk) < 0) { + if (keyidx > 4095) { + wpa_printf(MSG_WARNING, + "WPA: Invalid IGTK KeyID %d", keyidx); + } + wpa_printf(MSG_WARNING, + "WPA: Failed to configure IGTK to the driver"); + return -1; + } + + sm->igtk.igtk_len = len; + os_memcpy(sm->igtk.igtk, igtk->igtk, sm->igtk.igtk_len); + + return 0; } #endif /* CONFIG_IEEE80211W */ @@ -2740,14 +2740,16 @@ int wpa_sm_set_ap_rsnxe(const u8 *ie, size_t len) sm->ap_rsnxe_len = len; } - sm->sae_pwe = esp_wifi_get_config_sae_pwe_h2e_internal(WIFI_IF_STA); + if (sm->ap_rsnxe != NULL) { + sm->sae_pwe = esp_wifi_get_config_sae_pwe_h2e_internal(WIFI_IF_STA); #ifdef CONFIG_SAE_PK - const u8 *pw = (const u8 *)esp_wifi_sta_get_prof_password_internal(); - if (esp_wifi_sta_get_config_sae_pk_internal() != WPA3_SAE_PK_MODE_DISABLED && - sae_pk_valid_password((const char*)pw)) { - sm->sae_pk = true; - } + const u8 *pw = (const u8 *)esp_wifi_sta_get_prof_password_internal(); + if (esp_wifi_sta_get_config_sae_pk_internal() != WPA3_SAE_PK_MODE_DISABLED && + sae_pk_valid_password((const char*)pw)) { + sm->sae_pk = true; + } #endif /* CONFIG_SAE_PK */ + } return 0; } diff --git a/components/wpa_supplicant/test_apps/main/test_crypto.c b/components/wpa_supplicant/test_apps/main/test_crypto.c index e7b5a2159b2..42fefce8038 100644 --- a/components/wpa_supplicant/test_apps/main/test_crypto.c +++ b/components/wpa_supplicant/test_apps/main/test_crypto.c @@ -22,7 +22,7 @@ typedef struct crypto_bignum crypto_bignum; TEST_CASE("Test crypto lib bignum apis", "[wpa_crypto]") { - set_leak_threshold(250); + set_leak_threshold(300); { uint8_t buf[32], buf2[32]; diff --git a/components/wpa_supplicant/test_apps/main/test_dpp.c b/components/wpa_supplicant/test_apps/main/test_dpp.c index b75cbbd9153..69b5176fe82 100644 --- a/components/wpa_supplicant/test_apps/main/test_dpp.c +++ b/components/wpa_supplicant/test_apps/main/test_dpp.c @@ -34,7 +34,7 @@ extern size_t dpp_nonce_override_len; TEST_CASE("Test vectors DPP responder p256", "[wpa_dpp]") { - set_leak_threshold(120); + set_leak_threshold(130); /* Global variables */ char command[1200] = {0}; const u8 *frame; diff --git a/components/wpa_supplicant/test_apps/main/test_eloop.c b/components/wpa_supplicant/test_apps/main/test_eloop.c index 9553c50bb66..ea2b115ef47 100644 --- a/components/wpa_supplicant/test_apps/main/test_eloop.c +++ b/components/wpa_supplicant/test_apps/main/test_eloop.c @@ -55,7 +55,7 @@ extern const wifi_osi_funcs_t *wifi_funcs; /* Check if eloop runs its timers correctly & in correct order */ TEST_CASE("Test eloop timers run", "[eloop]") { - set_leak_threshold(800); + set_leak_threshold(1000); wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); cfg.nvs_enable = false; ESP_ERROR_CHECK(esp_wifi_init(&cfg)); diff --git a/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c b/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c index 6e94c3e403d..5e74a7b76d3 100644 --- a/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c +++ b/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c @@ -15,7 +15,7 @@ TEST_CASE("Test pbkdf2", "[crypto-pbkdf2]") { - set_leak_threshold(120); + set_leak_threshold(130); uint8_t PMK[PMK_LEN]; uint8_t ssid_len; diff --git a/components/wpa_supplicant/test_apps/main/test_sae.c b/components/wpa_supplicant/test_apps/main/test_sae.c index d2cef1572ee..bb1e36728dd 100644 --- a/components/wpa_supplicant/test_apps/main/test_sae.c +++ b/components/wpa_supplicant/test_apps/main/test_sae.c @@ -48,7 +48,7 @@ void wpabuf_free2(struct wpabuf *buf) TEST_CASE("Test SAE functionality with ECC group", "[wpa3_sae]") { - set_leak_threshold(120); + set_leak_threshold(400); ESP_LOGI("SAE Test", "### Beginning SAE init and deinit ###"); { /* Test init and deinit*/ @@ -162,7 +162,7 @@ TEST_CASE("Test SAE functionality with ECC group", "[wpa3_sae]") TEST_ASSERT(sae.tmp->sae_rand != NULL); TEST_ASSERT(mask != NULL); - TEST_ASSERT(crypto_bignum_add(sae.tmp->sae_rand, mask, sae.tmp->own_commit_scalar) == 0) + TEST_ASSERT(crypto_bignum_add(sae.tmp->sae_rand, mask, sae.tmp->own_commit_scalar) == 0); TEST_ASSERT(crypto_bignum_mod(sae.tmp->own_commit_scalar, sae.tmp->order, sae.tmp->own_commit_scalar) == 0); TEST_ASSERT(crypto_ec_point_mul(sae.tmp->ec, sae.tmp->pwe_ecc, mask, sae.tmp->own_commit_element_ecc) == 0); TEST_ASSERT(crypto_ec_point_invert(sae.tmp->ec, sae.tmp->own_commit_element_ecc) == 0); @@ -176,7 +176,7 @@ TEST_CASE("Test SAE functionality with ECC group", "[wpa3_sae]") TEST_ASSERT(os_memcmp(wpabuf_head(buf), local_commit, sizeof(local_commit)) == 0); TEST_ASSERT(sae_parse_commit(&sae, peer_commit, sizeof(peer_commit), NULL, NULL, NULL, 0) == 0); - TEST_ASSERT(sae_process_commit(&sae) == 0) + TEST_ASSERT(sae_process_commit(&sae) == 0); ESP_LOGI("SAE TEST", "### Compare derived KCK,PMK,PMKID with predefined vectors ###"); ESP_LOG_BUFFER_HEXDUMP("SAE: Derived KCK ", sae.tmp->kck, SAE_KCK_LEN, ESP_LOG_INFO); @@ -214,7 +214,7 @@ TEST_CASE("Test SAE functionality with ECC group", "[wpa3_sae]") ESP_LOG_BUFFER_HEXDUMP("SAE: Derived SAE: PT.y ", bin + prime_len, prime_len, ESP_LOG_INFO); ESP_LOG_BUFFER_HEXDUMP("SAE: Predefined SAE: PT.y ", pwe_19_y, prime_len, ESP_LOG_INFO); - TEST_ASSERT(os_memcmp(pwe_19_y, bin + prime_len, prime_len) == 0) + TEST_ASSERT(os_memcmp(pwe_19_y, bin + prime_len, prime_len) == 0); crypto_ec_point_deinit(pwe, 1); sae_deinit_pt(pt_info); diff --git a/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py b/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py index f2d647ed70e..2db192bb119 100644 --- a/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py +++ b/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py @@ -2,8 +2,8 @@ # SPDX-License-Identifier: CC0-1.0 import pytest -from idf_unity_tester import CaseTester from pytest_embedded import Dut +from pytest_embedded_idf.unity_tester import CaseTester @pytest.mark.generic @@ -19,6 +19,13 @@ def test_wpa_supplicant_ut(dut: Dut) -> None: @pytest.mark.esp32 @pytest.mark.wifi_two_dut +@pytest.mark.parametrize( + 'count', + [ + 2, + ], + indirect=True +) def test_wpa_supplicant_ut_offchan(case_tester: CaseTester) -> None: for case in case_tester.test_menu: if case.attributes.get('test_env') == 'wifi_two_dut': diff --git a/components/xtensa/deprecated_include/freertos/xtensa_api.h b/components/xtensa/deprecated_include/freertos/xtensa_api.h index 1e506180eec..891d1f59f6e 100644 --- a/components/xtensa/deprecated_include/freertos/xtensa_api.h +++ b/components/xtensa/deprecated_include/freertos/xtensa_api.h @@ -6,6 +6,6 @@ #pragma once -/* This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead */ -/* Todo: IDF-7230 */ -#include +#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead" + +#include diff --git a/components/xtensa/deprecated_include/freertos/xtensa_context.h b/components/xtensa/deprecated_include/freertos/xtensa_context.h index 83c7a762b2e..fda0bf23e39 100644 --- a/components/xtensa/deprecated_include/freertos/xtensa_context.h +++ b/components/xtensa/deprecated_include/freertos/xtensa_context.h @@ -6,6 +6,6 @@ #pragma once -/* This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead */ -/* Todo: IDF-7230 */ -#include +#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead" + +#include diff --git a/components/xtensa/deprecated_include/freertos/xtensa_timer.h b/components/xtensa/deprecated_include/freertos/xtensa_timer.h index 40f7223f44f..5f33d4b91cd 100644 --- a/components/xtensa/deprecated_include/freertos/xtensa_timer.h +++ b/components/xtensa/deprecated_include/freertos/xtensa_timer.h @@ -6,6 +6,6 @@ #pragma once -/* This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead */ -/* Todo: IDF-7230 */ +#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead" + #include diff --git a/components/xtensa/deprecated_include/xtensa/xtensa_api.h b/components/xtensa/deprecated_include/xtensa/xtensa_api.h index dbcbfd91c8d..71bd8f32483 100644 --- a/components/xtensa/deprecated_include/xtensa/xtensa_api.h +++ b/components/xtensa/deprecated_include/xtensa/xtensa_api.h @@ -6,6 +6,6 @@ #pragma once -/* This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead */ -/* Todo: IDF-7230 */ +#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead" + #include diff --git a/components/xtensa/deprecated_include/xtensa/xtensa_context.h b/components/xtensa/deprecated_include/xtensa/xtensa_context.h index e49c7e5df80..baef27983ec 100644 --- a/components/xtensa/deprecated_include/xtensa/xtensa_context.h +++ b/components/xtensa/deprecated_include/xtensa/xtensa_context.h @@ -6,6 +6,6 @@ #pragma once -/* This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead */ -/* Todo: IDF-7230 */ +#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead" + #include diff --git a/components/xtensa/deprecated_include/xtensa/xtensa_timer.h b/components/xtensa/deprecated_include/xtensa/xtensa_timer.h index 7df0c8d502e..b17332c9f1f 100644 --- a/components/xtensa/deprecated_include/xtensa/xtensa_timer.h +++ b/components/xtensa/deprecated_include/xtensa/xtensa_timer.h @@ -6,6 +6,6 @@ #pragma once -/* This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead */ -/* Todo: IDF-7230 */ +#warning "This header file has been moved, thus `#include ` is deprecated. Please use `#include ` instead" + #include diff --git a/components/xtensa/xtensa_intr.c b/components/xtensa/xtensa_intr.c index c02f82d0709..4d374aad50e 100644 --- a/components/xtensa/xtensa_intr.c +++ b/components/xtensa/xtensa_intr.c @@ -31,7 +31,7 @@ #include #include "esp_attr.h" -#include "xtensa/xtensa_api.h" +#include "xtensa_api.h" #include "sdkconfig.h" #include "esp_rom_sys.h" diff --git a/components/xtensa/xtensa_intr_asm.S b/components/xtensa/xtensa_intr_asm.S index 79d9beafe94..27fe781bfd4 100644 --- a/components/xtensa/xtensa_intr_asm.S +++ b/components/xtensa/xtensa_intr_asm.S @@ -36,7 +36,7 @@ #include #include -#include "xtensa/xtensa_context.h" +#include "xtensa_context.h" /* * When compiling for G0-only, we don't have FreeRTOS component. diff --git a/conftest.py b/conftest.py index cf127e7fe98..0fdc3ad45ad 100644 --- a/conftest.py +++ b/conftest.py @@ -28,20 +28,19 @@ from _pytest.fixtures import FixtureRequest from pytest_embedded.plugin import multi_dut_argument, multi_dut_fixture from pytest_embedded_idf.dut import IdfDut +from pytest_embedded_idf.unity_tester import CaseTester try: from idf_ci_utils import IDF_PATH from idf_pytest.constants import DEFAULT_SDKCONFIG, ENV_MARKERS, SPECIAL_MARKERS, TARGET_MARKERS from idf_pytest.plugin import IDF_PYTEST_EMBEDDED_KEY, IdfPytestEmbedded from idf_pytest.utils import format_case_id, get_target_marker_from_expr - from idf_unity_tester import CaseTester except ImportError: sys.path.append(os.path.join(os.path.dirname(__file__), 'tools', 'ci')) from idf_ci_utils import IDF_PATH from idf_pytest.constants import DEFAULT_SDKCONFIG, ENV_MARKERS, SPECIAL_MARKERS, TARGET_MARKERS from idf_pytest.plugin import IDF_PYTEST_EMBEDDED_KEY, IdfPytestEmbedded from idf_pytest.utils import format_case_id, get_target_marker_from_expr - from idf_unity_tester import CaseTester try: import common_test_methods # noqa: F401 @@ -70,8 +69,8 @@ def session_tempdir() -> str: @pytest.fixture -def case_tester(dut: IdfDut, **kwargs): # type: ignore - yield CaseTester(dut, **kwargs) +def case_tester(unity_tester: CaseTester) -> CaseTester: + return unity_tester @pytest.fixture diff --git a/docs/_static/diagrams/sd/sd_arch.diag b/docs/_static/diagrams/sd/sd_arch.diag new file mode 100644 index 00000000000..b6bd8f096e9 --- /dev/null +++ b/docs/_static/diagrams/sd/sd_arch.diag @@ -0,0 +1,13 @@ +blockdiag sd_arch { + default_fontsize = 16; + node_width = 300; + node_height = 100; + span_width = 150; + + A [label = "SD Protocol Layer Driver Component:\nsdmmc"] + B [label = "Host Driver Component:\nesp_driver_sdmmc"] + C [label = "Host Driver Component:\nesp_driver_sdspi"] + + A -> B [dir = back, label = "Implements", style = dashed, hstyle = generalization, fontsize=14] + A -> C [dir = back, label = "Implements", style = dashed, hstyle = generalization, fontsize=14] +} diff --git a/docs/_static/diagrams/sd/sd_arch.png b/docs/_static/diagrams/sd/sd_arch.png new file mode 100644 index 00000000000..e94c0ff3675 Binary files /dev/null and b/docs/_static/diagrams/sd/sd_arch.png differ diff --git a/docs/conf_common.py b/docs/conf_common.py index 6d286875c9a..143bb53e0c6 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -66,7 +66,10 @@ 'api-reference/network/esp_now.rst', 'api-reference/network/esp_smartconfig.rst', 'api-reference/network/esp_wifi.rst', - 'api-reference/network/esp_dpp.rst'] + 'api-reference/network/esp_dpp.rst', + 'api-reference/provisioning/provisioning.rst', + 'api-reference/provisioning/wifi_provisioning.rst', + 'migration-guides/release-5.x/5.2/wifi.rst'] NAN_DOCS = ['api-reference/network/esp_nan.rst'] @@ -145,15 +148,16 @@ SPI_SLAVE_HD_DOCS = ['api-reference/peripherals/spi_slave_hd.rst'] +QEMU_DOCS = ['api-guides/tools/qemu.rst'] + ESP32_DOCS = ['api-reference/system/himem.rst', 'api-guides/romconsole.rst', 'api-reference/system/ipc.rst', 'security/secure-boot-v1.rst', - 'api-reference/peripherals/secure_element.rst', 'api-reference/peripherals/dac.rst', 'api-reference/peripherals/sd_pullup_requirements.rst', 'hw-reference/esp32/**', - 'api-guides/RF_calibration.rst'] + FTDI_JTAG_DOCS + 'api-guides/RF_calibration.rst'] + FTDI_JTAG_DOCS + QEMU_DOCS ESP32S2_DOCS = ['hw-reference/esp32s2/**', 'api-guides/usb-console.rst', @@ -171,7 +175,7 @@ # No JTAG docs for this one as it gets gated on SOC_USB_SERIAL_JTAG_SUPPORTED down below. ESP32C3_DOCS = ['hw-reference/esp32c3/**', - 'api-guides/RF_calibration.rst'] + 'api-guides/RF_calibration.rst'] + QEMU_DOCS ESP32C2_DOCS = ['api-guides/RF_calibration.rst'] @@ -210,6 +214,7 @@ 'SOC_RISCV_COPROC_SUPPORTED':RISCV_COPROC_DOCS, 'SOC_LP_CORE_SUPPORTED':LP_CORE_DOCS, 'SOC_DIG_SIGN_SUPPORTED':['api-reference/peripherals/ds.rst'], + 'SOC_ECDSA_SUPPORTED':['api-reference/peripherals/ecdsa.rst'], 'SOC_HMAC_SUPPORTED':['api-reference/peripherals/hmac.rst'], 'SOC_ASYNC_MEMCPY_SUPPORTED':['api-reference/system/async_memcpy.rst'], 'CONFIG_IDF_TARGET_ARCH_XTENSA':XTENSA_DOCS, @@ -251,6 +256,8 @@ # Use wavedrompy as backend, insted of wavedrom-cli render_using_wavedrompy = True +smartquotes = False + # link roles config github_repo = 'espressif/esp-idf' diff --git a/docs/docs_not_updated/esp32h2.txt b/docs/docs_not_updated/esp32h2.txt deleted file mode 100644 index eab138e1bbd..00000000000 --- a/docs/docs_not_updated/esp32h2.txt +++ /dev/null @@ -1,19 +0,0 @@ -api-guides/RF_calibration -api-guides/coexist -api-guides/cplusplus -api-guides/dfu -api-guides/index -api-reference/peripherals/spi_features -api-reference/peripherals/sdio_slave -api-reference/peripherals/dedic_gpio -api-reference/peripherals/sd_pullup_requirements -api-reference/peripherals/index -api-reference/peripherals/sdmmc_host -api-reference/network/index -api-reference/system/sleep_modes -api-reference/system/power_management -api-reference/system/inc/power_management_esp32 -api-reference/system/inc/power_management_esp32s2_and_later -api-reference/protocols/esp_serial_slave_link -api-reference/protocols/esp_sdio_slave_protocol -api-reference/protocols/index diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index 5a4bec20473..90faae64ceb 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -27,40 +27,23 @@ api-guides/tools/idf-monitor.rst api-guides/tools/idf-tools-notes.inc api-guides/tools/idf-docker-image.rst api-guides/tools/index.rst -api-guides/startup.rst -api-guides/hlinterrupts.rst api-guides/RF_calibration.rst -api-guides/unit-tests.rst api-guides/deep-sleep-stub.rst -api-guides/lwip.rst api-guides/coexist.rst api-guides/flash_psram_config.rst api-guides/usb-serial-jtag-console.rst -api-guides/linker-script-generation.rst api-guides/wifi.rst api-guides/usb-otg-console.rst api-guides/wireshark-user-guide.rst -api-guides/bootloader.rst api-guides/esp-wifi-mesh.rst -api-guides/cplusplus.rst api-guides/SYSVIEW_FreeRTOS.txt -api-guides/build-system.rst api-guides/core_dump.rst -api-guides/inc/linux-host-requirements.rst api-guides/dfu.rst api-guides/current-consumption-measurement-modules.rst -api-guides/reproducible-builds.rst -api-guides/hardware-abstraction.rst api-guides/wifi-security.rst api-guides/host-apps.rst api-guides/index.rst api-guides/openthread.rst -api-guides/fatal-errors.rst -api-guides/memory-types.rst -api-guides/general-notes.rst -conf.py -api-reference/api-conventions.rst -api-reference/template.rst api-reference/provisioning/protocomm.rst api-reference/provisioning/provisioning.rst api-reference/provisioning/index.rst @@ -73,12 +56,10 @@ api-reference/storage/fatfs.rst api-reference/storage/nvs_partition_gen.rst api-reference/storage/nvs_flash.rst api-reference/storage/partition.rst -api-reference/storage/sdmmc.rst api-reference/storage/mass_mfg.rst api-reference/storage/fatfsgen.rst api-reference/storage/index.rst api-reference/storage/nvs_partition_parse.rst -api-reference/peripherals/gpio/esp32p4.inc api-reference/peripherals/adc_continuous.rst api-reference/peripherals/adc_oneshot.rst api-reference/peripherals/usb_host.rst @@ -87,12 +68,10 @@ api-reference/peripherals/usb_host/usb_host_notes_index.rst api-reference/peripherals/usb_host/usb_host_notes_dwc_otg.rst api-reference/peripherals/usb_host/usb_host_notes_design.rst api-reference/peripherals/usb_device.rst -api-reference/peripherals/gpio.rst api-reference/peripherals/dac.rst api-reference/peripherals/touch_element.rst api-reference/peripherals/lcd.rst api-reference/peripherals/ana_cmpr.rst -api-reference/peripherals/secure_element.rst api-reference/peripherals/temp_sensor.rst api-reference/peripherals/sdio_slave.rst api-reference/peripherals/clk_tree.rst @@ -111,12 +90,8 @@ api-reference/peripherals/i2c.rst api-reference/peripherals/dedic_gpio.rst api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/index.rst -api-reference/peripherals/sdmmc_host.rst api-reference/peripherals/uart.rst -api-reference/kconfig.rst api-reference/network/esp_openthread.rst -api-reference/network/esp_eth.rst -api-reference/network/esp_netif_driver.rst api-reference/network/esp_dpp.rst api-reference/network/esp_now.rst api-reference/network/esp-wifi-mesh.rst @@ -124,42 +99,23 @@ api-reference/network/esp_smartconfig.rst api-reference/network/esp_nan.rst api-reference/network/esp_wifi.rst api-reference/network/index.rst -api-reference/network/esp_netif.rst api-reference/system/sleep_modes.rst api-reference/system/ota.rst api-reference/system/app_trace.rst api-reference/system/ulp_macros.rst -api-reference/system/perfmon.rst api-reference/system/ulp-lp-core.rst api-reference/system/ulp.rst -api-reference/system/esp_function_with_shared_stack.rst api-reference/system/ulp_instruction_set.rst api-reference/system/random.rst -api-reference/system/esp_event.rst -api-reference/system/system_time.rst -api-reference/system/log.rst -api-reference/system/soc_caps.rst -api-reference/system/internal-unstable.rst -api-reference/system/app_image_format.rst -api-reference/system/himem.rst api-reference/system/power_management.rst -api-reference/system/mem_alloc.rst api-reference/system/misc_system_api.rst -api-reference/system/bootloader_image_format.rst api-reference/system/inc/power_management_esp32p4.rst -api-reference/system/heap_debug.rst api-reference/system/esp_https_ota.rst api-reference/system/ulp-risc-v.rst -api-reference/system/esp_err.rst -api-reference/system/console.rst api-reference/system/intr_alloc.rst -api-reference/system/index.rst -api-reference/system/pthread.rst -api-reference/error-codes.rst api-reference/index.rst api-reference/protocols/icmp_echo.rst api-reference/protocols/esp_serial_slave_link.rst -api-reference/protocols/mqtt.rst api-reference/protocols/mbedtls.rst api-reference/protocols/esp_http_server.rst api-reference/protocols/esp_sdio_slave_protocol.rst @@ -167,21 +123,13 @@ api-reference/protocols/esp_local_ctrl.rst api-reference/protocols/esp_crt_bundle.rst api-reference/protocols/esp_http_client.rst api-reference/protocols/esp_https_server.rst -api-reference/protocols/modbus.rst api-reference/protocols/esp_tls.rst -api-reference/protocols/mdns.rst api-reference/protocols/index.rst -api-reference/protocols/asio.rst security/host-based-security-workflows.rst security/flash-encryption.rst security/security.rst security/esp32p4_log.inc security/index.rst -migration-guides/release-5.x/5.2/protocols.rst -migration-guides/release-5.x/5.2/index.rst -migration-guides/release-5.x/5.2/peripherals.rst -migration-guides/index.rst -_templates/layout.html get-started/establish-serial-connection.rst get-started/linux-macos-setup.rst get-started/linux-macos-start-project.rst diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index 41f96611dc4..d92b07e169c 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -73,52 +73,11 @@ INPUT = \ $(PROJECT_PATH)/components/bt/host/bluedroid/api/include/api/esp_spp_api.h \ $(PROJECT_PATH)/components/bt/host/nimble/esp-hci/include/esp_nimble_hci.h \ $(PROJECT_PATH)/components/console/esp_console.h \ - $(PROJECT_PATH)/components/driver/analog_comparator/include/driver/ana_cmpr.h \ - $(PROJECT_PATH)/components/driver/analog_comparator/include/driver/ana_cmpr_etm.h \ - $(PROJECT_PATH)/components/driver/analog_comparator/include/driver/ana_cmpr_types.h \ - $(PROJECT_PATH)/components/driver/dac/include/driver/dac_continuous.h \ - $(PROJECT_PATH)/components/driver/dac/include/driver/dac_cosine.h \ - $(PROJECT_PATH)/components/driver/dac/include/driver/dac_oneshot.h \ - $(PROJECT_PATH)/components/driver/dac/include/driver/dac_types.h \ - $(PROJECT_PATH)/components/driver/i2c/include/driver/i2c_master.h \ - $(PROJECT_PATH)/components/driver/i2c/include/driver/i2c_slave.h \ - $(PROJECT_PATH)/components/driver/i2c/include/driver/i2c_types.h \ - $(PROJECT_PATH)/components/driver/i2s/include/driver/i2s_common.h \ - $(PROJECT_PATH)/components/driver/i2s/include/driver/i2s_pdm.h \ - $(PROJECT_PATH)/components/driver/i2s/include/driver/i2s_std.h \ - $(PROJECT_PATH)/components/driver/i2s/include/driver/i2s_tdm.h \ - $(PROJECT_PATH)/components/driver/i2s/include/driver/i2s_types.h \ $(PROJECT_PATH)/components/driver/ledc/include/driver/ledc.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_cap.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_cmpr.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_etm.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_fault.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_gen.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_oper.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_sync.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_timer.h \ - $(PROJECT_PATH)/components/driver/mcpwm/include/driver/mcpwm_types.h \ $(PROJECT_PATH)/components/driver/parlio/include/driver/parlio_tx.h \ $(PROJECT_PATH)/components/driver/parlio/include/driver/parlio_types.h \ - $(PROJECT_PATH)/components/driver/rmt/include/driver/rmt_common.h \ - $(PROJECT_PATH)/components/driver/rmt/include/driver/rmt_encoder.h \ - $(PROJECT_PATH)/components/driver/rmt/include/driver/rmt_rx.h \ - $(PROJECT_PATH)/components/driver/rmt/include/driver/rmt_tx.h \ - $(PROJECT_PATH)/components/driver/rmt/include/driver/rmt_types.h \ - $(PROJECT_PATH)/components/driver/sdio_slave/include/driver/sdio_slave.h \ - $(PROJECT_PATH)/components/driver/sigma_delta/include/driver/sdm.h \ - $(PROJECT_PATH)/components/driver/sdmmc/include/driver/sdmmc_default_configs.h \ - $(PROJECT_PATH)/components/driver/sdmmc/include/driver/sdmmc_host.h \ - $(PROJECT_PATH)/components/driver/sdmmc/include/driver/sdmmc_types.h \ - $(PROJECT_PATH)/components/driver/spi/include/driver/sdspi_host.h \ - $(PROJECT_PATH)/components/driver/spi/include/driver/spi_common.h \ - $(PROJECT_PATH)/components/driver/spi/include/driver/spi_master.h \ - $(PROJECT_PATH)/components/driver/spi/include/driver/spi_slave_hd.h \ - $(PROJECT_PATH)/components/driver/spi/include/driver/spi_slave.h \ - $(PROJECT_PATH)/components/driver/temperature_sensor/include/driver/temperature_sensor.h \ $(PROJECT_PATH)/components/driver/touch_sensor/include/driver/touch_sensor_common.h \ $(PROJECT_PATH)/components/driver/twai/include/driver/twai.h \ - $(PROJECT_PATH)/components/driver/uart/include/driver/uart.h \ $(PROJECT_PATH)/components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h \ $(PROJECT_PATH)/components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h \ $(PROJECT_PATH)/components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h \ @@ -133,6 +92,13 @@ INPUT = \ $(PROJECT_PATH)/components/esp_common/include/esp_check.h \ $(PROJECT_PATH)/components/esp_common/include/esp_err.h \ $(PROJECT_PATH)/components/esp_common/include/esp_idf_version.h \ + $(PROJECT_PATH)/components/esp_driver_ana_cmpr/include/driver/ana_cmpr.h \ + $(PROJECT_PATH)/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_etm.h \ + $(PROJECT_PATH)/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h \ + $(PROJECT_PATH)/components/esp_driver_dac/include/driver/dac_continuous.h \ + $(PROJECT_PATH)/components/esp_driver_dac/include/driver/dac_cosine.h \ + $(PROJECT_PATH)/components/esp_driver_dac/include/driver/dac_oneshot.h \ + $(PROJECT_PATH)/components/esp_driver_dac/include/driver/dac_types.h \ $(PROJECT_PATH)/components/esp_driver_gpio/include/driver/dedic_gpio.h \ $(PROJECT_PATH)/components/esp_driver_gpio/include/driver/gpio.h \ $(PROJECT_PATH)/components/esp_driver_gpio/include/driver/gpio_etm.h \ @@ -142,7 +108,42 @@ INPUT = \ $(PROJECT_PATH)/components/esp_driver_gptimer/include/driver/gptimer.h \ $(PROJECT_PATH)/components/esp_driver_gptimer/include/driver/gptimer_etm.h \ $(PROJECT_PATH)/components/esp_driver_gptimer/include/driver/gptimer_types.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_cmpr.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_etm.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_fault.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_gen.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_oper.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_sync.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_timer.h \ + $(PROJECT_PATH)/components/esp_driver_mcpwm/include/driver/mcpwm_types.h \ + $(PROJECT_PATH)/components/esp_driver_i2c/include/driver/i2c_master.h \ + $(PROJECT_PATH)/components/esp_driver_i2c/include/driver/i2c_slave.h \ + $(PROJECT_PATH)/components/esp_driver_i2c/include/driver/i2c_types.h \ + $(PROJECT_PATH)/components/esp_driver_i2s/include/driver/i2s_common.h \ + $(PROJECT_PATH)/components/esp_driver_i2s/include/driver/i2s_pdm.h \ + $(PROJECT_PATH)/components/esp_driver_i2s/include/driver/i2s_std.h \ + $(PROJECT_PATH)/components/esp_driver_i2s/include/driver/i2s_tdm.h \ + $(PROJECT_PATH)/components/esp_driver_i2s/include/driver/i2s_types.h \ $(PROJECT_PATH)/components/esp_driver_pcnt/include/driver/pulse_cnt.h \ + $(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_common.h \ + $(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_encoder.h \ + $(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_rx.h \ + $(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_tx.h \ + $(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_types.h \ + $(PROJECT_PATH)/components/esp_driver_sdio/include/driver/sdio_slave.h \ + $(PROJECT_PATH)/components/esp_driver_sdm/include/driver/sdm.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_host.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_types.h \ + $(PROJECT_PATH)/components/esp_driver_sdspi/include/driver/sdspi_host.h \ + $(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_common.h \ + $(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_master.h \ + $(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_slave_hd.h \ + $(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_slave.h \ + $(PROJECT_PATH)/components/esp_driver_tsens/include/driver/temperature_sensor.h \ + $(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart.h \ + $(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart_vfs.h \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth_com.h \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth_driver.h \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth_mac.h \ @@ -265,6 +266,7 @@ INPUT = \ $(PROJECT_PATH)/components/lwip/include/apps/esp_sntp.h \ $(PROJECT_PATH)/components/lwip/include/apps/ping/ping_sock.h \ $(PROJECT_PATH)/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h \ + $(PROJECT_PATH)/components/mbedtls/port/include/ecdsa/ecdsa_alt.h \ $(PROJECT_PATH)/components/mqtt/esp-mqtt/include/mqtt_client.h \ $(PROJECT_PATH)/components/nvs_flash/include/nvs_flash.h \ $(PROJECT_PATH)/components/nvs_flash/include/nvs.h \ @@ -278,9 +280,11 @@ INPUT = \ $(PROJECT_PATH)/components/protocomm/include/security/protocomm_security.h \ $(PROJECT_PATH)/components/protocomm/include/security/protocomm_security0.h \ $(PROJECT_PATH)/components/protocomm/include/security/protocomm_security1.h \ + $(PROJECT_PATH)/components/protocomm/include/security/protocomm_security2.h \ $(PROJECT_PATH)/components/protocomm/include/transports/protocomm_ble.h \ $(PROJECT_PATH)/components/protocomm/include/transports/protocomm_console.h \ $(PROJECT_PATH)/components/protocomm/include/transports/protocomm_httpd.h \ + $(PROJECT_PATH)/components/protocomm/include/crypto/srp6a/esp_srp.h \ $(PROJECT_PATH)/components/pthread/include/esp_pthread.h \ $(PROJECT_PATH)/components/sdmmc/include/sdmmc_cmd.h \ $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/adc_channel.h \ diff --git a/docs/doxygen/Doxyfile_esp32p4 b/docs/doxygen/Doxyfile_esp32p4 index 910f295a01f..a2f272484f4 100644 --- a/docs/doxygen/Doxyfile_esp32p4 +++ b/docs/doxygen/Doxyfile_esp32p4 @@ -1 +1,10 @@ INPUT += \ + $(PROJECT_PATH)/components/ulp/lp_core/include/lp_core_i2c.h \ + $(PROJECT_PATH)/components/ulp/lp_core/include/lp_core_uart.h \ + $(PROJECT_PATH)/components/ulp/lp_core/include/ulp_lp_core.h \ + $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h \ + $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h \ + $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_print.h \ + $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h \ + $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h \ + $(PROJECT_PATH)/components/ulp/ulp_common/include/ulp_common.h \ diff --git a/docs/en/COPYRIGHT.rst b/docs/en/COPYRIGHT.rst index d9e29466aeb..8f022e98adb 100644 --- a/docs/en/COPYRIGHT.rst +++ b/docs/en/COPYRIGHT.rst @@ -67,6 +67,12 @@ These third party libraries can be included into the application (firmware) prod * `SEGGER SystemView`_ target-side library, Copyright (c) 1995-2021 SEGGER Microcontroller GmbH, is licensed under BSD 1-clause license. +* `protobuf-c`_ Protocol Buffers implementation in C, Copyright (c) 2008-2022, Dave Benson and the protobuf-c authors. For details please check :component_file:`LICENSE file `. + +* `CMock`_ Mock/stub generator for C, Copyright (c) 2007-14 Mike Karlesky, Mark VanderVoord, Greg Williams, is licensed under MIT license as described in :component_file:`LICENSE file `. + +* `Unity`_ Simple Unit Testing library, Copyright (c) 2007-23 Mike Karlesky, Mark VanderVoord, Greg Williams, is licensed under MIT license as described in :component_file:`LICENSE file `. + Documentation ------------- @@ -165,6 +171,9 @@ Copyright (C) 2011, ChaN, all right reserved. .. _OpenBSD SD/MMC driver: https://github.com/openbsd/src/blob/f303646/sys/dev/sdmmc/sdmmc.c .. _Mbed TLS: https://github.com/Mbed-TLS/mbedtls .. _spiffs: https://github.com/pellepl/spiffs +.. _CMock: https://github.com/ThrowTheSwitch/CMock +.. _protobuf-c: https://github.com/protobuf-c/protobuf-c +.. _Unity: https://github.com/ThrowTheSwitch/Unity .. _asio: https://github.com/chriskohlhoff/asio .. _mqtt: https://github.com/espressif/esp-mqtt .. _zephyr: https://github.com/zephyrproject-rtos/zephyr diff --git a/docs/en/api-guides/app_trace.rst b/docs/en/api-guides/app_trace.rst index 90ee9efd4f0..1507f0d8d73 100644 --- a/docs/en/api-guides/app_trace.rst +++ b/docs/en/api-guides/app_trace.rst @@ -420,7 +420,7 @@ Data Visualization After trace data are collected, users can use a special tool to visualize the results and inspect behavior of the program. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES Unfortunately, SystemView does not support tracing from multiple cores. So when tracing from {IDF_TARGET_NAME} with JTAG interfaces in the dual-core mode, two files are generated: one for PRO CPU and another for APP CPU. Users can load each file into separate instances of the tool. For tracing over UART, users can select ``Component config`` > ``Application Level Tracing`` > ``FreeRTOS SystemView Tracing`` in menuconfig Pro or App to choose which CPU has to be traced. @@ -432,7 +432,7 @@ Good instructions on how to install, configure, and visualize data in Impulse fr ESP-IDF uses its own mapping for SystemView FreeRTOS events IDs, so users need to replace the original file mapping ``$SYSVIEW_INSTALL_DIR/Description/SYSVIEW_FreeRTOS.txt`` with ``$IDF_PATH/tools/esp_app_trace/SYSVIEW_FreeRTOS.txt``. Also, contents of that ESP-IDF-specific file should be used when configuring SystemView serializer using the above link. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES Configure Impulse for Dual Core Traces ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/en/api-guides/bootloader.rst b/docs/en/api-guides/bootloader.rst index 86d3061d4f9..a28a74ac36c 100644 --- a/docs/en/api-guides/bootloader.rst +++ b/docs/en/api-guides/bootloader.rst @@ -3,8 +3,6 @@ Bootloader :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} - The ESP-IDF Software Bootloader performs the following functions: 1. Minimal initial configuration of internal modules; @@ -12,7 +10,7 @@ The ESP-IDF Software Bootloader performs the following functions: 3. Select the application partition to boot, based on the partition table and ota_data (if any); 4. Load this image to RAM (IRAM & DRAM) and transfer management to the image that was just loaded. -Bootloader is located at the address {IDF_TARGET_BOOTLOADER_OFFSET} in the flash. +Bootloader is located at the address {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} in the flash. For a full description of the startup process including the ESP-IDF bootloader, see :doc:`startup`. @@ -95,10 +93,10 @@ In addition, the following configuration options control the reset condition: .. only:: SOC_RTC_FAST_MEM_SUPPORTED If an application needs to know if the factory reset has occurred, users can call the function :cpp:func:`bootloader_common_get_rtc_retain_mem_factory_reset_state`. - + - If the status is read as true, the function will return the status, indicating that the factory reset has occurred. The function then resets the status to false for subsequent factory reset judgement. - If the status is read as false, the function will return the status, indicating that the factory reset has not occurred, or the memory where this status is stored is invalid. - + Note that this feature reserves some RTC FAST memory (the same size as the :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` feature). .. only:: not SOC_RTC_FAST_MEM_SUPPORTED diff --git a/docs/en/api-guides/build-system.rst b/docs/en/api-guides/build-system.rst index a9603b9a6ec..de708a7834a 100644 --- a/docs/en/api-guides/build-system.rst +++ b/docs/en/api-guides/build-system.rst @@ -361,6 +361,7 @@ The following are some project/build variables that are available as build prope * If :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` option is set, the value of :ref:`CONFIG_APP_PROJECT_VER` will be used. * Else, if ``PROJECT_VER`` variable is set in project CMakeLists.txt file, its value will be used. * Else, if the ``PROJECT_DIR/version.txt`` exists, its contents will be used as ``PROJECT_VER``. + * Else, if ``VERSION`` argument is passed to the ``project()`` call in the CMakeLists.txt file as ``project(... VERSION x.y.z.w )`` then it will be used as ``PROJECT_VER``. The ``VERSION`` argument must be compilant with the `cmake standard `_. * Else, if the project is located inside a Git repository, the output of git description will be used. * Otherwise, ``PROJECT_VER`` will be "1". - ``EXTRA_PARTITION_SUBTYPES``: CMake list of extra partition subtypes. Each subtype description is a comma-separated string with ``type_name, subtype_name, numeric_value`` format. Components may add new subtypes by appending them to this list. @@ -709,8 +710,6 @@ This is an equivalent to ``project_include.cmake`` for :ref:`component-configura Take care when adding configuration values in this file, as they will be included across the entire project configuration. Where possible, it's generally better to create a KConfig file for :ref:`component-configuration`. -``project_include.cmake`` files are used inside ESP-IDF, for defining project-wide build features such as ``esptool.py`` command line arguments and the ``bootloader`` "special app". - Wrappers to Redefine or Extend Existing Functions ------------------------------------------------- diff --git a/docs/en/api-guides/c.rst b/docs/en/api-guides/c.rst new file mode 100644 index 00000000000..50f50e52af2 --- /dev/null +++ b/docs/en/api-guides/c.rst @@ -0,0 +1,36 @@ +C Support +=========== + +:link_to_translation:`zh_CN:[中文]` + +.. highlight:: cpp + +ESP-IDF is primarily written in C and provides C APIs. `Newlib `_ is used as standard C library (the Newlib version can be found in :component_file:`newlib/sbom.yml`). In general, all C features supported by the compiler, currently GCC, should be available in ESP-IDF, unless specified in :ref:`unsupported_c_features` below. + +.. _c_version: + +C Version +--------- + +**GNU dialect of ISO C17** (``--std=gnu17``) is the current default C version in ESP-IDF. + +To compile the source code of a certain component using a different language standard, set the desired compiler flag in the component's ``CMakeLists.txt`` file: + +.. code-block:: cmake + + idf_component_register( ... ) + target_compile_options(${COMPONENT_LIB} PRIVATE -std=gnu11) + +If the public header files of the component also need to be compiled with the same language standard, replace the flag ``PRIVATE`` with ``PUBLIC``. + +.. _unsupported_c_features: + +Unsupported C Features +---------------------- + +The following features are not supported in ESP-IDF. + +Nested Function Pointers +^^^^^^^^^^^^^^^^^^^^^^^^ + +The **GNU dialect of ISO C17** supports `nested functions `_. However, they do not work in ESP-IDF when referenced as function pointer because the compiler generates a trampoline on the stack, while the stack is not executable in ESP-IDF. Hence, do not use function pointers to nested functions. diff --git a/docs/en/api-guides/coexist.rst b/docs/en/api-guides/coexist.rst index 328af6b762e..d0a626097a6 100644 --- a/docs/en/api-guides/coexist.rst +++ b/docs/en/api-guides/coexist.rst @@ -6,7 +6,7 @@ RF Coexistence Overview --------------- -{IDF_TARGET_NAME} has only one 2.4 GHz ISM band RF module, which is shared by Bluetooth (BT & BLE) and Wi-Fi, so Bluetooth can't receive or transmit data while Wi-Fi is receiving or transmitting data and vice versa. Under such circumstances, {IDF_TARGET_NAME} uses the time-division multiplexing method to receive and transmit packets. +ESP boards now support three modules: Bluetooth (BT & BLE), IEEE802.15.4, and Wi-Fi. Each type of board has only one 2.4 GHz ISM band RF module, shared by two or three modules. Consequently, a module cannot receive or transmit data while another module is engaged in data transmission or reception. In such scenarios, {IDF_TARGET_NAME} employs the time-division multiplexing method to manage the reception and transmission of packets. Supported Coexistence Scenario for {IDF_TARGET_NAME} @@ -69,6 +69,24 @@ Supported Coexistence Scenario for {IDF_TARGET_NAME} | | |TX |Y |Y |Y |Y |Y | +-------+--------+-----------+--------+-------------+-----+----------+-----------+ +.. only:: SOC_IEEE802154_SUPPORTED + + .. table:: Supported Features of Thread (IEEE802.15.4) and BLE Coexistence + + +--------+-----------------+-----+------------+-----------+----------+ + | |BLE | + + +-----+------------+-----------+----------+ + | |Scan |Advertising |Connecting |Connected | + +--------+-----------------+-----+------------+-----------+----------+ + | Thread |Scan |X |Y |Y |Y | + + +-----------------+-----+------------+-----------+----------+ + | |Connecting |X |Y |Y |Y | + + +-----------------+-----+------------+-----------+----------+ + | |Connected |X |Y |Y |Y | + + +-----------------+-----+------------+-----------+----------+ + | |Connected | | | | | + | |(high throughput)|X |C1 |C1 |C1 | + +--------+-----------------+-----+------------+-----------+----------+ .. note:: @@ -131,6 +149,9 @@ Coexistence Period and Time Slice Wi-Fi and BLE have their fixed time slice to use the RF. In the Wi-Fi time slice, Wi-Fi will send a higher priority request to the coexistence arbitration module. Similarly, BLE can enjoy higher priority at their own time slice. The duration of the coexistence period and the proportion of each time slice are divided into four categories according to the Wi-Fi status: +.. only:: SOC_IEEE802154_SUPPORTED + + Currently, the only supported strategy ensures that the priority of BLE always takes precedence over IEEE802.15.4. .. list:: @@ -154,8 +175,7 @@ According to the coexistence logic, different coexistence periods and time slice Dynamic Priority """""""""""""""""""""""""""" -The coexistence module assigns different priorities to different status of Wi-Fi and Bluetooth. And the priority for each status is dynamic. For example, in every N BLE Advertising events, there is always one event with high priority. If a high-priority BLE Advertising event occurs within the Wi-Fi time slice, the right to use the RF may be preempted by BLE. - +The coexistence module assigns varying priorities to different statuses of each module, and these priorities are dynamic. For example, in every N BLE Advertising events, there is always one event with high priority. If a high-priority BLE Advertising event occurs within the Wi-Fi time slice, the right to use the RF may be preempted by BLE. .. only:: SOC_WIFI_SUPPORTED @@ -231,4 +251,4 @@ Setting Coexistence Compile-time Options .. note:: - Since the coexistence configuration option depends on the Bluetooth configuration option, please turn on the Bluetooth configuration option first before configuring the coexistence feature in the Wi-Fi configuration option. + As the coexistence configuration option relies on the presence of any two enabled modules, please ensure that both modules are activated before configuring any coexistence features. diff --git a/docs/en/api-guides/deep-sleep-stub.rst b/docs/en/api-guides/deep-sleep-stub.rst index b7440ffc3e0..d5f4f50fdad 100644 --- a/docs/en/api-guides/deep-sleep-stub.rst +++ b/docs/en/api-guides/deep-sleep-stub.rst @@ -78,7 +78,7 @@ The first way is to use the ``RTC_DATA_ATTR`` and ``RTC_RODATA_ATTR`` to specify .. only:: SOC_RTC_SLOW_MEM_SUPPORTED - The RTC memory area where this data will be placed can be configured via menuconfig option named ``CONFIG_{IDF_TARGET_CFG_PREFIX}_RTCDATA_IN_FAST_MEM``. This option allows to keep slow memory area for ULP programs and once it is enabled the data marked with ``RTC_DATA_ATTR`` and ``RTC_RODATA_ATTR`` are placed in the RTC fast memory segment otherwise it goes to RTC slow memory (default option). This option depends on the ``CONFIG_FREERTOS_UNICORE`` because RTC fast memory can be accessed only by PRO_CPU. + The RTC memory area where this data will be placed can be configured via menuconfig option named ``CONFIG_{IDF_TARGET_CFG_PREFIX}_RTCDATA_IN_FAST_MEM``. This option allows to keep slow memory area for ULP programs and once it is enabled the data marked with ``RTC_DATA_ATTR`` and ``RTC_RODATA_ATTR`` are placed in the RTC fast memory segment otherwise it goes to RTC slow memory (default option). This option depends on the :ref:`CONFIG_FREERTOS_UNICORE` option because RTC fast memory can be accessed only by PRO_CPU. The attributes ``RTC_FAST_ATTR`` and ``RTC_SLOW_ATTR`` can be used to specify data that will be force placed into RTC_FAST and RTC_SLOW memory respectively. Any access to data marked with ``RTC_FAST_ATTR`` is allowed by PRO_CPU only and it is responsibility of user to make sure about it. diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst index b851cdb7f7e..1b6c6dcf00a 100644 --- a/docs/en/api-guides/external-ram.rst +++ b/docs/en/api-guides/external-ram.rst @@ -24,7 +24,16 @@ Hardware .. note:: - Some PSRAM chips are 1.8 V devices and some are 3.3 V. The working voltage of the PSRAM chip must match the working voltage of the flash component. Consult the datasheet for your PSRAM chip and {IDF_TARGET_NAME} device to find out the working voltages. For a 1.8 V PSRAM chip, make sure to either set the MTDI pin to a high signal level on bootup, or program {IDF_TARGET_NAME} eFuses to always use the VDD_SIO level of 1.8 V. Not doing this can damage the PSRAM and/or flash chip. + .. only:: esp32 or esp32s2 or esp32s3 + + Some PSRAM chips are 1.8 V devices and some are 3.3 V. The working voltage of the PSRAM chip must match the working voltage of the flash component. Consult the datasheet for your PSRAM chip and {IDF_TARGET_NAME} device to find out the working voltages. For a 1.8 V PSRAM chip, make sure to either set the MTDI pin to a high signal level on bootup, or program {IDF_TARGET_NAME} eFuses to always use the VDD_SIO level of 1.8 V. Not doing this can damage the PSRAM and/or flash chip. + + .. only:: esp32p4 + + Some PSRAM chips are 1.8 V devices and some are 3.3 V. Consult the datasheet for your PSRAM chip and {IDF_TARGET_NAME} device to find out the working voltages. + + By default PSRAM is powered up by the on-chip LDO2, you can use :ref:`CONFIG_SPIRAM_LDO_ID` to switch the LDO ID according. Setting this value to -1 for using external power supply. + By default PSRAM connected LDO is set to correct voltage according to the used Espressif module. You can still use :ref:`CONFIG_SPIRAM_LDO_VOLTAGE_MV` to select LDO output voltage if you do not use an Espressif module. When using external power supply, this option does not exist. .. note:: diff --git a/docs/en/api-guides/fatal-errors.rst b/docs/en/api-guides/fatal-errors.rst index 7a7b18580ac..ee23dd15679 100644 --- a/docs/en/api-guides/fatal-errors.rst +++ b/docs/en/api-guides/fatal-errors.rst @@ -282,7 +282,7 @@ The GDB prompt can be used to inspect CPU registers, local and static variables, RTC Watchdog Timeout -------------------- -{IDF_TARGET_RTCWDT_RTC_RESET:default="Not updated", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS"} +{IDF_TARGET_RTCWDT_RTC_RESET:default="Not updated", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS", esp32p4="LP_WDT_SYS"} The RTC watchdog is used in the startup code to keep track of execution time and it also helps to prevent a lock-up caused by an unstable power source. It is enabled by default (see :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`). If the execution time is exceeded, the RTC watchdog will restart the system. In this case, the ROM bootloader will print a message with the ``RTC Watchdog Timeout`` reason for the reboot. diff --git a/docs/en/api-guides/index.rst b/docs/en/api-guides/index.rst index 19990f593ff..c3ceeeb0583 100644 --- a/docs/en/api-guides/index.rst +++ b/docs/en/api-guides/index.rst @@ -12,8 +12,9 @@ API Guides bootloader build-system :SOC_SUPPORT_COEXISTENCE: coexist - core_dump + c cplusplus + core_dump current-consumption-measurement-modules :SOC_RTC_MEM_SUPPORTED: deep-sleep-stub :SOC_USB_OTG_SUPPORTED: dfu @@ -42,3 +43,4 @@ API Guides :SOC_USB_SERIAL_JTAG_SUPPORTED: usb-serial-jtag-console :SOC_WIFI_SUPPORTED: wifi :SOC_WIFI_SUPPORTED: wifi-security + low-power-mode diff --git a/docs/en/api-guides/linker-script-generation.rst b/docs/en/api-guides/linker-script-generation.rst index 1104101ef5b..40e1d9d2b56 100644 --- a/docs/en/api-guides/linker-script-generation.rst +++ b/docs/en/api-guides/linker-script-generation.rst @@ -603,14 +603,3 @@ Then the corresponding excerpt from the generated linker script will be as follo Rule generated from the default scheme entry ``iram -> iram0_text``. Since the default scheme specifies an ``iram -> iram0_text`` entry, it too is placed wherever ``iram0_text`` is referenced by a marker. Since it is a rule generated from the default scheme, it comes first among all other rules collected under the same target name. The linker script template currently used is :component_file:`esp_system/ld/{IDF_TARGET_PATH_NAME}/sections.ld.in`; the generated output script ``sections.ld`` is put under its build directory. - -.. _ldgen-migrate-lf-grammar : - -Migrate to ESP-IDF v5.0 Linker Script Fragment Files Grammar -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The old grammar supported in ESP-IDF v3.x would be dropped in ESP-IDF v5.0. Here are a few notes on how to migrate properly: - -1. Now indentation is enforced and improperly indented fragment files would generate a runtime parse exception. This was not enforced in the old version but previous documentation and examples demonstrate properly indented grammar. -2. Migrate the old condition entry to the ``if...elif...else`` structure for conditionals. You can refer to the :ref:`earlier chapter ` for detailed grammar. -3. mapping fragments now requires a name like other fragment types. diff --git a/docs/en/api-guides/low-power-mode.rst b/docs/en/api-guides/low-power-mode.rst new file mode 100644 index 00000000000..cefab6cc239 --- /dev/null +++ b/docs/en/api-guides/low-power-mode.rst @@ -0,0 +1,7 @@ +Low Power Mode User Guide +========================== + + +:link_to_translation:`zh_CN:[中文]` + +The document has not been translated into English yet. In the meantime, please refer to the Chinese version. \ No newline at end of file diff --git a/docs/en/api-guides/lwip.rst b/docs/en/api-guides/lwip.rst index 2464e48af93..58fef8a3e01 100644 --- a/docs/en/api-guides/lwip.rst +++ b/docs/en/api-guides/lwip.rst @@ -13,6 +13,8 @@ ESP-IDF supports the following lwIP TCP/IP stack functions: - `BSD Sockets API`_ - `Netconn API`_ is enabled but not officially supported for ESP-IDF applications +.. _lwip-dns-limitation: + Adapted APIs ^^^^^^^^^^^^ @@ -23,6 +25,12 @@ Adapted APIs Some common lwIP app APIs are supported indirectly by ESP-IDF: - Dynamic Host Configuration Protocol (DHCP) Server & Client are supported indirectly via the :doc:`/api-reference/network/esp_netif` functionality. +- Domain Name System (DNS) is supported in lwIP; DNS servers could be assigned automatically when acquiring a DHCP address, or manually configured using the :doc:`/api-reference/network/esp_netif` API. + +.. note:: + + DNS server configuration in lwIP is global, not interface-specific. If you are using multiple network interfaces with distinct DNS servers, exercise caution to prevent inadvertent overwrites of one interface's DNS settings when acquiring a DHCP lease from another interface. + - Simple Network Time Protocol (SNTP) is also supported via the :doc:`/api-reference/network/esp_netif`, or directly via the :component_file:`lwip/include/apps/esp_sntp.h` functions, which also provide thread-safe API to :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` functions, see also :ref:`system-time-sntp-sync`. - ICMP Ping is supported using a variation on the lwIP ping API, see :doc:`/api-reference/protocols/icmp_echo`. - ICMPv6 Ping, supported by lwIP's ICMPv6 Echo API, is used to test IPv6 network connectivity. For more information, see :example:`protocols/sockets/icmpv6_ping`. @@ -411,6 +419,8 @@ IP Layer Features - IPV4-mapped IPV6 addresses are supported +.. _lwip-custom-hooks: + Customized lwIP Hooks +++++++++++++++++++++ @@ -422,10 +432,25 @@ The original lwIP supports implementing custom compile-time modifications via `` target_compile_options(${lwip} PRIVATE "-I${PROJECT_DIR}/main") target_compile_definitions(${lwip} PRIVATE "-DESP_IDF_LWIP_HOOK_FILENAME=\"my_hook.h\"") +Customized lwIP Options From ESP-IDF Build System +++++++++++++++++++++++++++++++++++++++++++++++++++ + +The most common lwIP options are configurable through the component configuration menu. However, certain definitions need to be injected from the command line. The CMake function ``target_compile_definitions()`` can be employed to define macros, as illustrated below: + +.. code-block:: cmake + + idf_component_get_property(lwip lwip COMPONENT_LIB) + target_compile_definitions(${lwip} PRIVATE "-DETHARP_SUPPORT_VLAN=1") + +This approach may not work for function-like macros, as there is no guarantee that the definition will be accepted by all compilers, although it is supported in GCC. To address this limitation, the ``add_definitions()`` function can be utilized to define the macro for the entire project, for example: ``add_definitions("-DFALLBACK_DNS_SERVER_ADDRESS(addr)=\"IP_ADDR4((addr), 8,8,8,8)\"")``. + +Alternatively, you can define your function-like macro in a header file which will be pre-included as an lwIP hook file, see :ref:`lwip-custom-hooks`. Limitations ^^^^^^^^^^^ +ESP-IDF additions to lwIP still suffer from the global DNS limitation, described in :ref:`lwip-dns-limitation`. To address this limitation from application code, the ``FALLBACK_DNS_SERVER_ADDRESS()`` macro can be utilized to define a global DNS fallback server accessible from all interfaces. Alternatively, you have the option to maintain per-interface DNS servers and reconfigure them whenever the default interface changes. + Calling ``send()`` or ``sendto()`` repeatedly on a UDP socket may eventually fail with ``errno`` equal to ``ENOMEM``. This failure occurs due to the limitations of buffer sizes in the lower-layer network interface drivers. If all driver transmit buffers are full, the UDP transmission will fail. For applications that transmit a high volume of UDP datagrams and aim to avoid any dropped datagrams by the sender, it is advisable to implement error code checking and employ a retransmission mechanism with a short delay. .. only:: esp32 @@ -446,9 +471,7 @@ TCP/IP performance is a complex subject, and performance can be optimized toward Maximum Throughput ^^^^^^^^^^^^^^^^^^ -Espressif tests ESP-IDF TCP/IP throughput using the :example:`wifi/iperf` example in an RF-sealed enclosure. - -The :example_file:`wifi/iperf/sdkconfig.defaults` file for the iperf example contains settings known to maximize TCP/IP throughput, usually at the expense of higher RAM usage. To get maximum TCP/IP throughput in an application at the expense of other factors, it is suggested to apply settings from this file into the project sdkconfig. +Espressif tests ESP-IDF TCP/IP throughput using the iperf test application: https://iperf.fr/, please refer to :ref:`improve-network-speed` for more details about the actual testing and using the optimized configuration. .. important:: diff --git a/docs/en/api-guides/memory-types.rst b/docs/en/api-guides/memory-types.rst index f2ae0dc9d53..d56d6264ab5 100644 --- a/docs/en/api-guides/memory-types.rst +++ b/docs/en/api-guides/memory-types.rst @@ -184,6 +184,14 @@ The ``DRAM_ATTR`` attribute can be used to force constants from DROM into the :r Remaining RTC FAST memory is added to the heap unless the option :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` is disabled. This memory can be used interchangeably with :ref:`DRAM`, but is slightly slower to access. +.. only:: SOC_MEM_TCM_SUPPORTED + + TCM (Tightly-Coupled Memory) + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + TCM is memory placed near the CPU, accessible at CPU frequency without passing through a cache. Even though on average, it may not surpass the efficiency or speed of cached memory, it does provide predictable and consistent access times. TCM can be useful for time-critical routines where having a deterministic access speed is important. + + DMA-Capable Requirement ^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-guides/partition-tables.rst b/docs/en/api-guides/partition-tables.rst index d096aa9eac8..2c601542f35 100644 --- a/docs/en/api-guides/partition-tables.rst +++ b/docs/en/api-guides/partition-tables.rst @@ -150,16 +150,19 @@ Extra Partition SubTypes A component can define a new partition subtype by setting the ``EXTRA_PARTITION_SUBTYPES`` property. This property is a CMake list, each entry of which is a comma separated string with ``, , `` format. The build system uses this property to add extra subtypes and creates fields named ``ESP_PARTITION_SUBTYPE__`` in :cpp:type:`esp_partition_subtype_t`. The project can use this subtype to define partitions in the partitions table CSV file and use the new fields in :cpp:type:`esp_partition_subtype_t`. +.. _partition-offset-and-size: + Offset & Size ~~~~~~~~~~~~~ -The offset represents the partition address in the SPI flash, which sector size is 0x1000 (4 KB). Thus, the offset must be a multiple of 4 KB. - -Partitions with blank offsets in the CSV file will start after the previous partition, or after the partition table in the case of the first partition. - -Partitions of type ``app`` have to be placed at offsets aligned to 0x10000 (64 K). If you leave the offset field blank, ``gen_esp32part.py`` will automatically align the partition. If you specify an unaligned offset for an app partition, the tool will return an error. +.. list:: -Sizes and offsets can be specified as decimal numbers, hex numbers with the prefix 0x, or size multipliers K or M (1024 and 1024*1024 bytes). + - The offset represents the partition address in the SPI flash, which sector size is 0x1000 (4 KB). Thus, the offset must be a multiple of 4 KB. + - Partitions with blank offsets in the CSV file will start after the previous partition, or after the partition table in the case of the first partition. + - Partitions of type ``app`` have to be placed at offsets aligned to 0x10000 (64 KB). If you leave the offset field blank, ``gen_esp32part.py`` will automatically align the partition. If you specify an unaligned offset for an ``app`` partition, the tool will return an error. + - Partitions of type ``app`` should have the size aligned to the flash sector size (4 KB). If you specify an unaligned size for an ``app`` partition, the tool will return an error. + :SOC_SECURE_BOOT_V1: - If Secure Boot V1 is enabled, then the partition of type ``app`` needs to have size aligned to 0x10000 (64 KB) boundary. + - Sizes and offsets can be specified as decimal numbers, hex numbers with the prefix 0x, or size multipliers K or M (1024 and 1024*1024 bytes). If you want the partitions in the partition table to work relative to any placement (:ref:`CONFIG_PARTITION_TABLE_OFFSET`) of the table itself, leave the offset field (in CSV file) for all partitions blank. Similarly, if changing the partition table offset then be aware that all blank partition offsets may change to match, and that any fixed offsets may now collide with the partition table (causing an error). diff --git a/docs/en/api-guides/performance/speed.rst b/docs/en/api-guides/performance/speed.rst index 23eed563dee..017707144e6 100644 --- a/docs/en/api-guides/performance/speed.rst +++ b/docs/en/api-guides/performance/speed.rst @@ -54,7 +54,7 @@ Executing the target multiple times can help average out factors, e.g., RTOS con - It is also possible to use the standard Unix ``gettimeofday()`` and ``utime()`` functions, although the overhead is slightly higher. - Otherwise, including ``hal/cpu_hal.h`` and calling the HAL function ``cpu_hal_get_cycle_count()`` returns the number of CPU cycles executed. This function has lower overhead than the others, which is good for measuring very short execution times with high precision. - .. only:: not CONFIG_FREERTOS_UNICORE + .. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES The CPU cycles are counted per-core, so only use this method from an interrupt handler, or a task that is pinned to a single core. @@ -159,7 +159,7 @@ Common priorities are: .. Note: the following two lists should be kept the same, but the second list also shows CPU affinities -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES .. list:: @@ -176,7 +176,7 @@ Common priorities are: - If using the :doc:`/api-reference/protocols/mqtt` component, it creates a task with default priority 5 (:ref:`configurable`), depending on :ref:`CONFIG_MQTT_USE_CUSTOM_CONFIG`, and also configurable at runtime by ``task_prio`` field in the :cpp:class:`esp_mqtt_client_config_t`) - To see what is the task priority for ``mDNS`` service, please check `Performance Optimization `__. -.. only :: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES .. list:: @@ -204,11 +204,11 @@ Common priorities are: Choosing Task Priorities of the Application ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES In general, it is not recommended to set task priorities higher than the built-in {IDF_TARGET_RF_TYPE} operations as starving them of CPU may make the system unstable. For very short timing-critical operations that do not use the network, use an ISR or a very restricted task (with very short bursts of runtime only) at the highest priority (24). Choosing priority 19 allows lower-layer {IDF_TARGET_RF_TYPE} functionality to run without delays, but still preempts the lwIP TCP/IP stack and other less time-critical internal functionality - this is the best option for time-critical tasks that do not perform network operations. Any task that does TCP/IP network operations should run at a lower priority than the lwIP TCP/IP task (18) to avoid priority-inversion issues. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES With a few exceptions, most importantly the lwIP TCP/IP task, in the default configuration most built-in tasks are pinned to Core 0. This makes it quite easy for the application to place high priority tasks on Core 1. Using priority 19 or higher guarantees that an application task can run on Core 1 without being preempted by any built-in task. To further isolate the tasks running on each CPU, configure the :ref:`lwIP task ` to only run on Core 0 instead of either core, which may reduce total TCP/IP throughput depending on what other tasks are running. @@ -234,19 +234,21 @@ To obtain the best performance for a particular interrupt handler: .. list:: - Assign more important interrupts a higher priority using a flag such as ``ESP_INTR_FLAG_LEVEL2`` or ``ESP_INTR_FLAG_LEVEL3`` when calling :cpp:func:`esp_intr_alloc`. - :not CONFIG_FREERTOS_UNICORE: - Assign the interrupt on a CPU where built-in {IDF_TARGET_RF_TYPE} tasks are not configured to run, which means assigning the interrupt on Core 1 by default, see :ref:`built-in-task-priorities`. Interrupts are assigned on the same CPU where the :cpp:func:`esp_intr_alloc` function call is made. + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - Assign the interrupt on a CPU where built-in {IDF_TARGET_RF_TYPE} tasks are not configured to run, which means assigning the interrupt on Core 1 by default, see :ref:`built-in-task-priorities`. Interrupts are assigned on the same CPU where the :cpp:func:`esp_intr_alloc` function call is made. - If you are sure the entire interrupt handler can run from IRAM (see :ref:`iram-safe-interrupt-handlers`) then set the ``ESP_INTR_FLAG_IRAM`` flag when calling :cpp:func:`esp_intr_alloc` to assign the interrupt. This prevents it being temporarily disabled if the application firmware writes to the internal SPI flash. - Even if the interrupt handler is not IRAM-safe, if it is going to be executed frequently then consider moving the handler function to IRAM anyhow. This minimizes the chance of a flash cache miss when the interrupt code is executed (see :ref:`speed-targeted-optimizations`). It is possible to do this without adding the ``ESP_INTR_FLAG_IRAM`` flag to mark the interrupt as IRAM-safe, if only part of the handler is guaranteed to be in IRAM. +.. _improve-network-speed: + Improving Network Speed ----------------------- .. list:: :SOC_WIFI_SUPPORTED: * For Wi-Fi, see :ref:`How-to-improve-Wi-Fi-performance` and :ref:`wifi-buffer-usage` - * For lwIP TCP/IP (Wi-Fi and Ethernet), see :ref:`lwip-performance` - :SOC_WIFI_SUPPORTED: * The :example:`wifi/iperf` example contains a configuration that is heavily optimized for Wi-Fi TCP/IP throughput. Append the contents of the files :example_file:`wifi/iperf/sdkconfig.defaults`, :example_file:`wifi/iperf/sdkconfig.defaults.{IDF_TARGET_PATH_NAME}` and :example_file:`wifi/iperf/sdkconfig.ci.99` to the ``sdkconfig`` file in your project in order to add all of these options. Note that some of these options may have trade-offs in terms of reduced debuggability, increased firmware size, increased memory usage, or reduced performance of other features. To get the best result, read the documentation pages linked above and use related information to determine exactly which options are best suited for your app. - :SOC_EMAC_SUPPORTED: * The :example:`ethernet/iperf` example contains a configuration that is heavily optimized for Ethernet TCP/IP throughput. Examine :example_file:`ethernet/iperf/sdkconfig.defaults` for more details. Note that some of these options may have trade-offs in terms of reduced debuggability, increased firmware size, increased memory usage, or reduced performance of other features. To get the best result, read the documentation pages linked above and use related information to determine exactly which options are best suited for your app. + * For lwIP TCP/IP, see :ref:`lwip-performance` + :SOC_WIFI_SUPPORTED: * The :example:`wifi/iperf` example contains a configuration that is heavily optimized for Wi-Fi TCP/IP throughput, usually at the expense of higher RAM usage. Append the contents of the files :example_file:`wifi/iperf/sdkconfig.defaults`, :example_file:`wifi/iperf/sdkconfig.defaults.{IDF_TARGET_PATH_NAME}` and :example_file:`wifi/iperf/sdkconfig.ci.99` to the ``sdkconfig`` file in your project in order to add all of these options. Note that some of these options may have trade-offs in terms of reduced debuggability, increased firmware size, increased memory usage, or reduced performance of other features. To get the best result, read the documentation pages linked above and use related information to determine exactly which options are best suited for your app. + :SOC_EMAC_SUPPORTED: * The :example:`ethernet/iperf` example contains a configuration that is heavily optimized for Ethernet TCP/IP throughput, usually at the expense of higher RAM usage. Examine :example_file:`ethernet/iperf/sdkconfig.defaults` for more details. Note that some of these options may have trade-offs in terms of reduced debuggability, increased firmware size, increased memory usage, or reduced performance of other features. To get the best result, read the documentation pages linked above and use related information to determine exactly which options are best suited for your app. Improving I/O Performance ------------------------- diff --git a/docs/en/api-guides/startup.rst b/docs/en/api-guides/startup.rst index d402bb770a6..e0276986eac 100644 --- a/docs/en/api-guides/startup.rst +++ b/docs/en/api-guides/startup.rst @@ -3,13 +3,11 @@ Application Startup Flow :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} - This note explains various steps which happen before ``app_main`` function of an ESP-IDF application is called. The high level view of startup process is as follows: -1. :ref:`first-stage-bootloader` in ROM loads second-stage bootloader image to RAM (IRAM & DRAM) from flash offset {IDF_TARGET_BOOTLOADER_OFFSET}. +1. :ref:`first-stage-bootloader` in ROM loads second-stage bootloader image to RAM (IRAM & DRAM) from flash offset {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}. 2. :ref:`second-stage-bootloader` loads partition table and main app image from flash. Main app incorporates both RAM segments and read-only segments mapped via flash cache. @@ -22,11 +20,11 @@ This process is explained in detail in the following sections. First Stage Bootloader ^^^^^^^^^^^^^^^^^^^^^^ -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES After SoC reset, PRO CPU will start running immediately, executing reset vector code, while APP CPU will be held in reset. During startup process, PRO CPU does all the initialization. APP CPU reset is de-asserted in the ``call_start_cpu0`` function of application startup code. Reset vector code is located in the mask ROM of the {IDF_TARGET_NAME} chip and cannot be modified. -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES After SoC reset, the CPU will start running immediately to perform initialization. The reset vector code is located in the mask ROM of the {IDF_TARGET_NAME} chip and cannot be modified. @@ -46,15 +44,19 @@ Startup code called from the reset vector determines the boot mode by checking ` .. only:: esp32 - Second stage bootloader binary image is loaded from flash starting at address 0x1000. If :doc:`/security/secure-boot-v1` is in use then the first 4 kB sector of flash is used to store secure boot IV and digest of the bootloader image. Otherwise, this sector is unused. + Second stage bootloader binary image is loaded from flash starting at address {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}. If :doc:`/security/secure-boot-v1` is in use then the first 4 kB sector of flash is used to store secure boot IV and digest of the bootloader image. Otherwise, this sector is unused. .. only:: esp32s2 - Second stage bootloader binary image is loaded from flash starting at address 0x1000. The 4 kB sector of flash before this address is unused. + Second stage bootloader binary image is loaded from flash starting at address {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}. The 4 kB sector of flash before this address is unused. + +.. only:: esp32p4 -.. only:: not (esp32 or esp32s2) + Second stage bootloader binary image is loaded from flash starting at address {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}. The 8 kB sector of flash before this address is reserved for the key manager for use with flash encryption (AES-XTS). - Second stage bootloader binary image is loaded from the start of flash at offset 0x0. +.. only:: not (esp32 or esp32s2 or esp32p4) + + Second stage bootloader binary image is loaded from the start of flash at offset {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}. .. TODO: describe application binary image format, describe optional flash configuration commands. @@ -63,11 +65,11 @@ Startup code called from the reset vector determines the boot mode by checking ` Second Stage Bootloader ^^^^^^^^^^^^^^^^^^^^^^^ -In ESP-IDF, the binary image which resides at offset {IDF_TARGET_BOOTLOADER_OFFSET} in flash is the second stage bootloader. Second stage bootloader source code is available in :idf:`components/bootloader` directory of ESP-IDF. Second stage bootloader is used in ESP-IDF to add flexibility to flash layout (using partition tables), and allow for various flows associated with flash encryption, secure boot, and over-the-air updates (OTA) to take place. +In ESP-IDF, the binary image which resides at offset {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} in flash is the second stage bootloader. Second stage bootloader source code is available in :idf:`components/bootloader` directory of ESP-IDF. Second stage bootloader is used in ESP-IDF to add flexibility to flash layout (using partition tables), and allow for various flows associated with flash encryption, secure boot, and over-the-air updates (OTA) to take place. When the first stage bootloader is finished checking and loading the second stage bootloader, it jumps to the second stage bootloader entry point found in the binary image header. -Second stage bootloader reads the partition table found by default at offset 0x8000 (:ref:`configurable value `). See :doc:`partition tables ` documentation for more information. The bootloader finds factory and OTA app partitions. If OTA app partitions are found in the partition table, the bootloader consults the ``otadata`` partition to determine which one should be booted. See :doc:`/api-reference/system/ota` for more information. +Second stage bootloader reads the partition table found by default at offset {IDF_TARGET_CONFIG_PARTITION_TABLE_OFFSET} (:ref:`configurable value `). See :doc:`partition tables ` documentation for more information. The bootloader finds factory and OTA app partitions. If OTA app partitions are found in the partition table, the bootloader consults the ``otadata`` partition to determine which one should be booted. See :doc:`/api-reference/system/ota` for more information. For a full description of the configuration options available for the ESP-IDF bootloader, see :doc:`bootloader`. @@ -76,7 +78,7 @@ For the selected partition, second stage bootloader reads the binary image from - For segments with load addresses in internal :ref:`iram` or :ref:`dram`, the contents are copied from flash to the load address. - For segments which have load addresses in :ref:`drom` or :ref:`irom` regions, the flash MMU is configured to provide the correct mapping from the flash to the load address. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: esp32 Note that the second stage bootloader configures flash MMU for both PRO and APP CPUs, but it only enables flash MMU for PRO CPU. Reason for this is that second stage bootloader code is loaded into the memory region used by APP CPU cache. The duty of enabling cache for APP CPU is passed on to the application. @@ -112,15 +114,15 @@ This port-layer initialization function initializes the basic C Runtime Environm - Finish configuring the MMU cache. :SOC_SPIRAM_SUPPORTED: - Enable PSRAM if configured. - Set the CPU clocks to the frequencies configured for the project. - :CONFIG_ESP_SYSTEM_MEMPROT_FEATURE: - Initialize memory protection if configured. + :SOC_MEMPROT_SUPPORTED: - Initialize memory protection if configured. :esp32: - Reconfigure the main SPI flash based on the app header settings (necessary for compatibility with bootloader versions before ESP-IDF V4.0, see :ref:`bootloader-compatibility`). - :not CONFIG_FREERTOS_UNICORE: - If the app is configured to run on multiple cores, start the other core and wait for it to initialize as well (inside the similar "port layer" initialization function ``call_start_cpu1``). + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - If the app is configured to run on multiple cores, start the other core and wait for it to initialize as well (inside the similar "port layer" initialization function ``call_start_cpu1``). -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES Once ``call_start_cpu0`` completes running, it calls the "system layer" initialization function ``start_cpu0`` found in :idf_file:`components/esp_system/startup.c`. Other cores will also complete port-layer initialization and call ``start_other_cores`` found in the same file. -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES Once ``call_start_cpu0`` completes running, it calls the "system layer" initialization function ``start_cpu0`` found in :idf_file:`components/esp_system/startup.c`. @@ -156,13 +158,13 @@ After doing some more initialization tasks (that require the scheduler to have s The main task that runs ``app_main`` has a fixed RTOS priority (one higher than the minimum) and a :ref:`configurable stack size `. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES The main task core affinity is also configurable: :ref:`CONFIG_ESP_MAIN_TASK_AFFINITY`. Unlike normal FreeRTOS tasks (or embedded C ``main`` functions), the ``app_main`` task is allowed to return. If this happens, The task is cleaned up and the system will continue running with other RTOS tasks scheduled normally. Therefore, it is possible to implement ``app_main`` as either a function that creates other application tasks and then returns, or as a main application task itself. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES Second Core Startup ------------------- @@ -175,4 +177,4 @@ Unlike normal FreeRTOS tasks (or embedded C ``main`` functions), the ``app_main` The ``start_cpu_other_cores_default`` function does some core-specific system initialization and then waits for the PRO CPU to start the FreeRTOS scheduler, at which point it executes ``esp_startup_start_app_other_cores`` which is another weak-linked function defaulting to ``esp_startup_start_app_other_cores_default``. - By default ``esp_startup_start_app_other_cores_default`` does nothing but spin in a busy-waiting loop until the scheduler of the PRO CPU triggers an interrupt to start the RTOS scheduler on the APP CPU. \ No newline at end of file + By default ``esp_startup_start_app_other_cores_default`` does nothing but spin in a busy-waiting loop until the scheduler of the PRO CPU triggers an interrupt to start the RTOS scheduler on the APP CPU. diff --git a/docs/en/api-guides/tools/idf-docker-image.rst b/docs/en/api-guides/tools/idf-docker-image.rst index edb751a6881..03f4f544c02 100644 --- a/docs/en/api-guides/tools/idf-docker-image.rst +++ b/docs/en/api-guides/tools/idf-docker-image.rst @@ -66,6 +66,10 @@ The above command explained: - ``espressif/idf``: uses Docker image ``espressif/idf`` with tag ``latest``. The ``latest`` tag is implicitly added by Docker when no tag is specified. - ``idf.py build``: runs this command inside the container. +.. note:: + + When the mounted directory, ``/project``, contains a git repository owned by a different user (``UID``) than the one running the Docker container, git commands executed within ``/project`` might fail, displaying an error message ``fatal: detected dubious ownership in repository at '/project'``. To resolve this issue, you can designate the ``/project`` directory as safe by setting the IDF_GIT_SAFE_DIR environment variable during the Docker container startup. For instance, you can achieve this by including ``-e IDF_GIT_SAFE_DIR='/project'`` as a parameter. Additionally, multiple directories can be specified by using a ``:`` separator. To entirely disable this git security check, ``*`` can be used. + To build with a specific Docker image tag, specify it as ``espressif/idf:TAG``, for example: .. code-block:: bash @@ -139,7 +143,8 @@ The Docker file in ESP-IDF repository provides several build arguments which can - ``IDF_CLONE_URL``: URL of the repository to clone ESP-IDF from. Can be set to a custom URL when working with a fork of ESP-IDF. The default is ``https://github.com/espressif/esp-idf.git``. - ``IDF_CLONE_BRANCH_OR_TAG``: Name of a git branch or tag used when cloning ESP-IDF. This value is passed to the ``git clone`` command using the ``--branch`` argument. The default is ``master``. - ``IDF_CHECKOUT_REF``: If this argument is set to a non-empty value, ``git checkout $IDF_CHECKOUT_REF`` command performs after cloning. This argument can be set to the SHA of the specific commit to check out, for example, if some specific commit on a release branch is desired. -- ``IDF_CLONE_SHALLOW``: If this argument is set to a non-empty value, ``--depth=1 --shallow-submodules`` arguments are be used when performing ``git clone``. This significantly reduces the amount of data downloaded and the size of the resulting Docker image. However, if switching to a different branch in such a "shallow" repository is necessary, an additional ``git fetch origin `` command must be executed first. +- ``IDF_CLONE_SHALLOW``: If this argument is set to a non-empty value, ``--depth=1 --shallow-submodules`` arguments are used when performing ``git clone``. Depth can be customized using ``IDF_CLONE_SHALLOW_DEPTH``. Doing a shallow clone significantly reduces the amount of data downloaded and the size of the resulting Docker image. However, if switching to a different branch in such a "shallow" repository is necessary, an additional ``git fetch origin `` command must be executed first. +- ``IDF_CLONE_SHALLOW_DEPTH``: This argument specifies the depth value to use when doing a shallow clone. If not set, ``--depth=1`` will be used. This argument has effect only if ``IDF_CLONE_SHALLOW`` is used. Use this argument if you are building a Docker image for a branch, and the image has to contain the latest tag on that branch. To determine the required depth, run ``git describe`` for the given branch and note the offset number. Increment it by 1, then use it as the value of this argument. The resulting image will contain the latest tag on the branch, and consequently ``git describe`` command inside the Docker image will work as expected. - ``IDF_INSTALL_TARGETS``: Comma-separated list of ESP-IDF targets to install toolchains for, or ``all`` to install toolchains for all targets. Selecting specific targets reduces the amount of data downloaded and the size of the resulting Docker image. The default is ``all``. To use these arguments, pass them via the ``--build-arg`` command line option. For example, the following command builds a Docker image with a shallow clone of ESP-IDF v4.4.1 and tools for ESP32-C3 only: diff --git a/docs/en/api-guides/tools/idf-monitor.rst b/docs/en/api-guides/tools/idf-monitor.rst index 69611b53481..10703657340 100644 --- a/docs/en/api-guides/tools/idf-monitor.rst +++ b/docs/en/api-guides/tools/idf-monitor.rst @@ -33,8 +33,8 @@ For easy interaction with IDF Monitor, use the keyboard shortcuts given in the t - Send the exit character itself to remote - * - * Ctrl + P - - Reset target into bootloader to pause app via RTS line - - Resets the target, into bootloader via the RTS line (if connected), so that the board runs nothing. Useful when you need to wait for another device to startup. + - Reset target into bootloader to pause app via RTS and DTR lines + - Resets the target into the bootloader using the RTS and DTR lines (if connected). This stops the board from executing the application, making it useful when waiting for another device to start. For additional details, refer to :ref:`target-reset-into-bootloader`. * - * Ctrl + R - Reset target board via RTS - Resets the target board and re-starts the application via the RTS line (if connected). @@ -235,6 +235,81 @@ By default, IDF Monitor will reset the target when connecting to it. The reset o The ``--no-reset`` option applies the same behavior even when connecting IDF Monitor to a particular port (e.g., ``idf.py monitor --no-reset -p [PORT]``). +.. _target-reset-into-bootloader: + +Target Reset into Bootloader +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +IDF Monitor provides the capability to reset a chip into the bootloader using a pre-defined reset sequence that has been tuned to work in most environments. Additionally, users have the flexibility to set a custom reset sequence, allowing for fine-tuning and adaptability to diverse scenarios. + +Using Pre-defined Reset Sequence +-------------------------------- + +IDF Monitor's default reset sequence is designed to work seamlessly across a wide range of environments. To trigger a reset into the bootloader using the default sequence, no additional configuration is required. + +Custom Reset Sequence +--------------------- + +For more advanced users or specific use cases, IDF Monitor supports the configuration of a custom reset sequence using :ref:`configuration-file`. This is particularly useful in extreme edge cases where the default sequence may not suffice. + +The sequence is defined with a string in the following format: + +- Consists of individual commands divided by ``|`` (e.g. ``R0|D1|W0.5``). +- Commands (e.g. ``R0``) are defined by a code (``R``) and an argument (``0``). + +.. list-table:: + :header-rows: 1 + :widths: 15 50 35 + :align: center + + * - Code + - Action + - Argument + * - D + - Set DTR control line + - ``1``/``0`` + * - R + - Set RTS control line + - ``1``/``0`` + * - U + - Set DTR and RTS control lines at the same time (Unix-like systems only) + - ``0,0``/``0,1``/``1,0``/``1,1`` + * - W + - Wait for ``N`` seconds (where ``N`` is a float) + - N + +Example: + +.. code-block:: ini + + [esp-idf-monitor] + custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 + +Refer to `custom reset sequence`_ from Esptool documentation for further details. Please note that ``custom_reset_sequence`` is the only used value from the Esptool configuration, and others will be ignored in IDF Monitor. + +Share Configuration Across Tools +-------------------------------- + +The configuration for the custom reset sequence can be specified in a shared configuration file between IDF Monitor and Esptool. In this case, your configuration file name should be either ``setup.cfg`` or ``tox.ini`` so it would be recognized by both tools. + +Example of a shared configuration file: + +.. code-block:: ini + + [esp-idf-monitor] + menu_key = T + skip_menu_key = True + + [esptool] + custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 + +.. note:: + + When using the ``custom_reset_sequence`` parameter in both the ``[esp-idf-monitor]`` section and the ``[esptool]`` section, the configuration from the ``[esp-idf-monitor]`` section will take precedence in IDF Monitor. Any conflicting configuration in the ``[esptool]`` section will be ignored. + + This precedence rule also applies when the configuration is spread across multiple files. The global esp-idf-monitor configuration will take precedence over the local esptool configuration. + + Launching GDB with GDBStub ~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -256,15 +331,19 @@ In both cases (i.e., sending the ``Ctrl+C`` message, or receiving the special st Output Filtering ~~~~~~~~~~~~~~~~ -IDF monitor can be invoked as ``idf.py monitor --print-filter="xyz"``, where ``--print-filter`` is the parameter for output filtering. The default value is an empty string, which means that everything is printed. +IDF monitor can be invoked as ``idf.py monitor --print-filter="xyz"``, where ``--print-filter`` is the parameter for output filtering. The default value is an empty string, which means that everything is printed. Filtering can also be configured using the ``ESP_IDF_MONITOR_PRINT_FILTER`` environment variable. + +.. note:: + + When using both the environment variable ``ESP_IDF_MONITOR_PRINT_FILTER`` and the argument ``--print-filter``, the setting from the CLI argument will take precedence. Restrictions on what to print can be specified as a series of ``:`` items where ```` is the tag string and ```` is a character from the set ``{N, E, W, I, D, V, *}`` referring to a level for :doc:`logging <../../api-reference/system/log>`. -For example, ``PRINT_FILTER="tag1:W"`` matches and prints only the outputs written with ``ESP_LOGW("tag1", ...)`` or at lower verbosity level, i.e., ``ESP_LOGE("tag1", ...)``. Not specifying a ```` or using ``*`` defaults to Verbose level. +For example, ``--print_filter="tag1:W"`` matches and prints only the outputs written with ``ESP_LOGW("tag1", ...)`` or at lower verbosity level, i.e., ``ESP_LOGE("tag1", ...)``. Not specifying a ```` or using ``*`` defaults to a Verbose level. .. note:: - Use primary logging to disable at compilation the outputs you do not need through the :doc:`logging library <../../api-reference/system/log>`. Output filtering with ESP- monitor is a secondary solution which can be useful for adjusting the filtering options without recompiling the application. + Use primary logging to disable at compilation the outputs you do not need through the :doc:`logging library <../../api-reference/system/log>`. Output filtering with the IDF monitor is a secondary solution that can be useful for adjusting the filtering options without recompiling the application. Your app tags must not contain spaces, asterisks ``*``, or colons ``:`` to be compatible with the output filtering feature. @@ -273,7 +352,7 @@ If the last line of the output in your app is not followed by a carriage return, Examples of Filtering Rules: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- ``*`` can be used to match any tags. However, the string ``PRINT_FILTER="*:I tag1:E"`` with regards to ``tag1`` prints errors only, because the rule for ``tag1`` has a higher priority over the rule for ``*``. +- ``*`` can be used to match any tags. However, the string ``--print_filter="*:I tag1:E"`` with regards to ``tag1`` prints errors only, because the rule for ``tag1`` has a higher priority over the rule for ``*``. - The default (empty) rule is equivalent to ``*:V`` because matching every tag at the Verbose level or lower means matching everything. - ``"*:N"`` suppresses not only the outputs from logging functions, but also the prints made by ``printf``, etc. To avoid this, use ``*:E`` or a higher verbosity level. - Rules ``"tag1:V"``, ``"tag1:v"``, ``"tag1:"``, ``"tag1:*"``, and ``"tag1"`` are equivalent. @@ -300,12 +379,12 @@ The following log snippet was acquired without any filtering options:: D (318) vfs: esp_vfs_register_fd_range is successful for range <54; 64) and VFS ID 1 I (328) wifi: wifi driver task: 3ffdbf84, prio:23, stack:4096, core=0 -The captured output for the filtering options ``PRINT_FILTER="wifi esp_image:E light_driver:I"`` is given below:: +The captured output for the filtering options ``--print_filter="wifi esp_image:E light_driver:I"`` is given below:: E (31) esp_image: image at 0x30000 has invalid magic byte I (328) wifi: wifi driver task: 3ffdbf84, prio:23, stack:4096, core=0 -The options ``PRINT_FILTER="light_driver:D esp_image:N boot:N cpu_start:N vfs:N wifi:N *:V"`` show the following output:: +The options ``--print_filter="light_driver:D esp_image:N boot:N cpu_start:N vfs:N wifi:N *:V"`` show the following output:: load:0x40078000,len:13564 entry 0x40078d4c @@ -313,6 +392,8 @@ The options ``PRINT_FILTER="light_driver:D esp_image:N boot:N cpu_start:N vfs:N D (309) light_driver: [light_init, 74]:status: 1, mode: 2 +.. _configuration-file: + Configuration File ================== @@ -392,6 +473,9 @@ Below is a table listing the available configuration options: * - skip_menu_key - Pressing the menu key can be skipped for menu commands. - ``False`` + * - custom_reset_sequence + - Custom reset sequence for resetting into the bootloader. + - N/A Syntax @@ -399,7 +483,7 @@ Syntax The configuration file is in .ini file format: it must be introduced by an ``[esp-idf-monitor]`` header to be recognized as valid. This section then contains name = value entries. Lines beginning with ``#`` or ``;`` are ignored as comments. -.. code-block:: text +.. code-block:: ini # esp-idf-monitor.cfg file to configure internal settings of esp-idf-monitor [esp-idf-monitor] @@ -419,12 +503,7 @@ The configuration file is in .ini file format: it must be introduced by an ``[es Known Issues with IDF Monitor ============================= -Issues Observed on Windows -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- Arrow keys, as well as some other keys, do not work in GDB due to Windows Console limitations. -- Occasionally, when "idf.py" exits, it might stall for up to 30 seconds before IDF Monitor resumes. -- When "gdb" is run, it might stall for a short time before it begins communicating with the GDBStub. +If you encounter any issues while using IDF Monitor, check our `GitHub repository `_ for a list of known issues and their current status. If you come across a problem that hasn't been documented yet, we encourage you to create a new issue report. .. _addr2line: https://sourceware.org/binutils/docs/binutils/addr2line.html .. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor @@ -432,3 +511,4 @@ Issues Observed on Windows .. _pySerial: https://github.com/pyserial/pyserial .. _miniterm: https://pyserial.readthedocs.org/en/latest/tools.html#module-serial.tools.miniterm .. _C0 control codes: https://en.wikipedia.org/wiki/C0_and_C1_control_codes#C0_controls +.. _custom reset sequence: https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/esptool/configuration-file.html#custom-reset-sequence diff --git a/docs/en/api-guides/tools/idf-py.rst b/docs/en/api-guides/tools/idf-py.rst index 7fc6afaa65b..c785b7a212b 100644 --- a/docs/en/api-guides/tools/idf-py.rst +++ b/docs/en/api-guides/tools/idf-py.rst @@ -140,8 +140,6 @@ For commands that are not known to ``idf.py``, an attempt to execute them as a b The command ``idf.py`` supports `shell autocompletion `_ for bash, zsh and fish shells. -In order to make `shell autocompletion `_ supported, please make sure you have at least Python 3.5 and `click `_ 7.1 or newer (:ref:`Software `). - To enable autocompletion for ``idf.py``, use the ``export`` command (:ref:`Step 4. Set up the environment variables `). Autocompletion is initiated by pressing the TAB key. Type ``idf.py -`` and press the TAB key to autocomplete options. The autocomplete support for PowerShell is planned in the future. @@ -237,6 +235,23 @@ To list all available root level options, run ``idf.py --help``. To list options - ``--cmake-warn-uninitialized`` (or ``-w``) causes CMake to print uninitialized variable warnings found in the project directory only. This only controls CMake variable warnings inside CMake itself, not other types of build warnings. This option can also be set permanently by setting the ``IDF_CMAKE_WARN_UNINITIALIZED`` environment variable to a non-zero value. - ``--no-hints`` flag disables hints on resolving errors and disable capturing output. +Passing arguments via a ``@file`` +--------------------------------- + +It is possible to pass multiple arguments to ``idf.py`` via a file. The file or path to the file must be annotated with ``@`` at the beginning. Arguments in the file can be separated by newlines or spaces and are expanded exactly as if they had appeared in that order on the idf.py command line. + +For example, let's have a file `custom_flash.txt`: + +.. code-block:: bash + + flash --baud 115200 + +Then the command can be executed as: ``idf.py @custom_flash.txt monitor`` + +Arguments from a file can be combined with additional command line arguments, and multiple files annotated with ``@`` can be used simultaneously. For instance, if there is a second file ``another_config.txt``, both can be utilized by specifying ``idf.py @custom_flash.txt @another_config.txt monitor``. + +A further example of how this argument file can be used, e.g., creating configuration profile files via @filename, is in the :example_file:`Multiple Build Configurations Example `. + .. _cmake: https://cmake.org .. _ninja: https://ninja-build.org .. _esptool.py: https://github.com/espressif/esptool/#readme diff --git a/docs/en/api-guides/tools/index.rst b/docs/en/api-guides/tools/index.rst index cff1f37ed8f..2f3251c3a24 100644 --- a/docs/en/api-guides/tools/index.rst +++ b/docs/en/api-guides/tools/index.rst @@ -11,3 +11,4 @@ Tools idf-component-manager idf-clang-tidy idf-tools + :esp32 or esp32c3: qemu diff --git a/docs/en/api-guides/tools/qemu.rst b/docs/en/api-guides/tools/qemu.rst new file mode 100644 index 00000000000..379d227d79f --- /dev/null +++ b/docs/en/api-guides/tools/qemu.rst @@ -0,0 +1,85 @@ +QEMU Emulator +============= + +Espressif maintains a `fork `_ of the QEMU emulator with support for {IDF_TARGET_NAME}. This fork implements emulation of the CPU, memory, and several peripherals of {IDF_TARGET_NAME}. For more information about QEMU for {IDF_TARGET_NAME}, see the `documentation `_. + +:doc:`idf.py` allows for running and debugging applications in QEMU. This is a convenient way to test applications without having to flash them to real hardware. + +Prerequisites +------------- + +To use QEMU with ``idf.py`` you first need to install the above-mentioned fork of QEMU. ESP-IDF provides pre-built binaries for x86_64 and arm64 Linux and macOS, as well as x86_64 Windows. If you are using this platform, you can install the pre-built binaries with the following command: + +.. code-block:: console + + python $IDF_PATH/tools/idf_tools.py install qemu-xtensa qemu-riscv32 + +After installing QEMU, make sure it is added to PATH by running ``. ./export.sh`` in the IDF directory. + +If you are using a different platform, you need to build QEMU from source. Refer to official QEMU documentation for instructions. + +Usage +----- + +Running an Application +~~~~~~~~~~~~~~~~~~~~~~ + +To run an IDF application in QEMU, use the following command: + +.. code-block:: console + + idf.py qemu monitor + +This command builds the application, starts QEMU and opens :doc:`IDF monitor `, connecting it to the emulated UART port. You can see the console output of the application and interact with it. IDF Monitor also provides automatic decoding of panic backtraces and UART core dumps. + +Debugging +~~~~~~~~~ + +To debug an application in QEMU, use the following command: + +.. code-block:: console + + idf.py qemu gdb + +This command builds the application, starts QEMU with the GDB server enabled, and opens an interactive GDB session. You can use GDB to debug the application as if it was running on real hardware. + +To see console output while debugging in QEMU, use two terminals. + +* In the first terminal, run: + + .. code-block:: console + + idf.py qemu --gdb monitor + + This command starts QEMU and IDF Monitor, and tells QEMU to wait for a GDB connection. + +* In the second terminal, run: + + .. code-block:: console + + idf.py gdb + + This command starts an interactive GDB sessions and connects it to QEMU. You can now debug the application, and the console output will be visible in the first terminal. + +It is also possible to run QEMU without the IDF Monitor: + +.. code-block:: console + + idf.py qemu + +In this case, the IDF Monitor is not used, and you can interact with QEMU process directly. To switch between the emulated UART console and QEMU console ("QEMU monitor"), use Ctrl-A shortcut. For example, to exit QEMU, press Ctrl-A, then type ``q`` and press Enter. You can use the QEMU console to enter commands, such as for inspecting registers and memory. + +Graphics Support +~~~~~~~~~~~~~~~~ + +QEMU supports a virtual framebuffer device. This device doesn't exist in the real {IDF_TARGET_NAME} hardware, but it can be used to test graphics applications in QEMU. + +To launch QEMU with a virtual framebuffer device enabled, use the following command: + +.. code-block:: console + + idf.py qemu --graphics monitor + +When the ``--graphics`` option is used, QEMU opens an additional window where the framebuffer contents are displayed. + +To use the virtual framebuffer device in your application, you can add the `espressif/esp_lcd_qemu_rgb `_ component to your project. This component provides an esp_lcd compatible driver for the virtual framebuffer device. diff --git a/docs/en/api-guides/unit-tests.rst b/docs/en/api-guides/unit-tests.rst index 84cc5e10005..de436d226c3 100644 --- a/docs/en/api-guides/unit-tests.rst +++ b/docs/en/api-guides/unit-tests.rst @@ -185,6 +185,11 @@ Use menuconfig to set the serial port for flashing. For more information, see :i Running Unit Tests ------------------ +.. note:: + + We also provide the pytest-based framework `pytest-embedded `_ to help make running unit-tests more convenient and efficient. If you need to run tests in CI or run multiple tests in a row we recommend checking out this project. For more information see `Pytest-embedded Docs `_ and :doc:`/contribute/esp-idf-tests-with-pytest`. + + After flashing reset the {IDF_TARGET_NAME} and it will boot the unit test app. When unit test app is idle, press "Enter" will make it print test menu with all available tests:: diff --git a/docs/en/api-guides/usb-serial-jtag-console.rst b/docs/en/api-guides/usb-serial-jtag-console.rst index 5188e811bf2..cbcfc4b4657 100644 --- a/docs/en/api-guides/usb-serial-jtag-console.rst +++ b/docs/en/api-guides/usb-serial-jtag-console.rst @@ -89,6 +89,10 @@ For data transmitted from {IDF_TARGET_NAME} to PC Terminal (e.g., stdout, logs), For data transmitted from the PC Terminal to {IDF_TARGET_NAME} (e.g., console commands), many PC Terminals wait for the {IDF_TARGET_NAME} to ingest the bytes before allowing you to send more data. This is in contrast to using a USB-to-Serial (UART) bridge chip, which always ingests the bytes and sends them to a (possibly not listening) {IDF_TARGET_NAME}. +.. note:: + + In rare cases, it is possible that data sent from {IDF_TARGET_NAME} to the host gets 'stuck' in host memory. Sending more data will get it 'unstuck', but if the application does not send more data, depending on the driver, this data needs to be flushed to the host manually. The non-blocking (default) driver and the VFS implementation will flush automatically after a newline. The blocking (interrupt-based) driver will automatically flush when its transmit buffer becomes empty. + Sleep Mode Considerations ------------------------- diff --git a/docs/en/api-guides/wifi.rst b/docs/en/api-guides/wifi.rst index 9ecca160735..a1e9e27c132 100644 --- a/docs/en/api-guides/wifi.rst +++ b/docs/en/api-guides/wifi.rst @@ -1752,6 +1752,8 @@ A config option :ref:`CONFIG_ESP_WIFI_11R_SUPPORT` and configuration parameter : {IDF_TARGET_NAME} Wi-Fi Power-saving Mode ----------------------------------------- +This subsection will briefly introduce the concepts and usage related to Wi-Fi Power Saving Mode, for a more detailed introduction please refer to the :doc:`Low Power Mode User Guide <../api-guides/low-power-mode>` + Station Sleep ++++++++++++++++++++++ diff --git a/docs/en/api-reference/index.rst b/docs/en/api-reference/index.rst index 715fe0abae9..acb2c585b13 100644 --- a/docs/en/api-reference/index.rst +++ b/docs/en/api-reference/index.rst @@ -1,6 +1,7 @@ ************* API Reference ************* + :link_to_translation:`zh_CN:[中文]` .. toctree:: diff --git a/docs/en/api-reference/peripherals/adc_calibration.rst b/docs/en/api-reference/peripherals/adc_calibration.rst index 8e5bbce299a..cc639012d40 100644 --- a/docs/en/api-reference/peripherals/adc_calibration.rst +++ b/docs/en/api-reference/peripherals/adc_calibration.rst @@ -106,12 +106,12 @@ If you use your custom ADC calibration schemes, you could either modify this fun After setting up the configuration structure, call :cpp:func:`adc_cali_create_scheme_curve_fitting` to create a Curve Fitting calibration scheme handle. This function may fail due to reasons such as :c:macro:`ESP_ERR_INVALID_ARG` or :c:macro:`ESP_ERR_NO_MEM`. - ADC Calibration Efuse Related Failures + ADC Calibration eFuse Related Failures ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ When the function :cpp:func:`adc_cali_create_scheme_curve_fitting` returns :c:macro:`ESP_ERR_NOT_SUPPORTED`, this means the calibration scheme required eFuse bits are not correct on your board. - ESP-IDF provided ADC calibration scheme is based on the values in certain ADC calibration related on-chip eFuse bits. Espressif guarantees that these bits are burned during module manufacturing, so you don't have to burn these eFuses bits yourself. + The ADC calibration scheme provided by ESP-IDF is based on the values in certain ADC calibration related on-chip eFuse bits. Espressif guarantees that these bits are burned during module manufacturing, so you don't have to burn these eFuses bits yourself. If you see such an error, please contact us at `Technical Inquiries `__ website. diff --git a/docs/en/api-reference/peripherals/dac.rst b/docs/en/api-reference/peripherals/dac.rst index 2b7267f3d5c..2d3bdc23b55 100644 --- a/docs/en/api-reference/peripherals/dac.rst +++ b/docs/en/api-reference/peripherals/dac.rst @@ -142,5 +142,5 @@ API Reference .. include-build-file:: inc/dac_oneshot.inc .. include-build-file:: inc/dac_cosine.inc .. include-build-file:: inc/dac_continuous.inc -.. include-build-file:: inc/components/driver/dac/include/driver/dac_types.inc +.. include-build-file:: inc/components/esp_driver_dac/include/driver/dac_types.inc .. include-build-file:: inc/components/hal/include/hal/dac_types.inc diff --git a/docs/en/api-reference/peripherals/dedic_gpio.rst b/docs/en/api-reference/peripherals/dedic_gpio.rst index 54b6618a406..477bd66a7eb 100644 --- a/docs/en/api-reference/peripherals/dedic_gpio.rst +++ b/docs/en/api-reference/peripherals/dedic_gpio.rst @@ -15,7 +15,7 @@ Create/Destroy GPIO Bundle A GPIO bundle is a group of GPIOs, which can be manipulated at the same time in one CPU cycle. The maximal number of GPIOs that a bundle can contain is limited by each CPU. What's more, the GPIO bundle has a strong relevance to the CPU which it derives from. **Any operations on the GPIO bundle should be put inside a task which is running on the same CPU core to the GPIO bundle belongs to.** Likewise, only those ISRs who are installed on the same CPU core are allowed to do operations on that GPIO bundle. .. note:: - + Dedicated GPIO is more of a CPU peripheral, so it has a strong relationship with CPU core. It's highly recommended to install and operate GPIO bundle in a pin-to-core task. For example, if GPIOA is connected to CPU0, and the dedicated GPIO instruction is issued from CPU1, then it's impossible to control GPIOA. To install a GPIO bundle, one needs to call :cpp:func:`dedic_gpio_new_bundle` to allocate the software resources and connect the dedicated channels to user selected GPIOs. Configurations for a GPIO bundle are covered in :cpp:type:`dedic_gpio_bundle_config_t` structure: @@ -98,7 +98,7 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod - Clear bits of GPIO: ``clr_bit_gpio_out imm[7:0]`` - Note: Immediate value width depends on the number of dedicated GPIO channels - .. only:: esp32c2 or esp32c3 or esp32c6 + .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 - Set bits of GPIO: ``csrrsi rd, csr, imm[4:0]`` - Clear bits of GPIO: ``csrrci rd, csr, imm[4:0]`` @@ -112,7 +112,7 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod For details of supported dedicated GPIO instructions, please refer to **{IDF_TARGET_NAME} Technical Reference Manual** > **Processor Instruction Extensions (PIE) (to be added later)** [`PDF <{IDF_TARGET_TRM_EN_URL}#pie>`__]. -.. only:: esp32c2 or esp32c3 or esp32c6 +.. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 Code examples for manipulating dedicated GPIOs from assembly are provided in the :example:`peripherals/dedicated_gpio` directory of ESP-IDF examples. These examples show how to emulate a UART, an I2C and an SPI bus in assembly thanks to dedicated GPIOs. diff --git a/docs/en/api-reference/peripherals/ecdsa.rst b/docs/en/api-reference/peripherals/ecdsa.rst new file mode 100644 index 00000000000..d6e19cf5bcc --- /dev/null +++ b/docs/en/api-reference/peripherals/ecdsa.rst @@ -0,0 +1,82 @@ +Elliptic Curve Digital Signature Algorithm (ECDSA) +================================================== + +The Elliptic Curve Digital Signature Algorithm (ECDSA) offers a variant of the Digital Signature Algorithm (DSA) which uses elliptic-curve cryptography. + +{IDF_TARGET_NAME}'s ECDSA peripheral provides a secure and efficient environment for computing ECDSA signatures. It offers fast computations while ensuring the confidentiality of the signing process to prevent information leakage. ECDSA private key used in the signing process is accessible only to the hardware peripheral, and it is not readable by software. + +ECDSA peripheral can help to establish **Secure Device Identity** for TLS mutual authentication and similar use-cases. + +Supported Features +------------------ + +- ECDSA digital signature generation and verification +- Two different elliptic curves, namely P-192 and P-256 (FIPS 186-3 specification) +- Two hash algorithms for message hash in the ECDSA operation, namely SHA-224 and SHA-256 (FIPS PUB 180-4 specification) + + +ECDSA on {IDF_TARGET_NAME} +-------------------------- + +On {IDF_TARGET_NAME}, the ECDSA module works with a secret key burnt into an eFuse block. This eFuse key is made completely inaccessible (default mode) for any resources outside the cryptographic modules, thus avoiding key leakage. + +ECDSA key can be programmed externally through ``espefuse.py`` script using: + +.. code:: bash + + espefuse.py burn_key ECDSA_KEY + +.. only:: SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK + + .. note:: + + Five physical eFuse blocks can be used as keys for the ECDSA module: block 4 ~ block 8. E.g., for block 4 (which is the first key block) , the argument should be ``BLOCK_KEY0``. + +.. only:: not SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK + + .. note:: + + Six physical eFuse blocks can be used as keys for the ECDSA module: block 4 ~ block 9. E.g., for block 4 (which is the first key block) , the argument should be ``BLOCK_KEY0``. + + +Alternatively the ECDSA key can also be programmed through the application running on the target. + +Following code snippet uses :cpp:func:`esp_efuse_write_key` to set physical key block 0 in the eFuse with key purpose as :cpp:enumerator:`esp_efuse_purpose_t::ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY`: + +.. code-block:: c + + #include "esp_efuse.h" + + const uint8_t key_data[32] = { ... }; + + esp_err_t status = esp_efuse_write_key(EFUSE_BLK_KEY0, + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, + key_data, sizeof(key_data)); + + if (status == ESP_OK) { + // written key + } else { + // writing key failed, maybe written already + } + + +Dependency on TRNG +------------------ + +ECDSA peripheral relies on the hardware True Random Number Generator (TRNG) for its internal entropy requirement. During ECDSA signature creation, the algorithm requires a random integer to be generated as specified in the `RFC 6090 `_ section 5.3.2. + +Please ensure that hardware :doc:`RNG <../system/random>` is enabled before starting ECDSA computations (primarily signing) in the application. + +Application Outline +------------------- + +Please refer to the :ref:`ecdsa-peri-with-esp-tls` guide for details on how-to use ECDSA peripheral for establishing a mutually authenticated TLS connection. + +The ECDSA peripheral in mbedTLS stack is integrated by overriding the ECDSA sign and verify APIs. Please note that, the ECDSA peripheral does not support all curves or hash algorithms and hence for cases where the requirements do not meet the hardware, implementation falls back to the software. + +For a particular TLS context, additional APIs have been supplied to populate certain fields (e.g., private key ctx) to differentiate routing to hardware. ESP-TLS layer integrates these APIs internally and hence no additional work is required at the application layer. However, for custom use-cases please refer to API details below. + +API Reference +------------- + +.. include-build-file:: inc/ecdsa_alt.inc diff --git a/docs/en/api-reference/peripherals/gpio.rst b/docs/en/api-reference/peripherals/gpio.rst index a7622fc908a..af5d24215e9 100644 --- a/docs/en/api-reference/peripherals/gpio.rst +++ b/docs/en/api-reference/peripherals/gpio.rst @@ -21,7 +21,7 @@ GPIO driver offers a dump function :cpp:func:`gpio_dump_io_configuration` to sho FuncSel: 1 (GPIO) GPIO Matrix SigIn ID: (simple GPIO input) SleepSelEn: 1 - + IO[18] - Pullup: 0, Pulldown: 0, DriveCap: 2 InputEn: 0, OutputEn: 1, OpenDrain: 0 @@ -34,7 +34,7 @@ GPIO driver offers a dump function :cpp:func:`gpio_dump_io_configuration` to sho InputEn: 1, OutputEn: 0, OpenDrain: 0 FuncSel: 0 (IOMUX) SleepSelEn: 1 - + =================IO DUMP End================== If an IO pin is routed to a peripheral signal through the GPIO matrix, the signal ID printed in the dump information is defined in the ``soc/gpio_sig_map.h`` file. The word ``**RESERVED**`` indicates the IO is occupied by either FLASH or PSRAM. It is strongly not recommended to reconfigure them for other application purposes. @@ -44,7 +44,7 @@ If an IO pin is routed to a peripheral signal through the GPIO matrix, the signa .. only:: not SOC_LP_PERIPHERALS_SUPPORTED There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power and analog subsystem. These pin functions can be used when: - + .. only:: SOC_LP_PERIPHERALS_SUPPORTED There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power, analog subsystem, and Low-Power(LP) peripherals. These pin functions can be used when: @@ -52,7 +52,9 @@ If an IO pin is routed to a peripheral signal through the GPIO matrix, the signa .. list:: - In Deep-sleep mode - :SOC_ULP_SUPPORTED and not esp32c6: - The :doc:`Ultra Low Power co-processor <../../api-reference/system/ulp>` is running + :SOC_ULP_FSM_SUPPORTED: - The :doc:`Ultra Low Power FSM co-processor <../../api-reference/system/ulp>` is running + :SOC_RISCV_COPROC_SUPPORTED: - The :doc:`Ultra Low Power RISC-V co-processor <../../api-reference/system/ulp-risc-v>` is running + :SOC_LP_CORE_SUPPORTED: - The :doc:`Ultra Low Power LP-Core co-processor <../../api-reference/system/ulp-lp-core>` is running - Analog functions such as ADC/DAC/etc are in use :SOC_LP_PERIPHERALS_SUPPORTED: - LP peripherals, such as LP_UART, LP_I2C, are in use diff --git a/docs/en/api-reference/peripherals/gpio/esp32p4.inc b/docs/en/api-reference/peripherals/gpio/esp32p4.inc index 47335f01694..64e199dd542 100644 --- a/docs/en/api-reference/peripherals/gpio/esp32p4.inc +++ b/docs/en/api-reference/peripherals/gpio/esp32p4.inc @@ -9,7 +9,7 @@ .. gpio-summary -The {IDF_TARGET_NAME} chip features 57 physical GPIO pins (GPIO0 ~ GPIO56). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. +The {IDF_TARGET_NAME} chip features 55 physical GPIO pins (GPIO0 ~ GPIO54). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions. @@ -297,16 +297,6 @@ The table below provides more information on pin usage, and please note the comm - - - * - GPIO55 - - - - - - - - * - GPIO56 - - - - - - - .. note:: - Strapping pin: GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 are strapping pins. For more infomation, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__. diff --git a/docs/en/api-reference/peripherals/i2c.rst b/docs/en/api-reference/peripherals/i2c.rst index 127b7e0aed9..8563c60c40a 100644 --- a/docs/en/api-reference/peripherals/i2c.rst +++ b/docs/en/api-reference/peripherals/i2c.rst @@ -544,5 +544,5 @@ API Reference .. include-build-file:: inc/i2c_slave.inc -.. include-build-file:: inc/components/driver/i2c/include/driver/i2c_types.inc +.. include-build-file:: inc/components/esp_driver_i2c/include/driver/i2c_types.inc .. include-build-file:: inc/components/hal/include/hal/i2c_types.inc \ No newline at end of file diff --git a/docs/en/api-reference/peripherals/i2s.rst b/docs/en/api-reference/peripherals/i2s.rst index a6eac202d4c..ed781cceff8 100644 --- a/docs/en/api-reference/peripherals/i2s.rst +++ b/docs/en/api-reference/peripherals/i2s.rst @@ -297,7 +297,7 @@ The clock config helper macro is: - :c:macro:`I2S_STD_CLK_DEFAULT_CONFIG` -Please refer to :ref:`i2s-api-reference-i2s_std` for information about STD API. And for more details, please refer to :component_file:`driver/i2s/include/driver/i2s_std.h`. +Please refer to :ref:`i2s-api-reference-i2s_std` for information about STD API. And for more details, please refer to :component_file:`esp_driver_i2s/include/driver/i2s_std.h`. STD TX Mode ~~~~~~~~~~~ @@ -551,7 +551,7 @@ Here is the table of the data received in the buffer with different :cpp:member: - :c:macro:`I2S_PDM_TX_CLK_DEFAULT_CONFIG` - Please refer to :ref:`i2s-api-reference-i2s_pdm` for information about PDM TX API. And for more details, please refer to :component_file:`driver/i2s/include/driver/i2s_pdm.h`. + Please refer to :ref:`i2s-api-reference-i2s_pdm` for information about PDM TX API. And for more details, please refer to :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`. The PDM data width is fixed to 16-bit. When the data in an ``int16_t`` writing buffer is: @@ -647,7 +647,7 @@ Here is the table of the data received in the buffer with different :cpp:member: - :c:macro:`I2S_PDM_RX_CLK_DEFAULT_CONFIG` - Please refer to :ref:`i2s-api-reference-i2s_pdm` for information about PDM RX API. And for more details, please refer to :component_file:`driver/i2s/include/driver/i2s_pdm.h`. + Please refer to :ref:`i2s-api-reference-i2s_pdm` for information about PDM RX API. And for more details, please refer to :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`. The PDM data width is fixed to 16-bit. When the data on the line (The PDM format on the line is transferred to PCM format for easier comprehension) is: @@ -733,7 +733,7 @@ Here is the table of the data received in the buffer with different :cpp:member: - :c:macro:`I2S_TDM_CLK_DEFAULT_CONFIG` - Please refer to :ref:`i2s-api-reference-i2s_tdm` for information about TDM API. And for more details, please refer to :component_file:`driver/i2s/include/driver/i2s_tdm.h`. + Please refer to :ref:`i2s-api-reference-i2s_tdm` for information about TDM API. And for more details, please refer to :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`. .. note:: @@ -1070,5 +1070,5 @@ I2S Driver I2S Types ^^^^^^^^^ -.. include-build-file:: inc/components/driver/i2s/include/driver/i2s_types.inc +.. include-build-file:: inc/components/esp_driver_i2s/include/driver/i2s_types.inc .. include-build-file:: inc/components/hal/include/hal/i2s_types.inc diff --git a/docs/en/api-reference/peripherals/index.rst b/docs/en/api-reference/peripherals/index.rst index b2fa1605737..cf65cdd5464 100644 --- a/docs/en/api-reference/peripherals/index.rst +++ b/docs/en/api-reference/peripherals/index.rst @@ -12,6 +12,7 @@ Peripherals API :SOC_ANA_CMPR_SUPPORTED: ana_cmpr clk_tree :SOC_DAC_SUPPORTED: dac + :SOC_ECDSA_SUPPORTED: ecdsa :SOC_ETM_SUPPORTED: etm gpio gptimer @@ -34,7 +35,6 @@ Peripherals API spi_flash/index spi_master spi_slave - :esp32: secure_element :SOC_SPI_SUPPORT_SLAVE_HD_VER2: spi_slave_hd :SOC_TEMP_SENSOR_SUPPORTED: temp_sensor :SOC_TOUCH_SENSOR_SUPPORTED: touch_pad diff --git a/docs/en/api-reference/peripherals/mcpwm.rst b/docs/en/api-reference/peripherals/mcpwm.rst index 01791562158..90c9305c1da 100644 --- a/docs/en/api-reference/peripherals/mcpwm.rst +++ b/docs/en/api-reference/peripherals/mcpwm.rst @@ -204,10 +204,11 @@ Next, to allocate a capture channel, you can call the :cpp:func:`mcpwm_new_captu - :cpp:member:`mcpwm_capture_channel_config_t::intr_priority` sets the priority of the interrupt. If it is set to ``0``, the driver will allocate an interrupt with a default priority. Otherwise, the driver will use the given priority. - :cpp:member:`mcpwm_capture_channel_config_t::gpio_num` sets the GPIO number used by the capture channel. - :cpp:member:`mcpwm_capture_channel_config_t::prescale` sets the prescaler of the input signal. -- :cpp:member:`mcpwm_capture_channel_config_t::pos_edge` and :cpp:member:`mcpwm_capture_channel_config_t::neg_edge` set whether to capture on the positive and/or falling edge of the input signal. -- :cpp:member:`mcpwm_capture_channel_config_t::pull_up` and :cpp:member:`mcpwm_capture_channel_config_t::pull_down` set whether to pull up and/or pull down the GPIO internally. -- :cpp:member:`mcpwm_capture_channel_config_t::invert_cap_signal` sets whether to invert the capture signal. -- :cpp:member:`mcpwm_capture_channel_config_t::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral. +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::pos_edge` and :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::neg_edge` set whether to capture on the positive and/or falling edge of the input signal. +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::pull_up` and :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::pull_down` set whether to pull up and/or pull down the GPIO internally. +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::invert_cap_signal` sets whether to invert the capture signal. +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral. +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::keep_io_conf_at_exit` sets whether to keep the GPIO configuration when the capture channel is deleted. The :cpp:func:`mcpwm_new_capture_channel` will return a pointer to the allocated capture channel object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there is no free capture channel left in the capture timer, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. @@ -855,6 +856,10 @@ When a sync signal is taken by the MCPWM timer, the timer will be forced into a - :cpp:member:`mcpwm_timer_sync_phase_config_t::count_value` sets the count value to load when the sync signal is taken. - :cpp:member:`mcpwm_timer_sync_phase_config_t::direction` sets the count direction when the sync signal is taken. +.. note:: + + When the MCPWM timer is working in :cpp:enumerator:`MCPWM_TIMER_COUNT_MODE_UP_DOWN` mode, special attention needs to be taken. In this mode, counter range ``[0 -> peak-1]`` belongs to the **increment** phase, and counter range ``[peak -> 1]`` belongs to the **decrement** phase. Thus if you set the :cpp:member:`mcpwm_timer_sync_phase_config_t::count_value` to zero, you may also want to set the :cpp:member:`mcpwm_timer_sync_phase_config_t::direction` to :cpp:enumerator:`MCPWM_TIMER_DIRECTION_UP`. Otherwise, the timer will be continue with the decrement phase, and the count value underflows to ``peak``. + Likewise, the `MCPWM Capture Timer <#mcpwm-capture-timer-and-channels>`__ can be synced as well. You can set the sync phase for the capture timer by calling :cpp:func:`mcpwm_capture_timer_set_phase_on_sync`. The sync phase configuration is defined in :cpp:type:`mcpwm_capture_timer_sync_phase_config_t` structure: - :cpp:member:`mcpwm_capture_timer_sync_phase_config_t::sync_src` sets the sync signal source. See `MCPWM Sync Sources <#mcpwm-sync-sources>`__ for how to create a sync source object. Specifically, if this is set to ``NULL``, the driver will disable the sync feature for the MCPWM capture timer. @@ -1044,7 +1049,7 @@ API Reference .. include-build-file:: inc/mcpwm_sync.inc .. include-build-file:: inc/mcpwm_cap.inc .. include-build-file:: inc/mcpwm_etm.inc -.. include-build-file:: inc/components/driver/mcpwm/include/driver/mcpwm_types.inc +.. include-build-file:: inc/components/esp_driver_mcpwm/include/driver/mcpwm_types.inc .. include-build-file:: inc/components/hal/include/hal/mcpwm_types.inc diff --git a/docs/en/api-reference/peripherals/rmt.rst b/docs/en/api-reference/peripherals/rmt.rst index a3b86645703..6710fa833c2 100644 --- a/docs/en/api-reference/peripherals/rmt.rst +++ b/docs/en/api-reference/peripherals/rmt.rst @@ -203,9 +203,13 @@ The RX channel-supported event callbacks are listed in the :cpp:type:`rmt_rx_eve - :cpp:member:`rmt_rx_event_callbacks_t::on_recv_done` sets a callback function for "receive-done" event. The function prototype is declared in :cpp:type:`rmt_rx_done_callback_t`. +.. note:: + + The "receive-done" is not equivalent to "receive-finished". This callback can also be called at a "partial-receive-done" time, for many times during one receive transaction. + Users can save their own context in :cpp:func:`rmt_tx_register_event_callbacks` and :cpp:func:`rmt_rx_register_event_callbacks` as well, via the parameter ``user_data``. The user data is directly passed to each callback function. -In the callback function, users can fetch the event-specific data that is filled by the driver in the ``edata``. Note that the ``edata`` pointer is only valid during the callback. +In the callback function, users can fetch the event-specific data that is filled by the driver in the ``edata``. Note that the ``edata`` pointer is **only** valid during the callback, please do not try to save this pointer and use that outside of the callback function. The TX-done event data is defined in :cpp:type:`rmt_tx_done_event_data_t`: @@ -213,8 +217,9 @@ The TX-done event data is defined in :cpp:type:`rmt_tx_done_event_data_t`: The RX-complete event data is defined in :cpp:type:`rmt_rx_done_event_data_t`: -- :cpp:member:`rmt_rx_done_event_data_t::received_symbols` points to the received RMT symbols. These symbols are saved in the ``buffer`` parameter of the :cpp:func:`rmt_receive` function. Users should not free this receive buffer before the callback returns. +- :cpp:member:`rmt_rx_done_event_data_t::received_symbols` points to the received RMT symbols. These symbols are saved in the ``buffer`` parameter of the :cpp:func:`rmt_receive` function. Users should not free this receive buffer before the callback returns. If you also enabled the partial receive feature, then the user buffer will be used as a "second level buffer", where its content can be overwritten by data comes in afterwards. In this case, you should copy the received data to another place if you want to keep it or process it later. - :cpp:member:`rmt_rx_done_event_data_t::num_symbols` indicates the number of received RMT symbols. This value is not larger than the ``buffer_size`` parameter of :cpp:func:`rmt_receive` function. If the ``buffer_size`` is not sufficient to accommodate all the received RMT symbols, the driver only keeps the maximum number of symbols that the buffer can hold, and excess symbols are discarded or ignored. +- :cpp:member:`rmt_rx_done_event_data_t::is_last` indicates whether the current received buffer is the last one in the transaction. This is useful when you enable the partial reception feature by :cpp:member:`rmt_receive_config_t::extra_flags::en_partial_rx`. .. _rmt-enable-and-disable-channel: @@ -326,6 +331,7 @@ As also discussed in the :ref:`rmt-enable-and-disable-channel`, calling :cpp:fun - :cpp:member:`rmt_receive_config_t::signal_range_min_ns` specifies the minimal valid pulse duration in either high or low logic levels. A pulse width that is smaller than this value is treated as a glitch, and ignored by the hardware. - :cpp:member:`rmt_receive_config_t::signal_range_max_ns` specifies the maximum valid pulse duration in either high or low logic levels. A pulse width that is bigger than this value is treated as **Stop Signal**, and the receiver generates receive-complete event immediately. +- If the incoming packet is long, that they cannot be stored in the user buffer at once, you can enable the partial reception feature by setting :cpp:member:`rmt_receive_config_t::extra_flags::en_partial_rx` to ``true``. In this case, the driver invokes :cpp:member:`rmt_rx_event_callbacks_t::on_recv_done` callback multiple times during one transaction, when the user buffer is **almost full**. You can check the value of :cpp:member::`rmt_rx_done_event_data_t::is_last` to know if the transaction is about to finish. The RMT receiver starts the RX machine after the user calls :cpp:func:`rmt_receive` with the provided configuration above. Note that, this configuration is transaction specific, which means, to start a new round of reception, the user needs to set the :cpp:type:`rmt_receive_config_t` again. The receiver saves the incoming signals into its internal memory block or DMA buffer, in the format of :cpp:type:`rmt_symbol_word_t`. @@ -337,7 +343,7 @@ The RMT receiver starts the RX machine after the user calls :cpp:func:`rmt_recei Due to the limited size of the memory block, the RMT receiver can only save short frames whose length is not longer than the memory block capacity. Long frames are truncated by the hardware, and the driver reports an error message: ``hw buffer too small, received symbols truncated``. -The copy destination should be provided in the ``buffer`` parameter of :cpp:func:`rmt_receive` function. If this buffer overlfows due to an insufficient buffer size, the receiver can continue to work, but overflowed symbols are dropped and the following error message is reported: ``user buffer too small, received symbols truncated``. Please take care of the lifecycle of the ``buffer`` parameter, ensuring that the buffer is not recycled before the receiver is finished or stopped. +The copy destination should be provided in the ``buffer`` parameter of :cpp:func:`rmt_receive` function. If this buffer overflows due to an insufficient buffer size, the receiver can continue to work, but overflowed symbols are dropped and the following error message is reported: ``user buffer too small, received symbols truncated``. Please take care of the lifecycle of the ``buffer`` parameter, ensuring that the buffer is not recycled before the receiver is finished or stopped. The receiver is stopped by the driver when it finishes working, i.e., receive a signal whose duration is bigger than :cpp:member:`rmt_receive_config_t::signal_range_max_ns`. The user needs to call :cpp:func:`rmt_receive` again to restart the receiver, if necessary. The user can get the received data in the :cpp:member:`rmt_rx_event_callbacks_t::on_recv_done` callback. See also :ref:`rmt-register-event-callbacks` for more information. @@ -603,7 +609,7 @@ API Reference .. include-build-file:: inc/rmt_rx.inc .. include-build-file:: inc/rmt_common.inc .. include-build-file:: inc/rmt_encoder.inc -.. include-build-file:: inc/components/driver/rmt/include/driver/rmt_types.inc +.. include-build-file:: inc/components/esp_driver_rmt/include/driver/rmt_types.inc .. include-build-file:: inc/components/hal/include/hal/rmt_types.inc diff --git a/docs/en/api-reference/peripherals/sdmmc_host.rst b/docs/en/api-reference/peripherals/sdmmc_host.rst index 58bd62d669e..5b8f231447b 100644 --- a/docs/en/api-reference/peripherals/sdmmc_host.rst +++ b/docs/en/api-reference/peripherals/sdmmc_host.rst @@ -67,10 +67,15 @@ Overview Pins used by Slot 0 (``HS1_*``) are also used to connect the SPI flash chip in ESP32-WROOM and ESP32-WROVER modules. These pins cannot be concurrently shared between an SD card and an SPI flash. If you need to use Slot 0, establish an alternative connection for the SPI flash using different pins and configure the necessary eFuses accordingly. -.. only:: SOC_SDMMC_USE_GPIO_MATRIX +.. only:: esp32s3 Both slots :c:macro:`SDMMC_HOST_SLOT_0` and :c:macro:`SDMMC_HOST_SLOT_1` support 1-, 4- and 8-line SD interfaces. The slots are connected to {IDF_TARGET_NAME} GPIOs using the GPIO matrix. This means that any GPIO may be used for each of the SD card signals. +.. only:: esp32p4 + + - :c:macro:`SDMMC_HOST_SLOT_1` is routed via GPIO Matrix. This means that any GPIO may be used for each of the SD card signals. It is for non UHS-I usage. + - :c:macro:`SDMMC_HOST_SLOT_0` is dedicated to UHS-I mode, which is not yet supported in the driver. + Supported Speed Modes --------------------- diff --git a/docs/en/api-reference/peripherals/secure_element.rst b/docs/en/api-reference/peripherals/secure_element.rst deleted file mode 100644 index 22762d128af..00000000000 --- a/docs/en/api-reference/peripherals/secure_element.rst +++ /dev/null @@ -1,28 +0,0 @@ -ESP32-WROOM-32SE (Secure Element) -================================= - -:link_to_translation:`zh_CN:[中文]` - -Overview --------- - -ESP32-WROOM-32SE integrates Microchip's ATECC608A cryptoauth chip in the module. ATECC608A is a secure element, which would generate and store ECC private key in the hardware. The ECC private key can be used to enhance security to connect to IoT cloud services with the use of X.509-based mutual authentication. - -The application example demonstrates ECDSA sign and verify functions using ECC private key stored in ATECC608A. - -Application Example -------------------- - -Secure Element ECDSA Sign/Verify example: :example:`peripherals/secure_element/atecc608_ecdsa`. - -How to Configure and Provision ESP32-WROOM-32SE for TLS -------------------------------------------------------- - -To configure and provision ATECC608A chip on ESP32-WROOM-32SE please visit `esp_cryptoauth_utility `_. - -How to Use ATECC608A of ESP32-WROOM-32SE for TLS ------------------------------------------------- - -ATECC608A can be used for TLS connections using ESP-TLS. - -To configure ESP-TLS for using a secure element, please refer to **ATECC608A (Secure Element) with ESP-TLS** in :doc:`../protocols/esp_tls`. diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst index 2d6a22451fa..897f4f552c4 100644 --- a/docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst +++ b/docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst @@ -42,11 +42,11 @@ Under this condition, all CPUs should always execute code and access data from i When :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and :ref:`CONFIG_SPIRAM_RODATA` are both enabled, these APIs will not disable the caches. -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES The way that these APIs disable the caches suspends all the other tasks. Besides, all non-IRAM-safe interrupts will be disabled. The other core will be polling in a busy loop. These will be restored until the Flash operation completes. -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES The way that these APIs disable the caches also disables non-IRAM-safe interrupts. These will be restored until the Flash operation completes. diff --git a/docs/en/api-reference/peripherals/touch_pad.rst b/docs/en/api-reference/peripherals/touch_pad.rst index 2bad8a74bde..a658e2af78f 100644 --- a/docs/en/api-reference/peripherals/touch_pad.rst +++ b/docs/en/api-reference/peripherals/touch_pad.rst @@ -16,7 +16,7 @@ For design, operation, and control registers of a touch sensor, see **{IDF_TARGE In-depth design details of touch sensors and firmware development guidelines for {IDF_TARGET_NAME} are available in `Touch Sensor Application Note `_. -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 For more information about testing touch sensors in various configurations, please check the `Guide for ESP32-Sense-Kit `_. @@ -118,14 +118,14 @@ Configuration * - T13 - GPIO13 * - T14 - - GPIO14 + - GPIO14 Use the function :cpp:func:`touch_pad_set_fsm_mode` to select if touch pad measurement (operated by FSM) should be started automatically by a hardware timer, or by software. If software mode is selected, use :cpp:func:`touch_pad_sw_start` to start the FSM. Touch State Measurements ^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 The following two functions come in handy to read raw or filtered measurements from the sensor: @@ -138,7 +138,7 @@ Touch State Measurements Before using :cpp:func:`touch_pad_read_filtered`, you need to initialize and configure the filter by calling specific filter functions described in Section `Filtering of Measurements`_. -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 The following function come in handy to read raw measurements from the sensor: @@ -151,7 +151,7 @@ For the demonstration of how to read the touch pad data, check the application e Method of Measurements ^^^^^^^^^^^^^^^^^^^^^^ -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 The touch sensor counts the number of charge/discharge cycles over a fixed period of time (specified by :cpp:func:`touch_pad_set_measurement_clock_cycles`). The count result is the raw data that read from :cpp:func:`touch_pad_read_raw_data`. After finishing one measurement, the touch sensor sleeps until the next measurement start, this interval between two measurements can be set by :cpp:func:`touch_pad_set_measurement_interval`. @@ -159,7 +159,7 @@ Method of Measurements If the specified clock cycles for measurement is too samll, the result may be inaccurate, but increasing clock cycles will increase the power consumption as well. Additionally, the response of the touch sensor will slow down if the total time of the inverval and measurement is too long. -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 The touch sensor records the period of time (i.e., the number of clock cycles) over a fixed charge/discharge cycles (specified by :cpp:func:`touch_pad_set_charge_discharge_times`). The count result is the raw data that read from :cpp:func:`touch_pad_read_raw_data`. After finishing one measurement, the touch sensor sleeps until the next measurement start, this interval between two measurements can be set by :cpp:func:`touch_pad_set_measurement_interval`. @@ -172,11 +172,11 @@ Optimization of Measurements A touch sensor has several configurable parameters to match the characteristics of a particular touch pad design. For instance, to sense smaller capacity changes, it is possible to narrow down the reference voltage range within which the touch pads are charged/discharged. The high and low reference voltages are set using the function :cpp:func:`touch_pad_set_voltage`. -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 Besides the ability to discern smaller capacity changes, a positive side effect is reduction of power consumption for low power applications. A likely negative effect is an increase in measurement noise. If the dynamic range of obtained readings is still satisfactory, then further reduction of power consumption might be done by reducing the measurement time with :cpp:func:`touch_pad_set_measurement_clock_cycles`. -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 Besides the ability to discern smaller capacity changes, a positive side effect is reduction of power consumption for low power applications. A likely negative effect is an increase in measurement noise. If the dynamic range of obtained readings is still satisfactory, then further reduction of power consumption might be done by reducing the measurement time with :cpp:func:`touch_pad_set_charge_discharge_times`. @@ -187,17 +187,17 @@ The following list summarizes available measurement parameters and corresponding * voltage range: :cpp:func:`touch_pad_set_voltage` * speed (slope): :cpp:func:`touch_pad_set_cnt_mode` -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 * Clock cycles of one measurement: :cpp:func:`touch_pad_set_measurement_clock_cycles` -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 * Charge and discharge times of one measurement: :cpp:func:`touch_pad_set_charge_discharge_times` Relationship between the voltage range (high/low reference voltages), speed (slope), and measurement time is shown in the figure below. -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 .. figure:: ../../../_static/touch_pad-measurement-parameters.jpg :align: center @@ -208,7 +208,7 @@ Relationship between the voltage range (high/low reference voltages), speed (slo The last chart **Output** represents the touch sensor reading, i.e., the count of pulses collected within the measurement time. -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 .. figure:: ../../../_static/touch_pad-measurement-parameters-version2.png :align: center @@ -225,7 +225,7 @@ All functions are provided in pairs to **set** a specific parameter and to **get Filtering of Measurements ^^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 If measurements are noisy, you can filter them with provided API functions. Before using the filter, please start it by calling :cpp:func:`touch_pad_filter_start`. @@ -233,7 +233,7 @@ Filtering of Measurements You can stop the filter with :cpp:func:`touch_pad_filter_stop`. If not required anymore, the filter can be deleted by invoking :cpp:func:`touch_pad_filter_delete`. -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 If measurements are noisy, you can filter them with provided API functions. The {IDF_TARGET_NAME}'s touch functionality provide two sets of APIs for doing this. @@ -259,7 +259,7 @@ Before enabling an interrupt on a touch detection, you should establish a touch Once a detection threshold is established, it can be set during initialization with :cpp:func:`touch_pad_config` or at the runtime with :cpp:func:`touch_pad_set_thresh`. -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 In the next step, configure how interrupts are triggered. They can be triggered below or above the threshold, which is set with the function :cpp:func:`touch_pad_set_trigger_mode`. @@ -270,13 +270,13 @@ Finally, configure and manage interrupt calls using the following functions: When interrupts are operational, you can obtain the information from which particular pad an interrupt came by invoking :cpp:func:`touch_pad_get_status` and clear the pad status with :cpp:func:`touch_pad_clear_status`. -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 .. note:: Interrupts on touch detection operate on raw/unfiltered measurements checked against user established threshold and are implemented in hardware. Enabling the software filtering API (see :ref:`touch_pad-api-filtering-of-measurements`) does not affect this process. -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 Wakeup from Sleep Mode ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-reference/peripherals/usb_host.rst b/docs/en/api-reference/peripherals/usb_host.rst index 5007bea0e31..db2d3254525 100644 --- a/docs/en/api-reference/peripherals/usb_host.rst +++ b/docs/en/api-reference/peripherals/usb_host.rst @@ -398,38 +398,37 @@ Host Stack Configuration Non-Compliant Device Support ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To support USB devices that are non-compliant in various scenarios or exhibit specific behaviors it is possible to configure the USB Host stack. +To support USB devices that are non-compliant in various scenarios or exhibit specific behaviors, it is possible to configure the USB Host stack. -As a USB device may be hot-plugged, it is essential to have the configurable delays between power switching and device attachment, and when the device's internal power has stabilized. +As a USB device may be hot-plugged, it is essential to have configurable delays between power switching and device attachment, and when the device's internal power has stabilized. Enumeration Configuration """"""""""""""""""""""""" -During the process of enumerating connected USB devices, several timeout values ensure the proper functioning of the device. +During the process of enumerating connected USB devices, several delay values ensure the proper functioning of the device. .. figure:: ../../../_static/usb_host/poweron-timings.png :align: center :alt: USB Root Hub Power-on and Connection Events Timing - :figclass: align-center USB Root Hub Power-on and Connection Events Timing -The figure above shows all the timeouts associated with both turning on port power with a device connected and hot-plugging a device. +The figure above shows all the delay values associated with both turning on port power with a device connected and hot-plugging a device. -* After a port is reset or resumed, the USB System Software is expected to provide a “recovery” interval of 10 ms before the device attached to the port is expected to respond to data transfers. -* After the reset/resume recovery interval, if a device receives a SetAddress() request, the device must be able to complete processing of the request and be able to successfully complete the Status stage of the request within 50 ms. -* After successful completion of the Status stage, the device is allowed a SetAddress() recovery interval of 2 ms. +* After a port is reset or resumed, the USB system software is expected to provide a "recovery" interval of 10 ms before the device attached to the port is expected to respond to data transfers. +* After the reset/resume recovery interval, if a device receives a ``SetAddress()`` request, the device must be able to complete processing of the request and be able to successfully complete the Status stage of the request within 50 ms. +* After successful completion of the Status stage, the device is allowed a ``SetAddress()`` recovery interval of 2 ms. .. note:: - For more details regarding connection event timings, please refer to the Universal Serial Bus 2.0 specification, chapter 7.1.7.3 "Connect and Disconnect Signaling". + For more details regarding connection event timings, please refer to `USB 2.0 Specification `_ > Chapter 7.1.7.3 *Connect and Disconnect Signaling*. Configurable parameters of the USB host stack can be configured with multiple options via Menuconfig. -* For Debounce delay refer to :ref:`CONFIG_USB_HOST_DEBOUNCE_DELAY_MS` -* For Reset hold interval refer to :ref:`CONFIG_USB_HOST_RESET_HOLD_MS` -* For Reset recovery interval refer to :ref:`CONFIG_USB_HOST_RESET_RECOVERY_MS` -* Fer SetAddress() recovery interval refer to: :ref:`CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS` +* For debounce delay, refer to :ref:`CONFIG_USB_HOST_DEBOUNCE_DELAY_MS`. +* For reset hold interval, refer to :ref:`CONFIG_USB_HOST_RESET_HOLD_MS`. +* For reset recovery interval, refer to :ref:`CONFIG_USB_HOST_RESET_RECOVERY_MS`. +* Fer ``SetAddress()`` recovery interval, refer to :ref:`CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS`. .. -------------------------------------------------- API Reference ---------------------------------------------------- diff --git a/docs/en/api-reference/protocols/esp_crt_bundle.rst b/docs/en/api-reference/protocols/esp_crt_bundle.rst index 88e343ab407..6c9956ed8fa 100644 --- a/docs/en/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/en/api-reference/protocols/esp_crt_bundle.rst @@ -16,7 +16,7 @@ The bundle comes with the complete list of root certificates from Mozilla's NSS When generating the bundle you may choose between: - * The full root certificate bundle from Mozilla, containing more than 130 certificates. The current bundle was updated Tue Aug 22 03:12:04 2023 GMT. + * The full root certificate bundle from Mozilla, containing more than 130 certificates. The current bundle was updated Tue Dec 12 04:12:04 2023 GMT. * A pre-selected filter list of the name of the most commonly used root certificates, reducing the amount of certificates to around 41 while still having around 90% absolute usage coverage and 99% market share coverage according to SSL certificate authorities statistics. In addition, it is possible to specify a path to a certificate file or a directory containing certificates which then will be added to the generated bundle. diff --git a/docs/en/api-reference/protocols/esp_http_client.rst b/docs/en/api-reference/protocols/esp_http_client.rst index 7cce2f3365b..8a487c69a1d 100644 --- a/docs/en/api-reference/protocols/esp_http_client.rst +++ b/docs/en/api-reference/protocols/esp_http_client.rst @@ -83,6 +83,7 @@ ESP HTTP client supports both **Basic** and **Digest** Authentication. * Users can provide the username and password in the ``url`` or the ``username`` and ``password`` members of the ``esp_http_client_config_t`` configuration. For ``auth_type = HTTP_AUTH_TYPE_BASIC``, the HTTP client takes only one perform operation to pass the authentication process. * If ``auth_type = HTTP_AUTH_TYPE_NONE``, but the ``username`` and ``password`` fields are present in the configuration, the HTTP client takes two perform operations. The client will receive the ``401 Unauthorized`` header in its first attempt to connect to the server. Based on this information, it decides which authentication method to choose and performs it in the second operation. * Check out the example functions ``http_auth_basic``, ``http_auth_basic_redirect`` (for Basic authentication) and ``http_auth_digest`` (for Digest authentication) in the application example for implementation details. + * Currently, only MD5 and SHA-256 algorithms are supported with Digest authentication. Examples of Authentication Configuration @@ -138,6 +139,20 @@ Expected data types for different HTTP Client events in the event loop are as fo The :cpp:type:`esp_http_client_handle_t` received along with the event data will be valid until :cpp:enumerator:`HTTP_EVENT_DISCONNECTED ` is not received. This handle has been sent primarily to differentiate between different client connections and must not be used for any other purpose, as it may change based on client connection state. +TLS Protocol Version +-------------------- + +TLS protocol version to be used for the underlying TLS connection can be set in :cpp:type:`esp_http_client_config_t`. Please refer to the **TLS Protocol Version** section in the :doc:`/api-reference/protocols/esp_tls` for more details. + +The TLS protocol version for the HTTP client can be configured as follows: + + .. code-block:: c + + #include "esp_http_client.h" + esp_http_client_config_t config = { + .tls_version = ESP_HTTP_CLIENT_TLS_VER_TLS_1_2, + }; + API Reference ------------- diff --git a/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst b/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst index 54553148090..90c0e8dd89c 100644 --- a/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst +++ b/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst @@ -43,9 +43,17 @@ In the half duplex mode, the master has to use the protocol defined by the slave For some commands (WRBUF, RDBUF), this phase specifies the address of the shared register to write to/read from. For other commands with this phase, they are meaningless but still have to exist in the transaction. -- Dummy: 8-bit, floating, optional +.. only:: esp32s2 - This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master. + - Dummy: 8-bit (for 1-bit mode) or 4-bit (for 2/4-bit mode), floating, optional + + This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master. + +.. only:: not esp32s2 + + - Dummy: 8-bit, floating, optional + + This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master. - Data: variable length, the direction is also determined by the command. diff --git a/docs/en/api-reference/protocols/esp_tls.rst b/docs/en/api-reference/protocols/esp_tls.rst index 241c5d9c498..a1ba508c2ee 100644 --- a/docs/en/api-reference/protocols/esp_tls.rst +++ b/docs/en/api-reference/protocols/esp_tls.rst @@ -143,11 +143,11 @@ The following table shows a typical comparison between WolfSSL and MbedTLS when ATECC608A (Secure Element) with ESP-TLS -------------------------------------------------- - ESP-TLS provides support for using ATECC608A cryptoauth chip with ESP32-WROOM-32SE. The use of ATECC608A is supported only when ESP-TLS is used with MbedTLS as its underlying SSL/TLS stack. ESP-TLS uses MbedTLS as its underlying TLS/SSL stack by default unless changed manually. + ESP-TLS provides support for using ATECC608A cryptoauth chip with ESP32 series of SoCs. The use of ATECC608A is supported only when ESP-TLS is used with MbedTLS as its underlying SSL/TLS stack. ESP-TLS uses MbedTLS as its underlying TLS/SSL stack by default unless changed manually. .. note:: - ATECC608A chip on ESP32-WROOM-32SE must be already configured, for details refer `esp_cryptoauth_utility `_. + ATECC608A chip interfaced to ESP32 must be already configured. For details, please refer to `esp_cryptoauth_utility `_. To enable the secure element support, and use it in your project for TLS connection, you have to follow the below steps: @@ -203,6 +203,8 @@ The following table shows a typical comparison between WolfSSL and MbedTLS when .. only:: SOC_ECDSA_SUPPORTED + .. _ecdsa-peri-with-esp-tls: + ECDSA Peripheral with ESP-TLS ----------------------------- @@ -244,6 +246,26 @@ ESP-TLS will not check the validity of ``ciphersuites_list`` that was set, you s This feature is supported only in the MbedTLS stack. +TLS Protocol Version +-------------------- + +ESP-TLS provides the ability to set the TLS protocol version for the respective TLS connection. Once the version is specified, it should be exclusively used to establish the TLS connection. This provides an ability to route different TLS connections to different protocol versions like TLS 1.2 and TLS 1.3 at runtime. + +.. note:: + + At the moment, the feature is supported only when ESP-TLS is used with MbedTLS as its underlying SSL/TLS stack. + +To set TLS protocol version with ESP-TLS, set :cpp:member:`esp_tls_cfg_t::tls_version` to the required protocol version from :cpp:type:`esp_tls_proto_ver_t`. If the protocol version field is not set, then the default policy is to allow TLS connection based on the server requirement. + +The ESP-TLS connection can be configured to use the specified protocol version as follows: + + .. code-block:: c + + #include "esp_tls.h" + esp_tls_cfg_t cfg = { + .tls_version = ESP_TLS_VER_TLS_1_2, + }; + API Reference ------------- diff --git a/docs/en/api-reference/protocols/mqtt.rst b/docs/en/api-reference/protocols/mqtt.rst index 4160e8e60e4..0773d7d8ba4 100644 --- a/docs/en/api-reference/protocols/mqtt.rst +++ b/docs/en/api-reference/protocols/mqtt.rst @@ -145,13 +145,13 @@ It is possible to set authentication parameters through the :cpp:class:`authenti * :cpp:member:`password `: use a password by setting * :cpp:member:`certificate ` and :cpp:member:`key `: mutual authentication with TLS, and both can be provided in PEM or DER format - * :cpp:member:`use_secure_element `: use secure element available in ESP32-WROOM-32SE + * :cpp:member:`use_secure_element `: use secure element (ATECC608A) interfaced to ESP32 * :cpp:member:`ds_data `: use Digital Signature Peripheral available in some Espressif devices Session ^^^^^^^^^^^ -For MQTT session related configurations, :cpp:class:`session ` fields should be used. +For MQTT session-related configurations, :cpp:class:`session ` fields should be used. ======================= Last Will and Testament diff --git a/docs/en/api-reference/provisioning/protocomm.rst b/docs/en/api-reference/provisioning/protocomm.rst index 04cfe3f9ceb..abab0b4d962 100644 --- a/docs/en/api-reference/provisioning/protocomm.rst +++ b/docs/en/api-reference/provisioning/protocomm.rst @@ -28,8 +28,11 @@ Protocomm provides the framework for various transports: :SOC_WIFI_SUPPORTED: - Wi-Fi (SoftAP + HTTPD) - Console, in which case the handler invocation is automatically taken care of on the device side. See Transport Examples below for code snippets. +Note that for protocomm_security1 and protocomm_security2, the client still needs to establish sessions by performing the two-way handshake. -Note that for protocomm_security1 and protocomm_security2, the client still needs to establish sessions by performing the two-way handshake. See :doc:`provisioning` for more details about the secure handshake logic. +.. only:: SOC_WIFI_SUPPORTED + + See :doc:`provisioning` for more details about the secure handshake logic. .. _enabling-protocomm-security-version: @@ -43,7 +46,7 @@ The protocomm component provides a project configuration menu to enable/disable * Support ``protocomm_security2`` with SRP6a-based key exchange + AES-GCM encryption/decryption: :ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2`. .. note:: - + Enabling multiple security versions at once offers the ability to control them dynamically but also increases the firmware size. .. only:: SOC_WIFI_SUPPORTED @@ -299,5 +302,7 @@ API Reference .. include-build-file:: inc/protocomm_security.inc .. include-build-file:: inc/protocomm_security0.inc .. include-build-file:: inc/protocomm_security1.inc +.. include-build-file:: inc/protocomm_security2.inc +.. include-build-file:: inc/esp_srp.inc .. include-build-file:: inc/protocomm_httpd.inc .. include-build-file:: inc/protocomm_ble.inc diff --git a/docs/en/api-reference/provisioning/provisioning.rst b/docs/en/api-reference/provisioning/provisioning.rst index 6749d84c7d4..4ddacab5caa 100644 --- a/docs/en/api-reference/provisioning/provisioning.rst +++ b/docs/en/api-reference/provisioning/provisioning.rst @@ -1,5 +1,3 @@ -:orphan: - Unified Provisioning ^^^^^^^^^^^^^^^^^^^^ @@ -14,7 +12,7 @@ The unified provisioning support in the ESP-IDF provides an extensible mechanism The protocol is completely flexible and it offers the ability for the developers to send custom configuration in the provisioning process. The data representation is also left to the application to decide. -2. **Transport Flexibility** +2. **Transport Flexibility** The protocol can work on Wi-Fi (SoftAP + HTTP server) or on Bluetooth LE as a transport protocol. The framework provides an ability to add support for any other transport easily as long as command-response behavior can be supported on the transport. @@ -22,7 +20,7 @@ The protocol can work on Wi-Fi (SoftAP + HTTP server) or on Bluetooth LE as a tr It is understood that each use case may require different security scheme to secure the data that is exchanged in the provisioning process. Some applications may work with SoftAP that is WPA2 protected or Bluetooth LE with the "just-works" security. Or the applications may consider the transport to be insecure and may want application-level security. The unified provisioning framework allows the application to choose the security as deemed suitable. -4. **Compact Data Representation** +4. **Compact Data Representation** The protocol uses `Google Protobufs `_ as a data representation for session setup and Wi-Fi provisioning. They provide a compact data representation and ability to parse the data in multiple programming languages in native format. Please note that this data representation is not forced on application-specific data and the developers may choose the representation of their choice. @@ -233,8 +231,8 @@ Details about the Security 2 scheme are shown in the below sequence diagram: Verifier v = g^x where x = H(s | I | p)"]; DEVICE -> DEVICE [label = "Generate\nKey Pair", leftnote = "b (dev_privkey) = 256 bit random value B(dev_pubkey) = k*v + g^b where k = H(N, g)"]; - DEVICE -> DEVICE [label = "Shared Key", leftnote = "Shared Key K = H(S) where, - S = (A * v^u) ^ b + DEVICE -> DEVICE [label = "Shared Key", leftnote = "Shared Key K = H(S) where, + S = (A * v^u) ^ b u = H(A, B)"]; DEVICE -> CLIENT [label = "SessionResp0(dev_pubkey B, dev_rand)"]; CLIENT -> CLIENT [label = "Shared Key", rightnote = "shared_key(K) = H(S) where, @@ -243,7 +241,7 @@ Details about the Security 2 scheme are shown in the below sequence diagram: k = H(N, g), v = g^x, x = H(s | I | p). - + "]; CLIENT -> CLIENT [label = "Verification\nToken", rightnote = "client_proof M = H[H(N) XOR H(g) | H(I) | s | A | B | K]"]; CLIENT -> DEVICE [label = "SessionCmd1(client_proof M1)"]; diff --git a/docs/en/api-reference/provisioning/wifi_provisioning.rst b/docs/en/api-reference/provisioning/wifi_provisioning.rst index c9baa34c285..3b7ffc59e11 100644 --- a/docs/en/api-reference/provisioning/wifi_provisioning.rst +++ b/docs/en/api-reference/provisioning/wifi_provisioning.rst @@ -1,5 +1,3 @@ -:orphan: - Wi-Fi Provisioning ================== diff --git a/docs/en/api-reference/storage/fatfs.rst b/docs/en/api-reference/storage/fatfs.rst index ae7721dcbe3..338aac18ed6 100644 --- a/docs/en/api-reference/storage/fatfs.rst +++ b/docs/en/api-reference/storage/fatfs.rst @@ -19,32 +19,32 @@ The function :cpp:func:`esp_vfs_fat_unregister_path` deletes the registration wi Most applications use the following workflow when working with ``esp_vfs_fat_`` functions: -1. Call :cpp:func:`esp_vfs_fat_register` to specify: +#. Call :cpp:func:`esp_vfs_fat_register` to specify: - Path prefix where to mount the filesystem (e.g., ``"/sdcard"``, ``"/spiflash"``) - FatFs drive number - A variable which receives the pointer to the ``FATFS`` structure -2. Call :cpp:func:`ff_diskio_register` to register the disk I/O driver for the drive number used in Step 1. +#. Call :cpp:func:`ff_diskio_register` to register the disk I/O driver for the drive number used in Step 1. -3. Call the FatFs function :cpp:func:`f_mount`, and optionally :cpp:func:`f_fdisk`, :cpp:func:`f_mkfs`, to mount the filesystem using the same drive number which was passed to :cpp:func:`esp_vfs_fat_register`. For more information, see `FatFs documentation `_. +#. To mount the filesystem using the same drive number which was passed to :cpp:func:`esp_vfs_fat_register`, call the FatFs function :cpp:func:`f_mount`. If the filesystem is not present on the target logical drive, :cpp:func:`f_mount` will fail with the ``FR_NO_FILESYSTEM`` error. In such case, call :cpp:func:`f_mkfs` to create a fresh FatFS structure on the drive first, and then call:cpp:func:`f_mount` again. Note that SD cards need to be partitioned with :cpp:func:`f_fdisk` prior to previously described steps. For more information, see `FatFs documentation `_. -4. Call the C standard library and POSIX API functions to perform such actions on files as open, read, write, erase, copy, etc. Use paths starting with the path prefix passed to :cpp:func:`esp_vfs_register` (for example, ``"/sdcard/hello.txt"``). The filesystem uses `8.3 filenames `_ format (SFN) by default. If you need to use long filenames (LFN), enable the :ref:`CONFIG_FATFS_LONG_FILENAMES` option. More details on the FatFs filenames are available `here `_. +#. Call the C standard library and POSIX API functions to perform such actions on files as open, read, write, erase, copy, etc. Use paths starting with the path prefix passed to :cpp:func:`esp_vfs_register` (for example, ``"/sdcard/hello.txt"``). The filesystem uses `8.3 filenames `_ format (SFN) by default. If you need to use long filenames (LFN), enable the :ref:`CONFIG_FATFS_LONG_FILENAMES` option. Please refer to `FatFs filenames `_ for more details. -5. Optionally, by enabling the option :ref:`CONFIG_FATFS_USE_FASTSEEK`, you can use the POSIX lseek function to perform it faster. The fast seek does not work for files in write mode, so to take advantage of fast seek, you should open (or close and then reopen) the file in read-only mode. +#. Optionally, call the FatFs library functions directly. In this case, use paths without a VFS prefix, for example, ``"/hello.txt"``. -6. Optionally, by enabling the option :ref:`CONFIG_FATFS_IMMEDIATE_FSYNC`, you can enable automatic calling of :cpp:func:`f_sync` to flush recent file changes after each call of :cpp:func:`vfs_fat_write`, :cpp:func:`vfs_fat_pwrite`, :cpp:func:`vfs_fat_link`, :cpp:func:`vfs_fat_truncate` and :cpp:func:`vfs_fat_ftruncate` functions. This feature improves file-consistency and size reporting accuracy for the FatFs, at a price on decreased performance due to frequent disk operations. +#. Close all open files. -7. Optionally, call the FatFs library functions directly. In this case, use paths without a VFS prefix, for example, ``"/hello.txt"``. +#. Call the FatFs function :cpp:func:`f_mount` for the same drive number with NULL ``FATFS*`` argument to unmount the filesystem. -8. Close all open files. +#. Call the FatFs function :cpp:func:`ff_diskio_register` with NULL ``ff_diskio_impl_t*`` argument and the same drive number to unregister the disk I/O driver. -9. Call the FatFs function :cpp:func:`f_mount` for the same drive number with NULL ``FATFS*`` argument to unmount the filesystem. +#. Call :cpp:func:`esp_vfs_fat_unregister_path` with the path where the file system is mounted to remove FatFs from VFS, and free the ``FATFS`` structure allocated in Step 1. -10. Call the FatFs function :cpp:func:`ff_diskio_register` with NULL ``ff_diskio_impl_t*`` argument and the same drive number to unregister the disk I/O driver. +The convenience functions :cpp:func:`esp_vfs_fat_sdmmc_mount`, :cpp:func:`esp_vfs_fat_sdspi_mount`, and :cpp:func:`esp_vfs_fat_sdcard_unmount` wrap the steps described above and also handle SD card initialization. These functions are described in the next section. -11. Call :cpp:func:`esp_vfs_fat_unregister_path` with the path where the file system is mounted to remove FatFs from VFS, and free the ``FATFS`` structure allocated in Step 1. +.. note:: -The convenience functions :cpp:func:`esp_vfs_fat_sdmmc_mount`, :cpp:func:`esp_vfs_fat_sdspi_mount`, and :cpp:func:`esp_vfs_fat_sdcard_unmount` wrap the steps described above and also handle SD card initialization. These functions are described in the next section. + Because FAT filesystem does not support hardlinks, :cpp:func:`link` copies contents of the file instead. (This only applies to files on FatFs volumes.) Using FatFs with VFS and SD Cards @@ -60,6 +60,15 @@ Using FatFs with VFS in Read-Only Mode The header file :component_file:`fatfs/vfs/esp_vfs_fat.h` also defines the convenience functions :cpp:func:`esp_vfs_fat_spiflash_mount_ro` and :cpp:func:`esp_vfs_fat_spiflash_unmount_ro`. These functions perform Steps 1-3 and 7-9 respectively for read-only FAT partitions. These are particularly helpful for data partitions written only once during factory provisioning, which will not be changed by production application throughout the lifetime of the hardware. +Configuration options +--------------------- + +The following configuration options are available for the FatFs component: + +* :ref:`CONFIG_FATFS_USE_FASTSEEK` - If enabled, the POSIX :cpp:func:`lseek` function will be performed faster. The fast seek does not work for files in write mode, so to take advantage of fast seek, you should open (or close and then reopen) the file in read-only mode. +* :ref:`CONFIG_FATFS_IMMEDIATE_FSYNC` - If enabled, the FatFs will automatically call :cpp:func:`f_sync` to flush recent file changes after each call of :cpp:func:`write`, :cpp:func:`pwrite`, :cpp:func:`link`, :cpp:func:`truncate` and :cpp:func:`ftruncate` functions. This feature improves file-consistency and size reporting accuracy for the FatFs, at a price on decreased performance due to frequent disk operations. +* :ref:`CONFIG_FATFS_LINK_LOCK` - If enabled, this option guarantees the API thread safety, while disabling this option might be necessary for applications that require fast frequent small file operations (e.g., logging to a file). Note that if this option is disabled, the copying performed by :cpp:func:`link` will be non-atomic. In such case, using :cpp:func:`link` on a large file on the same volume in a different task is not guaranteed to be thread safe. + FatFS Disk IO Layer ------------------- @@ -109,13 +118,13 @@ If you decide for any reason to use ``fatfs_create_rawflash_image`` (without wea The arguments of the function are as follows: -1. partition - the name of the partition as defined in the partition table (e.g., :example_file:`storage/fatfsgen/partitions_example.csv`). +#. partition - the name of the partition as defined in the partition table (e.g., :example_file:`storage/fatfsgen/partitions_example.csv`). -2. base_dir - the directory that will be encoded to FatFs partition and optionally flashed into the device. Beware that you have to specify the suitable size of the partition in the partition table. +#. base_dir - the directory that will be encoded to FatFs partition and optionally flashed into the device. Beware that you have to specify the suitable size of the partition in the partition table. -3. flag ``FLASH_IN_PROJECT`` - optionally, users can have the image automatically flashed together with the app binaries, partition tables, etc. on ``idf.py flash -p `` by specifying ``FLASH_IN_PROJECT``. +#. flag ``FLASH_IN_PROJECT`` - optionally, users can have the image automatically flashed together with the app binaries, partition tables, etc. on ``idf.py flash -p `` by specifying ``FLASH_IN_PROJECT``. -4. flag ``PRESERVE_TIME`` - optionally, users can force preserving the timestamps from the source folder to the target image. Without preserving the time, every timestamp will be set to the FATFS default initial time (1st January 1980). +#. flag ``PRESERVE_TIME`` - optionally, users can force preserving the timestamps from the source folder to the target image. Without preserving the time, every timestamp will be set to the FATFS default initial time (1st January 1980). For example:: @@ -136,8 +145,9 @@ It is a reverse tool of (:component_file:`fatfsgen.py `), i.e Usage:: - ./fatfsparse.py [-h] [--wl-layer {detect,enabled,disabled}] fatfs_image.img + ./fatfsparse.py [-h] [--wl-layer {detect,enabled,disabled}] [--verbose] fatfs_image.img +Parameter --verbose prints detailed information from boot sector of the FatFs image to the terminal before folder structure is generated. High-level API Reference ------------------------ diff --git a/docs/en/api-reference/storage/nvs_encryption.rst b/docs/en/api-reference/storage/nvs_encryption.rst index e9fbaeaa055..ef061b2c339 100644 --- a/docs/en/api-reference/storage/nvs_encryption.rst +++ b/docs/en/api-reference/storage/nvs_encryption.rst @@ -20,7 +20,13 @@ NVS Encryption: Flash Encryption-Based Scheme In this scheme, the keys required for NVS encryption are stored in yet another partition, which is protected using :doc:`Flash Encryption <../../security/flash-encryption>`. Therefore, enabling :doc:`Flash Encryption <../../security/flash-encryption>` becomes a prerequisite for NVS encryption here. -NVS encryption is enabled by default when :doc:`../../security/flash-encryption` is enabled. This is done because Wi-Fi driver stores credentials (like SSID and passphrase) in the default NVS partition. It is important to encrypt them as default choice if platform level encryption is already enabled. +.. only:: SOC_HMAC_SUPPORTED + + NVS encryption should be enabled when :doc:`../../security/flash-encryption` is enabled because the Wi-Fi driver stores credentials (like SSID and passphrase) in the default NVS partition. It is important to encrypt them if platform-level encryption is already enabled. + +.. only:: not SOC_HMAC_SUPPORTED + + NVS encryption is enabled by default when :doc:`../../security/flash-encryption` is enabled. This is done because Wi-Fi driver stores credentials (like SSID and passphrase) in the default NVS partition. It is important to encrypt them as default choice if platform-level encryption is already enabled. For using NVS encryption using this scheme, the partition table must contain the :ref:`nvs_encr_key_partition`. Two partition tables containing the :ref:`nvs_encr_key_partition` are provided for NVS encryption under the partition table option (``menuconfig`` > ``Partition Table``). They can be selected with the project configuration menu (``idf.py menuconfig``). Please refer to the example :example:`security/flash_encryption` for how to configure and use the NVS encryption feature. diff --git a/docs/en/api-reference/storage/sdmmc.rst b/docs/en/api-reference/storage/sdmmc.rst index ec2fbe2dbf7..8cffc601db4 100644 --- a/docs/en/api-reference/storage/sdmmc.rst +++ b/docs/en/api-reference/storage/sdmmc.rst @@ -6,47 +6,28 @@ SD/SDIO/MMC Driver Overview -------- -The SD/SDIO/MMC driver currently supports SD memory, SDIO cards, and eMMC chips. This is a protocol level driver built on top of SDMMC and SD SPI host drivers. - -SDMMC and SD SPI host drivers (:component_file:`driver/sdmmc/include/driver/sdmmc_host.h` and :component_file:`driver/spi/include/driver/sdspi_host.h`) provide API functions for: - -- Sending commands to slave devices -- Sending and receiving data -- Handling error conditions within the bus - -For functions used to initialize and configure: +The SD/SDIO/MMC driver currently supports SD memory, SDIO cards, and eMMC chips. This is a protocol layer driver (:component_file:`sdmmc/include/sdmmc_cmd.h`) which can be implemented by: .. list:: + :SOC_SDMMC_HOST_SUPPORTED: - SDMMC host driver (:component_file:`esp_driver_sdmmc/include/driver/sdmmc_host.h`), see :doc:`SDMMC Host API <../peripherals/sdmmc_host>` for more details. + - SDSPI host driver (:component_file:`esp_driver_sdspi/include/driver/sdspi_host.h`), see :doc:`SD SPI Host API <../peripherals/sdspi_host>` for more details. - :SOC_SDMMC_HOST_SUPPORTED: - SDMMC host, see :doc:`SDMMC Host API <../peripherals/sdmmc_host>` - - SD SPI host, see :doc:`SD SPI Host API <../peripherals/sdspi_host>` - - -.. only:: SOC_SDMMC_HOST_SUPPORTED - - The SDMMC protocol layer described in this document handles the specifics of the SD protocol, such as the card initialization and data transfer commands. - - The protocol layer works with the host via the :cpp:class:`sdmmc_host_t` structure. This structure contains pointers to various functions of the host. - -Pin Configurations ------------------- - -..only:: SOC_SDMMC_USE_IOMUX and not SOC_SDMMC_USE_GPIO_MATRIX - - SDMMC pins are dedicated, you don't have to configure the pins. +Protocol Layer vs Host Layer +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -..only:: SOC_SDMMC_USE_GPIO_MATRIX and not SOC_SDMMC_USE_IOMUX +The SDMMC protocol layer described in this document handles the specifics of the SD protocol, such as the card initialization flow and variours data transfer command flows. The protocol layer works with the host via the :cpp:class:`sdmmc_host_t` structure. This structure contains pointers to various functions of the host. - SDMMC pin signals are routed via GPIO Matrix, so you will need to configure the pins in :cpp:type:`sdmmc_slot_config_t`. +Host layer driver(s) implement the protocol layer driver by supporting these functions: -..only:: esp32p4 - - SDMMC have two slots: +- Sending commands to slave devices +- Sending and receiving data +- Handling error conditions within the bus - .. list:: +.. blockdiag:: /../_static/diagrams/sd/sd_arch.diag + :scale: 100% + :caption: SD Host Side Component Architecture + :align: center - - slot 0 pins are dedicated for UHS-I mode. This is not yet supported in the driver. - - slot 1 pins are routed via GPIO Matrix, and it's for non UHS-I usage. You will need to configure the pins in :cpp:type:`sdmmc_slot_config_t` to use the slot 1. Application Example ------------------- @@ -58,7 +39,7 @@ An example which combines the SDMMC driver with the FATFS library is provided in Protocol Layer API ------------------ - The protocol layer is given the :cpp:class:`sdmmc_host_t` structure. This structure describes the SD/MMC host driver, lists its capabilities, and provides pointers to functions of the driver. The protocol layer stores card-specific information in the :cpp:class:`sdmmc_card_t` structure. When sending commands to the SD/MMC host driver, the protocol layer uses the :cpp:class:`sdmmc_command_t` structure to describe the command, arguments, expected return values, and data to transfer if there is any. + The protocol layer is given the :cpp:class:`sdmmc_host_t` structure. This structure describes the SD/MMC host driver, lists its capabilities, and provides pointers to functions for the implementation driver. The protocol layer stores card-specific information in the :cpp:class:`sdmmc_card_t` structure. When sending commands to the SD/MMC host driver, the protocol layer uses the :cpp:class:`sdmmc_command_t` structure to describe the command, arguments, expected return values, and data to transfer if there is any. Using API with SD Memory Cards diff --git a/docs/en/api-reference/storage/vfs.rst b/docs/en/api-reference/storage/vfs.rst index d7a74c92ab8..c50527716d7 100644 --- a/docs/en/api-reference/storage/vfs.rst +++ b/docs/en/api-reference/storage/vfs.rst @@ -104,7 +104,7 @@ If you want to use :cpp:func:`select` with a file descriptor belonging to a non- :cpp:func:`end_select` might be called without a previous :cpp:func:`start_select` call in some rare circumstances. :cpp:func:`end_select` should fail gracefully if this is the case (i.e., should not crash but return an error instead). -Please refer to the reference implementation for the UART peripheral in :component_file:`vfs/vfs_uart.c` and most particularly to the functions :cpp:func:`esp_vfs_dev_uart_register`, :cpp:func:`uart_start_select`, and :cpp:func:`uart_end_select` for more information. +Please refer to the reference implementation for the UART peripheral in :component_file:`esp_driver_uart/src/uart_vfs.c` and most particularly to the functions :cpp:func:`uart_vfs_dev_register`, :cpp:func:`uart_start_select`, and :cpp:func:`uart_end_select` for more information. Please check the following examples that demonstrate the use of :cpp:func:`select` with VFS file descriptors: @@ -189,9 +189,9 @@ Writing to ``stdout`` or ``stderr`` sends characters to the UART transmit FIFO. By default, VFS uses simple functions for reading from and writing to UART. Writes busy-wait until all data is put into UART FIFO, and reads are non-blocking, returning only the data present in the FIFO. Due to this non-blocking read behavior, higher level C library calls, such as ``fscanf("%d\n", &var);``, might not have desired results. -Applications which use the UART driver can instruct VFS to use the driver's interrupt driven, blocking read and write functions instead. This can be done using a call to the ``esp_vfs_dev_uart_use_driver`` function. It is also possible to revert to the basic non-blocking functions using a call to ``esp_vfs_dev_uart_use_nonblocking``. +Applications which use the UART driver can instruct VFS to use the driver's interrupt driven, blocking read and write functions instead. This can be done using a call to the :cpp:func:`uart_vfs_dev_use_driver` function. It is also possible to revert to the basic non-blocking functions using a call to :cpp:func:`uart_vfs_dev_use_nonblocking`. -VFS also provides an optional newline conversion feature for input and output. Internally, most applications send and receive lines terminated by the LF (''\n'') character. Different terminal programs may require different line termination, such as CR or CRLF. Applications can configure this separately for input and output either via menuconfig, or by calls to the functions ``esp_vfs_dev_uart_port_set_rx_line_endings`` and ``esp_vfs_dev_uart_port_set_tx_line_endings``. +VFS also provides an optional newline conversion feature for input and output. Internally, most applications send and receive lines terminated by the LF (''\n'') character. Different terminal programs may require different line termination, such as CR or CRLF. Applications can configure this separately for input and output either via menuconfig, or by calls to the functions :cpp:func:`uart_vfs_dev_port_set_rx_line_endings` and :cpp:func:`uart_vfs_dev_port_set_tx_line_endings`. Standard Streams and FreeRTOS Tasks @@ -235,4 +235,6 @@ API Reference .. include-build-file:: inc/esp_vfs_dev.inc +.. include-build-file:: inc/uart_vfs.inc + .. include-build-file:: inc/esp_vfs_eventfd.inc diff --git a/docs/en/api-reference/system/bootloader_image_format.rst b/docs/en/api-reference/system/bootloader_image_format.rst index 3bbd6836de3..1937c81839b 100644 --- a/docs/en/api-reference/system/bootloader_image_format.rst +++ b/docs/en/api-reference/system/bootloader_image_format.rst @@ -1,13 +1,17 @@ Bootloader Image Format ======================= -The bootloader image consists of the same structures as the application image, see :ref:`Application Image Structures `. The only difference is in the :ref:`Bootloader Description ` structure. +:link_to_translation:`zh_CN:[中文]` + +The bootloader image consists of the same structures as the application image, see :ref:`Application Image Structures `. The only difference is in the :ref:`image-format-bootloader-description` structure. To get information about the bootloader image, please run the following command: .. code-block:: - esptool.py --chip {IDF_TARGET_PATH_NAME} image_info build/bootloader/bootloader.bin --version 2 + esptool.py --chip {IDF_TARGET_PATH_NAME} image_info build/bootloader/bootloader.bin --version 2 + +The resultant output will resemble the following: .. code-block:: @@ -50,6 +54,7 @@ To get information about the bootloader image, please run the following command: ESP-IDF: v5.1-dev-4304-gcb51a3b-dirty Compile time: Mar 30 2023 19:14:17 + .. _image-format-bootloader-description: Bootloader Description @@ -57,14 +62,14 @@ Bootloader Description The ``DRAM0`` segment of the bootloader binary starts with the :cpp:type:`esp_bootloader_desc_t` structure which carries specific fields describing the bootloader. This structure is located at a fixed offset = sizeof(:cpp:type:`esp_image_header_t`) + sizeof(:cpp:type:`esp_image_segment_header_t`). - * ``magic_byte`` - the magic byte for the esp_bootloader_desc structure. - * ``reserved`` - reserved for the future IDF use. - * ``version`` - bootloader version, see :ref:`CONFIG_BOOTLOADER_PROJECT_VER` - * ``idf_ver`` - ESP-IDF version. ``*`` - * ``date`` and ``time`` - compile date and time. - * ``reserved2`` - reserved for the future IDF use. + * ``magic_byte``: the magic byte for the esp_bootloader_desc structure + * ``reserved``: reserved for the future IDF use + * ``version``: bootloader version, see :ref:`CONFIG_BOOTLOADER_PROJECT_VER` + * ``idf_ver``: ESP-IDF version. [#f1]_ + * ``date`` and ``time``: compile date and time + * ``reserved2``: reserved for the future IDF use -``*`` - The maximum length is 32 characters, including null-termination character. +.. [#f1] The maximum length is 32 characters, including null-termination character. To get the :cpp:type:`esp_bootloader_desc_t` structure from the running bootloader, use :cpp:func:`esp_bootloader_get_description`. diff --git a/docs/en/api-reference/system/console.rst b/docs/en/api-reference/system/console.rst index 999473c3ca6..107be3695d7 100644 --- a/docs/en/api-reference/system/console.rst +++ b/docs/en/api-reference/system/console.rst @@ -147,7 +147,12 @@ For each command, application provides the following information (in the form of - Command name (string without spaces) - Help text explaining what the command does - Optional hint text listing the arguments of the command. If application uses Argtable3 for argument parsing, hint text can be generated automatically by providing a pointer to argtable argument definitions structure instead. -- The command handler function. +- Command handler function (without context), or +- Command handler function (with context). If this function is given, an additional call to :cpp:func:`esp_console_cmd_set_context` must follow *before* the command may be called to initialize the context. + +.. note:: + + You can either use a command handler function which takes a context or a command handler function which does not take a context, not both. If you use the command handler function which takes a context, you MUST call :cpp:func:`esp_console_cmd_set_context` to initialize its context, otherwise the function may access the uninitialized context. A few other functions are provided by the command registration module: diff --git a/docs/en/api-reference/system/freertos.rst b/docs/en/api-reference/system/freertos.rst index ca1b1fcdc55..db18a581316 100644 --- a/docs/en/api-reference/system/freertos.rst +++ b/docs/en/api-reference/system/freertos.rst @@ -51,7 +51,7 @@ For the full list of user configurable kernel options, see :doc:`/api-reference/ - :ref:`CONFIG_FREERTOS_UNICORE` runs FreeRTOS only on CPU0. Note that this is **not equivalent to running Vanilla FreeRTOS**. Furthermore, this option may affect behavior of components other than :component:`freertos`. For more details regarding the effects of running FreeRTOS on a single core, refer to :ref:`freertos-smp-single-core` (if using ESP-IDF FreeRTOS) or the official Amazon SMP FreeRTOS documentation. Alternatively, users can also search for occurrences of ``CONFIG_FREERTOS_UNICORE`` in the ESP-IDF components. -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES .. note:: As {IDF_TARGET_NAME} is a single core SoC, the :ref:`CONFIG_FREERTOS_UNICORE` configuration is always set. diff --git a/docs/en/api-reference/system/index.rst b/docs/en/api-reference/system/index.rst index 3f284fcf092..9b288356d09 100644 --- a/docs/en/api-reference/system/index.rst +++ b/docs/en/api-reference/system/index.rst @@ -25,7 +25,7 @@ System API heap_debug esp_timer internal-unstable - :not CONFIG_FREERTOS_UNICORE: ipc + :SOC_HP_CPU_HAS_MULTIPLE_CORES: ipc intr_alloc log misc_system_api diff --git a/docs/en/api-reference/system/internal-unstable.rst b/docs/en/api-reference/system/internal-unstable.rst index c5b3d9491e1..67c4df0b2ee 100644 --- a/docs/en/api-reference/system/internal-unstable.rst +++ b/docs/en/api-reference/system/internal-unstable.rst @@ -1,6 +1,8 @@ Internal and Unstable APIs ========================== +:link_to_translation:`zh_CN:[中文]` + This section is listing some APIs that are internal or likely to be changed or removed in the next releases of ESP-IDF. diff --git a/docs/en/api-reference/system/intr_alloc.rst b/docs/en/api-reference/system/intr_alloc.rst index 06b7bc456df..62329d945db 100644 --- a/docs/en/api-reference/system/intr_alloc.rst +++ b/docs/en/api-reference/system/intr_alloc.rst @@ -143,7 +143,7 @@ If you have confirmed that the application is indeed running out of interrupts, .. list:: - :not CONFIG_FREERTOS_UNICORE: - On multi-core SoCs, try initializing some of the peripheral drivers from a task pinned to the second core. Interrupts are typically allocated on the same core where the peripheral driver initialization function runs. Therefore by running the initialization function on the second core, more interrupt inputs can be used. + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - On multi-core SoCs, try initializing some of the peripheral drivers from a task pinned to the second core. Interrupts are typically allocated on the same core where the peripheral driver initialization function runs. Therefore by running the initialization function on the second core, more interrupt inputs can be used. - Determine the interrupts which can tolerate higher latency, and allocate them using ``ESP_INTR_FLAG_SHARED`` flag (optionally ORed with ``ESP_INTR_FLAG_LOWMED``). Using this flag for two or more peripherals will let them use a single interrupt input, and therefore save interrupt inputs for other peripherals. See :ref:`intr-alloc-shared-interrupts` above. :not SOC_CPU_HAS_FLEXIBLE_INTC: - Some peripheral driver may default to allocating interrupts with ``ESP_INTR_FLAG_LEVEL1`` flag, so priority 2 and 3 interrupts do not get used by default. If :cpp:func:`esp_intr_dump` shows that some priority 2 or 3 interrupts are available, try changing the interrupt allocation flags when initializing the driver to ``ESP_INTR_FLAG_LEVEL2`` or ``ESP_INTR_FLAG_LEVEL3``. - Check if some of the peripheral drivers do not need to be used all the time, and initialize or deinitialize them on demand. This can reduce the number of simultaneously allocated interrupts. diff --git a/docs/en/api-reference/system/log.rst b/docs/en/api-reference/system/log.rst index 65fd2519dbe..ccc4980e9e0 100644 --- a/docs/en/api-reference/system/log.rst +++ b/docs/en/api-reference/system/log.rst @@ -1,4 +1,126 @@ -.. include:: ../../../../components/log/README.rst +Logging library +=============== + +:link_to_translation:`zh_CN:[中文]` + +Overview +-------- + +The logging library provides three ways for setting log verbosity: + +- **At compile time**: in menuconfig, set the verbosity level using the option :ref:`CONFIG_LOG_DEFAULT_LEVEL`. +- Optionally, also in menuconfig, set the maximum verbosity level using the option :ref:`CONFIG_LOG_MAXIMUM_LEVEL`. By default, this is the same as the default level, but it can be set higher in order to compile more optional logs into the firmware. +- **At runtime**: all logs for verbosity levels lower than :ref:`CONFIG_LOG_DEFAULT_LEVEL` are enabled by default. The function :cpp:func:`esp_log_level_set` can be used to set a logging level on a per-module basis. Modules are identified by their tags, which are human-readable ASCII zero-terminated strings. +- **At runtime**: if :ref:`CONFIG_LOG_MASTER_LEVEL` is enabled then a ``Master logging level`` can be set using :cpp:func:`esp_log_set_level_master`. This option adds an additional logging level check for all compiled logs. Note that this will increase application size. This feature is useful if you want to compile a lot of logs that are selectable at runtime, but also want to avoid the performance hit from looking up the tags and their log level when you don't want log output. + +There are the following verbosity levels: + +- Error (lowest) +- Warning +- Info +- Debug +- Verbose (highest) + +.. note:: + + The function :cpp:func:`esp_log_level_set` cannot set logging levels higher than specified by :ref:`CONFIG_LOG_MAXIMUM_LEVEL`. To increase log level for a specific file above this maximum at compile time, use the macro `LOG_LOCAL_LEVEL` (see the details below). + + +How to Use Logging Library +-------------------------- + +In each C file that uses logging functionality, define the TAG variable as shown below: + +.. code-block:: c + + static const char* TAG = "MyModule"; + +Then use one of logging macros to produce output, e.g: + +.. code-block:: c + + ESP_LOGW(TAG, "Baud rate error %.1f%%. Requested: %d baud, actual: %d baud", error * 100, baud_req, baud_real); + +Several macros are available for different verbosity levels: + +* ``ESP_LOGE`` - Error (lowest) +* ``ESP_LOGW`` - Warning +* ``ESP_LOGI`` - Info +* ``ESP_LOGD`` - Debug +* ``ESP_LOGV`` - Verbose (highest) + +Additionally, there are ``ESP_EARLY_LOGx`` versions for each of these macros, e.g. :c:macro:`ESP_EARLY_LOGE`. These versions have to be used explicitly in the early startup code only, before heap allocator and syscalls have been initialized. Normal ``ESP_LOGx`` macros can also be used while compiling the bootloader, but they will fall back to the same implementation as ``ESP_EARLY_LOGx`` macros. + +There are also ``ESP_DRAM_LOGx`` versions for each of these macros, e.g. :c:macro:`ESP_DRAM_LOGE`. These versions are used in some places where logging may occur with interrupts disabled or with flash cache inaccessible. Use of this macros should be as sparse as possible, as logging in these types of code should be avoided for performance reasons. + +.. note:: + + Inside critical sections interrupts are disabled so it's only possible to use ``ESP_DRAM_LOGx`` (preferred) or ``ESP_EARLY_LOGx``. Even though it's possible to log in these situations, it's better if your program can be structured not to require it. + +To override default verbosity level at file or component scope, define the ``LOG_LOCAL_LEVEL`` macro. + +At file scope, define it before including ``esp_log.h``, e.g.: + +.. code-block:: c + + #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE + #include "esp_log.h" + +At component scope, define it in the component CMakeLists: + +.. code-block:: cmake + + target_compile_definitions(${COMPONENT_LIB} PUBLIC "-DLOG_LOCAL_LEVEL=ESP_LOG_VERBOSE") + +To configure logging output per module at runtime, add calls to the function :cpp:func:`esp_log_level_set` as follows: + +.. code-block:: c + + esp_log_level_set("*", ESP_LOG_ERROR); // set all components to ERROR level + esp_log_level_set("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack + esp_log_level_set("dhcpc", ESP_LOG_INFO); // enable INFO logs from DHCP client + +.. note:: + + The "DRAM" and "EARLY" log macro variants documented above do not support per module setting of log verbosity. These macros will always log at the "default" verbosity level, which can only be changed at runtime by calling ``esp_log_level("*", level)``. + +Even when logs are disabled by using a tag name, they will still require a processing time of around 10.9 microseconds per entry. + +Master Logging Level +^^^^^^^^^^^^^^^^^^^^ + +To enable the Master logging level feature, the :ref:`CONFIG_LOG_MASTER_LEVEL` option must be enabled. It adds an additional level check for ``ESP_LOGx`` macros before calling :cpp:func:`esp_log_write`. This allows to set a higher :ref:`CONFIG_LOG_MAXIMUM_LEVEL`, but not inflict a performance hit during normal operation (only when directed). An application may set the master logging level (:cpp:func:`esp_log_set_level_master`) globally to enforce a maximum log level. ``ESP_LOGx`` macros above this level will be skipped immediately, rather than calling :cpp:func:`esp_log_write` and doing a tag lookup. It is recommended to only use this in an top-level application and not in shared components as this would override the global log level for any user using the component. By default, at startup, the Master logging level is :ref:`CONFIG_LOG_DEFAULT_LEVEL`. + +Note that this feature increases application size because the additional check is added into all ``ESP_LOGx`` macros. + +The snippet below shows how it works. Setting the Master logging level to ``ESP_LOG_NONE`` disables all logging globally. :cpp:func:`esp_log_level_set` does not currently affect logging. But after the Master logging level is released, the logs will be printed as set by :cpp:func:`esp_log_level_set`. + +.. code-block:: c + + // Master logging level is CONFIG_LOG_DEFAULT_LEVEL at start up and = ESP_LOG_INFO + ESP_LOGI("lib_name", "Message for print"); // prints a INFO message + esp_log_level_set("lib_name", ESP_LOG_WARN); // enables WARN logs from lib_name + + esp_log_set_level_master(ESP_LOG_NONE); // disables all logs globally. esp_log_level_set has no effect at the moment + + ESP_LOGW("lib_name", "Message for print"); // no print, Master logging level blocks it + esp_log_level_set("lib_name", ESP_LOG_INFO); // enable INFO logs from lib_name + ESP_LOGI("lib_name", "Message for print"); // no print, Master logging level blocks it + + esp_log_set_level_master(ESP_LOG_INFO); // enables all INFO logs globally + + ESP_LOGI("lib_name", "Message for print"); // prints a INFO message + +Logging to Host via JTAG +^^^^^^^^^^^^^^^^^^^^^^^^ + +By default, the logging library uses the vprintf-like function to write formatted output to the dedicated UART. By calling a simple API, all log output may be routed to JTAG instead, making logging several times faster. For details, please refer to Section :ref:`app_trace-logging-to-host`. + +Thread Safety +^^^^^^^^^^^^^ + +The log string is first written into a memory buffer and then sent to the UART for printing. Log calls are thread-safe, i.e., logs of different threads do not conflict with each other. + Application Example ------------------- @@ -13,6 +135,3 @@ API Reference ------------- .. include-build-file:: inc/esp_log.inc - - - diff --git a/docs/en/api-reference/system/mem_alloc.rst b/docs/en/api-reference/system/mem_alloc.rst index 2d8f0182e1f..7bfb9296d3c 100644 --- a/docs/en/api-reference/system/mem_alloc.rst +++ b/docs/en/api-reference/system/mem_alloc.rst @@ -31,7 +31,10 @@ For more details on these internal memory types, see :ref:`memory-layout`. All DRAM memory is single-byte accessible, thus all DRAM heaps possess the ``MALLOC_CAP_8BIT`` capability. Users can call ``heap_caps_get_free_size(MALLOC_CAP_8BIT)`` to get the free size of all DRAM heaps. -If ran out of ``MALLOC_CAP_8BIT``, the users can use ``MALLOC_CAP_IRAM_8BIT`` instead. In that case, IRAM can still be used as a "reserve" pool of internal memory if the users only access it in a 32-bit aligned manner, or if they enable ``CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)``. +.. only:: esp32 + + If ran out of ``MALLOC_CAP_8BIT``, the users can use ``MALLOC_CAP_IRAM_8BIT`` instead. In that case, IRAM can still be used as a "reserve" pool of internal memory if the users only access it in a 32-bit aligned manner, or if they enable ``CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)``. + When calling ``malloc()``, the ESP-IDF ``malloc()`` internally calls ``heap_caps_malloc_default(size)``. This will allocate memory with the capability ``MALLOC_CAP_DEFAULT``, which is byte-addressable. @@ -122,11 +125,11 @@ Memory allocated with ``MALLOC_CAP_32BIT`` can **only** be accessed via 32-bit r External SPI Memory ^^^^^^^^^^^^^^^^^^^ - When :doc:`external RAM ` is enabled, external SPI RAM under 4 MiB in size can be allocated using standard ``malloc`` calls, or via ``heap_caps_malloc(MALLOC_CAP_SPIRAM)``, depending on the configuration. See :ref:`external_ram_config` for more details. + When :doc:`external RAM ` is enabled, external SPI RAM can be allocated using standard ``malloc`` calls, or via ``heap_caps_malloc(MALLOC_CAP_SPIRAM)``, depending on the configuration. See :ref:`external_ram_config` for more details. .. only:: esp32 - To use the region above the 4 MiB limit, you can use the :doc:`himem API `. + On ESP32 only external SPI RAM under 4 MiB in size can be allocated this way. To use the region above the 4 MiB limit, you can use the :doc:`himem API `. Thread Safety ------------- diff --git a/docs/en/api-reference/system/misc_system_api.rst b/docs/en/api-reference/system/misc_system_api.rst index 1d6ab962bbe..68fe3d20150 100644 --- a/docs/en/api-reference/system/misc_system_api.rst +++ b/docs/en/api-reference/system/misc_system_api.rst @@ -4,7 +4,7 @@ Miscellaneous System APIs :link_to_translation:`zh_CN:[中文]` {IDF_TARGET_BASE_MAC_BLOCK: default="BLK1", esp32="BLK0"} -{IDF_TARGET_CPU_RESET_DES: default="the CPU is reset", esp32="both CPUs are reset", esp32s3="both CPUs are reset"} +{IDF_TARGET_CPU_RESET_DES: default="the CPU is reset", esp32="both CPUs are reset", esp32s3="both CPUs are reset", esp32p4="both CPUs are reset"} Software Reset -------------- @@ -90,8 +90,8 @@ In ESP-IDF, the MAC addresses for the various network interfaces are calculated .. only:: not SOC_EMAC_SUPPORTED - .. note:: - + .. note:: + Although {IDF_TARGET_NAME} has no integrated Ethernet MAC, it is still possible to calculate an Ethernet MAC address. However, this MAC address can only be used with an external ethernet interface such as an SPI-Ethernet device. See :doc:`/api-reference/network/esp_eth`. Custom Interface MAC diff --git a/docs/en/api-reference/system/pthread.rst b/docs/en/api-reference/system/pthread.rst index 783a66548a1..ec79ca8d62b 100644 --- a/docs/en/api-reference/system/pthread.rst +++ b/docs/en/api-reference/system/pthread.rst @@ -189,7 +189,7 @@ The API :cpp:func:`esp_pthread_set_cfg` defined in the ``esp_pthreads.h`` header .. list:: - Default stack size of new threads, if not specified when calling ``pthread_create()`` (overrides :ref:`CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT`). - RTOS priority of new threads (overrides :ref:`CONFIG_PTHREAD_TASK_PRIO_DEFAULT`). - :not CONFIG_FREERTOS_UNICORE: - Core affinity / core pinning of new threads (overrides :ref:`CONFIG_PTHREAD_TASK_CORE_DEFAULT`). + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - Core affinity / core pinning of new threads (overrides :ref:`CONFIG_PTHREAD_TASK_CORE_DEFAULT`). - FreeRTOS task name for new threads (overrides :ref:`CONFIG_PTHREAD_TASK_NAME_DEFAULT`) This configuration is scoped to the calling thread (or FreeRTOS task), meaning that :cpp:func:`esp_pthread_set_cfg` can be called independently in different threads or tasks. If the ``inherit_cfg`` flag is set in the current configuration then any new thread created will inherit the creator's configuration (if that thread calls ``pthread_create()`` recursively), otherwise the new thread will have the default configuration. diff --git a/docs/en/api-reference/system/random.rst b/docs/en/api-reference/system/random.rst index 0e28b99e0b8..abca5925d06 100644 --- a/docs/en/api-reference/system/random.rst +++ b/docs/en/api-reference/system/random.rst @@ -1,43 +1,45 @@ Random Number Generation ======================== -{IDF_TARGET_RF_NAME: default="Wi-Fi or Bluetooth", esp32s2="Wi-Fi"} +:link_to_translation:`zh_CN:[中文]` + +{IDF_TARGET_RF_NAME: default="Wi-Fi or Bluetooth", esp32s2="Wi-Fi", esp32h2="Bluetooth or 802.15.4 Thread/Zigbee", esp32c6="Wi-Fi or Bluetooth or 802.15.4 Thread/Zigbee"} {IDF_TARGET_RF_IS: default="are", esp32s2="is"} {IDF_TARGET_BOOTLOADER_RANDOM_INCOMPATIBLE: default="", esp32="I2S, "} -{IDF_TARGET_NAME} contains a hardware random number generator, values from it can be obtained using the APIs :cpp:func:`esp_random` and :cpp:func:`esp_fill_random`. +{IDF_TARGET_NAME} contains a hardware random number generator (RNG). You can use the APIs :cpp:func:`esp_random` and :cpp:func:`esp_fill_random` to obtained random values from it. -The hardware RNG produces true random numbers under any of the following conditions: +The hardware RNG produces true random numbers so long as one or more of the following conditions are met: -- RF subsystem is enabled (i.e., {IDF_TARGET_RF_NAME} {IDF_TARGET_RF_IS} enabled). +- RF subsystem is enabled. i.e., {IDF_TARGET_RF_NAME} {IDF_TARGET_RF_IS} enabled. - An internal entropy source has been enabled by calling :cpp:func:`bootloader_random_enable` and not yet disabled by calling :cpp:func:`bootloader_random_disable`. -- While the ESP-IDF :ref:`second-stage-bootloader` is running. This is because the default ESP-IDF bootloader implementation calls :cpp:func:`bootloader_random_enable` when the bootloader starts, and :cpp:func:`bootloader_random_disable` before executing the app. +- While the ESP-IDF :ref:`second-stage-bootloader` is running. This is because the default ESP-IDF bootloader implementation calls :cpp:func:`bootloader_random_enable` when the bootloader starts, and :cpp:func:`bootloader_random_disable` before executing the application. -When any of these conditions are true, samples of physical noise are continuously mixed into the internal hardware RNG state to provide entropy. Consult the **{IDF_TARGET_NAME} Technical Reference Manual** > **Random Number Generator (RNG)** [`PDF <{IDF_TARGET_TRM_EN_URL}#rng>`__] chapter for more details. +When any of these conditions are true, samples of physical noise are continuously mixed into the internal hardware RNG state to provide entropy. Consult the **{IDF_TARGET_NAME} Technical Reference Manual** > **Random Number Generator (RNG)** [`PDF <{IDF_TARGET_TRM_EN_URL}#rng>`__] chapter for more details. -If none of the above conditions are true, the output of the RNG should be considered pseudo-random only. +If none of the above conditions are true, the output of the RNG should be considered as pseudo-random only. Startup ------- -During startup, ESP-IDF bootloader temporarily enables a non-RF entropy source (internal reference voltage noise) that provides entropy for any first boot key generation. However, after the app starts executing then normally only pseudo-random numbers are available until {IDF_TARGET_RF_NAME} {IDF_TARGET_RF_IS} initialized. +During startup, ESP-IDF bootloader temporarily enables a non-RF entropy source (internal reference voltage noise) that provides entropy for any first boot key generation. However, after the application starts executing, then normally only pseudo-random numbers are available until {IDF_TARGET_RF_NAME} {IDF_TARGET_RF_IS} initialized. -To re-enable the entropy source temporarily during app startup, or for an application that does not use {IDF_TARGET_RF_NAME}, call the function :cpp:func:`bootloader_random_enable` to re-enable the internal entropy source. The function :cpp:func:`bootloader_random_disable` must be called to disable the entropy source again before using ADC, {IDF_TARGET_BOOTLOADER_RANDOM_INCOMPATIBLE}{IDF_TARGET_RF_NAME}. +To re-enable the entropy source temporarily during application startup, or for an application that does not use {IDF_TARGET_RF_NAME}, call the function :cpp:func:`bootloader_random_enable` to re-enable the internal entropy source. The function :cpp:func:`bootloader_random_disable` must be called to disable the entropy source again before using ADC, {IDF_TARGET_BOOTLOADER_RANDOM_INCOMPATIBLE} {IDF_TARGET_RF_NAME}. .. note:: - The entropy source enabled during the boot process by the ESP-IDF Second Stage Bootloader seeds the internal RNG state with some entropy. However, the internal hardware RNG state is not large enough to provide a continuous stream of true random numbers. This is why a continuous entropy source must be enabled whenever true random numbers are required. + The entropy source enabled during the boot process by the ESP-IDF Second Stage Bootloader seeds the internal RNG state with some entropy. However, the internal hardware RNG state is not large enough to provide a continuous stream of true random numbers. This is why a continuous entropy source must be enabled whenever true random numbers are required. .. note:: - If an application requires a source of true random numbers but it is not possible to permanently enable a hardware entropy source, consider using a strong software DRBG implementation such as the mbedTLS CTR-DRBG or HMAC-DRBG, with an initial seed of entropy from hardware RNG true random numbers. + If an application requires a source of true random numbers but cannot permanently enable a hardware entropy source, consider using a strong software DRBG implementation such as the mbedTLS CTR-DRBG or HMAC-DRBG, with an initial seed of entropy from hardware RNG true random numbers. .. only:: not esp32 Secondary Entropy ----------------- - {IDF_TARGET_NAME} RNG contains a secondary entropy source, based on sampling an asynchronous 8 MHz internal oscillator (see the Technical Reference Manual for details). This entropy source is always enabled in ESP-IDF and continuously mixed into the RNG state by hardware. In testing, this secondary entropy source was sufficient to pass the `Dieharder`_ random number test suite without the main entropy source enabled (test input was created by concatenating short samples from a continuously resetting {IDF_TARGET_NAME}). However, it is currently only guaranteed that true random numbers are produced when the main entropy source is also enabled as described above. + {IDF_TARGET_NAME} RNG contains a secondary entropy source, based on sampling an asynchronous 8 MHz internal oscillator (see the Technical Reference Manual for details). This entropy source is always enabled in ESP-IDF and is continuously mixed into the RNG state by hardware. In testing, this secondary entropy source was sufficient to pass the `Dieharder`_ random number test suite without the main entropy source enabled (test input was created by concatenating short samples from continuously resetting {IDF_TARGET_NAME}). However, it is currently only guaranteed that true random numbers are produced when the main entropy source is also enabled as described above. API Reference ------------- @@ -52,34 +54,34 @@ A compatible version of the Linux ``getrandom()`` function is also provided for .. code-block:: c - #include + #include - ssize_t getrandom(void *buf, size_t buflen, unsigned int flags); + ssize_t getrandom(void *buf, size_t buflen, unsigned int flags); This function is implemented by calling :cpp:func:`esp_fill_random` internally. -The ``flags`` argument is ignored, this function is always non-blocking but the strength of any random numbers is dependent on the same conditions described above. +The ``flags`` argument is ignored. This function is always non-blocking but the strength of any random numbers is dependent on the same conditions described above. Return value is -1 (with ``errno`` set to ``EFAULT``) if the ``buf`` argument is NULL, and equal to ``buflen`` otherwise. ``getentropy()`` ---------------- -A compatible version of the Linux ``getentropy()`` function is also provided for ease of porting: +A compatible version of the Linux ``getentropy()`` function is also provided for easy porting: .. code-block:: c - #include + #include - int getentropy(void *buffer, size_t length); + int getentropy(void *buffer, size_t length); This function is implemented by calling :cpp:func:`getrandom` internally. -Strength of any random numbers is dependent on the same conditions described above. +The strength of any random numbers is dependent on the same conditions described above. Return value is 0 on success and -1 otherwise with ``errno`` set to: - - ``EFAULT`` if the ``buffer`` argument is NULL. - - ``EIO`` if the ``length`` is more then 256. -.. _Dieharder: https://webhome.phy.duke.edu/~rgb/General/dieharder.php + - ``EFAULT`` if the ``buffer`` argument is NULL. + - ``EIO`` if the ``length`` is more then 256. +.. _Dieharder: https://webhome.phy.duke.edu/~rgb/General/dieharder.php diff --git a/docs/en/api-reference/system/sleep_modes.rst b/docs/en/api-reference/system/sleep_modes.rst index 9f3cb2bf302..4431084dc97 100644 --- a/docs/en/api-reference/system/sleep_modes.rst +++ b/docs/en/api-reference/system/sleep_modes.rst @@ -220,7 +220,7 @@ RTC peripherals or RTC memories do not need to be powered on during sleep in thi External Wakeup (``ext1``) ^^^^^^^^^^^^^^^^^^^^^^^^^^ - The RTC controller contains the logic to trigger wakeup using multiple RTC GPIOs. One of the following two logic functions can be used to trigger general ext1 wakeup: + The RTC controller contains the logic to trigger wakeup using multiple RTC GPIOs. One of the following two logic functions can be used to trigger ext1 wakeup: .. only:: esp32 @@ -248,11 +248,13 @@ RTC peripherals or RTC memories do not need to be powered on during sleep in thi gpio_pullup_dis(gpio_num); gpio_pulldown_en(gpio_num); - :cpp:func:`esp_sleep_enable_ext1_wakeup` function can be used to enable this wakeup source for general ext1 wakeup. + :cpp:func:`esp_sleep_enable_ext1_wakeup_io` function can be used to append ext1 wakeup IO and set corresponding wakeup level. + + :cpp:func:`esp_sleep_disable_ext1_wakeup_io` function can be used to remove ext1 wakeup IO. .. only:: SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN - Besides the above mentioned general ext1 wakeup, the RTC controller also contains a more powerful logic to trigger wakeup using multiple RTC GPIOs with a customized RTC IO wakeup level bitmap. This can be configured with :cpp:func`esp_sleep_enable_ext1_wakeup_with_level_mask`. + The RTC controller also supports triggering wakeup, allowing configurable IO to use different wakeup levels simultaneously. This can be configured with :cpp:func`esp_sleep_enable_ext1_wakeup_io`. .. warning:: @@ -305,6 +307,12 @@ RTC peripherals or RTC memories do not need to be powered on during sleep in thi Additionally, IOs that are powered by the VDD3P3_RTC power domain can be used to wake up the chip from Deep-sleep. The wakeup pin and wakeup trigger level can be configured by calling :cpp:func:`esp_deep_sleep_enable_gpio_wakeup`. The function will enable the Deep-sleep wakeup for the selected pin. + .. only:: esp32c6 or esp32h2 + + .. note:: + + In Light-sleep mode, setting Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP` will invalidate GPIO wakeup. + UART Wakeup (Light-sleep Only) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -312,6 +320,12 @@ When {IDF_TARGET_NAME} receives UART input from external devices, it is often ne :cpp:func:`esp_sleep_enable_uart_wakeup` function can be used to enable this wakeup source. + .. only:: esp32c6 or esp32h2 + + .. note:: + + In Light-sleep mode, setting Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP` will invalidate UART wakeup. + .. _disable_sleep_wakeup_source: Disable Sleep Wakeup Source @@ -431,20 +445,15 @@ Checking Sleep Wakeup Cause Application Example ------------------- -- :example:`protocols/sntp`: the implementation of basic functionality of Deep-sleep, where ESP module is periodically waken up to retrieve time from NTP server. -- :example:`wifi/power_save`: the usage of Wi-Fi Modem-sleep mode and automatic Light-sleep feature to maintain Wi-Fi connections. - -.. only:: SOC_BT_SUPPORTED - - - :example:`bluetooth/nimble/power_save`: the usage of Bluetooth Modem-sleep mode and automatic Light-sleep feature to maintain Bluetooth connections. - -.. only:: SOC_ULP_SUPPORTED - - - :example:`system/deep_sleep`: the usage of various Deep-sleep wakeup triggers and ULP coprocessor programming. +.. list:: -.. only:: esp32c3 or esp32c2 + - :example:`protocols/sntp`: the implementation of basic functionality of Deep-sleep, where ESP module is periodically waken up to retrieve time from NTP server. + - :example:`wifi/power_save`: the usage of Wi-Fi Modem-sleep mode and automatic Light-sleep feature to maintain Wi-Fi connections. + :SOC_BT_SUPPORTED: - :example:`bluetooth/nimble/power_save`: the usage of Bluetooth Modem-sleep mode and automatic Light-sleep feature to maintain Bluetooth connections. + :SOC_ULP_SUPPORTED: - :example:`system/deep_sleep`: the usage of various Deep-sleep wakeup triggers and ULP coprocessor programming. + :not SOC_ULP_SUPPORTED: - :example:`system/deep_sleep`: the usage of Deep-sleep wakeup triggered by various sources supported by the chip (RTC Timer, GPIO, EXT0, EXT1, Touch Sensor, etc.). + - :example:`system/light_sleep`: the usage of Light-sleep wakeup triggered by various sources supported by the chip (Timer, GPIO, Touch Sensor, etc.). - - :example:`system/deep_sleep`: the usage of Deep-sleep wakeup triggered by timer. API Reference ------------- diff --git a/docs/en/api-reference/system/system_time.rst b/docs/en/api-reference/system/system_time.rst index be1f5b2edc2..f959f1c42c5 100644 --- a/docs/en/api-reference/system/system_time.rst +++ b/docs/en/api-reference/system/system_time.rst @@ -3,12 +3,12 @@ System Time :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_RTC_CLK_FRE:default="Not updated", esp32="150 kHz", esp32s2="90 kHz", esp32s3="136 kHz", esp32c3="136 kHz", esp32c2="136 kHz", esp32c6="150 kHz", esp32h2="150 kHz"} -{IDF_TARGET_INT_OSC_FRE:default="Not updated", esp32="8.5 MHz", esp32s2="8.5 MHz", esp32s3="17.5 MHz", esp32c3="17.5 MHz", esp32c2="17.5 MHz", esp32c6="20 MHz"} +{IDF_TARGET_RTC_CLK_FRE:default="Not updated", esp32="150 kHz", esp32s2="90 kHz", esp32s3="136 kHz", esp32c3="136 kHz", esp32c2="136 kHz", esp32c6="150 kHz", esp32h2="150 kHz", esp32p4="150 kHz"} +{IDF_TARGET_INT_OSC_FRE:default="Not updated", esp32="8.5 MHz", esp32s2="8.5 MHz", esp32s3="17.5 MHz", esp32c3="17.5 MHz", esp32c2="17.5 MHz"} {IDF_TARGET_INT_OSC_FRE_DIVIDED:default="Not updated", esp32="about 33 kHz", esp32s2="about 33 kHz", esp32s3="about 68 kHz", esp32c3="about 68 kHz", esp32c2="about 68 kHz"} -{IDF_TARGET_EXT_CRYSTAL_PIN:default="Not updated", esp32="32K_XP and 32K_XN", esp32s2="XTAL_32K_P and XTAL_32K_N", esp32s3="XTAL_32K_P and XTAL_32K_N", esp32c3="XTAL_32K_P and XTAL_32K_N", esp32c6="XTAL_32K_P and XTAL_32K_N", esp32h2="XTAL_32K_P and XTAL_32K_N"} -{IDF_TARGET_EXT_OSC_PIN:default="Not updated", esp32="32K_XN", esp32s2="XTAL_32K_P", esp32s3="XTAL_32K_P", esp32c3="XTAL_32K_P", esp32c2="GPIO0", esp32c6="XTAL_32K_P"} -{IDF_TARGET_HARDWARE_DESIGN_URL:default="Not updated",esp32="`ESP32 Hardware Design Guidelines `_", esp32s2="`ESP32-S2 Hardware Design Guidelines `_", esp32s3="`ESP32-S3 Hardware Design Guidelines `_", esp32c3="`ESP32-C3 Hardware Design Guidelines `_", esp32c6="`ESP32-C6 Hardware Design Guidelines `_", esp32c2="`ESP8684 Hardware Design Guidelines `_", esp32h2="`ESP32-H2 Hardware Design Guidelines `_"} +{IDF_TARGET_EXT_CRYSTAL_PIN:default="Not updated", esp32="32K_XP and 32K_XN", esp32s2="XTAL_32K_P and XTAL_32K_N", esp32s3="XTAL_32K_P and XTAL_32K_N", esp32c3="XTAL_32K_P and XTAL_32K_N", esp32c6="XTAL_32K_P and XTAL_32K_N", esp32h2="XTAL_32K_P and XTAL_32K_N", esp32p4="XTAL_32K_P and XTAL_32K_N"} +{IDF_TARGET_EXT_OSC_PIN:default="Not updated", esp32="32K_XN", esp32s2="XTAL_32K_P", esp32s3="XTAL_32K_P", esp32c3="XTAL_32K_P", esp32c2="GPIO0", esp32c6="XTAL_32K_P", esp32h2="XTAL_32K_P", esp32p4="XTAL_32K_P"} +{IDF_TARGET_HARDWARE_DESIGN_URL:default="Not updated",esp32="`ESP32 Hardware Design Guidelines `_", esp32s2="`ESP32-S2 Hardware Design Guidelines `_", esp32s3="`ESP32-S3 Hardware Design Guidelines `_", esp32c3="`ESP32-C3 Hardware Design Guidelines `_", esp32c6="`ESP32-C6 Hardware Design Guidelines `_", esp32c2="`ESP8684 Hardware Design Guidelines `_", esp32h2="`ESP32-H2 Hardware Design Guidelines `_", esp32p4="`ESP32-P4 Hardware Design Guidelines `_"} Overview @@ -45,9 +45,9 @@ The RTC timer has the following clock sources: - ``External 32 kHz oscillator at {IDF_TARGET_EXT_OSC_PIN} pin``: Allows using 32 kHz clock generated by an external circuit. The external clock signal must be connected to the {IDF_TARGET_EXT_OSC_PIN} pin. The amplitude should be less than 1.2 V for sine wave signal and less than 1 V for square wave signal. Common mode voltage should be in the range of 0.1 < Vcm < 0.5xVamp, where Vamp stands for signal amplitude. In this case, the {IDF_TARGET_EXT_OSC_PIN} pin cannot be used as a GPIO pin. - :not esp32c6 and not esp32h2: - ``Internal {IDF_TARGET_INT_OSC_FRE} oscillator, divided by 256 ({IDF_TARGET_INT_OSC_FRE_DIVIDED})``: Provides better frequency stability than the ``Internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator`` at the expense of a higher (by 5 μA) Deep-sleep current consumption. It also does not require external components. + :not esp32c6 and not esp32h2 and not esp32p4: - ``Internal {IDF_TARGET_INT_OSC_FRE} oscillator, divided by 256 ({IDF_TARGET_INT_OSC_FRE_DIVIDED})``: Provides better frequency stability than the ``Internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator`` at the expense of a higher (by 5 μA) Deep-sleep current consumption. It also does not require external components. - :esp32c6 or esp32h2: - ``Internal 32 kHz RC oscillator`` + :esp32c6 or esp32h2 or esp32p4: - ``Internal 32 kHz RC oscillator`` The choice depends on your requirements for system time accuracy and power consumption in sleep modes. To modify the RTC clock source, set :ref:`CONFIG_RTC_CLK_SRC` in project configuration. diff --git a/docs/en/api-reference/system/ulp-lp-core.rst b/docs/en/api-reference/system/ulp-lp-core.rst index e03a1706755..bbe23831271 100644 --- a/docs/en/api-reference/system/ulp-lp-core.rst +++ b/docs/en/api-reference/system/ulp-lp-core.rst @@ -32,7 +32,7 @@ The ULP LP-Core code is compiled together with your ESP-IDF project as a separat The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The name specified here is also used by other generated artifacts such as the ELF file, map file, header file, and linker export file. The second argument specifies the ULP source files. Finally, the third argument specifies the list of component source files which include the header file to be generated. This list is needed to build the dependencies correctly and ensure that the generated header file is created before any of these files are compiled. See the section below for the concept of generated header files for ULP applications. -1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menucofig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP and must be set to a value big enough to store both the ULP LP-Core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one. +1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menucofig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP-Core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one. 2. Build the application as usual (e.g., ``idf.py app``). @@ -160,7 +160,7 @@ Application Examples * :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in deep sleep. * :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met. -* :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver from the LP core. +* :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core. * :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core. API Reference diff --git a/docs/en/api-reference/system/wdts.rst b/docs/en/api-reference/system/wdts.rst index 7f73aaf085c..f1525362b33 100644 --- a/docs/en/api-reference/system/wdts.rst +++ b/docs/en/api-reference/system/wdts.rst @@ -113,7 +113,7 @@ The following config options control TWDT configuration. They are all enabled by - :ref:`CONFIG_ESP_TASK_WDT_EN` - enables TWDT feature. If this option is disabled, TWDT cannot be used, even if initialized at runtime. - :ref:`CONFIG_ESP_TASK_WDT_INIT` - the TWDT is initialized automatically during startup. If this option is disabled, it is still possible to initialize the Task WDT at runtime by calling :cpp:func:`esp_task_wdt_init`. - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0` - {IDF_TARGET_IDLE_TASK} is subscribed to the TWDT during startup. If this option is disabled, it is still possible to subscribe the idle task by calling :cpp:func:`esp_task_wdt_init` again. - :not CONFIG_FREERTOS_UNICORE: - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` - CPU1 Idle task is subscribed to the TWDT during startup. + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` - CPU1 Idle task is subscribed to the TWDT during startup. .. note:: diff --git a/docs/en/contribute/esp-idf-tests-with-pytest.rst b/docs/en/contribute/esp-idf-tests-with-pytest.rst index 2ba0b276b82..90509dd5c87 100644 --- a/docs/en/contribute/esp-idf-tests-with-pytest.rst +++ b/docs/en/contribute/esp-idf-tests-with-pytest.rst @@ -627,6 +627,8 @@ Filter the Test Cases In other cases, pytest would run all the test cases with sdkconfig file ``sdkconfig.ci.``. +- Filter by test-case name with ``pytest -k `` to run a single test-case, e.g. ``pytest -k test_int_wdt_cache_disabled``. + Add New Markers --------------- diff --git a/docs/en/contribute/style-guide.rst b/docs/en/contribute/style-guide.rst index 4e48b5d88dd..3259b4576ce 100644 --- a/docs/en/contribute/style-guide.rst +++ b/docs/en/contribute/style-guide.rst @@ -239,7 +239,7 @@ The standard C ``assert()`` function, defined in ``assert.h`` should be used to .. note:: - When asserting a value of type ``esp_err_t``is equal to ``ESP_OK``, use the :ref:`esp-error-check-macro` instead of an ``assert()``. + When asserting a value of type ``esp_err_t`` is equal to ``ESP_OK``, use the :ref:`esp-error-check-macro` instead of an ``assert()``. It is possible to configure ESP-IDF projects with assertions disabled (see :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL`). Therefore, functions called in an ``assert()`` statement should not have side-effects. diff --git a/docs/en/get-started/esp32_output_log.inc b/docs/en/get-started/esp32_output_log.inc new file mode 100644 index 00000000000..67b270cf314 --- /dev/null +++ b/docs/en/get-started/esp32_output_log.inc @@ -0,0 +1,39 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin + esptool.py v3.0-dev + Serial port /dev/ttyUSB0 + Connecting........_ + Chip is ESP32D0WDQ6 (revision 0) + Features: WiFi, BT, Dual Core, Coding Scheme None + Crystal is 40MHz + MAC: 24:0a:c4:05:b9:14 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 5962.8 kbit/s)... + Hash of data verified. + Compressed 26096 bytes to 15408... + Writing at 0x00001000... (100 %) + Wrote 26096 bytes (15408 compressed) at 0x00001000 in 0.4 seconds (effective 546.7 kbit/s)... + Hash of data verified. + Compressed 147104 bytes to 77364... + Writing at 0x00010000... (20 %) + Writing at 0x00014000... (40 %) + Writing at 0x00018000... (60 %) + Writing at 0x0001c000... (80 %) + Writing at 0x00020000... (100 %) + Wrote 147104 bytes (77364 compressed) at 0x00010000 in 1.9 seconds (effective 615.5 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/en/get-started/esp32c2_output_log.inc b/docs/en/get-started/esp32c2_output_log.inc new file mode 100644 index 00000000000..e194676a332 --- /dev/null +++ b/docs/en/get-started/esp32c2_output_log.inc @@ -0,0 +1,41 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py esp32c2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 60m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v3.3.1 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-C2 (revision 1) + Features: Wi-Fi + Crystal is 40MHz + MAC: 10:97:bd:f0:e5:0c + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00004fff... + Flash will be erased from 0x00010000 to 0x0002ffff... + Flash will be erased from 0x00008000 to 0x00008fff... + Compressed 18192 bytes to 10989... + Writing at 0x00000000... (100 %) + Wrote 18192 bytes (10989 compressed) at 0x00000000 in 0.6 seconds (effective 248.5 kbit/s)... + Hash of data verified. + Compressed 128640 bytes to 65895... + Writing at 0x00010000... (20 %) + Writing at 0x00019539... (40 %) + Writing at 0x00020bf2... (60 %) + Writing at 0x00027de1... (80 %) + Writing at 0x0002f480... (100 %) + Wrote 128640 bytes (65895 compressed) at 0x00010000 in 1.7 seconds (effective 603.0 kbit/s)... + Hash of data verified. + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 360.1 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... \ No newline at end of file diff --git a/docs/en/get-started/esp32c3_output_log.inc b/docs/en/get-started/esp32c3_output_log.inc new file mode 100644 index 00000000000..33d56b5e488 --- /dev/null +++ b/docs/en/get-started/esp32c3_output_log.inc @@ -0,0 +1,39 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py --chip esp32c3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin + esptool.py v3.0 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-C3 + Features: Wi-Fi + Crystal is 40MHz + MAC: 7c:df:a1:40:02:a4 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 4238.1 kbit/s)... + Hash of data verified. + Compressed 18960 bytes to 11311... + Writing at 0x00000000... (100 %) + Wrote 18960 bytes (11311 compressed) at 0x00000000 in 0.3 seconds (effective 584.9 kbit/s)... + Hash of data verified. + Compressed 145520 bytes to 71984... + Writing at 0x00010000... (20 %) + Writing at 0x00014000... (40 %) + Writing at 0x00018000... (60 %) + Writing at 0x0001c000... (80 %) + Writing at 0x00020000... (100 %) + Wrote 145520 bytes (71984 compressed) at 0x00010000 in 2.3 seconds (effective 504.4 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/en/get-started/esp32c6_output_log.inc b/docs/en/get-started/esp32c6_output_log.inc new file mode 100644 index 00000000000..7c640c2a12a --- /dev/null +++ b/docs/en/get-started/esp32c6_output_log.inc @@ -0,0 +1,49 @@ +.. output_log + +.. code-block:: none + + ... + esptool esp32c6 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset --no-stub write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v4.3 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-C6 (revision v0.0) + Features: WiFi 6, BT 5 + Crystal is 40MHz + MAC: 60:55:f9:f6:01:38 + Changing baud rate to 460800 + Changed. + Enabling default SPI flash mode... + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00004fff... + Flash will be erased from 0x00010000 to 0x00028fff... + Flash will be erased from 0x00008000 to 0x00008fff... + Erasing flash... + Took 0.17s to erase flash block + Writing at 0x00000000... (5 %) + Writing at 0x00000c00... (23 %) + Writing at 0x00001c00... (47 %) + Writing at 0x00003000... (76 %) + Writing at 0x00004000... (100 %) + Wrote 17408 bytes at 0x00000000 in 0.5 seconds (254.6 kbit/s)... + Hash of data verified. + Erasing flash... + Took 0.85s to erase flash block + Writing at 0x00010000... (1 %) + Writing at 0x00014c00... (20 %) + Writing at 0x00019c00... (40 %) + Writing at 0x0001ec00... (60 %) + Writing at 0x00023c00... (80 %) + Writing at 0x00028c00... (100 %) + Wrote 102400 bytes at 0x00010000 in 3.2 seconds (253.5 kbit/s)... + Hash of data verified. + Erasing flash... + Took 0.04s to erase flash block + Writing at 0x00008000... (33 %) + Writing at 0x00008400... (66 %) + Writing at 0x00008800... (100 %) + Wrote 3072 bytes at 0x00008000 in 0.1 seconds (269.0 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... \ No newline at end of file diff --git a/docs/en/get-started/esp32h2_output_log.inc b/docs/en/get-started/esp32h2_output_log.inc new file mode 100644 index 00000000000..fe526e923d5 --- /dev/null +++ b/docs/en/get-started/esp32h2_output_log.inc @@ -0,0 +1,41 @@ +.. output_log + +.. code-block:: none + + ... + esptool esp32h2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 48m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v4.6 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-H2 (revision v0.1) + Features: BLE + Crystal is 32MHz + MAC: 60:55:f9:f7:3e:93:ff:fe + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00005fff... + Flash will be erased from 0x00010000 to 0x00034fff... + Flash will be erased from 0x00008000 to 0x00008fff... + Compressed 20880 bytes to 12788... + Writing at 0x00000000... (100 %) + Wrote 20880 bytes (12788 compressed) at 0x00000000 in 0.6 seconds (effective 297.5 kbit/s)... + Hash of data verified. + Compressed 149424 bytes to 79574... + Writing at 0x00010000... (20 %) + Writing at 0x00019959... (40 %) + Writing at 0x00020bb5... (60 %) + Writing at 0x00026d8f... (80 %) + Writing at 0x0002e60a... (100 %) + Wrote 149424 bytes (79574 compressed) at 0x00010000 in 2.1 seconds (effective 571.7 kbit/s)... + Hash of data verified. + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 539.7 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... \ No newline at end of file diff --git a/docs/en/get-started/esp32p4_output_log.inc b/docs/en/get-started/esp32p4_output_log.inc new file mode 100644 index 00000000000..69a66d4736d --- /dev/null +++ b/docs/en/get-started/esp32p4_output_log.inc @@ -0,0 +1 @@ +.. output_log \ No newline at end of file diff --git a/docs/en/get-started/esp32s2_output_log.inc b/docs/en/get-started/esp32s2_output_log.inc new file mode 100644 index 00000000000..95279df68b7 --- /dev/null +++ b/docs/en/get-started/esp32s2_output_log.inc @@ -0,0 +1,39 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py --chip esp32s2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin + esptool.py v3.0-dev + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-S2 + Features: WiFi + Crystal is 40MHz + MAC: 18:fe:34:72:50:e3 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 3851.6 kbit/s)... + Hash of data verified. + Compressed 22592 bytes to 13483... + Writing at 0x00001000... (100 %) + Wrote 22592 bytes (13483 compressed) at 0x00001000 in 0.3 seconds (effective 595.1 kbit/s)... + Hash of data verified. + Compressed 140048 bytes to 70298... + Writing at 0x00010000... (20 %) + Writing at 0x00014000... (40 %) + Writing at 0x00018000... (60 %) + Writing at 0x0001c000... (80 %) + Writing at 0x00020000... (100 %) + Wrote 140048 bytes (70298 compressed) at 0x00010000 in 1.7 seconds (effective 662.5 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/en/get-started/esp32s3_output_log.inc b/docs/en/get-started/esp32s3_output_log.inc new file mode 100644 index 00000000000..b8caeaed3cc --- /dev/null +++ b/docs/en/get-started/esp32s3_output_log.inc @@ -0,0 +1,43 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py esp32s3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v3.2-dev + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-S3 + Features: WiFi, BLE + Crystal is 40MHz + MAC: 7c:df:a1:e0:00:64 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00004fff... + Flash will be erased from 0x00010000 to 0x00039fff... + Flash will be erased from 0x00008000 to 0x00008fff... + Compressed 18896 bytes to 11758... + Writing at 0x00000000... (100 %) + Wrote 18896 bytes (11758 compressed) at 0x00000000 in 0.5 seconds (effective 279.9 kbit/s)... + Hash of data verified. + Compressed 168208 bytes to 88178... + Writing at 0x00010000... (16 %) + Writing at 0x0001a80f... (33 %) + Writing at 0x000201f1... (50 %) + Writing at 0x00025dcf... (66 %) + Writing at 0x0002d0be... (83 %) + Writing at 0x00036c07... (100 %) + Wrote 168208 bytes (88178 compressed) at 0x00010000 in 2.4 seconds (effective 569.2 kbit/s)... + Hash of data verified. + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 478.9 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/en/get-started/linux-macos-setup.rst b/docs/en/get-started/linux-macos-setup.rst index cf4c800ba6e..f462393b527 100644 --- a/docs/en/get-started/linux-macos-setup.rst +++ b/docs/en/get-started/linux-macos-setup.rst @@ -216,9 +216,19 @@ To prefer the Espressif download server when installing tools, use the following Customizing the Tools Installation Path ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The scripts introduced in this step install compilation tools required by ESP-IDF inside the user home directory: ``$HOME/.espressif`` on Linux. If you wish to install the tools into a different directory, set the environment variable ``IDF_TOOLS_PATH`` before running the installation scripts. Make sure that your user account has sufficient permissions to read and write this path. +The scripts introduced in this step install compilation tools required by ESP-IDF inside the user home directory: ``$HOME/.espressif`` on Linux. If you wish to install the tools into a different directory, **export the environment variable IDF_TOOLS_PATH before running the installation scripts**. Make sure that your user account has sufficient permissions to read and write this path. -If changing the ``IDF_TOOLS_PATH``, make sure it is set to the same value every time the Install script (``install.bat``, ``install.ps1`` or ``install.sh``) and an Export script (``export.bat``, ``export.ps1`` or ``export.sh``) are executed. +.. code-block:: bash + + export IDF_TOOLS_PATH="$HOME/required_idf_tools_path" + ./install.sh + + . ./export.sh + +If changing the ``IDF_TOOLS_PATH``, make sure it is exported in the environment before running any ESP-IDF tools or scripts. + +.. note:: + Using ``IDF_TOOLS_PATH`` in variable assignement, e.g., ``IDF_TOOLS_PATH="$HOME/required_idf_tools_path" ./install.sh``, without prior exporting, will not work in most shells because the variable assignment will not affect the current execution environment, even if it's exported/changed in the sourced script. .. _get-started-set-up-env: @@ -294,7 +304,6 @@ Related Documents establish-serial-connection flashing-troubleshooting - ../api-guides/tools/idf-monitor .. _AUR: https://wiki.archlinux.org/index.php/Arch_User_Repository .. _First Steps on ESP-IDF: ../get-started/first-steps.html diff --git a/docs/en/get-started/start-project.rst b/docs/en/get-started/start-project.rst index 89610ac9b07..1e837f8edd0 100644 --- a/docs/en/get-started/start-project.rst +++ b/docs/en/get-started/start-project.rst @@ -60,305 +60,8 @@ Normal Operation When flashing, you will see the output log similar to the following: -.. only:: esp32 - - .. code-block:: none - - ... - esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin - esptool.py v3.0-dev - Serial port /dev/ttyUSB0 - Connecting........_ - Chip is ESP32D0WDQ6 (revision 0) - Features: WiFi, BT, Dual Core, Coding Scheme None - Crystal is 40MHz - MAC: 24:0a:c4:05:b9:14 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 5962.8 kbit/s)... - Hash of data verified. - Compressed 26096 bytes to 15408... - Writing at 0x00001000... (100 %) - Wrote 26096 bytes (15408 compressed) at 0x00001000 in 0.4 seconds (effective 546.7 kbit/s)... - Hash of data verified. - Compressed 147104 bytes to 77364... - Writing at 0x00010000... (20 %) - Writing at 0x00014000... (40 %) - Writing at 0x00018000... (60 %) - Writing at 0x0001c000... (80 %) - Writing at 0x00020000... (100 %) - Wrote 147104 bytes (77364 compressed) at 0x00010000 in 1.9 seconds (effective 615.5 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - -.. only:: esp32s2 - - .. code-block:: none - - ... - esptool.py --chip esp32s2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin - esptool.py v3.0-dev - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-S2 - Features: WiFi - Crystal is 40MHz - MAC: 18:fe:34:72:50:e3 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 3851.6 kbit/s)... - Hash of data verified. - Compressed 22592 bytes to 13483... - Writing at 0x00001000... (100 %) - Wrote 22592 bytes (13483 compressed) at 0x00001000 in 0.3 seconds (effective 595.1 kbit/s)... - Hash of data verified. - Compressed 140048 bytes to 70298... - Writing at 0x00010000... (20 %) - Writing at 0x00014000... (40 %) - Writing at 0x00018000... (60 %) - Writing at 0x0001c000... (80 %) - Writing at 0x00020000... (100 %) - Wrote 140048 bytes (70298 compressed) at 0x00010000 in 1.7 seconds (effective 662.5 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - -.. only:: esp32s3 - - .. code-block:: none - - ... - esptool.py esp32s3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v3.2-dev - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-S3 - Features: WiFi, BLE - Crystal is 40MHz - MAC: 7c:df:a1:e0:00:64 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00004fff... - Flash will be erased from 0x00010000 to 0x00039fff... - Flash will be erased from 0x00008000 to 0x00008fff... - Compressed 18896 bytes to 11758... - Writing at 0x00000000... (100 %) - Wrote 18896 bytes (11758 compressed) at 0x00000000 in 0.5 seconds (effective 279.9 kbit/s)... - Hash of data verified. - Compressed 168208 bytes to 88178... - Writing at 0x00010000... (16 %) - Writing at 0x0001a80f... (33 %) - Writing at 0x000201f1... (50 %) - Writing at 0x00025dcf... (66 %) - Writing at 0x0002d0be... (83 %) - Writing at 0x00036c07... (100 %) - Wrote 168208 bytes (88178 compressed) at 0x00010000 in 2.4 seconds (effective 569.2 kbit/s)... - Hash of data verified. - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 478.9 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - - -.. only:: esp32c2 - - .. code-block:: none - - ... - esptool.py esp32c2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 60m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v3.3.1 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-C2 (revision 1) - Features: Wi-Fi - Crystal is 40MHz - MAC: 10:97:bd:f0:e5:0c - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00004fff... - Flash will be erased from 0x00010000 to 0x0002ffff... - Flash will be erased from 0x00008000 to 0x00008fff... - Compressed 18192 bytes to 10989... - Writing at 0x00000000... (100 %) - Wrote 18192 bytes (10989 compressed) at 0x00000000 in 0.6 seconds (effective 248.5 kbit/s)... - Hash of data verified. - Compressed 128640 bytes to 65895... - Writing at 0x00010000... (20 %) - Writing at 0x00019539... (40 %) - Writing at 0x00020bf2... (60 %) - Writing at 0x00027de1... (80 %) - Writing at 0x0002f480... (100 %) - Wrote 128640 bytes (65895 compressed) at 0x00010000 in 1.7 seconds (effective 603.0 kbit/s)... - Hash of data verified. - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 360.1 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - - -.. only:: esp32c3 - - .. code-block:: none - - ... - esptool.py --chip esp32c3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin - esptool.py v3.0 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-C3 - Features: Wi-Fi - Crystal is 40MHz - MAC: 7c:df:a1:40:02:a4 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 4238.1 kbit/s)... - Hash of data verified. - Compressed 18960 bytes to 11311... - Writing at 0x00000000... (100 %) - Wrote 18960 bytes (11311 compressed) at 0x00000000 in 0.3 seconds (effective 584.9 kbit/s)... - Hash of data verified. - Compressed 145520 bytes to 71984... - Writing at 0x00010000... (20 %) - Writing at 0x00014000... (40 %) - Writing at 0x00018000... (60 %) - Writing at 0x0001c000... (80 %) - Writing at 0x00020000... (100 %) - Wrote 145520 bytes (71984 compressed) at 0x00010000 in 2.3 seconds (effective 504.4 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - -.. only:: esp32c6 - - .. code-block:: none - - ... - esptool esp32c6 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset --no-stub write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v4.3 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-C6 (revision v0.0) - Features: WiFi 6, BT 5 - Crystal is 40MHz - MAC: 60:55:f9:f6:01:38 - Changing baud rate to 460800 - Changed. - Enabling default SPI flash mode... - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00004fff... - Flash will be erased from 0x00010000 to 0x00028fff... - Flash will be erased from 0x00008000 to 0x00008fff... - Erasing flash... - Took 0.17s to erase flash block - Writing at 0x00000000... (5 %) - Writing at 0x00000c00... (23 %) - Writing at 0x00001c00... (47 %) - Writing at 0x00003000... (76 %) - Writing at 0x00004000... (100 %) - Wrote 17408 bytes at 0x00000000 in 0.5 seconds (254.6 kbit/s)... - Hash of data verified. - Erasing flash... - Took 0.85s to erase flash block - Writing at 0x00010000... (1 %) - Writing at 0x00014c00... (20 %) - Writing at 0x00019c00... (40 %) - Writing at 0x0001ec00... (60 %) - Writing at 0x00023c00... (80 %) - Writing at 0x00028c00... (100 %) - Wrote 102400 bytes at 0x00010000 in 3.2 seconds (253.5 kbit/s)... - Hash of data verified. - Erasing flash... - Took 0.04s to erase flash block - Writing at 0x00008000... (33 %) - Writing at 0x00008400... (66 %) - Writing at 0x00008800... (100 %) - Wrote 3072 bytes at 0x00008000 in 0.1 seconds (269.0 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - -.. only:: esp32h2 - - .. code-block:: none - - ... - esptool esp32h2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 48m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v4.6 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-H2 (revision v0.1) - Features: BLE - Crystal is 32MHz - MAC: 60:55:f9:f7:3e:93:ff:fe - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00005fff... - Flash will be erased from 0x00010000 to 0x00034fff... - Flash will be erased from 0x00008000 to 0x00008fff... - Compressed 20880 bytes to 12788... - Writing at 0x00000000... (100 %) - Wrote 20880 bytes (12788 compressed) at 0x00000000 in 0.6 seconds (effective 297.5 kbit/s)... - Hash of data verified. - Compressed 149424 bytes to 79574... - Writing at 0x00010000... (20 %) - Writing at 0x00019959... (40 %) - Writing at 0x00020bb5... (60 %) - Writing at 0x00026d8f... (80 %) - Writing at 0x0002e60a... (100 %) - Wrote 149424 bytes (79574 compressed) at 0x00010000 in 2.1 seconds (effective 571.7 kbit/s)... - Hash of data verified. - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 539.7 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... +.. include:: {IDF_TARGET_PATH_NAME}_output_log.inc + :start-after: output_log If there are no issues by the end of the flash process, the board will reboot and start up the "hello_world" application. diff --git a/docs/en/get-started/windows-setup.rst b/docs/en/get-started/windows-setup.rst index 7c74ff8e572..b9a0ad6deea 100644 --- a/docs/en/get-started/windows-setup.rst +++ b/docs/en/get-started/windows-setup.rst @@ -132,7 +132,6 @@ For advanced users who want to customize the install process: windows-setup-update establish-serial-connection flashing-troubleshooting - ../api-guides/tools/idf-monitor .. _CMake: https://cmake.org/download/ .. _Ninja: https://ninja-build.org/ diff --git a/docs/en/hw-reference/esp32/get-started-devkitc.rst b/docs/en/hw-reference/esp32/get-started-devkitc.rst index 604b6ffc769..ec2e64baeb0 100644 --- a/docs/en/hw-reference/esp32/get-started-devkitc.rst +++ b/docs/en/hw-reference/esp32/get-started-devkitc.rst @@ -210,6 +210,7 @@ Related Documents * `ESP32 Datasheet `_ (PDF) * `ESP32-WROOM-32 Datasheet `_ (PDF) * `ESP32-WROOM-32D and ESP32-WROOM-32U Datasheet `_ (PDF) +* `ESP32-WROOM-32E and ESP32-WROOM-32UE Datasheet `_ (PDF) * `ESP32-WROOM-DA Datasheet `_ (PDF) * `ESP32-WROVER Datasheet `_ (PDF) * `ESP32-WROVER-B Datasheet `_ (PDF) diff --git a/docs/en/migration-guides/release-5.x/5.0/build-system.rst b/docs/en/migration-guides/release-5.x/5.0/build-system.rst index 76ee5454344..19b80e03787 100644 --- a/docs/en/migration-guides/release-5.x/5.0/build-system.rst +++ b/docs/en/migration-guides/release-5.x/5.0/build-system.rst @@ -9,7 +9,12 @@ ESP-IDF v5.0 no longer supports GNU make-based projects. Please follow the :ref: Update Fragment File Grammar ---------------------------- -Please follow the :ref:`migrate linker script fragment files grammar ` chapter for migrating v3.x grammar to the new one. +The former grammar, supported in ESP-IDF v3.x, was dropped in ESP-IDF v5.0. Here are a few notes on how to migrate properly: + +1. Indentation is now enforced: improperly indented fragment files generate a runtime parse exception. Although the former version did not enforce this, the previous documentation and examples demonstrated properly indented grammar. +2. Migrate the old condition entry to the ``if...elif...else`` structure for conditionals. You can refer to the :ref:`ldgen-conditional-placements` for detailed grammar. +3. Mapping fragments now requires a name like other fragment types. + Specify Component Requirements Explicitly ----------------------------------------- diff --git a/docs/en/migration-guides/release-5.x/5.0/peripherals.rst b/docs/en/migration-guides/release-5.x/5.0/peripherals.rst index e7645d8fb49..e450d3e3c64 100644 --- a/docs/en/migration-guides/release-5.x/5.0/peripherals.rst +++ b/docs/en/migration-guides/release-5.x/5.0/peripherals.rst @@ -459,7 +459,7 @@ LCD I2S Driver ---------- - The I2S driver has been redesigned (see :doc:`I2S Driver <../../../api-reference/peripherals/i2s>`), which aims to rectify the shortcomings of the driver that were exposed when supporting all the new features of ESP32-C3 & ESP32-S3. The new driver's APIs are available by including corresponding I2S mode's header files :component_file:`driver/i2s/include/driver/i2s_std.h`, :component_file:`driver/i2s/include/driver/i2s_pdm.h`, or :component_file:`driver/i2s/include/driver/i2s_tdm.h`. + The I2S driver has been redesigned (see :doc:`I2S Driver <../../../api-reference/peripherals/i2s>`), which aims to rectify the shortcomings of the driver that were exposed when supporting all the new features of ESP32-C3 & ESP32-S3. The new driver's APIs are available by including corresponding I2S mode's header files :component_file:`esp_driver_i2s/include/driver/i2s_std.h`, :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`, or :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`. Meanwhile, the old driver's APIs in :component_file:`driver/deprecated/driver/i2s.h` are still supported for backward compatibility. But there will be warnings if users keep using the old APIs in their projects, these warnings can be suppressed by the Kconfig option :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN`. @@ -489,9 +489,9 @@ LCD I2S communication modes are categorized into the following three modes. Note that: - - **Standard mode**: Standard mode always has two slots, it can support Philips, MSB, and PCM (short frame sync) formats. Please refer to :component_file:`driver/i2s/include/driver/i2s_std.h` for more details. - - **PDM mode**: PDM mode only supports two slots with 16-bit data width, but the configurations of PDM TX and PDM RX are slightly different. For PDM TX, the sample rate can be set by :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate`, and its clock frequency depends on the up-sampling configuration. For PDM RX, the sample rate can be set by :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate`, and its clock frequency depends on the down-sampling configuration. Please refer to :component_file:`driver/i2s/include/driver/i2s_pdm.h` for details. - - **TDM mode**: TDM mode can support up to 16 slots. It can work in Philips, MSB, PCM (short frame sync), and PCM (long frame sync) formats. Please refer to :component_file:`driver/i2s/include/driver/i2s_tdm.h` for details. + - **Standard mode**: Standard mode always has two slots, it can support Philips, MSB, and PCM (short frame sync) formats. Please refer to :component_file:`esp_driver_i2s/include/driver/i2s_std.h` for more details. + - **PDM mode**: PDM mode only supports two slots with 16-bit data width, but the configurations of PDM TX and PDM RX are slightly different. For PDM TX, the sample rate can be set by :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate`, and its clock frequency depends on the up-sampling configuration. For PDM RX, the sample rate can be set by :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate`, and its clock frequency depends on the down-sampling configuration. Please refer to :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h` for details. + - **TDM mode**: TDM mode can support up to 16 slots. It can work in Philips, MSB, PCM (short frame sync), and PCM (long frame sync) formats. Please refer to :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h` for details. When allocating a new channel in a specific mode, users should initialize that channel by its corresponding function. It is strongly recommended to use the helper macros to generate the default configurations in case the default values are changed in the future. diff --git a/docs/en/migration-guides/release-5.x/5.2/index.rst b/docs/en/migration-guides/release-5.x/5.2/index.rst index c497099d32b..eea59de0436 100644 --- a/docs/en/migration-guides/release-5.x/5.2/index.rst +++ b/docs/en/migration-guides/release-5.x/5.2/index.rst @@ -9,5 +9,6 @@ Migration from 5.1 to 5.2 gcc peripherals protocols + storage system - wifi + :SOC_WIFI_SUPPORTED: wifi diff --git a/docs/en/migration-guides/release-5.x/5.2/storage.rst b/docs/en/migration-guides/release-5.x/5.2/storage.rst new file mode 100644 index 00000000000..31bda417007 --- /dev/null +++ b/docs/en/migration-guides/release-5.x/5.2/storage.rst @@ -0,0 +1,11 @@ +Storage +======= + +:link_to_translation:`zh_CN:[中文]` + +NVS Encryption +-------------- + +- For SoCs with the HMAC peripheral (``SOC_HMAC_SUPPORTED``), turning on :doc:`../../../security/flash-encryption` will no longer automatically turn on :doc:`../../../api-reference/storage/nvs_encryption`. +- You will need to explicitly turn on NVS encryption and select the required scheme (flash encryption-based or HMAC peripheral-based). You can select the HMAC peripheral-based scheme (:ref:`CONFIG_NVS_SEC_KEY_PROTECTION_SCHEME`), even if flash encryption is not enabled. +- SoCs without the HMAC peripheral will still automatically turn on NVS encryption when flash encryption is enabled. diff --git a/docs/en/migration-guides/release-5.x/5.2/system.rst b/docs/en/migration-guides/release-5.x/5.2/system.rst index 1cf76ae4beb..916ad605f39 100644 --- a/docs/en/migration-guides/release-5.x/5.2/system.rst +++ b/docs/en/migration-guides/release-5.x/5.2/system.rst @@ -11,4 +11,13 @@ Task Snapshot The Task Snapshot API has been made private due to a lack of a practical way for the API to be used from user code (the scheduler must be halted before the API can be called). -As a result, the ``#include "freertos/task_snapshot.h"`` include path has been deprecated. \ No newline at end of file +.. only:: CONFIG_IDF_TARGET_ARCH_XTENSA + + Xtensa + ------ + + A number of legacy include paths for Xtensa headers have been deprecated: + + - ``#include "freertos/xtensa_api.h"`` is deprecated, please use ``#include "xtensa_api.h"`` instead. + - ``#include "freertos/xtensa_context.h"`` is deprecated, please use ``#include "xtensa_context.h"`` instead. + - ``#include "freertos/xtensa_timer.h"`` is deprecated, please use ``#include "xtensa_timer.h"`` instead. diff --git a/docs/en/migration-guides/release-5.x/5.3/index.rst b/docs/en/migration-guides/release-5.x/5.3/index.rst index caccc541875..c07bfca1c8a 100644 --- a/docs/en/migration-guides/release-5.x/5.3/index.rst +++ b/docs/en/migration-guides/release-5.x/5.3/index.rst @@ -7,3 +7,6 @@ Migration from 5.2 to 5.3 :maxdepth: 1 peripherals + security + storage + system diff --git a/docs/en/migration-guides/release-5.x/5.3/peripherals.rst b/docs/en/migration-guides/release-5.x/5.3/peripherals.rst index 7321835ee14..1ace4952cf3 100644 --- a/docs/en/migration-guides/release-5.x/5.3/peripherals.rst +++ b/docs/en/migration-guides/release-5.x/5.3/peripherals.rst @@ -3,11 +3,27 @@ Peripherals :link_to_translation:`zh_CN:[中文]` +Drivers +------- + In order to control the dependence of other components on drivers at a smaller granularity, the original peripheral drivers under the `driver`` component were split into separate components: - `esp_driver_gptimer` - Driver for general purpose timers - `esp_driver_pcnt` - Driver for pulse counter - `esp_driver_gpio` - Driver for GPIO +- `esp_driver_spi` - Driver for GPSPI +- `esp_driver_mcpwm` - Driver for Motor Control PWM +- `esp_driver_sdmmc` - Driver for SDMMC +- `esp_driver_sdspi` - Driver for SDSPI +- `esp_driver_sdio` - Driver for SDIO +- `esp_driver_ana_cmpr` - Driver for Analog Comparator +- `esp_driver_i2s` - Driver for I2S +- `esp_driver_dac` - Driver for DAC +- `esp_driver_rmt` - Driver for RMT +- `esp_driver_tsens` - Driver for Temperature Sensor +- `esp_driver_sdm` - Driver for Sigma-Delta Modulator +- `esp_driver_i2c` - Driver for I2C +- `esp_driver_uart` - Driver for UART For compatibility, the original `driver`` component is still treated as an all-in-one component by registering these `esp_driver_xyz`` components as its public dependencies. In other words, you do not need to modify the CMake file of an existing project, but you now have a way to specify the specific peripheral driver that your project depends on. @@ -28,3 +44,11 @@ Should be changed to: archive: libesp_driver_gpio.a entries: gpio (noflash) + + +Secure Element +-------------- + +The ATECC608A secure element interfacing example has been moved to `ESP Cryptoauthlib Repository `_ on GitHub. + +This example is also part of the `esp-cryptoauthlib `_ in the component manager registry. diff --git a/docs/en/migration-guides/release-5.x/5.3/security.rst b/docs/en/migration-guides/release-5.x/5.3/security.rst new file mode 100644 index 00000000000..fcb1143db50 --- /dev/null +++ b/docs/en/migration-guides/release-5.x/5.3/security.rst @@ -0,0 +1,14 @@ +Security +======== + +:link_to_translation:`zh_CN:[中文]` + +.. only:: SOC_FLASH_ENC_SUPPORTED + + Platform security features + -------------------------- + + When flash encryption is enabled, encrypt only the app image that is present partition of type app, instead of encrypting the whole partition. This can help to optimize the encryption time required during the first boot. + + This could be configured using the config ``CONFIG_SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART``, which is enabled by default from ESP-IDF v5.3 + and is disabled for all earlier releases to avoid any breaking behaviour. diff --git a/docs/en/migration-guides/release-5.x/5.3/storage.rst b/docs/en/migration-guides/release-5.x/5.3/storage.rst new file mode 100644 index 00000000000..77b01c0b74b --- /dev/null +++ b/docs/en/migration-guides/release-5.x/5.3/storage.rst @@ -0,0 +1,18 @@ +Storage +======= + +:link_to_translation:`zh_CN:[中文]` + +VFS +--- + +The UART implementation of VFS operators has been moved from `vfs` component to `esp_driver_uart` component. + +APIs with `esp_vfs_dev_uart_` prefix are all deprecated, replaced with new APIs in `uart_vfs.h` starting with `uart_vfs_dev_` prefix. Specifically, +- ``esp_vfs_dev_uart_register`` has been renamed to ``uart_vfs_dev_register`` +- ``esp_vfs_dev_uart_port_set_rx_line_endings`` has been renamed to ``uart_vfs_dev_port_set_rx_line_endings`` +- ``esp_vfs_dev_uart_port_set_tx_line_endings`` has been renamed to ``uart_vfs_dev_port_set_tx_line_endings`` +- ``esp_vfs_dev_uart_use_nonblocking`` has been renamed to ``uart_vfs_dev_use_nonblocking`` +- ``esp_vfs_dev_uart_use_driver`` has been renamed to ``uart_vfs_dev_use_driver`` + +For compatibility, `vfs` component still registers `esp_driver_uart` as its private dependency. In other words, you do not need to modify the CMake file of an existing project. diff --git a/docs/en/migration-guides/release-5.x/5.3/system.rst b/docs/en/migration-guides/release-5.x/5.3/system.rst new file mode 100644 index 00000000000..215b428992e --- /dev/null +++ b/docs/en/migration-guides/release-5.x/5.3/system.rst @@ -0,0 +1,31 @@ +System +====== + +:link_to_translation:`zh_CN:[中文]` + +Power Management +----------------------- + +* ``esp_sleep_enable_ext1_wakeup_with_level_mask`` is deprecated, use :cpp:func:`esp_sleep_enable_ext1_wakeup_io` and :cpp:func:`esp_sleep_disable_ext1_wakeup_io` instead. + +Unit Testing +----------------------- + +In the past versions of Unity framework, it was possible to omit a semicolon at the end of a ``TEST_ASSERT_*`` macro statement. This is no longer the case in the newer version of Unity, used in IDF v5.3. + +For example, the following code: + +.. code-block:: c + + TEST_ASSERT(some_func() == ESP_OK) + +will now result in a compilation error. To fix this, add a semicolon at the end of the statement: + + TEST_ASSERT(some_func() == ESP_OK); + +Partition Table +--------------- + +Partition Table generation tool has been fixed to ensure that the size of partition of type ``app`` is having flash sector (minimum erase size) aligned size (please see :ref:`partition-offset-and-size`). If the partition does not have aligned size, partition table generator tool will raise an error. This fix ensures that OTA updates for a case where the file size is close or equal to the size of partition works correctly (erase operation does not go beyond the partition size). + +In case you have the ``app`` partition size which is not a multiple of the 4 KB then please note that while migrating to ESP-IDF 5.3, you must align this size to its lower 4 KB boundary for the build to succeed. This does not impact the partition table for existing devices as such but ensures that generated firmware size remains within the OTA update capablilty limit. diff --git a/docs/en/security/flash-encryption.rst b/docs/en/security/flash-encryption.rst index f8f93249f1c..22db63990e2 100644 --- a/docs/en/security/flash-encryption.rst +++ b/docs/en/security/flash-encryption.rst @@ -929,6 +929,7 @@ On the first boot, the flash encryption process burns by default the following e :SOC_EFUSE_DIS_PAD_JTAG and SOC_EFUSE_DIS_USB_JTAG: - ``DIS_PAD_JTAG`` and ``DIS_USB_JTAG`` which disables JTAG. :SOC_EFUSE_HARD_DIS_JTAG and SOC_EFUSE_DIS_USB_JTAG: - ``HARD_DIS_JTAG`` and ``DIS_USB_JTAG`` which disables JTAG. - ``DIS_DIRECT_BOOT`` (old name ``DIS_LEGACY_SPI_BOOT``) which disables direct boot mode + :SOC_EFUSE_DIS_DOWNLOAD_MSPI: - ``DIS_DOWNLOAD_MSPI`` which disables the MSPI access in download mode. However, before the first boot you can choose to keep any of these features enabled by burning only selected eFuses and write-protect the rest of eFuses with unset value 0. For example: diff --git a/docs/en/security/host-based-security-workflows.rst b/docs/en/security/host-based-security-workflows.rst index 5753572f92a..96855700d37 100644 --- a/docs/en/security/host-based-security-workflows.rst +++ b/docs/en/security/host-based-security-workflows.rst @@ -290,6 +290,7 @@ In this case, all the eFuses related to flash encryption are written with help o :SOC_EFUSE_DIS_USB_JTAG: - ``DIS_USB_JTAG``: Disable USB switch to JTAG :SOC_EFUSE_DIS_PAD_JTAG: - ``DIS_PAD_JTAG``: Disable JTAG permanently :not esp32: - ``DIS_DOWNLOAD_MANUAL_ENCRYPT``: Disable UART bootloader encryption access + :SOC_EFUSE_DIS_DOWNLOAD_MSPI: - ``DIS_DOWNLOAD_MSPI``: Disable the MSPI access in download mode The respective eFuses can be burned by running: diff --git a/docs/en/security/secure-boot-v1.rst b/docs/en/security/secure-boot-v1.rst index c7afbc70209..598e8614310 100644 --- a/docs/en/security/secure-boot-v1.rst +++ b/docs/en/security/secure-boot-v1.rst @@ -1,104 +1,112 @@ Secure Boot =========== +:link_to_translation:`zh_CN:[中文]` + .. important:: - All references in this document are related to Secure Boot V1 (The AES based Secure Boot Scheme). ESP32 Revision 3 onwards, the preferred secure boot scheme is :doc:`secure-boot-v2`. - Please refer to Secure Boot V2 document for ESP32 Revision 3 or ESP32-S2. + All references in this document are related to Secure Boot V1, i.e., the AES-based Secure Boot Scheme. For ESP32 v3.0 onwards, the preferred secure boot scheme is :doc:`secure-boot-v2`. + + Please refer to :doc:`secure-boot-v2` for ESP32 v3.0 or ESP32-S2. -Secure Boot is a feature for ensuring only your code can run on the chip. Data loaded from flash is verified on each reset. +Secure boot is a feature for ensuring only your code can run on the chip. Data loaded from flash is verified on each reset. -Secure Boot is separate from the :doc:`flash-encryption` feature, and you can use secure boot without encrypting the flash contents. However, for a secure environment both should be used simultaneously. See :ref:`secure-boot-and-flash-encr` for more details. +Secure boot is separate from the :doc:`flash-encryption` feature, and you can use secure boot without encrypting the flash contents. However, for a secure environment, both should be used simultaneously. See :ref:`secure-boot-and-flash-encr` for more details. .. important:: - Enabling secure boot limits your options for further updates of your {IDF_TARGET_NAME}. Make sure to read this document throughly and understand the implications of enabling secure boot. + Enabling secure boot limits your options for further updates of your {IDF_TARGET_NAME}. Make sure to read this document thoroughly and understand the implications of enabling secure boot. + Background ---------- -- Most data is stored in flash. Flash access does not need to be protected from physical access in order for secure boot to function, because critical data is stored (non-software-accessible) in Efuses internal to the chip. +- Most data is stored in flash. Flash access does not need to be protected from physical access for secure boot to function, because critical data is stored in eFuses internal to the chip and is non-software-accessible. + +- eFuses are used to store the secure boot information permanently. The secure boot key is stored in eFuse BLOCK2, and also, a single eFuse bit ABS_DONE_0 is burned, or written to 1, to permanently enable secure boot on the chip. For more details on eFuses, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (EFUSE)* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. -- Efuses are used to store the secure bootloader key (in efuse BLOCK2), and also a single Efuse bit (ABS_DONE_0) is burned (written to 1) to permanently enable secure boot on the chip. For more details on eFuses, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. +- To understand the secure boot process, please familiarize yourself with the standard :doc:`../api-guides/startup`. -- To understand the secure boot process, first familiarise yourself with the standard :doc:`../api-guides/startup`. +- Both stages of the boot process, including initial software bootloader load and subsequent partition & app loading, are verified by the secure boot process, in a chain of trust relationship. -- Both stages of the boot process (initial software bootloader load, and subsequent partition & app loading) are verified by the secure boot process, in a "chain of trust" relationship. Secure Boot Process Overview ---------------------------- -This is a high level overview of the secure boot process. Step by step instructions are supplied under :ref:`secure-boot-howto`. Further in-depth details are supplied under :ref:`secure-boot-technical-details`: +This is a high-level overview of the secure boot process. Step-by-step instructions are supplied under :ref:`secure-boot-how-to`. Further in-depth details are supplied under :ref:`secure-boot-technical-details`: -1. The options to enable secure boot are provided in the :ref:`project-configuration-menu`, under "Secure Boot Configuration". +1. The options to enable secure boot are provided in the :ref:`project-configuration-menu`, under ``Secure Boot Configuration``. -2. Secure Boot defaults to signing images and partition table data during the build process. The "Secure boot private signing key" config item is a file path to a ECDSA public/private key pair in a PEM format file. +2. Secure boot defaults to signing images and partition table data during the build process. The ``Secure boot private signing key`` config item is a file path to an ECDSA public/private key pair in a PEM format file. -3. The software bootloader image is built by esp-idf with secure boot support enabled and the public key (signature verification) portion of the secure boot signing key compiled in. This software bootloader image is flashed at offset 0x1000. +3. The software bootloader image is built by ESP-IDF with secure boot support enabled, and the public key for signature verification is integrated into the bootloader image. This software bootloader image is flashed at offset 0x1000. -4. On first boot, the software bootloader follows the following process to enable secure boot: +4. On the first boot, the software bootloader follows the following process to enable a secure boot: - - Hardware secure boot support generates a device secure bootloader key (generated via hardware RNG, then stored read/write protected in efuse), and a secure digest. The digest is derived from the key, an IV, and the bootloader image contents. + - Hardware secure boot support generates a device-secure bootloader key and a secure digest. The secure bootloader key is generated with the help of the hardware RNG, and then stored in eFuse with read and write protection enabled. The digest is derived from the key, an initialization vector (IV), and the bootloader image contents. - The secure digest is flashed at offset 0x0 in the flash. - - Depending on Secure Boot Configuration, efuses are burned to disable JTAG and the ROM BASIC interpreter (it is strongly recommended these options are turned on.) - - Bootloader permanently enables secure boot by burning the ABS_DONE_0 efuse. The software bootloader then becomes protected (the chip will only boot a bootloader image if the digest matches.) + - Depending on Secure Boot Configuration, eFuses are burned to disable JTAG and the ROM BASIC interpreter. It is **strongly recommended** that these options are turned on. + - Bootloader permanently enables secure boot by burning the ABS_DONE_0 eFuse. The software bootloader then becomes protected. After this point, the chip will only boot a bootloader image if the digest matches. -5. On subsequent boots the ROM bootloader sees that the secure boot efuse is burned, reads the saved digest at 0x0 and uses hardware secure boot support to compare it with a newly calculated digest. If the digest does not match then booting will not continue. The digest and comparison are performed entirely by hardware, and the calculated digest is not readable by software. For technical details see :ref:`secure-boot-hardware-support`. +5. On subsequent boots, the ROM bootloader sees that the secure boot eFuse is burned, reads the saved digest at 0x0, and uses hardware secure boot support to compare it with a newly calculated digest. If the digest does not match then booting will not continue. The digest and comparison are performed entirely by hardware, and the calculated digest is not readable by software. For technical details see :ref:`secure-boot-hardware-support`. + +6. When running in secure boot mode, the software bootloader uses the secure boot signing key, the public key of which is embedded in the bootloader itself and therefore validated as part of the bootloader, to verify the signature appended to all subsequent partition tables and app images before they are booted. -6. When running in secure boot mode, the software bootloader uses the secure boot signing key (the public key of which is embedded in the bootloader itself, and therefore validated as part of the bootloader) to verify the signature appended to all subsequent partition tables and app images before they are booted. Keys ---- The following keys are used by the secure boot process: -- "secure bootloader key" is a 256-bit AES key that is stored in Efuse block 2. The bootloader can generate this key itself from the internal hardware random number generator, the user does not need to supply it (it is optionally possible to supply this key, see :ref:`secure-boot-reflashable`). The Efuse holding this key is read & write protected (preventing software access) before secure boot is enabled. +- The secure bootloader key is a 256-bit AES key that is stored in eFuse block 2. The bootloader can generate this key itself from the internal hardware random number generator, and you do not need to supply it. It is optionally possible to supply this key, see :ref:`secure-boot-reflashable`. The eFuse holding this key is read and write protected before the secure boot is enabled to prevent further software access of the key. - - By default, the Efuse Block 2 Coding Scheme is "None" and a 256 bit key is stored in this block. On some {IDF_TARGET_NAME}s, the Coding Scheme is set to 3/4 Encoding (CODING_SCHEME efuse has value 1) and a 192 bit key must be stored in this block. + - By default, the eFuse Block 2 Coding Scheme is ``None`` and a 256-bit key is stored in this block. On some versions of {IDF_TARGET_NAME}s, the Coding Scheme is set to ``3/4 Encoding`` with CODING_SCHEME eFuse has value 1, and a 192-bit key must be stored in this block. .. only:: esp32 - For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *System Parameter coding_scheme* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. + For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (EFUSE)* > *System Parameter coding_scheme* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. + + The algorithm operates on a 256-bit key in all cases. 192-bit keys are extended by repeating some bits, see :ref:`secure-bootloader-digest-algorithm`. - The algorithm operates on a 256 bit key in all cases, 192 bit keys are extended by repeating some bits (:ref:`secure-bootloader-digest-algorithm`). +- ``secure boot signing key`` is a standard ECDSA public/private key pair in PEM format, see :ref:`secure-boot-image-signing-algorithm`. -- "secure boot signing key" is a standard ECDSA public/private key pair (see :ref:`secure-boot-image-signing-algorithm`) in PEM format. + - The public key from this key pair is compiled into the software bootloader. It is only used for signature verification purposes and not signature creation. This public key is used to verify the second stage of booting, including the partition table and app image, before booting continues. The public key can be freely distributed; it does not need to be kept secret. - - The public key from this key pair (for signature verification but not signature creation) is compiled into the software bootloader and used to verify the second stage of booting (partition table, app image) before booting continues. The public key can be freely distributed, it does not need to be kept secret. + - The private key from this key pair **must be securely kept private**, as anyone who has this key can authenticate to any bootloader that is configured with a secure boot and the matching public key. - - The private key from this key pair *must be securely kept private*, as anyone who has this key can authenticate to any bootloader that is configured with secure boot and the matching public key. Bootloader Size --------------- -Enabling Secure boot and/or flash encryption will increase the size of bootloader, which might require updating partition table offset. See :ref:`bootloader-size`. +Enabling secure boot and/or flash encryption will increase the size of the bootloader, which might require updating the partition table offset. See :ref:`bootloader-size`. -.. _secure-boot-howto: -How To Enable Secure Boot +.. _secure-boot-how-to: + +How to Enable Secure Boot ------------------------- -1. Open the :ref:`project-configuration-menu`, navigate to "Secure Boot Configuration" and select the option "One-time Flash". (To understand the alternative "Reflashable" choice, see :ref:`secure-boot-reflashable`.) +1. Open the :ref:`project-configuration-menu`, navigate to ``Secure Boot Configuration`` and select the option ``One-time Flash``. To understand the alternative ``Reflashable`` option, see :ref:`secure-boot-reflashable`. -2. Select a name for the secure boot signing key. This option will appear after secure boot is enabled. The file can be anywhere on your system. A relative path will be evaluated from the project directory. The file does not need to exist yet. +2. Select a name for the secure boot signing key. This option will appear after secure boot is enabled, and the key file can be anywhere on your system. If you opt for a relative path, it will be evaluated based on the project directory. Importantly, there's no need for the file to exist when making this selection. -3. Set other menuconfig options (as desired). Pay particular attention to the "Bootloader Config" options, as you can only flash the bootloader once. Then exit menuconfig and save your configuration +3. Set other menuconfig options as desired. Pay particular attention to the ``Bootloader Config`` options, as you can only flash the bootloader once. Then exit menuconfig and save your configuration. -4. The first time you run ``make``, if the signing key is not found then an error message will be printed with a command to generate a signing key via ``espsecure.py generate_signing_key``. +4. When you run ``idf.py build`` for the first time, if the signing key is not found, then an error message will be printed with a command to generate a signing key via ``espsecure.py generate_signing_key``. .. important:: - A signing key generated this way will use the best random number source available to the OS and its Python installation (`/dev/urandom` on OSX/Linux and `CryptGenRandom()` on Windows). If this random number source is weak, then the private key will be weak. + A signing key generated this way will use the best random number source available to the OS and its Python installation, i.e., `/dev/urandom` on OSX/Linux and `CryptGenRandom()` on Windows. If this random number source is weak, then the private key will be weak. .. important:: - For production environments, we recommend generating the keypair using openssl or another industry standard encryption program. See :ref:`secure-boot-generate-key` for more details. + For production environments, we recommend generating the key pair using OpenSSL or another industry-standard encryption program. See :ref:`secure-boot-generate-key` for more details. -5. Run ``idf.py bootloader`` to build a secure boot enabled bootloader. The build output will include a prompt for a flashing command, using ``esptool.py write_flash``. +5. Run ``idf.py bootloader`` to build a secure boot-enabled bootloader. The build output will include a prompt for a flashing command, using ``esptool.py write_flash``. .. _secure-boot-resume-normal-flashing: -6. When you are ready to flash the bootloader, run the specified command (you have to enter it yourself, this step is not performed by make) and then wait for flashing to complete. **Remember this is a one time flash, you can not change the bootloader after this!**. +6. When you are ready to flash the bootloader, run the specified command. You have to enter it yourself, this step is not performed by make. And then wait for flashing to complete. **Remember this is a one-time flash, you can not change the bootloader after this!** 7. Run ``idf.py flash`` to build and flash the partition table and the just-built app image. The app image will be signed using the signing key you generated in step 4. @@ -110,90 +118,101 @@ How To Enable Secure Boot .. note:: - Secure boot will not be enabled until after a valid partition table and app image have been flashed. This is to prevent accidents before the system is fully configured. + The secure boot will not be enabled until after a valid partition table and app image have been flashed. This is to prevent accidents before the system is fully configured. .. note:: - If the {IDF_TARGET_NAME} is reset or powered down during the first boot, it will start the process again on the next boot. + If {IDF_TARGET_NAME} is reset or powered down during the first boot, it will start the process again on the next boot. + +9. On subsequent boots, the secure boot hardware will verify the software bootloader has not changed using the secure bootloader key, and then the software bootloader will verify the signed partition table and app image using the public key portion of the secure boot signing key. -9. On subsequent boots, the secure boot hardware will verify the software bootloader has not changed (using the secure bootloader key) and then the software bootloader will verify the signed partition table and app image (using the public key portion of the secure boot signing key). .. _secure-boot-reflashable: -Re-Flashable Software Bootloader --------------------------------- +Reflashable Software Bootloader +------------------------------- -Configuration "Secure Boot: One-Time Flash" is the recommended configuration for production devices. In this mode, each device gets a unique key that is never stored outside the device. +Configuration ``Secure Boot: One-Time Flash`` is the recommended configuration for production devices. In this mode, each device gets a unique key that is never stored outside the device. However, an alternative mode :ref:`CONFIG_SECURE_BOOTLOADER_MODE` is also available. This mode allows you to supply a binary key file that is used for the secure bootloader key. As you have the key file, you can generate new bootloader images and secure boot digests for them. -In the esp-idf build process, this 256-bit key file is derived from the ECDSA app signing key generated by the user (see the :ref:`secure-boot-generate-key` step below). This private key's SHA-256 digest is used as the secure bootloader key in efuse (as-is for Coding Scheme None, or truncate to 192 bytes for 3/4 Encoding). This is a convenience so you only need to generate/protect a single private key. +In the ESP-IDF build process, this 256-bit key file is derived from the ECDSA app signing key generated by the user, see the :ref:`secure-boot-generate-key` step below. This private key's SHA-256 digest is used as the secure bootloader key in eFuse, as-is for Coding Scheme ``None``, or truncated to 192 bytes for ``3/4 Encoding``. This is a convenience so you only need to generate or protect a single private key. .. note:: - Although it is possible, we strongly recommend not generating one secure boot key and flashing it to every device in a production environment. The "One-Time Flash" option is recommended for production environments. + Although it is possible, we strongly recommend not generating one secure boot key and flashing it to every device in a production environment. The ``One-Time Flash`` option is recommended for production environments. To enable a reflashable bootloader: -1. In the :ref:`project-configuration-menu`, select "Bootloader Config" > :ref:`CONFIG_SECURE_BOOT` > CONFIG_SECURE_BOOT_V1_ENABLED > :ref:`CONFIG_SECURE_BOOTLOADER_MODE` > Reflashable. +1. In the :ref:`project-configuration-menu`, select ``Bootloader Config`` > :ref:`CONFIG_SECURE_BOOT` > ``CONFIG_SECURE_BOOT_V1_ENABLED`` > :ref:`CONFIG_SECURE_BOOTLOADER_MODE` > ``Reflashable``. 2. If necessary, set the :ref:`CONFIG_SECURE_BOOTLOADER_KEY_ENCODING` based on the coding scheme used by the device. The coding scheme is shown in the ``Features`` line when ``esptool.py`` connects to the chip, or in the ``espefuse.py summary`` output. -3. Please follow the steps shown in :ref:`secure-boot-generate-key` to generate signing key. Path of the generated key file must be specified in "Secure Boot Configuration" menu. +3. Please follow the steps shown in :ref:`secure-boot-generate-key` to generate the signing key. The path of the generated key file must be specified in the ``Secure Boot Configuration`` menu. -4. Run ``idf.py bootloader``. A binary key file will be created, derived from the private key that is used for signing. Two sets of flashing steps will be printed - the first set of steps includes an ``espefuse.py burn_key secure_boot_v1 path_to/secure-bootloader-key-xxx.bin`` command which is used to write the bootloader key to efuse. (Flashing this key is a one-time-only process.) The second set of steps can be used to reflash the bootloader with a pre-calculated digest (generated during the build process). +4. Run ``idf.py bootloader``. A binary key file will be created, derived from the private key that is used for signing. Two sets of flashing steps will be printed. The first set of steps includes an ``espefuse.py burn_key secure_boot_v1 path_to/secure-bootloader-key-xxx.bin`` command which is used to write the bootloader key to eFuse. Flashing this key is a one-time-only process. The second set of steps can be used to reflash the bootloader with a pre-calculated digest, which is generated during the build process. 5. Resume from :ref:`Step 6 of the one-time flashing process `, to flash the bootloader and enable secure boot. Watch the console log output closely to ensure there were no errors in the secure boot configuration. + .. _secure-boot-generate-key: Generating Secure Boot Signing Key ---------------------------------- -The build system will prompt you with a command to generate a new signing key via ``espsecure.py generate_signing_key``. This uses the python-ecdsa library, which in turn uses Python's os.urandom() as a random number source. +The build system will prompt you with a command to generate a new signing key via ``espsecure.py generate_signing_key``. This uses the python-ecdsa library, which in turn uses Python's ``os.urandom()`` as a random number source. + +The strength of the signing key is proportional to the random number source of the system, and the correctness of the algorithm used. For production devices, we recommend generating signing keys from a system with a quality entropy source and using the best available EC key generation utilities. -The strength of the signing key is proportional to (a) the random number source of the system, and (b) the correctness of the algorithm used. For production devices, we recommend generating signing keys from a system with a quality entropy source, and using the best available EC key generation utilities. +For example, to generate a signing key using the OpenSSL command line: -For example, to generate a signing key using the openssl command line: +.. code-block:: -``` -openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem -``` + openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem Remember that the strength of the secure boot system depends on keeping the signing key private. + .. _remote-sign-image: Remote Signing of Images ------------------------ -For production builds, it can be good practice to use a remote signing server rather than have the signing key on the build machine (which is the default esp-idf secure boot configuration). The espsecure.py command line program can be used to sign app images & partition table data for secure boot, on a remote system. +For production builds, it can be good practice to use a remote signing server rather than have the signing key on the build machine, which is the default ESP-IDF secure boot configuration. The ``espsecure.py`` command line program can be used to sign app images & partition table data for secure boot, on a remote system. + +To use remote signing, disable the option ``Sign binaries during build``. The private signing key does not need to be present on the build system. However, the public signature verification key is required because it is compiled into the bootloader, and can be used to verify image signatures during OTA updates. -To use remote signing, disable the option "Sign binaries during build". The private signing key does not need to be present on the build system. However, the public (signature verification) key is required because it is compiled into the bootloader (and can be used to verify image signatures during OTA updates. +To extract the public key from the private key: -To extract the public key from the private key:: +.. code-block:: espsecure.py extract_public_key --keyfile PRIVATE_SIGNING_KEY PUBLIC_VERIFICATION_KEY -The path to the public signature verification key needs to be specified in the menuconfig under "Secure boot public signature verification key" in order to build the secure bootloader. +The path to the public signature verification key needs to be specified in the menuconfig under ``Secure boot public signature verification key`` in order to build the secure bootloader. -After the app image and partition table are built, the build system will print signing steps using espsecure.py:: +After the app image and partition table are built, the build system will print signing steps using ``espsecure.py``: + +.. code-block:: espsecure.py sign_data --keyfile PRIVATE_SIGNING_KEY BINARY_FILE -The above command appends the image signature to the existing binary. You can use the `--output` argument to write the signed binary to a separate file:: +The above command appends the image signature to the existing binary. You can use the `--output` argument to write the signed binary to a separate file: + +.. code-block:: espsecure.py sign_data --keyfile PRIVATE_SIGNING_KEY --output SIGNED_BINARY_FILE BINARY_FILE + Secure Boot Best Practices -------------------------- * Generate the signing key on a system with a quality source of entropy. * Keep the signing key private at all times. A leak of this key will compromise the secure boot system. -* Do not allow any third party to observe any aspects of the key generation or signing process using espsecure.py. Both processes are vulnerable to timing or other side-channel attacks. -* Enable all secure boot options in the Secure Boot Configuration. These include flash encryption, disabling of JTAG, disabling BASIC ROM interpeter, and disabling the UART bootloader encrypted flash access. +* Do not allow any third party to observe any aspects of the key generation or signing process using ``espsecure.py``. Both processes are vulnerable to timing or other side-channel attacks. +* Enable all secure boot options in Secure Boot Configuration. These include flash encryption, disabling of JTAG, disabling BASIC ROM interpreter, and disabling the UART bootloader encrypted flash access. * Use secure boot in combination with :doc:`flash-encryption` to prevent local readout of the flash contents. + .. _secure-boot-technical-details: Technical Details @@ -201,18 +220,20 @@ Technical Details The following sections contain low-level reference descriptions of various secure boot elements: + .. _secure-boot-hardware-support: Secure Boot Hardware Support ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The first stage of secure boot verification (checking the software bootloader) is done via hardware. The {IDF_TARGET_NAME}'s Secure Boot support hardware can perform three basic operations: +The first stage of secure boot verification, i.e., checking the software bootloader, is done via hardware. The {IDF_TARGET_NAME}'s secure boot support hardware can perform three basic operations: 1. Generate a random sequence of bytes from a hardware random number generator. -2. Generate a digest from data (usually the bootloader image from flash) using a key stored in Efuse block 2. The key in Efuse can (& should) be read/write protected, which prevents software access. For full details of this algorithm see `Secure Bootloader Digest Algorithm`_. The digest can only be read back by software if Efuse ABS_DONE_0 is *not* burned (ie still 0). +2. Generate a digest from data, usually the bootloader image from flash, using a key stored in eFuse block 2. The key in eFuse can and should be read/write protected, which prevents software access. For full details of this algorithm see `Secure Bootloader Digest Algorithm`_. The digest can only be read back by software if eFuse ABS_DONE_0 is **not** burned, i.e., still 0. + +3. Generate a digest from data, usually the bootloader image from flash, using the same algorithm as step 2 and compare it to a pre-calculated digest supplied in a buffer, usually read from flash offset 0x0. The hardware returns a true/false comparison without making the digest available to the software. This function is available even when eFuse ABS_DONE_0 is burned. -3. Generate a digest from data (usually the bootloader image from flash) using the same algorithm as step 2 and compare it to a pre-calculated digest supplied in a buffer (usually read from flash offset 0x0). The hardware returns a true/false comparison without making the digest available to software. This function is available even when Efuse ABS_DONE_0 is burned. .. _secure-bootloader-digest-algorithm: @@ -221,23 +242,26 @@ Secure Bootloader Digest Algorithm Starting with an "image" of binary data as input, this algorithm generates a digest as output. The digest is sometimes referred to as an "abstract" in hardware documentation. -For a Python version of this algorithm, see the ``espsecure.py`` tool in the components/esptool_py directory (specifically, the ``digest_secure_bootloader`` command). +For a Python version of this algorithm, see the ``espsecure.py`` tool in the :component:`/esptool_py` directory. Specifically, the ``digest_secure_bootloader`` command. Items marked with (^) are to fulfill hardware restrictions, as opposed to cryptographic restrictions. -1. Read the AES key from efuse block 2, in reversed byte order. If Coding Scheme is set to 3/4 Encoding, extend the 192 bit key to 256 bits using the same algorithm described in :ref:`flash-encryption-algorithm`. -2. Prefix the image with a 128 byte randomly generated IV. -3. If the image length is not modulo 128, pad the image to a 128 byte boundary with 0xFF. (^) -4. For each 16 byte plaintext block of the input image: - - Reverse the byte order of the plaintext input block (^) +1. Read the AES key from eFuse block 2, in reversed byte order. If the Coding Scheme is set to ``3/4 Encoding``, extend the 192-bit key to 256 bits using the same algorithm described in :ref:`flash-encryption-algorithm`. +2. Prefix the image with a 128-byte randomly generated IV. +3. If the image length is not modulo 128, pad the image to a 128-byte boundary with 0xFF. (^) +4. For each 16-byte plaintext block of the input image: + + - Reverse the byte order of the plaintext input block. (^) - Apply AES256 in ECB mode to the plaintext block. - Reverse the byte order of the ciphertext output block. (^) - Append to the overall ciphertext output. -5. Byte-swap each 4 byte word of the ciphertext (^) + +5. Byte-swap each 4-byte word of the ciphertext. (^) 6. Calculate SHA-512 of the ciphertext. -7. Byte-swap each 4 byte word of the above calculated digest. (^) +7. Byte-swap each 4-byte word of the above-calculated digest. (^) + +Output digest is 192 bytes of data: the 128-byte IV, followed by the 64-byte SHA-512 digest. -Output digest is 192 bytes of data: The 128 byte IV, followed by the 64 byte SHA-512 digest. .. _secure-boot-image-signing-algorithm: @@ -246,72 +270,82 @@ Image Signing Algorithm Deterministic ECDSA as specified by `RFC 6979 `_. -- Curve is NIST256p (openssl calls this curve "prime256v1", it is also sometimes called secp256r1). -- Hash function is SHA256. -- Key format used for storage is PEM. +- Curve is NIST256p. OpenSSL calls this curve prime256v1, and it is also sometimes called secp256r1. +- The hash function is SHA256. +- The key format used for storage is PEM. - - In the bootloader, the public key (for signature verification) is flashed as 64 raw bytes. + - In the bootloader, the public key for signature verification is flashed as 64 raw bytes. + +- Image signature is 68 bytes: a 4-byte version word (currently zero), followed by 64 bytes of signature data. These 68 bytes are appended to an app image or partition table data. -- Image signature is 68 bytes - a 4 byte version word (currently zero), followed by a 64 bytes of signature data. These 68 bytes are appended to an app image or partition table data. Manual Commands ~~~~~~~~~~~~~~~ -Secure boot is integrated into the esp-idf build system, so ``make`` will automatically sign an app image if secure boot is enabled. ``idf.py bootloader`` will produce a bootloader digest if menuconfig is configured for it. +Secure boot is integrated into the ESP-IDF build system, so ``idf.py build`` will automatically sign an app image if secure boot is enabled. ``idf.py bootloader`` will produce a bootloader digest if menuconfig is configured for it. However, it is possible to use the ``espsecure.py`` tool to make standalone signatures and digests. -To sign a binary image:: +To sign a binary image: + +.. code-block:: espsecure.py sign_data --keyfile ./my_signing_key.pem --output ./image_signed.bin image-unsigned.bin -Keyfile is the PEM file containing an ECDSA private signing key. +The keyfile is the PEM file containing an ECDSA private signing key. -To generate a bootloader digest:: +To generate a bootloader digest: + +.. code-block:: espsecure.py digest_secure_bootloader --keyfile ./securebootkey.bin --output ./bootloader-digest.bin build/bootloader/bootloader.bin -Keyfile is the 32 byte raw secure boot key for the device. +The keyfile is the 32-byte raw secure boot key for the device. + +The output of the ``espsecure.py digest_secure_bootloader`` command is a single file that contains both the digest and the bootloader appended to it. To flash the combined digest plus bootloader to the device: -The output of the ``espsecure.py digest_secure_bootloader`` command is a single file which contains both the digest and the bootloader appended to it. To flash the combined digest plus bootloader to the device:: +.. code-block:: esptool.py write_flash 0x0 bootloader-digest.bin + .. _secure-boot-and-flash-encr: Secure Boot & Flash Encryption ------------------------------ -If secure boot is used without :doc:`flash-encryption`, it is possible to launch "time-of-check to time-of-use" attack, where flash contents are swapped after the image is verified and running. Therefore, it is recommended to use both the features together. +If secure boot is used without :doc:`flash-encryption`, it is possible to launch a ``time-of-check to time-of-use`` attack, where flash contents are swapped after the image is verified and running. Therefore, it is recommended to use both features together. + .. _signed-app-verify: Signed App Verification Without Hardware Secure Boot ---------------------------------------------------- -The integrity of apps can be checked even without enabling the hardware secure boot option. This option uses the same app signature scheme as hardware secure -boot, but unlike hardware secure boot it does not prevent the bootloader from being physically updated. This means that the device can be secured -against remote network access, but not physical access. Compared to using hardware Secure Boot this option is much simpler to implement. See :ref:`signed-app-verify-howto` for step by step instructions. +The integrity of apps can be checked even without enabling the hardware secure boot option. This option uses the same app signature scheme as hardware secure boot, but unlike hardware secure boot, it does not prevent the bootloader from being physically updated. This means that the device can be secured against remote network access, but not physical access. Compared to using hardware secure boot, this option is much simpler to implement. See :ref:`signed-app-verify-how-to` for step-by-step instructions. An app can be verified on update and, optionally, be verified on boot. -- Verification on update: When enabled, the signature is automatically checked whenever the esp_ota_ops.h APIs are used for OTA updates. If hardware secure boot is enabled, this option is always enabled and cannot be disabled. If hardware secure boot is not enabled, this option still adds significant security against network-based attackers by preventing spoofing of OTA updates. +- Verification on update: When enabled, the signature is automatically checked whenever the ``esp_ota_ops.h`` APIs are used for OTA updates. If hardware secure boot is enabled, this option is always enabled and cannot be disabled. If hardware secure boot is not enabled, this option still adds significant security against network-based attackers by preventing spoofing of OTA updates. - Verification on boot: When enabled, the bootloader will be compiled with code to verify that an app is signed before booting it. If hardware secure boot is enabled, this option is always enabled and cannot be disabled. If hardware secure boot is not enabled, this option does not add significant security by itself so most users will want to leave it disabled. -.. _signed-app-verify-howto: + +.. _signed-app-verify-how-to: How To Enable Signed App Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1. Open :ref:`project-configuration-menu` > Security features > Enable :ref:`CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT` +1. Open :ref:`project-configuration-menu` > ``Security features`` > enable :ref:`CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT` + +2. ``Bootloader verifies app signatures`` can be enabled, which verifies app on boot. + +3. By default, ``Sign binaries during build`` will be enabled by selecting the ``Require signed app images`` option, which will sign binary files as a part of the build process. The file named ``Secure boot private signing key`` will be used to sign the image. -2. "Bootloader verifies app signatures" can be enabled, which verifies app on boot. +4. If you disable the ``Sign binaries during build`` option then you will have to enter the path of a public key file used to verify signed images in the ``Secure boot public signature verification key``. -3. By default, "Sign binaries during build" will be enabled on selecting "Require signed app images" option, which will sign binary files as a part of build process. The file named in "Secure boot private signing key" will be used to sign the image. + In this case, the private signing key should be generated by following instructions in :ref:`secure-boot-generate-key`; the public verification key and signed image should be generated by following instructions in :ref:`remote-sign-image`. -4. If you disable "Sign binaries during build" option then you will have to enter path of a public key file used to verify signed images in "Secure boot public signature verification key". - In this case, private signing key should be generated by following instructions in :ref:`secure-boot-generate-key`; public verification key and signed image should be generated by following instructions in :ref:`remote-sign-image`. Advanced Features ----------------- @@ -319,6 +353,6 @@ Advanced Features JTAG Debugging ~~~~~~~~~~~~~~ -By default, when Secure Boot is enabled then JTAG debugging is disabled via eFuse. The bootloader does this on first boot, at the same time it enables Secure Boot. +By default, when secure boot is enabled, JTAG debugging is disabled via eFuse. The bootloader does this on the first boot, at the same time it enables secure boot. -See :ref:`jtag-debugging-security-features` for more information about using JTAG Debugging with either Secure Boot or signed app verification enabled. +See :ref:`jtag-debugging-security-features` for more information about using JTAG Debugging with either secure boot or signed app verification enabled. diff --git a/docs/en/security/secure-boot-v2.rst b/docs/en/security/secure-boot-v2.rst index e01919b0b6d..ea5bb7d0549 100644 --- a/docs/en/security/secure-boot-v2.rst +++ b/docs/en/security/secure-boot-v2.rst @@ -3,11 +3,11 @@ Secure Boot V2 ============== -{IDF_TARGET_SBV2_SCHEME:default="RSA-PSS", esp32c2="ECDSA", esp32c6 or esp32h2 or esp32p4="RSA-PSS or ECDSA"} +{IDF_TARGET_SBV2_SCHEME:default="RSA-PSS", esp32c2="ECDSA", esp32c6="RSA-PSS or ECDSA", esp32h2="RSA-PSS or ECDSA", esp32p4="RSA-PSS or ECDSA"} -{IDF_TARGET_SBV2_KEY:default="RSA-3072", esp32c2="ECDSA-256 or ECDSA-192", esp32c6 or esp32h2 or esp32p4="RSA-3072, ECDSA-256, or ECDSA-192"} +{IDF_TARGET_SBV2_KEY:default="RSA-3072", esp32c2="ECDSA-256 or ECDSA-192", esp32c6="RSA-3072, ECDSA-256, or ECDSA-192", esp32h2="RSA-3072, ECDSA-256, or ECDSA-192", esp32p4="RSA-3072, ECDSA-256, or ECDSA-192"} -{IDF_TARGET_SECURE_BOOT_OPTION_TEXT:default="", esp32c6 or esp32h2 or esp32p4="RSA is recommended because of faster verification time. You can choose between RSA and ECDSA scheme from the menu."} +{IDF_TARGET_SECURE_BOOT_OPTION_TEXT:default="", esp32c6="RSA is recommended because of faster verification time. You can choose between RSA and ECDSA scheme from the menu.", esp32h2="RSA is recommended because of faster verification time. You can choose between RSA and ECDSA scheme from the menu.", esp32p4="RSA is recommended because of faster verification time. You can choose between RSA and ECDSA scheme from the menu."} {IDF_TARGET_ECO_VERSION:default="", esp32="(ECO 3 onwards)", esp32c3="(ECO 3 onwards)"} diff --git a/docs/en/security/security.rst b/docs/en/security/security.rst index 8b173aaa0ea..4dcad127eb3 100644 --- a/docs/en/security/security.rst +++ b/docs/en/security/security.rst @@ -1,6 +1,10 @@ Security ======== +{IDF_TARGET_CIPHER_SCHEME:default="RSA", esp32h2="RSA or ECDSA", esp32p4="RSA or ECDSA"} + +{IDF_TARGET_SIG_PERI:default="DS", esp32h2="DS or ECDSA", esp32p4="DS or ECDSA"} + :link_to_translation:`zh_CN:[中文]` This guide provides an overview of the overall security features available in various Espressif solutions. It is highly recommended to consider this guide while designing the products with the Espressif platform and the ESP-IDF software stack from the **security** perspective. @@ -73,9 +77,19 @@ Flash Encryption Best Practices The Digital Signature peripheral in {IDF_TARGET_NAME} produces hardware-accelerated RSA digital signatures with the assistance of HMAC, without the RSA private key being accessible by software. This allows the private key to be kept secured on the device without anyone other than the device hardware being able to access it. - This peripheral can help to establish the **Secure Device Identity** to the remote endpoint, e.g., in the case of TLS mutual authentication based on the RSA cipher scheme. + .. only:: SOC_ECDSA_SUPPORTED + + {IDF_TARGET_NAME} also supportes ECDSA peripheral for generating hardware-accelerated ECDSA digital signatures. ECDSA private key can be directly programmed in an eFuse block and marked as read protected from the software. + + {IDF_TARGET_SIG_PERI} peripheral can help to establish the **Secure Device Identity** to the remote endpoint, e.g., in the case of TLS mutual authentication based on the {IDF_TARGET_CIPHER_SCHEME} cipher scheme. + + .. only:: not SOC_ECDSA_SUPPORTED - Please refer to the :doc:`../api-reference/peripherals/ds` for detailed documentation. + Please refer to the :doc:`../api-reference/peripherals/ds` for detailed documentation. + + .. only:: SOC_ECDSA_SUPPORTED + + Please refer to the :doc:`../api-reference/peripherals/ecdsa` and :doc:`../api-reference/peripherals/ds` guides for detailed documentation. .. only:: SOC_MEMPROT_SUPPORTED or SOC_CPU_IDRAM_SPLIT_USING_PMP @@ -185,30 +199,32 @@ UART Download Mode Root certificates list update could have following reasons: - New firmware has different set of remote endpoint(s). - - Existing certificate has expired. + - The existing certificate has expired. - The certificate has been added or retracted from the upstream certificate bundle. - The certificate list changed due to market share statistics (``CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN`` case). Some guidelines to consider on this topic: - Please consider enabling :ref:`OTA rollback ` and then keep the successful connection to the OTA update server as the checkpoint to cancel the rollback process. This ensures that the newly updated firmware can successfully reach till the OTA update server, otherwise rollback process will go back to the previous firmware on the device. - - If you plan to enable the :ref:`CONFIG_MBEDTLS_HAVE_TIME_DATE` option then please consider to have sufficient number of trusted certificates and the time sync mechanism (SNTP) in place. + - If you plan to enable the :ref:`CONFIG_MBEDTLS_HAVE_TIME_DATE` option, then please consider to have the time sync mechanism (SNTP) and sufficient number of trusted certificates in place. Product Security ---------------- -Secure Provisioning -~~~~~~~~~~~~~~~~~~~ +.. only:: SOC_WIFI_SUPPORTED -Secure Provisioning refers to a process of secure on-boarding of the ESP device on to the Wi-Fi network. This mechanism also allows provision of additional custom configuration data during the initial provisioning phase from the provisioning entity, e.g., Smartphone. + Secure Provisioning + ~~~~~~~~~~~~~~~~~~~ -ESP-IDF provides various security schemes to establish a secure session between ESP and the provisioning entity, they are highlighted at :ref:`provisioning_security_schemes`. + Secure Provisioning refers to a process of secure on-boarding of the ESP device on to the Wi-Fi network. This mechanism also allows provision of additional custom configuration data during the initial provisioning phase from the provisioning entity, e.g., Smartphone. -Please refer to the :doc:`../api-reference/provisioning/wifi_provisioning` documentation for details and the example code for this feature. + ESP-IDF provides various security schemes to establish a secure session between ESP and the provisioning entity, they are highlighted at :ref:`provisioning_security_schemes`. -.. note:: + Please refer to the :doc:`../api-reference/provisioning/wifi_provisioning` documentation for details and the example code for this feature. + + .. note:: - Espressif provides Android and iOS Phone Apps along with their sources, so that it could be easy to further customize them as per the product requirement. + Espressif provides Android and iOS Phone Apps along with their sources, so that it could be easy to further customize them as per the product requirement. Secure OTA (Over-the-air) Updates ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/zh_CN/api-guides/app_trace.rst b/docs/zh_CN/api-guides/app_trace.rst index 13012578ee7..1e00241e921 100644 --- a/docs/zh_CN/api-guides/app_trace.rst +++ b/docs/zh_CN/api-guides/app_trace.rst @@ -420,7 +420,7 @@ Start 子命令语法： 收集到跟踪数据后，用户可以使用特殊的工具对结果进行可视化并分析程序行为。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES 遗憾的是，SystemView 不支持从多个核心进行跟踪。所以当使用 JTAG 追踪双核模式下的 {IDF_TARGET_NAME} 时会生成两个文件：一个用于 PRO CPU，另一个用于 APP CPU。用户可以将每个文件加载到工具中单独分析。使用 UART 进行追踪时，用户可以在 menuconfig Pro 或 App 中点击 ``Component config`` > ``Application Level Tracing`` > ``FreeRTOS SystemView Tracing`` 并选择要追踪的 CPU。 @@ -432,7 +432,7 @@ Start 子命令语法： ESP-IDF 使用自己的 SystemView FreeRTOS 事件 ID 映射，因此用户需要将 ``$SYSVIEW_INSTALL_DIR/Description/SYSVIEW_FreeRTOS.txt`` 替换成 ``$IDF_PATH/tools/esp_app_trace/SYSVIEW_FreeRTOS.txt``。在使用上述链接配置 SystemView 序列化程序时，也应该使用该特定文件的内容。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES 配置 Impulse 实现双核跟踪 ~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/zh_CN/api-guides/bootloader.rst b/docs/zh_CN/api-guides/bootloader.rst index f068ff4f26e..468249fb0ad 100644 --- a/docs/zh_CN/api-guides/bootloader.rst +++ b/docs/zh_CN/api-guides/bootloader.rst @@ -3,8 +3,6 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} - ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务： 1. 内部模块的最小化初始配置； @@ -12,7 +10,7 @@ ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务： 3. 根据分区表和 ota_data（如果存在）选择需要引导的应用程序 (app) 分区； 4. 将此应用程序镜像加载到 RAM（IRAM 和 DRAM）中，最后把控制权转交给此应用程序。 -引导加载程序位于 flash 的 {IDF_TARGET_BOOTLOADER_OFFSET} 偏移地址处。 +引导加载程序位于 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处。 关于启动过程以及 ESP-IDF 引导加载程序的更多信息，请参考 :doc:`startup`。 @@ -95,7 +93,7 @@ ROM 中的 :ref:`first-stage-bootloader` 从 flash 中读取 :ref:`second-stage- .. only:: SOC_RTC_FAST_MEM_SUPPORTED 如果应用程序需要知道设备是否触发了出厂重置，可以通过调用 :cpp:func:`bootloader_common_get_rtc_retain_mem_factory_reset_state` 函数来确定： - + - 如果读取到设备出厂重置状态为 true，会返回状态 true，说明设备已经触发出厂重置。此后会重置状态为 false，以便后续的出厂重置触发判断。 - 如果读取到设备出厂重置状态为 false，会返回状态 false，说明设备并未触发出厂重置，或者保存此状态的内存区域已失效。 diff --git a/docs/zh_CN/api-guides/build-system.rst b/docs/zh_CN/api-guides/build-system.rst index 7a7451bc537..dfe2c1fa6db 100644 --- a/docs/zh_CN/api-guides/build-system.rst +++ b/docs/zh_CN/api-guides/build-system.rst @@ -361,6 +361,7 @@ ESP-IDF 在搜索所有待构建的组件时，会按照 ``COMPONENT_DIRS`` 指 * 如果设置 :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` 选项，将会使用 :ref:`CONFIG_APP_PROJECT_VER` 的值。 * 或者，如果在项目 CMakeLists.txt 文件中设置了 ``PROJECT_VER`` 变量，则该变量值可以使用。 * 或者，如果 ``PROJECT_DIR/version.txt`` 文件存在，其内容会用作 ``PROJECT_VER`` 的值。 + * 或者，如果在 CMakeLists.txt 文件中将 ``VERSION`` 参数传递给 ``project()`` 调用，形式为 ``project(... VERSION x.y.z.w )``，那么 ``VERSION`` 参数将用作为 ``PROJECT_VER`` 的值。``VERSION`` 参数必须符合 `cmake 标准 `_。 * 或者，如果项目位于某个 Git 仓库中，则使用 ``git describe`` 命令的输出作为 ``PROJECT_VER`` 的值。 * 否则，``PROJECT_VER`` 的值为 1。 - ``EXTRA_PARTITION_SUBTYPES``：CMake 列表，用于创建额外的分区子类型。子类型的描述由字符串组成，以逗号为分隔，格式为 ``type_name, subtype_name, numeric_value``。组件可通过此列表，添加新的子类型。 @@ -709,8 +710,6 @@ KConfig.projbuild 在此文件中添加配置时要小心，因为这些配置会包含在整个项目配置中。在可能的情况下，请为 :ref:`component-configuration` 创建 KConfig 文件。 -``project_include.cmake`` 文件在 ESP-IDF 内部使用，以定义项目范围内的构建功能，比如 ``esptool.py`` 的命令行参数和 ``bootloader`` 这个特殊的应用程序。 - 通过封装对现有函数进行重新定义或扩展 ------------------------------------- diff --git a/docs/zh_CN/api-guides/c.rst b/docs/zh_CN/api-guides/c.rst new file mode 100644 index 00000000000..60ba5842083 --- /dev/null +++ b/docs/zh_CN/api-guides/c.rst @@ -0,0 +1 @@ +.. include:: ../../en/api-guides/c.rst diff --git a/docs/zh_CN/api-guides/coexist.rst b/docs/zh_CN/api-guides/coexist.rst index e22af959b77..5680a483cfe 100644 --- a/docs/zh_CN/api-guides/coexist.rst +++ b/docs/zh_CN/api-guides/coexist.rst @@ -6,7 +6,7 @@ RF 共存 概览 ----- -{IDF_TARGET_NAME} 只支持一路 RF，Bluetooth（BT 和 BLE）和 Wi-Fi 共享这一路 RF，无法同时收发数据，因此采用时分复用的方法进行收发数据包。 +ESP系列芯片最多支持三种射频收发模块: Bluetooth（BT 和 BLE）, IEEE802.15.4 和 Wi-Fi, 而每款芯片只支持一路被多个射频收发模块共享的 RF，不同模块无法同时使用 RF 收发数据，因此采用时分复用的方法调节不同模块的数据包收发。 {IDF_TARGET_NAME} 支持的共存场景 @@ -69,6 +69,25 @@ RF 共存 | | |TX |Y |Y |Y |Y |Y | +-------+--------+-----------+--------+-------------+-----+----------+-----------+ +.. only:: SOC_IEEE802154_SUPPORTED + + .. table:: 表 3 Thread (IEEE802.15.4) 和 BLE 共存支持功能 + + + +--------+-----------------+-----+------------+-----------+----------+ + | |BLE | + + +-----+------------+-----------+----------+ + | |Scan |Advertising |Connecting |Connected | + +--------+-----------------+-----+------------+-----------+----------+ + | Thread |Scan |X |Y |Y |Y | + + +-----------------+-----+------------+-----------+----------+ + | |Connecting |X |Y |Y |Y | + + +-----------------+-----+------------+-----------+----------+ + | |Connected |X |Y |Y |Y | + + +-----------------+-----+------------+-----------+----------+ + | |Connected | | | | | + | |(high throughput)|X |C1 |C1 |C1 | + +--------+-----------------+-----+------------+-----------+----------+ .. note:: @@ -131,6 +150,9 @@ RF 共存 Wi-Fi、BLE 二者对于 RF 的使用，主要是按照时间片来划分的。在 Wi-Fi 的时间片内，Wi-Fi 会向共存仲裁模块发出较高优先级的请求，在 Bluetooth 的时间片内，BLE 会具有较高优先级。共存周期大小和各个时间片占比根据 Wi-Fi 的状态分成四类： +.. only:: SOC_IEEE802154_SUPPORTED + + 目前, 当 BLE 与 IEEE802.15.4 共存时, ESP 芯片使用的策略为 BLE 优先级始终优先于 IEEE802.15.4。 .. list:: @@ -154,7 +176,7 @@ RF 共存 动态优先级 """"""""""""""""""" -共存模块对 Wi-Fi 和 Bluetooth 不同的状态赋予其不同的优先级。每种状态下的优先级并不是一成不变的，例如每 N 个广播事件 (Advertising event) 中会有一个广播事件使用高优先级。如果高优先级的广播事件发生在 Wi-Fi 时间片内，RF 的使用权可能会被 BLE 抢占。 +共存模块为每个模块的不同状态分配不同的优先级。每种状态下的优先级并不是一成不变的，例如对于 BLE，每 N 个广播事件 (Advertising event) 中会有一个广播事件使用高优先级。如果高优先级的广播事件发生在 Wi-Fi 时间片内，RF 的使用权可能会被 BLE 抢占。 .. only:: SOC_WIFI_SUPPORTED @@ -231,4 +253,4 @@ BLE MESH 共存状态描述 .. note:: - 由于共存配置选项依赖于蓝牙配置选项，所以请先打开蓝牙配置选项，然后在 Wi-Fi 配置选项中打开共存配置选项。 + 由于共存配置选项依赖于任何两个已启用的射频收发模块的存在，请在配置任何共存功能之前，确保至少使能了两个射频收发模块。 diff --git a/docs/zh_CN/api-guides/fatal-errors.rst b/docs/zh_CN/api-guides/fatal-errors.rst index 6c0ed6b9193..64bc91cd585 100644 --- a/docs/zh_CN/api-guides/fatal-errors.rst +++ b/docs/zh_CN/api-guides/fatal-errors.rst @@ -282,7 +282,7 @@ GDB Stub RTC 看门狗超时 ---------------- -{IDF_TARGET_RTCWDT_RTC_RESET:default="Not updated", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS"} +{IDF_TARGET_RTCWDT_RTC_RESET:default="Not updated", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS", esp32p4="LP_WDT_SYS"} RTC 看门狗在启动代码中用于跟踪执行时间，也有助于防止由于电源不稳定引起的锁定。RTC 看门狗默认启用，参见 :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`。如果执行时间超时，RTC 看门狗将自动重启系统。此时，ROM 引导加载程序将打印消息 ``RTC Watchdog Timeout`` 说明重启原因。 diff --git a/docs/zh_CN/api-guides/host-apps.rst b/docs/zh_CN/api-guides/host-apps.rst index 54a770f6a89..c7004bd0261 100644 --- a/docs/zh_CN/api-guides/host-apps.rst +++ b/docs/zh_CN/api-guides/host-apps.rst @@ -82,6 +82,9 @@ ESP-IDF 已支持使用 `FreeRTOS POSIX/Linux 模拟器 iram0_text`` 生成的规则。默认协议指定了 ``iram -> iram0_text`` 条目，因此生成的规则同样也放在被 ``iram0_text`` 标记的地方。由于该规则是根据默认协议生成的，因此在同一目标下收集的所有规则下排在第一位。 目前使用的链接器脚本模板是 :component_file:`esp_system/ld/{IDF_TARGET_PATH_NAME}/sections.ld.in`，生成的脚本存放在构建目录下。 - -.. _ldgen-migrate-lf-grammar : - -将链接器脚本片段文件语法迁移至 ESP-IDF v5.0 适应版本 -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -ESP-IDF v5.0 中将不再支持 ESP-IDF v3.x 中链接器脚本片段文件的旧式语法。在迁移的过程中需注意以下几点： - -- 必须缩进，缩进不当的文件会产生解析异常；旧版本不强制缩进，但之前的文档和示例均遵循了正确的缩进语法 -- 条件改用 ``if...elif...else`` 结构，可以参照 :ref:`之前的章节` -- 映射片段和其他片段类型一样，需有名称 diff --git a/docs/zh_CN/api-guides/low-power-mode.rst b/docs/zh_CN/api-guides/low-power-mode.rst new file mode 100644 index 00000000000..75df5d1883d --- /dev/null +++ b/docs/zh_CN/api-guides/low-power-mode.rst @@ -0,0 +1,735 @@ +低功耗模式使用指南 +================== + +:link_to_translation:`en:[English]` + +对于物联网应用场景，终端的待机性能表现十分重要，本文档旨在介绍 {IDF_TARGET_NAME} 低功耗的基本原理，同时介绍 {IDF_TARGET_NAME} 支持的低功耗模式，需注意本文档主要针对 station mode。文档还会具体给出每种模式的配置步骤、推荐配置和功耗表现，以帮助用户根据实际需求快速配置适合的低功耗模式。 + +系统低功耗模式介绍 +---------------------------------- + +低功耗模式不仅涉及到系统相关问题，还涉及到芯片具体的工作场景，如处在 Wi-Fi 工作场景就会与处在蓝牙工作场景时产生不同。为此本节将首先介绍纯系统角度，即不涉及具体场景的低功耗模式，主要有 DFS、Light-sleep、Deep-sleep。纯系统下的低功耗模式主要思想就是在休眠时关闭或门控一些功能模块来降低功耗。 + +DFS +++++++++++++++++++++++++++++++++++ + +DFS (Dynamic frequency scaling) 即动态频率切换，是 ESP-IDF 中集成的电源管理机制的基础功能。DFS 可以根据应用程序持有电源锁的情况，调整外围总线 (APB) 频率和 CPU 频率。持有高性能锁就使用高频，空闲状态不持有电源锁时则使用低频来降低功耗，以此来尽可能减少运行应用程序的功耗。 + +DFS 的调频机制即根据持有电源锁的最大频率需求来调整频率，同时，freertos tick rates 的数值也会对 DFS 调频产生影响。系统任务调度的灵敏度越大，则意味着系统能更及时的根据需求调整频率。有关调频机制的详细信息，请参见 :doc:`电源管理 <../api-reference/system/power_management>`。 + +下图为 DFS 调频机制运行的理想电流情况。 + +.. figure:: ../../_static/Low-power-DFS-current.png + :align: center + + 理想 DFS 机制调频电流图 + +DFS 适用于 CPU 必须处于工作状态但是对低功耗有需求的场景，因此 DFS 经常与其他低功耗模式共同开启，下文会详细介绍。 + +Light-sleep +++++++++++++++++++++++++++++++++++ + +Light-sleep 模式是 {IDF_TARGET_NAME} 预设的一种低功耗模式，其核心思想就是在休眠时关闭或门控一些功能模块来降低功耗。从纯系统方面来说，Light-sleep 模式有两种进入方式，一种是通过 API 调用进入休眠，一种是自动进入的 auto 模式。两种模式都需要配置唤醒源进行唤醒，同时在进入休眠后会门控或关闭一些模块。这里主要介绍 Auto Light-sleep 模式。 + +Auto Light-sleep 模式是 ESP-IDF 电源管理机制和 Light-sleep 模式的结合。开启电源管理机制是其前置条件，auto 体现在系统进入空闲状态 (IDLE) 超过设定时间后，自动进入 Light-sleep。空闲状态下，应用程序释放所有电源锁，此时，DFS 将降频以减小功耗。 + +Auto Light-sleep 依赖于电源管理机制，系统经过提前判断，发现空闲时间超过设定时间时，则直接进入休眠。该过程为自动进行。休眠时会自动关闭 RF、8 MHz 振荡器、40 MHz 高速晶振、PLL、门控数字内核时钟，暂停 CPU 工作。 + +Auto Light-sleep 模式需配置唤醒源。该模式拥有多种唤醒源，支持相互组合，此时任何一个唤醒源都可以触发唤醒。唤醒后，会从进入休眠的位置继续执行程序。若不配置唤醒源，进入 Light-sleep 休眠后，芯片将一直处在睡眠状态，直到外部复位。具体唤醒源有 RTC 定时器、触摸传感器、外部唤醒 (ext0)、外部唤醒 (ext1)、ULP 协处理器、SDIO、GPIO、UART、Wi-Fi、BT 唤醒等。 + +Auto Light-sleep 模式工作流程相对复杂，但是进入休眠状态是自动进行，同时需注意在进入前配置好唤醒源，防止芯片一直处在休眠状态。 + +.. figure:: ../../_static/Low-power-auto-light-sleep-process.png + :align: center + + Auto Light-sleep 模式工作流程图 + +根据 Auto Light-sleep 的工作流程可得其理想电流图，关键节点均在图上标出。 + +.. figure:: ../../_static/Low-power-auto-light-sleep-current.png + :align: center + + Auto Light-sleep 模式模式理想电流图 + +.. note:: + 为更加清晰地展现出 Auto Light-sleep 的主要变化，图中省略了 DFS 降频过程。 + +Auto Light-sleep 模式适用于不需要实时响应外界需求的场景。 + +Deep-sleep +++++++++++++++++++++++++++++++++++ + +Deep-sleep 模式是为了追求更好的功耗表现所设计，休眠时仅保留 RTC 控制器、RTC 外设（可配置）、ULP 协处理器、RTC 高速内存、RTC 低速内存，其余模块全部关闭。与 Light-sleep 类似，Deep-sleep 同样通过 API 进入，且需要配置唤醒源进行唤醒。 + +Deep-sleep 通过调用 API 进入，休眠时会关闭除 RTC 控制器、RTC 外设、ULP 协处理器、RTC 高速内存、RTC 低速内存外的所有模块。 + +Deep-sleep 模式需配置唤醒源，其拥有多种唤醒源，这些唤醒源也可以组合在一起，此时任何一个唤醒源都可以触发唤醒。若不配置唤醒源进入 Deep-sleep 模式，芯片将一直处在睡眠状态，直到外部复位。具体唤醒源有 RTC 定时器、触摸传感器、外部唤醒 (ext0)、外部唤醒 (ext1)、ULP 协处理器、GPIO 唤醒等。 + +Deep-sleep 模式工作流程如下图所示： + +.. figure:: ../../_static/Low-power-deep-sleep-process.png + :align: center + + Deep-sleep 模式工作流程图 + +Deep-sleep 模式主要应用场景决定了系统很长时间才会苏醒一次，完成工作后又会继续进入 Deep-sleep，所以其理想电流图如下。 + +.. figure:: ../../_static/Low-power-deep-sleep-current.png + :align: center + + Deep-sleep 模式理想电流图 + +Deep-sleep 可以用于低功耗的传感器应用，或是大部分时间都不需要进行数据传输的情况，也就是通常所说的待机模式。设备可以每隔一段时间从 Deep-sleep 状态醒来测量数据并上传，之后重新进入 Deep-sleep；也可以将多个数据存储于 RTC memory，然后一次性发送出去。 + +如何配置纯系统下低功耗模式 ++++++++++++++++++++++++++++++++++++++ + +介绍完纯系统下的低功耗模式后，本节将介绍公共配置选项、每种模式独有的配置选项，以及相应低功耗模式 API 的使用说明，同时给出相应模式推荐的配置。 + +公共配置选项 ++++++++++++++ + +.. only:: esp32 or esp32s3 + + - 单双核工作模式 + 对于多核心芯片，可以选择单核工作模式。 + + + - RTOS Tick rate (Hz) + 该参数表示系统周期任务调度的频率。例如，当 RTOS Tick rate 配置为 1000 时，系统每毫秒都会进行一次任务调度；空闲时，系统也能够更敏锐的感知到空闲状态。 + + +DFS 配置 ++++++++++++++++++++++++ + +DFS 有如下可配置选项： + +- max_freq_mhz + 该参数表示最大 CPU 频率 (MHz)，即 CPU 最高性能工作时候的频率，一般设置为芯片参数的最大值。 + +- min_freq_mhz + 该参数表示最小 CPU 频率 (MHz)，即系统处在空闲状态时 CPU 的工作频率。该字段可设置为晶振 (XTAL) 频率值，或者 XTAL 频率值除以整数。 + +- light_sleep_enable + 使能该选项，系统将在空闲状态下自动进入 Light-sleep 状态，即 Auto Light-sleep 使能，上文已经具体介绍。 + +具体配置方法如下： + +- 1. 使能 CONFIG_PM_ENABLE +- 2. 配置 max_freq_mhz 和 min_freq_mhz，方式如下: + + :: + + esp_pm_config_t pm_config = { + .max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ, + .min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ, + .light_sleep_enable = flase + }; + ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); + +推荐配置： + +.. list-table:: + :header-rows: 1 + :widths: 20 20 + + * - 配置名称 + - 设置情况 + + * - CONFIG_PM_ENABLE + - ON + + * - RTOS Tick rate (Hz) + - 1000 + + * - max_freq_mhz + - 160 + + * - min_freq_mhz + - 40 + + * - light_sleep_enable + - false + +.. note:: + 上表中不涉及的配置均是默认。 + + +Light-sleep 配置 ++++++++++++++++++++ + +本节介绍 Auto Light-sleep 的推荐配置和配置步骤。 + +Auto Light-sleep 有如下可配置选项： + +- Minimum step to enter sleep mode + 该参数表示系统自动进入休眠的阈值。该参数单位为 RTOS Tick，故其表示的时间与 RTOS Tick rate 相关，例该参数值为 3，RTOS Tick rate 配置为 1000 Hz 时，即当系统空闲时间大于等于 3 ms 时进入 休眠。 + +- Put light sleep related codes in internal RAM + 如果使能该选项，一些 light-sleep 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加 1.8kB。 + +- Put RTOS IDLE related codes in internal RAM + 如果使能该选项，一些 RTOS IDLE 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加 260B。 + +- RTC slow clock source + 该参数表表示 RTC 慢速时钟源。系统休眠时计时器模块的时钟被门控，此时使用 RTC Timer 进行计时，唤醒后使用 RTC Timer 的计数值对系统时间进行补偿。 + +.. list-table:: + :header-rows: 1 + :widths: 20 20 20 + + * - 时钟源 + - 精度 + - 频偏 + + * - Internal 150kHz OSC + - 约6.7us/cycle + - 大 + + * - External 32kHz XTAL + - 约30.5us/cycle + - 小 + +- Disable all GPIO when chip at sleep + 如果使能该选项，系统将在休眠过程中禁用所有 GPIO 管脚，消除 GPIO 漏电，降低功耗，但是休眠过程中 GPIO 无法进行信号输入和输出。 + +.. only:: esp32c3 or esp32s3 + + - Power down MAC and baseband + 如果使能该选项，系统将在休眠时关闭 Wi-Fi 和蓝牙的 MAC 和 baseband 来降低功耗，休眠电流约降低 100 uA， 但是为保存上下文信息，将额外消耗 5.3 K DRAM。 + + - Power down CPU + 如果使能该选项，系统将在休眠时将关闭 CPU 来降低功耗，对于 esp32c3，休眠电流减小 100 uA 左右，对于 esp32s3，休眠电流减小 650 uA 左右。但是为保存上下文信息，对于 esp32c3，将消耗 1.6 KB 的 DRAM 空间，对于 esp32s3，将消耗 8.58 KB 的 DRAM 空间。 + + - Power down I/D-cache tag memory + 如果使能该选项，系统将在休眠时关闭 I/D cache tag memory 来降低功耗， 但是为保存 tag memory 信息，将额外消耗最大约 9 KB DRAM，同时因为 tag memory 信息特殊性，如需打开该选项，建议多进行测试。 + + - Power down flash in Light-sleep + 如果使能该选项，系统将在 Light-sleep 休眠时关闭 flash，降低系统功耗，该选项的前提是系统没有使用 PSRAM。 + +唤醒源： + +- RTC Timer Wakeup +- GPIO Wakeup +- UART Wakeup +- Touchpad Wakeup +- External Wakeup (ext0) +- External Wakeup (ext1) +- ULP Coprocessor Wakeup + +.. note:: + 以上仅列出可配置唤醒源，详细介绍请参考 :doc:`睡眠模式 <../api-reference/system/sleep_modes>`。 + +配置方法： + +- 1. 配置唤醒源 +- 2. 使能 CONFIG_PM_ENABLE +- 3. 使能 CONFIG_FREERTOS_USE_TICKLESS_IDLE +- 4. 配置 DFS 参数 +- 5. light_sleep_enable = true，具体如下: + + :: + + esp_pm_config_t pm_config = { + .max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ, + .min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ, + #if CONFIG_FREERTOS_USE_TICKLESS_IDLE + .light_sleep_enable = true + #endif + }; + ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); + +- 6. 配置介绍的其余相关参数 + +推荐配置： + +.. only:: esp32c3 or esp32s3 + + .. list-table:: + :header-rows: 1 + :widths: 30 15 + + * - 配置名称 + - 设置情况 + + * - CONFIG_PM_ENABLE + - ON + + * - CONFIG_FREERTOS_USE_TICKLESS_IDLE + - ON + + * - max_freq_mhz + - 160 + + * - min_freq_mhz + - 40 + + * - RTOS Tick rate (Hz) + - 1000 + + * - light_sleep_enable + - true + + * - Minimum step to enter sleep mode + - 3 + + * - Put light sleep codes in IRAM + - OFF + + * - Put RTOS IDLE codes in IRAM + - OFF + + * - RTC slow clock source + - Internal 150kHz OSC + + * - Disable all GPIO when chip at sleep + - ON + + * - Power down MAC and baseband + - ON + + * - Power down I/D-cache tag memory + - ON + + * - Power down CPU + - ON + + * - Power down flash in light sleep + - OFF + + .. note:: + 上表中不涉及的配置均是默认 + +.. only:: esp32 or esp32s2 + + .. list-table:: + :header-rows: 1 + :widths: 30 15 + + * - 配置名称 + - 设置情况 + + * - CONFIG_PM_ENABLE + - ON + + * - CONFIG_FREERTOS_USE_TICKLESS_IDLE + - ON + + * - max_freq_mhz + - 160 + + * - min_freq_mhz + - 40 + + * - RTOS Tick rate (Hz) + - 1000 + + * - light_sleep_enable + - true + + * - Minimum step to enter sleep mode + - 3 + + * - Put light sleep codes in IRAM + - OFF + + * - Put RTOS IDLE codes in IRAM + - OFF + + * - RTC slow clock source + - Internal 150kHz OSC + + * - Disable all GPIO when chip at sleep + - ON + + .. note:: + 上表中不涉及的配置均是默认 + +.. only:: esp32c2 + + .. list-table:: + :header-rows: 1 + :widths: 30 15 + + * - 配置名称 + - 设置情况 + + * - CONFIG_PM_ENABLE + - ON + + * - CONFIG_FREERTOS_USE_TICKLESS_IDLE + - ON + + * - max_freq_mhz + - 120 + + * - min_freq_mhz + - 40 + + * - RTOS Tick rate (Hz) + - 1000 + + * - light_sleep_enable + - true + + * - Minimum step to enter sleep mode + - 3 + + * - Put light sleep codes in IRAM + - OFF + + * - Put RTOS IDLE codes in IRAM + - OFF + + * - RTC slow clock source + - Internal 150kHz OSC + + * - Disable all GPIO when chip at sleep + - ON + + * - Power down MAC and baseband + - ON + + * - Power down I/D-cache tag memory + - ON + + * - Power down CPU + - ON + + * - Power down flash in light sleep + - OFF + + .. note:: + 上表中不涉及的配置均是默认 + +Deep-sleep 配置 +++++++++++++++++++ + +对 Deep-sleep 模式来说，除了唤醒源相关配置，其余配置意义已经不大。 + +Deep-sleep 有如下可配置选项： + +- RTC Timer wakeup +- EXT0/1 wakeup +- Touchpad wakeup +- ULP wakeup + +.. note:: + 以上仅列出可配置唤醒源，详细介绍请参考 :doc:`睡眠模式 <../api-reference/system/sleep_modes>`。 + +配置步骤： + +- 配置唤醒源 +- 调用 API，具体如下:: + + /* Enter deep sleep */ + esp_deep_sleep_start(); + +用户可以通过下列配置选项，让一些特定模块在休眠时保持开启状态： + +- Power up External 40 MHz XTAL + 在一些特殊应用中，部分模块对休眠时的时钟精度及稳定度有很高要求（例如 BT）。这种情况下，可以考虑在休眠过程中打开 External 40 MHz XTAL。 + 打开和关闭代码如下:: + + ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)); + ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_OFF)); + +- Power up Internal 8 MHz OSC + 在一些特殊应用中，部分模块（例如 LEDC）将 Internal 8 MHz OSC 作为时钟源，并且希望在 Light-sleep 休眠过程中也可以正常使用。这种情况下，可以考虑在休眠过程中打开 Internal 8 MHz OSC。 + 打开和关闭代码如下:: + + ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC8M, ESP_PD_OPTION_ON)); + ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC8M, ESP_PD_OPTION_OFF)); + +.. only:: SOC_WIFI_SUPPORTED + + Wi-Fi 场景下低功耗模式介绍 + ---------------------------------- + + 上文介绍了纯系统方向下的低功耗模式，但在实际应用中还需结合具体应用场景。本节将结合纯系统下的功耗模式来介绍在 Wi-Fi 场景下的低功耗模式。因为 Wi-Fi 场景的复杂性，本节会会首先介绍 Wi-Fi 省电的基本原理，然后再介绍具体的低功耗模式，同时本节主要针对 station 模式。 + + Wi-Fi 场景如何选择低功耗模式 + ++++++++++++++++++++++++++++++++++ + + 为方便用户选择合适的低功耗模式，在介绍具体内容前先给出 Wi-Fi 场景下低功耗模式总结表，以方便用户根据需求快速选择想要了解的内容。 + + .. include:: sleep-current/{IDF_TARGET_PATH_NAME}_summary.inc + + .. note:: + + 上表中所有电流均为平均电流，表中术语在下文均有介绍，用户可根据需求进行查看 + + + Wi-Fi 省电的基本原理 + +++++++++++++++++++++ + + 首先，在 station 的工作过程中，为在接收发送过程中避免冲突，需要长时间监听信道，能耗较大的 RF 模块会一直处于工作中，浪费电量。为此，Wi-Fi 协议引入省电模式。 + + 省电模式的基本原理是通过减少不必要的监听时间来降低耗能。AP 会缓存进入省电模式的 station 的包，同时周期发送包含 TIM 信息的 Beacon 帧，TIM 会指示 AP 缓存的单播包。TIM 中，DTIM 较为特殊，其会缓存广播包，并以 n 个（由 AP 决定）TIM 为周期发送。对 station 来说，TIM 非必听，而 DTIM 为必听。因此，station 可以选择只在每一个 DTIM 帧前醒来打开 Wi-Fi 相关模块（RF 模块），而不必时刻处于监听状态，这样就能有效降低功耗。 + + .. figure:: ../../_static/Low-power-DTIM4.png + :align: center + + DTIM4 省电模式示意图 + + 其次，station 从打开到再次关闭 Wi-Fi 相关模块的时间也会影响功耗。除必要的数据传输处理时间外，主要有四项配置会影响时间长短： + + - 时钟准确性导致的 time offset，主要原因是时钟或多或少都会与理想的时间存在偏移，同时偏移的正负不定。 + - 处理 Beacon 漏听后的时间，如漏听后持续监听时间、允许最多丢失 Beacon 数目等，这段时间存不存在以及存在多久都不定，但是可以配置范围。 + - 为了确保能够接受突发数据包而添加的 active 时间，可由配置决定。 + - ILDE 时间是具体某些功耗模式进入条件要求。因此在满足通信需求的情况下，降低工作时间可以改善功耗表现。 + + .. figure:: ../../_static/Low-power-time.png + :align: center + + 芯片工作时间组成图 + + 此外，在 station 没有处于 Wi-Fi 接收或发送状态时，影响功耗的因素变成了芯片的其他模块。不同的功耗模式会配置不同的时钟源，或者动态调整一些模块的工作频率如 CPU，同时还会关闭不同数量的功能模块，这将有效降低芯片的功耗。其实也就是纯系统相关的模式，用户可根据需求自己选择合适的配置。 + + 如果以时间为横轴，电流大小为纵轴建立坐标轴，那么处在低功耗模式下芯片的理想工作电流图可以简化成下图： + + .. figure:: ../../_static/Low-power-WiFi-base-current.png + :align: center + + 理想情况下 Wi-Fi 场景低功耗模式电流图 + + 其中 station 要进行 Wi-Fi 通信时，Wi-Fi 相关模块 (PHY) 开启，电流会显著上升，在工作完成前，电流会一直维持在一个较高的水平。工作完成后，芯片会关闭 Wi-Fi 相关模块，这时电流又会降低到一个较低水平。 + + 可以看出影响功耗表现的主要有三点：interval、period 和 base current。 + + - Interval 是 station Wi-Fi 相关模块工作的间隔，既可以由低功耗模式自定义，也可根据 Wi-Fi 协议省电机制（3.1 第一点介绍），由 DTIM 周期决定。可以看出在同等情下，interval 越大，功耗表现会更好，但是响应会更慢，影响通信的及时性。 + + - Period 可以看作每次 station Wi-Fi 工作的时间，这段时间的长度也会影响功耗的表现。period 不是一个固定的时长（3.1 第二点介绍），在保证 Wi-Fi 通信正常的情况下，period 持续时间越短，功耗表现越好。但是减少 period 时间，必然会影响通信的可靠性。 + + - Base current 是 Wi-Fi 相关模块不工作时芯片的电流，影响其大小的因素很多，不同的功耗模式下休眠策略不同。所以，在满足功能的情况下，优化配置降低该电流大小可以提高功耗表现，但同时关闭其余模块会影响相关功能和芯片的唤醒时间。 + + 知道了影响功耗的三点因素之后，要想降低功耗应从这三点入手，接下来介绍两种低功耗模式，Modem sleep、Auto Light-sleep。两种模式主要区别就是对三点因素的优化不同。 + + + Modem-sleep Mode + ++++++++++++++++++ + + Modem-sleep 模式主要工作原理基于 DTIM 机制，周期性的醒来处理 Wi-Fi 相关工作，又在周期间隔之间进入休眠，关闭 PHY（RF 模块）来降低功耗。同时通过 DTIM 机制，station 可以与 AP 保持 Wi-Fi 连接，数据传输。 + + Modem-sleep 模式会在 Wi-Fi task 结束后自动进入休眠无需调用 API，休眠时仅会关闭 Wi-Fi 相关模块 (PHY)，其余模块均处在正常上电状态。 + + Modem-sleep 模式默认会根据 DTIM 周期或 listen interval（下文介绍）醒来，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源，同时系统主动发包时也可以唤醒。 + + Modem-sleep 是一个开关型的模式，调用 API 开启后一直自动运行，其工作流程十分简单，具体如下图。 + + .. figure:: ../../_static/Low-power-modem-process.png + :align: center + + Modem sleep 工作流程图 + + + 根据上文的基本电流图，结合 Modem-sleep 的 工作原理，以 Min Modem（下文介绍）为例可得理想情况下电流变化图。 + + .. figure:: ../../_static/Low-power-modem-current.png + :align: center + + Min Modem-sleep 理想电流图 + + Modem-sleep 一般用于 CPU 持续处于工作状态并需要保持 Wi-Fi 连接的应用场景，例如，使用 {IDF_TARGET_NAME} 本地语音唤醒功能，CPU 需要持续采集和处理音频数据。 + + DFS+Modem sleep + ++++++++++++++++++ + + Modem sleep 模式休眠状态中 CPU 仍处在工作状态，而 DFS 机制主要作用于 CPU 和 APB 工作频率来降低功耗，因此 DFS + Modem sleep 可以进一步优化功耗表现，又因为 Wi-Fi task 会申请 ESP_PM_CPU_FREQ_MAX 电源锁来保证 Wi-Fi 任务快速运行，所以 DFS + Modem sleep 产生调频只会发生在 base current 阶段，即 Wi-Fi task 结束后。 + + 在 Wi-Fi 场景下，为了介绍的简化，让用户抓住主要的变化，DFS 可以进行一定的状态简化。具体来说，虽然 DFS 主要根据 CPU 和 APB 两把锁的最高需求来调频，但是 Wi-Fi 场景都需要 CPU 的频率最大化来工作，同时 Wi-Fi task 结束后，也可以理想化的认为，没有其余的工作要完成，这样就可以简单认为经过一段时间会释放两把锁进入空闲状态（IDLE 状态），也同时忽略这段时间锁的变化导致的电流变化，简化状态。 + + 在 Wi-Fi 场景下，DFS 最终简化为如下流程： + + .. figure:: ../../_static/Low-power-DFS-process.png + :align: center + + Wi-Fi场景 DFS 简化流程图 + + 在 Wi-Fi 工作的 active 状态与系统空闲的 IDLE 状态转换，Wi-Fi task 结束后，系统经过一段时间释放了所有锁进入 IDLE 状态，此时 DFS 机制降低频率到设定最低值，忽略了转换状态期间的调频动作，方便理解。 + + 简化过后的 DFS+Modem sleep 模式理想状态下的电流大小如下图所示： + + .. figure:: ../../_static/Low-power-DFS-modem-current.png + :align: center + + DFS+Modem sleep 模式理想电流图 + + + Auto Light-sleep+Wi-Fi 场景 + +++++++++++++++++++++++++++++++ + + Auto Light-sleep 模式在 Wi-Fi 场景下是 ESP-IDF 电源管理机制、DTIM 机制和 light-sleep 的结合。开启电源管理是其前置条件，auto 体现在系统进入 IDLE 状态超过设定值后自动进入 light-sleep。同时 auto light sleep 模式同样遵循 DTIM 机制，会自动苏醒，可以与 AP 保持 Wi-Fi 连接。 + + Auto Light-sleep 模式在 Wi-Fi 场景下休眠机制与纯系统下一样，仍然依赖于电源管理机制，进入休眠的条件为系统处于 IDLE 状态的时间超过设定时间，并且系统会提前判断空闲时间是否满足条件，若满足直接休眠。该过程为自动进行。休眠时会自动关闭 RF、8 MHz 振荡器、40 MHz 高速晶振、PLL，门控数字内核时钟，暂停 CPU 工作。 + + Auto Light-sleep 模式在 Wi-Fi 场景下遵循 DTIM 机制，自动在 DTIM 帧到来前苏醒，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源。同时系统主动发包时也可以唤醒。 + + Auto Light-sleep 模式在 Wi-Fi 场景下工作流程较为复杂，但全程都是自动进行，具体如下图所示。 + + .. figure:: ../../_static/Low-power-wifi-auto-light-process.png + :align: center + + Auto Light-sleep 工作流程图 + + Auto Light-sleep 模式在 Wi-Fi 场景下经常与 modem sleep 同时开启，这里给出 modem+auto light-sleep 模式的理想电流图，关键节点均在图上标出。 + + .. figure:: ../../_static/Low-power-wifi-auto-light-current.png + :align: center + + modem+auto light-sleep 模式理想电流图 + + Auto Light-sleep 模式在 Wi-Fi 场景下可用于需要保持 Wi-Fi 连接，可以实时响应 AP 发来数据的场景。并且在未接收到命令时，CPU 可以处于空闲状态。比如 Wi-Fi 开关的应用，大部分时间 CPU 都是空闲的，直到收到控制命令，CPU 才需要进行 GPIO 的操作。 + + + Deep-sleep+Wi-Fi 场景 + +++++++++++++++++++++++++++++++++ + + Deep-sleep 模式在 Wi-Fi 场景下与纯系统下基本相同，详情可以参考 `Deep-sleep`_ 这里不再介绍。 + + + 如何配置 Wi-Fi 场景下低功耗模式 + +++++++++++++++++++++++++++++++++++++ + + 介绍完 Wi-Fi 场景下低功耗模式后，本节将介绍公共配置选项、每种模式独有的配置选项，以及相应低功耗模式 API 的使用说明，同时给出相应模式推荐的配置（包含纯系统下的低功耗推荐配置）以及该配置的具体表现。 + + 公共配置选项： + + - 功耗类： + + - Max Wi-Fi TX power (dBm) + 该参数表示最大 TX 功率，降低该参数会减小发包功耗，但会影响 Wi-Fi 性能，默认设置最大 20。 + + - IRAM 类： + + - Wi-Fi IRAM speed optimization + 如果使能该选项，一些 Wi-Fi 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加，默认开启。 + + - Wi-Fi RX IRAM speed optimization + 如果使能该选项，一些 Wi-Fi RX 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加，默认开启。 + + - Wi-Fi Sleep IRAM speed optimization + 如果使能该选项，一些 Wi-Fi sleep 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加，默认关闭。 + + - Wi-Fi 协议类： + + - Minimum active time + 该参数表示 Station 接收完一次数据后需要等待时间。当终端与 AP 进行通信时，AP 发送到终端的数据经常是突发形式的，为确保后续的突发数据能够正常接收到，需要等待一段时间。默认 50。 + + - Maximum keep alive time + 该参数表示周期性的发送 sleep null data 来通告 AP 维持连接的时间。在 DTIM 机制下，若 AP 长时间没有某个 station 的包，可能会断开连接，因此需要 station 需要周期发送 sleep null data 维持连接。默认 10。 + + - Send gratuitous ARP periodically + 如果使能该选项，Station 将周期性的发送 gratuitous ARP 请求更新 AP ARP 缓存表。如无该需求，可以关闭。 + + - Wi-Fi sleep optimize when beacon lost + 如果使能该选项，Station 在检测到已经错过或者丢失 beacon 时，会立即关闭 RF 进入低功耗状态。 + + Modem sleep 配置方法如下: + + - 可配置选项 + + - Min Modem + 该参数表示 station 按照 DTIM 周期工作，在每个 DTIM 前醒来接收 Beacon，这样不会漏掉广播信息，但是 DTIM 周期由 AP 决定，如果 DTIM 周期较短，省电效果会降低。 + + - Max Modem + 该参数表示 station 会自定义一个 listen interval，并以 listen interval 为周期醒来接受 Beacon。这样在 listen interval 较大时会省电，但是容易漏听 DTIM，错过广播数据。 + + + - 配置方法： + + - 调用 API，选择模式参数:: + + typedef enum { + WIFI_PS_NONE, + WIFI_PS_MIN_MODEM, + WIFI_PS_MAX_MODEM, + } wifi_ps_type_t; + esp_err_t esp_wifi_set_ps(wifi_ps_type_t type); + + 若选择 WIFI_PS_MAX_MODEM，还需配置 listen interval，示例如下:: + + #define LISTEN_INTERVAL 3 + wifi_config_t wifi_config = { + .sta = { + .ssid = "SSID", + .password = "Password", + .listen_interval = LISTEN_INTERVAL, + }, + }; + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); + ESP_ERROR_CHECK(esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_config)); + ESP_ERROR_CHECK(esp_wifi_start()); + + 配置推荐： + + 这里给出的配置推荐是 Min Modem sleep + DFS 开启的配置 + + .. list-table:: + :header-rows: 1 + :widths: 20 15 + + * - 配置名称 + - 设置情况 + + * - WIFI_PS_MIN_MODEM + - ON + + * - CONFIG_PM_ENABLE + - ON + + * - RTOS Tick rate (Hz) + - 1000 + + * - max_freq_mhz + - 160 + + * - min_freq_mhz + - 40 + + * - light_sleep_enable + - false + + 配置表现： + + .. include:: sleep-current/{IDF_TARGET_PATH_NAME}_modem_sleep.inc + + Auto Light-sleep + Wi-Fi 场景配置： + + Auto Light-sleep 在 Wi-Fi 场景下的配置比纯系统下少了唤醒源的配置要求，其余几乎与纯系统下配置一致，因此可配置选项、配置步骤、推荐配置的详细介绍可以参考上文 `Light-sleep`_。同时 Wi-Fi 相关配置保持默认。 + + 配置表现： + + 该配置表现为 Auto Light-sleep 纯系统推荐配置 + 默认的 Wi-Fi 相关配置在 Wi-Fi 场景的表现。 + + .. include:: sleep-current/{IDF_TARGET_PATH_NAME}_light_sleep.inc + + Deep-sleep + Wi-Fi 场景配置： + + Deep-sleep 模式在 Wi-Fi 场景下的配置与纯系统下配置基本一致，因此可配置选项、配置步骤、推荐配置的详细介绍可以参考上文 `Deep-sleep`_。同时 Wi-Fi 相关配置保持默认。 + + 配置表现： + + 该配置表现为 Deep-sleep 纯系统推荐配置 + 默认的 Wi-Fi 相关配置在 Wi-Fi 场景的表现。 + + .. only:: esp32 + + 平均电流约 5.0 μA + + .. only:: esp32s2 + + 平均电流约 5.0 μA + + .. only:: esp32s3 + + 平均电流约 6.9 μA + + .. only:: esp32c3 + + 平均电流约 4.8 μA + + .. only:: esp32c2 + + 平均电流约 4.9 μA + + diff --git a/docs/zh_CN/api-guides/lwip.rst b/docs/zh_CN/api-guides/lwip.rst index 3351164d65f..690c21f9686 100644 --- a/docs/zh_CN/api-guides/lwip.rst +++ b/docs/zh_CN/api-guides/lwip.rst @@ -13,6 +13,8 @@ ESP-IDF 支持以下 lwIP TCP/IP 协议栈功能： - `BSD 套接字 API`_ - `Netconn API`_ 已启用，但暂无对 ESP-IDF 应用程序的官方支持 +.. _lwip-dns-limitation: + 适配的 API ^^^^^^^^^^^^ @@ -23,6 +25,12 @@ ESP-IDF 支持以下 lwIP TCP/IP 协议栈功能： ESP-IDF 间接支持以下常见的 lwIP 应用程序 API： - 动态主机设置协议 (DHCP) 服务器和客户端，由 :doc:`/api-reference/network/esp_netif` 功能间接支持。 +- 域名系统 (DNS)；获取 DHCP 地址时，可以自动分配 DNS 服务器，也可以通过 :doc:`/api-reference/network/esp_netif` API 手动配置。 + +.. note:: + + lwIP 中的 DNS 服务器配置为全局配置，而非针对特定接口的配置。如需同时使用不同 DNS 服务器的多个网络接口，在从一个接口获取 DHCP 租约时，请注意避免意外覆盖另一个接口的 DNS 设置。 + - 简单网络时间协议 (SNTP)，由 :doc:`/api-reference/network/esp_netif` 功能间接支持，或通过 :component_file:`lwip/include/apps/esp_sntp.h` 中的函数直接支持。该函数还为 :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` 函数提供了线程安全的 API，请参阅 :ref:`system-time-sntp-sync`。 - ICMP Ping，由 lwIP ping API 的变体支持，请参阅 :doc:`/api-reference/protocols/icmp_echo`。 - ICMPv6 Ping，由 lwIP 的 ICMPv6 Echo API 支持，用于测试 IPv6 网络连接情况。有关详细信息，请参阅 :example:`protocols/sockets/icmpv6_ping`。 @@ -411,6 +419,8 @@ IP 层特性 - 支持 IPV4 映射 IPV6 地址 +.. _lwip-custom-hooks: + 自定义 lwIP 钩子 +++++++++++++++++++++ @@ -422,10 +432,25 @@ IP 层特性 target_compile_options(${lwip} PRIVATE "-I${PROJECT_DIR}/main") target_compile_definitions(${lwip} PRIVATE "-DESP_IDF_LWIP_HOOK_FILENAME=\"my_hook.h\"") +使用 ESP-IDF 构建系统自定义 lwIP 选项 +++++++++++++++++++++++++++++++++++++++++++++++++++ + +组件配置菜单可以配置常见的 lwIP 选项，但是一些自定义选项需要通过命令行添加。CMake 函数 ``target_compile_definitions()`` 可以用于定义宏，示例如下： + +.. code-block:: cmake + + idf_component_get_property(lwip lwip COMPONENT_LIB) + target_compile_definitions(${lwip} PRIVATE "-DETHARP_SUPPORT_VLAN=1") + +使用这种方法可能无法定义函数式宏。虽然 GCC 支持此类定义，但是未必所有编译器都会接受。为了解决这一限制，可以使用 ``add_definitions()`` 函数为整个项目定义宏，例如 ``add_definitions("-DFALLBACK_DNS_SERVER_ADDRESS(addr)=\"IP_ADDR4((addr), 8,8,8,8)\"")``。 + +另一种方法是在头文件中定义函数式宏，该头文件将预先包含在 lwIP 钩子文件中，请参考 :ref:`lwip-custom-hooks`。 限制 ^^^^^^^^^^^ +如 :ref:`lwip-dns-limitation` 所述，ESP-IDF 中的 lwIP 扩展功能仍然受到全局 DNS 限制的影响。为了在应用程序代码中解决这一限制，可以使用 ``FALLBACK_DNS_SERVER_ADDRESS()`` 宏定义所有接口能够访问的全局 DNS 备用服务器，或者单独维护每个接口的 DNS 服务器，并在默认接口更改时重新配置。 + 在 UDP 套接字上重复调用 ``send()`` 或 ``sendto()`` 最终可能会导致错误。此时 ``errno`` 报错为 ``ENOMEM``，错误原因是底层网络接口驱动程序中的 buffer 大小有限。当所有驱动程序的传输 buffer 已满时，UDP 传输事务失败。如果应用程序需要发送大量 UDP 数据报，且不希望发送方丢弃数据报，建议检查错误代码，采用短延迟的重传机制。 .. only:: esp32 @@ -446,9 +471,7 @@ IP 层特性 最大吞吐量 ^^^^^^^^^^^^^^^^^^ -在 :example:`wifi/iperf` 示例中，乐鑫测试了在射频密封的封闭环境下 ESP-IDF 的 TCP/IP 吞吐量。 - -iperf 示例下的 :example_file:`wifi/iperf/sdkconfig.defaults` 文件包含已知可最大化 TCP/IP 吞吐量的设置，但该设置会占用更多 RAM。要牺牲其他性能，在应用程序中最大化 TCP/IP 吞吐量，建议将该示例文件中的设置应用到项目的 sdkconfig 文件中。 +乐鑫使用 iperf 测试应用程序 https://iperf.fr/ 测试了 ESP-IDF 的 TCP/IP 吞吐量。关于实际测试和优化配置的更多信息，请参考 :ref:`improve-network-speed`。 .. important:: diff --git a/docs/zh_CN/api-guides/memory-types.rst b/docs/zh_CN/api-guides/memory-types.rst index 4262cd1e1ed..234584ac504 100644 --- a/docs/zh_CN/api-guides/memory-types.rst +++ b/docs/zh_CN/api-guides/memory-types.rst @@ -184,6 +184,14 @@ DROM（数据存储在 flash 中） 除非禁用 :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` 选项，否则剩余的 RTC FAST memory 会被添加到堆中。该部分内存可以和 :ref:`DRAM` 互换使用，但是访问速度稍慢一点。 +.. only:: SOC_MEM_TCM_SUPPORTED + + 紧密耦合内存 (TCM) + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + TCM 是靠近 CPU 放置的内存，支持在 CPU 频率下直接访问，无需通过 cache。虽然在一般情况下，TCM 的效率或速度相较 cache 偏低，但是访问 TCM 所需的时间是可以预测且始终一致的。具有稳定的访问速度对于时间关键型例程来说十分重要，因此 TCM 对于此类例程而言非常有用。 + + 具备 DMA 功能 ^^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-guides/partition-tables.rst b/docs/zh_CN/api-guides/partition-tables.rst index a62915c6f66..6d0c84e7fed 100644 --- a/docs/zh_CN/api-guides/partition-tables.rst +++ b/docs/zh_CN/api-guides/partition-tables.rst @@ -150,16 +150,19 @@ SubType 字段长度为 8 bit，内容与具体分区 Type 有关。目前，esp 组件可以通过设置 ``EXTRA_PARTITION_SUBTYPES`` 属性来定义额外的分区子类型。 ``EXTRA_PARTITION_SUBTYPES`` 是一个 CMake 列表，其中的每个条目由字符串组成，以逗号为分隔，格式为 ``, , ``。构建系统通过该属性会自动添加额外的子类型，并在 :cpp:type:`esp_partition_subtype_t` 中插入名为 ``ESP_PARTITION_SUBTYPE__`` 的字段。项目可以使用这个子类型来定义分区表 CSV 文件中的分区，并使用 :cpp:type:`esp_partition_subtype_t` 中的新字段。 -偏移地址 (Offset) 和 Size 字段 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. _partition-offset-and-size: -偏移地址表示 SPI flash 中的分区地址，扇区大小为 0x1000 (4 KB)。 因此，偏移地址必须是 4 KB 的倍数。 +偏移地址 (Offset) 和 大小 (Size) 字段 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -分区若偏移地址为空，则会紧跟着前一个分区之后开始；若为首个分区，则将紧跟着分区表开始。 +.. list:: -app 分区的偏移地址必须要与 0x10000 (64 K) 对齐，如果将偏移字段留空，``gen_esp32part.py`` 工具会自动计算得到一个满足对齐要求的偏移地址。如果 app 分区的偏移地址没有与 0x10000 (64 K) 对齐，则该工具会报错。 - -app 分区的大小和偏移地址可以采用十进制数、以 0x 为前缀的十六进制数，且支持 K 或 M 的倍数单位（分别代表 1024 和 1024*1024 字节）。 + - 偏移地址表示 SPI flash 中的分区地址，扇区大小为 0x1000 (4 KB)。因此，偏移地址必须是 4 KB 的倍数。 + - 若 CSV 文件中的分区偏移地址为空，则该分区会接在前一个分区之后；若为首个分区，则将接在分区表之后。 + - ``app`` 分区的偏移地址必须与 0x10000 (64 KB) 对齐。如果偏移字段留空，则 ``gen_esp32part.py`` 工具会自动计算得到一个满足对齐要求的偏移地址。如果 ``app`` 分区的偏移地址没有与 0x10000 (64 KB) 对齐，则该工具会报错。 + - ``app`` 分区的大小必须与 flash 扇区大小对齐。为 ``app`` 分区指定未对齐的大小将返回错误。 + :SOC_SECURE_BOOT_V1: - 若启用了安全启动 V1，则 ``app`` 分区的大小需与 0x10000 (64 KB) 对齐。 + - ``app`` 分区的大小和偏移地址可以采用十进制数或是以 0x 为前缀的十六进制数，且支持 K 或 M 的倍数单位（K 和 M 分别代表 1024 和 1024*1024 字节）。 如果你希望允许分区表中的分区采用任意起始偏移量 (:ref:`CONFIG_PARTITION_TABLE_OFFSET`)，请将分区表（CSV 文件）中所有分区的偏移字段都留空。注意，此时，如果你更改了分区表中任意分区的偏移地址，则其他分区的偏移地址也会跟着改变。这种情况下，如果你之前还曾设定某个分区采用固定偏移地址，则可能造成分区表冲突，从而导致报错。 diff --git a/docs/zh_CN/api-guides/performance/speed.rst b/docs/zh_CN/api-guides/performance/speed.rst index 3e4792d6e3e..678abf9e6d0 100644 --- a/docs/zh_CN/api-guides/performance/speed.rst +++ b/docs/zh_CN/api-guides/performance/speed.rst @@ -54,7 +54,7 @@ - 也可以使用标准 Unix 函数 ``gettimeofday()`` 和 ``utime()`` 来进行计时测量，尽管其开销略高一些。 - 此外，代码中包含 ``hal/cpu_hal.h`` 头文件，并调用 HAL 函数 ``cpu_hal_get_cycle_count()`` 可以返回已执行的 CPU 循环数。该函数开销较低，适用于高精度测量执行时间极短的代码。 - .. only:: not CONFIG_FREERTOS_UNICORE + .. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES CPU 周期是各核心独立计数的，因此本方法仅适用于测量中断处理程序或固定在单个核心上的任务。 @@ -159,7 +159,7 @@ ESP-IDF 启动的系统任务预设了固定优先级。启动时，一些任务 .. Note: 以下两个列表应保持一致，但第二个列表还展示了 CPU 亲和性。 -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES .. list:: @@ -176,7 +176,7 @@ ESP-IDF 启动的系统任务预设了固定优先级。启动时，一些任务 - 如果使用 :doc:`/api-reference/protocols/mqtt` 组件，它会创建优先级默认为 5 的任务（ :ref:`可配置 ` ），可通过 :ref:`CONFIG_MQTT_USE_CUSTOM_CONFIG` 调整，也可以在运行时通过 :cpp:class:`esp_mqtt_client_config_t` 结构体中的 ``task_prio`` 字段调整。 - 关于 ``mDNS`` 服务的任务优先级，参见 `性能优化 `__ 。 -.. only :: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES .. list:: @@ -204,11 +204,11 @@ ESP-IDF 启动的系统任务预设了固定优先级。启动时，一些任务 设定应用程序任务优先级 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES 由于 {IDF_TARGET_RF_TYPE} 操作饥饿可能导致系统不稳定，通常不建议让特定任务的优先级高于 {IDF_TARGET_RF_TYPE} 操作的内置优先级。对于非常短且无需网络的实时操作，可以使用中断服务程序或极受限的任务（仅运行极短时间）并设置为最高优先级 (24)。将特定任务优先级设为 19 不会妨碍较低层级的 {IDF_TARGET_RF_TYPE} 功能无延迟运行，但仍然会抢占 lwIP TCP/IP 堆栈以及其他非实时内部功能，这对于不执行网络操作的实时任务而言是最佳选项。lwIP TCP/IP 任务优先级 (18) 应高于所有执行 TCP/IP 网络操作的任务，以保证任务正常执行。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES 默认配置下，除了个别例外，尤其是 lwIP TCP/IP 任务，大多数内置任务都固定在核心 0 上执行。因此，应用程序可以方便地将高优先级任务放置在核心 1 上执行。优先级大于等于 19 的应用程序任务在核心 1 上运行时可以确保不会被任何内置任务抢占。为了进一步隔离各个 CPU 上运行的任务，配置 :ref:`lwIP 任务 ` ，可以使 lwIP 任务仅在核心 0 上运行，而非上述任一核心，这可能会根据其他任务的运行情况减少总 TCP/IP 吞吐量。 @@ -234,19 +234,21 @@ ESP-IDF 支持动态 :doc:`/api-reference/system/intr_alloc` 和中断抢占。 .. list:: - 调用 :cpp:func:`esp_intr_alloc` 时使用 ``ESP_INTR_FLAG_LEVEL2`` 或 ``ESP_INTR_FLAG_LEVEL3`` 等标志，可以为更重要的中断设定更高优先级。 - :not CONFIG_FREERTOS_UNICORE: - 将中断分配到不运行内置 {IDF_TARGET_RF_TYPE} 任务的 CPU 上执行，即默认情况下，将中断分配到核心 1 上执行，参见 :ref:`built-in-task-priorities` 。调用 :cpp:func:`esp_intr_alloc` 函数即可将中断分配到函数所在 CPU。 + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - 将中断分配到不运行内置 {IDF_TARGET_RF_TYPE} 任务的 CPU 上执行，即默认情况下，将中断分配到核心 1 上执行，参见 :ref:`built-in-task-priorities` 。调用 :cpp:func:`esp_intr_alloc` 函数即可将中断分配到函数所在 CPU。 - 如果确定整个中断处理程序可以在 IRAM 中运行（参见 :ref:`iram-safe-interrupt-handlers` ），那么在调用 :cpp:func:`esp_intr_alloc` 分配中断时，请设置 ``ESP_INTR_FLAG_IRAM`` 标志，这样可以防止在应用程序固件写入内置 SPI flash 时临时禁用中断。 - 即使是非 IRAM 安全的中断处理程序，如果需要频繁执行，可以考虑将处理程序的函数移到 IRAM 中，从而尽可能规避执行中断代码时发生 flash 缓存缺失的可能性（参见 :ref:`speed-targeted-optimizations` ）。如果可以确保只有部分处理程序位于 IRAM 中，则无需添加 ``ESP_INTR_FLAG_IRAM`` 标志将程序标记为 IRAM 安全。 +.. _improve-network-speed: + 提高网络速度 ----------------------------- .. list:: :SOC_WIFI_SUPPORTED: * 关于提高 Wi-Fi 网速，参见 :ref:`How-to-improve-Wi-Fi-performance` 和 :ref:`wifi-buffer-usage` 。 - * 关于提高 lwIP TCP/IP（Wi-Fi 和以太网）网速，参见 :ref:`lwip-performance` 。 - :SOC_WIFI_SUPPORTED: * 示例 :example:`wifi/iperf` 中的配置针对 Wi-Fi TCP/IP 吞吐量进行了大量优化。将文件 :example_file:`wifi/iperf/sdkconfig.defaults` 、 :example_file:`wifi/iperf/sdkconfig.defaults.{IDF_TARGET_PATH_NAME}` 和 :example_file:`wifi/iperf/sdkconfig.ci.99` 的内容追加到项目的 ``sdkconfig`` 文件中，即可添加所有相关选项。请注意，部分选项可能会导致可调试性降低、固件大小增加、内存使用增加或其他功能的性能降低等影响。为了获得最佳结果，请阅读上述链接文档，并据此确定哪些选项最适合当前应用程序。 - :SOC_EMAC_SUPPORTED: * 示例 :example:`ethernet/iperf` 中的配置针对以太网 TCP/IP 吞吐量进行了大量优化。如需了解详情，请查看 :example_file:`ethernet/iperf/sdkconfig.defaults`。请注意，部分选项可能会导致可调试性降低、固件大小增加、内存使用增加或其他功能的性能降低等影响。为了获得最佳结果，请阅读上述链接文档，并据此确定哪些选项最适合当前应用程序。 + * 关于提高 lwIP TCP/IP 网速，参见 :ref:`lwip-performance` 。 + :SOC_WIFI_SUPPORTED: * 示例 :example:`wifi/iperf` 中的配置针对 Wi-Fi TCP/IP 吞吐量进行了大量优化，但该配置会占用更多 RAM。将文件 :example_file:`wifi/iperf/sdkconfig.defaults` 、 :example_file:`wifi/iperf/sdkconfig.defaults.{IDF_TARGET_PATH_NAME}` 和 :example_file:`wifi/iperf/sdkconfig.ci.99` 的内容追加到项目的 ``sdkconfig`` 文件中，即可添加所有相关选项。请注意，部分选项可能会导致可调试性降低、固件大小增加、内存使用增加或其他功能的性能降低等影响。为了获得最佳结果，请阅读上述链接文档，并据此确定哪些选项最适合当前应用程序。 + :SOC_EMAC_SUPPORTED: * 示例 :example:`ethernet/iperf` 中的配置针对以太网 TCP/IP 吞吐量进行了大量优化，但该配置会占用更多 RAM。如需了解详情，请查看 :example_file:`ethernet/iperf/sdkconfig.defaults`。请注意，部分选项可能会导致可调试性降低、固件大小增加、内存使用增加或其他功能的性能降低等影响。为了获得最佳结果，请阅读上述链接文档，并据此确定哪些选项最适合当前应用程序。 提高 I/O 性能 ---------------------------------- diff --git a/docs/zh_CN/api-guides/startup.rst b/docs/zh_CN/api-guides/startup.rst index 155b3c6b4ea..29db52f7f46 100644 --- a/docs/zh_CN/api-guides/startup.rst +++ b/docs/zh_CN/api-guides/startup.rst @@ -3,13 +3,11 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} - 本文将会介绍 {IDF_TARGET_NAME} 从上电到运行 ``app_main`` 函数中间所经历的步骤（即启动流程）。 宏观上，该启动流程可以分为如下 3 个步骤： -1. :ref:`first-stage-bootloader` 被固化在了 {IDF_TARGET_NAME} 内部的 ROM 中，它会从 flash 的 {IDF_TARGET_BOOTLOADER_OFFSET} 偏移地址处加载二级引导程序至 RAM (IRAM & DRAM) 中。 +1. :ref:`first-stage-bootloader` 被固化在了 {IDF_TARGET_NAME} 内部的 ROM 中，它会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载二级引导程序至 RAM (IRAM & DRAM) 中。 2. :ref:`second-stage-bootloader` 从 flash 中加载分区表和主程序镜像至内存中，主程序中包含了 RAM 段和通过 flash 高速缓存映射的只读段。 @@ -22,11 +20,11 @@ 一级引导程序 ~~~~~~~~~~~~ -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES SoC 复位后，PRO CPU 会立即开始运行，执行复位向量代码，而 APP CPU 仍然保持复位状态。在启动过程中，PRO CPU 会执行所有的初始化操作。APP CPU 的复位状态会在应用程序启动代码的 ``call_start_cpu0`` 函数中失效。复位向量代码位于 {IDF_TARGET_NAME} 芯片掩膜 ROM 处，且不能被修改。 -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES SoC 复位后，CPU 会立即开始运行，执行所有的初始化操作。复位向量代码位于 {IDF_TARGET_NAME} 芯片掩膜 ROM 处，且不能被修改。 @@ -46,15 +44,19 @@ .. only:: esp32 - 二级引导程序二进制镜像会从 flash 的 ``0x1000`` 偏移地址处加载。如果正在使用 :doc:`/security/secure-boot-v1`，则 flash 的第一个 4 kB 扇区用于存储安全启动 IV 以及引导程序镜像的摘要，否则不使用该扇区。 + 二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。如果正在使用 :doc:`/security/secure-boot-v1`，则 flash 的第一个 4 kB 扇区用于存储安全启动 IV 以及引导程序镜像的摘要，否则不使用该扇区。 .. only:: esp32s2 - 二级引导程序二进制镜像会从 flash 的 ``0x1000`` 偏移地址处加载。该地址前面的 flash 4 kB 扇区未使用。 + 二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。该地址前面的 flash 4 kB 扇区未使用。 + +.. only:: esp32p4 - .. only:: not (esp32 or esp32s2) + 二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。该地址前面的 flash 8 kB 扇区将为密钥管理器保留，用于与 flash 加密 (AES-XTS) 相关的操作。 - 二级引导程序二进制镜像会从 flash 的 `` 0x0`` 偏移地址处加载。 + .. only:: not (esp32 or esp32s2 or esp32p4) + + 二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。 .. TODO: describe application binary image format, describe optional flash configuration commands. @@ -63,11 +65,11 @@ 二级引导程序 ~~~~~~~~~~~~ -在 ESP-IDF 中，存放在 flash 的 {IDF_TARGET_BOOTLOADER_OFFSET} 偏移地址处的二进制镜像就是二级引导程序。二级引导程序的源码可以在 ESP-IDF 的 :idf:`components/bootloader` 目录下找到。ESP-IDF 使用二级引导程序可以增加 flash 分区的灵活性（使用分区表），并且方便实现 flash 加密，安全引导和空中升级 (OTA) 等功能。 +在 ESP-IDF 中，存放在 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处的二进制镜像就是二级引导程序。二级引导程序的源码可以在 ESP-IDF 的 :idf:`components/bootloader` 目录下找到。ESP-IDF 使用二级引导程序可以增加 flash 分区的灵活性（使用分区表），并且方便实现 flash 加密，安全引导和空中升级 (OTA) 等功能。 当一级引导程序校验并加载完二级引导程序后，它会从二进制镜像的头部找到二级引导程序的入口点，并跳转过去运行。 -二级引导程序默认从 flash 的 ``0x8000`` 偏移地址处（:ref:`可配置的值 `）读取分区表。请参考 :doc:`分区表 ` 获取详细信息。引导程序会寻找工厂分区和 OTA 应用程序分区。如果在分区表中找到了 OTA 应用程序分区，引导程序将查询 ``otadata`` 分区以确定应引导哪个分区。更多信息请参考 :doc:`/api-reference/system/ota`。 +二级引导程序默认从 flash 的 {IDF_TARGET_CONFIG_PARTITION_TABLE_OFFSET} 偏移地址处（:ref:`可配置的值 `）读取分区表。请参考 :doc:`分区表 ` 获取详细信息。引导程序会寻找工厂分区和 OTA 应用程序分区。如果在分区表中找到了 OTA 应用程序分区，引导程序将查询 ``otadata`` 分区以确定应引导哪个分区。更多信息请参考 :doc:`/api-reference/system/ota`。 关于 ESP-IDF 引导程序可用的配置选项，请参考 :doc:`bootloader`。 @@ -76,7 +78,7 @@ - 对于在内部 :ref:`iram` 或 :ref:`dram` 中具有加载地址的段，将把数据从 flash 复制到它们的加载地址处。 - 对于一些加载地址位于 :ref:`drom` 或 :ref:`irom` 区域的段，通过配置 flash MMU，可为从 flash 到加载地址提供正确的映射。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: esp32 请注意，二级引导程序同时为 PRO CPU 和 APP CPU 配置 flash MMU，但仅使能 PRO CPU 的 flash MMU。原因是二级引导程序代码已加载到 APP CPU 的高速缓存使用的内存区域中。因此使能 APP CPU 高速缓存的任务就交给了应用程序。 @@ -112,15 +114,15 @@ ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start - 完成 MMU 高速缓存配置。 :SOC_SPIRAM_SUPPORTED: - 如果配置了 PSRAM，则使能 PSRAM。 - 将 CPU 时钟设置为项目配置的频率。 - :CONFIG_ESP_SYSTEM_MEMPROT_FEATURE: - 如果配置了内存保护，则初始化内存保护。 + :SOC_MEMPROT_SUPPORTED: - 如果配置了内存保护，则初始化内存保护。 :esp32: - 根据应用程序头部设置重新配置主 SPI flash，这是为了与 ESP-IDF V4.0 之前的引导程序版本兼容，请参考 :ref:`bootloader-compatibility`。 - :not CONFIG_FREERTOS_UNICORE: - 如果应用程序被配置为在多个内核上运行，则启动另一个内核并等待其初始化（在类似的“端口层”初始化函数 ``call_start_cpu1`` 内）。 + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - 如果应用程序被配置为在多个内核上运行，则启动另一个内核并等待其初始化（在类似的“端口层”初始化函数 ``call_start_cpu1`` 内）。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES ``call_start_cpu0`` 完成运行后，将调用在 :idf_file:`components/esp_system/startup.c` 中找到的“系统层”初始化函数 ``start_cpu0``。其他内核也将完成端口层的初始化，并调用同一文件中的 ``start_other_cores``。 -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES ``call_start_cpu0`` 完成运行后，将调用在 :idf_file:`components/esp_system/startup.c` 中找到的“系统层”初始化函数 ``start_cpu0``。 @@ -156,13 +158,13 @@ ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start 运行 ``app_main`` 的主任务有一个固定的 RTOS 优先级（比最小值高）和一个 :ref:`可配置的堆栈大小`。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES 主任务的内核亲和性也是可以配置的，请参考 :ref:`CONFIG_ESP_MAIN_TASK_AFFINITY`。 与普通的 FreeRTOS 任务（或嵌入式 C 的 ``main`` 函数）不同，``app_main`` 任务可以返回。如果``app_main`` 函数返回，那么主任务将会被删除。系统将继续运行其他的 RTOS 任务。因此可以将 ``app_main`` 实现为一个创建其他应用任务然后返回的函数，或主应用任务本身。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES APP CPU 的内核启动流程 ------------------------------------ @@ -175,4 +177,4 @@ ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start ``start_cpu_other_cores_default`` 函数做了一些与内核相关的系统初始化，然后等待 PRO CPU 启动 FreeRTOS 的调度器，启动完成后，它会执行 ``esp_startup_start_app_other_cores`` 函数，这是另一个默认为 ``esp_startup_start_app_other_cores_default`` 的弱链接函数。 - 默认情况下，``esp_startup_start_app_other_cores_default`` 只会自旋，直到 PRO CPU 上的调度器触发中断，以启动 APP CPU 上的 RTOS 调度器。 \ No newline at end of file + 默认情况下，``esp_startup_start_app_other_cores_default`` 只会自旋，直到 PRO CPU 上的调度器触发中断，以启动 APP CPU 上的 RTOS 调度器。 diff --git a/docs/zh_CN/api-guides/tools/idf-docker-image.rst b/docs/zh_CN/api-guides/tools/idf-docker-image.rst index c87bb7e9b2b..3338748c801 100644 --- a/docs/zh_CN/api-guides/tools/idf-docker-image.rst +++ b/docs/zh_CN/api-guides/tools/idf-docker-image.rst @@ -66,6 +66,10 @@ IDF Docker 镜像 (``espressif/idf``) 为使用特定版本的 ESP-IDF 自动化 - ``espressif/idf``：使用标签为 ``latest`` 的 Docker 镜像 ``espressif/idf``。未指定标签时，Docker 会隐式添加 ``latest`` 标签。 - ``idf.py build``：在容器内运行此命令。 +.. note:: + + 如果挂载目录 ``/project`` 包含的 git 仓库的用户 (``UID``) 不同于运行 Docker 容器的用户，在 ``/project`` 中执行 git 命令可能会失败，并显示错误信息 ``fatal: detected dubious ownership in repository at '/project'``。如需解决此问题，可以在启动 Docker 容器时设置 IDF_GIT_SAFE_DIR 环境变量，将 ``/project`` 目录指定为安全目录。例如，可以将 ``-e IDF_GIT_SAFE_DIR='/project'`` 作为参数包含，还可以使用分隔符 ``:`` 指定多个目录，或使用 ``*`` 完全禁用此项 git 安全检查。 + 要以特定 Docker 镜像标签进行构建，请将其指定为 ``espressif/idf:TAG``，示例如下： .. code-block:: bash @@ -139,7 +143,8 @@ ESP-IDF 库中的 Docker 文件提供了以下构建参数，可用于构建自 - ``IDF_CLONE_URL``：克隆 ESP-IDF 存储库的 URL。在使用 ESP-IDF 分支时，可以将该参数设置为自定义 URL，默认值为 ``https://github.com/espressif/esp-idf.git``。 - ``IDF_CLONE_BRANCH_OR_TAG``：克隆 ESP-IDF 时使用的 git 分支或标签的名称。该参数将作为 ``git clone`` 命令的 ``--branch`` 参数传递，默认值为 ``master``。 - ``IDF_CHECKOUT_REF``：如果将此参数设置为非空值，在克隆之后会执行 ``git checkout $IDF_CHECKOUT_REF`` 命令。可以将此参数设置为特定 commit 的 SHA 值，以便切换到所需的版本分支或 commit。例如，在希望使用特定版本分支上的某个 commit 时，就可以将此参数设置为该 commit 的 SHA 值。 -- ``IDF_CLONE_SHALLOW``：如果将此参数设置为非空值，则会在执行 ``git clone`` 时使用 ``--depth=1 --shallow-submodules`` 参数。这可以极大减少下载的数据量及生成的 Docker 镜像大小。然而，如果需要切换到此类“浅层”存储库中的其他分支，必须先执行额外的 ``git fetch origin `` 命令。 +- ``IDF_CLONE_SHALLOW``：如果将此参数设置为非空值，则会在执行 ``git clone`` 时使用 ``--depth=1 --shallow-submodules`` 参数。浅克隆的深度可以使用 ``IDF_CLONE_SHALLOW_DEPTH`` 设置。浅克隆可以极大减少下载的数据量及生成的 Docker 镜像大小。然而，如果需要切换到此类“浅层”存储库中的其他分支，必须先执行额外的 ``git fetch origin `` 命令。 +- ``IDF_CLONE_SHALLOW_DEPTH``：此参数指定进行浅克隆时要使用的深度值。如未设置，将使用 ``--depth=1``。此参数仅在使用 ``IDF_CLONE_SHALLOW`` 时有效。如果要为分支构建 Docker 镜像，并且该镜像必须包含该分支上的最新标签，则需使用此参数。要确定所需的深度，请在特定的分支运行 ``git describe`` 命令，并注意偏移值。将偏移值加 1 后即可将其用作 ``IDF_CLONE_SHALLOW_DEPTH`` 参数的值。此过程将确保生成的镜像包含分支上的最新标签，且 Docker 镜像内部的 ``git describe`` 命令也会按预期工作。 - ``IDF_INSTALL_TARGETS``：以逗号分隔的 ESP-IDF 目标列表，用于安装工具链，或者使用 ``all`` 安装所有目标的工具链。选择特定目标可以减少下载的数据量和生成的 Docker 镜像的大小。该参数默认值为 ``all``。 要使用以上参数，请通过 ``--build-arg`` 命令行选项传递。例如，以下命令使用 ESP-IDF v4.4.1 的浅克隆以及仅适用于 ESP32-C3 的工具链构建了 Docker 镜像： diff --git a/docs/zh_CN/api-guides/tools/idf-monitor.rst b/docs/zh_CN/api-guides/tools/idf-monitor.rst index 3e5c96f6de4..2087569faf0 100644 --- a/docs/zh_CN/api-guides/tools/idf-monitor.rst +++ b/docs/zh_CN/api-guides/tools/idf-monitor.rst @@ -33,8 +33,8 @@ IDF 监视器是一个串行终端程序，使用了 esp-idf-monitor_ 包，用 - 将 exit 字符发送至远程 - * - * Ctrl + P - - 重置目标设备，进入引导加载程序，通过 RTS 线暂停应用程序 - - 重置目标设备，通过 RTS 线（如已连接）进入引导加载程序，此时开发板不运行任何程序。等待其他设备启动时可以使用此操作。 + - 重置目标设备，进入引导加载程序，通过 RTS 和 DTR 线暂停应用程序 + - 重置目标设备，通过 RTS 和 DTR 线（如已连接）进入引导加载程序。这会阻止开发板运行任何程序，在等待其他设备启动时可以使用此操作。更多详细信息，请参考 :ref:`target-reset-into-bootloader`。 * - * Ctrl + R - 通过 RTS 线重置目标设备 - 重置设备，并通过 RTS 线（如已连接）重新启动应用程序。 @@ -235,6 +235,81 @@ ROM ELF 文件会根据 ``IDF_PATH`` 和 ``ESP_ROM_ELF_DIR`` 环境变量的路 ``--no-reset`` 选项在 IDF 监视器连接到特定端口时可以实现同样的效果，如 ``idf.py monitor --no-reset -p [PORT]``。 +.. _target-reset-into-bootloader: + +复位目标到引导加载程序 +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +IDF 监视器可以通过预定义的复位序列将芯片复位到引导加载程序，该序列已经经过调整，可以在大多数环境中正常工作。此外，用户可以设置自定义复位序列。通过对复位序列进行微调，使其适应各种情况。 + +使用预定义的复位序列 +-------------------------------- + +IDF 监视器的默认复位序列可在大多数环境中使用。使用默认序列复位芯片到引导加载程序中，无需进行额外配置。 + +自定义复位序列 +--------------------- + +对于高级用户或特定用例，IDF 监视器支持使用 :ref:`configuration-file` 配置自定义复位序列。这在默认序列可能不足的极端情况下特别有用。 + +复位序列可通过以下格式的字符串定义： + +- 各个命令由 ``|`` 分隔（例如 ``R0|D1|W0.5``）。 +- 命令（例如 ``R0``）由代码（``R``）和参数（``0``）定义。 + +.. list-table:: + :header-rows: 1 + :widths: 15 50 35 + :align: center + + * - 代码 + - 操作 + - 参数 + * - D + - 设置 DTR 控制线 + - ``1``/``0`` + * - R + - 设置 RTS 控制线 + - ``1``/``0`` + * - U + - 同时设置 DTR 和 RTS 控制线（仅适用于类 Unix 系统） + - ``0,0``/``0,1``/``1,0``/``1,1`` + * - W + - 等待 ``N`` 秒（其中 ``N`` 为浮点数） + - N + +示例： + +.. code-block:: ini + + [esp-idf-monitor] + custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 + +有关更多详细信息，请参阅 Esptool 文档中 `custom reset sequence`_ 章节。请注意，IDF 监视器只使用了 Esptool 配置中的 ``custom_reset_sequence`` 值，其他值会被 IDF 监视器忽略。 + +IDF 监视器和 Esptool 之间共享配置 +---------------------------------------------- + +自定义复位序列的配置可以在 IDF 监视器和 Esptool 之间的共享配置文件中指定。在这种情况下，为了使两个工具都能识别配置文件，其名称应为 ``setup.cfg`` 或 ``tox.ini``。 + +共享配置文件的示例： + +.. code-block:: ini + + [esp-idf-monitor] + menu_key = T + skip_menu_key = True + + [esptool] + custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0 + +.. note:: + + 当在 ``[esp-idf-monitor]`` 部分和 ``[esptool]`` 部分都使用 ``custom_reset_sequence`` 参数时，IDF 监视器会优先使用 ``[esp-idf-monitor]`` 部分的配置。``[esptool]`` 部分中任何与之冲突的配置都将被忽略。 + + 当配置分散在多个文件中时，此优先规则也适用。全局 esp-idf-monitor 配置将优先于本地 esptool 配置。 + + 配置 GDBStub 以启用 GDB ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -256,11 +331,15 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 输出筛选 ~~~~~~~~~~~~~~~~ -可以调用 ``idf.py monitor --print-filter="xyz"`` 启动 IDF 监视器，其中，``--print-filter`` 是输出筛选的参数。参数默认值为空字符串，可打印任何内容。 +可以调用 ``idf.py monitor --print-filter="xyz"`` 启动 IDF 监视器，其中，``--print-filter`` 是输出筛选的参数。参数默认值为空字符串，即打印所有内容。支持使用环境变量 ``ESP_IDF_MONITOR_PRINT_FILTER`` 调整筛选设置。 + +.. note:: + + 同时使用环境变量 ``ESP_IDF_MONITOR_PRINT_FILTER`` 和参数 ``--print-filter`` 时，通过命令行输入的 CLI 参数 ``--print-filter`` 优先级更高。 若需对打印内容设置限制，可指定 ``:`` 等选项，其中 ```` 是标签字符串，```` 是 ``{N, E, W, I, D, V, *}`` 集合中的一个字母，指的是 :doc:`日志 <../../api-reference/system/log>` 级别。 -例如，``PRINT_FILTER="tag1:W"`` 只匹配并打印 ``ESP_LOGW("tag1", ...)`` 所写的输出，或者写在较低日志详细度级别的输出，即 ``ESP_LOGE("tag1", ...)``。请勿指定 ```` 或使用详细级别默认值 ``*``。 +例如，``--print_filter="tag1:W"`` 只匹配并打印 ``ESP_LOGW("tag1", ...)`` 所写的输出，或者写在较低日志详细度级别的输出，即 ``ESP_LOGE("tag1", ...)``。请勿指定 ```` 或使用详细级别默认值 ``*``。 .. note:: @@ -273,7 +352,7 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 筛选规则示例 ~~~~~~~~~~~~~~~~ -- ``*`` 可用于匹配任何类型标签。但 ``PRINT_FILTER="*:I tag1:E"`` 打印关于 ``tag1`` 的输出时会报错，这是因为 ``tag1`` 规则比 ``*`` 规则的优先级高。 +- ``*`` 可用于匹配任何类型标签。但 ``--print_filter="*:I tag1:E"`` 打印关于 ``tag1`` 的输出时会报错，这是因为 ``tag1`` 规则比 ``*`` 规则的优先级高。 - 默认规则（空）等价于 ``*:V``，因为在详细级别或更低级别匹配任意标签即意味匹配所有内容。 - ``"*:N"`` 不仅抑制了日志功能的输出，也抑制了 ``printf`` 的打印输出。为了避免这一问题，请使用 ``*:E`` 或更高的冗余级别。 - 规则 ``"tag1:V"``、``"tag1:v"``、``"tag1:"``、``"tag1:*"`` 和 ``"tag1"`` 等同。 @@ -300,12 +379,12 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 D (318) vfs: esp_vfs_register_fd_range is successful for range <54; 64) and VFS ID 1 I (328) wifi: wifi driver task: 3ffdbf84, prio:23, stack:4096, core=0 -``PRINT_FILTER="wifi esp_image:E light_driver:I"`` 筛选选项捕获的输出如下所示:: +``--print_filter="wifi esp_image:E light_driver:I"`` 筛选选项捕获的输出如下所示:: E (31) esp_image: image at 0x30000 has invalid magic byte I (328) wifi: wifi driver task: 3ffdbf84, prio:23, stack:4096, core=0 -``PRINT_FILTER="light_driver:D esp_image:N boot:N cpu_start:N vfs:N wifi:N *:V"`` 选项的输出如下:: +``--print_filter="light_driver:D esp_image:N boot:N cpu_start:N vfs:N wifi:N *:V"`` 选项的输出如下:: load:0x40078000,len:13564 entry 0x40078d4c @@ -313,6 +392,8 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 D (309) light_driver: [light_init, 74]:status: 1, mode: 2 +.. _configuration-file: + 配置文件 ======== @@ -392,6 +473,9 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 * - skip_menu_key - 设置使用菜单命令时无需按下主菜单键 - ``False`` + * - custom_reset_sequence + - 复位目标到引导加载程序的自定义复位序列 + - 无默认值 语法 @@ -399,7 +483,7 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 配置文件为 .ini 文件格式，必须以 ``[esp-idf-monitor]`` 标头引入才能被识别为有效文件。以下语法以“配置名称 = 配置值”形式列出。以 ``#`` 或 ``;`` 开头的行是注释，将被忽略。 -.. code-block:: text +.. code-block:: ini # esp-idf-monitor.cfg file to configure internal settings of esp-idf-monitor [esp-idf-monitor] @@ -419,12 +503,7 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过 IDF 监视器已知问题 ================================= -Windows 环境下已知问题 -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- 由于 Windows 控制台限制，有些箭头键及其他一些特殊键无法在 GDB 中使用。 -- 偶然情况下，``idf.py`` 退出时，可能会在 IDF 监视器恢复之前暂停 30 秒。 -- GDB 运行时，可能会暂停一段时间，然后才开始与 GDBStub 进行通信。 +如果在使用 IDF 监视器过程中遇到任何问题，请查看我们的 `GitHub 仓库 `_ 以获取已知问题列表及其当前状态。如果遇到的问题没有相关记录，请创建一个新的问题报告。 .. _addr2line: https://sourceware.org/binutils/docs/binutils/addr2line.html .. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor @@ -432,3 +511,4 @@ Windows 环境下已知问题 .. _pySerial: https://github.com/pyserial/pyserial .. _miniterm: https://pyserial.readthedocs.org/en/latest/tools.html#module-serial.tools.miniterm .. _C0 控制字符: https://zh.wikipedia.org/wiki/C0%E4%B8%8EC1%E6%8E%A7%E5%88%B6%E5%AD%97%E7%AC%A6#C0_(ASCII%E5%8F%8A%E5%85%B6%E6%B4%BE%E7%94%9F) +.. _custom reset sequence: https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/esptool/configuration-file.html#custom-reset-sequence diff --git a/docs/zh_CN/api-guides/tools/idf-py.rst b/docs/zh_CN/api-guides/tools/idf-py.rst index 6e21802bea0..38162c5bca0 100644 --- a/docs/zh_CN/api-guides/tools/idf-py.rst +++ b/docs/zh_CN/api-guides/tools/idf-py.rst @@ -140,8 +140,6 @@ ESP-IDF 支持多个目标芯片，运行 ``idf.py --list-targets`` 查看当前 命令 ``idf.py`` 支持 bash、zsh 和 fish shell 的 `shell 自动补全 `_。 -为实现 `shell 自动补全 `_，请确保 Python 版本为 3.5 及以上，`click `_ 版本为 7.1 及以上（请参阅 :ref:`软件 `）。 - 调用命令 ``export`` 为 ``idf.py`` 启用自动补全（:ref:`第四步：设置环境变量 `），按 TAB 键启动自动补全。输入 ``idf.py -`` 并按 TAB 键以自动补全选项。 预计未来版本将支持 PowerShell 自动补全。 @@ -237,6 +235,23 @@ ESP-IDF 支持多个目标芯片，运行 ``idf.py --list-targets`` 查看当前 - ``--cmake-warn-uninitialized`` （或 ``-w``）将使 CMake 只显示在工程目录中发现的变量未初始化的警告，该选项仅控制 CMake 内部的 CMake 变量警告，不控制其他类型的构建警告。将环境变量 ``IDF_CMAKE_WARN_UNINITIALIZED`` 设置为非零值，可永久启用该选项。 - ``--no-hints`` 用于禁用有关错误处理的提示并禁用捕获输出。 +通过 ``@file`` 传递参数 +--------------------------------- + +可以通过文件向 ``idf.py`` 传递多个参数。该文件或文件路径须在开头使用 ``@`` 进行标注。文件中的参数支持通过换行或空格分隔，并按其在 idf.py 命令行中的顺序扩展。 + +例如，当前有文件 `custom_flash.txt`： + +.. code-block:: bash + + flash --baud 115200 + +运行命令：``idf.py @custom_flash.txt monitor`` + +文件中的参数可以与额外的命令行参数结合使用，也支持同时使用带有 ``@`` 标注的多个文件。例如，另有一个文件 ``another_config.txt``，此时，可以通过指定 ``idf.py @custom_flash.txt @another_config.txt monitor`` 同时使用两个文件。 + +关于参数文件的更多示例，如通过 @filename 创建配置文件概要，请参阅 :example_file:`多个构建配置示例 `。 + .. _cmake: https://cmake.org .. _ninja: https://ninja-build.org .. _esptool.py: https://github.com/espressif/esptool/#readme diff --git a/docs/zh_CN/api-guides/tools/index.rst b/docs/zh_CN/api-guides/tools/index.rst index 29f134ba776..6702bcd48f1 100644 --- a/docs/zh_CN/api-guides/tools/index.rst +++ b/docs/zh_CN/api-guides/tools/index.rst @@ -11,3 +11,4 @@ idf-component-manager idf-clang-tidy idf-tools + :esp32 or esp32c3: qemu diff --git a/docs/zh_CN/api-guides/tools/qemu.rst b/docs/zh_CN/api-guides/tools/qemu.rst new file mode 100644 index 00000000000..bcb3ef6d2e3 --- /dev/null +++ b/docs/zh_CN/api-guides/tools/qemu.rst @@ -0,0 +1 @@ +.. include:: ../../../en/api-guides/tools/qemu.rst diff --git a/docs/zh_CN/api-guides/unit-tests.rst b/docs/zh_CN/api-guides/unit-tests.rst index 9ef5113fda1..11011e3c804 100644 --- a/docs/zh_CN/api-guides/unit-tests.rst +++ b/docs/zh_CN/api-guides/unit-tests.rst @@ -185,6 +185,11 @@ DUT2 (slave) 终端:: 运行单元测试 -------------- +.. note:: + + 我们还提供基于 pytest 的框架 `pytest-embedded `_，以便更方便、高效地运行单元测试。如需在 CI 中运行测试或连续运行多个测试，不妨尝试这一框架。了解更多信息，请查看 `pytest-embedded 文档 `_ 和 :doc:`/contribute/esp-idf-tests-with-pytest`。 + + 烧写完成后重启 {IDF_TARGET_NAME}， 它将启动单元测试程序。 当单元测试应用程序空闲时，输入回车键，它会打印出测试菜单，其中包含所有的测试项目:: diff --git a/docs/zh_CN/api-guides/usb-serial-jtag-console.rst b/docs/zh_CN/api-guides/usb-serial-jtag-console.rst index 73ffb2a0da4..ae6d2bfbc5e 100644 --- a/docs/zh_CN/api-guides/usb-serial-jtag-console.rst +++ b/docs/zh_CN/api-guides/usb-serial-jtag-console.rst @@ -89,6 +89,10 @@ USB 串行/JTAG 控制台功能存在一些限制，这些限制的影响程度 对于从 PC 终端发送到 {IDF_TARGET_NAME} 的数据（如控制台命令），许多 PC 终端会等待 {IDF_TARGET_NAME} 接收字节后，再允许发送更多数据。这与使用 USB 转串口 (URAT) 桥接芯片不同，URAT 桥接芯片始终接收字节，并将其发送到（可能未在监听）的 {IDF_TARGET_NAME}。 +.. note:: + + 在极少数情况下，从 {IDF_TARGET_NAME} 发送到主机的数据可能会“阻塞”在主机内存中。继续发送数据即可“取消阻塞”，但如果应用程序未继续发送数据，则需要手动将这些数据刷新到主机。能否继续发送数据取决于驱动程序，默认配置的非阻塞驱动程序和 VFS 实现会在换行后自动刷新，而基于中断的阻塞驱动程序会在发送缓冲区变空时自动刷新。 + 睡眠模式考虑因素 ------------------------- diff --git a/docs/zh_CN/api-guides/wifi.rst b/docs/zh_CN/api-guides/wifi.rst index 0683933e7ae..79830c3267b 100644 --- a/docs/zh_CN/api-guides/wifi.rst +++ b/docs/zh_CN/api-guides/wifi.rst @@ -1727,6 +1727,8 @@ WPA2-Enterprise 是企业无线网络的安全认证机制。在连接到接入 {IDF_TARGET_NAME} Wi-Fi 节能模式 ----------------------------------------- +本小节将简单介绍Wi-Fi节能模式相关的概念和使用方式，更加详细的介绍请参考 :doc:`低功耗模式使用指南 <../api-guides/low-power-mode>`。 + station 睡眠 ++++++++++++++++++++++ @@ -3674,738 +3676,6 @@ Wi-Fi AMPDU 通常，应使能 AMPDU。禁用 AMPDU 通常用于调试目的。 -如何使用低功耗模式 ------------------------ - -对于物联网应用场景，终端的待机性能表现十分重要，本文档旨在介绍 {IDF_TARGET_NAME} 低功耗的基本原理，同时介绍 {IDF_TARGET_NAME} 支持的低功耗模式，需注意本文档主要针对 station mode。文档还会具体给出每种模式的配置步骤、推荐配置和功耗表现，以帮助用户根据实际需求快速配置适合的低功耗模式。 - -纯系统下低功耗模式介绍 -++++++++++++++++++++++++++++++++++ - -低功耗模式不仅涉及到系统相关问题，还涉及到芯片具体的工作场景，如处在 Wi-Fi 工作场景就会与处在蓝牙工作场景时产生不同。为此本节将首先介绍纯系统角度，即不涉及具体场景的低功耗模式，主要有 DFS、Light-sleep、Deep-sleep。纯系统下的低功耗模式主要思想就是在休眠时关闭或门控一些功能模块来降低功耗。 - -DFS -++++++++++++++++++++++++++++++++++ - -DFS (Dynamic frequency scaling) 即动态频率切换，是 ESP-IDF 中集成的电源管理机制的基础功能。DFS 可以根据应用程序持有电源锁的情况，调整外围总线 (APB) 频率和 CPU 频率。持有高性能锁就使用高频，空闲状态不持有电源锁时则使用低频来降低功耗，以此来尽可能减少运行应用程序的功耗。 - -DFS 的调频机制即根据持有电源锁的最大频率需求来调整频率，同时，freertos tick rates 的数值也会对 DFS 调频产生影响。系统任务调度的灵敏度越大，则意味着系统能更及时的根据需求调整频率。有关调频机制的详细信息，请参见 :doc:`电源管理 <../api-reference/system/power_management>`。 - -下图为 DFS 调频机制运行的理想电流情况。 - -.. figure:: ../../_static/Low-power-DFS-current.png - :align: center - - 理想 DFS 机制调频电流图 - -DFS 适用于 CPU 必须处于工作状态但是对低功耗有需求的场景，因此 DFS 经常与其他低功耗模式共同开启，下文会详细介绍。 - -Light-sleep -++++++++++++++++++++++++++++++++++ - -Light-sleep 模式是 {IDF_TARGET_NAME} 预设的一种低功耗模式，其核心思想就是在休眠时关闭或门控一些功能模块来降低功耗。从纯系统方面来说，Light-sleep 模式有两种进入方式，一种是通过 API 调用进入休眠，一种是自动进入的 auto 模式。两种模式都需要配置唤醒源进行唤醒，同时在进入休眠后会门控或关闭一些模块。这里主要介绍 Auto Light-sleep 模式。 - -Auto Light-sleep 模式是 ESP-IDF 电源管理机制和 Light-sleep 模式的结合。开启电源管理机制是其前置条件，auto 体现在系统进入空闲状态 (IDLE) 超过设定时间后，自动进入 Light-sleep。空闲状态下，应用程序释放所有电源锁，此时，DFS 将降频以减小功耗。 - -Auto Light-sleep 依赖于电源管理机制，系统经过提前判断，发现空闲时间超过设定时间时，则直接进入休眠。该过程为自动进行。休眠时会自动关闭 RF、8 MHz 振荡器、40 MHz 高速晶振、PLL、门控数字内核时钟，暂停 CPU 工作。 - -Auto Light-sleep 模式需配置唤醒源。该模式拥有多种唤醒源，支持相互组合，此时任何一个唤醒源都可以触发唤醒。唤醒后，会从进入休眠的位置继续执行程序。若不配置唤醒源，进入 Light-sleep 休眠后，芯片将一直处在睡眠状态，直到外部复位。具体唤醒源有 RTC 定时器、触摸传感器、外部唤醒 (ext0)、外部唤醒 (ext1)、ULP 协处理器、SDIO、GPIO、UART、Wi-Fi、BT 唤醒等。 - -Auto Light-sleep 模式工作流程相对复杂，但是进入休眠状态是自动进行，同时需注意在进入前配置好唤醒源，防止芯片一直处在休眠状态。 - -.. figure:: ../../_static/Low-power-auto-light-sleep-process.png - :align: center - - Auto Light-sleep 模式工作流程图 - -根据 Auto Light-sleep 的工作流程可得其理想电流图，关键节点均在图上标出。 - -.. figure:: ../../_static/Low-power-auto-light-sleep-current.png - :align: center - - Auto Light-sleep 模式模式理想电流图 - -.. note:: - 为更加清晰地展现出 Auto Light-sleep 的主要变化，图中省略了 DFS 降频过程。 - -Auto Light-sleep 模式适用于不需要实时响应外界需求的场景。 - -Deep-sleep -++++++++++++++++++++++++++++++++++ - -Deep-sleep 模式是为了追求更好的功耗表现所设计，休眠时仅保留 RTC 控制器、RTC 外设（可配置）、ULP 协处理器、RTC 高速内存、RTC 低速内存，其余模块全部关闭。与 Light-sleep 类似，Deep-sleep 同样通过 API 进入，且需要配置唤醒源进行唤醒。 - -Deep-sleep 通过调用 API 进入，休眠时会关闭除 RTC 控制器、RTC 外设、ULP 协处理器、RTC 高速内存、RTC 低速内存外的所有模块。 - -Deep-sleep 模式需配置唤醒源，其拥有多种唤醒源，这些唤醒源也可以组合在一起，此时任何一个唤醒源都可以触发唤醒。若不配置唤醒源进入 Deep-sleep 模式，芯片将一直处在睡眠状态，直到外部复位。具体唤醒源有 RTC 定时器、触摸传感器、外部唤醒 (ext0)、外部唤醒 (ext1)、ULP 协处理器、GPIO 唤醒等。 - -Deep-sleep 模式工作流程如下图所示： - -.. figure:: ../../_static/Low-power-deep-sleep-process.png - :align: center - - Deep-sleep 模式工作流程图 - -Deep-sleep 模式主要应用场景决定了系统很长时间才会苏醒一次，完成工作后又会继续进入 Deep-sleep，所以其理想电流图如下。 - -.. figure:: ../../_static/Low-power-deep-sleep-current.png - :align: center - - Deep-sleep 模式理想电流图 - -Deep-sleep 可以用于低功耗的传感器应用，或是大部分时间都不需要进行数据传输的情况，也就是通常所说的待机模式。设备可以每隔一段时间从 Deep-sleep 状态醒来测量数据并上传，之后重新进入 Deep-sleep；也可以将多个数据存储于 RTC memory，然后一次性发送出去。 - -如何配置纯系统下低功耗模式 -+++++++++++++++++++++++++++++++++++++ - -介绍完纯系统下的低功耗模式后，本节将介绍公共配置选项、每种模式独有的配置选项，以及相应低功耗模式 API 的使用说明，同时给出相应模式推荐的配置。 - -公共配置选项 -+++++++++++++ - -.. only:: esp32 or esp32s3 - - - 单双核工作模式 - 对于多核心芯片，可以选择单核工作模式。 - - - - RTOS Tick rate (Hz) - 该参数表示系统周期任务调度的频率。例如，当 RTOS Tick rate 配置为 1000 时，系统每毫秒都会进行一次任务调度；空闲时，系统也能够更敏锐的感知到空闲状态。 - - -DFS 配置 -+++++++++++++++++++++++ - -DFS 有如下可配置选项： - -- max_freq_mhz - 该参数表示最大 CPU 频率 (MHz)，即 CPU 最高性能工作时候的频率，一般设置为芯片参数的最大值。 - -- min_freq_mhz - 该参数表示最小 CPU 频率 (MHz)，即系统处在空闲状态时 CPU 的工作频率。该字段可设置为晶振 (XTAL) 频率值，或者 XTAL 频率值除以整数。 - -- light_sleep_enable - 使能该选项，系统将在空闲状态下自动进入 Light-sleep 状态，即 Auto Light-sleep 使能，上文已经具体介绍。 - -具体配置方法如下： - -- 1. 使能 CONFIG_PM_ENABLE -- 2. 配置 max_freq_mhz 和 min_freq_mhz，方式如下: - - :: - - esp_pm_config_t pm_config = { - .max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ, - .min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ, - .light_sleep_enable = flase - }; - ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); - -推荐配置： - -.. list-table:: - :header-rows: 1 - :widths: 20 20 - - * - 配置名称 - - 设置情况 - - * - CONFIG_PM_ENABLE - - ON - - * - RTOS Tick rate (Hz) - - 1000 - - * - max_freq_mhz - - 160 - - * - min_freq_mhz - - 40 - - * - light_sleep_enable - - false - -.. note:: - 上表中不涉及的配置均是默认。 - - -Light-sleep 配置 -+++++++++++++++++++ - -本节介绍 Auto Light-sleep 的推荐配置和配置步骤。 - -Auto Light-sleep 有如下可配置选项： - -- Minimum step to enter sleep mode - 该参数表示系统自动进入休眠的阈值。该参数单位为 RTOS Tick，故其表示的时间与 RTOS Tick rate 相关，例该参数值为 3，RTOS Tick rate 配置为 1000 Hz 时，即当系统空闲时间大于等于 3 ms 时进入 休眠。 - -- Put light sleep related codes in internal RAM - 如果使能该选项，一些 light-sleep 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加 1.8kB。 - -- Put RTOS IDLE related codes in internal RAM - 如果使能该选项，一些 RTOS IDLE 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加 260B。 - -- RTC slow clock source - 该参数表表示 RTC 慢速时钟源。系统休眠时计时器模块的时钟被门控，此时使用 RTC Timer 进行计时，唤醒后使用 RTC Timer 的计数值对系统时间进行补偿。 - -.. list-table:: - :header-rows: 1 - :widths: 20 20 20 - - * - 时钟源 - - 精度 - - 频偏 - - * - Internal 150kHz OSC - - 约6.7us/cycle - - 大 - - * - External 32kHz XTAL - - 约30.5us/cycle - - 小 - -- Disable all GPIO when chip at sleep - 如果使能该选项，系统将在休眠过程中禁用所有 GPIO 管脚，消除 GPIO 漏电，降低功耗，但是休眠过程中 GPIO 无法进行信号输入和输出。 - -.. only:: esp32c3 or esp32s3 - - - Power down MAC and baseband - 如果使能该选项，系统将在休眠时关闭 Wi-Fi 和蓝牙的 MAC 和 baseband 来降低功耗，休眠电流约降低 100 uA， 但是为保存上下文信息，将额外消耗 5.3 K DRAM。 - - - Power down CPU - 如果使能该选项，系统将在休眠时将关闭 CPU 来降低功耗，对于 esp32c3，休眠电流减小 100 uA 左右，对于 esp32s3，休眠电流减小 650 uA 左右。但是为保存上下文信息，对于 esp32c3，将消耗 1.6 KB 的 DRAM 空间，对于 esp32s3，将消耗 8.58 KB 的 DRAM 空间。 - - - Power down I/D-cache tag memory - 如果使能该选项，系统将在休眠时关闭 I/D cache tag memory 来降低功耗， 但是为保存 tag memory 信息，将额外消耗最大约 9 KB DRAM，同时因为 tag memory 信息特殊性，如需打开该选项，建议多进行测试。 - - - Power down flash in Light-sleep - 如果使能该选项，系统将在 Light-sleep 休眠时关闭 flash，降低系统功耗，该选项的前提是系统没有使用 PSRAM。 - -唤醒源： - -- RTC Timer Wakeup -- GPIO Wakeup -- UART Wakeup -- Touchpad Wakeup -- External Wakeup (ext0) -- External Wakeup (ext1) -- ULP Coprocessor Wakeup - -.. note:: - 以上仅列出可配置唤醒源，详细介绍请参考:doc:`睡眠模式 <../api-reference/system/sleep_modes>`。 - -配置方法： - -- 1. 配置唤醒源 -- 2. 使能 CONFIG_PM_ENABLE -- 3. 使能 CONFIG_FREERTOS_USE_TICKLESS_IDLE -- 4. 配置 DFS 参数 -- 5. light_sleep_enable = true，具体如下: - - :: - - esp_pm_config_t pm_config = { - .max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ, - .min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ, - #if CONFIG_FREERTOS_USE_TICKLESS_IDLE - .light_sleep_enable = true - #endif - }; - ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); - -- 6. 配置介绍的其余相关参数 - -推荐配置： - -.. only:: esp32c3 or esp32s3 - - .. list-table:: - :header-rows: 1 - :widths: 30 15 - - * - 配置名称 - - 设置情况 - - * - CONFIG_PM_ENABLE - - ON - - * - CONFIG_FREERTOS_USE_TICKLESS_IDLE - - ON - - * - max_freq_mhz - - 160 - - * - min_freq_mhz - - 40 - - * - RTOS Tick rate (Hz) - - 1000 - - * - light_sleep_enable - - true - - * - Minimum step to enter sleep mode - - 3 - - * - Put light sleep codes in IRAM - - OFF - - * - Put RTOS IDLE codes in IRAM - - OFF - - * - RTC slow clock source - - Internal 150kHz OSC - - * - Disable all GPIO when chip at sleep - - ON - - * - Power down MAC and baseband - - ON - - * - Power down I/D-cache tag memory - - ON - - * - Power down CPU - - ON - - * - Power down flash in light sleep - - OFF - - .. note:: - 上表中不涉及的配置均是默认 - -.. only:: esp32 or esp32s2 - - .. list-table:: - :header-rows: 1 - :widths: 30 15 - - * - 配置名称 - - 设置情况 - - * - CONFIG_PM_ENABLE - - ON - - * - CONFIG_FREERTOS_USE_TICKLESS_IDLE - - ON - - * - max_freq_mhz - - 160 - - * - min_freq_mhz - - 40 - - * - RTOS Tick rate (Hz) - - 1000 - - * - light_sleep_enable - - true - - * - Minimum step to enter sleep mode - - 3 - - * - Put light sleep codes in IRAM - - OFF - - * - Put RTOS IDLE codes in IRAM - - OFF - - * - RTC slow clock source - - Internal 150kHz OSC - - * - Disable all GPIO when chip at sleep - - ON - - .. note:: - 上表中不涉及的配置均是默认 - -.. only:: esp32c2 - - .. list-table:: - :header-rows: 1 - :widths: 30 15 - - * - 配置名称 - - 设置情况 - - * - CONFIG_PM_ENABLE - - ON - - * - CONFIG_FREERTOS_USE_TICKLESS_IDLE - - ON - - * - max_freq_mhz - - 120 - - * - min_freq_mhz - - 40 - - * - RTOS Tick rate (Hz) - - 1000 - - * - light_sleep_enable - - true - - * - Minimum step to enter sleep mode - - 3 - - * - Put light sleep codes in IRAM - - OFF - - * - Put RTOS IDLE codes in IRAM - - OFF - - * - RTC slow clock source - - Internal 150kHz OSC - - * - Disable all GPIO when chip at sleep - - ON - - * - Power down MAC and baseband - - ON - - * - Power down I/D-cache tag memory - - ON - - * - Power down CPU - - ON - - * - Power down flash in light sleep - - OFF - - .. note:: - 上表中不涉及的配置均是默认 - -Deep-sleep 配置 -++++++++++++++++++ - -对 Deep-sleep 模式来说，除了唤醒源相关配置，其余配置意义已经不大。 - -Deep-sleep 有如下可配置选项： - -- RTC Timer wakeup -- EXT0/1 wakeup -- Touchpad wakeup -- ULP wakeup - -.. note:: - 以上仅列出可配置唤醒源，详细介绍请参考:doc:`睡眠模式 <../api-reference/system/sleep_modes>`。 - -配置步骤： - -- 配置唤醒源 -- 调用 API，具体如下:: - - /* Enter deep sleep */ - esp_deep_sleep_start(); - -用户可以通过下列配置选项，让一些特定模块在休眠时保持开启状态： - -- Power up External 40 MHz XTAL - 在一些特殊应用中，部分模块对休眠时的时钟精度及稳定度有很高要求（例如 BT）。这种情况下，可以考虑在休眠过程中打开 External 40 MHz XTAL。 - 打开和关闭代码如下:: - - ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)); - ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_OFF)); - -- Power up Internal 8 MHz OSC - 在一些特殊应用中，部分模块（例如 LEDC）将 Internal 8 MHz OSC 作为时钟源，并且希望在 Light-sleep 休眠过程中也可以正常使用。这种情况下，可以考虑在休眠过程中打开 Internal 8 MHz OSC。 - 打开和关闭代码如下:: - - ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC8M, ESP_PD_OPTION_ON)); - ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC8M, ESP_PD_OPTION_OFF)); - - -Wi-Fi 场景下低功耗模式介绍 -++++++++++++++++++++++++++++++++++ - -上文介绍了纯系统方向下的低功耗模式，但在实际应用中还需结合具体应用场景。本节将结合纯系统下的功耗模式来介绍在 Wi-Fi 场景下的低功耗模式。因为 Wi-Fi 场景的复杂性，本节会会首先介绍 Wi-Fi 省电的基本原理，然后再介绍具体的低功耗模式，同时本节主要针对 station 模式。 - -Wi-Fi 省电的基本原理 -+++++++++++++++++++++ - -首先，在 station 的工作过程中，为在接收发送过程中避免冲突，需要长时间监听信道，能耗较大的 RF 模块会一直处于工作中，浪费电量。为此，Wi-Fi 协议引入省电模式。 - -省电模式的基本原理是通过减少不必要的监听时间来降低耗能。AP 会缓存进入省电模式的 station 的包，同时周期发送包含 TIM 信息的 Beacon 帧，TIM 会指示 AP 缓存的单播包。TIM 中，DTIM 较为特殊，其会缓存广播包，并以 n 个（由 AP 决定）TIM 为周期发送。对 station 来说，TIM 非必听，而 DTIM 为必听。因此，station 可以选择只在每一个 DTIM 帧前醒来打开 Wi-Fi 相关模块（RF 模块），而不必时刻处于监听状态，这样就能有效降低功耗。 - -.. figure:: ../../_static/Low-power-DTIM4.png - :align: center - - DTIM4 省电模式示意图 - -其次，station 从打开到再次关闭 Wi-Fi 相关模块的时间也会影响功耗。除必要的数据传输处理时间外，主要有四项配置会影响时间长短： - - - 时钟准确性导致的 time offset，主要原因是时钟或多或少都会与理想的时间存在偏移，同时偏移的正负不定。 - - 处理 Beacon 漏听后的时间，如漏听后持续监听时间、允许最多丢失 Beacon 数目等，这段时间存不存在以及存在多久都不定，但是可以配置范围。 - - 为了确保能够接受突发数据包而添加的 active 时间，可由配置决定。 - - ILDE 时间是具体某些功耗模式进入条件要求。因此在满足通信需求的情况下，降低工作时间可以改善功耗表现。 - -.. figure:: ../../_static/Low-power-time.png - :align: center - - 芯片工作时间组成图 - -此外，在 station 没有处于 Wi-Fi 接收或发送状态时，影响功耗的因素变成了芯片的其他模块。不同的功耗模式会配置不同的时钟源，或者动态调整一些模块的工作频率如 CPU，同时还会关闭不同数量的功能模块，这将有效降低芯片的功耗。其实也就是纯系统相关的模式，用户可根据需求自己选择合适的配置。 - -如果以时间为横轴，电流大小为纵轴建立坐标轴，那么处在低功耗模式下芯片的理想工作电流图可以简化成下图： - -.. figure:: ../../_static/Low-power-WiFi-base-current.png - :align: center - - 理想情况下 Wi-Fi 场景低功耗模式电流图 - -其中 station 要进行 Wi-Fi 通信时，Wi-Fi 相关模块 (PHY) 开启，电流会显著上升，在工作完成前，电流会一直维持在一个较高的水平。工作完成后，芯片会关闭 Wi-Fi 相关模块，这时电流又会降低到一个较低水平。 - -可以看出影响功耗表现的主要有三点：interval、period 和 base current。 - - - Interval 是 station Wi-Fi 相关模块工作的间隔，既可以由低功耗模式自定义，也可根据 Wi-Fi 协议省电机制（3.1 第一点介绍），由 DTIM 周期决定。可以看出在同等情下，interval 越大，功耗表现会更好，但是响应会更慢，影响通信的及时性。 - - - Period 可以看作每次 station Wi-Fi 工作的时间，这段时间的长度也会影响功耗的表现。period 不是一个固定的时长（3.1 第二点介绍），在保证 Wi-Fi 通信正常的情况下，period 持续时间越短，功耗表现越好。但是减少 period 时间，必然会影响通信的可靠性。 - - - Base current 是 Wi-Fi 相关模块不工作时芯片的电流，影响其大小的因素很多，不同的功耗模式下休眠策略不同。所以，在满足功能的情况下，优化配置降低该电流大小可以提高功耗表现，但同时关闭其余模块会影响相关功能和芯片的唤醒时间。 - -知道了影响功耗的三点因素之后，要想降低功耗应从这三点入手，接下来介绍两种低功耗模式，Modem sleep、Auto Light-sleep。两种模式主要区别就是对三点因素的优化不同。 - - -Modem-sleep Mode -++++++++++++++++++ - -Modem-sleep 模式主要工作原理基于 DTIM 机制，周期性的醒来处理 Wi-Fi 相关工作，又在周期间隔之间进入休眠，关闭 PHY（RF 模块）来降低功耗。同时通过 DTIM 机制，station 可以与 AP 保持 Wi-Fi 连接，数据传输。 - -Modem-sleep 模式会在 Wi-Fi task 结束后自动进入休眠无需调用 API，休眠时仅会关闭 Wi-Fi 相关模块 (PHY)，其余模块均处在正常上电状态。 - -Modem-sleep 模式默认会根据 DTIM 周期或 listen interval（下文介绍）醒来，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源，同时系统主动发包时也可以唤醒。 - -Modem-sleep 是一个开关型的模式，调用 API 开启后一直自动运行，其工作流程十分简单，具体如下图。 - -.. figure:: ../../_static/Low-power-modem-process.png - :align: center - - Modem sleep 工作流程图 - - -根据上文的基本电流图，结合 Modem-sleep 的 工作原理，以 Min Modem（下文介绍）为例可得理想情况下电流变化图。 - -.. figure:: ../../_static/Low-power-modem-current.png - :align: center - - Min Modem-sleep 理想电流图 - -Modem-sleep 一般用于 CPU 持续处于工作状态并需要保持 Wi-Fi 连接的应用场景，例如，使用 {IDF_TARGET_NAME} 本地语音唤醒功能，CPU 需要持续采集和处理音频数据。 - -DFS+Modem sleep -++++++++++++++++++ - -Modem sleep 模式休眠状态中 CPU 仍处在工作状态，而 DFS 机制主要作用于 CPU 和 APB 工作频率来降低功耗，因此 DFS + Modem sleep 可以进一步优化功耗表现，又因为 Wi-Fi task 会申请 ESP_PM_CPU_FREQ_MAX 电源锁来保证 Wi-Fi 任务快速运行，所以 DFS + Modem sleep 产生调频只会发生在 base current 阶段，即 Wi-Fi task 结束后。 - -在 Wi-Fi 场景下，为了介绍的简化，让用户抓住主要的变化，DFS 可以进行一定的状态简化。具体来说，虽然 DFS 主要根据 CPU 和 APB 两把锁的最高需求来调频，但是 Wi-Fi 场景都需要 CPU 的频率最大化来工作，同时 Wi-Fi task 结束后，也可以理想化的认为，没有其余的工作要完成，这样就可以简单认为经过一段时间会释放两把锁进入空闲状态（IDLE 状态），也同时忽略这段时间锁的变化导致的电流变化，简化状态。 - -在 Wi-Fi 场景下，DFS 最终简化为如下流程： - -.. figure:: ../../_static/Low-power-DFS-process.png - :align: center - - Wi-Fi场景 DFS 简化流程图 - -在 Wi-Fi 工作的 active 状态与系统空闲的 IDLE 状态转换，Wi-Fi task 结束后，系统经过一段时间释放了所有锁进入 IDLE 状态，此时 DFS 机制降低频率到设定最低值，忽略了转换状态期间的调频动作，方便理解。 - -简化过后的 DFS+Modem sleep 模式理想状态下的电流大小如下图所示： - -.. figure:: ../../_static/Low-power-DFS-modem-current.png - :align: center - - DFS+Modem sleep 模式理想电流图 - - -Auto Light-sleep+Wi-Fi 场景 -+++++++++++++++++++++++++++++++ - -Auto Light-sleep 模式在 Wi-Fi 场景下是 ESP-IDF 电源管理机制、DTIM 机制和 light-sleep 的结合。开启电源管理是其前置条件，auto 体现在系统进入 IDLE 状态超过设定值后自动进入 light-sleep。同时 auto light sleep 模式同样遵循 DTIM 机制，会自动苏醒，可以与 AP 保持 Wi-Fi 连接。 - -Auto Light-sleep 模式在 Wi-Fi 场景下休眠机制与纯系统下一样，仍然依赖于电源管理机制，进入休眠的条件为系统处于 IDLE 状态的时间超过设定时间，并且系统会提前判断空闲时间是否满足条件，若满足直接休眠。该过程为自动进行。休眠时会自动关闭 RF、8 MHz 振荡器、40 MHz 高速晶振、PLL，门控数字内核时钟，暂停 CPU 工作。 - -Auto Light-sleep 模式在 Wi-Fi 场景下遵循 DTIM 机制，自动在 DTIM 帧到来前苏醒，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源。同时系统主动发包时也可以唤醒。 - -Auto Light-sleep 模式在 Wi-Fi 场景下工作流程较为复杂，但全程都是自动进行，具体如下图所示。 - -.. figure:: ../../_static/Low-power-wifi-auto-light-process.png - :align: center - - Auto Light-sleep 工作流程图 - -Auto Light-sleep 模式在 Wi-Fi 场景下经常与 modem sleep 同时开启，这里给出 modem+auto light-sleep 模式的理想电流图，关键节点均在图上标出。 - -.. figure:: ../../_static/Low-power-wifi-auto-light-current.png - :align: center - - modem+auto light-sleep 模式理想电流图 - -Auto Light-sleep 模式在 Wi-Fi 场景下可用于需要保持 Wi-Fi 连接，可以实时响应 AP 发来数据的场景。并且在未接收到命令时，CPU 可以处于空闲状态。比如 Wi-Fi 开关的应用，大部分时间 CPU 都是空闲的，直到收到控制命令，CPU 才需要进行 GPIO 的操作。 - - -Deep-sleep+Wi-Fi 场景 -+++++++++++++++++++++++++++++++++ - -Deep-sleep 模式在 Wi-Fi 场景下与纯系统下基本相同，详情可以参考 `Deep-sleep`_ 这里不再介绍。 - - -如何配置 Wi-Fi 场景下低功耗模式 -+++++++++++++++++++++++++++++++++++++ - -介绍完 Wi-Fi 场景下低功耗模式后，本节将介绍公共配置选项、每种模式独有的配置选项，以及相应低功耗模式 API 的使用说明，同时给出相应模式推荐的配置（包含纯系统下的低功耗推荐配置）以及该配置的具体表现。 - -公共配置选项： - -- 功耗类： - - - Max Wi-Fi TX power (dBm) - 该参数表示最大 TX 功率，降低该参数会减小发包功耗，但会影响 Wi-Fi 性能，默认设置最大 20。 - -- IRAM 类： - - - Wi-Fi IRAM speed optimization - 如果使能该选项，一些 Wi-Fi 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加，默认开启。 - - - Wi-Fi RX IRAM speed optimization - 如果使能该选项，一些 Wi-Fi RX 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加，默认开启。 - - - Wi-Fi Sleep IRAM speed optimization - 如果使能该选项，一些 Wi-Fi sleep 功能将被移至 IRAM，减少代码运行时间，降低系统功耗，IRAM 使用量将增加，默认关闭。 - -- Wi-Fi 协议类： - - - Minimum active time - 该参数表示 Station 接收完一次数据后需要等待时间。当终端与 AP 进行通信时，AP 发送到终端的数据经常是突发形式的，为确保后续的突发数据能够正常接收到，需要等待一段时间。默认 50。 - - - Maximum keep alive time - 该参数表示周期性的发送 sleep null data 来通告 AP 维持连接的时间。在 DTIM 机制下，若 AP 长时间没有某个 station 的包，可能会断开连接，因此需要 station 需要周期发送 sleep null data 维持连接。默认 10。 - - - Send gratuitous ARP periodically - 如果使能该选项，Station 将周期性的发送 gratuitous ARP 请求更新 AP ARP 缓存表。如无该需求，可以关闭。 - - - Wi-Fi sleep optimize when beacon lost - 如果使能该选项，Station 在检测到已经错过或者丢失 beacon 时，会立即关闭 RF 进入低功耗状态。 - -Modem sleep 配置方法如下: - -- 可配置选项 - - - Min Modem - 该参数表示 station 按照 DTIM 周期工作，在每个 DTIM 前醒来接收 Beacon，这样不会漏掉广播信息，但是 DTIM 周期由 AP 决定，如果 DTIM 周期较短，省电效果会降低。 - - - Max Modem - 该参数表示 station 会自定义一个 listen interval，并以 listen interval 为周期醒来接受 Beacon。这样在 listen interval 较大时会省电，但是容易漏听 DTIM，错过广播数据。 - - -- 配置方法： - - - 调用 API，选择模式参数:: - - typedef enum { - WIFI_PS_NONE, - WIFI_PS_MIN_MODEM, - WIFI_PS_MAX_MODEM, - } wifi_ps_type_t; - esp_err_t esp_wifi_set_ps(wifi_ps_type_t type); - - 若选择 WIFI_PS_MAX_MODEM，还需配置 listen interval，示例如下:: - - #define LISTEN_INTERVAL 3 - wifi_config_t wifi_config = { - .sta = { - .ssid = "SSID", - .password = "Password", - .listen_interval = LISTEN_INTERVAL, - }, - }; - ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); - ESP_ERROR_CHECK(esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_config)); - ESP_ERROR_CHECK(esp_wifi_start()); - -配置推荐： - -这里给出的配置推荐是 Min Modem sleep + DFS 开启的配置 - -.. list-table:: - :header-rows: 1 - :widths: 20 15 - - * - 配置名称 - - 设置情况 - - * - WIFI_PS_MIN_MODEM - - ON - - * - CONFIG_PM_ENABLE - - ON - - * - RTOS Tick rate (Hz) - - 1000 - - * - max_freq_mhz - - 160 - - * - min_freq_mhz - - 40 - - * - light_sleep_enable - - false - -配置表现： - -.. include:: sleep-current/{IDF_TARGET_PATH_NAME}_modem_sleep.inc - -Auto Light-sleep + Wi-Fi 场景配置： - -Auto Light-sleep 在 Wi-Fi 场景下的配置比纯系统下少了唤醒源的配置要求，其余几乎与纯系统下配置一致，因此可配置选项、配置步骤、推荐配置的详细介绍可以参考上文 `Light-sleep`_。同时 Wi-Fi 相关配置保持默认。 - -配置表现： - -该配置表现为 Auto Light-sleep 纯系统推荐配置 + 默认的 Wi-Fi 相关配置在 Wi-Fi 场景的表现。 - -.. include:: sleep-current/{IDF_TARGET_PATH_NAME}_light_sleep.inc - -Deep-sleep + Wi-Fi 场景配置： - -Deep-sleep 模式在 Wi-Fi 场景下的配置与纯系统下配置基本一致，因此可配置选项、配置步骤、推荐配置的详细介绍可以参考上文 `Deep-sleep`_。同时 Wi-Fi 相关配置保持默认。 - -配置表现： - -该配置表现为 Deep-sleep 纯系统推荐配置 + 默认的 Wi-Fi 相关配置在 Wi-Fi 场景的表现。 - -.. only:: esp32 - - 平均电流约 5.0 μA - -.. only:: esp32s2 - - 平均电流约 5.0 μA - -.. only:: esp32s3 - - 平均电流约 6.9 μA - -.. only:: esp32c3 - - 平均电流约 4.8 μA - -.. only:: esp32c2 - - 平均电流约 4.9 μA - - -Wi-Fi 场景如何选择低功耗模式 -++++++++++++++++++++++++++++++++++ - -为方便用户选择合适的低功耗模式，现给出 Wi-Fi 场景下低功耗模式总结表，用户可根据需求选择。 - -.. include:: sleep-current/{IDF_TARGET_PATH_NAME}_summary.inc - -.. note:: - - 上表中所有电流均为平均电流 - - 故障排除 --------------- diff --git a/docs/zh_CN/api-reference/index.rst b/docs/zh_CN/api-reference/index.rst index 51601e0b232..a1bb08070c9 100644 --- a/docs/zh_CN/api-reference/index.rst +++ b/docs/zh_CN/api-reference/index.rst @@ -1,6 +1,7 @@ ******** API 参考 ******** + :link_to_translation:`en:[English]` .. toctree:: diff --git a/docs/zh_CN/api-reference/peripherals/adc_calibration.rst b/docs/zh_CN/api-reference/peripherals/adc_calibration.rst index fe599f24d69..5adca51d1a3 100644 --- a/docs/zh_CN/api-reference/peripherals/adc_calibration.rst +++ b/docs/zh_CN/api-reference/peripherals/adc_calibration.rst @@ -106,6 +106,15 @@ ADC 校准驱动程序会提供 ADC 校准方案。对于驱动程序来说， 设置完上述配置结构体后，请调用 :cpp:func:`adc_cali_create_scheme_curve_fitting` 创建曲线拟合方案句柄。 由于 :c:macro:`ESP_ERR_INVALID_ARG` 或 :c:macro:`ESP_ERR_NO_MEM` 等原因，该函数调用可能失败。函数返回 :c:macro:`ESP_ERR_NOT_SUPPORTED` 时，说明你的开发板没有烧录校准方案所需的 eFuse 位。 + 与 eFuse 相关的 ADC 校准故障 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + 函数 :cpp:func:`adc_cali_create_scheme_curve_fitting` 返回 :c:macro:`ESP_ERR_NOT_SUPPORTED` 时，代表开发板上校准方案所需的 eFuse 位不正确。 + + ESP-IDF 提供的 ADC 校准方案基于芯片上某些与 ADC 校准相关的 eFuse 位的值。乐鑫模组已在出厂时完成烧录，无需用户额外烧录。 + + 如果遇到此类错误，请前往 `技术咨询 `__ 进行反馈。 + 创建曲线拟合方案句柄 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/zh_CN/api-reference/peripherals/dac.rst b/docs/zh_CN/api-reference/peripherals/dac.rst index 7d7da284189..6ef70b68989 100644 --- a/docs/zh_CN/api-reference/peripherals/dac.rst +++ b/docs/zh_CN/api-reference/peripherals/dac.rst @@ -142,5 +142,5 @@ API 参考 .. include-build-file:: inc/dac_oneshot.inc .. include-build-file:: inc/dac_cosine.inc .. include-build-file:: inc/dac_continuous.inc -.. include-build-file:: inc/components/driver/dac/include/driver/dac_types.inc +.. include-build-file:: inc/components/esp_driver_dac/include/driver/dac_types.inc .. include-build-file:: inc/components/hal/include/hal/dac_types.inc diff --git a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst index 40014392bc5..9b49e55d102 100644 --- a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst @@ -98,7 +98,7 @@ GPIO 捆绑包操作 - 清除 GPIO 位：``clr_bit_gpio_out imm[7:0]`` - 注意：立即数宽度取决于专用 GPIO 通道的数量 - .. only:: esp32c2 or esp32c3 or esp32c6 + .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 - 设置 GPIO 位：``csrrsi rd, csr, imm[4:0]`` - 清除 GPIO 位：``csrrci rd, csr, imm[4:0]`` @@ -112,7 +112,7 @@ GPIO 捆绑包操作 有关支持的专用 GPIO 指令的详细信息，请参考 **{IDF_TARGET_NAME} 技术参考手册** > **处理器指令拓展 (PIE)（稍后发布）** [`PDF <{IDF_TARGET_TRM_CN_URL}#pie>`__]. -.. only:: esp32c2 or esp32c3 or esp32c6 +.. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 通过汇编操作专用 GPIO 的示例代码存放在 ESP-IDF 示例项目的 :example:`peripherals/dedicated_gpio` 目录下。示例演示了如何通过汇编操作专用 GPIO 来模拟 UART、I2C 和 SPI 总线。 diff --git a/docs/zh_CN/api-reference/peripherals/ecdsa.rst b/docs/zh_CN/api-reference/peripherals/ecdsa.rst new file mode 100644 index 00000000000..5a65a8a8bff --- /dev/null +++ b/docs/zh_CN/api-reference/peripherals/ecdsa.rst @@ -0,0 +1 @@ +.. include:: ../../../en/api-reference/peripherals/ecdsa.rst diff --git a/docs/zh_CN/api-reference/peripherals/gpio.rst b/docs/zh_CN/api-reference/peripherals/gpio.rst index 0cf85c43c6a..269769ba2c8 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/gpio.rst @@ -21,7 +21,7 @@ GPIO 驱动提供了一个函数 :cpp:func:`gpio_dump_io_configuration` 用来 FuncSel: 1 (GPIO) GPIO Matrix SigIn ID: (simple GPIO input) SleepSelEn: 1 - + IO[18] - Pullup: 0, Pulldown: 0, DriveCap: 2 InputEn: 0, OutputEn: 1, OpenDrain: 0 @@ -34,7 +34,7 @@ GPIO 驱动提供了一个函数 :cpp:func:`gpio_dump_io_configuration` 用来 InputEn: 1, OutputEn: 0, OpenDrain: 0 FuncSel: 0 (IOMUX) SleepSelEn: 1 - + =================IO DUMP End================== 当 IO 管脚是通过 GPIO 交换矩阵连接到内部外设信号，输出信息打印中的外设信号 ID 定义可以在 ``soc/gpio_sig_map.h`` 文件中查看。``**RESERVED**`` 字样则表示此 IO 被用于连接 FLASH 或 PSRAM，因此该引脚不应该被其他任何应用场景所征用并进行重新配置。 @@ -52,7 +52,9 @@ GPIO 驱动提供了一个函数 :cpp:func:`gpio_dump_io_configuration` 用来 .. list:: - 处于 Deep-sleep 模式时 - :SOC_ULP_SUPPORTED and not esp32c6: - :doc:`超低功耗协处理器 (ULP) <../../api-reference/system/ulp>` 运行时 + :SOC_ULP_FSM_SUPPORTED: - :doc:`超低功耗协处理器 (ULP-FSM) <../../api-reference/system/ulp>` 运行时 + :SOC_RISCV_COPROC_SUPPORTED: - :doc:`超低功耗协处理器 (ULP-RISC-V) <../../api-reference/system/ulp-risc-v>` 运行时 + :SOC_LP_CORE_SUPPORTED: - :doc:`超低功耗协处理器 (ULP-LP-Core) <../../api-reference/system/ulp-lp-core>` 运行时 - 使用 ADC/DAC 等模拟功能时 :SOC_LP_PERIPHERALS_SUPPORTED: - 使用低功耗外设时，例如： LP_UART ， LP_I2C 等 diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc index 6864ecf35e9..229365e6870 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc @@ -9,7 +9,7 @@ .. gpio-summary -{IDF_TARGET_NAME} 芯片具有 57 个物理 GPIO 管脚（GPIO0 ~ GPIO56）。 +{IDF_TARGET_NAME} 芯片具有 55 个物理 GPIO 管脚（GPIO0 ~ GPIO54）。 每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。 @@ -299,16 +299,6 @@ - - - * - GPIO55 - - - - - - - - * - GPIO56 - - - - - - - .. note:: - Strapping 管脚：GPIO34, GPIO35、GPIO36、GPIO37 和 GPIO38 是 Strapping 管脚。更多信息请参考 `ESP32-P4 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。 diff --git a/docs/zh_CN/api-reference/peripherals/i2s.rst b/docs/zh_CN/api-reference/peripherals/i2s.rst index 4af4fc9d4a4..236281adb94 100644 --- a/docs/zh_CN/api-reference/peripherals/i2s.rst +++ b/docs/zh_CN/api-reference/peripherals/i2s.rst @@ -297,7 +297,7 @@ I2S 驱动例程请参考 :example:`peripherals/i2s` 目录。以下为每种模 - :c:macro:`I2S_STD_CLK_DEFAULT_CONFIG`。 -请参考 :ref:`i2s-api-reference-i2s_std` 了解 STD API 的相关信息。更多细节请参考 :component_file:`driver/i2s/include/driver/i2s_std.h`。 +请参考 :ref:`i2s-api-reference-i2s_std` 了解 STD API 的相关信息。更多细节请参考 :component_file:`esp_driver_i2s/include/driver/i2s_std.h`。 STD TX 模式 ~~~~~~~~~~~~~ @@ -551,7 +551,7 @@ STD RX 模式 - :c:macro:`I2S_PDM_TX_CLK_DEFAULT_CONFIG` - PDM TX API 的相关信息，可参考 :ref:`i2s-api-reference-i2s_pdm`。更多细节请参阅 :component_file:`driver/i2s/include/driver/i2s_pdm.h`。 + PDM TX API 的相关信息，可参考 :ref:`i2s-api-reference-i2s_pdm`。更多细节请参阅 :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`。 PDM 数据位宽固定为 16 位。如果 ``int16_t`` 写缓冲区中的数据如下： @@ -647,7 +647,7 @@ STD RX 模式 - :c:macro:`I2S_PDM_RX_CLK_DEFAULT_CONFIG` - PDM RX API 的相关信息，可参考 :ref:`i2s-api-reference-i2s_pdm`。更多细节请参阅 :component_file:`driver/i2s/include/driver/i2s_pdm.h`。 + PDM RX API 的相关信息，可参考 :ref:`i2s-api-reference-i2s_pdm`。更多细节请参阅 :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`。 PDM 数据位宽固定为 16 位。如果线路上的数据如下所示。为方便理解，已将线路上的数据格式由 PDM 转为 PCM。 @@ -733,7 +733,7 @@ STD RX 模式 - :c:macro:`I2S_TDM_CLK_DEFAULT_CONFIG` - 有关 TDM API 的信息，请参阅 :ref:`i2s-api-reference-i2s_tdm`。更多细节请参阅 :component_file:`driver/i2s/include/driver/i2s_tdm.h`。 + 有关 TDM API 的信息，请参阅 :ref:`i2s-api-reference-i2s_tdm`。更多细节请参阅 :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`。 .. note:: @@ -1070,5 +1070,5 @@ I2S 驱动 I2S 类型 ^^^^^^^^ -.. include-build-file:: inc/components/driver/i2s/include/driver/i2s_types.inc +.. include-build-file:: inc/components/esp_driver_i2s/include/driver/i2s_types.inc .. include-build-file:: inc/components/hal/include/hal/i2s_types.inc diff --git a/docs/zh_CN/api-reference/peripherals/index.rst b/docs/zh_CN/api-reference/peripherals/index.rst index e6f0399180c..46c5bb1e461 100644 --- a/docs/zh_CN/api-reference/peripherals/index.rst +++ b/docs/zh_CN/api-reference/peripherals/index.rst @@ -12,6 +12,7 @@ :SOC_ANA_CMPR_SUPPORTED: ana_cmpr clk_tree :SOC_DAC_SUPPORTED: dac + :SOC_ECDSA_SUPPORTED: ecdsa :SOC_ETM_SUPPORTED: etm gpio gptimer @@ -34,7 +35,6 @@ spi_flash/index spi_master spi_slave - :esp32: secure_element :SOC_SPI_SUPPORT_SLAVE_HD_VER2: spi_slave_hd :SOC_TEMP_SENSOR_SUPPORTED: temp_sensor :SOC_TOUCH_SENSOR_SUPPORTED: touch_pad diff --git a/docs/zh_CN/api-reference/peripherals/mcpwm.rst b/docs/zh_CN/api-reference/peripherals/mcpwm.rst index 0fc6d89b0c8..536f32631fd 100644 --- a/docs/zh_CN/api-reference/peripherals/mcpwm.rst +++ b/docs/zh_CN/api-reference/peripherals/mcpwm.rst @@ -204,10 +204,11 @@ MCPWM 组有一个专用定时器，用于捕获特定事件发生时的时间 - :cpp:member:`mcpwm_capture_channel_config_t::intr_priority` 设置中断的优先级。如果设置为 ``0``，则会分配一个默认优先级的中断，否则会使用指定的优先级。 - :cpp:member:`mcpwm_capture_channel_config_t::gpio_num` 设置捕获通道使用的 GPIO 编号。 - :cpp:member:`mcpwm_capture_channel_config_t::prescale` 设置输入信号的预分频器。 -- :cpp:member:`mcpwm_capture_channel_config_t::pos_edge` 和 :cpp:member:`mcpwm_capture_channel_config_t::neg_edge` 设置是否在输入信号的上升沿和/或下降沿捕获时间戳。 -- :cpp:member:`mcpwm_capture_channel_config_t::pull_up` 和 :cpp:member:`mcpwm_capture_channel_config_t::pull_down` 设置是否在内部拉高和/或拉低 GPIO。 -- :cpp:member:`mcpwm_capture_channel_config_t::invert_cap_signal` 设置是否取反捕获信号。 -- :cpp:member:`mcpwm_capture_channel_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。 +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::pos_edge` 和 :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::neg_edge` 设置是否在输入信号的上升沿和/或下降沿捕获时间戳。 +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::pull_up` 和 :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::pull_down` 设置是否在内部拉高和/或拉低 GPIO。 +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::invert_cap_signal` 设置是否取反捕获信号。 +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。 +- :cpp:member:`mcpwm_capture_channel_config_t::extra_flags::keep_io_conf_at_exit` 设置是否在删除通道时保留 GPIO 的相关配置。 分配成功后，:cpp:func:`mcpwm_new_capture_channel` 将返回一个指向已分配捕获通道的指针。否则，函数将返回错误代码。具体来说，当捕获定时器中没有空闲捕获通道时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。 @@ -855,6 +856,10 @@ MCPWM 定时器接收到同步信号后，定时器将强制进入一个预定 - :cpp:member:`mcpwm_timer_sync_phase_config_t::count_value` 设置接收同步信号后加载至计数器的值。 - :cpp:member:`mcpwm_timer_sync_phase_config_t::direction` 设置接收同步信号后的计数方向。 +.. note:: + + 当 MCPWM 定时器在 :cpp:enumerator:`MCPWM_TIMER_COUNT_MODE_UP_DOWN` 模式下工作时，需要特别注意。在该模式下，计数器范围 ``[0 -> peak-1]`` 属于 **递增** 阶段， ``[peak -> 1]`` 属于 **递减** 阶段。因此，如果你将 :cpp:member:`mcpwm_timer_sync_phase_config_t::count_value` 设置为零，则可能还需要将 :cpp:member:`mcpwm_timer_sync_phase_config_t::direction` 设置为 :cpp:enumerator:`MCPWM_TIMER_DIRECTION_UP`。否则，计时器将继续维持递减阶段，计数值会下溢至峰值。 + 同理， `MCPWM 捕获定时器和通道`_ 也支持同步。调用 :cpp:func:`mcpwm_capture_timer_set_phase_on_sync`，设置捕获定时器的同步相位。同步相位配置定义在 :cpp:type:`mcpwm_capture_timer_sync_phase_config_t` 结构体中： - :cpp:member:`mcpwm_capture_timer_sync_phase_config_t::sync_src` 设置同步信号源。关于如何创建一个同步源对象，请参见 `MCPWM 同步源`_。具体来说，当此参数设置为 ``NULL`` 时，驱动器将禁用 MCPWM 捕获定时器的同步功能。 @@ -1044,7 +1049,7 @@ API Reference .. include-build-file:: inc/mcpwm_sync.inc .. include-build-file:: inc/mcpwm_cap.inc .. include-build-file:: inc/mcpwm_etm.inc -.. include-build-file:: inc/components/driver/mcpwm/include/driver/mcpwm_types.inc +.. include-build-file:: inc/components/esp_driver_mcpwm/include/driver/mcpwm_types.inc .. include-build-file:: inc/components/hal/include/hal/mcpwm_types.inc diff --git a/docs/zh_CN/api-reference/peripherals/rmt.rst b/docs/zh_CN/api-reference/peripherals/rmt.rst index 2080cf59a15..2a2000edbe4 100644 --- a/docs/zh_CN/api-reference/peripherals/rmt.rst +++ b/docs/zh_CN/api-reference/peripherals/rmt.rst @@ -205,6 +205,10 @@ RMT 发射器可以生成载波信号，并将其调制到消息信号上。载 也可使用参数 ``user_data``，在 :cpp:func:`rmt_tx_register_event_callbacks` 和 :cpp:func:`rmt_rx_register_event_callbacks` 中保存自定义上下文。用户数据将直接传递给每个回调函数。 +.. note:: + + "receive-done" 不等同于 "receive-finished". 这个回调函数也可以在 "partial-receive-done" 时间发生的时候被调用。 + 在回调函数中可以获取驱动程序在 ``edata`` 中填充的特定事件数据。注意，``edata`` 指针仅在回调的持续时间内有效。 有关 TX 完成事件数据的定义，请参阅 :cpp:type:`rmt_tx_done_event_data_t`： @@ -213,8 +217,9 @@ RMT 发射器可以生成载波信号，并将其调制到消息信号上。载 有关 RX 完成事件数据的定义，请参阅 :cpp:type:`rmt_rx_done_event_data_t`： -- :cpp:member:`rmt_rx_done_event_data_t::received_symbols` 指向接收到的 RMT 符号，这些符号存储在 :cpp:func:`rmt_receive` 函数的 ``buffer`` 参数中，在回调函数返回前不应释放此接收缓冲区。 +- :cpp:member:`rmt_rx_done_event_data_t::received_symbols` 指向接收到的 RMT 符号，这些符号存储在 :cpp:func:`rmt_receive` 函数的 ``buffer`` 参数中，在回调函数返回前不应释放此接收缓冲区。如果你还启用了部分接收的功能，则这个用户缓冲区会被用作“二级缓冲区”，其中的内容可以被随后传入的数据覆盖。在这种情况下，如果你想要保存或者稍后处理一些数据，则需要将接收到的数据复制到其他位置。 - :cpp:member:`rmt_rx_done_event_data_t::num_symbols` 表示接收到的 RMT 符号数量，该值不会超过 :cpp:func:`rmt_receive` 函数的 ``buffer_size`` 参数。如果 ``buffer_size`` 不足以容纳所有接收到的 RMT 符号，驱动程序将只保存缓冲区能够容纳的最大数量的符号，并丢弃或忽略多余的符号。 +- :cpp:member:`rmt_rx_done_event_data_t::is_last` 指示收到的数据包是否是当前的接收任务中的最后一个。这个标志在你使能 :cpp:member:`rmt_receive_config_t::extra_flags::en_partial_rx` 部分接收功能时非常有用。 .. _rmt-enable-and-disable-channel: @@ -326,6 +331,7 @@ RMT 是一种特殊的通信外设，无法像 SPI 和 I2C 那样发送原始字 - :cpp:member:`rmt_receive_config_t::signal_range_min_ns` 指定高电平或低电平有效脉冲的最小持续时间。如果脉冲宽度小于指定值，硬件会将其视作干扰信号并忽略。 - :cpp:member:`rmt_receive_config_t::signal_range_max_ns` 指定高电平或低电平有效脉冲的最大持续时间。如果脉冲宽度大于指定值，接收器会将其视作 **停止信号**，并立即生成接收完成事件。 +- 如果传入的数据包很长，无法一次性保存在用户缓冲区中，可以通过将 :cpp:member:`rmt_receive_config_t::extra_flags::en_partial_rx` 设置为 ``true`` 来开启部分接收功能。在这种情况下，当用户缓冲区快满的时候，驱动会多次调用 :cpp:member:`rmt_rx_event_callbacks_t::on_recv_done` 回调函数来通知用户去处理已经收到的数据。你可以检查 :cpp:member::`rmt_rx_done_event_data_t::is_last` 的值来了解当前事务是否已经结束。 根据以上配置调用 :cpp:func:`rmt_receive` 后，RMT 接收器会启动 RX 机制。注意，以上配置均针对特定事务存在，也就是说，要开启新一轮的接收时，需要再次设置 :cpp:type:`rmt_receive_config_t` 选项。接收器会将传入信号以 :cpp:type:`rmt_symbol_word_t` 的格式保存在内部内存块或 DMA 缓冲区中。 @@ -337,7 +343,7 @@ RMT 是一种特殊的通信外设，无法像 SPI 和 I2C 那样发送原始字 由于内存块大小有限，RMT 接收器只能保存长度不超过内存块容量的短帧。硬件会将长帧截断，并由驱动程序报错：``hw buffer too small, received symbols truncated``。 -应在 :cpp:func:`rmt_receive` 函数的 ``buffer`` 参数中提供复制目标。如果由于缓冲区大小不足而导致缓冲区溢出，接收器仍可继续工作，但会丢弃溢出的符号，并报告此错误信息：``user buffer too small, received symbols truncated``。请注意 ``buffer`` 参数的生命周期，确保在接收器完成或停止工作前不会回收缓冲区。 +应在 :cpp:func:`rmt_receive` 函数的 ``buffer`` 参数中提供复制目标。如果由于缓冲区大小不足而导致缓冲区溢出，接收器仍可继续工作，但会丢弃溢出的符号，并报告此错误信息： ``user buffer too small, received symbols truncated``。请注意 ``buffer`` 参数的生命周期，确保在接收器完成或停止工作前不会回收缓冲区。 当接收器完成工作，即接收到持续时间大于 :cpp:member:`rmt_receive_config_t::signal_range_max_ns` 的信号时，驱动程序将停止接收器。如有需要，应再次调用 :cpp:func:`rmt_receive` 重新启动接收器。在 :cpp:member:`rmt_rx_event_callbacks_t::on_recv_done` 的回调中可以获取接收到的数据。要获取更多有关详情，请参阅 :ref:`rmt-register-event-callbacks`。 @@ -573,7 +579,7 @@ Kconfig 选项 - :ref:`CONFIG_RMT_ISR_IRAM_SAFE` 控制默认 ISR 处理程序能否在禁用 cache 的情况下工作。详情请参阅 :ref:`rmt-iram-safe`。 - :ref:`CONFIG_RMT_ENABLE_DEBUG_LOG` 用于启用调试日志输出，启用此选项将增加固件的二进制文件大小。 -- :ref:`CONFIG_RMT_RECV_FUNC_IN_IRAM` 用于控制 RMT 接收函数被链接到系统内存的哪个位置（IRAM 还是 Flash）。详情请参阅 :ref:`rmt-iram-safe`。 +- :ref:`CONFIG_RMT_RECV_FUNC_IN_IRAM` 用于控制 RMT 接收函数被链接到系统存储的哪个位置（IRAM 还是 Flash）。详情请参阅 :ref:`rmt-iram-safe`。 应用示例 -------------------- @@ -603,7 +609,7 @@ API 参考 .. include-build-file:: inc/rmt_rx.inc .. include-build-file:: inc/rmt_common.inc .. include-build-file:: inc/rmt_encoder.inc -.. include-build-file:: inc/components/driver/rmt/include/driver/rmt_types.inc +.. include-build-file:: inc/components/esp_driver_rmt/include/driver/rmt_types.inc .. include-build-file:: inc/components/hal/include/hal/rmt_types.inc diff --git a/docs/zh_CN/api-reference/peripherals/secure_element.rst b/docs/zh_CN/api-reference/peripherals/secure_element.rst deleted file mode 100644 index 2860ccc1706..00000000000 --- a/docs/zh_CN/api-reference/peripherals/secure_element.rst +++ /dev/null @@ -1,28 +0,0 @@ -ESP32-WROOM-32SE（安全元件） -================================= - -:link_to_translation:`en:[English]` - -概述 --------- - -ESP32-WROOM-32SE 模组集成了 Microchip 的 ATECC608A 加密认证芯片。ATECC608A 安全元件可以在硬件中生成并存储 ECC 私钥。通过使用基于 X.509 的双向认证，ECC 私钥可增强设备与物联网云服务连接的安全性。 - -有关如何使用存储在 ATECC608A 中的 ECC 私钥进行 ECDSA 签名和验证，请参阅以下应用示例。 - -应用示例 -------------------- - -请参阅安全元件 ECDSA 签名/验证示例 :example:`peripherals/secure_element/atecc608_ecdsa`。 - -对 ESP32-WROOM-32SE 配置并配网以进行 TLS 连接 -------------------------------------------------------- - -要在 ESP32-WROOM-32SE 上配置 ATECC608A 芯片，并对其进行配网，请参阅 `esp_cryptoauth_utility `_。 - -使用 ESP32-WROOM-32SE 的 ATECC608A 进行 TLS 连接 ------------------------------------------------------- - -通过使用 ESP-TLS，ATECC608A 可实现 TLS 连接。 - -要配置 ESP-TLS 以使用安全元件，请参阅 :doc:`../protocols/esp_tls` 中的 **ESP-TLS 中的 ATECC608A（安全元件）** 一节。 diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst index 3177abff4a5..bdbb9f4d7e8 100644 --- a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst +++ b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst @@ -42,11 +42,11 @@ SPI1 flash 并发约束 同时启用 :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` 和 :ref:`CONFIG_SPIRAM_RODATA` 选项后，不会禁用 cache。 -.. only:: not CONFIG_FREERTOS_UNICORE +.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES 为避免意外读取 flash cache，一个 CPU 在启动 flash 写入或擦除操作时，另一个 CPU 将阻塞。在 flash 操作完成前，会禁用所有在 CPU 上非 IRAM 安全的中断。 -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES 为避免意外读取 flash cache，在 flash 操作完成前，所有 CPU 上，会禁用所有在 CPU 上非 IRAM 安全的中断。 diff --git a/docs/zh_CN/api-reference/peripherals/touch_pad.rst b/docs/zh_CN/api-reference/peripherals/touch_pad.rst index 66abf2f6bd8..832928ac6d9 100644 --- a/docs/zh_CN/api-reference/peripherals/touch_pad.rst +++ b/docs/zh_CN/api-reference/peripherals/touch_pad.rst @@ -16,7 +16,7 @@ 请参考 `触摸传感器应用方案简介 `_，查看触摸传感器设计详情和固件开发指南。 -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 如果想评估触摸传感器的多种应用场景，请查看 `ESP32 触摸功能开发套件 `_。 @@ -125,7 +125,7 @@ 触摸状态测量 ^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 借助以下两个函数从传感器读取原始数据和滤波后的数据： @@ -138,7 +138,7 @@ 使用 :cpp:func:`touch_pad_read_filtered` 之前，需要先调用 `滤波采样`_ 中特定的滤波器函数来初始化并配置该滤波器。 -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 借助以下函数从传感器读取原始数据： @@ -151,7 +151,7 @@ 测量方式 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 触摸传感器会统计固定时间内的充放电次数，其计数结果即为原始数据，可由 :cpp:func:`touch_pad_read_raw_data` 读出。上述固定时间可通过 :cpp:func:`touch_pad_set_measurement_clock_cycles` 设置。完成一次测量后，触摸传感器会在下次测量开始前保持睡眠状态。两次测量之前的间隔时间可由 :cpp:func:`touch_pad_set_measurement_interval` 进行设置。 @@ -159,7 +159,7 @@ 若设置的计数时间太短（即测量持续的时钟周期数太小），则可能导致结果不准确，但是过大的计数时间也会造成功耗上升。另外，若睡眠时间加测量时间的总时间过长，则会造成触摸传感器响应变慢。 -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 触摸传感器会统计固定充放电次数所需的时间（即所需时钟周期数），其结果即为原始数据，可由 :cpp:func:`touch_pad_read_raw_data` 读出。上述固定的充放电次数可通过 :cpp:func:`touch_pad_set_charge_discharge_times` 设置。完成一次测量后，触摸传感器会在下次测量开始前保持睡眠状态。两次测量之前的间隔时间可由 :cpp:func:`touch_pad_set_measurement_interval` 进行设置。 @@ -172,11 +172,11 @@ 触摸传感器设有数个可配置参数，以适应触摸传感器设计特点。例如，如果需要感知较细微的电容变化，则可以缩小触摸传感器充放电的参考电压范围。使用 :cpp:func:`touch_pad_set_voltage` 函数，可以设置电压参考低值和参考高值。 -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 优化测量除了可以识别细微的电容变化之外，还可以降低应用程序功耗，但可能会增加测量噪声干扰。如果得到的动态读数范围结果比较理想，则可以调用 :cpp:func:`touch_pad_set_measurement_clock_cycles` 函数来减少测量时间，从而进一步降低功耗。 -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 优化测量除了可以识别细微的电容变化之外，还可以降低应用程序功耗，但可能会增加测量噪声干扰。如果得到的动态读数范围结果比较理想，则可以调用 :cpp:func:`touch_pad_set_charge_discharge_times` 函数来减少测量时间，从而进一步降低功耗。 @@ -187,17 +187,17 @@ * 电压门限：:cpp:func:`touch_pad_set_voltage` * 速率（斜率）：:cpp:func:`touch_pad_set_cnt_mode` -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 * 单次测量所用的时钟周期：:cpp:func:`touch_pad_set_measurement_clock_cycles` -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 * 单次测量所需充放电次数：:cpp:func:`touch_pad_set_charge_discharge_times` 电压门限（参考低值/参考高值）、速率（斜率）与测量时间的关系如下图所示： -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 .. figure:: ../../../_static/touch_pad-measurement-parameters.jpg :align: center @@ -208,7 +208,7 @@ 上图中的 **Output** 代表触摸传感器读值，即一个测量周期内测得的脉冲计数值。 -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 .. figure:: ../../../_static/touch_pad-measurement-parameters-version2.png :align: center @@ -225,7 +225,7 @@ 滤波采样 ^^^^^^^^^^^^^^^^^^^^^^^^^ -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 如果测量中存在噪声，可以使用提供的 API 函数对采样进行滤波。使用滤波器之前，请先调用 :cpp:func:`touch_pad_filter_start` 启动该滤波器。 @@ -233,7 +233,7 @@ 如需停止滤波器，请调用 :cpp:func:`touch_pad_filter_stop` 函数。如果不再使用该滤波器，请调用 :cpp:func:`touch_pad_filter_delete` 删除此滤波器。 -.. only:: SOC_TOUCH_VERSION_2 +.. only:: esp32s2 or esp32s3 如果测量中存在噪声，可以使用提供的 API 函数对采样进行滤波。{IDF_TARGET_NAME} 的触摸功能提供了两套 API 可实现此功能。 @@ -259,7 +259,7 @@ 确定监测阈值后就可以在初始化时调用 :cpp:func:`touch_pad_config` 设置此阈值，或在运行时调用 :cpp:func:`touch_pad_set_thresh` 设置此阈值。 -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 下一步就是设置如何触发中断。可以设置在阈值以下或以上触发中断，具体触发模式由函数 :cpp:func:`touch_pad_set_trigger_mode` 设置。 @@ -270,13 +270,13 @@ 中断配置完成后，可以调用 :cpp:func:`touch_pad_get_status` 查看中断信号来自哪个触摸传感器，也可以调用 :cpp:func:`touch_pad_clear_status` 清除触摸传感器状态信息。 -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 .. note:: 触摸监测中的中断信号基于原始/未经滤波的采样（对比设置的阈值），并在硬件中实现。启用软件滤波 API（请参考 :ref:`touch_pad-api-filtering-of-measurements`）并不会影响这一过程。 -.. only:: SOC_TOUCH_VERSION_1 +.. only:: esp32 从睡眠模式唤醒 ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/peripherals/usb_host.rst b/docs/zh_CN/api-reference/peripherals/usb_host.rst index 1f0042a4f50..3371b4c7aa6 100644 --- a/docs/zh_CN/api-reference/peripherals/usb_host.rst +++ b/docs/zh_CN/api-reference/peripherals/usb_host.rst @@ -390,6 +390,46 @@ UVC * USB 视频设备 Class 的主机 Class 驱动程序作为托管组件通过 `ESP-IDF 组件注册器 `__ 分发。 * 示例 :example:`peripherals/usb/host/uvc` 展示了如何使用 UVC 主机驱动程序接收来自 USB 摄像头的视频流，并可选择将该流通过 Wi-Fi 转发。 +.. ---------------------------------------------- USB Host Menuconfig -------------------------------------------------- + +主机栈配置 +---------- + +非兼容设备支持 +^^^^^^^^^^^^^^ + +为了支持某些非兼容或具有特定行为的 USB 设备，可以对 USB 主机栈进行配置。 + +USB 设备可能是热插拔的，因此必须配置电源开关和设备连接之间的延迟，以及设备内部电源稳定后的延迟。 + +枚举配置 +"""""""" + +在枚举已连接 USB 设备的过程中，需要给一些事件配置合适的间隔时间以确保设备正常运行。 + +.. figure:: ../../../_static/usb_host/poweron-timings.png + :align: center + :alt: USB 根集线器上电和连接事件时序 + + USB 根集线器上电和连接事件时序 + +上图展示了与连接设备时开启端口电源和热插拔设备相关的所有间隔时间。 + +* 端口复位或恢复运行后，USB 系统软件应提供 10 毫秒的恢复时间，此后连接到端口的设备才会响应数据传输。 +* 恢复时间结束后，如果设备收到 ``SetAddress()`` 请求，设备必须能够完成对该请求的处理，并能在 50 毫秒内成功完成请求的状态 (Status) 阶段。 +* 状态阶段结束后，设备允许有 2 毫秒的 ``SetAddress()`` 恢复时间。 + +.. note:: + + 有关连接事件时序的更多信息，请参阅 `通用串行总线 2.0 规范 `_ > 第 7.1.7.3 章 *连接和断开信令*。 + +可通过 Menuconfig 选项设置 USB 主机栈的可配置参数。 + +* :ref:`CONFIG_USB_HOST_DEBOUNCE_DELAY_MS` 用于配置防抖延迟。 +* :ref:`CONFIG_USB_HOST_RESET_HOLD_MS` 用于配置重置保持时间。 +* :ref:`CONFIG_USB_HOST_RESET_RECOVERY_MS` 用于配置重置恢复时间。 +* :ref:`CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS` 用于配置 ``SetAddress()`` 恢复时间。 + .. -------------------------------------------------- API Reference ---------------------------------------------------- API 参考 diff --git a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst index 92beed47d42..4fa8fa85d63 100644 --- a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst @@ -76,6 +76,11 @@ ESP x509 证书包 API 提供了一种简便的方法，帮助你安装自定义 证书包嵌入到应用程序中，通过 OTA 更新与应用程序一起更新。如果想使用比目前 ESP-IDF 中的证书包更新的包，则可按照 :ref:`updating_bundle` 中的说明从 Mozilla 下载证书列表。 +定期同步 +------------- + +证书包会与 Mozilla 的 NSS 根证书商店定期同步。在 ESP-IDF 的次要版本或补丁版本中，为了保证兼容性，会将上游证书包中已弃用的证书添加到弃用列表。如有需要，可以通过 :ref:`CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEPRECATED_LIST` 将弃用证书加入默认证书包。这些弃用证书将在下一个 ESP-IDF 主要版本中移除。 + 应用示例 --------- diff --git a/docs/zh_CN/api-reference/protocols/esp_http_client.rst b/docs/zh_CN/api-reference/protocols/esp_http_client.rst index ecd32f1d6f1..21ebf032d61 100644 --- a/docs/zh_CN/api-reference/protocols/esp_http_client.rst +++ b/docs/zh_CN/api-reference/protocols/esp_http_client.rst @@ -138,6 +138,20 @@ ESP HTTP 客户端诊断信息 在无法接收到 :cpp:enumerator:`HTTP_EVENT_DISCONNECTED ` 之前，与事件数据一起接收到的 :cpp:type:`esp_http_client_handle_t` 将始终有效。这个句柄主要是为了区分不同的客户端连接，无法用于其他目的，因为它可能会随着客户端连接状态的变化而改变。 +TLS 协议版本 +-------------------- + +可在 :cpp:type:`esp_http_client_config_t` 中设置用于底层 TLS 连接的 TLS 协议版本。了解更多信息，请参考 :doc:`/api-reference/protocols/esp_tls` 中的 **TLS 协议版本** 章节。 + +HTTP 客户端的 TLS 协议版本可按如下方式配置： + + .. code-block:: c + + #include "esp_http_client.h" + esp_http_client_config_t config = { + .tls_version = ESP_HTTP_CLIENT_TLS_VER_TLS_1_2, + }; + API 参考 --------- diff --git a/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst b/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst index 1a4dabc94de..ed676f12c0c 100644 --- a/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst +++ b/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst @@ -14,21 +14,21 @@ ESP SPI 从机 HD（半双工）模式协议 乐鑫芯片的 SPI 从机功能支持概况 --------------------------------- -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| SPI 从机 HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| Tohost intr | | N | N | N | N | N | N | -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| Frhost intr | | 2 * | 2 * | 2 * | 2 * | 2 * | 2 * | -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| TX DMA | | Y | Y | Y | Y | Y | Y | -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| RX DMA | | Y | Y | Y | Y | Y | Y | -+-------------+-------+----------+----------+----------+----------+----------+----------+ -| 共享寄存器 | | 72 | 64 | 64 | 64 | 64 | 64 | -+-------------+-------+----------+----------+----------+----------+----------+----------+ ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| SPI 从机 HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| Tohost intr | | N | N | N | N | N | N | N | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| Frhost intr | | 2 * | 2 * | 2 * | 2 * | 2 * | 2 * | 2 \* | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| TX DMA | | Y | Y | Y | Y | Y | Y | Y | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| RX DMA | | Y | Y | Y | Y | Y | Y | Y | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ +| 共享寄存器 | | 72 | 64 | 64 | 64 | 64 | 64 | 64 | ++-------------+-------+----------+----------+----------+----------+----------+----------+----------+ 概述 ---- @@ -43,9 +43,17 @@ ESP SPI 从机 HD（半双工）模式协议 对于某些命令（如 WRBUF、RDBUF），此阶段指定要写入/读取的共享寄存器地址。对于其他包括此阶段的命令，这没有实际意义，但仍必须存在于事务中。 -- Dummy 阶段：8 位，浮动，可选 +.. only:: esp32s2 - 此阶段是主机和从机在总线上的周转时间，并为从机向主机发送数据提供了充分的准备时间。 + - Dummy 阶段：8 位 (1线模式) 或 4 位 (2/4线模式)，浮动，可选 + + 此阶段是主机和从机在总线上的周转时间，并为从机向主机发送数据提供了充分的准备时间。 + +.. only:: not esp32s2 + + - Dummy 阶段：8 位，浮动，可选 + + 此阶段是主机和从机在总线上的周转时间，并为从机向主机发送数据提供了充分的准备时间。 - 数据阶段：长度可变，方向由命令确定。 @@ -59,7 +67,7 @@ ESP SPI 从机 HD（半双工）模式协议 在某些 IO 模式下，可以使用更多数据线来发送数据。因此，与 1 位模式相比，发送相同数据量所需的 SPI 时钟周期更少。例如，在 QIO 模式下，地址和数据（IN 和 OUT）应发送到全部 4 条数据线上（MOSI、MISO、WP 和 HD）。下表展示了 ESP32-S2 SPI 从机支持的模式，以及相应模式下使用的数据线数量。 +-------+----------+----------+------------+----------+ -| Mode | 命令线数 | 地址线数 | dummy 次数 | 数据线数 | +| Mode | 命令线数 | 地址线数 | dummy 线数 | 数据线数 | +-------+----------+----------+------------+----------+ | 1-bit | 1 | 1 | 1 | 1 | +-------+----------+----------+------------+----------+ diff --git a/docs/zh_CN/api-reference/protocols/esp_tls.rst b/docs/zh_CN/api-reference/protocols/esp_tls.rst index 369882c7f81..534c8b79241 100644 --- a/docs/zh_CN/api-reference/protocols/esp_tls.rst +++ b/docs/zh_CN/api-reference/protocols/esp_tls.rst @@ -143,11 +143,11 @@ MbedTLS 与 WolfSSL 对比 ESP-TLS 中的 ATECC608A（安全元件） -------------------------------------------------- - ESP-TLS 支持在 ESP32-WROOM-32SE 上使用 ATECC608A 加密芯片，但必须将 MbedTLS 作为 ESP-TLS 的底层 SSL/TLS 协议栈。未经手动更改，ESP-TLS 默认以 MbedTLS 为其底层 TLS/SSL 协议栈。 + ESP-TLS 支持在 ESP32 系列芯片上使用 ATECC608A 加密芯片，但必须将 MbedTLS 作为 ESP-TLS 的底层 SSL/TLS 协议栈。未经手动更改，ESP-TLS 默认以 MbedTLS 为其底层 TLS/SSL 协议栈。 .. note:: - 在 ESP32-WROOM-32SE 上的 ATECC608A 芯片必须预先配置，详情请参阅 `esp_cryptoauth_utility `_。 + 在 ESP32 上的 ATECC608A 芯片必须预先配置，详情请参阅 `esp_cryptoauth_utility `_。 要启用安全元件支持，并将其应用于工程 TLS 连接，请遵循以下步骤： @@ -203,6 +203,8 @@ MbedTLS 与 WolfSSL 对比 .. only:: SOC_ECDSA_SUPPORTED + .. _ecdsa-peri-with-esp-tls: + 在 ESP-TLS 中使用 ECDSA 外设 ----------------------------- @@ -244,6 +246,26 @@ ESP-TLS 不会检查 ``ciphersuites_list`` 的有效性，因此需调用 :cpp:f 此功能仅在 MbedTLS 协议栈中有效。 +TLS 协议版本 +-------------------- + +ESP-TLS 能够为 TLS 连接设置相应的 TLS 协议版本，指定版本将用于建立专用 TLS 连接。也就是说，在运行时不同的 TLS 连接可以配置到 TLS 1.2、TLS 1.3 等不同协议版本。 + +.. note:: + + 目前，仅在 MbedTLS 作为 ESP-TLS 的底层 SSL/TLS 协议栈时支持此功能。 + +要在 ESP-TLS 中设置 TLS 协议版本，请设置 :cpp:member:`esp_tls_cfg_t::tls_version`，从 :cpp:type:`esp_tls_proto_ver_t` 中选择所需版本。如未指定协议版本字段，将默认根据服务器要求建立 TLS 连接。 + +ESP-TLS 连接的协议版本可按如下方式配置： + + .. code-block:: c + + #include "esp_tls.h" + esp_tls_cfg_t cfg = { + .tls_version = ESP_TLS_VER_TLS_1_2, + }; + API 参考 ------------- diff --git a/docs/zh_CN/api-reference/protocols/mqtt.rst b/docs/zh_CN/api-reference/protocols/mqtt.rst index fa0a47bf6d8..9365dfe850a 100644 --- a/docs/zh_CN/api-reference/protocols/mqtt.rst +++ b/docs/zh_CN/api-reference/protocols/mqtt.rst @@ -145,7 +145,7 @@ ESP-MQTT 库将始终重新传输未确认的 QoS 1 和 2 发布消息，以避 * :cpp:member:`password `：使用密码 * * :cpp:member:`certificate ` 和 :cpp:member:`key `：进行双向 TLS 身份验证，PEM 或 DER 格式均可 - * :cpp:member:`use_secure_element `：使用 ESP32-WROOM-32SE 中的安全元素 + * :cpp:member:`use_secure_element `：使用 ESP32 中的安全元素 (ATECC608A) * :cpp:member:`ds_data `：使用某些乐鑫设备的数字签名外设 会话 diff --git a/docs/zh_CN/api-reference/provisioning/protocomm.rst b/docs/zh_CN/api-reference/provisioning/protocomm.rst index 4293496fa53..888990b1b8f 100644 --- a/docs/zh_CN/api-reference/provisioning/protocomm.rst +++ b/docs/zh_CN/api-reference/provisioning/protocomm.rst @@ -28,8 +28,11 @@ Protocomm 为以下各种传输提供框架： :SOC_WIFI_SUPPORTED: - Wi-Fi (SoftAP + HTTPD) - 控制台：使用该传输方案时，设备端会自动调用处理程序。相关代码片段，请参见下文传输示例。 +请注意，对于 ``protocomm_security1`` 和 ``protocomm_security2``，客户端仍需要执行双向握手来建立会话。 -请注意，对于 ``protocomm_security1`` 和 ``protocomm_security2``，客户端仍需要执行双向握手来建立会话。关于安全握手逻辑的详情，请参阅 :doc:`provisioning`。 +.. only:: SOC_WIFI_SUPPORTED + + 关于安全握手逻辑的详情，请参阅 :doc:`provisioning`。 .. _enabling-protocomm-security-version: @@ -40,10 +43,10 @@ Protocomm 为以下各种传输提供框架： * 支持 ``protocomm_security0``，该版本无安全功能：:ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0`，该选项默认启用。 * 支持 ``protocomm_security1``，使用 Curve25519 密钥交换和 AES-CTR 加密/解密：:ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1`，该选项默认启用。 - * 支持 ``protocomm_security2``，使用基于 SRP6a 的密钥交换和 AES-GCM 加密/解密：:ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2`。 + * 支持 ``protocomm_security2``，使用基于 SRP6a 的密钥交换和 AES-GCM 加密/解密：:ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2`。 + +.. note:: -.. note:: - 启用多个安全版本后可以动态控制安全版本，但也会增加固件大小。 .. only:: SOC_WIFI_SUPPORTED @@ -241,7 +244,7 @@ Protocomm 为以下各种传输提供框架： 使用 Security 0 的低功耗蓝牙传输方案示例 ------------------------------------------- - + 示例用法请参阅 :component_file:`wifi_provisioning/src/scheme_ble.c`。 .. highlight:: c @@ -299,5 +302,7 @@ API 参考 .. include-build-file:: inc/protocomm_security.inc .. include-build-file:: inc/protocomm_security0.inc .. include-build-file:: inc/protocomm_security1.inc +.. include-build-file:: inc/protocomm_security2.inc +.. include-build-file:: inc/esp_srp.inc .. include-build-file:: inc/protocomm_httpd.inc .. include-build-file:: inc/protocomm_ble.inc diff --git a/docs/zh_CN/api-reference/provisioning/provisioning.rst b/docs/zh_CN/api-reference/provisioning/provisioning.rst index 9c07884268f..d404fa84416 100644 --- a/docs/zh_CN/api-reference/provisioning/provisioning.rst +++ b/docs/zh_CN/api-reference/provisioning/provisioning.rst @@ -1,5 +1,3 @@ -:orphan: - 统一配网 ^^^^^^^^^^^^^^^^^^^^ @@ -18,11 +16,11 @@ ESP-IDF 支持统一配网，提供可扩展的机制，支持开发者使用不 该协议可以作为 Wi-Fi（SoftAP + HTTP 服务器）或低功耗蓝牙上的传输方式，并且可轻松应用于任何支持请求—响应行为的传输方式。 -3. **安全方案灵活** +3. **安全方案灵活** 配网过程中，各使用场景可能需要不同安全方案来保护传输的数据。部分应用程序可能使用 WPA2 保护的 SoftAP 或具有“即插即用 (just-works)”安全方案的低功耗蓝牙。亦或者，应用程序可能认为传输不安全，需要应用层的安全方案。统一配网框架支持应用程序根据需要选择合适的安全方案。 -4. **数据格式紧凑** +4. **数据格式紧凑** 该协议使用 `Google Protobufs `_ 作为会话设置和 Wi-Fi 配网的数据格式。该方案提供紧凑的数据格式，并可以使用不同编程语言进行数据解析。请注意，该配网的应用数据格式并不只局限于 Protobufs，开发者可以自行选择自己想用的数据格式。 @@ -97,7 +95,7 @@ ESP-IDF 支持统一配网，提供可扩展的机制，支持开发者使用不 有两种安全方案层级可供选择，开发者可以根据需求选择其中一种或结合使用。 -1. **传输层安全** +1. **传输层安全** 对于 SoftAP 配网，可以使用 WPA2 保护的安全方案，则每个设备都会有唯一密码，且该密码也可以用作 PoP。对于低功耗蓝牙配网，在考量其支持的安全层级后，可以使用“即插即用”方案保护传输层的安全。 @@ -152,8 +150,8 @@ ESP-IDF 支持统一配网，提供可扩展的机制，支持开发者使用不 基于 SRP6a 的共享密钥派生和 AES256-GCM 模式的数据加密。 -.. note:: - +.. note:: + 要启用相应安全方案，需要设置项目配置菜单，更多详情请参考 :ref:`enabling-protocomm-security-version`。 Security 1 方案 @@ -233,8 +231,8 @@ Security 2 方案基于 Secure Remote Password (SRP6a) 协议，详情请参阅 验证器 v = g^x，其中 x = H(s | I | p)"]; DEVICE -> DEVICE [label = "生成密钥对", leftnote = "b (dev_privkey) = 256 位随机值 B(dev_pubkey) = k*v + g^b，其中 k = H(N, g)"]; - DEVICE -> DEVICE [label = "共享密钥", leftnote = "共享密钥 K = H(S)，其中 - S = (A * v^u) ^ b + DEVICE -> DEVICE [label = "共享密钥", leftnote = "共享密钥 K = H(S)，其中 + S = (A * v^u) ^ b u = H(A, B)"]; DEVICE -> CLIENT [label = "SessionResp0(dev_pubkey B, dev_rand)"]; CLIENT -> CLIENT [label = "共享密钥", rightnote = "shared_key(K) = H(S)，其中 @@ -243,7 +241,7 @@ Security 2 方案基于 Secure Remote Password (SRP6a) 协议，详情请参阅 k = H(N, g), v = g^x, x = H(s | I | p). - + "]; CLIENT -> CLIENT [label = "验证令牌", rightnote = "client_proof M = H[H(N) XOR H(g) | H(I) | s | A | B | K]"]; CLIENT -> DEVICE [label = "SessionCmd1(client_proof M1)"]; diff --git a/docs/zh_CN/api-reference/provisioning/wifi_provisioning.rst b/docs/zh_CN/api-reference/provisioning/wifi_provisioning.rst index d8855e05284..70406e532f7 100644 --- a/docs/zh_CN/api-reference/provisioning/wifi_provisioning.rst +++ b/docs/zh_CN/api-reference/provisioning/wifi_provisioning.rst @@ -1,5 +1,3 @@ -:orphan: - Wi-Fi 配网 ==================== @@ -121,7 +119,7 @@ Wi-Fi 配网 此外，由于管理器内部使用了 ``protocomm``，可以选择其提供的任一安全功能： - * Security 1 是安全通信，该安全通信需要先握手，其中涉及 X25519 密钥交换和使用所有权证明 ``pop`` 完成身份验证，随后使用 AES-CTR 加密或解密后续消息。 + * Security 1 是安全通信，该安全通信需要先握手，其中涉及 X25519 密钥交换和使用所有权证明 ``pop`` 完成身份验证，随后使用 AES-CTR 加密或解密后续消息。 * Security 0 是纯文本通信，会直接忽略 ``pop``。 关于安全功能的更多详情，请参阅 :doc:`provisioning`。 diff --git a/docs/zh_CN/api-reference/storage/fatfs.rst b/docs/zh_CN/api-reference/storage/fatfs.rst index c16d8e65181..aa13b2dadf7 100644 --- a/docs/zh_CN/api-reference/storage/fatfs.rst +++ b/docs/zh_CN/api-reference/storage/fatfs.rst @@ -19,32 +19,32 @@ FatFs 与 VFS 配合使用 多数应用程序在使用 ``esp_vfs_fat_`` 函数时，采用如下步骤： -1. 调用 :cpp:func:`esp_vfs_fat_register`，指定： +#. 调用 :cpp:func:`esp_vfs_fat_register`，指定： - 挂载文件系统的路径前缀（例如，``"/sdcard"`` 或 ``"/spiflash"``） - FatFs 驱动编号 - 一个用于接收指向 ``FATFS`` 结构指针的变量 -2. 调用 :cpp:func:`ff_diskio_register`，为步骤 1 中的驱动编号注册磁盘 I/O 驱动； +#. 调用 :cpp:func:`ff_diskio_register`，为步骤 1 中的驱动编号注册磁盘 I/O 驱动； -3. 调用 FatFs 函数 :cpp:func:`f_mount`，随后调用 :cpp:func:`f_fdisk` 或 :cpp:func:`f_mkfs`，并使用与传递到 :cpp:func:`esp_vfs_fat_register` 相同的驱动编号挂载文件系统。请参考 `FatFs 文档 `_，查看更多信息； +#. 如需使用与传递到 :cpp:func:`esp_vfs_fat_register` 相同的驱动编号挂载文件系统，可调用 FatFs 函数 :cpp:func:`f_mount`。如果目标逻辑驱动上不存在该文件系统，:cpp:func:`f_mount` 将调用失败并报告 ``FR_NO_FILESYSTEM`` 错误。此时，应首先调用 :cpp:func:`f_mkfs`，在驱动上创建新的 FatFS 结构体，然后重新调用 :cpp:func:`f_mount`。注意，应在上述步骤之前调用 :cpp:func:`f_fdisk` 对 SD 卡进行分区。请参考 `FatFs 文档 `_，查看更多信息； -4. 调用 C 标准库和 POSIX API 对路径中带有步骤 1 中所述前缀的文件（例如，``"/sdcard/hello.txt"``）执行打开、读取、写入、擦除、复制等操作。文件系统默认使用 `8.3 文件名 `_ 格式 (SFN)。如需使用长文件名 (LFN)，启用 :ref:`CONFIG_FATFS_LONG_FILENAMES` 选项。请参考 `here `_，查看更多信息； +#. 调用 C 标准库和 POSIX API 对路径中带有步骤 1 中所述前缀的文件（例如，``"/sdcard/hello.txt"``）执行打开、读取、写入、擦除、复制等操作。文件系统默认使用 `8.3 文件名 `_ 格式 (SFN)。如需使用长文件名 (LFN)，启用 :ref:`CONFIG_FATFS_LONG_FILENAMES` 选项。请参考 `FatFs 文件系统 `_，查看更多信息； -5. 可以启用 :ref:`CONFIG_FATFS_USE_FASTSEEK` 选项，可以使用 POSIX lseek 实现快速执行。快速查找不适用于编辑模式下的文件，所以，使用快速查找时，应在只读模式下打开（或者关闭然后重新打开）文件； +#. 可以直接调用 FatFs 库函数，但需要使用没有 VFS 前缀的路径，如 ``"/hello.txt"``； -6. 可以启用 :ref:`CONFIG_FATFS_IMMEDIATE_FSYNC` 选项，在每次调用 :cpp:func:`vfs_fat_write`、:cpp:func:`vfs_fat_pwrite`、:cpp:func:`vfs_fat_link`、:cpp:func:`vfs_fat_truncate` 和 :cpp:func:`vfs_fat_ftruncate` 函数之后，自动调用 :cpp:func:`f_sync` 以同步最近的文件改动。该功能可提高文件系统中文件的一致性和文件大小报告的准确性，但是由于需要频繁进行磁盘操作，性能将会受到影响； +#. 关闭所有打开的文件； -7. 可以直接调用 FatFs 库函数，但需要使用没有 VFS 前缀的路径，如 ``"/hello.txt"``； +#. 调用 FatFs 函数 :cpp:func:`f_mount` 并使用 NULL ``FATFS*`` 参数，为与上述编号相同的驱动卸载文件系统； -8. 关闭所有打开的文件； +#. 调用 FatFs 函数 :cpp:func:`ff_diskio_register` 并使用 NULL ``ff_diskio_impl_t*`` 参数和相同的驱动编号，来释放注册的磁盘 I/O 驱动； -9. 调用 FatFs 函数 :cpp:func:`f_mount` 并使用 NULL ``FATFS*`` 参数，为与上述编号相同的驱动卸载文件系统； +#. 调用 :cpp:func:`esp_vfs_fat_unregister_path` 并使用文件系统挂载的路径将 FatFs 从 VFS 中移除，并释放步骤 1 中分配的 ``FATFS`` 结构。 -10. 调用 FatFs 函数 :cpp:func:`ff_diskio_register` 并使用 NULL ``ff_diskio_impl_t*`` 参数和相同的驱动编号，来释放注册的磁盘 I/O 驱动； +便捷函数 :cpp:func:`esp_vfs_fat_sdmmc_mount`、:cpp:func:`esp_vfs_fat_sdspi_mount` 和 :cpp:func:`esp_vfs_fat_sdcard_unmount` 对上述步骤进行了封装，并加入了对 SD 卡初始化的处理。我们将在下一章节详细介绍以上函数。 -11. 调用 :cpp:func:`esp_vfs_fat_unregister_path` 并使用文件系统挂载的路径将 FatFs 从 VFS 中移除，并释放步骤 1 中分配的 ``FATFS`` 结构。 +.. note:: -便捷函数 :cpp:func:`esp_vfs_fat_sdmmc_mount`、:cpp:func:`esp_vfs_fat_sdspi_mount` 和 :cpp:func:`esp_vfs_fat_sdcard_unmount` 对上述步骤进行了封装，并加入了对 SD 卡初始化的处理。我们将在下一章节详细介绍以上函数。 + FAT 文件系统不支持硬链接，因此调用 :cpp:func:`link` 后会复制文件内容（仅适用于 FatFs 卷上的文件）。 FatFs 与 VFS 和 SD 卡配合使用 @@ -60,6 +60,15 @@ FatFs 与 VFS 配合使用（只读模式下） 头文件 :component_file:`fatfs/vfs/esp_vfs_fat.h` 也定义了两个便捷函数 :cpp:func:`esp_vfs_fat_spiflash_mount_ro` 和 :cpp:func:`esp_vfs_fat_spiflash_unmount_ro`。上述两个函数分别对 FAT 只读分区执行步骤 1-3 和步骤 7-9。有些数据分区仅在工厂配置时写入一次，之后在整个硬件生命周期内都不会再有任何改动。利用上述两个函数处理这种数据分区非常方便。 +配置选项 +-------- + +FatFs 组件有以下配置选项： + +* :ref:`CONFIG_FATFS_USE_FASTSEEK` - 如果启用该选项，POSIX :cpp:func:`lseek` 函数将以更快的速度执行。快速查找不适用于编辑模式下的文件，所以，使用快速查找时，应在只读模式下打开（或者关闭然后重新打开）文件。 +* :ref:`CONFIG_FATFS_IMMEDIATE_FSYNC` - 如果启用该选项，FatFs 将在每次调用 :cpp:func:`write`、:cpp:func:`pwrite`、:cpp:func:`link`、:cpp:func:`truncate` 和 :cpp:func:`ftruncate` 函数后，自动调用 :cpp:func:`f_sync` 以同步最近的文件改动。该功能可提高文件系统中文件的一致性和文件大小报告的准确性，但由于需要频繁进行磁盘操作，性能将会受到影响。 +* :ref:`CONFIG_FATFS_LINK_LOCK` - 如果启用该选项，可保证 API 的线程安全，但如果应用程序需要快速频繁地进行小文件操作（例如将日志记录到文件），则可能有必要禁用该选项。请注意，如果禁用该选项，调用 :cpp:func:`link` 后的复制操作将是非原子的，此时如果在不同任务中对同一卷上的大文件调用 :cpp:func:`link`，则无法确保线程安全。 + FatFs 磁盘 I/O 层 ------------------- @@ -109,13 +118,13 @@ FatFs 分区生成器 该函数的参数如下： -1. partition - 分区的名称，需要在分区表中定义（如 :example_file:`storage/fatfsgen/partitions_example.csv`）。 +#. partition - 分区的名称，需要在分区表中定义（如 :example_file:`storage/fatfsgen/partitions_example.csv`）。 -2. base_dir - 目录名称，该目录会被编码为 FatFs 分区，也可以选择将其被烧录进设备。但注意必须在分区表中指定合适的分区大小。 +#. base_dir - 目录名称，该目录会被编码为 FatFs 分区，也可以选择将其被烧录进设备。但注意必须在分区表中指定合适的分区大小。 -3. ``FLASH_IN_PROJECT`` 标志 - 可选参数，用户可以通过指定 ``FLASH_IN_PROJECT``，选择在执行 ``idf.py flash -p `` 时让分区镜像自动与应用程序二进制文件、分区表等一同烧录进设备。 +#. ``FLASH_IN_PROJECT`` 标志 - 可选参数，用户可以通过指定 ``FLASH_IN_PROJECT``，选择在执行 ``idf.py flash -p `` 时让分区镜像自动与应用程序二进制文件、分区表等一同烧录进设备。 -4. ``PRESERVE_TIME`` 标志 - 可选参数，用户可强制让目标镜像保留源文件夹的时间戳。如果不保留，每个目标镜像的时间戳都将设置为 FATFS 默认初始时间（1980 年 1 月 1 日）。 +#. ``PRESERVE_TIME`` 标志 - 可选参数，用户可强制让目标镜像保留源文件夹的时间戳。如果不保留，每个目标镜像的时间戳都将设置为 FATFS 默认初始时间（1980 年 1 月 1 日）。 例如:: @@ -136,8 +145,9 @@ FatFs 分区分析器 可以使用:: - ./fatfsparse.py [-h] [--wl-layer {detect,enabled,disabled}] fatfs_image.img + ./fatfsparse.py [-h] [--wl-layer {detect,enabled,disabled}] [--verbose] fatfs_image.img +生成文件夹结构之前，参数 --verbose 将根据 FatFs 镜像的引导扇区在终端打印详细信息。 高级 API 参考 ------------------------ diff --git a/docs/zh_CN/api-reference/storage/nvs_encryption.rst b/docs/zh_CN/api-reference/storage/nvs_encryption.rst index 589dfb143ec..a5fb7008451 100644 --- a/docs/zh_CN/api-reference/storage/nvs_encryption.rst +++ b/docs/zh_CN/api-reference/storage/nvs_encryption.rst @@ -20,7 +20,13 @@ NVS 加密：基于 flash 加密的方案 在这个方案中，NVS 加密所需的密钥存储在另一个分区中，该分区用 :doc:`../../security/flash-encryption` 进行保护。因此，使用该方案时，必须先启用 :doc:`../../security/flash-encryption`。 -启用 :doc:`../../security/flash-encryption` 时，默认启用 NVS 加密。这是因为 Wi-Fi 驱动程序会将凭证（如 SSID 和密码）储存在默认的 NVS 分区中。如已启用平台级加密，那么同时默认启用 NVS 加密有其必要性。 +.. only:: SOC_HMAC_SUPPORTED + + 启用 :doc:`../../security/flash-encryption` 时需同时启用 NVS 加密，因为 Wi-Fi 驱动程序会将凭据（如 SSID 和密码）储存在默认的 NVS 分区中。如已启用平台级加密，那么则需要同时启用 NVS 加密。 + +.. only:: not SOC_HMAC_SUPPORTED + + 启用 :doc:`../../security/flash-encryption` 时，默认启用 NVS 加密。这是因为 Wi-Fi 驱动程序会将凭据（如 SSID 和密码）储存在默认的 NVS 分区中。如已启用平台级加密，那么则需要同时默认启用 NVS 加密。 要用这一方案进行 NVS 加密，分区表中必须包含 :ref:`nvs_encr_key_partition`。在分区表选项 ( ``menuconfig`` > ``Partition Table`` ) 中，有两个包含 :ref:`nvs_encr_key_partition` 的分区表，可通过项目配置菜单 ( ``idf.py menuconfig``) 进行选择。要了解如何配置和使用 NVS 加密功能，请参考示例 :example:`security/flash_encryption`。 diff --git a/docs/zh_CN/api-reference/storage/sdmmc.rst b/docs/zh_CN/api-reference/storage/sdmmc.rst index e62bf3822e8..1aa99edbda8 100644 --- a/docs/zh_CN/api-reference/storage/sdmmc.rst +++ b/docs/zh_CN/api-reference/storage/sdmmc.rst @@ -8,7 +8,7 @@ SD/SDIO/MMC 驱动程序 SD/SDIO/MMC 驱动是一种基于 SDMMC 和 SD SPI 主机驱动的协议级驱动程序，目前已支持 SD 存储器、SDIO 卡和 eMMC 芯片。 -SDMMC 主机驱动和 SD SPI 主机驱动（:component_file:`driver/sdmmc/include/driver/sdmmc_host.h` 和 :component_file:`driver/spi/include/driver/sdspi_host.h`）为以下功能提供 API： +SDMMC 主机驱动和 SD SPI 主机驱动（:component_file:`esp_driver_sdmmc/include/driver/sdmmc_host.h` 和 :component_file:`esp_driver_sdspi/include/driver/sdspi_host.h`）为以下功能提供 API： - 发送命令至从设备 - 接收和发送数据 @@ -28,6 +28,25 @@ SDMMC 主机驱动和 SD SPI 主机驱动（:component_file:`driver/sdmmc/includ 协议层通过 :cpp:class:`sdmmc_host_t` 结构体和主机协同工作，该结构体包含指向主机各类函数的指针。 +管脚配置 +------------------ + +..only:: SOC_SDMMC_USE_IOMUX and not SOC_SDMMC_USE_GPIO_MATRIX + + SDMMC 管脚为专用管脚，无需配置。 + +..only:: SOC_SDMMC_USE_GPIO_MATRIX and not SOC_SDMMC_USE_IOMUX + + SDMMC 管脚信号通过 GPIO 交换矩阵配置，请在 :cpp:type:`sdmmc_slot_config_t` 中配置管脚。 + +..only:: esp32p4 + + SDMMC 有两个卡槽： + + .. list:: + + - 卡槽 0 管脚为 UHS-I 模式专用，但驱动程序尚不支持此模式。 + - 卡槽 1 管脚可通过 GPIO 交换矩阵配置，用于 UHS-I 之外的情况。如要使用卡槽 1，请在 :cpp:type:`sdmmc_slot_config_t` 中配置管脚。 应用示例 ------------------- diff --git a/docs/zh_CN/api-reference/storage/vfs.rst b/docs/zh_CN/api-reference/storage/vfs.rst index 5e29685fadb..b27bbd34202 100644 --- a/docs/zh_CN/api-reference/storage/vfs.rst +++ b/docs/zh_CN/api-reference/storage/vfs.rst @@ -103,7 +103,7 @@ VFS 组件支持通过 :cpp:func:`select` 进行同步输入/输出多路复用 .. note:: 在少数情况下，在调用 :cpp:func:`end_select` 之前可能并没有调用过 :cpp:func:`start_select`。因此 :cpp:func:`end_select` 的实现必须在该情况下返回错误而不能崩溃。 -如需获取更多信息，请参考 :component_file:`vfs/vfs_uart.c` 中 UART 外设的 VFS 驱动，尤其是函数 :cpp:func:`esp_vfs_dev_uart_register`、:cpp:func:`uart_start_select` 和 :cpp:func:`uart_end_select`。 +如需获取更多信息，请参考 :component_file:`esp_driver_uart/src/uart_vfs.c` 中 UART 外设的 VFS 驱动，尤其是函数 :cpp:func:`uart_vfs_dev_register`、:cpp:func:`uart_start_select` 和 :cpp:func:`uart_end_select`。 请参考以下示例，查看如何使用 VFS 文件描述符调用 :cpp:func:`select`： @@ -189,9 +189,9 @@ VFS 对文件路径长度没有限制，但文件系统路径前缀受 ``ESP_VFS 默认情况下，VFS 使用简单的函数对 UART 进行读写操作。在所有数据放进 UART FIFO 之前，写操作将处于 busy-wait 状态，读操处于非阻塞状态，仅返回 FIFO 中已有数据。由于读操作为非阻塞，高层级 C 库函数调用（如 ``fscanf("%d\n", &var);``）可能获取不到所需结果。 -如果应用程序使用 UART 驱动，则可以调用 ``esp_vfs_dev_uart_use_driver`` 函数来指导 VFS 使用驱动中断、读写阻塞功能等，也可以调用 ``esp_vfs_dev_uart_use_nonblocking`` 来恢复非阻塞函数。 +如果应用程序使用 UART 驱动，则可以调用 :cpp:func:`uart_vfs_dev_use_driver` 函数来指导 VFS 使用驱动中断、读写阻塞功能等，也可以调用 :cpp:func:`uart_vfs_dev_use_nonblocking` 来恢复非阻塞函数。 -VFS 还为输入和输出提供换行符转换功能（可选）。多数应用程序在程序内部发送或接收以 LF (''\n'') 结尾的行，但不同的终端程序可能需要不同的换行符，比如 CR 或 CRLF。应用程序可以通过 menuconfig 或者调用 ``esp_vfs_dev_uart_port_set_rx_line_endings`` 和 ``esp_vfs_dev_uart_port_set_tx_line_endings`` 为输入输出配置换行符。 +VFS 还为输入和输出提供换行符转换功能（可选）。多数应用程序在程序内部发送或接收以 LF (''\n'') 结尾的行，但不同的终端程序可能需要不同的换行符，比如 CR 或 CRLF。应用程序可以通过 menuconfig 或者调用 :cpp:func:`uart_vfs_dev_port_set_rx_line_endings` 和 :cpp:func:`uart_vfs_dev_port_set_tx_line_endings` 为输入输出配置换行符。 标准流和 FreeRTOS 任务 @@ -235,4 +235,6 @@ API 参考 .. include-build-file:: inc/esp_vfs_dev.inc +.. include-build-file:: inc/uart_vfs.inc + .. include-build-file:: inc/esp_vfs_eventfd.inc diff --git a/docs/zh_CN/api-reference/system/bootloader_image_format.rst b/docs/zh_CN/api-reference/system/bootloader_image_format.rst index 3a87e9b16ba..b77b6c219aa 100644 --- a/docs/zh_CN/api-reference/system/bootloader_image_format.rst +++ b/docs/zh_CN/api-reference/system/bootloader_image_format.rst @@ -1 +1,81 @@ -.. include:: ../../../en/api-reference/system/bootloader_image_format.rst \ No newline at end of file +引导加载程序镜像的格式 +======================= + +:link_to_translation:`en:[English]` + +引导加载程序镜像与应用程序镜像具有相同的结构，参见 :ref:`app-image-structures`。二者唯一的区别在于 :ref:`描述引导加载程序的结构体 ` 不同。 + +要查看关于引导加载程序镜像的更多内容，请运行以下命令： + +.. code-block:: + + esptool.py --chip {IDF_TARGET_PATH_NAME} image_info build/bootloader/bootloader.bin --version 2 + +输出结果如下形式所示： + +.. code-block:: + + File size: 26576 (bytes) + + ESP32 image header + ================== + Image version: 1 + Entry point: 0x40080658 + Segments: 4 + Flash size: 2MB + Flash freq: 40m + Flash mode: DIO + + ESP32 extended image header + =========================== + WP pin: 0xee + Flash pins drive settings: clk_drv: 0x0, q_drv: 0x0, d_drv: 0x0, cs0_drv: 0x0, hd_drv: 0x0, wp_drv: 0x0 + Chip ID: 0 + Minimal chip revision: v0.0, (legacy min_rev = 0) + Maximal chip revision: v3.99 + + Segments information + ==================== + Segment Length Load addr File offs Memory types + ------- ------- ---------- ---------- ------------ + 1 0x01bb0 0x3fff0030 0x00000018 BYTE_ACCESSIBLE, DRAM, DIRAM_DRAM + 2 0x03c90 0x40078000 0x00001bd0 CACHE_APP + 3 0x00004 0x40080400 0x00005868 IRAM + 4 0x00f2c 0x40080404 0x00005874 IRAM + + ESP32 image footer + ================== + Checksum: 0x65 (valid) + Validation hash: 6f31a7f8512f26f6bce7c3b270f93bf6cf1ee4602c322998ca8ce27433527e92 (valid) + + Bootloader information + ====================== + Bootloader version: 1 + ESP-IDF: v5.1-dev-4304-gcb51a3b-dirty + Compile time: Mar 30 2023 19:14:17 + + +.. _image-format-bootloader-description: + +引导加载程序描述 +---------------------- + +引导加载程序二进制文件的 ``DRAM0`` 段起始位置为 :cpp:type:`esp_bootloader_desc_t` 结构体，其中包含描述引导加载程序的特定字段。此结构体位置具有固定偏移量，大小为 sizeof(:cpp:type:`esp_image_header_t`) + sizeof(:cpp:type:`esp_image_segment_header_t`)。 + + * ``magic_byte``：esp_bootloader_desc 结构体的魔术字节 + * ``reserved``：保留供 IDF 未来使用 + * ``version``：引导加载程序版本，参见 :ref:`CONFIG_BOOTLOADER_PROJECT_VER` + * ``idf_ver``：IDF 版本。[#f1]_ + * ``date`` 和 ``time``：编译日期和时间 + * ``reserved2``：保留供 IDF 未来使用 + +.. [#f1] 最大长度为 32 个字符，包括空终止符。 + +如需从正在运行的引导加载程序中获取 :cpp:type:`esp_bootloader_desc_t` 结构体，请使用 :cpp:func:`esp_bootloader_get_description`。 + +如需从正在运行的应用程序中获取 :cpp:type:`esp_bootloader_desc_t` 结构体，请使用 :cpp:func:`esp_ota_get_bootloader_description`。 + +API参考 +------------- + +.. include-build-file:: inc/esp_bootloader_desc.inc diff --git a/docs/zh_CN/api-reference/system/console.rst b/docs/zh_CN/api-reference/system/console.rst index 81af2d9e0a1..550ab6bad25 100644 --- a/docs/zh_CN/api-reference/system/console.rst +++ b/docs/zh_CN/api-reference/system/console.rst @@ -147,7 +147,12 @@ Linenoise 库不需要显式地初始化，但是在调用行编辑函数之前 - 命令名字（不含空格的字符串） - 帮助文档，解释该命令的用途 - 可选的提示文本，列出命令的参数。如果应用程序使用 ``Argtable3`` 库来解析参数，则可以通过提供指向 argtable 参数定义结构体的指针来自动生成提示文本 -- 命令处理函数 +- 命令处理函数（无上下文），或 +- 命令处理函数（有上下文）。如要使用此函数，则必须在调用其他命令 **之前** 调用 :cpp:func:`esp_console_cmd_set_context` 初始化上下文。 + +.. note:: + + 使用接受上下文的命令处理函数或者不接受上下文的命令处理函数均可，但两者不能同时使用。如果使用接受上下文的命令处理程序函数，则必须调用 :cpp:func:`esp_console_cmd_set_context` 初始化上下文，否则该函数可能会访问未初始化的上下文。 命令注册模块还提供了其它函数： diff --git a/docs/zh_CN/api-reference/system/freertos.rst b/docs/zh_CN/api-reference/system/freertos.rst index a2d88e48373..f6663e23758 100644 --- a/docs/zh_CN/api-reference/system/freertos.rst +++ b/docs/zh_CN/api-reference/system/freertos.rst @@ -51,7 +51,7 @@ ESP-IDF FreeRTOS - :ref:`CONFIG_FREERTOS_UNICORE`：仅在 CPU0 上运行 FreeRTOS。注意，这 **不等同于运行原生 FreeRTOS。** 另外，此选项还可能影响除 :component:`freertos` 外其他组件的行为。关于在单核上运行 FreeRTOS 的更多内容，请参考 :ref:`freertos-smp-single-core` （使用 ESP-IDF FreeRTOS 时）或参考 Amazon SMP FreeRTOS 的官方文档，还可以在 ESP-IDF 组件中搜索 ``CONFIG_FREERTOS_UNICORE``。 -.. only:: CONFIG_FREERTOS_UNICORE +.. only:: not SOC_HP_CPU_HAS_MULTIPLE_CORES .. note:: 由于 {IDF_TARGET_NAME} 是一个单核 SoC，所以总是会启用 :ref:`CONFIG_FREERTOS_UNICORE` 配置。 diff --git a/docs/zh_CN/api-reference/system/index.rst b/docs/zh_CN/api-reference/system/index.rst index 92045e52dde..6d5330f9d63 100644 --- a/docs/zh_CN/api-reference/system/index.rst +++ b/docs/zh_CN/api-reference/system/index.rst @@ -25,7 +25,7 @@ heap_debug esp_timer internal-unstable - :not CONFIG_FREERTOS_UNICORE or esp32p4: ipc + :SOC_HP_CPU_HAS_MULTIPLE_CORES: ipc intr_alloc log misc_system_api diff --git a/docs/zh_CN/api-reference/system/internal-unstable.rst b/docs/zh_CN/api-reference/system/internal-unstable.rst index fca9093b800..bc0e299e2b0 100644 --- a/docs/zh_CN/api-reference/system/internal-unstable.rst +++ b/docs/zh_CN/api-reference/system/internal-unstable.rst @@ -1 +1,12 @@ -.. include:: ../../../en/api-reference/system/internal-unstable.rst +内部 API 和不稳定的 API +========================== + +:link_to_translation:`en:[English]` + +该文档列举了一些 API，这些 API 供内部使用或可能在 ESP-IDF 后续版本中被更改或删除。 + + +API 参考 +------------- + +.. include-build-file:: inc/esp_rom_sys.inc diff --git a/docs/zh_CN/api-reference/system/intr_alloc.rst b/docs/zh_CN/api-reference/system/intr_alloc.rst index f795107ac73..1ac547249b9 100644 --- a/docs/zh_CN/api-reference/system/intr_alloc.rst +++ b/docs/zh_CN/api-reference/system/intr_alloc.rst @@ -143,7 +143,7 @@ CPU 中断在大多数 Espressif SoC 上都是有限的资源。因此，一个 .. list:: - :not CONFIG_FREERTOS_UNICORE: - 在多核 SoC 上，尝试通过固定在第二个核的任务来初始化某些外设驱动程序。中断通常分配在运行外设驱动程序初始化函数的同一个内核上，因此，通过在第二个内核上运行初始化函数，就可以使用更多的中断输入。 + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - 在多核 SoC 上，尝试通过固定在第二个核的任务来初始化某些外设驱动程序。中断通常分配在运行外设驱动程序初始化函数的同一个内核上，因此，通过在第二个内核上运行初始化函数，就可以使用更多的中断输入。 - 找到可接受更高延迟的中断，并用 ``ESP_INTR_FLAG_SHARED`` flag （或与 ``ESP_INTR_FLAG_LOWMED`` 进行 OR 运算）分配这些中断。对两个或更多外设使用此 flag 能让它们使用单个中断输入，从而为其他外设节约中断输入。参见 :ref:`intr-alloc-shared-interrupts`。 :not SOC_CPU_HAS_FLEXIBLE_INTC: - 一些外设驱动程序可能默认使用 ``ESP_INTR_FLAG_LEVEL1`` flag 来分配中断，因此默认情况下不会使用优先级为 2 或 3 的中断。如果 :cpp:func:`esp_intr_dump` 显示某些优先级为 2 或 3 的中断可用，尝试在初始化驱动程序时将中断分配 flag 改为 ``ESP_INTR_FLAG_LEVEL2`` 或 ``ESP_INTR_FLAG_LEVEL3``。 - 检查是否有些外设驱动程序不需要一直启用，并按需将其初始化或取消初始化。这样可以减少同时分配的中断数量。 diff --git a/docs/zh_CN/api-reference/system/log.rst b/docs/zh_CN/api-reference/system/log.rst index 9370697449e..0f1329c5205 100644 --- a/docs/zh_CN/api-reference/system/log.rst +++ b/docs/zh_CN/api-reference/system/log.rst @@ -1 +1,137 @@ -.. include:: ../../../en/api-reference/system/log.rst \ No newline at end of file +日志库 +=============== + +:link_to_translation:`en:[English]` + +概述 +-------- + +日志库提供了三种设置日志级别的方式： + +- **编译时**：在 menuconfig 中，使用选项 :ref:`CONFIG_LOG_DEFAULT_LEVEL` 来设置日志级别。 +- 另外，还可以选择在 menuconfig 中使用选项 :ref:`CONFIG_LOG_MAXIMUM_LEVEL` 设置最高日志级别。这个选项默认被配置为默认级别，但这个选项也可以被配置为更高级别，将更多的可选日志编译到固件中。 +- **运行时**：默认启用所有级别低于 :ref:`CONFIG_LOG_DEFAULT_LEVEL` 的日志。:cpp:func:`esp_log_level_set` 函数可以为各个模块分别设置不同的日志级别，可通过人类可读的 ASCII 零终止字符串标签来识别不同的模块。 +- **运行时**：启用 :ref:`CONFIG_LOG_MASTER_LEVEL` 时，可以使用 :cpp:func:`esp_log_set_level_master` 函数设置 ``主日志级别`` (Master logging level)。该选项会为所有已编译的日志添加额外的日志级别检查。注意，使用此选项会增加应用程序大小。如果希望在运行时编译大量可选日志，同时避免在不需要日志输出时查找标签及其级别带来的性能损耗，此功能会非常有用。 + +以下是不同的日志级别： + +- 错误（Error，最低级别） +- 警告 (Warning) +- 普通 (Info) +- 调试 (Debug) +- 冗余（Verbose，最高级别） + +.. note:: + + 注意，函数 :cpp:func:`esp_log_level_set` 无法将日志级别设置为高于 :ref:`CONFIG_LOG_MAXIMUM_LEVEL` 指定的级别。如需在编译时将特定文件的日志级别提高到此最高级别以上，请使用 `LOG_LOCAL_LEVEL` 宏（详细信息见下文）。 + + +如何使用日志库 +----------------------- + +在使用日志功能的所有 C 文件中，将 TAG 变量定义如下： + +.. code-block:: c + + static const char* TAG = "MyModule"; + +然后使用一个日志宏进行输出，例如： + +.. code-block:: c + + ESP_LOGW(TAG, "Baud rate error %.1f%%. Requested: %d baud, actual: %d baud", error * 100, baud_req, baud_real); + +可使用下列宏来定义不同的日志级别： + +* ``ESP_LOGE`` - 错误（最低级别） +* ``ESP_LOGW`` - 警告 +* ``ESP_LOGI`` - 普通 +* ``ESP_LOGD`` - 调试 +* ``ESP_LOGV`` - 冗余（最高级别） + +此外，上述宏还有对应的 ``ESP_EARLY_LOGx`` 版本，如 :c:macro:`ESP_EARLY_LOGE`。这些版本的宏必须在堆分配器和系统调用初始化之前，在早期启动代码中显式使用。通常情况下，编译引导加载程序时也可以使用普通的 ``ESP_LOGx`` 宏，但其最终实现与 ``ESP_EARLY_LOGx`` 宏相同。 + +上述宏还有对应的 ``ESP_DRAM_LOGx`` 版本，如 :c:macro:`ESP_DRAM_LOGE`。在禁用中断或无法访问 flash cache 的情况下需要输出日志时，可以使用这些版本的宏。但是，应尽量避免使用这些宏版本，因为在上述情况下输出日志可能会影响性能。 + +.. note:: + + 在关键部分中断被禁用，因此只能使用 ``ESP_DRAM_LOGx``（首选）或 ``ESP_EARLY_LOGx`` 宏。尽管这样可以输出日志，但最好可以调整程序使其不用输出日志。 + +如需在文件或组件范围内覆盖默认的日志级别，请定义 ``LOG_LOCAL_LEVEL`` 宏。 + +在文件中，该宏应在包含 ``esp_log.h`` 文件前进行定义，例如： + +.. code-block:: c + + #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE + #include "esp_log.h" + +在组件中，该宏应在组件的 CMakeList 中进行定义： + +.. code-block:: cmake + + target_compile_definitions(${COMPONENT_LIB} PUBLIC "-DLOG_LOCAL_LEVEL=ESP_LOG_VERBOSE") + +如需在运行时按模块配置日志输出，请按如下方式调用 :cpp:func:`esp_log_level_set` 函数： + +.. code-block:: c + + esp_log_level_set("*", ESP_LOG_ERROR); // 将所有组件的日志级别设置为错误 (ERROR) 级别 + esp_log_level_set("wifi", ESP_LOG_WARN); // 启用来自 WiFi 堆栈的警告 (WARN) 日志 + esp_log_level_set("dhcpc", ESP_LOG_INFO); // 启用来自 DHCP 客户端的普通 (INFO) 日志 + +.. note:: + + 上文介绍的 "DRAM" 和 "EARLY" 日志宏变型不支持按照模块设置日志级别。这些宏始终以“默认”级别记录日志，且只能在运行时调用 ``esp_log_level("*", level)`` 对日志级别进行更改。 + +即使已通过标签名称禁用日志输出，每个条目仍需约 10.9 微秒的处理时间。 + +主日志级别 +^^^^^^^^^^^^^^^^^^^^ + +要启用主日志级别功能，须启用 :ref:`CONFIG_LOG_MASTER_LEVEL` 选项。该功能在调用 :cpp:func:`esp_log_write` 之前为 ``ESP_LOGx`` 宏添加了额外的级别检查。这样就可以设置更高的 :ref:`CONFIG_LOG_MAXIMUM_LEVEL`，并且不会在正常操作期间对性能造成影响（仅在有指示时）。应用程序可以全局设置主日志级别（:cpp:func:`esp_log_set_level_master`）以强制执行最高日志级别。高于此级别的 ``ESP_LOGx`` 宏将直接跳过，不会调用 :cpp:func:`esp_log_write` 并进行标签查找。建议只在顶层应用程序中使用此功能，不要在共享组件中使用，因为这将覆盖所有使用该组件的用户的全局日志级别。默认情况下，启动时主日志级别是 :ref:`CONFIG_LOG_DEFAULT_LEVEL`。 + +注意，由于此功能为所有 ``ESP_LOGx`` 宏添加了额外的检查，会导致应用程序的大小增加。 + +以下代码片段展示了主日志级别的运行方式。将主日志级别设置为 ``ESP_LOG_NONE`` 将在全局范围内禁用所有日志记录。:cpp:func:`esp_log_level_set` 目前不会影响日志记录。但在主日志级别释放后，日志将按照 :cpp:func:`esp_log_level_set` 中的设置打印输出。 + +.. code-block:: c + + // 在启动时，主日志级别为 CONFIG_LOG_DEFAULT_LEVEL，并等于ESP_LOG_INFO + ESP_LOGI("lib_name", "用于打印的消息"); // 打印普通 (INFO) 级别消息 + esp_log_level_set("lib_name", ESP_LOG_WARN); // 启用 lib_name 的警告 (WARN) 日志 + + esp_log_set_level_master(ESP_LOG_NONE); // 全局禁用所有日志。esp_log_level_set 目前没有生效 + + ESP_LOGW("lib_name", "用于打印的消息"); // 主日志级别阻止了打印 + esp_log_level_set("lib_name", ESP_LOG_INFO); // 启用 lib_name 的 INFO 日志 + ESP_LOGI("lib_name", "用于打印的消息"); // 主日志级别阻止了打印 + + esp_log_set_level_master(ESP_LOG_INFO); // 全局启用所有 INFO 日志 + + ESP_LOGI("lib_name", "用于打印的消息"); // 打印一条 INFO 消息 + +通过 JTAG 将日志记录到主机 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +默认情况下，日志库使用类似 vprintf 的函数将格式化输出写入专用 UART。通过调用一个简单的 API，即可将所有日志通过 JTAG 输出，将日志输出速度提高数倍。如需了解详情，请参阅 :ref:`app_trace-logging-to-host`。 + +线程安全 +^^^^^^^^^^^^^ + +日志字符串首先被写入内存 buffer，然后发送到 UART 打印。日志调用是线程安全的，即不同线程的日志不会互相冲突。 + + +应用示例 +------------------- + +大多数 ESP-IDF 组件和示例都会使用日志库。如需查看有关日志功能的应用示例，请前往 ESP-IDF 的 :idf:`examples` 目录。与日志最相关的示例如下： + +* :example:`system/ota` +* :example:`storage/sd_card` +* :example:`protocols/https_request` + +API 参考 +------------- + +.. include-build-file:: inc/esp_log.inc diff --git a/docs/zh_CN/api-reference/system/mem_alloc.rst b/docs/zh_CN/api-reference/system/mem_alloc.rst index b723cc6f36f..5158750ae5a 100644 --- a/docs/zh_CN/api-reference/system/mem_alloc.rst +++ b/docs/zh_CN/api-reference/system/mem_alloc.rst @@ -31,7 +31,10 @@ ESP-IDF 应用程序使用常见的计算机架构模式：由程序控制流动 所有的 DRAM 内存都可以单字节访问，因此所有的 DRAM 堆都具有 ``MALLOC_CAP_8BIT`` 属性。要获取所有 DRAM 堆的剩余空间大小，请调用 ``heap_caps_get_free_size(MALLOC_CAP_8BIT)``。 -如果占用了所有的 ``MALLOC_CAP_8BIT`` 堆空间，则可以用 ``MALLOC_CAP_IRAM_8BIT`` 代替。此时，若只以 32 位对齐的方式访问 IRAM 内存，或者启用了 ``CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY``，则仍然可以将 IRAM 用作内部内存的“储备池”。 +.. only:: esp32 + + 如果占用了所有的 ``MALLOC_CAP_8BIT`` 堆空间，则可以用 ``MALLOC_CAP_IRAM_8BIT`` 代替。此时，若只以 32 位对齐的方式访问 IRAM 内存，或者启用了 ``CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY``，则仍然可以将 IRAM 用作内部内存的“储备池”。 + 调用 ``malloc()`` 时，ESP-IDF ``malloc()`` 内部调用 ``heap_caps_malloc_default(size)``，使用属性 ``MALLOC_CAP_DEFAULT`` 分配内存。该属性可实现字节寻址功能，即存储空间的最小编址单位为字节。 @@ -122,11 +125,11 @@ DMA 存储器 外部 SPI 内存 ^^^^^^^^^^^^^^^^^^^ - 当启用 :doc:`片外 RAM ` 时，可以根据配置调用标准 ``malloc`` 或通过 ``heap_caps_malloc(MALLOC_CAP_SPIRAM)`` 分配小于 4 MiB 的外部 SPI RAM，详情请参阅 :ref:`external_ram_config`。 + 当启用 :doc:`片外 RAM ` 时，可以根据配置调用标准 ``malloc`` 或通过 ``heap_caps_malloc(MALLOC_CAP_SPIRAM)`` 分配外部 SPI RAM，详情请参阅 :ref:`external_ram_config`。 .. only:: esp32 - 要使用超过 4 MiB 限制的区域，可以使用 :doc:`himem API`。 + 在 ESP32 上，只有不超过 4 MiB 的外部 SPI RAM 可以通过上述方式分配。要使用超过 4 MiB 限制的区域，可以使用 :doc:`himem API`。 线程安全性 ------------- diff --git a/docs/zh_CN/api-reference/system/misc_system_api.rst b/docs/zh_CN/api-reference/system/misc_system_api.rst index 4ac8cab8880..22757cc686e 100644 --- a/docs/zh_CN/api-reference/system/misc_system_api.rst +++ b/docs/zh_CN/api-reference/system/misc_system_api.rst @@ -4,7 +4,7 @@ :link_to_translation:`en:[English]` {IDF_TARGET_BASE_MAC_BLOCK: default="BLK1", esp32="BLK0"} -{IDF_TARGET_CPU_RESET_DES: default="CPU 复位", esp32="两个 CPU 均复位", esp32s3="两个 CPU 均复位"} +{IDF_TARGET_CPU_RESET_DES: default="CPU 复位", esp32="两个 CPU 均复位", esp32s3="两个 CPU 均复位", esp32p4="两个 CPU 均复位"} 软件复位 ------------ diff --git a/docs/zh_CN/api-reference/system/pthread.rst b/docs/zh_CN/api-reference/system/pthread.rst index 8a5f5e6bad2..ad23de102ef 100644 --- a/docs/zh_CN/api-reference/system/pthread.rst +++ b/docs/zh_CN/api-reference/system/pthread.rst @@ -189,7 +189,7 @@ ESP-IDF 扩展 .. list:: - 如果调用 ``pthread_create()`` 时未指定默认堆栈大小，可设置新线程的默认堆栈大小（覆盖 :ref:`CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT`）。 - 新线程的 RTOS 优先级（覆盖 :ref:`CONFIG_PTHREAD_TASK_PRIO_DEFAULT`）。 - :not CONFIG_FREERTOS_UNICORE: - 新线程的内核亲和性/内核固定（覆盖 :ref:`CONFIG_PTHREAD_TASK_CORE_DEFAULT`）。 + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - 新线程的内核亲和性/内核固定（覆盖 :ref:`CONFIG_PTHREAD_TASK_CORE_DEFAULT`）。 - 新线程的 FreeRTOS 任务名称（覆盖 :ref:`CONFIG_PTHREAD_TASK_NAME_DEFAULT`） 此配置的作用范围是调用线程或 FreeRTOS 任务，这意味着 :cpp:func:`esp_pthread_set_cfg` 可以在不同的线程或任务中独立调用。如果在当前配置中设置了 ``inherit_cfg`` 标志，那么当一个线程递归调用 ``pthread_create()`` 时，任何新创建的线程都会继承该线程的配置，否则新线程将采用默认配置。 diff --git a/docs/zh_CN/api-reference/system/random.rst b/docs/zh_CN/api-reference/system/random.rst index bcd4592e10c..b8980f81aca 100644 --- a/docs/zh_CN/api-reference/system/random.rst +++ b/docs/zh_CN/api-reference/system/random.rst @@ -1 +1,87 @@ -.. include:: ../../../en/api-reference/system/random.rst +随机数发生器 +======================== + +:link_to_translation:`en:[English]` + +{IDF_TARGET_RF_NAME: default="Wi-Fi 或蓝牙", esp32s2="Wi-Fi", esp32h2="蓝牙或 802.15.4 Thread/Zigbee", esp32c6="Wi-Fi 或蓝牙或 802.15.4 Thread/Zigbee"} +{IDF_TARGET_RF_IS: default="已启用", esp32s2="已启用"} +{IDF_TARGET_BOOTLOADER_RANDOM_INCOMPATIBLE: default="", esp32="I2S、"} + +{IDF_TARGET_NAME} 中包含一个硬件随机数发生器 (RNG)，可以调用 API :cpp:func:`esp_random` 和 :cpp:func:`esp_fill_random` 从中获取随机数值。 + +满足下列任意一个或多个条件时，硬件 RNG 会产生真随机数： + +- RF 子系统已启用，即 {IDF_TARGET_RF_NAME} {IDF_TARGET_RF_IS}。 +- 调用 :cpp:func:`bootloader_random_enable` 启用了内部熵源，并且熵源尚未被 :cpp:func:`bootloader_random_disable` 禁用。 +- 在 ESP-IDF :ref:`second-stage-bootloader` 运行时。这是因为默认的 ESP-IDF 引导加载程序启动时会调用 :cpp:func:`bootloader_random_enable`，并在执行应用程序前调用 :cpp:func:`bootloader_random_disable`。 + +当上述任一条件为真时，物理噪声样本会连续混合到内部硬件 RNG 状态中来提供熵。如需了解详情，请参阅 **{IDF_TARGET_NAME} 技术参考手册** > **随机数发生器 (RNG)** [`PDF <{IDF_TARGET_TRM_CN_URL}#rng>`__] 章节。 + +如果上述条件都不满足，那么 RNG 的输出仅应被看作伪随机数。 + +启动 +------- + +在启动过程中，ESP-IDF 引导加载程序暂时会启用一个非 RF 熵源（内部参考电压噪声），为首次生成的启动密钥提供熵。当应用程序开始执行后，一直到 {IDF_TARGET_RF_NAME} 初始化完成前，通常只有伪随机数可用。 + +如需在应用程序启动期间临时重启熵源，或为不使用 {IDF_TARGET_RF_NAME} 的应用程序临时重启熵源，请调用函数 :cpp:func:`bootloader_random_enable` 重启内部熵源。在使用 ADC、{IDF_TARGET_BOOTLOADER_RANDOM_INCOMPATIBLE} 或使用 {IDF_TARGET_RF_NAME} 前，必须调用函数 :cpp:func:`bootloader_random_disable` 以禁用熵源。 + +.. note:: + + ESP-IDF 第二阶段引导加载程序在启动过程中启用的熵源会用熵来初始化内部 RNG 状态。但是，内部硬件 RNG 状态的大小并不足以提供连续的真随机数流。因此，在需要真随机数时必须启用连续的熵源。 + +.. note:: + + 如果应用程序需要真随机数源，但无法永久性地启用硬件熵源，可以考虑使用软件 DRBG （确定性随机数发生器）来实现，如 mbedTLS CTR-DRBG 或 HMAC-DRBG，并使用来自硬件 RNG 真随机数来获取初始熵。 + +.. only:: not esp32 + + 二级熵源 + ----------------- + + {IDF_TARGET_NAME} RNG 包含一个基于异步 8 MHz 内部振荡器采样的二级熵源（详情请参阅技术参考手册）。该熵源在 ESP-IDF 中始终处于启用状态，并通过硬件持续混合到 RNG 状态中。在测试中，即使在不启用主熵源时，这个二级熵源也足以通过 `Dieharder`_ 随机数测试套件（测试输入数据是通过连续重置 {IDF_TARGET_NAME} 生成短样本并将其拼接来创建的）。但是，目前只有在同时启用上文所述的主熵源时，才能保证产生真随机数。 + +API 参考 +------------- + +.. include-build-file:: inc/esp_random.inc +.. include-build-file:: inc/bootloader_random.inc + +``getrandom()`` +--------------- + +为方便移植，还提供了与 Linux 的 ``getrandom()`` 函数兼容的版本： + +.. code-block:: c + + #include + + ssize_t getrandom(void *buf, size_t buflen, unsigned int flags); + +此函数通过内部调用 :cpp:func:`esp_fill_random` 来实现。 + +``flags`` 参数将被忽略。该函数始终是非阻塞的，但随机数的强度取决于本文档所述条件。 + +如果 ``buf`` 参数为 NULL，返回值为 -1，并将 ``errno`` 设置为 ``EFAULT``。否则返回 ``buflen``。 + +``getentropy()`` +---------------- + +为了便于移植，还提供了与 Linux 的 ``getentropy()`` 函数兼容的版本： + +.. code-block:: c + + #include + + int getentropy(void *buffer, size_t length); + +此函数通过内部调用 :cpp:func:`getrandom` 实现。 + +随机数强度取决于本文档所述条件。 + +如果执行成功则返回 0，否则返回 -1，同时： + + - 如果 ``buffer`` 参数为 NULL，``errno`` 设置为 ``EFAULT``。 + - 如果 ``length`` 超过 256，``errno`` 设置为 ``EIO``。 + +.. _Dieharder: https://webhome.phy.duke.edu/~rgb/General/dieharder.php diff --git a/docs/zh_CN/api-reference/system/sleep_modes.rst b/docs/zh_CN/api-reference/system/sleep_modes.rst index ea367bff3b7..a1a4c1091ce 100644 --- a/docs/zh_CN/api-reference/system/sleep_modes.rst +++ b/docs/zh_CN/api-reference/system/sleep_modes.rst @@ -220,7 +220,7 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒 外部唤醒 (``ext1``) ^^^^^^^^^^^^^^^^^^^^^^ - RTC 控制器中包含使用多个 RTC GPIO 触发唤醒的逻辑。从以下两个逻辑函数中任选其一，均可触发普通 ext1 唤醒： + RTC 控制器中包含使用多个 RTC GPIO 触发唤醒的逻辑。从以下两个逻辑函数中任选其一，均可触发 ext1 唤醒： .. only:: esp32 @@ -248,11 +248,13 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒 gpio_pullup_dis(gpio_num); gpio_pulldown_en(gpio_num); - 可调用 :cpp:func:`esp_sleep_enable_ext1_wakeup` 函数来启用普通 ext1 唤醒。 + 可调用 :cpp:func:`esp_sleep_enable_ext1_wakeup_io` 函数可用于增加 ext1 唤醒 IO 并设置相应的唤醒电平。 + + 可调用 :cpp:func:`esp_sleep_disable_ext1_wakeup_io` 函数可用于移除 ext1 唤醒 IO。 .. only:: SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN - 除了上述提到的普通 ext1 唤醒之外，当前的 RTC 控制器也包含更强大的逻辑，可以使用多个 RTC GPIO 并根据自定义的 RTC IO 唤醒电平位图来唤醒。这可以通过:cpp:func:`esp_sleep_enable_ext1_wakeup_with_level_mask` 函数来进行配置。 + 当前的 RTC 控制器也包含更强大的逻辑，允许配置的 IO 同时使用不同的唤醒电平。这可以通过:cpp:func:`esp_sleep_enable_ext1_wakeup_io` 函数来进行配置。 .. warning:: @@ -305,6 +307,12 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒 此外，可将由 VDD3P3_RTC 电源域供电的 IO 用于芯片的 Deep-sleep 唤醒。调用 :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` 函数可以配置相应的唤醒管脚和唤醒触发电平，该函数用于启用相应管脚的 Deep-sleep 唤醒功能。 + .. only:: esp32c6 or esp32h2 + + .. note:: + + 在 Light-sleep 模式下，设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP` 将使 GPIO 唤醒失效。 + UART 唤醒（仅适用于 Light-sleep 模式） ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -312,6 +320,12 @@ UART 唤醒（仅适用于 Light-sleep 模式） 可调用 :cpp:func:`esp_sleep_enable_uart_wakeup` 函数来启用此唤醒源。 + .. only:: esp32c6 or esp32h2 + + .. note:: + + 在 Light-sleep 模式下，设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP` 将使 UART 唤醒失效。 + .. _disable_sleep_wakeup_source: 禁用睡眠模式唤醒源 @@ -431,20 +445,15 @@ UART 输出处理 应用程序示例 ------------------- -- :example:`protocols/sntp`：如何实现 Deep-sleep 模式的基本功能，周期性唤醒 ESP 模块，以从 NTP 服务器获取时间。 -- :example:`wifi/power_save`：如何通过 Wi-Fi Modem-sleep 模式和自动 Light-sleep 模式保持 Wi-Fi 连接。 - -.. only:: SOC_BT_SUPPORTED - - - :example:`bluetooth/nimble/power_save`：如何通过 Bluetooth Modem-sleep 模式和自动 Light-sleep 模式保持 Bluetooth 连接。 - -.. only:: SOC_ULP_SUPPORTED - - - :example:`system/deep_sleep`：如何使用 Deep-sleep 唤醒触发器和 ULP 协处理器编程。 +.. list:: -.. only:: esp32c3 or esp32c2 + - :example:`protocols/sntp`：如何实现 Deep-sleep 模式的基本功能，周期性唤醒 ESP 模块，以从 NTP 服务器获取时间。 + - :example:`wifi/power_save`：如何通过 Wi-Fi Modem-sleep 模式和自动 Light-sleep 模式保持 Wi-Fi 连接。 + :SOC_BT_SUPPORTED: - :example:`bluetooth/nimble/power_save`：如何通过 Bluetooth Modem-sleep 模式和自动 Light-sleep 模式保持 Bluetooth 连接。 + :SOC_ULP_SUPPORTED: - :example:`system/deep_sleep`：如何使用 Deep-sleep 唤醒触发器和 ULP 协处理器编程。 + :not SOC_ULP_SUPPORTED: - :example:`system/deep_sleep`：如何通过多种芯片支持的唤醒源，如 RTC 定时器, GPIO, EXT0, EXT1, 触摸传感器等，触发 Deep-sleep 唤醒。 + - :example:`system/light_sleep`: 如何使用多种芯片支持的唤醒源，如定时器，GPIO，触摸传感器等，触发 Light-sleep 唤醒。 - - :example:`system/deep_sleep`：如何通过定时器触发 Deep-sleep 唤醒。 API 参考 ------------- diff --git a/docs/zh_CN/api-reference/system/system_time.rst b/docs/zh_CN/api-reference/system/system_time.rst index 6bd7e2aa72a..f14dc188615 100644 --- a/docs/zh_CN/api-reference/system/system_time.rst +++ b/docs/zh_CN/api-reference/system/system_time.rst @@ -3,12 +3,12 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_RTC_CLK_FRE:default="未更新", esp32="150 kHz", esp32s2="90 kHz", esp32s3="136 kHz", esp32c3="136 kHz", esp32c2="136 kHz", esp32c6="150 kHz", esp32h2="150 kHz"} -{IDF_TARGET_INT_OSC_FRE:default="未更新", esp32="8.5 MHz", esp32s2="8.5 MHz", esp32s3="17.5 MHz", esp32c3="17.5 MHz", esp32c2="17.5 MHz", esp32c6="20 MHz"} +{IDF_TARGET_RTC_CLK_FRE:default="未更新", esp32="150 kHz", esp32s2="90 kHz", esp32s3="136 kHz", esp32c3="136 kHz", esp32c2="136 kHz", esp32c6="150 kHz", esp32h2="150 kHz", esp32p4="150 kHz"} +{IDF_TARGET_INT_OSC_FRE:default="未更新", esp32="8.5 MHz", esp32s2="8.5 MHz", esp32s3="17.5 MHz", esp32c3="17.5 MHz", esp32c2="17.5 MHz"} {IDF_TARGET_INT_OSC_FRE_DIVIDED:default="未更新", esp32="约 33 kHz", esp32s2="约 33 kHz", esp32s3="约 68 kHz", esp32c3="约 68 kHz", esp32c2="约 68 kHz"} -{IDF_TARGET_EXT_CRYSTAL_PIN:default="未更新", esp32="32K_XP 和 32K_XN", esp32s2="XTAL_32K_P 和 XTAL_32K_N", esp32s3="XTAL_32K_P 和 XTAL_32K_N", esp32c3="XTAL_32K_P 和 XTAL_32K_N", esp32c6="XTAL_32K_P 和 XTAL_32K_N", esp32h2="XTAL_32K_P 和 XTAL_32K_N"} -{IDF_TARGET_EXT_OSC_PIN:default="未更新", esp32="32K_XN", esp32s2="XTAL_32K_P", esp32s3="XTAL_32K_P", esp32c3="XTAL_32K_P", esp32c2="GPIO0", esp32c6="XTAL_32K_P"} -{IDF_TARGET_HARDWARE_DESIGN_URL:default="未更新", esp32="`ESP32 硬件设计指南 `_", esp32s2="`ESP32-S2 硬件设计指南 `_", esp32s3="`ESP32-S3 硬件设计指南 `_", esp32c3="`ESP32-C3 硬件设计指南 `_", esp32c2="`ESP8684 硬件设计指南 `_", esp32c6="`ESP32-C6 硬件设计指南 `_", esp32h2="`ESP32-H2 硬件设计指南 `_"} +{IDF_TARGET_EXT_CRYSTAL_PIN:default="未更新", esp32="32K_XP 和 32K_XN", esp32s2="XTAL_32K_P 和 XTAL_32K_N", esp32s3="XTAL_32K_P 和 XTAL_32K_N", esp32c3="XTAL_32K_P 和 XTAL_32K_N", esp32c6="XTAL_32K_P 和 XTAL_32K_N", esp32h2="XTAL_32K_P 和 XTAL_32K_N", esp32p4="XTAL_32K_P 和 XTAL_32K_N"} +{IDF_TARGET_EXT_OSC_PIN:default="未更新", esp32="32K_XN", esp32s2="XTAL_32K_P", esp32s3="XTAL_32K_P", esp32c3="XTAL_32K_P", esp32c2="GPIO0", esp32c6="XTAL_32K_P", esp32h2="XTAL_32K_P", esp32p4="XTAL_32K_P"} +{IDF_TARGET_HARDWARE_DESIGN_URL:default="未更新", esp32="`ESP32 硬件设计指南 `_", esp32s2="`ESP32-S2 硬件设计指南 `_", esp32s3="`ESP32-S3 硬件设计指南 `_", esp32c3="`ESP32-C3 硬件设计指南 `_", esp32c2="`ESP8684 硬件设计指南 `_", esp32c6="`ESP32-C6 硬件设计指南 `_", esp32h2="`ESP32-H2 硬件设计指南 `_", esp32p4="`ESP32-P4 硬件设计指南 `_"} 概述 @@ -45,9 +45,9 @@ RTC 定时器有以下时钟源： - ``管脚 {IDF_TARGET_EXT_OSC_PIN} 外置 32 kHz 振荡器``：允许使用由外部电路产生的 32 kHz 时钟。外部时钟信号必须连接到管脚 {IDF_TARGET_EXT_OSC_PIN}。正弦波信号的振幅应小于 1.2 V，方波信号的振幅应小于 1 V。正常模式下，电压范围应为 0.1 < Vcm < 0.5 xVamp，其中 Vamp 代表信号振幅。使用此时钟源时，管脚 {IDF_TARGET_EXT_OSC_PIN} 无法用作 GPIO 管脚。 - :not esp32c6 and not esp32h2: - ``内置 {IDF_TARGET_INT_OSC_FRE} 振荡器的 256 分频时钟 ({IDF_TARGET_INT_OSC_FRE_DIVIDED})``：频率稳定性优于 ``内置 {IDF_TARGET_RTC_CLK_FRE} RC 振荡器``，同样无需外部元件，但 Deep-sleep 模式下电流消耗更高（比默认模式高 5 μA）。 + :not esp32c6 and not esp32h2 and not esp32p4: - ``内置 {IDF_TARGET_INT_OSC_FRE} 振荡器的 256 分频时钟 ({IDF_TARGET_INT_OSC_FRE_DIVIDED})``：频率稳定性优于 ``内置 {IDF_TARGET_RTC_CLK_FRE} RC 振荡器``，同样无需外部元件，但 Deep-sleep 模式下电流消耗更高（比默认模式高 5 μA）。 - :esp32c6 or esp32h2: - ``内置 32 kHz RC 振荡器`` + :esp32c6 or esp32h2 or esp32p4: - ``内置 32 kHz RC 振荡器`` 时钟源的选择取决于系统时间精度要求和睡眠模式下的功耗要求。要修改 RTC 时钟源，请在项目配置中设置 :ref:`CONFIG_RTC_CLK_SRC`。 diff --git a/docs/zh_CN/api-reference/system/ulp-lp-core.rst b/docs/zh_CN/api-reference/system/ulp-lp-core.rst index f52566a32cd..702cbe2d72f 100644 --- a/docs/zh_CN/api-reference/system/ulp-lp-core.rst +++ b/docs/zh_CN/api-reference/system/ulp-lp-core.rst @@ -32,9 +32,9 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 ``ulp_embed_binary`` 的第一个参数为 ULP 二进制文件的文件名，该文件名也用于其他生成的文件，如 ELF 文件、映射文件、头文件和链接器导出文件。第二个参数为 ULP 源文件。第三个参数为组件源文件列表，用于包含要生成的头文件。要正确构建依赖关系、确保在编译这些文件前创建要生成的头文件，都需要此文件列表。有关 ULP 应用程序生成头文件的概念，请参阅本文档后续章节。 -3. 在 menuconfig 中启用 :ref:`CONFIG_ULP_COPROC_ENABLED` 和 :ref:`CONFIG_ULP_COPROC_TYPE` 选项，并将后者设置为 ``CONFIG_ULP_COPROC_TYPE_LP_CORE``。:ref:`CONFIG_ULP_COPROC_RESERVE_MEM` 选项为 ULP 保留 RTC 内存，因此必须设置为一个足够大的值，以存储 ULP LP-Core 代码和数据。如果应用程序组件包含多个 ULP 程序，那么 RTC 内存的大小必须足够容纳其中最大的程序。 +1. 在 menuconfig 中启用 :ref:`CONFIG_ULP_COPROC_ENABLED` 和 :ref:`CONFIG_ULP_COPROC_TYPE` 选项，并将 :ref:`CONFIG_ULP_COPROC_TYPE` 设置为 ``CONFIG_ULP_COPROC_TYPE_LP_CORE``。:ref:`CONFIG_ULP_COPROC_RESERVE_MEM` 选项为 ULP 保留 RTC 内存，因此必须设置为一个足够大的值，以存储 ULP LP-Core 代码和数据。如果应用程序组件包含多个 ULP 程序，那么 RTC 内存的大小必须足够容纳其中最大的程序。 -4. 按照常规步骤构建应用程序（例如 ``idf.py app``）。 +2. 按照常规步骤构建应用程序（例如 ``idf.py app``）。 在构建过程中，采取以下步骤来构建 ULP 程序： @@ -153,12 +153,15 @@ ULP LP-Core 支持的外设 * LP IO * LP I2C + * LP UART 应用示例 -------------------- * 在示例 :example:`system/ulp/lp_core/gpio` 中，ULP LP-Core 协处理器在主 CPU 深度睡眠时轮询 GPIO。 * 在示例 :example:`system/ulp/lp_core/lp_i2c` 中，ULP LP-Core 协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。 +* 在示例 :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 中，低功耗内核上运行的 LP UART 驱动程序读取并回显写入串行控制台的数据。 +* :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。 API 参考 ------------- @@ -168,6 +171,7 @@ API 参考 .. include-build-file:: inc/ulp_lp_core.inc .. include-build-file:: inc/lp_core_i2c.inc +.. include-build-file:: inc/lp_core_uart.inc LP 内核 API 参考 ~~~~~~~~~~~~~~~~~~~~~~ @@ -175,3 +179,5 @@ LP 内核 API 参考 .. include-build-file:: inc/ulp_lp_core_utils.inc .. include-build-file:: inc/ulp_lp_core_gpio.inc .. include-build-file:: inc/ulp_lp_core_i2c.inc +.. include-build-file:: inc/ulp_lp_core_uart.inc +.. include-build-file:: inc/ulp_lp_core_print.inc diff --git a/docs/zh_CN/api-reference/system/wdts.rst b/docs/zh_CN/api-reference/system/wdts.rst index bb582b962b0..df6f18c0cb9 100644 --- a/docs/zh_CN/api-reference/system/wdts.rst +++ b/docs/zh_CN/api-reference/system/wdts.rst @@ -113,7 +113,7 @@ TWDT 的默认超时时间可以通过 :ref:`CONFIG_ESP_TASK_WDT_TIMEOUT_S` 配 - :ref:`CONFIG_ESP_TASK_WDT_EN` - 启用 TWDT 功能。如果禁用此选项， TWDT 即使运行时已初始化也无法使用。 - :ref:`CONFIG_ESP_TASK_WDT_INIT` - TWDT 在启动期间自动初始化。禁用此选项时，仍可以调用 :cpp:func:`esp_task_wdt_init` 在运行时初始化 TWDT。 - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0` - {IDF_TARGET_IDLE_TASK}在启动时订阅了 TWDT。如果此选项被禁用，仍可以调用 :cpp:func:`esp_task_wdt_init` 再次订阅。 - :not CONFIG_FREERTOS_UNICORE: - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` - CPU1 空闲任务在启动时订阅了 TWDT。 + :SOC_HP_CPU_HAS_MULTIPLE_CORES: - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` - CPU1 空闲任务在启动时订阅了 TWDT。 .. note:: diff --git a/docs/zh_CN/contribute/esp-idf-tests-with-pytest.rst b/docs/zh_CN/contribute/esp-idf-tests-with-pytest.rst index 88246441b20..a55837d76dd 100644 --- a/docs/zh_CN/contribute/esp-idf-tests-with-pytest.rst +++ b/docs/zh_CN/contribute/esp-idf-tests-with-pytest.rst @@ -627,6 +627,8 @@ CI 用于执行所有相关测试的命令为： ``pytest --target 如果是其他情况，pytest 会执行所有 sdkconfig 文件包含 ``sdkconfig.ci.`` 的测试用例。 +- 使用 ``pytest -k `` 按测试用例名称筛选，可以运行单个测试用例，例如 ``pytest -k test_int_wdt_cache_disabled``。 + 添加新 marker ---------------- diff --git a/docs/zh_CN/get-started/esp32_output_log.inc b/docs/zh_CN/get-started/esp32_output_log.inc new file mode 100644 index 00000000000..67b270cf314 --- /dev/null +++ b/docs/zh_CN/get-started/esp32_output_log.inc @@ -0,0 +1,39 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin + esptool.py v3.0-dev + Serial port /dev/ttyUSB0 + Connecting........_ + Chip is ESP32D0WDQ6 (revision 0) + Features: WiFi, BT, Dual Core, Coding Scheme None + Crystal is 40MHz + MAC: 24:0a:c4:05:b9:14 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 5962.8 kbit/s)... + Hash of data verified. + Compressed 26096 bytes to 15408... + Writing at 0x00001000... (100 %) + Wrote 26096 bytes (15408 compressed) at 0x00001000 in 0.4 seconds (effective 546.7 kbit/s)... + Hash of data verified. + Compressed 147104 bytes to 77364... + Writing at 0x00010000... (20 %) + Writing at 0x00014000... (40 %) + Writing at 0x00018000... (60 %) + Writing at 0x0001c000... (80 %) + Writing at 0x00020000... (100 %) + Wrote 147104 bytes (77364 compressed) at 0x00010000 in 1.9 seconds (effective 615.5 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32c2_output_log.inc b/docs/zh_CN/get-started/esp32c2_output_log.inc new file mode 100644 index 00000000000..e194676a332 --- /dev/null +++ b/docs/zh_CN/get-started/esp32c2_output_log.inc @@ -0,0 +1,41 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py esp32c2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 60m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v3.3.1 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-C2 (revision 1) + Features: Wi-Fi + Crystal is 40MHz + MAC: 10:97:bd:f0:e5:0c + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00004fff... + Flash will be erased from 0x00010000 to 0x0002ffff... + Flash will be erased from 0x00008000 to 0x00008fff... + Compressed 18192 bytes to 10989... + Writing at 0x00000000... (100 %) + Wrote 18192 bytes (10989 compressed) at 0x00000000 in 0.6 seconds (effective 248.5 kbit/s)... + Hash of data verified. + Compressed 128640 bytes to 65895... + Writing at 0x00010000... (20 %) + Writing at 0x00019539... (40 %) + Writing at 0x00020bf2... (60 %) + Writing at 0x00027de1... (80 %) + Writing at 0x0002f480... (100 %) + Wrote 128640 bytes (65895 compressed) at 0x00010000 in 1.7 seconds (effective 603.0 kbit/s)... + Hash of data verified. + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 360.1 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32c3_output_log.inc b/docs/zh_CN/get-started/esp32c3_output_log.inc new file mode 100644 index 00000000000..33d56b5e488 --- /dev/null +++ b/docs/zh_CN/get-started/esp32c3_output_log.inc @@ -0,0 +1,39 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py --chip esp32c3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin + esptool.py v3.0 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-C3 + Features: Wi-Fi + Crystal is 40MHz + MAC: 7c:df:a1:40:02:a4 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 4238.1 kbit/s)... + Hash of data verified. + Compressed 18960 bytes to 11311... + Writing at 0x00000000... (100 %) + Wrote 18960 bytes (11311 compressed) at 0x00000000 in 0.3 seconds (effective 584.9 kbit/s)... + Hash of data verified. + Compressed 145520 bytes to 71984... + Writing at 0x00010000... (20 %) + Writing at 0x00014000... (40 %) + Writing at 0x00018000... (60 %) + Writing at 0x0001c000... (80 %) + Writing at 0x00020000... (100 %) + Wrote 145520 bytes (71984 compressed) at 0x00010000 in 2.3 seconds (effective 504.4 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32c6_output_log.inc b/docs/zh_CN/get-started/esp32c6_output_log.inc new file mode 100644 index 00000000000..7c640c2a12a --- /dev/null +++ b/docs/zh_CN/get-started/esp32c6_output_log.inc @@ -0,0 +1,49 @@ +.. output_log + +.. code-block:: none + + ... + esptool esp32c6 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset --no-stub write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v4.3 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-C6 (revision v0.0) + Features: WiFi 6, BT 5 + Crystal is 40MHz + MAC: 60:55:f9:f6:01:38 + Changing baud rate to 460800 + Changed. + Enabling default SPI flash mode... + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00004fff... + Flash will be erased from 0x00010000 to 0x00028fff... + Flash will be erased from 0x00008000 to 0x00008fff... + Erasing flash... + Took 0.17s to erase flash block + Writing at 0x00000000... (5 %) + Writing at 0x00000c00... (23 %) + Writing at 0x00001c00... (47 %) + Writing at 0x00003000... (76 %) + Writing at 0x00004000... (100 %) + Wrote 17408 bytes at 0x00000000 in 0.5 seconds (254.6 kbit/s)... + Hash of data verified. + Erasing flash... + Took 0.85s to erase flash block + Writing at 0x00010000... (1 %) + Writing at 0x00014c00... (20 %) + Writing at 0x00019c00... (40 %) + Writing at 0x0001ec00... (60 %) + Writing at 0x00023c00... (80 %) + Writing at 0x00028c00... (100 %) + Wrote 102400 bytes at 0x00010000 in 3.2 seconds (253.5 kbit/s)... + Hash of data verified. + Erasing flash... + Took 0.04s to erase flash block + Writing at 0x00008000... (33 %) + Writing at 0x00008400... (66 %) + Writing at 0x00008800... (100 %) + Wrote 3072 bytes at 0x00008000 in 0.1 seconds (269.0 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32h2_output_log.inc b/docs/zh_CN/get-started/esp32h2_output_log.inc new file mode 100644 index 00000000000..fe526e923d5 --- /dev/null +++ b/docs/zh_CN/get-started/esp32h2_output_log.inc @@ -0,0 +1,41 @@ +.. output_log + +.. code-block:: none + + ... + esptool esp32h2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 48m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v4.6 + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-H2 (revision v0.1) + Features: BLE + Crystal is 32MHz + MAC: 60:55:f9:f7:3e:93:ff:fe + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00005fff... + Flash will be erased from 0x00010000 to 0x00034fff... + Flash will be erased from 0x00008000 to 0x00008fff... + Compressed 20880 bytes to 12788... + Writing at 0x00000000... (100 %) + Wrote 20880 bytes (12788 compressed) at 0x00000000 in 0.6 seconds (effective 297.5 kbit/s)... + Hash of data verified. + Compressed 149424 bytes to 79574... + Writing at 0x00010000... (20 %) + Writing at 0x00019959... (40 %) + Writing at 0x00020bb5... (60 %) + Writing at 0x00026d8f... (80 %) + Writing at 0x0002e60a... (100 %) + Wrote 149424 bytes (79574 compressed) at 0x00010000 in 2.1 seconds (effective 571.7 kbit/s)... + Hash of data verified. + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 539.7 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32p4_output_log.inc b/docs/zh_CN/get-started/esp32p4_output_log.inc new file mode 100644 index 00000000000..69a66d4736d --- /dev/null +++ b/docs/zh_CN/get-started/esp32p4_output_log.inc @@ -0,0 +1 @@ +.. output_log \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32s2_output_log.inc b/docs/zh_CN/get-started/esp32s2_output_log.inc new file mode 100644 index 00000000000..95279df68b7 --- /dev/null +++ b/docs/zh_CN/get-started/esp32s2_output_log.inc @@ -0,0 +1,39 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py --chip esp32s2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin + esptool.py v3.0-dev + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-S2 + Features: WiFi + Crystal is 40MHz + MAC: 18:fe:34:72:50:e3 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 3851.6 kbit/s)... + Hash of data verified. + Compressed 22592 bytes to 13483... + Writing at 0x00001000... (100 %) + Wrote 22592 bytes (13483 compressed) at 0x00001000 in 0.3 seconds (effective 595.1 kbit/s)... + Hash of data verified. + Compressed 140048 bytes to 70298... + Writing at 0x00010000... (20 %) + Writing at 0x00014000... (40 %) + Writing at 0x00018000... (60 %) + Writing at 0x0001c000... (80 %) + Writing at 0x00020000... (100 %) + Wrote 140048 bytes (70298 compressed) at 0x00010000 in 1.7 seconds (effective 662.5 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/zh_CN/get-started/esp32s3_output_log.inc b/docs/zh_CN/get-started/esp32s3_output_log.inc new file mode 100644 index 00000000000..b8caeaed3cc --- /dev/null +++ b/docs/zh_CN/get-started/esp32s3_output_log.inc @@ -0,0 +1,43 @@ +.. output_log + +.. code-block:: none + + ... + esptool.py esp32s3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin + esptool.py v3.2-dev + Serial port /dev/ttyUSB0 + Connecting.... + Chip is ESP32-S3 + Features: WiFi, BLE + Crystal is 40MHz + MAC: 7c:df:a1:e0:00:64 + Uploading stub... + Running stub... + Stub running... + Changing baud rate to 460800 + Changed. + Configuring flash size... + Flash will be erased from 0x00000000 to 0x00004fff... + Flash will be erased from 0x00010000 to 0x00039fff... + Flash will be erased from 0x00008000 to 0x00008fff... + Compressed 18896 bytes to 11758... + Writing at 0x00000000... (100 %) + Wrote 18896 bytes (11758 compressed) at 0x00000000 in 0.5 seconds (effective 279.9 kbit/s)... + Hash of data verified. + Compressed 168208 bytes to 88178... + Writing at 0x00010000... (16 %) + Writing at 0x0001a80f... (33 %) + Writing at 0x000201f1... (50 %) + Writing at 0x00025dcf... (66 %) + Writing at 0x0002d0be... (83 %) + Writing at 0x00036c07... (100 %) + Wrote 168208 bytes (88178 compressed) at 0x00010000 in 2.4 seconds (effective 569.2 kbit/s)... + Hash of data verified. + Compressed 3072 bytes to 103... + Writing at 0x00008000... (100 %) + Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 478.9 kbit/s)... + Hash of data verified. + + Leaving... + Hard resetting via RTS pin... + Done \ No newline at end of file diff --git a/docs/zh_CN/get-started/linux-macos-setup.rst b/docs/zh_CN/get-started/linux-macos-setup.rst index 1df948783be..529346091dd 100644 --- a/docs/zh_CN/get-started/linux-macos-setup.rst +++ b/docs/zh_CN/get-started/linux-macos-setup.rst @@ -216,9 +216,19 @@ ESP-IDF 工具安装器会下载 Github 发布版本中附带的一些工具， 自定义工具安装路径 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -本步骤中介绍的脚本将 ESP-IDF 所需的编译工具默认安装在用户的根目录中，即 Linux 系统中的 ``$HOME/.espressif`` 目录。可以选择将工具安装到其他目录中，但请在运行安装脚本前，重新设置环境变量 ``IDF_TOOLS_PATH``。注意，请确保用户账号已经具备了读写该路径的权限。 +本步骤中介绍的脚本将 ESP-IDF 所需的编译工具默认安装在用户的根目录中，即 Linux 系统中的 ``$HOME/.espressif`` 目录。可以选择将工具安装到其他目录中，**但请在运行安装脚本前，导出环境变量 IDF_TOOLS_PATH**。注意，请确保用户账号已经具备了读写该路径的权限。 -如果修改了 ``IDF_TOOLS_PATH`` 变量，请确保该变量在每次执行安装脚本（``install.bat``、``install.ps1`` 或 ``install.sh``）和导出脚本（``export.bat``、``export.ps1`` 或 ``export.sh``）均保持一致。 +.. code-block:: bash + + export IDF_TOOLS_PATH="$HOME/required_idf_tools_path" + ./install.sh + + . ./export.sh + +如果修改了 ``IDF_TOOLS_PATH`` 变量，请在运行任意 ESP-IDF 工具或脚本前，将该变量导出到环境变量中。 + +.. note:: + 如未导出环境变量，大多数 shell 将不支持在变量赋值中使用 ``IDF_TOOLS_PATH``，例如 ``IDF_TOOLS_PATH="$HOME/required_idf_tools_path" ./install.sh``。因为即便在源脚本中导出或修改了该变量，当前的执行环境也不受变量赋值影响。 .. _get-started-set-up-env: @@ -294,7 +304,6 @@ ESP-IDF 工具安装器会下载 Github 发布版本中附带的一些工具， establish-serial-connection flashing-troubleshooting - ../api-guides/tools/idf-monitor .. _AUR: https://wiki.archlinux.org/index.php/Arch_User_Repository .. _First Steps on ESP-IDF: ../get-started/first-steps.html diff --git a/docs/zh_CN/get-started/start-project.rst b/docs/zh_CN/get-started/start-project.rst index b2f46b1f530..0241beea6ad 100644 --- a/docs/zh_CN/get-started/start-project.rst +++ b/docs/zh_CN/get-started/start-project.rst @@ -60,305 +60,8 @@ 在烧录过程中，会看到类似如下的输出日志： -.. only:: esp32 - - .. code-block:: none - - ... - esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin - esptool.py v3.0-dev - Serial port /dev/ttyUSB0 - Connecting........_ - Chip is ESP32D0WDQ6 (revision 0) - Features: WiFi, BT, Dual Core, Coding Scheme None - Crystal is 40MHz - MAC: 24:0a:c4:05:b9:14 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 5962.8 kbit/s)... - Hash of data verified. - Compressed 26096 bytes to 15408... - Writing at 0x00001000... (100 %) - Wrote 26096 bytes (15408 compressed) at 0x00001000 in 0.4 seconds (effective 546.7 kbit/s)... - Hash of data verified. - Compressed 147104 bytes to 77364... - Writing at 0x00010000... (20 %) - Writing at 0x00014000... (40 %) - Writing at 0x00018000... (60 %) - Writing at 0x0001c000... (80 %) - Writing at 0x00020000... (100 %) - Wrote 147104 bytes (77364 compressed) at 0x00010000 in 1.9 seconds (effective 615.5 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - -.. only:: esp32s2 - - .. code-block:: none - - ... - esptool.py --chip esp32s2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x10000 hello_world.bin - esptool.py v3.0-dev - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-S2 - Features: WiFi - Crystal is 40MHz - MAC: 18:fe:34:72:50:e3 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 3851.6 kbit/s)... - Hash of data verified. - Compressed 22592 bytes to 13483... - Writing at 0x00001000... (100 %) - Wrote 22592 bytes (13483 compressed) at 0x00001000 in 0.3 seconds (effective 595.1 kbit/s)... - Hash of data verified. - Compressed 140048 bytes to 70298... - Writing at 0x00010000... (20 %) - Writing at 0x00014000... (40 %) - Writing at 0x00018000... (60 %) - Writing at 0x0001c000... (80 %) - Writing at 0x00020000... (100 %) - Wrote 140048 bytes (70298 compressed) at 0x00010000 in 1.7 seconds (effective 662.5 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - -.. only:: esp32s3 - - .. code-block:: none - - ... - esptool.py esp32s3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v3.2-dev - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-S3 - Features: WiFi, BLE - Crystal is 40MHz - MAC: 7c:df:a1:e0:00:64 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00004fff... - Flash will be erased from 0x00010000 to 0x00039fff... - Flash will be erased from 0x00008000 to 0x00008fff... - Compressed 18896 bytes to 11758... - Writing at 0x00000000... (100 %) - Wrote 18896 bytes (11758 compressed) at 0x00000000 in 0.5 seconds (effective 279.9 kbit/s)... - Hash of data verified. - Compressed 168208 bytes to 88178... - Writing at 0x00010000... (16 %) - Writing at 0x0001a80f... (33 %) - Writing at 0x000201f1... (50 %) - Writing at 0x00025dcf... (66 %) - Writing at 0x0002d0be... (83 %) - Writing at 0x00036c07... (100 %) - Wrote 168208 bytes (88178 compressed) at 0x00010000 in 2.4 seconds (effective 569.2 kbit/s)... - Hash of data verified. - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 478.9 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - - -.. only:: esp32c2 - - .. code-block:: none - - ... - esptool.py esp32c2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 60m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v3.3.1 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-C2 (revision 1) - Features: Wi-Fi - Crystal is 40MHz - MAC: 10:97:bd:f0:e5:0c - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00004fff... - Flash will be erased from 0x00010000 to 0x0002ffff... - Flash will be erased from 0x00008000 to 0x00008fff... - Compressed 18192 bytes to 10989... - Writing at 0x00000000... (100 %) - Wrote 18192 bytes (10989 compressed) at 0x00000000 in 0.6 seconds (effective 248.5 kbit/s)... - Hash of data verified. - Compressed 128640 bytes to 65895... - Writing at 0x00010000... (20 %) - Writing at 0x00019539... (40 %) - Writing at 0x00020bf2... (60 %) - Writing at 0x00027de1... (80 %) - Writing at 0x0002f480... (100 %) - Wrote 128640 bytes (65895 compressed) at 0x00010000 in 1.7 seconds (effective 603.0 kbit/s)... - Hash of data verified. - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 360.1 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - - -.. only:: esp32c3 - - .. code-block:: none - - ... - esptool.py --chip esp32c3 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x8000 partition_table/partition-table.bin 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin - esptool.py v3.0 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-C3 - Features: Wi-Fi - Crystal is 40MHz - MAC: 7c:df:a1:40:02:a4 - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 4238.1 kbit/s)... - Hash of data verified. - Compressed 18960 bytes to 11311... - Writing at 0x00000000... (100 %) - Wrote 18960 bytes (11311 compressed) at 0x00000000 in 0.3 seconds (effective 584.9 kbit/s)... - Hash of data verified. - Compressed 145520 bytes to 71984... - Writing at 0x00010000... (20 %) - Writing at 0x00014000... (40 %) - Writing at 0x00018000... (60 %) - Writing at 0x0001c000... (80 %) - Writing at 0x00020000... (100 %) - Wrote 145520 bytes (71984 compressed) at 0x00010000 in 2.3 seconds (effective 504.4 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - Done - -.. only:: esp32c6 - - .. code-block:: none - - ... - esptool esp32c6 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset --no-stub write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v4.3 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-C6 (revision v0.0) - Features: WiFi 6, BT 5 - Crystal is 40MHz - MAC: 60:55:f9:f6:01:38 - Changing baud rate to 460800 - Changed. - Enabling default SPI flash mode... - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00004fff... - Flash will be erased from 0x00010000 to 0x00028fff... - Flash will be erased from 0x00008000 to 0x00008fff... - Erasing flash... - Took 0.17s to erase flash block - Writing at 0x00000000... (5 %) - Writing at 0x00000c00... (23 %) - Writing at 0x00001c00... (47 %) - Writing at 0x00003000... (76 %) - Writing at 0x00004000... (100 %) - Wrote 17408 bytes at 0x00000000 in 0.5 seconds (254.6 kbit/s)... - Hash of data verified. - Erasing flash... - Took 0.85s to erase flash block - Writing at 0x00010000... (1 %) - Writing at 0x00014c00... (20 %) - Writing at 0x00019c00... (40 %) - Writing at 0x0001ec00... (60 %) - Writing at 0x00023c00... (80 %) - Writing at 0x00028c00... (100 %) - Wrote 102400 bytes at 0x00010000 in 3.2 seconds (253.5 kbit/s)... - Hash of data verified. - Erasing flash... - Took 0.04s to erase flash block - Writing at 0x00008000... (33 %) - Writing at 0x00008400... (66 %) - Writing at 0x00008800... (100 %) - Wrote 3072 bytes at 0x00008000 in 0.1 seconds (269.0 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... - -.. only:: esp32h2 - - .. code-block:: none - - ... - esptool esp32h2 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 48m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 hello_world.bin 0x8000 partition_table/partition-table.bin - esptool.py v4.6 - Serial port /dev/ttyUSB0 - Connecting.... - Chip is ESP32-H2 (revision v0.1) - Features: BLE - Crystal is 32MHz - MAC: 60:55:f9:f7:3e:93:ff:fe - Uploading stub... - Running stub... - Stub running... - Changing baud rate to 460800 - Changed. - Configuring flash size... - Flash will be erased from 0x00000000 to 0x00005fff... - Flash will be erased from 0x00010000 to 0x00034fff... - Flash will be erased from 0x00008000 to 0x00008fff... - Compressed 20880 bytes to 12788... - Writing at 0x00000000... (100 %) - Wrote 20880 bytes (12788 compressed) at 0x00000000 in 0.6 seconds (effective 297.5 kbit/s)... - Hash of data verified. - Compressed 149424 bytes to 79574... - Writing at 0x00010000... (20 %) - Writing at 0x00019959... (40 %) - Writing at 0x00020bb5... (60 %) - Writing at 0x00026d8f... (80 %) - Writing at 0x0002e60a... (100 %) - Wrote 149424 bytes (79574 compressed) at 0x00010000 in 2.1 seconds (effective 571.7 kbit/s)... - Hash of data verified. - Compressed 3072 bytes to 103... - Writing at 0x00008000... (100 %) - Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.0 seconds (effective 539.7 kbit/s)... - Hash of data verified. - - Leaving... - Hard resetting via RTS pin... +.. include:: {IDF_TARGET_PATH_NAME}_output_log.inc + :start-after: output_log 如果一切顺利，烧录完成后，开发板将会复位，应用程序 "hello_world" 开始运行。 diff --git a/docs/zh_CN/get-started/windows-setup.rst b/docs/zh_CN/get-started/windows-setup.rst index 13fdb60ad53..2c109110c97 100644 --- a/docs/zh_CN/get-started/windows-setup.rst +++ b/docs/zh_CN/get-started/windows-setup.rst @@ -132,7 +132,6 @@ ESP-IDF 工具安装器可在“开始”菜单中，创建一个打开 ESP-IDF windows-setup-update establish-serial-connection flashing-troubleshooting - ../api-guides/tools/idf-monitor .. _CMake: https://cmake.org/download/ .. _Ninja: https://ninja-build.org/ diff --git a/docs/zh_CN/hw-reference/esp32/get-started-devkitc.rst b/docs/zh_CN/hw-reference/esp32/get-started-devkitc.rst index 987a01c8f19..b2efc73befc 100644 --- a/docs/zh_CN/hw-reference/esp32/get-started-devkitc.rst +++ b/docs/zh_CN/hw-reference/esp32/get-started-devkitc.rst @@ -210,6 +210,7 @@ ESP32-DevKitC V4 上电前，请首先确认开发板完好无损。 * `《ESP32 技术规格书》 `_ (PDF) * `《ESP32-WROOM-32 技术规格书》 `_ (PDF) * `《ESP32-WROOM-32D & ESP32-WROOM-32U 技术规格书》 `_ (PDF) +* `《ESP32-WROOM-32E & ESP32-WROOM-32UE 技术规格书》 `_ (PDF) * `《ESP32-WROOM-DA 技术规格书》 `_ (PDF) * `《ESP32-WROVER 技术规格书》 `_ (PDF) * `《ESP32-WROVER-B 技术规格书》 `_ (PDF) diff --git a/docs/zh_CN/migration-guides/release-5.x/5.0/build-system.rst b/docs/zh_CN/migration-guides/release-5.x/5.0/build-system.rst index d762e253324..43ee713096f 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.0/build-system.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.0/build-system.rst @@ -9,7 +9,12 @@ ESP-IDF v5.0 已不再支持基于 Make 的工程，请参考 :ref:`从 ESP-IDF 更新片段文件语法 ---------------------------- -请参考 :ref:`将链接器脚本片段文件语法迁移至 ESP-IDF v5.0 适应版本 ` 对 v3.x 的语法进行更新。 +ESP-IDF v5.0 中将不再支持 ESP-IDF v3.x 中链接器脚本片段文件的旧式语法。在迁移的过程中需注意以下几点： + +- 必须缩进，缩进不当的文件会产生解析异常；旧版本不强制缩进，但之前的文档和示例均遵循了正确的缩进语法。 +- 条件改用 ``if...elif...else`` 结构，可以参照 :ref:`之前的章节`。 +- 映射片段和其他片段类型一样，需有名称。 + 明确指定组件依赖 ----------------------------------------- diff --git a/docs/zh_CN/migration-guides/release-5.x/5.0/peripherals.rst b/docs/zh_CN/migration-guides/release-5.x/5.0/peripherals.rst index adb3f3d4331..2ca83ac1546 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.0/peripherals.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.0/peripherals.rst @@ -459,7 +459,7 @@ LCD I2S 驱动 ----------------------- - 旧版 I2S 驱动在支持 ESP32-C3 和 ESP32-S3 新功能时暴露了很多缺点，为解决这些缺点，I2S 驱动已更新（请参考:doc:`I2S Driver <../../../api-reference/peripherals/i2s>`）。用户可以通过引用不同 I2S 模式对应的头文件来使用新版驱动的 API，如 :component_file:`driver/i2s/include/driver/i2s_std.h`， :component_file:`driver/i2s/include/driver/i2s_pdm.h` 以及 :component_file:`driver/i2s/include/driver/i2s_tdm.h`。 + 旧版 I2S 驱动在支持 ESP32-C3 和 ESP32-S3 新功能时暴露了很多缺点，为解决这些缺点，I2S 驱动已更新（请参考:doc:`I2S Driver <../../../api-reference/peripherals/i2s>`）。用户可以通过引用不同 I2S 模式对应的头文件来使用新版驱动的 API，如 :component_file:`esp_driver_i2s/include/driver/i2s_std.h`， :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h` 以及 :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`。 为保证前向兼容，旧版驱动的 API 仍然在 :component_file:`driver/deprecated/driver/i2s.h` 中可用。但使用旧版 API 会触发编译警告，该警告可通过配置 Kconfig 选项 :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN` 来关闭。 @@ -489,9 +489,9 @@ LCD I2S 通信模式包括以下三种模式，请注意： - - **标准模式**：标准模式通常包括两个声道，支持 Philips，MSB 和 PCM（短帧同步）格式，详见 :component_file:`driver/i2s/include/driver/i2s_std.h`。 - - **PDM模式**：PDM 模式仅支持两个声道，16 bit 数据位宽，但是 PDM TX 和 PDM RX 的配置略有不同。对于 PDM TX，采样率可通过 :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate` 进行设置，其时钟频率取决于上采样的配置。对于 PDM RX，采样率可通过 :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate` 进行设置，其时钟频率取决于下采样的配置，详见 :component_file:`driver/i2s/include/driver/i2s_pdm.h`。 - - **TDM 模式**：TDM 模式可支持高达 16 声道，该模式可工作在 Philips，MSB，PCM（短帧同步）和PCM（长帧同步）格式下，详见 :component_file:`driver/i2s/include/driver/i2s_tdm.h`。 + - **标准模式**：标准模式通常包括两个声道，支持 Philips，MSB 和 PCM（短帧同步）格式，详见 :component_file:`esp_driver_i2s/include/driver/i2s_std.h`。 + - **PDM模式**：PDM 模式仅支持两个声道，16 bit 数据位宽，但是 PDM TX 和 PDM RX 的配置略有不同。对于 PDM TX，采样率可通过 :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate` 进行设置，其时钟频率取决于上采样的配置。对于 PDM RX，采样率可通过 :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate` 进行设置，其时钟频率取决于下采样的配置，详见 :component_file:`esp_driver_i2s/include/driver/i2s_pdm.h`。 + - **TDM 模式**：TDM 模式可支持高达 16 声道，该模式可工作在 Philips，MSB，PCM（短帧同步）和PCM（长帧同步）格式下，详见 :component_file:`esp_driver_i2s/include/driver/i2s_tdm.h`。 在某个模式下分配新通道时，必须通过相应的函数初始化这个通道。我们强烈建议使用辅助宏来生成默认配置，以避免默认值被改动。 diff --git a/docs/zh_CN/migration-guides/release-5.x/5.2/index.rst b/docs/zh_CN/migration-guides/release-5.x/5.2/index.rst index 3e1477075ae..e0b3a2f93f6 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.2/index.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.2/index.rst @@ -9,5 +9,6 @@ gcc peripherals protocols + storage system - wifi + :SOC_WIFI_SUPPORTED: wifi diff --git a/docs/zh_CN/migration-guides/release-5.x/5.2/storage.rst b/docs/zh_CN/migration-guides/release-5.x/5.2/storage.rst new file mode 100644 index 00000000000..0173765c92e --- /dev/null +++ b/docs/zh_CN/migration-guides/release-5.x/5.2/storage.rst @@ -0,0 +1,11 @@ +存储 +==== + +:link_to_translation:`en:[English]` + +NVS 加密 +-------- + +- 在集成 HMAC 外设 (``SOC_HMAC_SUPPORTED``) 的 SoC 上，启用 :doc:`../../../security/flash-encryption` 时将不再自动启用 :doc:`../../../api-reference/storage/nvs_encryption`。 +- 因此需显式启用 NVS 加密，并按照需要选择基于 flash 加密或基于 HMAC 外设的方案。即使未启用 flash 加密，也可选择基于 HMAC 外设的方案 (:ref:`CONFIG_NVS_SEC_KEY_PROTECTION_SCHEME`)。 +- 启用 flash 加密后，未集成 HMAC 外设的 SoC 仍会自动启用 NVS 加密。 diff --git a/docs/zh_CN/migration-guides/release-5.x/5.3/index.rst b/docs/zh_CN/migration-guides/release-5.x/5.3/index.rst index 25aeb7dff3f..51af4fd0013 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.3/index.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.3/index.rst @@ -7,3 +7,6 @@ :maxdepth: 1 peripherals + security + storage + system diff --git a/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst b/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst index 81411dc91f5..09d3f4c59c0 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst @@ -3,11 +3,27 @@ :link_to_translation:`en:[English]` +驱动程序 +--------------- + 为了细粒度地控制其他组件对外设驱动的依赖，原先位于 `driver` 组件下的驱动程序被拆分到了各自独立的组件中。这些组件包括： - `esp_driver_gptimer` - 通用定时器驱动 - `esp_driver_pcnt` - 脉冲计数器驱动 - `esp_driver_gpio` - GPIO 驱动 +- `esp_driver_spi` - 通用 SPI 驱动 +- `esp_driver_mcpwm` - 电机控制 PWM 驱动 +- `esp_driver_sdmmc` - SDMMC 驱动 +- `esp_driver_sdspi` - SDSPI 驱动 +- `esp_driver_sdio` - SDIO 驱动 +- `esp_driver_ana_cmpr` - 模拟比较器驱动 +- `esp_driver_i2s` - I2S 驱动 +- `esp_driver_dac` - DAC 驱动 +- `esp_driver_rmt` - RMT 驱动 +- `esp_driver_tsens` - 温度传感器驱动 +- `esp_driver_sdm` - Sigma-Delta 调制器驱动 +- `esp_driver_i2c` - I2C 驱动 +- `esp_driver_uart` - UART 驱动 为了兼容性，原来的 `driver` 组件仍然存在，并作为一个 “all-in-one" 的组件，将以上这些 `esp_driver_xyz` 组件注册成自己的公共依赖。换句话说，你无需修改既有项目的 CMake 文件，但是你现在多了一个途径去指定你项目依赖的具体的外设驱动。 @@ -28,3 +44,11 @@ archive: libesp_driver_gpio.a entries: gpio (noflash) + + +安全元素 +-------------- + +ATECC608A 安全元素接口示例现已移至 GitHub 上的 `esp-cryptoauthlib 仓库 `_ 中。 + +该示例也是组件管理器注册表中 `esp-cryptoauthlib `_ 的一部分。 diff --git a/docs/zh_CN/migration-guides/release-5.x/5.3/security.rst b/docs/zh_CN/migration-guides/release-5.x/5.3/security.rst new file mode 100644 index 00000000000..2dd66a31bd5 --- /dev/null +++ b/docs/zh_CN/migration-guides/release-5.x/5.3/security.rst @@ -0,0 +1 @@ +.. include:: ../../../../en/migration-guides/release-5.x/5.3/security.rst diff --git a/docs/zh_CN/migration-guides/release-5.x/5.3/storage.rst b/docs/zh_CN/migration-guides/release-5.x/5.3/storage.rst new file mode 100644 index 00000000000..2f896e39000 --- /dev/null +++ b/docs/zh_CN/migration-guides/release-5.x/5.3/storage.rst @@ -0,0 +1,18 @@ +存储 +======= + +:link_to_translation:`en:[English]` + +VFS +--- + +VFS 操作符的 UART 具体实现函数从 `vfs` 组件挪到了 `esp_driver_uart` 组件中。 + +所有以 `esp_vfs_dev_uart_` 前缀开头的 API 已被弃用, 更新成在 `uart_vfs.h` 文件中定义的以 `uart_vfs_dev_` 为前缀的一组 API。具体来说， +- ``esp_vfs_dev_uart_register`` 更名为 ``uart_vfs_dev_register`` +- ``esp_vfs_dev_uart_port_set_rx_line_endings`` 更名为 ``uart_vfs_dev_port_set_rx_line_endings`` +- ``esp_vfs_dev_uart_port_set_tx_line_endings`` 更名为 ``uart_vfs_dev_port_set_tx_line_endings`` +- ``esp_vfs_dev_uart_use_nonblocking`` 更名为 ``uart_vfs_dev_use_nonblocking`` +- ``esp_vfs_dev_uart_use_driver`` 更名为 ``uart_vfs_dev_use_driver`` + +为了兼容性，`vfs` 组件依旧将 `esp_driver_uart` 注册成了其私有依赖。换句话说，你无需修改既有项目的 CMake 文件。 diff --git a/docs/zh_CN/migration-guides/release-5.x/5.3/system.rst b/docs/zh_CN/migration-guides/release-5.x/5.3/system.rst new file mode 100644 index 00000000000..d984c08a777 --- /dev/null +++ b/docs/zh_CN/migration-guides/release-5.x/5.3/system.rst @@ -0,0 +1 @@ +.. include:: ../../../../en/migration-guides/release-5.x/5.3/system.rst \ No newline at end of file diff --git a/docs/zh_CN/security/secure-boot-v1.rst b/docs/zh_CN/security/secure-boot-v1.rst index fd3d07baf60..5bf1e444ba6 100644 --- a/docs/zh_CN/security/secure-boot-v1.rst +++ b/docs/zh_CN/security/secure-boot-v1.rst @@ -1 +1,358 @@ -.. include:: ../../en/security/secure-boot-v1.rst \ No newline at end of file +安全启动 +=========== + +:link_to_translation:`en:[English]` + +.. important:: + + 本文档中的参考均与安全启动 V1，即基于 AES 的安全启动方案有关。版本高于 ESP32 v3.0 的芯片推荐选用 :doc:`secure-boot-v2`。 + + ESP32 v3.0 和 ESP32-S2 的安全启动请参阅 :doc:`secure-boot-v2`。 + +安全启动功能用于确保芯片上仅运行签名后的代码，每次系统重置都会验证从 flash 加载的数据。 + +安全启动功能独立于 :doc:`flash-encryption` 功能，可以在不加密 flash 内容的情况下使用。然而，为确保使用环境安全，建议同时启用安全启动和 flash 加密功能。详情请参阅 :ref:`secure-boot-and-flash-encr`。 + +.. important:: + + 启用安全启动将限制进一步更新 {IDF_TARGET_NAME}。请仔细阅读本文档，了解启用安全启动的影响。 + + +背景信息 +---------- + +- 大部分数据存储在 flash 中，关键数据存储在芯片内部的 eFuse 中，无法通过软件访问。因此，为确保安全启动正常运行，无需额外对 flash 访问进行物理保护。 + +- eFuse 用于永久存储安全引导信息，安全引导密钥存放在 eFuse BLOCK2 中。单个 eFuse 位 ABS_DONE_0 也会进行烧录或写入 1，保持芯片上的安全启动始终启用。有关 eFuse 的更多内容，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (EFUSE)* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。 + +- 为理解安全启动过程，请熟悉标准 :doc:`../api-guides/startup`。 + +- 安全启动过程会验证启动过程的两个阶段，包括初始软件引导加载程序和随后的分区与应用加载，形成一条信任链。 + + +安全启动过程概述 +---------------------------- + +以下是对安全启动过程的宏观概述，操作指南请参阅 :ref:`secure-boot-how-to`，进一步的技术细节请参阅 :ref:`secure-boot-technical-details`： + +1. 启用安全启动的选项可以在 ``Secure Boot Configuration`` 下的 :ref:`project-configuration-menu` 中找到。 + +2. 安全启动默认在构建过程中签名镜像和分区表数据。配置项 ``Secure boot private signing key`` 是指向 PEM 格式文件中 ECDSA 公钥/私钥对的文件路径。 + +3. 启用安全启动支持的 ESP-IDF 负责构建软件引导加载程序镜像，签名验证所需公钥已集成到引导加载程序镜像中。此软件引导加载程序镜像将刷写到 0x1000 偏移地址。 + +4. 初次启动时，软件引导加载程序按以下方式启用安全启动： + + - 硬件安全启动支持生成设备安全引导加载程序密钥以及安全摘要。密钥借助硬件随机数生成，随后存储在 eFuse 中，受读写保护。硬件安全启动还支持生成安全摘要，摘要源自密钥、初始向量 (IV) 和引导加载程序镜像内容。 + - 安全摘要将刷写到 flash 中的 0x0 偏移地址。 + - 根据安全启动配置，烧录 eFuse 以禁用 JTAG 和 ROM 基本解释器。**强烈建议** 禁用 JTAG 和 ROM 基本解释器。 + - 烧录 ABS_DONE_0 eFuse 后，引导加载程序将始终启用安全启动，软件引导加载程序也随之受到保护。此后，芯片只有在摘要匹配时才会启动引导加载程序镜像。 + +5. 在后续启动过程中，ROM 引导加载程序检测到安全启动 eFuse 已烧录，读取 0x0 处保存的摘要，然后使用硬件安全启动支持来将其与新计算的摘要进行对比。如果摘要不匹配，启动过程终止。摘要读取和对比完全由硬件完成，软件无法读取计算的摘要。更多技术详情，请参阅 :ref:`secure-boot-hardware-support`。 + +6. 在安全启动模式下运行时，软件引导加载程序使用安全启动签名密钥，该密钥的公钥已嵌入引导加载程序本身，并作为引导加载程序的一部分进行验证，以在启动前验证附加到所有后续分区表和应用程序镜像的签名。 + + +密钥 +---- + +安全启动过程中使用以下密钥： + +- 安全引导加载程序密钥是一个 256 位 AES 密钥，存储在 eFuse 块 2 中。引导加载程序可以使用内部硬件随机数生成器自行生成该密钥，无需手动提供。也可以选择提供该密钥，请参阅 :ref:`secure-boot-reflashable`。在启用安全启动之前，存储该密钥的 eFuse 受到读取和写入保护，防止软件访问。 + + - eFuse 块 2 默认编码方案为 ``None``，块中存储了一个 256 位密钥。在某些版本的 {IDF_TARGET_NAME} 上，编码方案设置为 ``3/4 Encoding``，CODING_SCHEME eFuse 值为 1，且块中必须存储一个 192 位密钥。 + + .. only:: esp32 + + 详情请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (EFUSE)* > *系统参数 coding_scheme* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]. + + 算法始终使用 256 位密钥进行操作。对于 192 位密钥，则通过重复某些位来将其扩展至 256 位，请参阅 :ref:`secure-bootloader-digest-algorithm`。 + +- ``secure boot signing key`` 是标准的 ECDSA 公钥/私钥对，以 PEM 格式存储，请参阅 :ref:`secure-boot-image-signing-algorithm`。 + + - 该密钥对的公钥用于验证签名，但不用于创建签名。它编译到软件引导加载程序中，并在启动继续前验证启动过程的第二阶段，包括分区表和应用程序镜像。该公钥可以自由分发，无需保密。 + + - 该密钥对的私钥必须严格保密。一旦持有该私钥，即可用它对配置了安全启动和匹配公钥的引导加载程序进行身份验证。 + + +引导加载程序大小 +------------------- + +启用安全启动和/或 flash 加密都会增加引导加载程序的大小，因此可能需要更新分区表偏移量，请参阅 :ref:`bootloader-size`。 + + +.. _secure-boot-how-to: + +启用安全启动 +------------------------- + +1. 打开 :ref:`project-configuration-menu`，在 ``Secure Boot Configuration`` 中选择 ``One-time Flash`` 选项。如果要了解备选的 ``Reflashable`` 选项，请参阅 :ref:`secure-boot-reflashable`。 + +2. 为安全启动签名密钥选择名称。此选项将在启用安全启动后出现，密钥文件可以存放在系统的任何位置。如果使用相对路径，系统将基于项目目录确认该路径指向的实际位置。注意，无需在命名前准备好密钥文件。 + +3. 根据需要设置其他 menuconfig 选项。需注意，``Bootloader Config`` 选项对应的引导加载程序仅支持烧录一次。随后，退出 menuconfig 并保存配置。 + +4. 初次运行 ``idf.py build`` 时，如果找不到签名密钥，将打印错误信息，并提供一个通过 ``espsecure.py generate_signing_key`` 生成签名密钥的命令。 + +.. important:: + + 由此方法生成的签名密钥将使用操作系统及其 Python 安装中提供的最佳随机数源，在 OSX/Linux 上为 `/dev/urandom`，在 Windows 上为 `CryptGenRandom()`。此随机数源的安全性将会直接影响私钥的强度。 + +.. important:: + + 在生产环境下，建议使用 OpenSSL 或其他行业标准的加密程序生成密钥对，详情请参阅 :ref:`secure-boot-generate-key`。 + +5. 运行 ``idf.py bootloader`` 构建启用了安全启动的引导加载程序，构建输出中包含一个使用 ``esptool.py write_flash`` 烧录命令的提示。 + +.. _secure-boot-resume-normal-flashing: + +6. 准备就绪后，运行上述命令并等待烧录完成。注意，此处的指定命令需要手动输入，构建系统不会执行此过程。**注意，完成该一次性烧录后，不支持再对引导加载程序进行任何修改**。 + +7. 运行 ``idf.py flash`` 构建并烧录分区表和刚刚构建的应用程序镜像。应用程序镜像将使用在步骤 4 中生成的签名密钥签名。 + +.. note:: + + 如果启用了安全启动，``idf.py flash`` 不会烧录引导加载程序。 + +8. 重置 {IDF_TARGET_NAME} 以启动烧录的软件引导加载程序。该软件引导加载程序会在芯片上启用安全启动，验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。 + +.. note:: + + 为避免在系统配置完成前发生意外情况，仅当有效的分区表和应用程序镜像烧录成功后，才会启用安全启动。 + +.. note:: + + 如果在初次启动过程中重置或关闭了 {IDF_TARGET_NAME}，它会在下次启动时重新开始上述步骤。 + +9. 在后续启动过程中，安全启动硬件将使用安全引导加载程序密钥验证软件引导加载程序是否更改，随后，软件引导加载程序将使用安全启动签名密钥的公钥部分来验证已签名的分区表和应用程序镜像。 + + +.. _secure-boot-reflashable: + +可重复烧录的软件引导加载程序 +------------------------------- + +对于生产设备，推荐使用 ``Secure Boot: One-Time Flash`` 配置。该模式下，每个设备都对应拥有始终存储在设备内部的唯一密钥。 + +除上述配置外，也可选择 :ref:`CONFIG_SECURE_BOOTLOADER_MODE` 模式。在该备选模式下，可以提供一个二进制密钥文件作为安全引导加载程序密钥。此时，可以生成新的引导加载程序镜像，并为这些镜像生成安全启动摘要。 + +在 ESP-IDF 构建过程中，该 256 位密钥文件派生自用户生成的 ECDSA 应用程序签名密钥，请参阅下文的 :ref:`secure-boot-generate-key` 步骤。该私钥的 SHA-256 摘要用作 eFuse 中的安全引导加载程序密钥，如果编码方案为 ``None``，则使用完整的 256 位密钥；如果编码方案为 ``3/4 Encoding``，则将密钥截断为 192 字节。这样一来，只需要生成或保护单个密钥文件。 + +.. note:: + + 尽管该方案可行，但在生产环境中，强烈建议不要仅生成一个安全引导加载程序密钥并将其烧录到每个设备上。推荐使用 ``One-Time Flash`` 选项。 + +请按以下步骤启用可重复烧录的引导加载程序： + +1. 在 :ref:`project-configuration-menu` 中，选择 ``Bootloader Config`` > :ref:`CONFIG_SECURE_BOOT` > ``CONFIG_SECURE_BOOT_V1_ENABLED`` > :ref:`CONFIG_SECURE_BOOTLOADER_MODE` > ``Reflashable``。 + +2. 如有需要，按照设备使用的编码方案设置 :ref:`CONFIG_SECURE_BOOTLOADER_KEY_ENCODING`。编码方案将在 ``esptool.py`` 连接到芯片时显示在 ``Features`` 行中，或在 ``espefuse.py summary`` 输出中显示。 + +3. 请按 :ref:`secure-boot-generate-key` 中的步骤生成签名密钥。生成的密钥文件路径必须在 ``Secure Boot Configuration`` 菜单中指定。 + +4. 运行 ``idf.py bootloader`` 将创建一个二进制密钥文件，该文件派生自用于签名的私钥。同时将打印两组烧录步骤。第一组步骤包括一个 ``espefuse.py burn_key secure_boot_v1 path_to/secure-bootloader-key-xxx.bin`` 命令，用于将引导加载程序密钥写入 eFuse，此密钥仅可烧录一次。第二组步骤可使用预计算的摘要重新烧录引导加载程序，该摘要在构建过程中生成。 + +5. 从 :ref:`一次性烧录步骤 6 ` 继续，烧录引导加载程序并启用安全启动。请密切监视控制器日志输出，确保安全启动配置正确无误。 + + +.. _secure-boot-generate-key: + +生成安全启动签名密钥 +---------------------------------- + +构建系统将提供一个命令，用于通过 ``espsecure.py generate_signing_key`` 生成新的签名密钥。这个命令使用 python-ecdsa 库，而该库则使用 Python 的 ``os.urandom()`` 作为随机数源。 + +签名密钥的强度取决于系统的随机数源和所用算法的正确性。对于生产设备，建议从具有高质量熵源的系统生成签名密钥，并使用最佳的可用 EC 密钥生成工具。 + +例如，可以采用以下 OpenSSL 命令行生成签名密钥： + +.. code-block:: + + openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem + +注意，安全启动系统的强度取决于能否保持签名密钥的私密性。 + + +.. _remote-sign-image: + +远程镜像签名 +------------------------ + +生产构建中，建议使用远程签名服务器，而非将签名密钥存储在构建机器上，这也是默认的 ESP-IDF 安全启动配置。可以使用命令行工具 ``espsecure.py`` 在远程系统上为应用程序镜像和分区表数据签名，供安全启动使用。 + +使用远程签名时，请禁用选项 ``Sign binaries during build``。此时，签名私钥无需存在于构建系统，但签名公钥必须存在，它会编译到引导加载程序中，并在 OTA 更新期间验证镜像签名。 + +可以采用以下命令从私钥中提取公钥： + +.. code-block:: + + espsecure.py extract_public_key --keyfile PRIVATE_SIGNING_KEY PUBLIC_VERIFICATION_KEY + +请在 ``Secure boot public signature verification key`` 下的 menuconfig 中指定公共签名验证密钥的路径，构建安全引导加载程序。 + +构建完应用程序镜像和分区表后，构建系统会使用 ``espsecure.py`` 打印签名步骤： + +.. code-block:: + + espsecure.py sign_data --keyfile PRIVATE_SIGNING_KEY BINARY_FILE + +上述命令将镜像签名附加到现有的二进制文件中，可以使用 `--output` 参数将签名后的二进制文件写入单独的文件： + +.. code-block:: + + espsecure.py sign_data --keyfile PRIVATE_SIGNING_KEY --output SIGNED_BINARY_FILE BINARY_FILE + + +使用安全启动的建议 +-------------------------- + +* 在具备高质量熵源的系统上生成签名密钥。 +* 时刻对签名密钥保密，泄漏此密钥将危及安全启动系统。 +* 不允许第三方查看 ``espsecure.py`` 进行密钥生成或签名过程的任何细节，因为这样容易受到定时或其他侧信道攻击的威胁。 +* 在安全启动配置中启用所有安全启动选项，包括 flash 加密、禁用 JTAG、禁用 BASIC ROM 解释器和禁用 UART 引导加载程序的加密 flash 访问。 +* 结合 :doc:`flash-encryption` 使用安全启动，防止本地读取 flash 内容。 + + +.. _secure-boot-technical-details: + +技术细节 +----------------- + +以下小节包含安全启动元件的详细参考描述： + + +.. _secure-boot-hardware-support: + +安全启动硬件支持 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +安全启动验证的第一阶段为检查软件引导加载程序，该检查通过硬件完成。{IDF_TARGET_NAME} 的安全启动支持硬件提供以下三种基本操作： + +1. 通过硬件随机数生成器生成一系列随机字节。 + +2. 使用存储在 eFuse 块 2 中的密钥生成数据摘要，通常是从 flash 中提取的引导加载程序镜像。eFuse 中的密钥可以且应设置为读取和写入保护，防止软件访问。有关此算法的完整详细信息，请参阅 `安全引导加载程序摘要算法`_。只有在 eFuse ABS_DONE_0 **未** 烧录，即仍为 0 时，才能通过软件读取摘要。 + +3. 使用与步骤 2 相同的算法从数据中生成摘要，该数据通常是从 flash 中提取的引导加载程序镜像，然后比较生成的摘要与 buffer 中提供的预计算摘要，预计算摘要通常从 flash 偏移 0x0 处读取。硬件返回一个 true/false 的比较结果，无需向软件提供摘要。即使 eFuse ABS_DONE_0 已经烧录，此功能依旧可用。 + + +.. _secure-bootloader-digest-algorithm: + +安全引导加载程序摘要算法 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +输入二进制数据镜像，该算法会生成并输出摘要 (digest)，此摘要在硬件文档中有时也称摘要 (abstract)。 + +请前往 :component:`/esptool_py` 目录，查看 ``espsecure.py`` 工具，了解算法使用的 Python 版本。具体而言，请查看 ``digest_secure_bootloader`` 命令。 + +以下带有 (^) 标记的项目用于满足硬件限制，而非密码学限制。 + +1. 以反向字节顺序从 eFuse 块 2 中读取 AES 密钥。如果编码方案设置为 ``3/4 Encoding``，请使用与 :ref:`flash-encryption-algorithm` 中描述的算法相同的算法，将 192 位密钥扩展到 256 位。 +2. 给镜像添加 128 位随机生成的 IV 前缀。 +3. 如果镜像长度不是 128 的倍数，则使用 0xFF 将镜像填充至恰为 128 字节的倍数。(^) +4. 对于输入镜像的每个 16 字节明文块： + + - 反转明文输入块的字节顺序。(^) + - 将 AES256 以 ECB 模式应用于明文块。 + - 反转密文输出块的字节顺序。(^) + - 将其追加到总体密文输出。 + +5. 对密文中的每个 4 字节字进行字节交换。(^) +6. 计算密文的 SHA-512 摘要。 +7. 对上述计算得到的摘要中的每个 4 字节字进行字节交换。(^) + +输出摘要为 192 字节的数据：128 字节的 IV，后跟 64 字节的 SHA-512 摘要。 + + +.. _secure-boot-image-signing-algorithm: + +镜像签名算法 +~~~~~~~~~~~~~~~~~~~~~~~ + +按照 `RFC 6979 `_ 中的规定，指定确定性的 ECDSA。 + +- 使用 NIST256p 曲线。OpenSSL 将此曲线称为 prime256v1，有时也称 secp256r1。 +- 哈希函数采用 SHA256。 +- 用于存储的密钥格式为 PEM。 + + - 在引导加载程序中，用于签名签证的公钥作为 64 个原始字节烧录。 + +- 镜像签名为 68 字节：4 字节的版本号（当前为 0），后跟 64 字节的签名数据。这 68 字节会添加到应用程序镜像或分区表数据末尾。 + + +手动命令 +~~~~~~~~~~~~~~~ + +安全启动已集成到 ESP-IDF 构建系统中，因此若启用了安全启动，``idf.py build`` 将自动签名应用程序镜像。如果 menuconfig 配置了相应选项，``idf.py bootloader`` 将生成引导加载程序摘要。 + +然而，也可以使用 ``espsecure.py`` 工具生成独立的签名和摘要。 + +可以使用以下命令进行二进制镜像签名： + +.. code-block:: + + espsecure.py sign_data --keyfile ./my_signing_key.pem --output ./image_signed.bin image-unsigned.bin + +keyfile 是包含 ECDSA 签名私钥的 PEM 文件。 + +可以使用以下命令生成引导加载程序摘要： + +.. code-block:: + + espsecure.py digest_secure_bootloader --keyfile ./securebootkey.bin --output ./bootloader-digest.bin build/bootloader/bootloader.bin + +keyfile 是设备的 32 字节原始安全启动密钥。 + +``espsecure.py digest_secure_bootloader`` 命令的输出是一个包含摘要和附加的引导加载程序的独立文件。可以使用以下命令将合并的摘要和引导加载程序烧录到设备上： + +.. code-block:: + + esptool.py write_flash 0x0 bootloader-digest.bin + + +.. _secure-boot-and-flash-encr: + +安全启动 & flash 加密 +------------------------------ + +如果使用安全启动时没有启用 :doc:`flash-encryption`，可能会发生 ``time-of-check to time-of-use`` 攻击，即在验证并运行镜像后交换 flash 内容。因此，建议同时使用这两个功能。 + + +.. _signed-app-verify: + +在未启用硬件安全启动时验证已签名的应用程序 +---------------------------------------------------- + +即使没有启用硬件安全启动选项，也可以检查应用程序的完整性。这种方法使用与硬件安全启动相同的应用程序签名方案，但与硬件安全启动不同的是，它不会阻止引导加载程序的物理更新。这意味着设备可以防止远程网络访问，但无法阻止物理访问。与使用硬件安全启动相比，不使用硬件安全启动更加简单。具体操作请参阅 :ref:`signed-app-verify-how-to`。 + +应用程序可以在更新时验证，也可以在启动时验证。 + +- 更新时验证：启用此选项后，每当使用 ``esp_ota_ops.h`` API 执行 OTA 更新，系统都会自动检查签名。如果启用硬件安全启动，则此选项保持启用且无法禁用。如果未启用硬件安全启动，仍然可以通过启用此选项更好地防护网络攻击，防止伪造 OTA 更新。 + +- 启动时验证：启用此选项后，引导加载程序会编译代码，验证应用程序在启动前是否已签名。如果启用硬件安全启动，则此选项保持启用且无法禁用。如果未启用安全启动，该选项本身无法更好地防护网络攻击，因此多数用户会保持禁用该选项。 + + +.. _signed-app-verify-how-to: + +启用已签名的应用程序验证 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +1. 打开 :ref:`project-configuration-menu` > ``Security features`` > 启用 :ref:`CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT`。 + +2. 启用 ``Bootloader verifies app signatures``，在启动时验证应用程序。 + +3. 默认情况下，选择 ``Require signed app images`` 选项将启用 ``Sign binaries during build`` 功能，该功能会在构建过程中对二进制文件签名。在 ``Secure boot private signing key`` 中指定的文件将用于镜像签名。 + +4. 如果禁用了 ``Sign binaries during build`` 选项，则需要在 ``Secure boot public signature verification key`` 中输入用于验证已签名图像的公钥文件路径。 + + 此时，私钥应按照 :ref:`secure-boot-generate-key` 中的说明生成；公钥验证密钥和已签名镜像应按照 :ref:`remote-sign-image` 中的说明生成。 + + +进阶功能 +----------------- + +JTAG 调试 +~~~~~~~~~~~~~~ + +启用安全启动模式时，eFuse 会默认禁用 JTAG。初次启动时，引导加载程序即禁用 JTAG 调试功能，并启用安全启动模式。 + +有关在启用安全启动或已签名应用程序验证的情况下使用 JTAG 调试的更多信息，请参阅 :ref:`jtag-debugging-security-features`。 diff --git a/docs/zh_CN/security/security.rst b/docs/zh_CN/security/security.rst index f92ea3de53b..06edea83878 100644 --- a/docs/zh_CN/security/security.rst +++ b/docs/zh_CN/security/security.rst @@ -1,6 +1,10 @@ 安全 ==== +{IDF_TARGET_CIPHER_SCHEME:default="RSA", esp32h2="RSA 或 ECDSA", esp32p4="RSA 或 ECDSA"} + +{IDF_TARGET_SIG_PERI:default="DS", esp32h2="DS 或 ECDSA", esp32p4="DS 或 ECDSA"} + :link_to_translation:`en:[English]` 本指南概述了乐鑫解决方案中可用的整体安全功能。从 **安全** 角度考虑，强烈建议在使用乐鑫平台和 ESP-IDF 软件栈设计产品时参考本指南。 @@ -73,9 +77,19 @@ flash 加密最佳实践 在 {IDF_TARGET_NAME} 中，数字签名外设借助硬件加速，通过 HMAC 算法生成 RSA 数字签名。RSA 私钥仅限设备硬件访问，软件无法获取，保证了设备上存储密钥的安全性。 - 数字签名外设可以建立与远程终端之间的 **安全设备身份**，如基于 RSA 加密算法的 TLS 双向认证。 + .. only:: SOC_ECDSA_SUPPORTED + + {IDF_TARGET_NAME} 还支持 ECDSA 外设，用于生成硬件加速的 ECDSA 数字签名。ECDSA 私钥支持直接编程到 eFuse 块中，并在软件中标记为读保护。 + + {IDF_TARGET_SIG_PERI} 外设可以建立与远程终端之间的 **安全设备身份**，如基于 {IDF_TARGET_CIPHER_SCHEME} 加密算法的 TLS 双向认证。 + + .. only:: not SOC_ECDSA_SUPPORTED - 更多详情请参阅 :doc:`../api-reference/peripherals/ds`。 + 详情请参阅 :doc:`../api-reference/peripherals/ds`。 + + .. only:: SOC_ECDSA_SUPPORTED + + 详情请参阅 :doc:`../api-reference/peripherals/ecdsa` 及 :doc:`../api-reference/peripherals/ds`。 .. only:: SOC_MEMPROT_SUPPORTED or SOC_CPU_IDRAM_SPLIT_USING_PMP @@ -177,21 +191,40 @@ UART 下载模式 强烈建议基于 X.509 证书验证服务器身份，谨防与 **伪造** 服务器建立通信。 + 根证书管理 + ^^^^^^^^^^^^^ + + 内嵌在应用程序内的根证书必须谨慎管理。更新根证书列表或 :doc:`../api-reference/protocols/esp_crt_bundle` 都可能影响与远程端点的 TLS 连接，包括与 OTA 更新服务器的连接。在某些情况下，此类问题可能会在后续 OTA 更新中出现，导致设备永远无法进行 OTA 更新。 + + 根证书列表更新可能出于以下原因： + + - 新固件的远程端点不同。 + - 现有证书过期。 + - 证书已从上游证书包中添加或撤销。 + - 市场份额统计数据的变化引起证书列表的变化（``CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN`` 情况）。 + + 其他相关建议： + + - 请考虑启用 :ref:`ota_rollback`，将成功连接至 OTA 更新服务器作为取消回滚过程的检查点，从而确保更新后的固件成功连接至 OTA 更新服务器。否则，回滚过程将导致设备回退到之前的固件版本。 + - 如果计划启用 :ref:`CONFIG_MBEDTLS_HAVE_TIME_DATE` 选项，请确保具备时间同步机制 (SNTP) 和足够的受信任证书。 + 产品安全 ---------------- -安全配网 -~~~~~~~~~~~~~~~~~~~ +.. only:: SOC_WIFI_SUPPORTED -安全配网是指将 ESP 设备安全接入 Wi-Fi 网络的过程。该机制还支持在初始配网阶段从配网实体（如智能手机等）获取额外的自定义配置数据。 + 安全配网 + ~~~~~~~~~~~~~~~~~~~ -ESP-IDF 提供了多种安全方案，可以在 ESP 设备和配网实体之间建立安全会话，具体方案请参阅 :ref:`provisioning_security_schemes`。 + 安全配网是指将 ESP 设备安全接入 Wi-Fi 网络的过程。该机制还支持在初始配网阶段从配网实体（如智能手机等）获取额外的自定义配置数据。 -关于该功能的更多详情和代码示例，请参阅 :doc:`../api-reference/provisioning/wifi_provisioning`。 + ESP-IDF 提供了多种安全方案，可以在 ESP 设备和配网实体之间建立安全会话，具体方案请参阅 :ref:`provisioning_security_schemes`。 -.. note:: + 关于该功能的更多详情和代码示例，请参阅 :doc:`../api-reference/provisioning/wifi_provisioning`。 + + .. note:: - 乐鑫提供了 Android 和 iOS 手机应用程序及其源代码，以便进一步根据产品需求定制安全配网方案。 + 乐鑫提供了 Android 和 iOS 手机应用程序及其源代码，以便进一步根据产品需求定制安全配网方案。 安全 OTA 更新 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml index 279c3bed760..4917e5c5fca 100644 --- a/examples/bluetooth/.build-test-rules.yml +++ b/examples/bluetooth/.build-test-rules.yml @@ -42,10 +42,10 @@ examples/bluetooth/bluedroid/classic_bt: - esp_console - vfs - esp_driver_gpio + - esp_driver_i2s + - esp_driver_uart depends_filepatterns: - components/driver/dac/**/* - - components/driver/i2s/**/* - - components/driver/uart/**/* examples/bluetooth/bluedroid/coex/a2dp_gatts_coex: <<: *bt_default_depends @@ -53,9 +53,10 @@ examples/bluetooth/bluedroid/coex/a2dp_gatts_coex: - if: IDF_TARGET != "esp32" temporary: true reason: the other targets are not tested yet + depends_components: + - esp_driver_i2s depends_filepatterns: - components/driver/dac/**/* - - components/driver/i2s/**/* examples/bluetooth/blufi: disable: @@ -103,24 +104,6 @@ examples/bluetooth/esp_ble_mesh/aligenie_demo: depends_filepatterns: - examples/bluetooth/esp_ble_mesh/common_components/**/* -examples/bluetooth/esp_ble_mesh/coex_test: - enable: - - if: IDF_TARGET in ["esp32"] - temporary: true - reason: the other targets are not tested yet - depends_components: - - bt - - esp_phy - - esp_console - - vfs - - mbedtls - - esp_coex - - esp_wifi - - esp_netif - - esp_driver_gpio - depends_filepatterns: - - examples/bluetooth/esp_ble_mesh/common_components/**/* - examples/bluetooth/esp_ble_mesh/wifi_coexist: disable: - if: SOC_BLE_MESH_SUPPORTED != 1 @@ -151,15 +134,15 @@ examples/bluetooth/hci/controller_hci_uart_esp32: <<: *bt_default_depends enable: - if: IDF_TARGET == "esp32" - depends_filepatterns: - - components/driver/uart/**/* + depends_components: + - esp_driver_uart examples/bluetooth/hci/controller_hci_uart_esp32c3_and_esp32s3: <<: *bt_default_depends enable: - if: IDF_TARGET in ["esp32c3", "esp32s3"] - depends_filepatterns: - - components/driver/uart/**/* + depends_components: + - esp_driver_uart # config BT_NIMBLE_ENABLED does not depends on any soc cap @@ -273,7 +256,7 @@ examples/bluetooth/nimble/throughput_app: - if: SOC_BLE_SUPPORTED != 1 depends_components: - esp_driver_gpio + - esp_driver_uart depends_filepatterns: - examples/bluetooth/nimble/common/**/* - examples/bluetooth/nimble/throughput_app/blecent_throughput/components/**/* - - components/driver/uart/**/* diff --git a/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/main/ble_compatibility_test.c b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/main/ble_compatibility_test.c index 5b6d092c73b..a0102ab1bcd 100644 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/main/ble_compatibility_test.c +++ b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/main/ble_compatibility_test.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -393,20 +393,21 @@ void example_prepare_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t { EXAMPLE_DEBUG(EXAMPLE_TAG, "prepare write, handle = %d, value len = %d", param->write.handle, param->write.len); esp_gatt_status_t status = ESP_GATT_OK; - if (prepare_write_env->prepare_buf == NULL) { + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE * sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(EXAMPLE_TAG, "%s, Gatt_server prep no mem", __func__); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } + /*send response when param->write.need_rsp is true */ if (param->write.need_rsp){ esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults index 8676c818a38..e580bb15298 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults @@ -4,6 +4,7 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n CONFIG_GATTS_NOTIFY_THROUGHPUT=y CONFIG_GATTC_WRITE_THROUGHPUT=n diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/main/example_ble_server_throughput.c b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/main/example_ble_server_throughput.c index 8747c5b316a..ceebe06f3b7 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/main/example_ble_server_throughput.c +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/main/example_ble_server_throughput.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -280,20 +280,19 @@ void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t *prepare esp_gatt_status_t status = ESP_GATT_OK; if (param->write.need_rsp) { if (param->write.is_prep) { - if (prepare_write_env->prepare_buf == NULL) { + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE * sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(GATTS_TAG, "Gatt_server prep no mem"); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE || - prepare_write_env->prepare_len > param->write.offset) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults index 58af7f81e68..1decbd1f1d6 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults @@ -6,4 +6,5 @@ CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c b/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c index 6b6bb9f4086..18d2cc7aced 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c +++ b/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c @@ -242,20 +242,19 @@ static void gap_event_handler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t *prepare_write_env, esp_ble_gatts_cb_param_t *param){ esp_gatt_status_t status = ESP_GATT_OK; if (param->write.need_rsp){ - if (param->write.is_prep){ - if (prepare_write_env->prepare_buf == NULL) { + if (param->write.is_prep) { + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE*sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(GATTS_TAG, "Gatt_server prep no mem"); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/tutorial/Gatt_Server_Example_Walkthrough.md b/examples/bluetooth/bluedroid/ble/gatt_server/tutorial/Gatt_Server_Example_Walkthrough.md index 2f6aa348b64..2de00d434b6 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/tutorial/Gatt_Server_Example_Walkthrough.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server/tutorial/Gatt_Server_Example_Walkthrough.md @@ -772,35 +772,37 @@ The `example_write_event_env()` function contains the logic for the write long c void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t *prepare_write_env, esp_ble_gatts_cb_param_t *param){ esp_gatt_status_t status = ESP_GATT_OK; if (param->write.need_rsp){ - if (param->write.is_prep){ - if (prepare_write_env->prepare_buf == NULL){ + if (param->write.is_prep) { + if(param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE*sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(GATTS_TAG, "Gatt_server prep no mem"); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } - else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); - gatt_rsp->attr_value.len = param->write.len; - gatt_rsp->attr_value.handle = param->write.handle; - gatt_rsp->attr_value.offset = param->write.offset; - gatt_rsp->attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; - memcpy(gatt_rsp->attr_value.value, param->write.value, param->write.len); - esp_err_t response_err = esp_ble_gatts_send_response(gatts_if, param->write.conn_id, - param->write.trans_id, status, gatt_rsp); - if (response_err != ESP_OK){ - ESP_LOGE(GATTS_TAG, "Send response error"); + if (gatt_rsp) { + gatt_rsp->attr_value.len = param->write.len; + gatt_rsp->attr_value.handle = param->write.handle; + gatt_rsp->attr_value.offset = param->write.offset; + gatt_rsp->attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; + memcpy(gatt_rsp->attr_value.value, param->write.value, param->write.len); + esp_err_t response_err = esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, gatt_rsp); + if (response_err != ESP_OK) { + ESP_LOGE(GATTS_TAG, "Send response error\n"); + } + free(gatt_rsp); + } else { + ESP_LOGE(GATTS_TAG, "malloc failed, no resource to send response error\n"); + status = ESP_GATT_NO_RESOURCES; } - free(gatt_rsp); if (status != ESP_GATT_OK){ return; } @@ -809,7 +811,7 @@ void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t *prepare param->write.len); prepare_write_env->prepare_len += param->write.len; - }else{ + } else { esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, NULL); } } @@ -830,9 +832,9 @@ The function then checks if the Prepare Write Request parameter represented by t ```c … -if (param->write.is_prep){ +if (param->write.is_prep) { … -}else{ +} else { esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, NULL); } … @@ -852,7 +854,7 @@ static prepare_type_env_t b_prepare_write_env; In order to use the prepare buffer, some memory space is allocated for it. In case the allocation fails due to a lack of memory, an error is printed: ```c -if (prepare_write_env->prepare_buf == NULL) { +if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t*)malloc(PREPARE_BUF_MAX_SIZE*sizeof(uint8_t)); prepare_write_env->prepare_len = 0; diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/main/gatts_table_creat_demo.c b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/main/gatts_table_creat_demo.c index 982927ef3bd..4bd81ddef2e 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/main/gatts_table_creat_demo.c +++ b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/main/gatts_table_creat_demo.c @@ -281,20 +281,20 @@ void example_prepare_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t { ESP_LOGI(GATTS_TABLE_TAG, "prepare write, handle = %d, value len = %d", param->write.handle, param->write.len); esp_gatt_status_t status = ESP_GATT_OK; - if (prepare_write_env->prepare_buf == NULL) { + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE * sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(GATTS_TABLE_TAG, "%s, Gatt_server prep no mem", __func__); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } + /*send response when param->write.need_rsp is true */ if (param->write.need_rsp){ esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); @@ -305,7 +305,7 @@ void example_prepare_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t gatt_rsp->attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; memcpy(gatt_rsp->attr_value.value, param->write.value, param->write.len); esp_err_t response_err = esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, gatt_rsp); - if (response_err != ESP_OK){ + if (response_err != ESP_OK) { ESP_LOGE(GATTS_TABLE_TAG, "Send response error"); } free(gatt_rsp); @@ -403,6 +403,11 @@ static void gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_ { indicate_data[i] = i % 0xff; } + + // if want to change the value in server database, call: + // esp_ble_gatts_set_attr_value(heart_rate_handle_table[IDX_CHAR_VAL_A], sizeof(indicate_data), indicate_data); + + //the size of indicate_data[] need less than MTU size esp_ble_gatts_send_indicate(gatts_if, param->write.conn_id, heart_rate_handle_table[IDX_CHAR_VAL_A], sizeof(indicate_data), indicate_data, true); diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/tutorial/Gatt_Server_Service_Table_Example_Walkthrough.md b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/tutorial/Gatt_Server_Service_Table_Example_Walkthrough.md index 7db332db2a0..623043e7132 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/tutorial/Gatt_Server_Service_Table_Example_Walkthrough.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/tutorial/Gatt_Server_Service_Table_Example_Walkthrough.md @@ -159,6 +159,7 @@ The application registration takes place inside ``app_main()`` using the ``esp_b ```c esp_ble_gatts_app_register(ESP_HEART_RATE_APP_ID); ``` +The ``ESP_HEART_RATE_APP_ID`` serves as an application ID, distinguishing between various application layer callbacks. This identifier corresponds to the ``app_id`` found within the ``gatts_reg_evt_param`` in ESP_GATTS_REG_EVT. ## Setting GAP Parameters diff --git a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/tutorial/Periodic_Sync_Example_Walkthrough.md b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/tutorial/Periodic_Sync_Example_Walkthrough.md index bba00bb45a9..ab9e3740788 100644 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/tutorial/Periodic_Sync_Example_Walkthrough.md +++ b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/tutorial/Periodic_Sync_Example_Walkthrough.md @@ -241,13 +241,22 @@ same for the periodic sync: * @brief periodic adv sync parameters */ typedef struct { - esp_ble_gap_sync_t filter_policy; /*!< periodic advertising sync filter policy */ - uint8_t sid; /*!< periodic advertising sid */ - esp_ble_addr_type_t addr_type; /*!< periodic advertising address type */ - esp_bd_addr_t addr; /*!< periodic advertising address */ - uint16_t skip; /*!< the maximum number of periodic advertising events t -hat can be skipped */ - uint16_t sync_timeout; /*!< synchronization timeout */ + esp_ble_gap_sync_t filter_policy; /*!< Configures the filter policy for periodic advertising sync: + 0: Use Advertising SID, Advertiser Address Type, and Advertiser Address parameters to determine the advertiser to listen to. + 1: Use the Periodic Advertiser List to determine the advertiser to listen to. */ + #if (BLE_FEAT_CREATE_SYNC_ENH) + esp_ble_gap_sync_t reports_disabled; /*!< Supported only by esp32c2, esp32c6, and esp32h2; can be set by menuconfig: + 0: Reporting initially enabled. + 1: Reporting initially disabled. */ + esp_ble_gap_sync_t filter_duplicates; /*!< Supported only by esp32c2, esp32c6, and esp32h2; can be set by menuconfig: + 0: Duplicate filtering initially disabled. + 1: Duplicate filtering initially enabled. */ + #endif + uint8_t sid; /*!< SID of the periodic advertising */ + esp_ble_addr_type_t addr_type; /*!< Address type of the periodic advertising */ + esp_bd_addr_t addr; /*!< Address of the periodic advertising */ + uint16_t skip; /*!< Maximum number of periodic advertising events that can be skipped */ + uint16_t sync_timeout; /*!< Synchronization timeout */ } esp_ble_gap_periodic_adv_sync_params_t; ``` diff --git a/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/CMakeLists.txt b/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/CMakeLists.txt index c34ea69578b..e68a065139b 100644 --- a/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/CMakeLists.txt +++ b/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/CMakeLists.txt @@ -1,4 +1,5 @@ idf_component_register(SRCS "bt_app_av.c" "bt_app_core.c" "main.c" + PRIV_REQUIRES esp_driver_i2s bt nvs_flash esp_ringbuf esp_driver_dac INCLUDE_DIRS ".") diff --git a/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_core.c b/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_core.c index 29ce385feb1..29c915e893e 100644 --- a/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_core.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_client/main/bt_app_core.c b/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_client/main/bt_app_core.c index 58b22dddea4..89354ac8600 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_client/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_client/main/bt_app_core.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_server/main/bt_app_core.c b/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_server/main/bt_app_core.c index 58b22dddea4..89354ac8600 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_server/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_l2cap_server/main/bt_app_core.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_acceptor/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/bt_spp_acceptor/sdkconfig.defaults index 1974e0e8cb5..ce7f5a4cd4e 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_acceptor/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_acceptor/sdkconfig.defaults @@ -1,10 +1,8 @@ # Override some defaults so BT stack is enabled -# and WiFi disabled by default in this example CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y CONFIG_BTDM_CTRL_MODE_BTDM=n CONFIG_BT_CLASSIC_ENABLED=y -CONFIG_ESP_WIFI_ENABLED=n CONFIG_BT_SPP_ENABLED=y CONFIG_BT_BLE_ENABLED=n diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c index bde63273b7d..7e10c2ea106 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c @@ -5,7 +5,6 @@ */ #include "driver/uart.h" -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/sdkconfig.defaults index 1974e0e8cb5..ce7f5a4cd4e 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/sdkconfig.defaults @@ -1,10 +1,8 @@ # Override some defaults so BT stack is enabled -# and WiFi disabled by default in this example CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y CONFIG_BTDM_CTRL_MODE_BTDM=n CONFIG_BT_CLASSIC_ENABLED=y -CONFIG_ESP_WIFI_ENABLED=n CONFIG_BT_SPP_ENABLED=y CONFIG_BT_BLE_ENABLED=n diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c index f944aa729e6..275df04fda8 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/sdkconfig.defaults index 1974e0e8cb5..ce7f5a4cd4e 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/sdkconfig.defaults @@ -1,10 +1,8 @@ # Override some defaults so BT stack is enabled -# and WiFi disabled by default in this example CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y CONFIG_BTDM_CTRL_MODE_BTDM=n CONFIG_BT_CLASSIC_ENABLED=y -CONFIG_ESP_WIFI_ENABLED=n CONFIG_BT_SPP_ENABLED=y CONFIG_BT_BLE_ENABLED=n diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/main/spp_task.c b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/main/spp_task.c index f944aa729e6..275df04fda8 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/main/spp_task.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/main/spp_task.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/sdkconfig.defaults index 1974e0e8cb5..ce7f5a4cd4e 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_initiator/sdkconfig.defaults @@ -1,10 +1,8 @@ # Override some defaults so BT stack is enabled -# and WiFi disabled by default in this example CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y CONFIG_BTDM_CTRL_MODE_BTDM=n CONFIG_BT_CLASSIC_ENABLED=y -CONFIG_ESP_WIFI_ENABLED=n CONFIG_BT_SPP_ENABLED=y CONFIG_BT_BLE_ENABLED=n diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_core.c b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_core.c index 799ea803f62..c1b8ba81b87 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_core.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults index d79e6d40d8e..9586b714780 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults @@ -1,5 +1,5 @@ # Override some defaults so BT stack is enabled and -# Classic BT is enabled and BT_DRAM_RELEASE is disabled +# Classic BT is enabled CONFIG_BT_ENABLED=y CONFIG_BT_BLE_ENABLED=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c index 549ba82af02..c8762d8313d 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults index 4775673416a..351210d4f83 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults @@ -1,5 +1,5 @@ # Override some defaults so BT stack is enabled and -# Classic BT is enabled and BT_DRAM_RELEASE is disabled +# Classic BT is enabled CONFIG_BT_ENABLED=y CONFIG_BT_BLE_ENABLED=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y diff --git a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/CMakeLists.txt b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/CMakeLists.txt index c34ea69578b..e68a065139b 100644 --- a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/CMakeLists.txt +++ b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/CMakeLists.txt @@ -1,4 +1,5 @@ idf_component_register(SRCS "bt_app_av.c" "bt_app_core.c" "main.c" + PRIV_REQUIRES esp_driver_i2s bt nvs_flash esp_ringbuf esp_driver_dac INCLUDE_DIRS ".") diff --git a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_core.c b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_core.c index 29ce385feb1..29c915e893e 100644 --- a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_core.c @@ -7,7 +7,6 @@ #include #include #include -#include "freertos/xtensa_api.h" #include "freertos/FreeRTOSConfig.h" #include "freertos/FreeRTOS.h" #include "freertos/queue.h" diff --git a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/main.c b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/main.c index 87f5a82f4a5..bc2dd5e938c 100644 --- a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/main.c +++ b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/main.c @@ -197,20 +197,20 @@ static void gap_event_handler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t *prepare_write_env, esp_ble_gatts_cb_param_t *param){ esp_gatt_status_t status = ESP_GATT_OK; if (param->write.need_rsp){ - if (param->write.is_prep){ - if (prepare_write_env->prepare_buf == NULL) { + if (param->write.is_prep) { + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE*sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(BT_BLE_COEX_TAG, "Gatt_server prep no mem"); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); diff --git a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults index c7e3115a4da..a20f726e121 100644 --- a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults @@ -7,7 +7,6 @@ CONFIG_BTDM_CTRL_MODE_BTDM=y CONFIG_BTDM_CTRL_PINNED_TO_CORE_0=y CONFIG_BTDM_CTRL_PINNED_TO_CORE_1=n CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 -CONFIG_BTDM_CTRL_HCI_MODE_VHCI=y CONFIG_BTDM_CTRL_HCI_MODE_UART_H4=n CONFIG_BT_BLUEDROID_ENABLED=y CONFIG_BT_BLUEDROID_PINNED_TO_CORE_0=y @@ -17,13 +16,10 @@ CONFIG_BT_BTC_TASK_STACK_SIZE=3072 CONFIG_BT_BLUEDROID_MEM_DEBUG=n CONFIG_BT_CLASSIC_ENABLED=y CONFIG_BT_A2DP_ENABLE=y -CONFIG_A2DP_SINK_ENABLE=y -CONFIG_A2DP_SRC_ENABLE=n CONFIG_BT_SPP_ENABLED=n CONFIG_BT_GATTS_ENABLE=y CONFIG_BT_GATTC_ENABLE=n CONFIG_BT_BLE_SMP_ENABLE=n -CONFIG_BLE_ENABLE_SRVCHG_REG=y CONFIG_BT_STACK_NO_LOG=n CONFIG_BT_ACL_CONNECTIONS=4 CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=n diff --git a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/main/gattc_gatts_coex.c b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/main/gattc_gatts_coex.c index 89e0136baa6..bbe1e80d2ba 100644 --- a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/main/gattc_gatts_coex.c +++ b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/main/gattc_gatts_coex.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -535,19 +535,18 @@ static void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t * esp_gatt_status_t status = ESP_GATT_OK; if (param->write.need_rsp) { if (param->write.is_prep) { - if (prepare_write_env->prepare_buf == NULL) { + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE*sizeof(uint8_t)); prepare_write_env->prepare_len = 0; if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(COEX_TAG, "Gatt_server prep no mem"); status = ESP_GATT_NO_RESOURCES; } - } else { - if(param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); diff --git a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/sdkconfig.defaults b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/sdkconfig.defaults index 9391307bcb2..1bf8906ea7d 100644 --- a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/sdkconfig.defaults @@ -4,4 +4,5 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. CONFIG_BT_LE_50_FEATURE_SUPPORT=n diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/README.md b/examples/bluetooth/esp_ble_mesh/coex_test/README.md deleted file mode 100644 index 4c9ebb15115..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/README.md +++ /dev/null @@ -1,110 +0,0 @@ -| Supported Targets | ESP32 | -| ----------------- | ----- | - -# Example of BLE Mesh and TCP Server/Client Coexistence - -This example introduces how to test the basic functions of `BLE Mesh data interface` and `TCP Server/Client Coexistence`. `BLE Mesh data interface` is GAP scanning and advertising. - -There are two working modes here: - - * In automatic mode, the program coordinates three development boards working through a synchronization mechanism. - - * In manual mode, you will work with three development boards via commands - - -## Test Preparation - -* Before running the test, you need to prepare a router and three ESP32 development boards. This Example of BLE Mesh and TCP Server/Client Coexistence has the following three items, and any of the three development boards is for running one specific item. - - * ble_dev : Run only the BLE program. - * coex_dev: Run BLE and Wi-Fi program. - * wifi_dev: Run only the Wi-Fi program. - -``Note: If you want better performance in BLE and WiFi coexistence, you should use a development board with PSRAM that could run a coexistence program. Such as ESP32_LyraT, ESP32-WROVER-B and etc.`` - -* The following structure shows the parameters you need to configure. And usually, there are two methods for configuration, i.e. configuring during initialization or configuring with the command `env`. - -```c -coex_test_env_t test_env = { -#if defined(CONFIG_EXAMPLE_MANAUL) - .ap_ssid = CONFIG_EXAMPLE_WIFI_SSID, - .ap_password = CONFIG_EXAMPLE_WIFI_PASSWORD, -#endif -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - .ap_ssid = CONFIG_EXAMPLE_WIFI_SSID, - .ap_password = CONFIG_EXAMPLE_WIFI_PASSWORD, -#endif - .test_port = "8080", - .server_ip = "192.168.3.32", - .duration = "120000", - .is_start = false, -}; -``` - - -## Run Test Case Manually -Configure to Manual Mode via `Example Configuration --->run mode (manual) ` - -The meaning of the numeric argument of the command `run_tc` is as follows: - -| id | case name | description | -|:-:|:-|:-| -| 0 | wifi_tcp_tx_throughput| Test the case of Wi-Fi tcp tx, which will create a tcp client that will continuously send data to the tcp server. | -| 1 |wifi_tcp_rx_throughput| Test the case of Wi-Fi tcp rx, which will create a tcp server that will continuously receive data from the tcp client. | -| 2 | ble_adv | Test the case of BLE advertising. | -| 3 | ble_scan| Test the case of BLE Scan.| - - -### Case 1: tcp tx + scan -1. wifi_dev: run_tc -w 1 -2. coex_dev: env -s -k server_ip -v 192.168.3.34 run_tc -w 0 -b 3 -3. ble_dev : run_tc -b 2 - - -### Case 2: tcp rx + scan -1. coex_dev: run_tc -w 1 -b 3 -2. wifi_dev: env -s -k server_ip -v 192.168.3.34 run_tc -w 0 -3. ble_dev : run_tc -b 2 - -### Case 3: tcp tx + adv -1. wifi_dev: run_tc -w 1 -2. coex_dev: env -s -k server_ip -v 192.168.3.13 run_tc -w 0 -b 2 -3. ble_dev : run_tc -b 3 - - -### Case 4: tcp rx + adv -1. coex_dev: run_tc -w 1 -b 2 -2. wifi_dev: env -s -k server_ip -v 192.168.3.34 run_tc -w 0 -3. ble_dev : run_tc -b 3 - -## Run Test Case By Automation -Configure to Automatic Mode via `Example Configuration --->run mode (auto) ` - -### Coexistence device configuration -1. Select a development board as coexistence role by `Example Configuration --->select role (run device as coex role) ` -2. Select a test case by `Example Configuration --->select case `. -* There are four types of cases: - * TCP TX and BLE ADV: The TCP client will be created on the coexistence device, and bluetooth will start advertising when the Wi-Fi is running tx throughput program. - * TCP RX and BLE ADV: The TCP server will be created on the coexistence device, and bluetooth will start advertising when the Wi-Fi is running rx throughput program. - * TCP TX and BLE SCAN: The TCP client will be created on the coexistence device, and bluetooth will start scanning when the Wi-Fi is running tx throughput program. - * TCP RX and BLE SCAN: The TCP server will be created on the coexistence device, and bluetooth will start scanning when the Wi-Fi is running rx throughput program. - -### Bluetooth device configuration -1. Select a development board as bluetooth role by `select role (run device as bluetooth role) ` - -### Wi-Fi device configuration -1. Select a development board as bluetooth role by `select role (run device as wifi role) ` - - -## Coexistence Configuration -In theory, the performance of BLE and Wi-Fi coexistence will drop to half of the performance in BLE Only mode or Wi-Fi Only mode. - -* ESP32 working frequency: - * Component config ---> ESP32-specific ---> CPU frequency (240 MHz) - -* ESP32 external PSRAM - * Component config ---> ESP32-specific ---> Support for external, SPI-connected RAM - * Devices that do not support PSRAM cannot open this option! - -* ESP32 coexistence mode - * Component config ---> Wi-Fi ---> WiFi/Bluetooth coexistence performance preference (Balance) diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/CMakeLists.txt b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/CMakeLists.txt deleted file mode 100644 index b08fff2317d..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -set(srcs "ble_unit.c" - "run_tc.c" - "sync.c" - "test_env.c" - "wifi_connect.c" - "wifi_unit.c") - -idf_component_register(SRCS "${srcs}" - INCLUDE_DIRS "." - REQUIRES console nvs_flash bt - REQUIRED_IDF_TARGETS esp32) diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/ble_unit.c b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/ble_unit.c deleted file mode 100644 index eb2ff480686..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/ble_unit.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include - -#include "ble_unit.h" -#include "sync.h" -#define TAG "BLE_UINT" - -#define GAP_TRANS_DEFAULT_SHORT_TO 50 // 50ms for events expected to reported as soon as API called - -static uint8_t default_adv_data[] = { - 0x02, 0x01, 0x06, - 0x02, 0x0a, 0xeb, 0x03, 0x03, 0xab, 0xcd -}; -static uint8_t default_scan_rsp_data[] = { - 0x0f, 0x09, 0x45, 0x53, 0x50, 0x5f, 0x47, 0x41, 0x54, 0x54, 0x53, 0x5f, 0x43, - 0x4f, 0x45, 0x58 -}; - -esp_ble_scan_params_t default_scan_param = { - .scan_type = BLE_SCAN_TYPE_ACTIVE, - .own_addr_type = BLE_ADDR_TYPE_PUBLIC, - .scan_filter_policy = BLE_SCAN_FILTER_ALLOW_ALL, - .scan_interval = 0x100, - .scan_window = 0x100 -}; - -esp_ble_adv_params_t default_adv_param = { - .adv_int_min = 0x40, - .adv_int_max = 0x40, - .adv_type = ADV_TYPE_IND, - .own_addr_type = BLE_ADDR_TYPE_PUBLIC, - .channel_map = ADV_CHNL_ALL, - .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, -}; - -ble_util_scan_count_t scan_count; - -static void ble_gap_event_default_handler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) -{ - switch (event) { - case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT: { - if (param->scan_param_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "set scan parameter failed, error status = %x", param->scan_param_cmpl.status); - } - break; - } - case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: { - if (param->adv_data_raw_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "set row data failed, error status = %x", param->adv_data_raw_cmpl.status); - } - break; - } - case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: { - if (param->scan_rsp_data_raw_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "set scan response data failed, error status = %x", param->scan_rsp_data_raw_cmpl.status); - } - break; - } - case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: { - if (param->adv_start_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "Advertising start failed"); - } - break; - } - case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: - if (param->adv_stop_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "Advertising stop failed"); - } - break; - case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT: { - if (param->scan_start_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "scan start failed, error status = %x", param->scan_start_cmpl.status); - } - break; - } - case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT: - if (param->scan_stop_cmpl.status != ESP_BT_STATUS_SUCCESS) { - ESP_LOGE(TAG, "scan stop failed, error status = %x", param->scan_stop_cmpl.status); - } - break; - default: - break; - } -} - -static void ble_gap_util_handler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) -{ - if (sync_obj.cmd_recv != NULL) { - sync_obj.cmd_recv(param->scan_rst.ble_adv, param->scan_rst.adv_data_len); - } - - switch (event) { - case ESP_GAP_BLE_SCAN_RESULT_EVT: - switch (param->scan_rst.search_evt) { - case ESP_GAP_SEARCH_INQ_RES_EVT: - if (param->scan_rst.adv_data_len > 0 \ - && (memcmp(default_adv_data, param->scan_rst.ble_adv, sizeof(default_adv_data)) == 0)) { - scan_count.adv_count += 1; - if (scan_count.adv_count % 10 == 0) { - ESP_LOGI(TAG, "adv count:%" PRIu32 " scan_res count %" PRIu32, scan_count.adv_count, scan_count.scan_res_count); - } - } - - if (param->scan_rst.scan_rsp_len > 0 \ - && (memcmp(default_scan_rsp_data, (param->scan_rst.ble_adv + param->scan_rst.adv_data_len), sizeof(default_scan_rsp_data)) == 0)) { - scan_count.scan_res_count += 1; - } - break; - default: - break; - } - break; - default: - ble_gap_event_default_handler(event, param); - break; - } -} - - -esp_err_t ble_gap_util_set_adv_data(uint8_t *adv_data, uint32_t adv_data_len, uint8_t *scan_rsp_data, uint32_t scan_rsp_data_len) -{ - esp_err_t ret; - - ret = esp_ble_gap_config_adv_data_raw(adv_data, adv_data_len); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_config_adv_data_raw error, %d", ret); - return ret; - } - ret = esp_ble_gap_config_scan_rsp_data_raw(scan_rsp_data, scan_rsp_data_len); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_config_scan_rsp_data_raw error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t ble_gap_util_set_default_adv_data(void) -{ - return ble_gap_util_set_adv_data(default_adv_data, sizeof(default_adv_data), default_scan_rsp_data, sizeof(default_scan_rsp_data)); -} - -esp_err_t ble_gap_util_start_adv(esp_ble_adv_params_t *adv_param) -{ - esp_err_t ret; - ret = esp_ble_gap_start_advertising(adv_param); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_start_advertising error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t ble_gap_util_start_adv_default(void) -{ - esp_err_t ret; - - ret = esp_ble_gap_start_advertising(&default_adv_param); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_start_advertising error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t ble_gap_util_stop_adv(void) -{ - esp_err_t ret; - ret = esp_ble_gap_stop_advertising(); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_stop_advertising error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t ble_gap_util_set_scan_param(esp_ble_scan_params_t *scan_param) -{ - esp_err_t ret; - ret = esp_ble_gap_set_scan_params(scan_param); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_set_scan_params error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t ble_gap_util_set_default_scan_param(void) -{ - return ble_gap_util_set_scan_param(&default_scan_param); -} - -esp_err_t ble_gap_util_start_scan(uint32_t duration) -{ - esp_err_t ret; - ret = esp_ble_gap_start_scanning(duration); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_start_scanning error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t ble_gap_util_stop_scan(void) -{ - esp_err_t ret; - ret = esp_ble_gap_stop_scanning(); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_stop_scanning error, %d", ret); - return ret; - } - return 0; -} - - -void ble_gap_util_stop(void) -{ - ble_gap_util_stop_adv(); - ble_gap_util_stop_scan(); -} - -esp_err_t init_ble_gap_test_util(void) -{ - esp_err_t ret; - ret = esp_ble_gap_register_callback(ble_gap_util_handler); - if (ret) { - ESP_LOGE(TAG, "gap register error, error code = %x", ret); - } - return ret; -} - -void bt_test_init(void) -{ - ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT)); - esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); - ESP_ERROR_CHECK(esp_bt_controller_init(&bt_cfg)); - ESP_ERROR_CHECK(esp_bt_controller_enable(ESP_BT_MODE_BLE)); - esp_bluedroid_config_t bluedroid_cfg = BT_BLUEDROID_INIT_CONFIG_DEFAULT(); - ESP_ERROR_CHECK(esp_bluedroid_init_with_cfg(&bluedroid_cfg)); - ESP_ERROR_CHECK(esp_bluedroid_enable()); -} - -void bt_test_deinit(void) -{ - esp_bluedroid_disable(); - esp_bluedroid_deinit(); - esp_bt_controller_disable(); - esp_bt_controller_deinit(); -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/ble_unit.h b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/ble_unit.h deleted file mode 100644 index d5b4c5362c2..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/ble_unit.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef _BLE_UNIT_H_ -#define _BLE_UNIT_H_ -#include -#include -#include "esp_system.h" -#include "esp_timer.h" -#include "esp_log.h" -#include "nvs_flash.h" -#include "esp_bt.h" - -#include "esp_gap_ble_api.h" -#include "esp_gatts_api.h" -#include "esp_gattc_api.h" -#include "esp_bt_defs.h" -#include "esp_bt_main.h" -#include "esp_gatt_common_api.h" - -#define BLE_TC_SCAN_REPORT_PERIOD 10000 - -typedef struct { - uint32_t adv_count; - uint32_t scan_res_count; -} ble_util_scan_count_t; - - -extern esp_bd_addr_t bt_addr; -extern ble_util_scan_count_t scan_count; -extern esp_ble_adv_params_t default_adv_param; -extern esp_ble_scan_params_t default_scan_param; - -void bt_test_init(void); -void bt_test_deinit(void); -void ble_gap_util_stop(void); - -esp_err_t ble_gap_util_set_adv_data(uint8_t *adv_data, uint32_t adv_data_len, uint8_t *scan_rsp_data, uint32_t scan_rsp_data_len); -esp_err_t ble_gap_util_set_default_adv_data(void); -esp_err_t ble_gap_util_start_adv(esp_ble_adv_params_t *adv_param); -esp_err_t ble_gap_util_start_adv_default(void); -esp_err_t ble_gap_util_stop_adv(void); - -esp_err_t ble_gap_util_set_scan_param(esp_ble_scan_params_t *scan_param); -esp_err_t ble_gap_util_set_default_scan_param(void); -esp_err_t ble_gap_util_start_scan(uint32_t duration); -esp_err_t ble_gap_util_stop_scan(void); - -esp_err_t init_ble_gap_test_util(void); - -#endif /* _BLE_UNIT_H_ */ diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/run_tc.c b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/run_tc.c deleted file mode 100644 index 08460ae9981..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/run_tc.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include - -#include "run_tc.h" -#include "test_env.h" -#include "wifi_unit.h" -#include "ble_unit.h" -#include "sync.h" -#include "wifi_connect.h" - -#define TAG "CASE" - -QueueHandle_t xTaskQueue = 0; - -static const char *coex_get_case_env(coex_test_env_t *test_env, const char *keyword) -{ - const char *ret = NULL; - if (!strcmp(keyword, "ap_ssid")) { - ret = test_env->ap_ssid; - } else if (!strcmp(keyword, "ap_password")) { - ret = test_env->ap_password; - } else if (!strcmp(keyword, "test_port")) { - ret = test_env->test_port; - } else if (!strcmp(keyword, "server_ip")) { - ret = test_env->server_ip; - } else if (!strcmp(keyword, "duration")) { - ret = test_env->duration; - } - - return ret; -} - -static void wifi_tc_sta_throughput_timeout(void *arg) -{ - static uint32_t statistic_count = 0; - static uint64_t accumulate_speed = 0; - - uint32_t now = utils_get_system_ts(); - uint32_t *report = (uint32_t *) arg; - uint32_t last_timestamp = report[0]; - - if (now > last_timestamp) { - uint32_t speed = report[1] * 8 / (now - last_timestamp); - accumulate_speed += speed; - statistic_count += 1; - printf("speed: %" PRIu32 " kbps average speed: %lld kbps\n", speed, accumulate_speed / statistic_count ); - report[1] = 0; - report[0] = now; - } -} - -static esp_err_t create_statistic_timer(esp_timer_handle_t *timer_hdl , uint32_t statistic_date[]) -{ - esp_err_t ret; - esp_timer_create_args_t tca = { - .callback = (esp_timer_cb_t)wifi_tc_sta_throughput_timeout, - .dispatch_method = ESP_TIMER_TASK, - .name = "TCP_STATISTIC", - }; - tca.arg = statistic_date; - ret = esp_timer_create(&tca, timer_hdl); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "statistic_timer create failed"); - return ret; - } - esp_timer_start_periodic(*timer_hdl, 1000000); //1000ms - return ret; -} - - -void wifi_tcp_tx_throught_start(void *param) -{ - esp_timer_handle_t timer_hdl = NULL; - esp_err_t ret; - int sock = -1; - uint32_t statistic_date[2] = {0}; - - const char *ssid = coex_get_case_env(param, "ap_ssid"); - const char *passwd = coex_get_case_env(param, "ap_password"); - - - wifi_util_init(); - // wifi_unit_connect_ap(ssid, passwd); - example_connect(ssid, passwd); - -#if defined(CONFIG_EXAMPLE_AUTO) - if (((coex_test_env_t *)param)->run_mutex != NULL) { - //This will be blocked by the sync timer. - xSemaphoreTake(((coex_test_env_t *)param)->run_mutex, portMAX_DELAY); - xSemaphoreGive(((coex_test_env_t *)param)->run_mutex); - } -#endif - const char *ip = coex_get_case_env(param, "server_ip"); - const char *port = coex_get_case_env(param, "test_port"); - const char *duration = coex_get_case_env(param, "duration"); - wifi_unit_client_establish(&sock, ip, port); - - ret = create_statistic_timer(&timer_hdl, statistic_date); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "statistic_timer create failed"); - goto _stop; - } - - ret = wifi_util_tcp_send(sock, 1460, 0, &statistic_date[1], atoi(duration)); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "send failed, %x", ret); - } - -_stop: - if (timer_hdl) { - esp_timer_stop(timer_hdl); - esp_timer_delete(timer_hdl); - } - - if (sock > 0) { - close(sock); - } -} - -void wifi_tcp_tx_throught_end(void) -{ - esp_wifi_disconnect(); -} - -void wifi_tcp_rx_throught_start(void *param) -{ - esp_timer_handle_t timer_hdl = NULL; - esp_err_t ret; - int sock = -1; - uint32_t statistic_date[2] = {0}; - - const char *ssid = coex_get_case_env(param, "ap_ssid"); - const char *passwd = coex_get_case_env(param, "ap_password"); - const char *port = coex_get_case_env(param, "test_port"); - const char *duration = coex_get_case_env(param, "duration"); - - wifi_util_init(); - // wifi_unit_connect_ap(ssid, passwd); - example_connect(ssid, passwd); - wifi_unit_server_establish( &sock, port); - - ret = create_statistic_timer(&timer_hdl, statistic_date); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "statistic_timer create failed"); - goto _stop; - } - ret = wifi_unit_tcp_recv(sock, duration, statistic_date); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "tcp receive failed"); - goto _stop; - } -_stop: - if (timer_hdl) { - esp_timer_stop(timer_hdl); - esp_timer_delete(timer_hdl); - } - - if (sock > 0) { - close(sock); - } -} - -void wifi_tcp_rx_throught_end(void) -{ - esp_wifi_disconnect(); -} - -void ble_adv_start(void *param) -{ - esp_err_t ret; - const char *duration = coex_get_case_env(param, "duration"); -#if defined(CONFIG_EXAMPLE_MANAUL) - bt_test_init(); -#endif - ret = ble_gap_util_set_default_adv_data(); - - if (ret != ESP_OK) { - ESP_LOGE(TAG, "failed to set adv data"); - return; - } - - ret = ble_gap_util_start_adv(&default_adv_param); - - if (ret != ESP_OK) { - ESP_LOGE(TAG, "failed to start adv"); - return; - } - - vTaskDelay(atoi(duration) / portTICK_PERIOD_MS); - -} - -void ble_adv_end(void) -{ - ble_gap_util_stop(); -} - - -void ble_scan_start(void *param) -{ - esp_err_t ret; -#if defined(CONFIG_EXAMPLE_MANAUL) - bt_test_init(); - vTaskDelay(10 / portTICK_PERIOD_MS); - init_ble_gap_test_util(); -#endif - - - ret = ble_gap_util_set_scan_param(&default_scan_param); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "set scan param fail"); - return; - } - vTaskDelay(10 / portTICK_PERIOD_MS); - - scan_count.adv_count = 0; - scan_count.scan_res_count = 0; - - ret = esp_ble_gap_start_scanning(BLE_TC_SCAN_REPORT_PERIOD); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_start_scanning error, %d", ret); - return; - } -} - -void ble_scan_end(void) -{ - ESP_LOGI(TAG, "%s", __func__); -} - -tc_t tc_case[] = { - DECLARE_TC(TC_WIFI_COEX_TCP_TX_THROUGHPUT, 0, wifi_tcp_tx_throught_start, wifi_tcp_tx_throught_end, (void *)&test_env), - DECLARE_TC(TC_WIFI_COEX_TCP_RX_THROUGHPUT, 1, wifi_tcp_rx_throught_start, wifi_tcp_rx_throught_end, (void *)&test_env), - DECLARE_TC(TC_BLE_COEX_ADV, 2, ble_adv_start, ble_adv_end, (void *)&test_env), - DECLARE_TC(TC_BLE_COEX_SCAN, 3, ble_scan_start, ble_scan_end, (void *)&test_env), -}; - -static void excute_case(void *arg) -{ - tc_t *run_case = (tc_t *) arg; - if (run_case && run_case->func_start != NULL) { - run_case->func_start(run_case->param_list); - } - - if (run_case && run_case->func_stop != NULL ) { - vTaskDelay(100 / portTICK_PERIOD_MS); - run_case->func_stop(); - } - vTaskDelete(NULL); -} - -static void run_task(void *arg) -{ - tc_t *tc_case_table = (tc_t *) arg; - run_task_msg_t msg; - - for (;;) { - if (pdTRUE == xQueueReceive(xTaskQueue, &msg, (TickType_t)portMAX_DELAY)) { - if ( msg.case_id < sizeof(tc_case) / sizeof(tc_case[0]) ) { - xTaskCreatePinnedToCore(excute_case, tc_case_table->name, 4096, &tc_case_table[msg.case_id], RUN_TASK_PRIORITY, NULL, 0); - } else { - ESP_LOGW(TAG, "msg.case_id %d", msg.case_id); - } - - } - } - vTaskDelete(NULL); -} - - -void run_tc_init(void) -{ - xTaskQueue = xQueueCreate(RUN_TASK_QUEUE_LEN, sizeof(run_task_msg_t)); - if (!xTaskQueue) { - ESP_LOGE(TAG, "xTaskQueue create failed"); - return; - } - xTaskCreatePinnedToCore(run_task, "run_task", 4096, tc_case, RUN_TASK_PRIORITY, NULL, 0); -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/run_tc.h b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/run_tc.h deleted file mode 100644 index 9f07194acba..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/run_tc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef __RUN_TC_H__ -#define __RUN_TC_H__ - -#include -#include -#include -#include - -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/queue.h" - -#define TC_NAME_LEN 63 -typedef void (*tc_func_start_t)(void *param); -typedef void (*tc_func_end_t)(void); - - -typedef struct tc { - char name[TC_NAME_LEN + 1]; - uint8_t case_id; - tc_func_start_t func_start; - tc_func_end_t func_stop; - void *param_list; -} tc_t; - - -#define TC_WIFI_COEX_TCP_TX_THROUGHPUT "TCP_COEX_TX_THROUGHPUT" -#define TC_WIFI_COEX_TCP_RX_THROUGHPUT "TCP_COEX_RX_THROUGHPUT" -#define TC_BLE_COEX_ADV "BLE_COEX_ADVERTISING" -#define TC_BLE_COEX_SCAN "BLE_COEX_SCAN" - -// run_task queue size -#define RUN_TASK_QUEUE_LEN 6 -#define RUN_TASK_PRIORITY 18 - -#define DECLARE_TC(name, id, start_func, stop_func, param_list) \ - {name, id, start_func, stop_func, param_list} - -typedef struct run_task_msg { - uint8_t case_id; -} run_task_msg_t; - -extern QueueHandle_t xTaskQueue ; - -void run_tc_init(void); - -#endif /* __RUN_TC_H__ */ diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/sync.c b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/sync.c deleted file mode 100644 index 0680cd5c699..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/sync.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include "sync.h" -#include "run_tc.h" -#include "wifi_unit.h" -#define TAG "SYNC" - -SemaphoreHandle_t client_mutex; - -struct sync_t sync_obj = { - .except_recv_wifi_id = false, - .except_recv_bt_id = false, - .recv_param_bit = 0x0, - .start_time = 0x0, - -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - .state = ASSIGN_CASE, -#else - .state = WAIT_CASE, -#endif -#if defined(CONFIG_EXAMPLE_COEX_TX_ADV) - .own_wifi_case = WIFI_TCP_TX_CASE, - .own_ble_case = BLE_ADV_CASE, -#elif defined(CONFIG_EXAMPLE_COEX_RX_ADV) - .own_wifi_case = WIFI_TCP_RX_CASE, - .own_ble_case = BLE_ADV_CASE, -#elif defined(CONFIG_EXAMPLE_COEX_TX_SCAN) - .own_wifi_case = WIFI_TCP_TX_CASE, - .own_ble_case = BLE_SCAN_CASE, -#elif defined(CONFIG_EXAMPLE_COEX_RX_SCAN) - .own_wifi_case = WIFI_TCP_RX_CASE, - .own_ble_case = BLE_SCAN_CASE, -#else - .own_wifi_case = NOT_CASE, - .own_ble_case = NOT_CASE, -#endif -}; - - -auto_tc auto_tb[6] = { - {WIFI_TCP_TX_CASE, PARAMTER(0b011011)}, //need paramter: wifi_case_id ssid password server ip - {WIFI_TCP_RX_CASE, PARAMTER(0b010011)}, //need paramter: wifi_case_id ssid password - {BLE_ADV_CASE, PARAMTER(0b100000)}, //need paramter: ble_case_id - {BLE_SCAN_CASE, PARAMTER(0b100000)}, //need paramter: ble_case_id -}; - - -esp_err_t send_adv(uint8_t *raw_data, uint32_t raw_data_len) -{ - esp_err_t ret; - - esp_ble_adv_params_t adv_param = { - .adv_int_min = 0x40, - .adv_int_max = 0x40, - .adv_type = ADV_TYPE_NONCONN_IND, - .own_addr_type = BLE_ADDR_TYPE_PUBLIC, - .channel_map = ADV_CHNL_ALL, - .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, - }; - ret = esp_ble_gap_config_adv_data_raw(raw_data, raw_data_len); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_config_adv_data_raw error, %d", ret); - return ret; - } - - ret = esp_ble_gap_start_advertising(&adv_param); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_start_advertising error, %d", ret); - return ret; - } - vTaskDelay(30 / portTICK_PERIOD_MS); //every 30ms send one packet - - ret = esp_ble_gap_stop_advertising(); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_stop_advertising error, %d", ret); - return ret; - } - return 0; -} - -esp_err_t send_adv_data(sync_msg *msg) -{ - send_adv((uint8_t *)msg, sizeof(sync_msg)); - return 0; -} - -void send_start_msg(uint8_t start_time) -{ - sync_msg msg = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = 0x4, - .ctl = MSG_CONTINUE, - .param_bit = 0b000100 << PARAM_MAX, - .reserve = 0xff, - .data = {start_time}, - }; - send_adv_data(&msg); -} -void send_start_countdown(void) -{ - if (sync_obj.except_recv_bt_id == true && sync_obj.except_recv_wifi_id == true) { - esp_timer_stop(sync_obj.sync_timer); - esp_timer_start_once(sync_obj.sync_timer, 1000000); - sync_obj.state = START_CASE; - } -} -void send_tcp_rx_inited_msg(void) -{ - uint8_t hex_ip[4]; - uint32_t ip = wifi_util_get_ip(); - memcpy(hex_ip, &ip, sizeof(hex_ip)); - if (hex_ip[0] == 0x0) { - return; - } - sync_msg msg = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = MSG_ID_WIFI_DEV_INIT_FINISH, - .ctl = MSG_CONTINUE, - .param_bit = 0b001000 << PARAM_MAX, - .reserve = 0xff, - .data = {hex_ip[0], hex_ip[1], hex_ip[2], hex_ip[3]}, - }; - send_adv_data(&msg); -} -void send_case_inited_msg(uint8_t msg_id) -{ - sync_msg msg = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = msg_id, - .ctl = MSG_CONTINUE, - .param_bit = 0b000000 << PARAM_MAX, - .reserve = 0xff, - .data = {0}, - }; - send_adv_data(&msg); -} - -void assign_case_to_dev(uint8_t ble_id, uint8_t wifi_id) -{ - if ( sync_obj.own_wifi_case == WIFI_TCP_RX_CASE ) { - uint8_t hex_ip[4]; - uint32_t ip = wifi_util_get_ip(); - ESP_LOGI(TAG, "ip:%s", inet_ntoa(ip)); - memcpy(hex_ip, &ip, sizeof(hex_ip)); - if (hex_ip[0] == 0x0) { - return; - } - sync_msg msg = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = 0x1, - .ctl = MSG_CONTINUE, - .param_bit = 0b111000 << PARAM_MAX, - .reserve = 0xff, - .data = {ble_id, wifi_id, hex_ip[0], hex_ip[1], hex_ip[2], hex_ip[3]}, - }; - send_adv_data(&msg); - } else if ( sync_obj.own_wifi_case == WIFI_TCP_TX_CASE ) { - sync_msg msg1 = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = 0x1, - .ctl = MSG_CONTINUE, - .param_bit = 0b110000 << PARAM_MAX, - .reserve = 0xff, - .data = {ble_id, wifi_id}, - }; - send_adv_data(&msg1); - } -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - if (strlen(CONFIG_EXAMPLE_WIFI_SSID) < 20) { - sync_msg msg = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = 0x1, - .ctl = MSG_CONTINUE, - .param_bit = 0b000010 << PARAM_MAX, - .reserve = 0xff, - .data[0] = strlen(CONFIG_EXAMPLE_WIFI_SSID), - }; - for (uint8_t i = 0 ; i < strlen(CONFIG_EXAMPLE_WIFI_SSID); i++) { - msg.data[i + 1] = CONFIG_EXAMPLE_WIFI_SSID[i] - '0'; - } - send_adv_data(&msg); - } - - if (strlen(CONFIG_EXAMPLE_WIFI_PASSWORD) < 20) { - sync_msg msg = { - .length = 30, - .type = MSG_TYPE, - .head = MSG_HEAD, - .msg_id = 0x1, - .ctl = MSG_END, - .param_bit = 0b000001 << PARAM_MAX, - .reserve = 0xff, - .data[0] = strlen(CONFIG_EXAMPLE_WIFI_PASSWORD), - }; - for (int i = 0 ; i < strlen(CONFIG_EXAMPLE_WIFI_PASSWORD); i++) { - msg.data[i + 1] = CONFIG_EXAMPLE_WIFI_PASSWORD[i] - '0'; - } - send_adv_data(&msg); - } -#endif -} - - -void excute_case(uint8_t run_case) -{ - run_task_msg_t msg; - msg.case_id = run_case; - if (xQueueSend(xTaskQueue, &msg, portMAX_DELAY) != pdTRUE) { - ESP_LOGE(TAG, "xTaskQueue Post failed"); - } -} - - -void assign_test_case(void) -{ -#if defined(CONFIG_EXAMPLE_COEX_TX_ADV) - assign_case_to_dev(BLE_SCAN_CASE, WIFI_TCP_RX_CASE); -#elif defined(CONFIG_EXAMPLE_COEX_RX_ADV) - assign_case_to_dev(BLE_SCAN_CASE, WIFI_TCP_TX_CASE); -#elif defined(CONFIG_EXAMPLE_COEX_TX_SCAN) - assign_case_to_dev(BLE_ADV_CASE, WIFI_TCP_RX_CASE); -#elif defined(CONFIG_EXAMPLE_COEX_RX_SCAN) - assign_case_to_dev(BLE_ADV_CASE, WIFI_TCP_TX_CASE); -#endif -} - - -void analys_param(uint16_t param_bit, uint8_t data[], uint16_t *recv_param_bit) -{ - - uint8_t data_ptr = 0; - - for (int i = 0 ; i < PARAM_MAX; i++ ) { - switch (GET_PARAM(param_bit, 0x1000 >> i)) { - case BLE_CASE_ID: - ESP_LOGD(TAG, "BLE_CASE_ID"); -#if defined(CONFIG_EXAMPLE_BT_ROLE) - sync_obj.own_ble_case = data[data_ptr]; - (*recv_param_bit) |= BLE_CASE_ID; -#endif - data_ptr += 1; - break; - case WIFI_CASE_ID: - ESP_LOGD(TAG, "WIFI_CASE_ID"); -#if defined(CONFIG_EXAMPLE_WIFI_ROLE) - sync_obj.own_wifi_case = data[data_ptr]; - (*recv_param_bit) |= WIFI_CASE_ID; -#endif - data_ptr += 1; - break; - case START_TIME: - ESP_LOGD(TAG, "START_TIME"); - sync_obj.start_time = data[data_ptr]; - data_ptr += 1; - break; - case SERVER_IP: { - ESP_LOGD(TAG, "SERVER_IP"); - char server_ip[16]; - memset(server_ip, '0', sizeof(server_ip)); - sprintf(server_ip, "%d.%d.%d.%d", data[data_ptr], data[data_ptr + 1], data[data_ptr + 2], data[data_ptr + 3]); // size conversion - coex_set_test_env("server_ip", server_ip, sizeof(server_ip)); - coex_print_test_env(); - data_ptr += 4; - (*recv_param_bit) |= SERVER_IP; - break; - } - case WIFI_SSID: { - ESP_LOGD(TAG, "WIFI_SSID"); - uint8_t length = data[data_ptr]; - data_ptr += 1; - if ( length > 20) { - ESP_LOGE(TAG, "ssid length error"); - break; - } - char *ssid = malloc(length + 1); - if (ssid == NULL) { - ESP_LOGE(TAG, "%s malloc fail", __func__); - return ; - } - memset(ssid, '0', sizeof(length + 1)); - - for (int i = length - 1 ; i >= 0 ; i--) { - ssid[i] = data[data_ptr + i] + '0'; - } - ssid[length] = '\n'; - coex_set_test_env("ap_ssid", ssid, length); - coex_print_test_env(); - (*recv_param_bit) |= WIFI_SSID; - free(ssid); - break; - } - case WIFI_PASSWIRD: { - ESP_LOGD(TAG, "WIFI_PASSWIRD"); - uint8_t length = data[data_ptr]; - data_ptr += 1; - if ( length > 20) { - ESP_LOGE(TAG, "password length error"); - break; - } - char *password = malloc(length + 1); - if (password == NULL) { - ESP_LOGE(TAG, "%s malloc fail", __func__); - return ; - } - memset(password, '0', sizeof(length + 1)); - for (int i = length - 1 ; i >= 0 ; i--) { - password[i] = data[data_ptr + i] + '0'; - } - password[length] = '\n'; - coex_set_test_env("ap_password", password, length); - coex_print_test_env(); - (*recv_param_bit) |= WIFI_PASSWIRD; - free(password); - break; - } - default: - break; - } - } - -} - -void sync_cmd_recv(uint8_t *raw_data, uint32_t raw_data_len) -{ - if (raw_data_len < MSG_MIN_LEN) { - ESP_LOGD(TAG, "msg length is low"); - } - sync_msg_head msg_head = {0}; - memcpy(&msg_head, raw_data, sizeof(sync_msg_head)); - - if (msg_head.type != MSG_TYPE || msg_head.head != MSG_HEAD) { - ESP_LOGD(TAG, "msg is unknown"); - return; - } - ESP_LOGD(TAG, "msg_id: %x", msg_head.msg_id); - // ESP_LOG_BUFFER_HEX("sync recv:", raw_data, raw_data_len); - switch (sync_obj.state) { -#if defined(CONFIG_EXAMPLE_WIFI_ROLE) || defined(CONFIG_EXAMPLE_BT_ROLE) - case WAIT_CASE: { - ESP_LOGD(TAG, "WAIT_CASE"); - if (msg_head.msg_id == MSG_ID_ASSIGN_CASE) { - analys_param(msg_head.param_bit, raw_data + MSG_DATA_BASE, &sync_obj.recv_param_bit ); -#if defined(CONFIG_EXAMPLE_WIFI_ROLE) - if (sync_obj.own_wifi_case != NOT_CASE) { - if ((sync_obj.recv_param_bit & auto_tb[sync_obj.own_wifi_case].excpet_param_bit) == auto_tb[sync_obj.own_wifi_case].excpet_param_bit) { - excute_case(sync_obj.own_wifi_case); - sync_obj.state = WAIT_START; - esp_timer_start_periodic(sync_obj.sync_timer, SYNC_TIMEOUT ); - } - } -#endif -#if defined(CONFIG_EXAMPLE_BT_ROLE) - if (sync_obj.own_ble_case != NOT_CASE) { - if ((sync_obj.recv_param_bit & auto_tb[sync_obj.own_ble_case].excpet_param_bit) == auto_tb[sync_obj.own_ble_case].excpet_param_bit) { - sync_obj.state = WAIT_START; - esp_timer_start_periodic(sync_obj.sync_timer, SYNC_TIMEOUT ); - } - } -#endif - } - break; - } - case WAIT_START: - ESP_LOGD(TAG, "WAIT_START"); - ESP_LOGD(TAG, "WAIT_START %x", msg_head.msg_id); - if (msg_head.msg_id == MSG_ID_START_CASE) { - analys_param(msg_head.param_bit, raw_data + MSG_DATA_BASE, &sync_obj.recv_param_bit ); - sync_obj.state = START_CASE; - ble_gap_util_stop(); -#if defined(CONFIG_EXAMPLE_WIFI_ROLE) - bt_test_deinit(); -#endif - esp_timer_stop(sync_obj.sync_timer); - esp_timer_start_once(sync_obj.sync_timer, sync_obj.start_time * 1000000); - } - break; -#endif -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - case ASSIGN_CASE: - ESP_LOGD(TAG, "ASSIGN_CASE"); - switch (msg_head.msg_id) { - case MSG_ID_WIFI_DEV_INIT_FINISH: - if (msg_head.param_bit != 0x0) { - analys_param(msg_head.param_bit, raw_data + MSG_DATA_BASE, &sync_obj.recv_param_bit ); - } - sync_obj.except_recv_wifi_id = true; - break; - case MSG_ID_BT_DEV_INIT_FINISH: - sync_obj.except_recv_bt_id = true; - break; - default: - break; - } - send_start_countdown(); - break; -#endif - default: - ESP_LOGD(TAG, "state is unknown %s", __func__); - break; - } -} - -static void handle_sync_timeout(void *arg) -{ - static bool run_first = true; - if (run_first == true) { - xSemaphoreTake((SemaphoreHandle_t)arg, (TickType_t)portMAX_DELAY); - esp_timer_start_periodic( (esp_timer_handle_t)arg, 1000000); - run_first = false; - } - switch (sync_obj.state) { -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - case ASSIGN_CASE: - ESP_LOGD(TAG, "ASSIGN_CASE"); - assign_test_case(); - esp_timer_start_periodic(sync_obj.sync_timer, SYNC_TIMEOUT); - break; -#endif - -#if defined(CONFIG_EXAMPLE_WIFI_ROLE) || defined(CONFIG_EXAMPLE_BT_ROLE) - case WAIT_START: { - ESP_LOGD(TAG, "WAIT_START"); -#if defined(CONFIG_EXAMPLE_WIFI_ROLE) - if ( WIFI_TCP_RX_CASE == sync_obj.own_wifi_case ) { - send_tcp_rx_inited_msg(); - } else { - send_case_inited_msg(MSG_ID_WIFI_DEV_INIT_FINISH); - } -#elif defined(CONFIG_EXAMPLE_BT_ROLE) - send_case_inited_msg(MSG_ID_BT_DEV_INIT_FINISH); -#endif - esp_timer_start_periodic(sync_obj.sync_timer, SYNC_TIMEOUT); - break; - } -#endif - - - case START_CASE: { - ESP_LOGD(TAG, "START_CASE"); -#if defined(CONFIG_EXAMPLE_BT_ROLE) - excute_case(sync_obj.own_ble_case); - -#elif defined(CONFIG_EXAMPLE_WIFI_ROLE) - ESP_LOGD(TAG, "START_CASE"); - if (arg != NULL) { - xSemaphoreGive((SemaphoreHandle_t)arg); - run_first = true; - esp_timer_stop(sync_obj.sync_timer); - - } -#else - static uint8_t send_start_count = 10; - if (send_start_count == 0) { - excute_case(sync_obj.own_ble_case); - xSemaphoreGive((SemaphoreHandle_t)arg); - run_first = true; - esp_timer_stop(sync_obj.sync_timer); - break; - } - - send_start_msg(send_start_count); - send_start_count -= 1; - esp_timer_start_once(sync_obj.sync_timer, 1000000); -#endif - break; - } - default: - ESP_LOGD(TAG, "state is unknown%s", __func__); - break; - } -} - -esp_err_t create_sync_timer(esp_timer_handle_t *timer_hdl) -{ - esp_err_t ret; - esp_timer_create_args_t tca = { - .callback = (esp_timer_cb_t)handle_sync_timeout, - .dispatch_method = ESP_TIMER_TASK, - .name = "SYNC_TIMER", - }; - tca.arg = client_mutex; - - ret = esp_timer_create(&tca, timer_hdl); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "timer create failed %d %x", __LINE__, ret); - return ret; - } - esp_timer_start_once( *timer_hdl, 10); - - return ret; -} - - -void sync_init(void) -{ - esp_err_t ret; - sync_obj.cmd_recv = &sync_cmd_recv; - client_mutex = xSemaphoreCreateMutex(); - if (!client_mutex) { - ESP_LOGE(TAG, "client_mutex Create failed "); - return; - } - coex_set_test_env("mutex", NULL, 0); - - bt_test_init(); - init_ble_gap_test_util(); - ret = esp_ble_gap_start_scanning(BLE_TC_SCAN_REPORT_PERIOD); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "esp_ble_gap_start_scanning error, %d", ret); - return ; - } - ret = create_sync_timer(&sync_obj.sync_timer); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "sync timer create failed"); - return ; - } - -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - excute_case(sync_obj.own_wifi_case); - vTaskDelay(3000 / portTICK_PERIOD_MS); -#endif - -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/sync.h b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/sync.h deleted file mode 100644 index d45325f4486..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/sync.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef __SYNC_H__ -#define __SYNC_H__ - -#include -#include -#include -#include -#include "esp_log.h" -#include "esp_timer.h" -#include "ble_unit.h" -#include "test_env.h" - -#include "esp_bt.h" -#include "esp_bt_main.h" -#include "esp_bt_device.h" -#include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" -#include "freertos/task.h" -#include "freertos/queue.h" - -#include "mesh/utils.h" -#define PARAM_MAX 7 - -#define SYNC_TIMEOUT 500000 //500ms -#define PARAMTER(value) (((uint32_t)value) << 7) - -#define WIFI_TCP_TX_CASE 0x0 -#define WIFI_TCP_RX_CASE 0x1 -#define BLE_ADV_CASE 0x2 -#define BLE_SCAN_CASE 0x3 -#define NOT_CASE 0xff - -#define MSG_HEAD 0xcbb3 -#define MSG_TYPE 0xff -#define MSG_CONTINUE 0x0 -#define MSG_END 0x1 -#define MSG_DATA_BASE 0x8 -#define MSG_ID_ASSIGN_CASE 0x1 -#define MSG_ID_WIFI_DEV_INIT_FINISH 0x2 -#define MSG_ID_BT_DEV_INIT_FINISH 0x3 -#define MSG_ID_START_CASE 0x4 - -#define BLE_CASE_ID 0b100000 << PARAM_MAX -#define WIFI_CASE_ID 0b010000 << PARAM_MAX -#define SERVER_IP 0b001000 << PARAM_MAX -#define START_TIME 0b000100 << PARAM_MAX -#define WIFI_SSID 0b000010 << PARAM_MAX -#define WIFI_PASSWIRD 0b000001 << PARAM_MAX - - -#define GET_PARAM(value,bit) (((value) & (bit)) ? bit:0x0) - -#define MSG_MIN_LEN 8 - -typedef void (*sync_recv)(uint8_t *raw_data, uint32_t raw_data_len); - -typedef struct { - uint8_t length; - uint8_t type; - uint16_t head; - uint8_t msg_id; - uint16_t ctl: 3, - param_bit: 13; -} __attribute__((packed)) sync_msg_head; - -typedef struct { - uint8_t length; - uint8_t type; - uint16_t head; - uint8_t msg_id; - uint16_t ctl: 3, - param_bit: 13; - uint8_t reserve; //reserved for extend param_bit - uint8_t data[23]; -} __attribute__((packed)) sync_msg; - -typedef struct { - uint8_t case_id; - const uint16_t excpet_param_bit; -} auto_tc; -extern auto_tc auto_tb[6]; - - -typedef enum { -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - ASSIGN_CASE, -#else - WAIT_CASE, - WAIT_START, -#endif - START_CASE, -} sync_state; - -struct sync_t { - sync_state state; - uint8_t own_wifi_case; - uint8_t own_ble_case; - uint8_t start_time; - - uint16_t recv_param_bit; - - bool except_recv_wifi_id; - bool except_recv_bt_id; - - esp_timer_handle_t sync_timer; - sync_recv cmd_recv; -}; -extern struct sync_t sync_obj; - -extern SemaphoreHandle_t client_mutex; -void sync_init(void); - -#endif diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/test_env.c b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/test_env.c deleted file mode 100644 index 636990b0480..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/test_env.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include - -#include "esp_err.h" -#include "esp_log.h" -#include "test_env.h" -#include "sync.h" - -#define TAG "ENV" - -coex_test_env_t test_env = { -#if defined(CONFIG_EXAMPLE_MANAUL) - .ap_ssid = CONFIG_EXAMPLE_WIFI_SSID, - .ap_password = CONFIG_EXAMPLE_WIFI_PASSWORD, -#endif -#if defined(CONFIG_EXAMPLE_COEX_ROLE) - .ap_ssid = CONFIG_EXAMPLE_WIFI_SSID, - .ap_password = CONFIG_EXAMPLE_WIFI_PASSWORD, -#endif - .test_port = "8080", - .server_ip = "192.168.3.32", - .duration = "120000", - .is_start = false, -}; - -esp_err_t coex_set_test_env(const char *keyword, const char *value, uint8_t length) -{ - esp_err_t ret = ESP_OK; - if (!strcmp(keyword, "ap_ssid")) { - memset(test_env.ap_ssid, '\0', sizeof(test_env.ap_ssid)); - strncpy(test_env.ap_ssid, value, length); - } else if (!strcmp(keyword, "ap_password")) { - memset(test_env.ap_password, '\0', sizeof(test_env.ap_password)); - strncpy(test_env.ap_password, value, length); - } else if (!strcmp( keyword, "test_port")) { - memset(test_env.test_port, '\0', sizeof(test_env.test_port)); - strncpy(test_env.test_port, value, length); - } else if (!strcmp(keyword, "server_ip")) { - memset(test_env.server_ip, '\0', sizeof(test_env.server_ip)); - strncpy(test_env.server_ip, value, length); - } else if (!strcmp(keyword, "duration")) { - strncpy(test_env.duration, value, length); - } else if (!strcmp(keyword, "mutex")) { - test_env.run_mutex = client_mutex; - - } else { - ret = ESP_ERR_NOT_SUPPORTED; - } - return ret; -} - -const char *coex_get_test_env(const char *keyword) -{ - const char *ret = NULL; - if (!strcmp(keyword, "ap_ssid")) { - ret = test_env.ap_ssid; - } else if (!strcmp(keyword, "ap_password")) { - ret = test_env.ap_password; - } else if (!strcmp(keyword, "test_port")) { - ret = test_env.test_port; - } else if (!strcmp(keyword, "server_ip")) { - ret = test_env.server_ip; - } else if (!strcmp(keyword, "duration")) { - ret = test_env.duration; - } - return ret; -} - -void coex_print_test_env(void) -{ - ESP_LOGI(TAG, "current test env:"); - ESP_LOGI(TAG, "\tap_ssid: %s", test_env.ap_ssid); - ESP_LOGI(TAG, "\tap_password: %s", test_env.ap_password); - ESP_LOGI(TAG, "\ttest_port: %s", test_env.test_port); - ESP_LOGI(TAG, "\tserver_ip: %s", test_env.server_ip); - ESP_LOGI(TAG, "\tduration: %s", test_env.duration); -} - -bool coex_env_str_to_mac(uint8_t *str, uint8_t *dest) -{ - uint8_t loop = 0; - uint8_t tmp = 0; - uint8_t *src_p = str; - - if (strlen((char *)src_p) != 17) { // must be like 12:34:56:78:90:AB - ESP_LOGE(TAG, "wrong format"); - return false; - } - - for (loop = 0; loop < 17 ; loop++) { - if (loop % 3 == 2) { - if (src_p[loop] != ':') { - ESP_LOGE(TAG, "wrong format"); - return false; - } - - continue; - } - - if ((src_p[loop] >= '0') && (src_p[loop] <= '9')) { - tmp = tmp * 16 + src_p[loop] - '0'; - } else if ((src_p[loop] >= 'A') && (src_p[loop] <= 'F')) { - tmp = tmp * 16 + src_p[loop] - 'A' + 10; - } else if ((src_p[loop] >= 'a') && (src_p[loop] <= 'f')) { - tmp = tmp * 16 + src_p[loop] - 'a' + 10; - } else { - ESP_LOGE(TAG, "wrong format"); - return false; - } - - if (loop % 3 == 1) { - *dest++ = tmp; - tmp = 0; - } - } - - return true; -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/test_env.h b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/test_env.h deleted file mode 100644 index e17eb0c35e1..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/test_env.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef __TEST_ENV_H__ -#define __TEST_ENV_H__ - -#include -#include "esp_err.h" -#include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" - -#define MAX_SSID_LEN 32 -#define MAX_PASSWORD_LEN 64 -#define MAX_IP_STR_LEN 15 -#define MAX_PORT_STR_LEN 5 -#define MAX_MAC_ADDR_LEN 17 -#define INVALID_REMOTE_BT_MAC "ff:ff:ff:ff:ff:ff" -#define DURATION_MAX_LEN 10 - -typedef struct { - char ap_ssid[MAX_SSID_LEN + 1]; - char ap_password[MAX_PASSWORD_LEN + 1]; - char test_port[MAX_PORT_STR_LEN + 1]; - char server_ip[MAX_IP_STR_LEN + 1]; - char duration[DURATION_MAX_LEN + 1]; - bool is_start; - SemaphoreHandle_t run_mutex; -} coex_test_env_t; - -extern coex_test_env_t test_env; - -esp_err_t coex_set_test_env(const char *keyword, const char *value, uint8_t length); -const char *coex_get_test_env(const char *keyword); -void coex_print_test_env(void); -bool coex_env_str_to_mac(uint8_t *str, uint8_t *dest); - -#endif /* __TEST_ENV_H__ */ diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_connect.c b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_connect.c deleted file mode 100644 index 6ceb5c42654..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_connect.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include - -#include "esp_err.h" -#include "esp_log.h" - -#include "wifi_connect.h" - - -#include -#include "sdkconfig.h" -#include "esp_event.h" -#include "esp_wifi.h" -#include "esp_wifi_default.h" - -#include "esp_log.h" -#include "esp_netif.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/event_groups.h" -#include "lwip/err.h" -#include "lwip/sys.h" - -#define GOT_IPV4_BIT BIT(0) - -#define CONNECTED_BITS (GOT_IPV4_BIT) - - -static EventGroupHandle_t s_connect_event_group; -static esp_ip4_addr_t s_ip_addr; -static const char *s_connection_name; -static esp_netif_t *s_example_esp_netif = NULL; - - - -static const char *TAG = "example_connect"; - -/* set up connection, Wi-Fi or Ethernet */ -static void start(const char *ssid, const char *passwd); - -/* tear down connection, release resources */ -static void stop(void); - -static void on_got_ip(void *arg, esp_event_base_t event_base, - int32_t event_id, void *event_data) -{ - ESP_LOGI(TAG, "Got IP event!"); - ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data; - memcpy(&s_ip_addr, &event->ip_info.ip, sizeof(s_ip_addr)); - xEventGroupSetBits(s_connect_event_group, GOT_IPV4_BIT); -} - -esp_err_t example_connect(const char *ssid, const char *passwd) -{ - if (s_connect_event_group != NULL) { - return ESP_ERR_INVALID_STATE; - } - s_connect_event_group = xEventGroupCreate(); - start(ssid, passwd); - ESP_ERROR_CHECK(esp_register_shutdown_handler(&stop)); - ESP_LOGI(TAG, "Waiting for IP"); - xEventGroupWaitBits(s_connect_event_group, CONNECTED_BITS, true, true, portMAX_DELAY); - ESP_LOGI(TAG, "Connected to %s", s_connection_name); - ESP_LOGI(TAG, "IPv4 address: " IPSTR, IP2STR(&s_ip_addr)); - return ESP_OK; -} - -esp_err_t example_disconnect(void) -{ - if (s_connect_event_group == NULL) { - return ESP_ERR_INVALID_STATE; - } - vEventGroupDelete(s_connect_event_group); - s_connect_event_group = NULL; - stop(); - ESP_LOGI(TAG, "Disconnected from %s", s_connection_name); - s_connection_name = NULL; - return ESP_OK; -} - - -static void on_wifi_disconnect(void *arg, esp_event_base_t event_base, - int32_t event_id, void *event_data) -{ - ESP_LOGI(TAG, "Wi-Fi disconnected, trying to reconnect..."); - esp_err_t err = esp_wifi_connect(); - if (err == ESP_ERR_WIFI_NOT_STARTED) { - return; - } - ESP_ERROR_CHECK(err); -} - -static void start(const char *ssid, const char *passwd) -{ - wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); - ESP_ERROR_CHECK(esp_wifi_init(&cfg)); - - esp_netif_config_t netif_config = ESP_NETIF_DEFAULT_WIFI_STA(); - - esp_netif_t *netif = esp_netif_new(&netif_config); - - assert(netif); - - esp_netif_attach_wifi_station(netif); - esp_wifi_set_default_wifi_sta_handlers(); - - s_example_esp_netif = netif; - - ESP_ERROR_CHECK(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_STA_DISCONNECTED, &on_wifi_disconnect, NULL)); - ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_STA_GOT_IP, &on_got_ip, NULL)); - ESP_ERROR_CHECK(esp_wifi_set_storage(WIFI_STORAGE_RAM)); - - wifi_config_t wifi_config; - memset(&wifi_config, 0, sizeof(wifi_config)); - if (ssid) { - strncpy((char *)wifi_config.sta.ssid, ssid, strlen(ssid)); - } - if (passwd) { - strncpy((char *)wifi_config.sta.password, passwd, strlen(passwd)); - } - - ESP_LOGI(TAG, "Connecting to %s...", wifi_config.sta.ssid); - ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); - ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); - ESP_ERROR_CHECK(esp_wifi_start()); - esp_wifi_connect(); - s_connection_name = ssid; -} - -static void stop(void) -{ - ESP_ERROR_CHECK(esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_STA_DISCONNECTED, &on_wifi_disconnect)); - ESP_ERROR_CHECK(esp_event_handler_unregister(IP_EVENT, IP_EVENT_STA_GOT_IP, &on_got_ip)); - esp_err_t err = esp_wifi_stop(); - if (err == ESP_ERR_WIFI_NOT_INIT) { - return; - } - ESP_ERROR_CHECK(err); - ESP_ERROR_CHECK(esp_wifi_deinit()); - ESP_ERROR_CHECK(esp_wifi_clear_default_wifi_driver_and_handlers(s_example_esp_netif)); - esp_netif_destroy(s_example_esp_netif); - s_example_esp_netif = NULL; -} - -esp_netif_t *get_example_netif(void) -{ - return s_example_esp_netif; -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_connect.h b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_connect.h deleted file mode 100644 index 774a409c2ff..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_connect.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef __WIFI_CONNECT_H__ -#define __WIFI_CONNECT_H__ - -#include "esp_err.h" -#include "esp_netif.h" -#include "esp_event.h" - -esp_err_t example_connect(const char *ssid, const char *passwd); -esp_err_t example_disconnect(void); -esp_err_t example_configure_stdin_stdout(void); -esp_netif_t *get_example_netif(void); - -#endif /* __WIFI_CONNECT_H__ */ diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_unit.c b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_unit.c deleted file mode 100644 index 15feed083fe..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_unit.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include -#include -#include - -#include "wifi_unit.h" -#include "wifi_connect.h" -#define TAG "WIFI_UINT" - -uint32_t utils_get_system_ts(void) -{ - return esp_log_timestamp(); -} - -esp_err_t wifi_unit_client_establish(int *sock, const char *ip, const char *port) -{ - esp_err_t ret = 0; - uint32_t start_ts; - uint32_t timeout = 10000; - struct sockaddr_in sock_addr; - int s; - - memset(&sock_addr, 0, sizeof(sock_addr)); - sock_addr.sin_family = AF_INET; - sock_addr.sin_addr.s_addr = ipaddr_addr(ip); - sock_addr.sin_port = htons(atoi(port)); - - start_ts = utils_get_system_ts(); - do { - s = socket(AF_INET, SOCK_STREAM, IPPROTO_IP); - if (s < 0) { - ESP_LOGE(TAG, "Unable to create socket: errno %d", errno); - } - ret = connect(s, (struct sockaddr *)&sock_addr, sizeof(sock_addr)); - if (ret == 0) { - *sock = s; - break; - } else if (s > 0) { - close(s); - } - } while (utils_get_system_ts() - start_ts < timeout); - return ret; -} - -esp_err_t wifi_unit_server_establish(int *socket_id, const char *port) -{ - esp_err_t ret = -1; - struct sockaddr_in local_addr; - uint32_t local_ip; - - static int ls_sock = -1; - - local_ip = wifi_util_get_ip(); - - if (ls_sock < 0) { - ls_sock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP); - if (ls_sock < 0) { - ESP_LOGE(TAG, "create socket failed"); - return ls_sock; - } - - local_addr.sin_family = AF_INET; - local_addr.sin_port = htons(atoi(port)); - local_addr.sin_addr.s_addr = local_ip; - ret = bind(ls_sock, (struct sockaddr *)&local_addr, sizeof(local_addr)); - if (ret != 0) { - ESP_LOGE(TAG, "socket bind failed"); - return ret; - } - - ret = listen(ls_sock, 1); - if (ret < 0) { - ESP_LOGE(TAG, "socket listen failed"); - return ret; - } - } - - struct sockaddr_in6 sourceAddr; // Large enough for both IPv4 or IPv6 - socklen_t addrLen = sizeof(sourceAddr); - *socket_id = accept(ls_sock, (struct sockaddr *)&sourceAddr, &addrLen); - if (*socket_id < 0) { - ESP_LOGE(TAG, "Unable to accept connection: errno %d", errno); - return -1; - } - ESP_LOGI(TAG, "Socket accepted"); - return ret; -} - -esp_err_t wifi_unit_tcp_recv(int socket_id, const char *duration, uint32_t user_date[]) -{ - esp_err_t ret = -1; - uint32_t start_ts; - uint8_t *buffer; - struct timeval tv_t; - uint32_t *recv_len = &user_date[1]; - tv_t.tv_sec = 1; - tv_t.tv_usec = 0; - ret = setsockopt(socket_id, SOL_SOCKET, SO_RCVTIMEO, &tv_t, sizeof(tv_t)); - - buffer = malloc(2920); - - if (buffer == NULL) { - ESP_LOGE(TAG, "%s malloc fail", __func__); - return ESP_ERR_NO_MEM; - } - - start_ts = utils_get_system_ts(); - - while (utils_get_system_ts() - start_ts < atoi(duration)) { - ret = recv(socket_id, buffer, 2920, 0); - if (ret > 0) { - *recv_len = *recv_len + ret; - } else if (ret == 0) { - break; - } - } - free(buffer); - if (ret > 0 ) { - ret = ESP_OK; - } - return ret; -} - -esp_err_t wifi_util_tcp_send(int socket_id, uint32_t len, uint32_t delay, uint32_t *sent_len, uint32_t timeout) -{ - esp_err_t ret = ESP_OK; - uint32_t start_ts; - uint8_t *buffer; - - if ( len == 0) { - return ESP_ERR_INVALID_ARG; - } - buffer = malloc(len); - if (buffer == NULL) { - ESP_LOGE(TAG, "%s malloc fail", __func__); - return ESP_ERR_NO_MEM; - } - - start_ts = utils_get_system_ts(); - - while (utils_get_system_ts() - start_ts < timeout) { - ret = send(socket_id, buffer, len, 0); - if (ret < 0) { - ESP_LOGE(TAG, "recv failed: errno %d", errno); - break; - } - *sent_len = *sent_len + ret; - - if (delay) { - vTaskDelay(delay / portTICK_PERIOD_MS); - } - } - if (ret == len) { - ret = ESP_OK; - } else { - ESP_LOGE(TAG, "tcp send error, %d", ret); - ret = -2; - } - - free(buffer); - - return ret; -} - -uint32_t wifi_util_get_ip(void) -{ - esp_netif_ip_info_t ip_info; - esp_netif_t *netif = get_example_netif(); - esp_netif_get_ip_info(netif, &ip_info); - return ip_info.ip.addr; -} - -void wifi_util_init(void) -{ - ESP_ERROR_CHECK(nvs_flash_init()); - ESP_ERROR_CHECK(esp_netif_init()); - ESP_ERROR_CHECK(esp_event_loop_create_default()); -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_unit.h b/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_unit.h deleted file mode 100644 index f702e2fbf16..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/components/case/wifi_unit.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef _WIFI_UNIT_H -#define _WIFI_UNIT_H - -#include "esp_wifi_types.h" -#include "esp_wifi.h" -#include "esp_event.h" -#include "esp_log.h" -#include "esp_timer.h" -#include "nvs_flash.h" - -#include "esp_netif.h" - -#include "lwip/err.h" -#include "lwip/sockets.h" -#include "lwip/sys.h" -#include "lwip/netdb.h" -#include "lwip/dns.h" - -uint32_t utils_get_system_ts(void); - -void wifi_util_init(void); - -uint32_t wifi_util_get_ip(void); -esp_err_t wifi_unit_client_establish(int *sock, const char *ip, const char *port); -esp_err_t wifi_unit_server_establish(int *socket_id, const char *port); - -esp_err_t wifi_unit_tcp_recv(int socket_id, const char *duration, uint32_t user_date[]); -esp_err_t wifi_util_tcp_send(int socket_id, uint32_t len, uint32_t delay, uint32_t *sent_len, uint32_t timeout); -#endif /* _WIFI_UNIT_H */ diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/main/CMakeLists.txt b/examples/bluetooth/esp_ble_mesh/coex_test/main/CMakeLists.txt deleted file mode 100644 index db5b9da87e4..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/main/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -idf_component_register(SRCS "main.c" "coex_cmd.c" - INCLUDE_DIRS "." - REQUIRED_IDF_TARGETS esp32) diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/coex_test/main/Kconfig.projbuild deleted file mode 100644 index cf4ef2778c3..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/main/Kconfig.projbuild +++ /dev/null @@ -1,70 +0,0 @@ -menu "Example Configuration" - - choice EXAMPLE_RUN_MODE - prompt "select run mode" - help - select run mode - - config EXAMPLE_AUTO - bool "auto" - help - In automatic mode, the program coordinates three development board work - through a synchronization mechanism. - - config EXAMPLE_MANAUL - bool "manual" - help - In manual mode, you will work with three development boards via commands. - endchoice - - config EXAMPLE_WIFI_SSID - depends on EXAMPLE_MANAUL - string "WiFi SSID" - help - SSID (network name) for the example to connect to. The length cannot exceed 20 bytes. - config EXAMPLE_WIFI_PASSWORD - depends on EXAMPLE_MANAUL - string "WiFi Password" - help - WiFi password (WPA or WPA2) for the example to use. - Can be left blank if the network has no security set. - The length cannot exceed 20 bytes. - - choice EXAMPLE_SELECT_ROLE - prompt "select role" - depends on EXAMPLE_AUTO - config EXAMPLE_COEX_ROLE - bool "run device as coex role" - config EXAMPLE_WIFI_ROLE - bool "run device as wifi role" - config EXAMPLE_BT_ROLE - bool "run device as bluetooth role" - endchoice - - choice EXAMPLE_SELECT_CASE - prompt "select case" - depends on EXAMPLE_COEX_ROLE - config EXAMPLE_COEX_TX_ADV - bool "TCP TX and BLE ADV" - config EXAMPLE_COEX_RX_ADV - bool "TCP RX and BLE ADV" - config EXAMPLE_COEX_TX_SCAN - bool "TCP TX and BLE SCAN" - config EXAMPLE_COEX_RX_SCAN - bool "TCP RX and BLE SCAN" - endchoice - - config EXAMPLE_WIFI_SSID - depends on EXAMPLE_COEX_ROLE - string "WiFi SSID" - help - SSID (network name) for the example to connect to. The length cannot exceed 20 bytes. - config EXAMPLE_WIFI_PASSWORD - depends on EXAMPLE_COEX_ROLE - string "WiFi Password" - help - WiFi password (WPA or WPA2) for the example to use. - Can be left blank if the network has no security set. - The length cannot exceed 20 bytes. - -endmenu #"Example Configuration End" diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/main/coex_cmd.c b/examples/bluetooth/esp_ble_mesh/coex_test/main/coex_cmd.c deleted file mode 100644 index e1f39052a08..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/main/coex_cmd.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include -#include "esp_log.h" -#include "esp_mac.h" -#include "esp_console.h" -#include "argtable3/argtable3.h" - -#include "esp_bt.h" -#include "esp_bt_main.h" -#include "esp_bt_device.h" - -#include "run_tc.h" -#include "test_env.h" - - -#define TAG_CNSL "CNSL" - -typedef struct { - struct arg_str *wifi_tc_idx; - struct arg_str *bt_tc_idx; - struct arg_end *end; -} tc_run_args_t; - -typedef struct { - struct arg_lit *set; - struct arg_lit *get; - struct arg_str *key; - struct arg_str *value; - struct arg_end *end; -} env_param_cmd_args_t; - -static tc_run_args_t tc_run_args; -static env_param_cmd_args_t env_param_cmd_args; - -static int process_env_parameter_cmd(int argc, char **argv) -{ - int nerrors = arg_parse(argc, argv, (void **) &env_param_cmd_args); - int ret; - const char *env_value = ""; - - if (nerrors != 0) { - arg_print_errors(stderr, env_param_cmd_args.end, argv[0]); - return 1; - } - if (env_param_cmd_args.set->count == 1) { - if (env_param_cmd_args.key->count == 1) { - if (env_param_cmd_args.value->count == 1) { - env_value = env_param_cmd_args.value->sval[0]; - } - ret = coex_set_test_env(env_param_cmd_args.key->sval[0], env_value, strlen(env_param_cmd_args.value->sval[0])); - if (ret == ESP_ERR_NOT_SUPPORTED) { - ESP_LOGE(TAG_CNSL, "Not supported env key"); - } else if (ret == ESP_ERR_INVALID_ARG) { - ESP_LOGE(TAG_CNSL, "Invalid value"); - } - ESP_LOGI(TAG_CNSL, "env set done"); - } else { - ESP_LOGE(TAG_CNSL, "env key not set correctly"); - } - } else if (env_param_cmd_args.get->count == 1) { - coex_print_test_env(); - } - return 0; -} - -static int process_restart_cmd(int argc, char **argv) -{ - ESP_LOGI(TAG_CNSL, "restarting..."); - esp_restart(); - return 0; -} - - -static int process_run_tc_cmd(int argc, char **argv) -{ - run_task_msg_t msg; - int nerrors = arg_parse(argc, argv, (void **) &tc_run_args); - if (nerrors != 0) { - arg_print_errors(stderr, tc_run_args.end, argv[0]); - return 1; - } - - if (tc_run_args.wifi_tc_idx->count == 1) { - msg.case_id = atoi(tc_run_args.wifi_tc_idx->sval[0]); - if (xQueueSend(xTaskQueue, &msg, portMAX_DELAY) != pdTRUE) { - ESP_LOGE(TAG_CNSL, "xTaskQueue Post failed"); - } - } - - if (tc_run_args.bt_tc_idx->count == 1) { - msg.case_id = atoi(tc_run_args.bt_tc_idx->sval[0]); - if (xQueueSend(xTaskQueue, &msg, portMAX_DELAY) != pdTRUE) { - ESP_LOGE(TAG_CNSL, "xTaskQueue Post failed"); - } - } - - return 0; -} - -static int process_get_mac_addr_cmd(int argc, char **argv) -{ - const uint8_t *mac = esp_bt_dev_get_address(); - - if (mac != NULL) { - ESP_LOGI(TAG_CNSL, "+BTMAC:"MACSTR, MAC2STR(mac)); - } - return 0; -} -void register_coex_cmd(void) -{ - const esp_console_cmd_t restart_cmd = { - .command = "restart", - .help = "restart cmd", - .hint = NULL, - .func = &process_restart_cmd, - .argtable = NULL - }; - - ESP_ERROR_CHECK( esp_console_cmd_register(&restart_cmd) ); - - const esp_console_cmd_t get_mac_cmd = { - .command = "mac", - .help = "Get DUT mac address", - .hint = NULL, - .func = &process_get_mac_addr_cmd, - .argtable = NULL - }; - - ESP_ERROR_CHECK( esp_console_cmd_register(&get_mac_cmd) ); - - tc_run_args.wifi_tc_idx = arg_str0("w", "wifi", "", "0 : wifi_tcp_tx_throught 1 : wifi_tcp_rx_throught\n"); - tc_run_args.bt_tc_idx = arg_str0("b", "bluetooth", "", "2 :ble_adv 3 : ble_scan\n"); - tc_run_args.end = arg_end(2); - - const esp_console_cmd_t run_tc_cmd = { - .command = "run_tc", - .help = "run wifi bt test case command", - .hint = NULL, - .func = &process_run_tc_cmd, - .argtable = &tc_run_args - }; - - ESP_ERROR_CHECK( esp_console_cmd_register(&run_tc_cmd) ); - - env_param_cmd_args.set = arg_lit0("s", "set", "set env parameter"); - env_param_cmd_args.get = arg_lit0("g", "get", "get env parameter"); - env_param_cmd_args.key = arg_str0("k", "key", "", "env parameter key"); - env_param_cmd_args.value = arg_str0("v", "value", "", "env parameter value (only used with set)"); - env_param_cmd_args.end = arg_end(4); - - const esp_console_cmd_t env_cmd = { - .command = "env", - .help = "Set or get test environment parameters", - .hint = NULL, - .func = &process_env_parameter_cmd, - .argtable = &env_param_cmd_args, - }; - - ESP_ERROR_CHECK( esp_console_cmd_register(&env_cmd) ); -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/main/coex_cmd.h b/examples/bluetooth/esp_ble_mesh/coex_test/main/coex_cmd.h deleted file mode 100644 index 4340c148424..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/main/coex_cmd.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#ifndef MAIN_COEX_CMD_H_ -#define MAIN_COEX_CMD_H_ - -#define CNSL_CMD_OUTPUT_PREFIX "COEX_CNSL_OUTPUT" -void register_coex_cmd(void); - -#endif /* MAIN_COEX_CMD_H_ */ diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/main/main.c b/examples/bluetooth/esp_ble_mesh/coex_test/main/main.c deleted file mode 100644 index f0e01d47550..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/main/main.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * ESP BLE Mesh Example - * - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include -#include "esp_system.h" -#include "esp_log.h" -#include "esp_console.h" -#include "esp_vfs_dev.h" -#include "esp_vfs_fat.h" -#include "nvs.h" -#include "nvs_flash.h" -#include "esp_coexist.h" -#include "coex_cmd.h" -#include "run_tc.h" -#include "sync.h" - -static void initialize_nvs(void) -{ - esp_err_t err = nvs_flash_init(); - if (err == ESP_ERR_NVS_NO_FREE_PAGES || err == ESP_ERR_NVS_NEW_VERSION_FOUND) { - ESP_ERROR_CHECK( nvs_flash_erase() ); - err = nvs_flash_init(); - } - ESP_ERROR_CHECK(err); -} - -void app_main(void) -{ - initialize_nvs(); - run_tc_init(); - - esp_console_repl_t *repl = NULL; - esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); - repl_config.prompt = "ble_mesh_coex>"; - // install console REPL environment -#if CONFIG_ESP_CONSOLE_UART - esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); - ESP_ERROR_CHECK(esp_console_new_repl_uart(&uart_config, &repl_config, &repl)); -#elif CONFIG_ESP_CONSOLE_USB_CDC - esp_console_dev_usb_cdc_config_t cdc_config = ESP_CONSOLE_DEV_CDC_CONFIG_DEFAULT(); - ESP_ERROR_CHECK(esp_console_new_repl_usb_cdc(&cdc_config, &repl_config, &repl)); -#elif CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG - esp_console_dev_usb_serial_jtag_config_t usbjtag_config = ESP_CONSOLE_DEV_USB_SERIAL_JTAG_CONFIG_DEFAULT(); - ESP_ERROR_CHECK(esp_console_new_repl_usb_serial_jtag(&usbjtag_config, &repl_config, &repl)); -#endif - - register_coex_cmd(); - -#if defined(CONFIG_EXAMPLE_AUTO) - sync_init(); -#endif - - /* Prompt to be printed before each line. - * This can be customized, made dynamic, etc. - */ - printf("esp-idf version: %s\n\n", esp_get_idf_version()); - printf("coexist version: %s\n\n", esp_coex_version_get()); - - // start console REPL - ESP_ERROR_CHECK(esp_console_start_repl(repl)); -} diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/partitions.csv b/examples/bluetooth/esp_ble_mesh/coex_test/partitions.csv deleted file mode 100644 index 612494574f1..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/partitions.csv +++ /dev/null @@ -1,5 +0,0 @@ -# Name, Type, SubType, Offset, Size, Flags -# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild -nvs, data, nvs, 0x9000, 0x6000, -phy_init, data, phy, 0xf000, 0x1000, -factory, app, factory, 0x10000, 0x1F0000, diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults b/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults deleted file mode 100644 index 95cd5303361..00000000000 --- a/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults +++ /dev/null @@ -1,109 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Espressif IoT Development Framework Configuration -# - -# -# SDK tool configuration -# -CONFIG_SDK_MAKE_WARN_UNDEFINED_VARIABLES=y -# -# Partition Table -# -# CONFIG_PARTITION_TABLE_SINGLE_APP is not set -# CONFIG_PARTITION_TABLE_TWO_OTA is not set -CONFIG_PARTITION_TABLE_CUSTOM=y -CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" -CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET=0x10000 -CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" -CONFIG_APP_OFFSET=0x10000 - - -# -# Serial flasher config -# -CONFIG_ESPTOOLPY_BAUD_921600B=y -CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y -CONFIG_ESPTOOLPY_FLASHFREQ_80M=y - -# -# Component config -# -# -# Bluetooth -# -CONFIG_BT_ENABLED=y -CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y -CONFIG_BTDM_CTRL_PINNED_TO_CORE=1 -CONFIG_CTRL_BTDM_MODEM_SLEEP=n -CONFIG_BTDM_BLE_SCAN_DUPL=y -CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y -CONFIG_BT_BLUEDROID_ENABLED=y -CONFIG_BT_BLUEDROID_PINNED_TO_CORE_1=y -CONFIG_BT_BTU_TASK_STACK_SIZE=4512 -CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y -CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=y -CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=y -CONFIG_BT_SMP_ENABLE=y -CONFIG_BTDM_RESERVE_DRAM=0x10000 - -# -# ESP32-specific -# -CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y -CONFIG_SPIRAM=y -CONFIG_SPIRAM_SPEED_80M=y -CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=4096 -CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y -CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=6 -CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 -CONFIG_SPIRAM_IGNORE_NOTFOUND=y - -# -# Wi-Fi -# -CONFIG_ESP_COEX_SW_COEXIST_ENABLE=y -CONFIG_ESP_WIFI_SW_COEXIST_PREFERENCE_BALANCE=y -CONFIG_ESP_WIFI_SW_COEXIST_PREFERENCE_VALUE=2 -CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=16 -CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=64 -CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y -CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0 -CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16 -CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y -CONFIG_ESP_WIFI_TX_BA_WIN=16 -CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y -CONFIG_ESP_WIFI_RX_BA_WIN=16 -CONFIG_ESP_WIFI_NVS_ENABLED=y -CONFIG_ESP_WIFI_MGMT_SBUF_NUM=6 - -# -# FreeRTOS -# -CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=1536 -CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=5 -CONFIG_FREERTOS_HZ=1000 - -# -# LWIP -# -CONFIG_LWIP_IP_FRAG=y -CONFIG_LWIP_IP_REASSEMBLY=y -CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=64 -CONFIG_LWIP_TCP_SND_BUF_DEFAULT=65534 -CONFIG_LWIP_TCP_WND_DEFAULT=65534 -CONFIG_LWIP_TCP_RECVMBOX_SIZE=64 -CONFIG_LWIP_UDP_RECVMBOX_SIZE=64 -CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0=y -CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x0 - -# -# ble mesh -# -CONFIG_BLE_MESH=y -CONFIG_BLE_MESH_NODE=y -CONFIG_BLE_MESH_PB_GATT=y -CONFIG_BLE_MESH_TX_SEG_MSG_COUNT=10 -CONFIG_BLE_MESH_RX_SEG_MSG_COUNT=10 -CONFIG_BLE_MESH_GENERIC_ONOFF_CLI=y diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c6 index 58ccc4d7a91..953de2c3d8d 100644 --- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c6 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32h2 index eeb1aec96e0..264e1ca692b 100644 --- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32h2 @@ -2,8 +2,6 @@ ##Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c6 index 78299bedf8d..d34bbf4ea3f 100644 --- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c6 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32h2 index 78299bedf8d..d34bbf4ea3f 100644 --- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32h2 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c6 index 94eb97b170f..65d06b5bcd3 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32h2 index 94eb97b170f..65d06b5bcd3 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.adv_scan b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.adv_scan index 83867c5ed1a..059ba29f132 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.adv_scan +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.adv_scan @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c6 index 5922d020134..b6a06a69431 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32h2 index 5922d020134..b6a06a69431 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c6 index 4569c251fc5..acfc8840e0d 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32h2 index 76a20f22e01..7757ba4f3b4 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32h2 @@ -3,7 +3,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.adv b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.adv index 3e13ad16d70..1bf27c1522f 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.adv +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.adv @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.bluedroid_log b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.bluedroid_log index 32a770f443c..923b5f9b6d8 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.bluedroid_log +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.bluedroid_log @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.nimble_log b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.nimble_log index e52e3bc5aa7..8400f85f6f5 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.nimble_log +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.nimble_log @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_NIMBLE_ENABLED=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.scan b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.scan index e300e76fca2..b9852e7177f 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.scan +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.ci.scan @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c6 index 5e455a7905c..5e225b42382 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32h2 index 5e455a7905c..5e225b42382 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.adv b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.adv index 19bdb75b029..9ceb4e4f3f1 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.adv +++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.adv @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs00 b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs00 index 8fec056f230..d16d737c311 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs00 +++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs00 @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs01 b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs01 index f8b0ea1ec1e..aeaf1a1c259 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs01 +++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.nvs01 @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.scan b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.scan index 48a4d1e9b56..c3be443fdc0 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.scan +++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.ci.scan @@ -2,7 +2,6 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n -CONFIG_BTDM_MODEM_SLEEP=n CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c6 index b87a9d10c4d..0ad62c2f04f 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32h2 index b87a9d10c4d..0ad62c2f04f 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c6 index 58ccc4d7a91..953de2c3d8d 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c6 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32h2 index 58ccc4d7a91..953de2c3d8d 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32h2 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c6 index 78299bedf8d..d34bbf4ea3f 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c6 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32h2 index 78299bedf8d..d34bbf4ea3f 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32h2 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c6 index 78299bedf8d..d34bbf4ea3f 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c6 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32h2 index 78299bedf8d..d34bbf4ea3f 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32h2 @@ -1,8 +1,6 @@ # Override some defaults so BT stack is enabled # by default in this example CONFIG_BT_ENABLED=y -CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c6 index 49528a193eb..6502ad92ce4 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32h2 index 49528a193eb..6502ad92ce4 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c6 index 5e455a7905c..5e225b42382 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32h2 index 5e455a7905c..5e225b42382 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c6 index 2bdb1a41537..52d72b3c2e2 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32h2 index 2bdb1a41537..52d72b3c2e2 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c6 index 5e455a7905c..5e225b42382 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32h2 b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32h2 index 5e455a7905c..5e225b42382 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32h2 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y CONFIG_BT_BTU_TASK_STACK_SIZE=4512 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c6 b/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c6 index bff73fae10c..7b05fb98466 100644 --- a/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c6 @@ -2,7 +2,6 @@ # by default in this example CONFIG_BT_ENABLED=y CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y -CONFIG_BT_CTRL_BLE_MESH_SCAN_DUPL_EN=y CONFIG_BT_CTRL_COEX_PARAMETERS_ENABLE=y CONFIG_BT_CTRL_COEX_USE_HOOKS=y CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y diff --git a/examples/bluetooth/esp_hid_device/main/Kconfig.projbuild b/examples/bluetooth/esp_hid_device/main/Kconfig.projbuild index 568ef5ae62f..37da169d7bd 100644 --- a/examples/bluetooth/esp_hid_device/main/Kconfig.projbuild +++ b/examples/bluetooth/esp_hid_device/main/Kconfig.projbuild @@ -6,4 +6,33 @@ menu "HID Example Configuration" help This enables the Secure Simple Pairing. If disable this option, Bluedroid will only support Legacy Pairing + + choice EXAMPLE_HID_DEVICE_ROLE + prompt "HID Device Role" + depends on BT_NIMBLE_ENABLED + default EXAMPLE_MEDIA_ENABLE + help + Three Supported Roles for Device + - Media Device + - Keyboard + - Mouse + + config EXAMPLE_MEDIA_ENABLE + select BT_NIMBLE_HID_SERVICE + bool "Enable Media Device" + + config EXAMPLE_KBD_ENABLE + select BT_NIMBLE_HID_SERVICE + bool "Enable Keyboard Device" + + config EXAMPLE_MOUSE_ENABLE + select BT_NIMBLE_HID_SERVICE + bool "Enable Mouse Device" + endchoice + + config EXAMPLE_HID_DEVICE_ROLE + int + default 1 if EXAMPLE_MEDIA_ENABLE + default 2 if EXAMPLE_KBD_ENABLE + default 3 if EXAMPLE_MOUSE_ENABLE endmenu diff --git a/examples/bluetooth/esp_hid_device/main/esp_hid_device_main.c b/examples/bluetooth/esp_hid_device/main/esp_hid_device_main.c index 7e95cdb65f1..7f32ddb446b 100644 --- a/examples/bluetooth/esp_hid_device/main/esp_hid_device_main.c +++ b/examples/bluetooth/esp_hid_device/main/esp_hid_device_main.c @@ -18,6 +18,12 @@ #include "esp_log.h" #include "nvs_flash.h" #include "esp_bt.h" + +#if CONFIG_BT_NIMBLE_ENABLED +#include "host/ble_hs.h" +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#else #include "esp_bt_defs.h" #if CONFIG_BT_BLE_ENABLED #include "esp_gap_ble_api.h" @@ -26,6 +32,7 @@ #endif #include "esp_bt_main.h" #include "esp_bt_device.h" +#endif #include "esp_hidd.h" #include "esp_hid_gap.h" @@ -40,7 +47,7 @@ typedef struct uint8_t *buffer; } local_param_t; -#if CONFIG_BT_BLE_ENABLED +#if CONFIG_BT_BLE_ENABLED || CONFIG_BT_NIMBLE_ENABLED static local_param_t s_ble_hid_param = {0}; const unsigned char mediaReportMap[] = { @@ -102,19 +109,287 @@ const unsigned char mediaReportMap[] = { 0x81, 0x03, // Input (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position) 0xC0, // End Collection }; +#if CONFIG_EXAMPLE_HID_DEVICE_ROLE && CONFIG_EXAMPLE_HID_DEVICE_ROLE == 3 +const unsigned char mouseReportMap[] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xa1, 0x01, // COLLECTION (Application) + + 0x09, 0x01, // USAGE (Pointer) + 0xa1, 0x00, // COLLECTION (Physical) + + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, // USAGE (Wheel) + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (3) + 0x81, 0x06, // INPUT (Data,Var,Rel) + + 0xc0, // END_COLLECTION + 0xc0 // END_COLLECTION +}; +// send the buttons, change in x, and change in y +void send_mouse(uint8_t buttons, char dx, char dy, char wheel) +{ + static uint8_t buffer[4] = {0}; + buffer[0] = buttons; + buffer[1] = dx; + buffer[2] = dy; + buffer[3] = wheel; + esp_hidd_dev_input_set(s_ble_hid_param.hid_dev, 0, 0, buffer, 4); +} + +void ble_hid_demo_task_mouse(void *pvParameters) +{ + static const char* help_string = "########################################################################\n"\ + "BT hid mouse demo usage:\n"\ + "You can input these value to simulate mouse: 'q', 'w', 'e', 'a', 's', 'd', 'h'\n"\ + "q -- click the left key\n"\ + "w -- move up\n"\ + "e -- click the right key\n"\ + "a -- move left\n"\ + "s -- move down\n"\ + "d -- move right\n"\ + "h -- show the help\n"\ + "########################################################################\n"; + printf("%s\n", help_string); + char c; + while (1) { + c = fgetc(stdin); + switch (c) { + case 'q': + send_mouse(1, 0, 0, 0); + break; + case 'w': + send_mouse(0, 0, -10, 0); + break; + case 'e': + send_mouse(2, 0, 0, 0); + break; + case 'a': + send_mouse(0, -10, 0, 0); + break; + case 's': + send_mouse(0, 0, 10, 0); + break; + case 'd': + send_mouse(0, 10, 0, 0); + break; + case 'h': + printf("%s\n", help_string); + break; + default: + break; + } + vTaskDelay(10 / portTICK_PERIOD_MS); + } +} +#endif + +#if CONFIG_EXAMPLE_HID_DEVICE_ROLE && CONFIG_EXAMPLE_HID_DEVICE_ROLE == 2 +#define CASE(a, b, c) \ + case a: \ + buffer[0] = b; \ + buffer[2] = c; \ + break;\ + +// USB keyboard codes +#define USB_HID_MODIFIER_LEFT_CTRL 0x01 +#define USB_HID_MODIFIER_LEFT_SHIFT 0x02 +#define USB_HID_MODIFIER_LEFT_ALT 0x04 +#define USB_HID_MODIFIER_RIGHT_CTRL 0x10 +#define USB_HID_MODIFIER_RIGHT_SHIFT 0x20 +#define USB_HID_MODIFIER_RIGHT_ALT 0x40 + +#define USB_HID_SPACE 0x2C +#define USB_HID_DOT 0x37 +#define USB_HID_NEWLINE 0x28 +#define USB_HID_FSLASH 0x38 +#define USB_HID_BSLASH 0x31 +#define USB_HID_COMMA 0x36 +#define USB_HID_DOT 0x37 + +const unsigned char keyboardReportMap[] = { //7 bytes input (modifiers, resrvd, keys*5), 1 byte output + 0x05, 0x01, // Usage Page (Generic Desktop Ctrls) + 0x09, 0x06, // Usage (Keyboard) + 0xA1, 0x01, // Collection (Application) + 0x85, 0x01, // Report ID (1) + 0x05, 0x07, // Usage Page (Kbrd/Keypad) + 0x19, 0xE0, // Usage Minimum (0xE0) + 0x29, 0xE7, // Usage Maximum (0xE7) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x75, 0x01, // Report Size (1) + 0x95, 0x08, // Report Count (8) + 0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position) + 0x95, 0x01, // Report Count (1) + 0x75, 0x08, // Report Size (8) + 0x81, 0x03, // Input (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position) + 0x95, 0x05, // Report Count (5) + 0x75, 0x01, // Report Size (1) + 0x05, 0x08, // Usage Page (LEDs) + 0x19, 0x01, // Usage Minimum (Num Lock) + 0x29, 0x05, // Usage Maximum (Kana) + 0x91, 0x02, // Output (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile) + 0x95, 0x01, // Report Count (1) + 0x75, 0x03, // Report Size (3) + 0x91, 0x03, // Output (Const,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile) + 0x95, 0x05, // Report Count (5) + 0x75, 0x08, // Report Size (8) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x65, // Logical Maximum (101) + 0x05, 0x07, // Usage Page (Kbrd/Keypad) + 0x19, 0x00, // Usage Minimum (0x00) + 0x29, 0x65, // Usage Maximum (0x65) + 0x81, 0x00, // Input (Data,Array,Abs,No Wrap,Linear,Preferred State,No Null Position) + 0xC0, // End Collection + + // 65 bytes +}; + +static void char_to_code(uint8_t *buffer, char ch) +{ + // Check if lower or upper case + if(ch >= 'a' && ch <= 'z') + { + buffer[0] = 0; + // convert ch to HID letter, starting at a = 4 + buffer[2] = (uint8_t)(4 + (ch - 'a')); + } + else if(ch >= 'A' && ch <= 'Z') + { + // Add left shift + buffer[0] = USB_HID_MODIFIER_LEFT_SHIFT; + // convert ch to lower case + ch = ch - ('A'-'a'); + // convert ch to HID letter, starting at a = 4 + buffer[2] = (uint8_t)(4 + (ch - 'a')); + } + else if(ch >= '0' && ch <= '9') // Check if number + { + buffer[0] = 0; + // convert ch to HID number, starting at 1 = 30, 0 = 39 + if(ch == '0') + { + buffer[2] = 39; + } + else + { + buffer[2] = (uint8_t)(30 + (ch - '1')); + } + } + else // not a letter nor a number + { + switch(ch) + { + CASE(' ', 0, USB_HID_SPACE); + CASE('.', 0,USB_HID_DOT); + CASE('\n', 0, USB_HID_NEWLINE); + CASE('?', USB_HID_MODIFIER_LEFT_SHIFT, USB_HID_FSLASH); + CASE('/', 0 ,USB_HID_FSLASH); + CASE('\\', 0, USB_HID_BSLASH); + CASE('|', USB_HID_MODIFIER_LEFT_SHIFT, USB_HID_BSLASH); + CASE(',', 0, USB_HID_COMMA); + CASE('<', USB_HID_MODIFIER_LEFT_SHIFT, USB_HID_COMMA); + CASE('>', USB_HID_MODIFIER_LEFT_SHIFT, USB_HID_COMMA); + CASE('@', USB_HID_MODIFIER_LEFT_SHIFT, 31); + CASE('!', USB_HID_MODIFIER_LEFT_SHIFT, 30); + CASE('#', USB_HID_MODIFIER_LEFT_SHIFT, 32); + CASE('$', USB_HID_MODIFIER_LEFT_SHIFT, 33); + CASE('%', USB_HID_MODIFIER_LEFT_SHIFT, 34); + CASE('^', USB_HID_MODIFIER_LEFT_SHIFT,35); + CASE('&', USB_HID_MODIFIER_LEFT_SHIFT, 36); + CASE('*', USB_HID_MODIFIER_LEFT_SHIFT, 37); + CASE('(', USB_HID_MODIFIER_LEFT_SHIFT, 38); + CASE(')', USB_HID_MODIFIER_LEFT_SHIFT, 39); + CASE('-', 0, 0x2D); + CASE('_', USB_HID_MODIFIER_LEFT_SHIFT, 0x2D); + CASE('=', 0, 0x2E); + CASE('+', USB_HID_MODIFIER_LEFT_SHIFT, 39); + CASE(8, 0, 0x2A); // backspace + CASE('\t', 0, 0x2B); + default: + buffer[0] = 0; + buffer[2] = 0; + } + } +} +void send_keyboard(char c) +{ + static uint8_t buffer[8] = {0}; + char_to_code(buffer, c); + esp_hidd_dev_input_set(s_ble_hid_param.hid_dev, 0, 1, buffer, 8); + /* send the keyrelease event with sufficient delay */ + vTaskDelay(50 / portTICK_PERIOD_MS); + memset(buffer, 0, sizeof(uint8_t) * 8); + esp_hidd_dev_input_set(s_ble_hid_param.hid_dev, 0, 1, buffer, 8); +} + +void ble_hid_demo_task_kbd(void *pvParameters) +{ + static const char* help_string = "########################################################################\n"\ + "BT hid keyboard demo usage:\n"\ + "########################################################################\n"; + /* TODO : Add support for function keys and ctrl, alt, esc, etc. */ + printf("%s\n", help_string); + char c; + while (1) { + c = fgetc(stdin); + + if(c != 255) { + send_keyboard(c); + } + vTaskDelay(10 / portTICK_PERIOD_MS); + } +} +#endif static esp_hid_raw_report_map_t ble_report_maps[] = { +#if !CONFIG_BT_NIMBLE_ENABLED || CONFIG_EXAMPLE_HID_DEVICE_ROLE == 1 + /* This block is compiled for bluedroid as well */ { .data = mediaReportMap, .len = sizeof(mediaReportMap) } +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE && CONFIG_EXAMPLE_HID_DEVICE_ROLE == 2 + { + .data = keyboardReportMap, + .len = sizeof(keyboardReportMap) + }, +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE && CONFIG_EXAMPLE_HID_DEVICE_ROLE == 3 + { + .data = mouseReportMap, + .len = sizeof(mouseReportMap) + }, +#endif }; static esp_hid_device_config_t ble_hid_config = { .vendor_id = 0x16C0, .product_id = 0x05DF, .version = 0x0100, +#if CONFIG_EXAMPLE_HID_DEVICE_ROLE == 2 + .device_name = "ESP Keyboard", +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE == 3 + .device_name = "ESP Mouse", +#else .device_name = "ESP BLE HID2", +#endif .manufacturer_name = "Espressif", .serial_number = "1234567890", .report_maps = ble_report_maps, @@ -272,6 +547,7 @@ void esp_hidd_send_consumer_value(uint8_t key_cmd, bool key_pressed) return; } +#if !CONFIG_BT_NIMBLE_ENABLED || CONFIG_EXAMPLE_HID_DEVICE_ROLE == 1 void ble_hid_demo_task(void *pvParameters) { static bool send_volum_up = false; @@ -290,6 +566,7 @@ void ble_hid_demo_task(void *pvParameters) vTaskDelay(2000 / portTICK_PERIOD_MS); } } +#endif void ble_hid_task_start_up(void) { @@ -297,8 +574,23 @@ void ble_hid_task_start_up(void) // Task already exists return; } +#if !CONFIG_BT_NIMBLE_ENABLED + /* Executed for bluedroid */ xTaskCreate(ble_hid_demo_task, "ble_hid_demo_task", 2 * 1024, NULL, configMAX_PRIORITIES - 3, &s_ble_hid_param.task_hdl); +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE == 1 + xTaskCreate(ble_hid_demo_task, "ble_hid_demo_task", 3 * 1024, NULL, configMAX_PRIORITIES - 3, + &s_ble_hid_param.task_hdl); + +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE == 2 + /* Nimble Specific */ + xTaskCreate(ble_hid_demo_task_kbd, "ble_hid_demo_task_kbd", 3 * 1024, NULL, configMAX_PRIORITIES - 3, + &s_ble_hid_param.task_hdl); +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE == 3 + /* Nimble Specific */ + xTaskCreate(ble_hid_demo_task_mouse, "ble_hid_demo_task_mouse", 3 * 1024, NULL, configMAX_PRIORITIES - 3, + &s_ble_hid_param.task_hdl); +#endif } void ble_hid_task_shut_down(void) @@ -557,6 +849,18 @@ static void bt_hidd_event_callback(void *handler_args, esp_event_base_t base, in } #endif +#if CONFIG_BT_NIMBLE_ENABLED +void ble_hid_device_host_task(void *param) +{ + ESP_LOGI(TAG, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} +void ble_store_config_init(void); +#endif + void app_main(void) { esp_err_t ret; @@ -575,14 +879,21 @@ void app_main(void) ret = esp_hid_gap_init(HID_DEV_MODE); ESP_ERROR_CHECK( ret ); -#if CONFIG_BT_BLE_ENABLED +#if CONFIG_BT_BLE_ENABLED || CONFIG_BT_NIMBLE_ENABLED +#if CONFIG_EXAMPLE_HID_DEVICE_ROLE == 2 + ret = esp_hid_ble_gap_adv_init(ESP_HID_APPEARANCE_KEYBOARD, ble_hid_config.device_name); +#elif CONFIG_EXAMPLE_HID_DEVICE_ROLE == 3 + ret = esp_hid_ble_gap_adv_init(ESP_HID_APPEARANCE_MOUSE, ble_hid_config.device_name); +#else ret = esp_hid_ble_gap_adv_init(ESP_HID_APPEARANCE_GENERIC, ble_hid_config.device_name); +#endif ESP_ERROR_CHECK( ret ); - +#if CONFIG_BT_BLE_ENABLED if ((ret = esp_ble_gatts_register_callback(esp_hidd_gatts_event_handler)) != ESP_OK) { ESP_LOGE(TAG, "GATTS register callback failed: %d", ret); return; } +#endif ESP_LOGI(TAG, "setting ble device"); ESP_ERROR_CHECK( esp_hidd_dev_init(&ble_hid_config, ESP_HID_TRANSPORT_BLE, ble_hidd_event_callback, &s_ble_hid_param.hid_dev)); @@ -600,4 +911,15 @@ void app_main(void) ESP_ERROR_CHECK( esp_hidd_dev_init(&bt_hid_config, ESP_HID_TRANSPORT_BT, bt_hidd_event_callback, &s_bt_hid_param.hid_dev)); #endif +#if CONFIG_BT_NIMBLE_ENABLED + /* XXX Need to have template for store */ + ble_store_config_init(); + + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + /* Starting nimble task after gatts is initialized*/ + ret = esp_nimble_enable(ble_hid_device_host_task); + if (ret) { + ESP_LOGE(TAG, "esp_nimble_enable failed: %d", ret); + } +#endif } diff --git a/examples/bluetooth/esp_hid_device/main/esp_hid_gap.c b/examples/bluetooth/esp_hid_device/main/esp_hid_gap.c index 1f0d2a460b7..472fc6e71d2 100644 --- a/examples/bluetooth/esp_hid_device/main/esp_hid_gap.c +++ b/examples/bluetooth/esp_hid_device/main/esp_hid_gap.c @@ -15,17 +15,28 @@ #include "esp_hid_gap.h" +#if CONFIG_BT_NIMBLE_ENABLED +#include "host/ble_hs.h" +#include "nimble/nimble_port.h" +#include "host/ble_gap.h" +#include "host/ble_hs_adv.h" +#include "nimble/ble.h" +#include "host/ble_sm.h" +#endif + static const char *TAG = "ESP_HID_GAP"; // uncomment to print all devices that were seen during a scan #define GAP_DBG_PRINTF(...) //printf(__VA_ARGS__) //static const char * gap_bt_prop_type_names[5] = {"","BDNAME","COD","RSSI","EIR"}; +#if !CONFIG_BT_NIMBLE_ENABLED static esp_hid_scan_result_t *bt_scan_results = NULL; static size_t num_bt_scan_results = 0; static esp_hid_scan_result_t *ble_scan_results = NULL; static size_t num_ble_scan_results = 0; +#endif static SemaphoreHandle_t bt_hidh_cb_semaphore = NULL; #define WAIT_BT_CB() xSemaphoreTake(bt_hidh_cb_semaphore, portMAX_DELAY) @@ -37,6 +48,7 @@ static SemaphoreHandle_t ble_hidh_cb_semaphore = NULL; #define SIZEOF_ARRAY(a) (sizeof(a)/sizeof(*a)) +#if !CONFIG_BT_NIMBLE_ENABLED static const char *ble_gap_evt_names[] = { "ADV_DATA_SET_COMPLETE", "SCAN_RSP_DATA_SET_COMPLETE", "SCAN_PARAM_SET_COMPLETE", "SCAN_RESULT", "ADV_DATA_RAW_SET_COMPLETE", "SCAN_RSP_DATA_RAW_SET_COMPLETE", "ADV_START_COMPLETE", "SCAN_START_COMPLETE", "AUTH_CMPL", "KEY", "SEC_REQ", "PASSKEY_NOTIF", "PASSKEY_REQ", "OOB_REQ", "LOCAL_IR", "LOCAL_ER", "NC_REQ", "ADV_STOP_COMPLETE", "SCAN_STOP_COMPLETE", "SET_STATIC_RAND_ADDR", "UPDATE_CONN_PARAMS", "SET_PKT_LENGTH_COMPLETE", "SET_LOCAL_PRIVACY_COMPLETE", "REMOVE_BOND_DEV_COMPLETE", "CLEAR_BOND_DEV_COMPLETE", "GET_BOND_DEV_COMPLETE", "READ_RSSI_COMPLETE", "UPDATE_WHITELIST_COMPLETE"}; static const char *bt_gap_evt_names[] = { "DISC_RES", "DISC_STATE_CHANGED", "RMT_SRVCS", "RMT_SRVC_REC", "AUTH_CMPL", "PIN_REQ", "CFM_REQ", "KEY_NOTIF", "KEY_REQ", "READ_RSSI_DELTA"}; static const char *ble_addr_type_names[] = {"PUBLIC", "RANDOM", "RPA_PUBLIC", "RPA_RANDOM"}; @@ -64,6 +76,7 @@ const char *bt_gap_evt_str(uint8_t event) } return bt_gap_evt_names[event]; } +#endif #if CONFIG_BT_BLE_ENABLED const char *esp_ble_key_type_str(esp_ble_key_type_t key_type) @@ -106,6 +119,7 @@ const char *esp_ble_key_type_str(esp_ble_key_type_t key_type) } #endif /* CONFIG_BT_BLE_ENABLED */ +#if !CONFIG_BT_NIMBLE_ENABLED void esp_hid_scan_results_free(esp_hid_scan_result_t *results) { esp_hid_scan_result_t *r = NULL; @@ -118,6 +132,7 @@ void esp_hid_scan_results_free(esp_hid_scan_result_t *results) free(r); } } +#endif #if (CONFIG_BT_HID_DEVICE_ENABLED || CONFIG_BT_BLE_ENABLED) static esp_hid_scan_result_t *find_scan_result(esp_bd_addr_t bda, esp_hid_scan_result_t *results) @@ -223,6 +238,7 @@ static void add_ble_scan_result(esp_bd_addr_t bda, esp_ble_addr_type_t addr_type } #endif /* CONFIG_BT_BLE_ENABLED */ +#if !CONFIG_BT_NIMBLE_ENABLED void print_uuid(esp_bt_uuid_t *uuid) { if (uuid->len == ESP_UUID_LEN_16) { @@ -238,6 +254,7 @@ void print_uuid(esp_bt_uuid_t *uuid) uuid->uuid.uuid128[13], uuid->uuid.uuid128[14], uuid->uuid.uuid128[15]); } } +#endif #if CONFIG_BT_HID_DEVICE_ENABLED static void handle_bt_device_result(struct disc_res_param *disc_res) @@ -616,6 +633,7 @@ static esp_err_t start_ble_scan(uint32_t seconds) return ret; } +#if !CONFIG_BT_NIMBLE_ENABLED esp_err_t esp_hid_ble_gap_adv_init(uint16_t appearance, const char *device_name) { @@ -693,7 +711,7 @@ esp_err_t esp_hid_ble_gap_adv_init(uint16_t appearance, const char *device_name) return ret; } - +#endif esp_err_t esp_hid_ble_gap_adv_start(void) { static esp_ble_adv_params_t hidd_adv_params = { @@ -707,11 +725,212 @@ esp_err_t esp_hid_ble_gap_adv_start(void) return esp_ble_gap_start_advertising(&hidd_adv_params); } #endif /* CONFIG_BT_BLE_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED +static struct ble_hs_adv_fields fields; +#define GATT_SVR_SVC_HID_UUID 0x1812 +esp_err_t esp_hid_ble_gap_adv_init(uint16_t appearance, const char *device_name) +{ + ble_uuid16_t *uuid16, *uuid16_1; + /** + * Set the advertisement data included in our advertisements: + * o Flags (indicates advertisement type and other general info). + * o Advertising tx power. + * o Device name. + * o 16-bit service UUIDs (HID). + */ + + memset(&fields, 0, sizeof fields); + + /* Advertise two flags: + * o Discoverability in forthcoming advertisement (general) + * o BLE-only (BR/EDR unsupported). + */ + fields.flags = BLE_HS_ADV_F_DISC_GEN | + BLE_HS_ADV_F_BREDR_UNSUP; + + /* Indicate that the TX power level field should be included; have the + * stack fill this value automatically. This is done by assigning the + * special value BLE_HS_ADV_TX_PWR_LVL_AUTO. + */ + fields.tx_pwr_lvl_is_present = 1; + fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + + fields.name = (uint8_t *)device_name; + fields.name_len = strlen(device_name); + fields.name_is_complete = 1; + + uuid16 = (ble_uuid16_t *)malloc(sizeof(ble_uuid16_t)); + uuid16_1 = (ble_uuid16_t[]) { + BLE_UUID16_INIT(GATT_SVR_SVC_HID_UUID) + }; + memcpy(uuid16, uuid16_1, sizeof(ble_uuid16_t)); + fields.uuids16 = uuid16; + fields.num_uuids16 = 1; + fields.uuids16_is_complete = 1; + + /* Initialize the security configuration */ + ble_hs_cfg.sm_io_cap = BLE_SM_IO_CAP_DISP_ONLY; + ble_hs_cfg.sm_bonding = 1; + ble_hs_cfg.sm_mitm = 1; + ble_hs_cfg.sm_sc = 1; + ble_hs_cfg.sm_our_key_dist = BLE_SM_PAIR_KEY_DIST_ID | BLE_SM_PAIR_KEY_DIST_ENC; + ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID | BLE_SM_PAIR_KEY_DIST_ENC; + + return ESP_OK; + +} + +static int +nimble_hid_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + int rc; + + switch (event->type) { + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + ESP_LOGI(TAG, "connection %s; status=%d", + event->connect.status == 0 ? "established" : "failed", + event->connect.status); + return 0; + break; + case BLE_GAP_EVENT_DISCONNECT: + ESP_LOGI(TAG, "disconnect; reason=%d", event->disconnect.reason); + + return 0; + case BLE_GAP_EVENT_CONN_UPDATE: + /* The central has updated the connection parameters. */ + ESP_LOGI(TAG, "connection updated; status=%d", + event->conn_update.status); + return 0; + + case BLE_GAP_EVENT_ADV_COMPLETE: + ESP_LOGI(TAG, "advertise complete; reason=%d", + event->adv_complete.reason); + return 0; + + case BLE_GAP_EVENT_SUBSCRIBE: + ESP_LOGI(TAG, "subscribe event; conn_handle=%d attr_handle=%d " + "reason=%d prevn=%d curn=%d previ=%d curi=%d\n", + event->subscribe.conn_handle, + event->subscribe.attr_handle, + event->subscribe.reason, + event->subscribe.prev_notify, + event->subscribe.cur_notify, + event->subscribe.prev_indicate, + event->subscribe.cur_indicate); + return 0; + + case BLE_GAP_EVENT_MTU: + ESP_LOGI(TAG, "mtu update event; conn_handle=%d cid=%d mtu=%d", + event->mtu.conn_handle, + event->mtu.channel_id, + event->mtu.value); + return 0; + + case BLE_GAP_EVENT_ENC_CHANGE: + /* Encryption has been enabled or disabled for this connection. */ + MODLOG_DFLT(INFO, "encryption change event; status=%d ", + event->enc_change.status); + rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc); + assert(rc == 0); + return 0; + + case BLE_GAP_EVENT_NOTIFY_TX: + MODLOG_DFLT(INFO, "notify_tx event; conn_handle=%d attr_handle=%d " + "status=%d is_indication=%d", + event->notify_tx.conn_handle, + event->notify_tx.attr_handle, + event->notify_tx.status, + event->notify_tx.indication); + return 0; + + case BLE_GAP_EVENT_REPEAT_PAIRING: + /* We already have a bond with the peer, but it is attempting to + * establish a new secure link. This app sacrifices security for + * convenience: just throw away the old bond and accept the new link. + */ + + /* Delete the old bond. */ + rc = ble_gap_conn_find(event->repeat_pairing.conn_handle, &desc); + assert(rc == 0); + ble_store_util_delete_peer(&desc.peer_id_addr); + + /* Return BLE_GAP_REPEAT_PAIRING_RETRY to indicate that the host should + * continue with the pairing operation. + */ + return BLE_GAP_REPEAT_PAIRING_RETRY; + + case BLE_GAP_EVENT_PASSKEY_ACTION: + ESP_LOGI(TAG, "PASSKEY_ACTION_EVENT started"); + struct ble_sm_io pkey = {0}; + int key = 0; + + if (event->passkey.params.action == BLE_SM_IOACT_DISP) { + pkey.action = event->passkey.params.action; + pkey.passkey = 123456; // This is the passkey to be entered on peer + ESP_LOGI(TAG, "Enter passkey %" PRIu32 "on the peer side", pkey.passkey); + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_NUMCMP) { + ESP_LOGI(TAG, "Accepting passkey.."); + pkey.action = event->passkey.params.action; + pkey.numcmp_accept = key; + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_OOB) { + static uint8_t tem_oob[16] = {0}; + pkey.action = event->passkey.params.action; + for (int i = 0; i < 16; i++) { + pkey.oob[i] = tem_oob[i]; + } + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_INPUT) { + ESP_LOGI(TAG, "Input not supported passing -> 123456"); + pkey.action = event->passkey.params.action; + pkey.passkey = 123456; + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } + return 0; + } + return 0; +} +esp_err_t esp_hid_ble_gap_adv_start(void) +{ + int rc; + struct ble_gap_adv_params adv_params; + /* maximum possible duration for hid device(180s) */ + int32_t adv_duration_ms = 180000; + + rc = ble_gap_adv_set_fields(&fields); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc); + return rc; + } + /* Begin advertising. */ + memset(&adv_params, 0, sizeof adv_params); + adv_params.conn_mode = BLE_GAP_CONN_MODE_UND; + adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN; + adv_params.itvl_min = BLE_GAP_ADV_ITVL_MS(30);/* Recommended interval 30ms to 50ms */ + adv_params.itvl_max = BLE_GAP_ADV_ITVL_MS(50); + rc = ble_gap_adv_start(BLE_OWN_ADDR_PUBLIC, NULL, adv_duration_ms, + &adv_params, nimble_hid_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc); + return rc; + } + return rc; +} +#endif + /* * CONTROLLER INIT * */ +#if !CONFIG_BT_NIMBLE_ENABLED static esp_err_t init_low_level(uint8_t mode) { esp_err_t ret; @@ -777,6 +996,43 @@ static esp_err_t init_low_level(uint8_t mode) #endif /* CONFIG_BT_BLE_ENABLED */ return ret; } +#endif + +#if CONFIG_BT_NIMBLE_ENABLED +static esp_err_t init_low_level(uint8_t mode) +{ + esp_err_t ret; + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); +#if CONFIG_IDF_TARGET_ESP32 + bt_cfg.mode = mode; +#endif + ret = esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT); + if (ret) { + ESP_LOGE(TAG, "esp_bt_controller_mem_release failed: %d", ret); + return ret; + } + ret = esp_bt_controller_init(&bt_cfg); + if (ret) { + ESP_LOGE(TAG, "esp_bt_controller_init failed: %d", ret); + return ret; + } + + ret = esp_bt_controller_enable(mode); + if (ret) { + ESP_LOGE(TAG, "esp_bt_controller_enable failed: %d", ret); + return ret; + } + + ret = esp_nimble_init(); + if (ret) { + ESP_LOGE(TAG, "esp_nimble_init failed: %d", ret); + return ret; + } + + + return ret; +} +#endif esp_err_t esp_hid_gap_init(uint8_t mode) { @@ -817,6 +1073,7 @@ esp_err_t esp_hid_gap_init(uint8_t mode) return ESP_OK; } +#if !CONFIG_BT_NIMBLE_ENABLED esp_err_t esp_hid_scan(uint32_t seconds, size_t *num_results, esp_hid_scan_result_t **results) { if (num_bt_scan_results || bt_scan_results || num_ble_scan_results || ble_scan_results) { @@ -857,3 +1114,4 @@ esp_err_t esp_hid_scan(uint32_t seconds, size_t *num_results, esp_hid_scan_resul ble_scan_results = NULL; return ESP_OK; } +#endif diff --git a/examples/bluetooth/esp_hid_device/main/esp_hid_gap.h b/examples/bluetooth/esp_hid_device/main/esp_hid_gap.h index 8e2cf3897bf..5211c90c839 100644 --- a/examples/bluetooth/esp_hid_device/main/esp_hid_gap.h +++ b/examples/bluetooth/esp_hid_device/main/esp_hid_gap.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -20,6 +20,8 @@ #endif #elif CONFIG_BT_BLE_ENABLED #define HID_DEV_MODE HIDD_BLE_MODE +#elif CONFIG_BT_NIMBLE_ENABLED +#define HID_DEV_MODE HIDD_BLE_MODE #else #define HID_DEV_MODE HIDD_IDLE_MODE #endif @@ -28,9 +30,11 @@ #include "esp_log.h" #include "esp_bt.h" +#if !CONFIG_BT_NIMBLE_ENABLED #include "esp_bt_defs.h" #include "esp_bt_main.h" #include "esp_gap_bt_api.h" +#endif #include "esp_hid_common.h" #if CONFIG_BT_BLE_ENABLED #include "esp_gattc_api.h" @@ -42,6 +46,7 @@ extern "C" { #endif +#if !CONFIG_BT_NIMBLE_ENABLED typedef struct esp_hidh_scan_result_s { struct esp_hidh_scan_result_s *next; @@ -62,16 +67,17 @@ typedef struct esp_hidh_scan_result_s { }; } esp_hid_scan_result_t; -esp_err_t esp_hid_gap_init(uint8_t mode); esp_err_t esp_hid_scan(uint32_t seconds, size_t *num_results, esp_hid_scan_result_t **results); void esp_hid_scan_results_free(esp_hid_scan_result_t *results); +const char *ble_addr_type_str(esp_ble_addr_type_t ble_addr_type); +void print_uuid(esp_bt_uuid_t *uuid); +#endif + +esp_err_t esp_hid_gap_init(uint8_t mode); esp_err_t esp_hid_ble_gap_adv_init(uint16_t appearance, const char *device_name); esp_err_t esp_hid_ble_gap_adv_start(void); -void print_uuid(esp_bt_uuid_t *uuid); -const char *ble_addr_type_str(esp_ble_addr_type_t ble_addr_type); - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/esp_hid_device/sdkconfig.defaults b/examples/bluetooth/esp_hid_device/sdkconfig.defaults index 644f74599d6..6496bd43ef1 100644 --- a/examples/bluetooth/esp_hid_device/sdkconfig.defaults +++ b/examples/bluetooth/esp_hid_device/sdkconfig.defaults @@ -1,6 +1,5 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BTDM=y -CONFIG_BTDM_CTRL_HCI_MODE_VHCI=y CONFIG_BT_BLUEDROID_ENABLED=y CONFIG_BT_CLASSIC_ENABLED=y CONFIG_BT_BLE_ENABLED=y diff --git a/examples/bluetooth/esp_hid_host/main/Kconfig.projbuild b/examples/bluetooth/esp_hid_host/main/Kconfig.projbuild index 568ef5ae62f..5b0fa17ed02 100644 --- a/examples/bluetooth/esp_hid_host/main/Kconfig.projbuild +++ b/examples/bluetooth/esp_hid_host/main/Kconfig.projbuild @@ -6,4 +6,12 @@ menu "HID Example Configuration" help This enables the Secure Simple Pairing. If disable this option, Bluedroid will only support Legacy Pairing + + config EXAMPLE_HID_HOST_ENABLED + bool "Enable Example HID Host" + depends on BT_NIMBLE_ENABLED + default y + select BT_NIMBLE_HID_SERVICE + help + This enables Nimble HID Host endmenu diff --git a/examples/bluetooth/esp_hid_host/main/esp_hid_gap.c b/examples/bluetooth/esp_hid_host/main/esp_hid_gap.c index ca16f6191f0..0299b37d115 100644 --- a/examples/bluetooth/esp_hid_host/main/esp_hid_gap.c +++ b/examples/bluetooth/esp_hid_host/main/esp_hid_gap.c @@ -14,6 +14,15 @@ #include "freertos/semphr.h" #include "esp_hid_gap.h" +#if CONFIG_BT_NIMBLE_ENABLED +#include "host/ble_hs.h" +#include "nimble/nimble_port.h" +#include "host/ble_gap.h" +#include "host/ble_hs_adv.h" +#include "nimble/ble.h" +#include "host/ble_sm.h" +#define BLE_HID_SVC_UUID 0x1812 /* HID Service*/ +#endif static const char *TAG = "ESP_HID_GAP"; @@ -40,6 +49,7 @@ static SemaphoreHandle_t ble_hidh_cb_semaphore = NULL; #define SIZEOF_ARRAY(a) (sizeof(a)/sizeof(*a)) +#if !CONFIG_BT_NIMBLE_ENABLED static const char *ble_gap_evt_names[] = { "ADV_DATA_SET_COMPLETE", "SCAN_RSP_DATA_SET_COMPLETE", "SCAN_PARAM_SET_COMPLETE", "SCAN_RESULT", "ADV_DATA_RAW_SET_COMPLETE", "SCAN_RSP_DATA_RAW_SET_COMPLETE", "ADV_START_COMPLETE", "SCAN_START_COMPLETE", "AUTH_CMPL", "KEY", "SEC_REQ", "PASSKEY_NOTIF", "PASSKEY_REQ", "OOB_REQ", "LOCAL_IR", "LOCAL_ER", "NC_REQ", "ADV_STOP_COMPLETE", "SCAN_STOP_COMPLETE", "SET_STATIC_RAND_ADDR", "UPDATE_CONN_PARAMS", "SET_PKT_LENGTH_COMPLETE", "SET_LOCAL_PRIVACY_COMPLETE", "REMOVE_BOND_DEV_COMPLETE", "CLEAR_BOND_DEV_COMPLETE", "GET_BOND_DEV_COMPLETE", "READ_RSSI_COMPLETE", "UPDATE_WHITELIST_COMPLETE"}; static const char *bt_gap_evt_names[] = { "DISC_RES", "DISC_STATE_CHANGED", "RMT_SRVCS", "RMT_SRVC_REC", "AUTH_CMPL", "PIN_REQ", "CFM_REQ", "KEY_NOTIF", "KEY_REQ", "READ_RSSI_DELTA"}; static const char *ble_addr_type_names[] = {"PUBLIC", "RANDOM", "RPA_PUBLIC", "RPA_RANDOM"}; @@ -67,7 +77,7 @@ const char *bt_gap_evt_str(uint8_t event) } return bt_gap_evt_names[event]; } - +#endif #if CONFIG_BT_BLE_ENABLED const char *esp_ble_key_type_str(esp_ble_key_type_t key_type) { @@ -136,6 +146,19 @@ static esp_hid_scan_result_t *find_scan_result(esp_bd_addr_t bda, esp_hid_scan_r } #endif /* (CONFIG_BT_HID_HOST_ENABLED || CONFIG_BT_BLE_ENABLED) */ +#if (CONFIG_BT_NIMBLE_ENABLED) +static esp_hid_scan_result_t *find_scan_result(const uint8_t *bda, esp_hid_scan_result_t *results) +{ + esp_hid_scan_result_t *r = results; + while (r) { + if (memcmp(bda, r->bda, sizeof(r->bda)) == 0) { + return r; + } + r = r->next; + } + return NULL; +} +#endif #if CONFIG_BT_HID_HOST_ENABLED static void add_bt_scan_result(esp_bd_addr_t bda, esp_bt_cod_t *cod, esp_bt_uuid_t *uuid, uint8_t *name, uint8_t name_len, int rssi) { @@ -226,6 +249,43 @@ static void add_ble_scan_result(esp_bd_addr_t bda, esp_ble_addr_type_t addr_type } #endif /* CONFIG_BT_BLE_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED +static void add_ble_scan_result(const uint8_t *bda, uint8_t addr_type, uint16_t appearance, uint8_t *name, uint8_t name_len, int rssi) +{ + if (find_scan_result(bda, ble_scan_results)) { + ESP_LOGW(TAG, "Result already exists!"); + return; + } + esp_hid_scan_result_t *r = (esp_hid_scan_result_t *)malloc(sizeof(esp_hid_scan_result_t)); + if (r == NULL) { + ESP_LOGE(TAG, "Malloc ble_hidh_scan_result_t failed!"); + return; + } + r->transport = ESP_HID_TRANSPORT_BLE; + memcpy(r->bda, bda, sizeof(r->bda)); + r->ble.appearance = appearance; + r->ble.addr_type = addr_type; + r->usage = esp_hid_usage_from_appearance(appearance); + r->rssi = rssi; + r->name = NULL; + if (name_len && name) { + char *name_s = (char *)malloc(name_len + 1); + if (name_s == NULL) { + free(r); + ESP_LOGE(TAG, "Malloc result name failed!"); + return; + } + memcpy(name_s, name, name_len); + name_s[name_len] = 0; + r->name = (const char *)name_s; + } + r->next = ble_scan_results; + ble_scan_results = r; + num_ble_scan_results++; +} +#endif /* CONFIG_BT_BLE_ENABLED */ + +#if !CONFIG_BT_NIMBLE_ENABLED void print_uuid(esp_bt_uuid_t *uuid) { if (uuid->len == ESP_UUID_LEN_16) { @@ -575,6 +635,7 @@ static void ble_gap_event_handler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_p break; } } +#endif static esp_err_t init_ble_gap(void) { @@ -708,6 +769,252 @@ esp_err_t esp_hid_ble_gap_adv_start(void) * CONTROLLER INIT * */ +#if CONFIG_BT_NIMBLE_ENABLED +static esp_err_t init_low_level(uint8_t mode) +{ + esp_err_t ret; + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); +#if CONFIG_IDF_TARGET_ESP32 + bt_cfg.mode = mode; +#endif + ret = esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT); + if (ret) { + ESP_LOGE(TAG, "esp_bt_controller_mem_release failed: %d", ret); + return ret; + } + ret = esp_bt_controller_init(&bt_cfg); + if (ret) { + ESP_LOGE(TAG, "esp_bt_controller_init failed: %d", ret); + return ret; + } + + ret = esp_bt_controller_enable(mode); + if (ret) { + ESP_LOGE(TAG, "esp_bt_controller_enable failed: %d", ret); + return ret; + } + + ret = esp_nimble_init(); + if (ret) { + ESP_LOGE(TAG, "esp_nimble_init failed: %d", ret); + return ret; + } + + return ret; +} + +static void handle_ble_device_result(const struct ble_gap_disc_desc *disc) +{ + int rc; + struct ble_hs_adv_fields fields; + uint16_t appearance; + uint8_t adv_name[BLE_HS_ADV_MAX_SZ]; + uint8_t adv_name_len = 0; + + appearance = 0; /* silent warnings for now */ + rc = ble_hs_adv_parse_fields(&fields, disc->data, disc->length_data); + if(rc != 0) { + return; + } + + if (fields.name != NULL) { + assert(fields.name_len < sizeof adv_name - 1); + memcpy(adv_name, fields.name, fields.name_len); + adv_name[fields.name_len] = '\0'; + adv_name_len = fields.name_len; + MODLOG_DFLT(DEBUG, " name(%scomplete)=%s\n", + fields.name_is_complete ? "" : "in", adv_name); + } + + if (fields.appearance_is_present) { + MODLOG_DFLT(DEBUG, " appearance=0x%04x\n", fields.appearance); + appearance = fields.appearance; + } + + for (int i = 0; i < fields.num_uuids16; i++) { + if (ble_uuid_u16(&fields.uuids16[i].u) == BLE_HID_SVC_UUID && + ((adv_name_len > 0 && memcmp("ESP BLE HID2", adv_name, adv_name_len) == 0) || + (adv_name_len > 0 && memcmp("ESP Mouse", adv_name, adv_name_len) == 0) || + (adv_name_len > 0 && memcmp("ESP Keyboard", adv_name, adv_name_len) == 0))) { + add_ble_scan_result(disc->addr.val, disc->addr.type, appearance, adv_name, adv_name_len, disc->rssi); + break; + } + } +} +#endif + +#if CONFIG_BT_NIMBLE_ENABLED +static int +nimble_hid_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + int rc; + + switch (event->type) { + case BLE_GAP_EVENT_DISC: + handle_ble_device_result(&event->disc); + if (rc != 0) { + return 0; + } + + /* An advertisment report was received during GAP discovery. */ + return 0; + break; + case BLE_GAP_EVENT_DISC_COMPLETE: + MODLOG_DFLT(INFO, "discovery complete; reason=%d\n", + event->disc_complete.reason); + SEND_BLE_CB(); + return 0; + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + ESP_LOGI(TAG, "connection %s; status=%d", + event->connect.status == 0 ? "established" : "failed", + event->connect.status); + return 0; + break; + case BLE_GAP_EVENT_DISCONNECT: + ESP_LOGI(TAG, "disconnect; reason=%d", event->disconnect.reason); + + return 0; + case BLE_GAP_EVENT_CONN_UPDATE: + /* The central has updated the connection parameters. */ + ESP_LOGI(TAG, "connection updated; status=%d", + event->conn_update.status); + return 0; + + case BLE_GAP_EVENT_ADV_COMPLETE: + ESP_LOGI(TAG, "advertise complete; reason=%d", + event->adv_complete.reason); + return 0; + + case BLE_GAP_EVENT_SUBSCRIBE: + ESP_LOGI(TAG, "subscribe event; conn_handle=%d attr_handle=%d " + "reason=%d prevn=%d curn=%d previ=%d curi=%d\n", + event->subscribe.conn_handle, + event->subscribe.attr_handle, + event->subscribe.reason, + event->subscribe.prev_notify, + event->subscribe.cur_notify, + event->subscribe.prev_indicate, + event->subscribe.cur_indicate); + return 0; + + case BLE_GAP_EVENT_MTU: + ESP_LOGI(TAG, "mtu update event; conn_handle=%d cid=%d mtu=%d", + event->mtu.conn_handle, + event->mtu.channel_id, + event->mtu.value); + return 0; + + case BLE_GAP_EVENT_ENC_CHANGE: + /* Encryption has been enabled or disabled for this connection. */ + MODLOG_DFLT(INFO, "encryption change event; status=%d ", + event->enc_change.status); + rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc); + assert(rc == 0); + return 0; + + case BLE_GAP_EVENT_NOTIFY_TX: + MODLOG_DFLT(INFO, "notify_tx event; conn_handle=%d attr_handle=%d " + "status=%d is_indication=%d", + event->notify_tx.conn_handle, + event->notify_tx.attr_handle, + event->notify_tx.status, + event->notify_tx.indication); + return 0; + + case BLE_GAP_EVENT_REPEAT_PAIRING: + /* We already have a bond with the peer, but it is attempting to + * establish a new secure link. This app sacrifices security for + * convenience: just throw away the old bond and accept the new link. + */ + + /* Delete the old bond. */ + rc = ble_gap_conn_find(event->repeat_pairing.conn_handle, &desc); + assert(rc == 0); + ble_store_util_delete_peer(&desc.peer_id_addr); + + /* Return BLE_GAP_REPEAT_PAIRING_RETRY to indicate that the host should + * continue with the pairing operation. + */ + return BLE_GAP_REPEAT_PAIRING_RETRY; + + case BLE_GAP_EVENT_PASSKEY_ACTION: + ESP_LOGI(TAG, "PASSKEY_ACTION_EVENT started"); + struct ble_sm_io pkey = {0}; + int key = 0; + + if (event->passkey.params.action == BLE_SM_IOACT_DISP) { + pkey.action = event->passkey.params.action; + pkey.passkey = 123456; // This is the passkey to be entered on peer + ESP_LOGI(TAG, "Enter passkey %" PRIu32 "on the peer side", pkey.passkey); + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_NUMCMP) { + ESP_LOGI(TAG, "Accepting passkey.."); + pkey.action = event->passkey.params.action; + pkey.numcmp_accept = key; + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_OOB) { + static uint8_t tem_oob[16] = {0}; + pkey.action = event->passkey.params.action; + for (int i = 0; i < 16; i++) { + pkey.oob[i] = tem_oob[i]; + } + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_INPUT) { + ESP_LOGI(TAG, "Input not supported passing -> 123456"); + pkey.action = event->passkey.params.action; + pkey.passkey = 123456; + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + ESP_LOGI(TAG, "ble_sm_inject_io result: %d", rc); + } + return 0; + } + return 0; +} + +static esp_err_t start_nimble_scan(uint32_t seconds) +{ + uint8_t own_addr_type; + struct ble_gap_disc_params disc_params; + int rc; + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return rc; + } + + /* Tell the controller to filter duplicates; we don't want to process + * repeated advertisements from the same device. + */ + disc_params.filter_duplicates = 1; + + /** + * Perform active scan. + */ + disc_params.passive = 0; + + /* Use defaults for the rest of the parameters. */ + disc_params.itvl = 0x50; + disc_params.window = 0x30; + disc_params.filter_policy = 0; + disc_params.limited = 0; + + rc = ble_gap_disc(own_addr_type, seconds * 1000, &disc_params, + nimble_hid_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error initiating GAP discovery procedure; rc=%d\n", + rc); + } + return rc; +} + +#else static esp_err_t init_low_level(uint8_t mode) { esp_err_t ret; @@ -773,6 +1080,7 @@ static esp_err_t init_low_level(uint8_t mode) #endif /* CONFIG_BT_BLE_ENABLED */ return ret; } +#endif esp_err_t esp_hid_gap_init(uint8_t mode) { @@ -827,6 +1135,14 @@ esp_err_t esp_hid_scan(uint32_t seconds, size_t *num_results, esp_hid_scan_resul return ESP_FAIL; } #endif /* CONFIG_BT_BLE_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED + if (start_nimble_scan(seconds) == ESP_OK) { + WAIT_BLE_CB(); + } else { + return ESP_FAIL; + } +#endif /* CONFIG_BT_BLE_ENABLED */ + #if CONFIG_BT_HID_HOST_ENABLED if (start_bt_scan(seconds) == ESP_OK) { diff --git a/examples/bluetooth/esp_hid_host/main/esp_hid_gap.h b/examples/bluetooth/esp_hid_host/main/esp_hid_gap.h index de46b2fd317..33bad931039 100644 --- a/examples/bluetooth/esp_hid_host/main/esp_hid_gap.h +++ b/examples/bluetooth/esp_hid_host/main/esp_hid_gap.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -21,6 +21,8 @@ #endif #elif CONFIG_BT_BLE_ENABLED #define HID_HOST_MODE HIDH_BLE_MODE +#elif CONFIG_BT_NIMBLE_ENABLED +#define HID_HOST_MODE HIDH_BLE_MODE #else #define HID_HOST_MODE HIDH_IDLE_MODE #endif @@ -29,9 +31,11 @@ #include "esp_log.h" #include "esp_bt.h" +#if !CONFIG_BT_NIMBLE_ENABLED #include "esp_bt_defs.h" #include "esp_bt_main.h" #include "esp_gap_bt_api.h" +#endif #include "esp_hid_common.h" #if CONFIG_BT_BLE_ENABLED #include "esp_gattc_api.h" @@ -39,19 +43,28 @@ #include "esp_gap_ble_api.h" #endif +#if CONFIG_BT_NIMBLE_ENABLED +#include "nimble/ble.h" +#endif + #ifdef __cplusplus extern "C" { #endif typedef struct esp_hidh_scan_result_s { struct esp_hidh_scan_result_s *next; - +#if CONFIG_BT_NIMBLE_ENABLED + uint8_t bda[6]; +#else esp_bd_addr_t bda; +#endif + const char *name; int8_t rssi; esp_hid_usage_t usage; esp_hid_transport_t transport; //BT, BLE or USB union { + #if !CONFIG_BT_NIMBLE_ENABLED struct { esp_bt_cod_t cod; esp_bt_uuid_t uuid; @@ -60,6 +73,12 @@ typedef struct esp_hidh_scan_result_s { esp_ble_addr_type_t addr_type; uint16_t appearance; } ble; + #else + struct { + uint8_t addr_type; + uint16_t appearance; + } ble; + #endif }; } esp_hid_scan_result_t; @@ -70,8 +89,10 @@ void esp_hid_scan_results_free(esp_hid_scan_result_t *results); esp_err_t esp_hid_ble_gap_adv_init(uint16_t appearance, const char *device_name); esp_err_t esp_hid_ble_gap_adv_start(void); +#if !CONFIG_BT_NIMBLE_ENABLED void print_uuid(esp_bt_uuid_t *uuid); const char *ble_addr_type_str(esp_ble_addr_type_t ble_addr_type); +#endif #ifdef __cplusplus } diff --git a/examples/bluetooth/esp_hid_host/main/esp_hid_host_main.c b/examples/bluetooth/esp_hid_host/main/esp_hid_host_main.c index 81d31ea512c..420ff9d72bf 100644 --- a/examples/bluetooth/esp_hid_host/main/esp_hid_host_main.c +++ b/examples/bluetooth/esp_hid_host/main/esp_hid_host_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -17,12 +17,34 @@ #include "esp_log.h" #include "nvs_flash.h" #include "esp_bt.h" + +#if CONFIG_BT_NIMBLE_ENABLED +#include "host/ble_hs.h" +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#else #include "esp_bt_defs.h" #include "esp_gap_ble_api.h" #include "esp_gatts_api.h" #include "esp_gatt_defs.h" #include "esp_bt_main.h" #include "esp_bt_device.h" +#endif + +#if CONFIG_BT_NIMBLE_ENABLED +#include "host/ble_hs.h" +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#define ESP_BD_ADDR_STR "%02x:%02x:%02x:%02x:%02x:%02x" +#define ESP_BD_ADDR_HEX(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5] +#else +#include "esp_bt_defs.h" +#include "esp_gap_ble_api.h" +#include "esp_gatts_api.h" +#include "esp_gatt_defs.h" +#include "esp_bt_main.h" +#include "esp_bt_device.h" +#endif #include "esp_hidh.h" #include "esp_hid_gap.h" @@ -99,6 +121,13 @@ void hid_demo_task(void *pvParameters) printf("ADDR_TYPE: '%s', ", ble_addr_type_str(r->ble.addr_type)); } #endif /* CONFIG_BT_BLE_ENABLED */ +#if CONFIG_BT_NIMBLE_ENABLED + if (r->transport == ESP_HID_TRANSPORT_BLE) { + cr = r; + printf("APPEARANCE: 0x%04x, ", r->ble.appearance); + printf("ADDR_TYPE: '%d', ", r->ble.addr_type); + } +#endif /* CONFIG_BT_BLE_ENABLED */ #if CONFIG_BT_HID_HOST_ENABLED if (r->transport == ESP_HID_TRANSPORT_BT) { cr = r; @@ -123,6 +152,17 @@ void hid_demo_task(void *pvParameters) vTaskDelete(NULL); } +#if CONFIG_BT_NIMBLE_ENABLED +void ble_hid_host_task(void *param) +{ + ESP_LOGI(TAG, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} +void ble_store_config_init(void); +#endif void app_main(void) { esp_err_t ret; @@ -148,5 +188,16 @@ void app_main(void) }; ESP_ERROR_CHECK( esp_hidh_init(&config) ); +#if CONFIG_BT_NIMBLE_ENABLED + /* XXX Need to have template for store */ + ble_store_config_init(); + + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + /* Starting nimble task after gatts is initialized*/ + ret = esp_nimble_enable(ble_hid_host_task); + if (ret) { + ESP_LOGE(TAG, "esp_nimble_enable failed: %d", ret); + } +#endif xTaskCreate(&hid_demo_task, "hid_task", 6 * 1024, NULL, 2, NULL); } diff --git a/examples/bluetooth/esp_hid_host/sdkconfig.defaults b/examples/bluetooth/esp_hid_host/sdkconfig.defaults index 1c2104eacc6..88817d5ac6e 100644 --- a/examples/bluetooth/esp_hid_host/sdkconfig.defaults +++ b/examples/bluetooth/esp_hid_host/sdkconfig.defaults @@ -1,6 +1,5 @@ CONFIG_BT_ENABLED=y CONFIG_BTDM_CTRL_MODE_BTDM=y -CONFIG_BTDM_CTRL_HCI_MODE_VHCI=y CONFIG_BT_BLUEDROID_ENABLED=y CONFIG_BT_CLASSIC_ENABLED=y CONFIG_BT_BLE_ENABLED=y diff --git a/examples/bluetooth/nimble/ble_htp/htp_prph/sdkconfig.ci b/examples/bluetooth/nimble/ble_htp/htp_prph/sdkconfig.ci deleted file mode 100644 index e4f6ca2ca19..00000000000 --- a/examples/bluetooth/nimble/ble_htp/htp_prph/sdkconfig.ci +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_FREERTOS_UNICORE=y -CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y -CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT=y diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/sdkconfig.ci b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/sdkconfig.ci deleted file mode 100644 index e4f6ca2ca19..00000000000 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/sdkconfig.ci +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_FREERTOS_UNICORE=y -CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y -CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT=y diff --git a/examples/bluetooth/nimble/blehr/sdkconfig.ci b/examples/bluetooth/nimble/blehr/sdkconfig.ci deleted file mode 100644 index e4f6ca2ca19..00000000000 --- a/examples/bluetooth/nimble/blehr/sdkconfig.ci +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_FREERTOS_UNICORE=y -CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y -CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT=y diff --git a/examples/bluetooth/nimble/power_save/sdkconfig.32m.esp32h2 b/examples/bluetooth/nimble/power_save/sdkconfig.32m.esp32h2 index aa5aebe523c..5578874e40d 100644 --- a/examples/bluetooth/nimble/power_save/sdkconfig.32m.esp32h2 +++ b/examples/bluetooth/nimble/power_save/sdkconfig.32m.esp32h2 @@ -2,9 +2,7 @@ CONFIG_IDF_TARGET="esp32h2" # Bluetooth Low Power Config CONFIG_BT_LE_SLEEP_ENABLE=y -# CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER is not set CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL=y -# CONFIG_BT_LE_LP_CLK_SRC_DEFAULT is not set # # Power Management @@ -12,7 +10,6 @@ CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL=y CONFIG_PM_ENABLE=y CONFIG_PM_DFS_INIT_AUTO=y CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y -# CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is not set # end of Power Management # diff --git a/examples/bluetooth/nimble/power_save/sdkconfig.40m.esp32c6 b/examples/bluetooth/nimble/power_save/sdkconfig.40m.esp32c6 index 885ab812bcd..101e2cb9e1f 100644 --- a/examples/bluetooth/nimble/power_save/sdkconfig.40m.esp32c6 +++ b/examples/bluetooth/nimble/power_save/sdkconfig.40m.esp32c6 @@ -2,9 +2,7 @@ CONFIG_IDF_TARGET="esp32c6" # Bluetooth Low Power Config CONFIG_BT_LE_SLEEP_ENABLE=y -# CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER is not set CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL=y -# CONFIG_BT_LE_LP_CLK_SRC_DEFAULT is not set # # Power Management @@ -12,7 +10,6 @@ CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL=y CONFIG_PM_ENABLE=y CONFIG_PM_DFS_INIT_AUTO=y CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y -# CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is not set # end of Power Management CONFIG_FREERTOS_USE_TICKLESS_IDLE=y @@ -21,4 +18,5 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y # Sleep Config # CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y +CONFIG_ESP_PHY_MAC_BB_PD=y # end of Sleep Config diff --git a/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32c6 b/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32c6 index fdf2ca28b40..ce9b3b61b5a 100644 --- a/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32c6 +++ b/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32c6 @@ -2,8 +2,6 @@ CONFIG_IDF_TARGET="esp32c6" # Bluetooth Low Power Config CONFIG_BT_LE_SLEEP_ENABLE=y -# CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER is not set -# CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL is not set CONFIG_BT_LE_LP_CLK_SRC_DEFAULT=y # @@ -21,13 +19,11 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y # Sleep Config # CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y +CONFIG_ESP_PHY_MAC_BB_PD=y # end of Sleep Config # # RTC Clock Config # -# CONFIG_RTC_CLK_SRC_INT_RC is not set CONFIG_RTC_CLK_SRC_EXT_CRYS=y -# CONFIG_RTC_CLK_SRC_EXT_OSC is not set -# CONFIG_RTC_CLK_SRC_INT_RC32K is not set # end of RTC Clock Config diff --git a/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32h2 b/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32h2 index 51e03d318ec..6a3908fc5da 100644 --- a/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32h2 +++ b/examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32h2 @@ -2,8 +2,6 @@ CONFIG_IDF_TARGET="esp32h2" # Bluetooth Low Power Config CONFIG_BT_LE_SLEEP_ENABLE=y -# CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER is not set -# CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL is not set CONFIG_BT_LE_LP_CLK_SRC_DEFAULT=y # @@ -24,8 +22,5 @@ CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y # # RTC Clock Config # -# CONFIG_RTC_CLK_SRC_INT_RC is not set CONFIG_RTC_CLK_SRC_EXT_CRYS=y -# CONFIG_RTC_CLK_SRC_EXT_OSC is not set -# CONFIG_RTC_CLK_SRC_INT_RC32K is not set # end of RTC Clock Config diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c b/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c index 060cd61c31a..59fe12c6e80 100644 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c +++ b/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c @@ -217,7 +217,7 @@ static int deep_sleep(int argc, char **argv) io_num, level ? "HIGH" : "LOW"); #if SOC_PM_SUPPORT_EXT1_WAKEUP - ESP_ERROR_CHECK( esp_sleep_enable_ext1_wakeup(1ULL << io_num, level) ); + ESP_ERROR_CHECK( esp_sleep_enable_ext1_wakeup_io(1ULL << io_num, level) ); #endif } diff --git a/examples/build_system/cmake/import_lib/components/tinyxml2/CMakeLists.txt b/examples/build_system/cmake/import_lib/components/tinyxml2/CMakeLists.txt index a3267a016f3..5c20751bb7e 100644 --- a/examples/build_system/cmake/import_lib/components/tinyxml2/CMakeLists.txt +++ b/examples/build_system/cmake/import_lib/components/tinyxml2/CMakeLists.txt @@ -20,7 +20,7 @@ externalproject_add(tinyxml2_proj # Download the source code of the third party project from the following URL. # (Two URLs are provided, the 2nd one is the mirror for Chinese users) URL https://github.com/leethomason/tinyxml2/archive/refs/tags/9.0.0.zip - https://gitcode.net/mirrors/leethomason/tinyxml2/-/archive/9.0.0/tinyxml2-9.0.0.zip + https://dl.espressif.com/dl/tinyxml2/9.0.0.zip # (Downloading is not the only option; the library can also be located in your source tree. # Consult ExternalProject_Add function documentation for other options.) diff --git a/examples/common_components/protocol_examples_common/stdin_out.c b/examples/common_components/protocol_examples_common/stdin_out.c index 5fbc8a38af1..9f3a5163f30 100644 --- a/examples/common_components/protocol_examples_common/stdin_out.c +++ b/examples/common_components/protocol_examples_common/stdin_out.c @@ -9,7 +9,7 @@ #include "protocol_examples_common.h" #include "esp_err.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" #include "sdkconfig.h" @@ -25,10 +25,10 @@ esp_err_t example_configure_stdin_stdout(void) ESP_ERROR_CHECK( uart_driver_install( (uart_port_t)CONFIG_ESP_CONSOLE_UART_NUM, 256, 0, 0, NULL, 0) ); /* Tell VFS to use UART driver */ - esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); - esp_vfs_dev_uart_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); + uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); + uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); /* Move the caret to the beginning of the next line on '\n' */ - esp_vfs_dev_uart_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); configured = true; return ESP_OK; } diff --git a/examples/ethernet/.build-test-rules.yml b/examples/ethernet/.build-test-rules.yml index c0e129ef801..b891fb5b348 100644 --- a/examples/ethernet/.build-test-rules.yml +++ b/examples/ethernet/.build-test-rules.yml @@ -9,8 +9,7 @@ examples/ethernet/basic: - lwip - esp_event - esp_driver_gpio - depends_filepatterns: - - components/driver/spi/**/* + - esp_driver_spi examples/ethernet/enc28j60: disable: @@ -23,8 +22,7 @@ examples/ethernet/enc28j60: - lwip - esp_event - esp_driver_gpio - depends_filepatterns: - - components/driver/spi/**/* + - esp_driver_spi examples/ethernet/iperf: disable_test: @@ -38,8 +36,8 @@ examples/ethernet/iperf: - esp_event - console - esp_driver_gpio + - esp_driver_spi depends_filepatterns: - - components/driver/spi/**/* - examples/common_components/iperf/**/* - examples/common_components/protocol_examples_common/**/* - examples/system/console/advanced/components/cmd_system/**/* diff --git a/examples/mesh/ip_internal_network/partitions.csv b/examples/mesh/ip_internal_network/partitions.csv index d01414b8a90..028e2a905b6 100644 --- a/examples/mesh/ip_internal_network/partitions.csv +++ b/examples/mesh/ip_internal_network/partitions.csv @@ -2,4 +2,4 @@ # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, -factory, app, factory, 0x10000, 1200000, +factory, app, factory, 0x10000, 1200K, diff --git a/examples/network/.build-test-rules.yml b/examples/network/.build-test-rules.yml index 9e71f8abafd..93f5b739c10 100644 --- a/examples/network/.build-test-rules.yml +++ b/examples/network/.build-test-rules.yml @@ -4,8 +4,8 @@ examples/network/bridge: disable_test: - if: IDF_TARGET != "esp32" reason: Generic functionality, no need to be run on specific targets - depends_filepatterns: - - components/driver/spi/**/* + depends_components: + - esp_driver_spi examples/network/eth2ap: disable: diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index 49f57448246..51217281f9e 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -21,10 +21,8 @@ - esp_hw_support examples/openthread/ot_br: - disable: - - if: IDF_TARGET in ["esp32h2", "esp32p4"] - temporary: true - reason: target(s) not supported yet + enable: + - if: SOC_WIFI_SUPPORTED == 1 disable_test: - if: IDF_TARGET in ["esp32", "esp32c3", "esp32c2", "esp32c6", "esp32s2"] temporary: true @@ -33,20 +31,24 @@ examples/openthread/ot_br: examples/openthread/ot_cli: enable: - - if: IDF_TARGET in ["esp32h2", "esp32c6"] + - if: SOC_IEEE802154_SUPPORTED == 1 <<: *openthread_dependencies examples/openthread/ot_rcp: enable: - - if: IDF_TARGET in ["esp32h2", "esp32c6"] + - if: SOC_IEEE802154_SUPPORTED == 1 disable_test: - if: IDF_TARGET == "esp32h2" temporary: true reason: only test on esp32c6 <<: *openthread_dependencies -# To add support for the ESP32-C6 in TZ-302 -examples/openthread/ot_sleepy_device: +examples/openthread/ot_sleepy_device/deep_sleep: + enable: + - if: SOC_IEEE802154_SUPPORTED == 1 + <<: [*openthread_dependencies, *openthread_sleep_dependencies] + +examples/openthread/ot_sleepy_device/light_sleep: enable: - - if: IDF_TARGET in ["esp32h2"] + - if: SOC_IEEE802154_SUPPORTED == 1 <<: [*openthread_dependencies, *openthread_sleep_dependencies] diff --git a/examples/openthread/ot_br/main/esp_ot_br.c b/examples/openthread/ot_br/main/esp_ot_br.c index f0b31fa0b09..4996935c2ce 100644 --- a/examples/openthread/ot_br/main/esp_ot_br.c +++ b/examples/openthread/ot_br/main/esp_ot_br.c @@ -92,8 +92,8 @@ static void ot_task_worker(void *aContext) esp_openthread_launch_mainloop(); // Clean up - esp_netif_destroy(openthread_netif); esp_openthread_netif_glue_deinit(); + esp_netif_destroy(openthread_netif); esp_vfs_eventfd_unregister(); vTaskDelete(NULL); } @@ -105,8 +105,10 @@ void app_main(void) // * task queue // * border router esp_vfs_eventfd_config_t eventfd_config = { -#if CONFIG_OPENTHREAD_RADIO_NATIVE +#if CONFIG_OPENTHREAD_RADIO_NATIVE || CONFIG_OPENTHREAD_RADIO_SPINEL_SPI // * radio driver (A native radio device needs a eventfd for radio driver.) + // * SpiSpinelInterface (The Spi Spinel Interface needs a eventfd.) + // The above will not exist at the same time. .max_fds = 4, #else .max_fds = 3, diff --git a/examples/openthread/ot_br/sdkconfig.defaults b/examples/openthread/ot_br/sdkconfig.defaults index d2ee6928f0c..c223da9ab8f 100644 --- a/examples/openthread/ot_br/sdkconfig.defaults +++ b/examples/openthread/ot_br/sdkconfig.defaults @@ -1,9 +1,3 @@ -# -# libsodium -# -CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y -# end of libsodium - # # Partition Table # @@ -30,7 +24,6 @@ CONFIG_MBEDTLS_ECJPAKE_C=y # CONFIG_OPENTHREAD_ENABLED=y CONFIG_OPENTHREAD_BORDER_ROUTER=y -CONFIG_OPENTHREAD_TREL=y # end of OpenThread # @@ -50,7 +43,6 @@ CONFIG_LWIP_IPV6_AUTOCONFIG=y # # mDNS # -CONFIG_MDNS_STRICT_MODE=y CONFIG_MDNS_MULTIPLE_INSTANCE=y # end of mDNS diff --git a/examples/openthread/ot_cli/main/esp_ot_cli.c b/examples/openthread/ot_cli/main/esp_ot_cli.c index 7baf80062d8..912881c362a 100644 --- a/examples/openthread/ot_cli/main/esp_ot_cli.c +++ b/examples/openthread/ot_cli/main/esp_ot_cli.c @@ -95,8 +95,8 @@ static void ot_task_worker(void *aContext) esp_openthread_launch_mainloop(); // Clean up - esp_netif_destroy(openthread_netif); esp_openthread_netif_glue_deinit(); + esp_netif_destroy(openthread_netif); esp_vfs_eventfd_unregister(); vTaskDelete(NULL); diff --git a/examples/openthread/ot_cli/sdkconfig.defaults b/examples/openthread/ot_cli/sdkconfig.defaults index b998de81760..3e302126d36 100644 --- a/examples/openthread/ot_cli/sdkconfig.defaults +++ b/examples/openthread/ot_cli/sdkconfig.defaults @@ -1,9 +1,3 @@ -# -# libsodium -# -CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y -# end of libsodium - # # Partition Table # diff --git a/examples/openthread/ot_rcp/sdkconfig.defaults b/examples/openthread/ot_rcp/sdkconfig.defaults index cc6c671d8e5..9447d6bf5d4 100644 --- a/examples/openthread/ot_rcp/sdkconfig.defaults +++ b/examples/openthread/ot_rcp/sdkconfig.defaults @@ -1,9 +1,3 @@ -# -# libsodium -# -CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y -# end of libsodium - # # Partition Table # diff --git a/examples/openthread/ot_sleepy_device/deep_sleep/README.md b/examples/openthread/ot_sleepy_device/deep_sleep/README.md index 5ee3f7d9b2d..211570037aa 100644 --- a/examples/openthread/ot_sleepy_device/deep_sleep/README.md +++ b/examples/openthread/ot_sleepy_device/deep_sleep/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-H2 | -| ----------------- | -------- | +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | # OpenThread Sleepy Device Example diff --git a/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c b/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c index 4c2e5924854..c7711406011 100644 --- a/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c +++ b/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c @@ -150,8 +150,8 @@ static void ot_deep_sleep_init(void) const uint64_t gpio_wakeup_pin_mask = 1ULL << gpio_wakeup_pin; // The configuration mode depends on your hardware design. // Since the BOOT button is connected to a pull-up resistor, the wake-up mode is configured as LOW. - const uint64_t ext_wakeup_mode = 0 << gpio_wakeup_pin; - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_with_level_mask(gpio_wakeup_pin_mask, ext_wakeup_mode)); + const uint64_t ext_wakeup_mode = 0; + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(gpio_wakeup_pin_mask, ext_wakeup_mode)); // Also these two GPIO configurations are also depended on the hardware design. // The BOOT button is connected to the pull-up resistor, so enable the pull-up mode and disable the pull-down mode. @@ -193,8 +193,8 @@ static void ot_task_worker(void *aContext) esp_openthread_launch_mainloop(); // Clean up - esp_netif_destroy(openthread_netif); esp_openthread_netif_glue_deinit(); + esp_netif_destroy(openthread_netif); esp_vfs_eventfd_unregister(); vTaskDelete(NULL); diff --git a/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults b/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults index 00774aa81de..ffd005ecd7a 100644 --- a/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults +++ b/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults @@ -45,8 +45,6 @@ CONFIG_IEEE802154_ENABLED=y # # deep sleep # -CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y -CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80 CONFIG_ULP_COPROC_ENABLED=y CONFIG_ULP_COPROC_RESERVE_MEM=512 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y diff --git a/examples/openthread/ot_sleepy_device/light_sleep/README.md b/examples/openthread/ot_sleepy_device/light_sleep/README.md index ebcf8eae273..d49a314b5e6 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/README.md +++ b/examples/openthread/ot_sleepy_device/light_sleep/README.md @@ -1,6 +1,5 @@ -| Supported Targets | ESP32-H2 | -| ----------------- | -------- | - +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | # OpenThread Sleepy Device Example The example demonstrates the Thread Sleepy End Device (SED), the device will enter [Light Sleep mode](https://docs.espressif.com/projects/esp-idf/en/latest/esp32h2/api-reference/system/sleep_modes.html#sleep-modes) during idle state. diff --git a/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c b/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c index ff5812dcd6d..95b5bc2e1d2 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c +++ b/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c @@ -129,8 +129,8 @@ static void ot_task_worker(void *aContext) esp_openthread_launch_mainloop(); // Clean up - esp_netif_destroy(openthread_netif); esp_openthread_netif_glue_deinit(); + esp_netif_destroy(openthread_netif); esp_vfs_eventfd_unregister(); vTaskDelete(NULL); diff --git a/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.ci.sleepy_c6 b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.ci.sleepy_c6 index 80eea908010..f0198c840e7 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.ci.sleepy_c6 +++ b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.ci.sleepy_c6 @@ -3,4 +3,4 @@ CONFIG_IDF_TARGET_ESP32C6=y CONFIG_OPENTHREAD_NETWORK_CHANNEL=12 CONFIG_OPENTHREAD_NETWORK_MASTERKEY="aabbccddeeff00112233445566778899" CONFIG_ESP_SLEEP_DEBUG=y -CONFIG_LOG_DEFAULT_LEVEL_DEBUG=y +CONFIG_LOG_MAXIMUM_LEVEL_DEBUG=y diff --git a/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults.esp32c6 b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults.esp32c6 new file mode 100644 index 00000000000..2c90c3e7eeb --- /dev/null +++ b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults.esp32c6 @@ -0,0 +1,7 @@ +CONFIG_IDF_TARGET="esp32c6" + +# +# Sleep Config +# +CONFIG_ESP_PHY_MAC_BB_PD=y +# end of Sleep Config diff --git a/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults.esp32h2 b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults.esp32h2 new file mode 100644 index 00000000000..ba2980822ca --- /dev/null +++ b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults.esp32h2 @@ -0,0 +1 @@ +CONFIG_IDF_TARGET="esp32h2" diff --git a/examples/openthread/pytest_otbr.py b/examples/openthread/pytest_otbr.py index 349cf19f04d..73ba43eb420 100644 --- a/examples/openthread/pytest_otbr.py +++ b/examples/openthread/pytest_otbr.py @@ -558,9 +558,13 @@ def test_TCP_NAT64(Init_interface:bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) -> N @pytest.mark.openthread_sleep @pytest.mark.parametrize( 'config, count, app_path, target', [ + ('cli_h2|sleepy_c6', 2, + f'{os.path.join(os.path.dirname(__file__), "ot_cli")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_sleepy_device/light_sleep")}', + 'esp32h2|esp32c6'), ('cli_c6|sleepy_h2', 2, f'{os.path.join(os.path.dirname(__file__), "ot_cli")}' - f'|{os.path.join(os.path.dirname(__file__), "ot_sleepy_device")}', + f'|{os.path.join(os.path.dirname(__file__), "ot_sleepy_device/light_sleep")}', 'esp32c6|esp32h2'), ], indirect=True, diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index fcd5d073c1a..b2ceb4fcb34 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -22,6 +22,9 @@ examples/peripherals/analog_comparator: - if: IDF_TARGET == "esp32p4" temporary: true reason: not supported yet + depends_components: + - esp_driver_gpio + - esp_driver_ana_cmpr examples/peripherals/dac: disable: @@ -35,6 +38,12 @@ examples/peripherals/gpio/matrix_keyboard: enable: - if: IDF_TARGET == "esp32s2" +examples/peripherals/i2c/i2c_eeprom: + disable: + - if: SOC_I2C_SUPPORTED != 1 + depends_components: + - esp_driver_i2c + examples/peripherals/i2c/i2c_self_test: disable: - if: SOC_I2C_SUPPORT_SLAVE != 1 @@ -63,6 +72,8 @@ examples/peripherals/i2s/i2s_basic/i2s_pdm: - if: IDF_TARGET == "esp32p4" temporary: true reason: lack of runners + depends_components: + - esp_driver_i2s examples/peripherals/i2s/i2s_basic/i2s_std: disable: @@ -71,6 +82,8 @@ examples/peripherals/i2s/i2s_basic/i2s_std: - if: IDF_TARGET == "esp32p4" temporary: true reason: lack of runners + depends_components: + - esp_driver_i2s examples/peripherals/i2s/i2s_basic/i2s_tdm: disable: @@ -79,6 +92,8 @@ examples/peripherals/i2s/i2s_basic/i2s_tdm: - if: IDF_TARGET == "esp32p4" temporary: true reason: lack of runners + depends_components: + - esp_driver_i2s examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm: disable: @@ -88,6 +103,11 @@ examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm: - if: IDF_TARGET == "esp32p4" temporary: true reason: lack of runners + depends_components: + - esp_driver_i2s + - esp_driver_spi + depends_filepatterns: + - components/driver/i2c/**/* examples/peripherals/i2s/i2s_codec/i2s_es8311: disable: @@ -97,12 +117,19 @@ examples/peripherals/i2s/i2s_codec/i2s_es8311: - if: IDF_TARGET == "esp32p4" temporary: true reason: lack of runners + depends_components: + - esp_driver_i2s + depends_filepatterns: + - components/driver/i2c/**/* examples/peripherals/i2s/i2s_recorder: disable: - if: SOC_SDMMC_HOST_SUPPORTED != 1 or IDF_TARGET == "esp32p4" enable: - if: SOC_I2S_SUPPORTS_PDM_RX > 0 + depends_components: + - esp_driver_spi + - esp_driver_i2s examples/peripherals/lcd/i2c_oled: disable: @@ -117,8 +144,7 @@ examples/peripherals/lcd/i80_controller: - if: SOC_LCD_I80_SUPPORTED != 1 depends_components: - esp_lcd - depends_filepatterns: - - components/driver/i2s/**/* # i80 IO driver relies on I2S on esp32 and esp32s2 + - esp_driver_i2s examples/peripherals/lcd/rgb_panel: disable: @@ -131,16 +157,14 @@ examples/peripherals/lcd/spi_lcd_touch: - if: SOC_GPSPI_SUPPORTED != 1 depends_components: - esp_lcd - depends_filepatterns: - - components/driver/spi/**/* + - esp_driver_spi examples/peripherals/lcd/tjpgd: disable: - if: SOC_GPSPI_SUPPORTED != 1 depends_components: - esp_lcd - depends_filepatterns: - - components/driver/spi/**/* + - esp_driver_spi examples/peripherals/ledc: disable: @@ -153,10 +177,14 @@ examples/peripherals/ledc/ledc_gamma_curve_fade: examples/peripherals/mcpwm: disable: - if: SOC_MCPWM_SUPPORTED != 1 + depends_components: + - esp_driver_mcpwm examples/peripherals/mcpwm/mcpwm_bdc_speed_control: disable: - if: SOC_MCPWM_SUPPORTED != 1 + depends_components: + - esp_driver_mcpwm disable_test: - if: IDF_TARGET != "esp32s3" temporary: true @@ -165,6 +193,8 @@ examples/peripherals/mcpwm/mcpwm_bdc_speed_control: examples/peripherals/mcpwm/mcpwm_bldc_hall_control: disable: - if: SOC_MCPWM_SUPPORTED != 1 + depends_components: + - esp_driver_mcpwm disable_test: - if: IDF_TARGET != "esp32s3" temporary: true @@ -173,6 +203,8 @@ examples/peripherals/mcpwm/mcpwm_bldc_hall_control: examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop: disable: - if: SOC_MCPWM_SUPPORTED != 1 + depends_components: + - esp_driver_mcpwm disable_test: - if: IDF_TARGET != "esp32s3" temporary: true @@ -203,6 +235,8 @@ examples/peripherals/pcnt: examples/peripherals/rmt: disable: - if: SOC_RMT_SUPPORTED != 1 + depends_components: + - esp_driver_rmt examples/peripherals/rmt/ir_nec_transceiver: disable: @@ -211,14 +245,20 @@ examples/peripherals/rmt/ir_nec_transceiver: - if: IDF_TARGET != "esp32" temporary: true reason: lack of runners + depends_components: + - esp_driver_rmt examples/peripherals/rmt/musical_buzzer: disable: - if: SOC_RMT_SUPPORT_TX_LOOP_COUNT != 1 + depends_components: + - esp_driver_rmt examples/peripherals/rmt/stepper_motor: disable: - if: SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP != 1 + depends_components: + - esp_driver_rmt examples/peripherals/sdio/host: disable: @@ -234,6 +274,8 @@ examples/peripherals/sdio/host: - if: IDF_TARGET != "esp32" temporary: true reason: lack of runners + depends_components: + - esp_driver_sdio examples/peripherals/sdio/slave: disable: @@ -242,16 +284,14 @@ examples/peripherals/sdio/slave: - if: IDF_TARGET != "esp32" temporary: true reason: lack of runners - -examples/peripherals/secure_element/atecc608_ecdsa: - enable: - - if: IDF_TARGET == "esp32" - temporary: true - reason: the other targets are not tested yet + depends_components: + - esp_driver_sdio examples/peripherals/sigma_delta: disable: - if: SOC_SDM_SUPPORTED != 1 + depends_components: + - esp_driver_sdm examples/peripherals/spi_master/hd_eeprom: disable: @@ -284,10 +324,14 @@ examples/peripherals/spi_slave_hd/segment_mode/seg_slave: examples/peripherals/temperature_sensor/temp_sensor: disable: - if: SOC_TEMP_SENSOR_SUPPORTED != 1 + depends_components: + - esp_driver_tsens examples/peripherals/temperature_sensor/temp_sensor_monitor: disable: - if: SOC_TEMPERATURE_SENSOR_INTR_SUPPORT != 1 + depends_components: + - esp_driver_tsens examples/peripherals/timer_group/gptimer: disable: @@ -318,11 +362,11 @@ examples/peripherals/touch_sensor/touch_element: examples/peripherals/touch_sensor/touch_sensor_v1: disable: - - if: SOC_TOUCH_VERSION_1 != 1 + - if: SOC_TOUCH_SENSOR_VERSION != 1 examples/peripherals/touch_sensor/touch_sensor_v2: disable: - - if: SOC_TOUCH_VERSION_2 != 1 + - if: SOC_TOUCH_SENSOR_VERSION != 2 examples/peripherals/twai/twai_alert_and_recovery: disable: @@ -354,4 +398,12 @@ examples/peripherals/uart/uart_echo_rs485: examples/peripherals/usb: disable: - - if: SOC_USB_PERIPH_NUM != 1 + - if: SOC_USB_OTG_SUPPORTED != 1 + +examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo: + disable: + - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET not in ["esp32c6"] + temporary: true + reason: lack of runners. Hardware is similar, test on one target is enough currently. diff --git a/examples/peripherals/analog_comparator/CMakeLists.txt b/examples/peripherals/analog_comparator/CMakeLists.txt index fa9f99dcd0f..914719a3fbd 100644 --- a/examples/peripherals/analog_comparator/CMakeLists.txt +++ b/examples/peripherals/analog_comparator/CMakeLists.txt @@ -5,4 +5,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(analog_comparator_example) diff --git a/examples/peripherals/analog_comparator/main/CMakeLists.txt b/examples/peripherals/analog_comparator/main/CMakeLists.txt index 07070ae0204..2a349279452 100644 --- a/examples/peripherals/analog_comparator/main/CMakeLists.txt +++ b/examples/peripherals/analog_comparator/main/CMakeLists.txt @@ -7,4 +7,5 @@ else() endif() idf_component_register(SRCS ${src} + PRIV_REQUIRES esp_driver_ana_cmpr esp_driver_gpio INCLUDE_DIRS ".") diff --git a/examples/peripherals/dac/dac_continuous/dac_audio/CMakeLists.txt b/examples/peripherals/dac/dac_continuous/dac_audio/CMakeLists.txt index eefcf9cbcd6..76186554844 100644 --- a/examples/peripherals/dac/dac_continuous/dac_audio/CMakeLists.txt +++ b/examples/peripherals/dac/dac_continuous/dac_audio/CMakeLists.txt @@ -2,5 +2,8 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(dac_audio) diff --git a/examples/peripherals/dac/dac_continuous/dac_audio/main/CMakeLists.txt b/examples/peripherals/dac/dac_continuous/dac_audio/main/CMakeLists.txt index 403d266ed29..93e667506c0 100644 --- a/examples/peripherals/dac/dac_continuous/dac_audio/main/CMakeLists.txt +++ b/examples/peripherals/dac/dac_continuous/dac_audio/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "dac_audio_example_main.c" - INCLUDE_DIRS ".") + INCLUDE_DIRS "." + PRIV_REQUIRES esp_driver_dac) diff --git a/examples/peripherals/dac/dac_continuous/signal_generator/CMakeLists.txt b/examples/peripherals/dac/dac_continuous/signal_generator/CMakeLists.txt index 99e61f9ac5a..9ad91aea668 100644 --- a/examples/peripherals/dac/dac_continuous/signal_generator/CMakeLists.txt +++ b/examples/peripherals/dac/dac_continuous/signal_generator/CMakeLists.txt @@ -2,5 +2,8 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(signal_generator) diff --git a/examples/peripherals/dac/dac_continuous/signal_generator/main/CMakeLists.txt b/examples/peripherals/dac/dac_continuous/signal_generator/main/CMakeLists.txt index 5a747f839f5..be52464f65b 100644 --- a/examples/peripherals/dac/dac_continuous/signal_generator/main/CMakeLists.txt +++ b/examples/peripherals/dac/dac_continuous/signal_generator/main/CMakeLists.txt @@ -3,4 +3,5 @@ set(srcs "dac_continuous_example_main.c" "dac_continuous_example_timer.c") idf_component_register(SRCS "${srcs}" - INCLUDE_DIRS ".") + INCLUDE_DIRS "." + PRIV_REQUIRES esp_driver_dac esp_driver_gpio esp_driver_gptimer esp_adc) diff --git a/examples/peripherals/dac/dac_cosine_wave/CMakeLists.txt b/examples/peripherals/dac/dac_cosine_wave/CMakeLists.txt index 85484ad64e5..531110f366c 100644 --- a/examples/peripherals/dac/dac_cosine_wave/CMakeLists.txt +++ b/examples/peripherals/dac/dac_cosine_wave/CMakeLists.txt @@ -2,5 +2,8 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(dac_cosine_wave) diff --git a/examples/peripherals/dac/dac_cosine_wave/main/CMakeLists.txt b/examples/peripherals/dac/dac_cosine_wave/main/CMakeLists.txt index f61c2b3e9f6..93a85ec4159 100644 --- a/examples/peripherals/dac/dac_cosine_wave/main/CMakeLists.txt +++ b/examples/peripherals/dac/dac_cosine_wave/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "dac_cosine_example_main.c" - INCLUDE_DIRS ".") + INCLUDE_DIRS "." + PRIV_REQUIRES esp_driver_dac esp_adc) diff --git a/examples/peripherals/dac/dac_oneshot/CMakeLists.txt b/examples/peripherals/dac/dac_oneshot/CMakeLists.txt index 66b66a84e72..0f427f4d0e4 100644 --- a/examples/peripherals/dac/dac_oneshot/CMakeLists.txt +++ b/examples/peripherals/dac/dac_oneshot/CMakeLists.txt @@ -2,5 +2,8 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(dac_oneshot) diff --git a/examples/peripherals/dac/dac_oneshot/main/CMakeLists.txt b/examples/peripherals/dac/dac_oneshot/main/CMakeLists.txt index 3ff1cab0607..0fe75058c50 100644 --- a/examples/peripherals/dac/dac_oneshot/main/CMakeLists.txt +++ b/examples/peripherals/dac/dac_oneshot/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "dac_oneshot_example_main.c" - INCLUDE_DIRS ".") + INCLUDE_DIRS "." + PRIV_REQUIRES esp_driver_dac esp_adc) diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_pdm/CMakeLists.txt index d36bacbe7b2..d5a6a35e1fb 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/CMakeLists.txt @@ -3,4 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(i2s_pdm_example) diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt index 01e2ce81d4c..f4e512386a6 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt @@ -9,4 +9,5 @@ if(CONFIG_SOC_I2S_SUPPORTS_PDM_RX AND CONFIG_EXAMPLE_PDM_RX) endif() idf_component_register(SRCS "${srcs}" + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_std/CMakeLists.txt index 3a5fb14727a..46dd23bba43 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_std/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_std/CMakeLists.txt @@ -3,4 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(i2s_std_example) diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt index 6ae8228b9d5..dca2bfa303b 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "i2s_std_example_main.c" + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_tdm/CMakeLists.txt index 6158d496e1f..8acb7b8a39c 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/CMakeLists.txt @@ -3,4 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(i2s_tdm_example) diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt index 90a398149fc..79edfd99254 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "i2s_tdm_example_main.c" + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt index 28f0ad3ad3b..515e28c303e 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt @@ -3,4 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(es7210_tdm_record_example) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt index b8fba1348e3..0241da8899b 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt @@ -1,3 +1,4 @@ idf_component_register(SRCS "i2s_es7210_record_example.c" + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio fatfs INCLUDE_DIRS "$ENV{IDF_PATH}/examples/peripherals/i2s/common" ) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es8311/CMakeLists.txt index 94b5eb3206a..f4203cb3ac8 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/CMakeLists.txt @@ -3,4 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(i2s-es8311-example) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/CMakeLists.txt index 6acf1972e28..bcedc48daa3 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "i2s_es8311_example.c" + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio EMBED_FILES "canon.pcm") diff --git a/examples/peripherals/i2s/i2s_recorder/CMakeLists.txt b/examples/peripherals/i2s/i2s_recorder/CMakeLists.txt index 4958e595d6d..31e41a08991 100644 --- a/examples/peripherals/i2s/i2s_recorder/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_recorder/CMakeLists.txt @@ -3,4 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) + project(esp32_i2s_driver_example) diff --git a/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt index 5c060abbce5..805f8fee955 100644 --- a/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt @@ -1,2 +1,3 @@ idf_component_register(SRCS "i2s_recorder_main.c" + PRIV_REQUIRES esp_driver_i2s fatfs INCLUDE_DIRS "$ENV{IDF_PATH}/examples/peripherals/i2s/common") diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/CMakeLists.txt b/examples/peripherals/secure_element/atecc608_ecdsa/CMakeLists.txt deleted file mode 100644 index 9d2688db774..00000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# The following lines of boilerplate have to be in your project's CMakeLists -# in this exact order for cmake to work correctly -cmake_minimum_required(VERSION 3.16) - -include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(atecc608a_ecdsa) diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/README.md b/examples/peripherals/secure_element/atecc608_ecdsa/README.md deleted file mode 100644 index de326e76079..00000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/README.md +++ /dev/null @@ -1,54 +0,0 @@ -| Supported Targets | ESP32 | -| ----------------- | ----- | - -# ECDSA sign/verify Example with ESP32-WROOM-32SE - -## Description - -(See the README.md file in the upper level 'examples' directory for more information about examples.) - -This example requires [ESP32-WROOM-32SE](https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32se_datasheet_en.pdf) which has Microchip's [ATECC608A](https://www.microchip.com/wwwproducts/en/ATECC608A) (Secure Element) integrated on the module. - -The example performs `ECDSA sign/verify` functions on sample data using hardware private key stored in ATECC608A chip. If you want to use bare `ATECC608A` chip (Secure Element) with `ESP32-WROOM-32` module by making external connections, please refer [this](https://github.com/espressif/esp-cryptoauthlib/blob/master/esp_cryptoauth_utility/README.md#using-atecc608a-with-esp32-wroom-32) for details. - -## How to use example - -Before project configuration and build, be sure to set the correct chip target using `idf.py set-target `. - -### Hardware Required - -To get started you will need a `ESP32-WROOM-32SE` development board which integrates Microchip’s ATECC608A CryptoAuth chip in the module. - -* A development board with ESP32-WROOM-32SE SoC or an custom board with the `ATECC608A` IC. -* A USB cable for Power supply and programming - -### Configure the project - -ATECC608A chip on ESP32-WROOM-32SE should be configured to run the example, for details on configuration of ATECC608A chip, please refer [esp_cryptoauth_utility](https://github.com/espressif/esp-cryptoauthlib/blob/master/esp_cryptoauth_utility/README.md#esp_cryptoauth_utility) - -Open the project configuration menu (`idf.py menuconfig`). - -In the `Component config -> esp-cryptoauthlib` menu: - -* Use `Choose the type of ATECC608A chip` to set the Crypto IC type [1]. -* Use `Enable Hardware ECDSA keys for mbedTLS` Enable Hardware ECDSA. - * Set `Enable ATECC608A sign operations in mbedTLS` to use Hardware ECDSA sign. - * Set `Enable ATECC608A verify operations in mbedTLS` to use Hardware ECDSA verify. -* Set `I2C SDA pin used to communicate with the ATECC608A`. -* Set `I2C SCL pin used to communicate with the ATECC608A`. - -[1]: for more details refer [Find ATECC608A chip type](https://github.com/espressif/esp-cryptoauthlib/blob/master/esp_cryptoauth_utility/README.md#find-type-of-atecc608a-chip-connected-to-esp32-wroom32-se). - -### Build and Flash - -Build the project and flash it to the board, then run the monitor tool to view the serial output: - -Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. - -(To exit the serial monitor, type ``Ctrl-]``.) - -See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for all the steps to configure and use the ESP-IDF to build projects. - -## Troubleshooting - -For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/main/CMakeLists.txt b/examples/peripherals/secure_element/atecc608_ecdsa/main/CMakeLists.txt deleted file mode 100644 index 0122eb9541d..00000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/main/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Main component CMakeLists.txt -idf_component_register( - SRC_DIRS "." - INCLUDE_DIRS "." - ) diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/main/ecdsa_example_main.c b/examples/peripherals/secure_element/atecc608_ecdsa/main/ecdsa_example_main.c deleted file mode 100644 index 516a03c929e..00000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/main/ecdsa_example_main.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * atecc608a_ecdsa example - * - * SPDX-FileCopyrightText: 2006-2016 ARM Limited, All Rights Reserved - * - * SPDX-License-Identifier: Apache-2.0 - * - * SPDX-FileContributor: 2015-2023 Espressif Systems (Shanghai) CO LTD - */ - -/* This is mbedtls boilerplate for library configuration */ -#include "mbedtls/mbedtls_config.h" - -/* System Includes*/ -#include -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "esp_system.h" -#include "spi_flash_mmap.h" -#include "esp_log.h" - -/* Cryptoauthlib includes */ -#include "cryptoauthlib.h" -#include "mbedtls/atca_mbedtls_wrap.h" - -/* mbedTLS includes */ -#include "mbedtls/platform.h" -#include "mbedtls/debug.h" -#include "mbedtls/ssl.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ctr_drbg.h" -#include "mbedtls/pk.h" - -static const char *TAG = "atecc_example"; -/* globals for mbedtls RNG */ -static mbedtls_entropy_context entropy; -static mbedtls_ctr_drbg_context ctr_drbg; - -static int configure_mbedtls_rng(void) -{ - int ret; - const char * seed = "some random seed string"; - mbedtls_ctr_drbg_init(&ctr_drbg); - - ESP_LOGI(TAG, "Seeding the random number generator..."); - - mbedtls_entropy_init(&entropy); - ret = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, - (const unsigned char *)seed, strlen(seed)); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! mbedtls_ctr_drbg_seed returned %d", ret); - } else { - ESP_LOGI(TAG, " ok"); - } - return ret; -} - -static void close_mbedtls_rng(void) -{ - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); -} - -/* An example hash */ -static unsigned char hash[32] = { - 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, - 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad -}; - -static const uint8_t public_key_x509_header[] = { - 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x08, 0x2A, - 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x07, 0x03, 0x42, 0x00, 0x04 -}; - -static void print_public_key(uint8_t *pubkey) -{ - uint8_t buf[128]; - uint8_t * tmp; - size_t buf_len = sizeof(buf); - - /* Calculate where the raw data will fit into the buffer */ - tmp = buf + sizeof(buf) - ATCA_PUB_KEY_SIZE - sizeof(public_key_x509_header); - - /* Copy the header */ - memcpy(tmp, public_key_x509_header, sizeof(public_key_x509_header)); - - /* Copy the key bytes */ - memcpy(tmp + sizeof(public_key_x509_header), pubkey, ATCA_PUB_KEY_SIZE); - - /* Convert to base 64 */ - (void)atcab_base64encode(tmp, ATCA_PUB_KEY_SIZE + sizeof(public_key_x509_header), (char*)buf, &buf_len); - - /* Add a null terminator */ - buf[buf_len] = '\0'; - - /* Print out the key */ - ESP_LOGI(TAG, "\r\n-----BEGIN PUBLIC KEY-----\r\n%s\r\n-----END PUBLIC KEY-----", buf); -} - -static int atca_ecdsa_test(void) -{ - mbedtls_pk_context pkey; - int ret; - unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; - size_t olen = 0; - - /* ECDSA Sign/Verify */ - -#ifdef MBEDTLS_ECDSA_SIGN_ALT - /* Convert to an mbedtls key */ - ESP_LOGI(TAG, " Using a hardware private key ..."); - ret = atca_mbedtls_pk_init(&pkey, 0); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! atca_mbedtls_pk_init returned %02x", ret); - goto exit; - } - ESP_LOGI(TAG, " ok"); -#else - ESP_LOGI(TAG, " Generating a software private key ..."); - mbedtls_pk_init(&pkey); - ret = mbedtls_pk_setup(&pkey, - mbedtls_pk_info_from_type(MBEDTLS_PK_ECDSA)); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! mbedtls_pk_setup returned -0x%04x", -ret); - goto exit; - } - - ret = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, - mbedtls_pk_ec(pkey), - mbedtls_ctr_drbg_random, &ctr_drbg); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! mbedtls_ecp_gen_key returned -0x%04x", -ret); - goto exit; - } - ESP_LOGI(TAG, " ok"); -#endif - - ESP_LOGI(TAG, " Generating ECDSA Signature..."); - ret = mbedtls_pk_sign(&pkey, MBEDTLS_MD_SHA256, hash, 0, buf, MBEDTLS_MPI_MAX_SIZE, &olen, - mbedtls_ctr_drbg_random, &ctr_drbg); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! mbedtls_pk_sign returned -0x%04x", -ret); - goto exit; - } - ESP_LOGI(TAG, " ok"); - - ESP_LOGI(TAG, " Verifying ECDSA Signature..."); - ret = mbedtls_pk_verify(&pkey, MBEDTLS_MD_SHA256, hash, 0, - buf, olen); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! mbedtls_pk_verify returned -0x%04x", -ret); - goto exit; - } - ESP_LOGI(TAG, " ok"); - -exit: - fflush(stdout); - return ret; -} - -void app_main(void) -{ - int ret = 0; - bool lock; - uint8_t buf[ATCA_ECC_CONFIG_SIZE]; - uint8_t pubkey[ATCA_PUB_KEY_SIZE]; - - /* Initialize the mbedtls library */ - ret = configure_mbedtls_rng(); -#ifdef CONFIG_ATECC608A_TNG - ESP_LOGI(TAG, " . Initialize the ATECC interface for Trust & GO ..."); - cfg_ateccx08a_i2c_default.atcai2c.address = 0x6A; -#elif CONFIG_ATECC608A_TFLEX /* CONFIG_ATECC608A_TNGO */ - ESP_LOGI(TAG, " . Initialize the ATECC interface for TrustFlex ..."); - cfg_ateccx08a_i2c_default.atcai2c.address = 0x6C; -#elif CONFIG_ATECC608A_TCUSTOM /* CONFIG_ATECC608A_TFLEX */ - ESP_LOGI(TAG, " . Initialize the ATECC interface for TrustCustom ..."); - /* Default slave address is same as that of TCUSTOM ATECC608A chips */ -#endif /* CONFIG_ATECC608A_TCUSTOM */ - ret = atcab_init(&cfg_ateccx08a_i2c_default); - if (ret != 0) { - ESP_LOGI(TAG, " failed ! atcab_init returned %02x", ret); - goto exit; - } - ESP_LOGI(TAG, " ok"); - - lock = 0; - ESP_LOGI(TAG, " Check the data zone lock status..."); - ret = atcab_is_locked(LOCK_ZONE_DATA, &lock); - if (ret != 0) { - ESP_LOGI(TAG, " failed\n ! atcab_is_locked returned %02x", ret); - goto exit; - } - - if (lock) { - ESP_LOGI(TAG, " ok: locked"); - } else { - ESP_LOGE(TAG, "unlocked, please lock(configure) the ATECC608A chip with help of esp_cryptoauth_utility and try again"); - goto exit; - } - - ESP_LOGI(TAG, " Get the device info (type)..."); - ret = atcab_info(buf); - if (ret != 0) { - ESP_LOGI(TAG, " failed\n ! atcab_info returned %02x", ret); - goto exit; - } - ESP_LOGI(TAG, " ok: %02x %02x", buf[2], buf[3]); - - ESP_LOGI(TAG, " Get the public key..."); - ret = atcab_get_pubkey(0, pubkey); - if (ret != 0) { - ESP_LOGI(TAG, " failed\n ! atcab_get_pubkey returned %02x", ret); - goto exit; - } - ESP_LOGI(TAG, " ok"); - print_public_key(pubkey); - - /* Perform a Sign/Verify Test */ - ret = atca_ecdsa_test(); - if (ret != 0) { - ESP_LOGE(TAG, " ECDSA sign/verify failed"); - goto exit; - } - -exit: - fflush(stdout); - close_mbedtls_rng(); - -} diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/main/idf_component.yml b/examples/peripherals/secure_element/atecc608_ecdsa/main/idf_component.yml deleted file mode 100644 index 6eb177a228a..00000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/main/idf_component.yml +++ /dev/null @@ -1,3 +0,0 @@ -## IDF Component Manager Manifest File -dependencies: - espressif/esp-cryptoauthlib: "^3.3.1" diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/sdkconfig.defaults b/examples/peripherals/secure_element/atecc608_ecdsa/sdkconfig.defaults deleted file mode 100644 index b704bedeffd..00000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/sdkconfig.defaults +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ATCA_MBEDTLS_ECDSA=y -CONFIG_ATCA_MBEDTLS_ECDSA_SIGN=y -CONFIG_ATCA_MBEDTLS_ECDSA_VERIFY=y diff --git a/examples/peripherals/sigma_delta/sdm_dac/README.md b/examples/peripherals/sigma_delta/sdm_dac/README.md index 42cd73b2bff..e7d7f71b6e4 100644 --- a/examples/peripherals/sigma_delta/sdm_dac/README.md +++ b/examples/peripherals/sigma_delta/sdm_dac/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Sigma Delta Modulation DAC Example diff --git a/examples/peripherals/sigma_delta/sdm_led/README.md b/examples/peripherals/sigma_delta/sdm_led/README.md index 3031bd36051..6a61366950a 100644 --- a/examples/peripherals/sigma_delta/sdm_led/README.md +++ b/examples/peripherals/sigma_delta/sdm_led/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Sigma Delta Modulation LED Example diff --git a/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c b/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c index c07e3913a5f..25a74520eda 100644 --- a/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c +++ b/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c @@ -87,7 +87,7 @@ DRAM_ATTR static const lcd_init_cmd_t st_init_cmds[] = { /* Frame Rate Control, 60Hz, inversion=0 */ {0xC6, {0x0f}, 1}, /* Power Control 1, AVDD=6.8V, AVCL=-4.8V, VDDS=2.3V */ - {0xD0, {0xA4, 0xA1}, 1}, + {0xD0, {0xA4, 0xA1}, 2}, /* Positive Voltage Gamma Control */ {0xE0, {0xD0, 0x00, 0x05, 0x0E, 0x15, 0x0D, 0x37, 0x43, 0x47, 0x09, 0x15, 0x12, 0x16, 0x19}, 14}, /* Negative Voltage Gamma Control */ @@ -333,13 +333,13 @@ static void send_lines(spi_device_handle_t spi, int ypos, uint16_t *linedata) trans[0].tx_data[0] = 0x2A; //Column Address Set trans[1].tx_data[0] = 0; //Start Col High trans[1].tx_data[1] = 0; //Start Col Low - trans[1].tx_data[2] = (320) >> 8; //End Col High - trans[1].tx_data[3] = (320) & 0xff; //End Col Low + trans[1].tx_data[2] = (320 - 1) >> 8; //End Col High + trans[1].tx_data[3] = (320 - 1) & 0xff; //End Col Low trans[2].tx_data[0] = 0x2B; //Page address set trans[3].tx_data[0] = ypos >> 8; //Start page high trans[3].tx_data[1] = ypos & 0xff; //start page low - trans[3].tx_data[2] = (ypos + PARALLEL_LINES) >> 8; //end page high - trans[3].tx_data[3] = (ypos + PARALLEL_LINES) & 0xff; //end page low + trans[3].tx_data[2] = (ypos + PARALLEL_LINES - 1) >> 8; //end page high + trans[3].tx_data[3] = (ypos + PARALLEL_LINES - 1) & 0xff; //end page low trans[4].tx_data[0] = 0x2C; //memory write trans[5].tx_buffer = linedata; //finally send the line data trans[5].length = 320 * 2 * 8 * PARALLEL_LINES; //Data length, in bits diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c index 10837efb7c1..e8a671ecfcb 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c +++ b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c @@ -196,7 +196,7 @@ void app_main(void) /* Filter setting */ touchsensor_filter_set(TOUCH_PAD_FILTER_IIR_16); - touch_pad_timeout_set(true, SOC_TOUCH_PAD_THRESHOLD_MAX); + touch_pad_timeout_set(true, TOUCH_PAD_THRESHOLD_MAX); /* Register touch interrupt ISR, enable intr type. */ touch_pad_isr_register(touchsensor_interrupt_cb, NULL, TOUCH_PAD_INTR_MASK_ALL); /* If you have other touch algorithm, you can get the measured value after the `TOUCH_PAD_INTR_MASK_SCAN_DONE` interrupt is generated. */ diff --git a/examples/peripherals/uart/uart_select/main/uart_select_example_main.c b/examples/peripherals/uart/uart_select/main/uart_select_example_main.c index 065837e4449..7364290a3c0 100644 --- a/examples/peripherals/uart/uart_select/main/uart_select_example_main.c +++ b/examples/peripherals/uart/uart_select/main/uart_select_example_main.c @@ -14,8 +14,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_log.h" -#include "esp_vfs.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" static const char* TAG = "uart_select_example"; @@ -48,7 +47,7 @@ static void uart_select_task(void *arg) } // We have a driver now installed so set up the read/write functions to use driver also. - esp_vfs_dev_uart_use_driver(0); + uart_vfs_dev_use_driver(0); while (1) { int s; diff --git a/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/sdkconfig.defaults b/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/sdkconfig.defaults index 12e3b2f205a..087e74a60c5 100644 --- a/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/sdkconfig.defaults +++ b/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/sdkconfig.defaults @@ -1,7 +1,6 @@ # This file was generated using idf.py save-defconfig. It can be edited manually. # Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration # -CONFIG_TINYUSB=y CONFIG_TINYUSB_MSC_ENABLED=y CONFIG_PARTITION_TABLE_CUSTOM=y diff --git a/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py b/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py index dc8868a8f12..68a7e34cf08 100644 --- a/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py +++ b/examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py @@ -10,11 +10,6 @@ def test_usb_device_msc_example(dut: Dut) -> None: dut.expect('Mount storage') dut.expect('TinyUSB Driver installed') dut.expect('USB MSC initialization DONE') - dut.write(' help') - dut.expect('read') - dut.expect('write') - dut.expect('size') - dut.expect('expose') - dut.expect('status') - dut.write(' status') + dut.expect('esp32s2>') + dut.write('status') dut.expect('storage exposed over USB') diff --git a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c index e7a06ea59fe..2a8b4c2dbfb 100644 --- a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c +++ b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c @@ -74,7 +74,6 @@ static void action_get_info(class_driver_t *driver_obj) ESP_ERROR_CHECK(usb_host_device_info(driver_obj->dev_hdl, &dev_info)); ESP_LOGI(TAG, "\t%s speed", (dev_info.speed == USB_SPEED_LOW) ? "Low" : "Full"); ESP_LOGI(TAG, "\tbConfigurationValue %d", dev_info.bConfigurationValue); - //Todo: Print string descriptors //Get the device descriptor next driver_obj->actions &= ~ACTION_GET_DEV_INFO; diff --git a/examples/peripherals/usb/host/uvc/README.md b/examples/peripherals/usb/host/uvc/README.md index 70e32a43b01..06f908e0b0a 100644 --- a/examples/peripherals/usb/host/uvc/README.md +++ b/examples/peripherals/usb/host/uvc/README.md @@ -10,14 +10,11 @@ This example demonstrates how to: - Capture video from a USB camera using the `libuvc` library. - Stream the video over WiFi by hosting a TCP server. -The example enumerates connected camera, negotiates selected resolution together with `FPS` and starts capturing video. -`frame_callback` function is then invoked after receiving each frame. User can process received frame according to his needs. +The example enumerates a connected USB camera, negotiates a selected resolution along with an associated `FPS`, then starts capturing video. The `frame_callback` function is then invoked after receiving each frame. Users can process the received frames according to their needs. -Optionally, captured video can be visualized on computer with help of `player.py` script located in this example. -After setting `Enable streaming` menuconfig option, example will create TCP server upon start, and wait until `player.py` connects to server. -Once connection is established, example streams each received frame to computer for visualization. +Optionally, the captured video can be visualized on a PC with help of the `player.py` script provided in this example. After setting the `Example Configuration->Enable streaming` option in menuconfig, the example will create a TCP server upon startup, and waits until `player.py` connects to the server. Once a connection is established, the example streams each received frame to the PC for visualization. The network connection can be configured in menuconfig via `Example Connection Configuration`. -**Notice** that `libuvc` selects highest possible `dwMaxPayloadTransferSize` by default, so example has to manually overwrite this value to 512 bytes (maximum transfer size supported by ESP32-S2/S3). +**Notice** that `libuvc` selects highest possible `dwMaxPayloadTransferSize` by default. As a result, this example will manually overwrite this value to 512 bytes (the maximum packet size supported by ESP32-S2/S3). (See the README.md file in the upper level 'examples' directory for more information about examples.) @@ -25,8 +22,11 @@ Once connection is established, example streams each received frame to computer ### Hardware Required -This example requires any ESP32-S2 or ESP32-S3 with external PSRAM and exposed USB connector attached to USB camera. -*ESP module without external PSRAM will fail to initialize* +* ESP with USB peripheral and external PSRAM +* Exposed USB host connector +* USB camera + +Running this example on an **ESP module without external PSRAM will fail on initialization**. Please select your PSRAM configuration in menuconfig `Component config->ESP PSRAM`. If you manually disable PSRAM, the required framebuffers might not fit into DRAM (especially on ESP32-S2). ### Configure the project @@ -51,36 +51,31 @@ In the `Example Configuration` menu: Optional: If you need, change the other options according to your requirements. -Additionally, `player.py` python script makes use of `opencv-python` and `numpy` packages, -not included in `idf-env` environment. Run following commands to install: -* `pip install opencv-python` -* `pip install numpy` +Additionally, the `player.py` python script makes use of the `opencv-python` and `numpy` packages which are not included in the `idf-env` environment by default. Run following command to install those packages: + +```bash +pip install opencv-python numpy +``` #### UVC Protocol Mode: Auto -When protocol mode set to Auto, the example tries to make three attempts to negotiatiate -the protocol with following parameters: +When the protocol mode is set to Auto, the example will make three attempts to negotiate the protocol with following parameters: -1 Attempt: 640x480, 15 FPS, MJPEG -2 Attempt: 320x240, 30 FPS, MJPEG -3 Attempt: 320x240, first available FPS, MJPEG +1. Attempt: 640x480, 15 FPS, MJPEG +2. Attempt: 320x240, 30 FPS, MJPEG +3. Attempt: 320x240, first available FPS, MJPEG -If all three attempts result in an error, the example displays the error message and -suggests to try another USB UVC Device. +If all three attempts result in an error, the example displays the error message and suggests to try another USB UVC Device. #### UVC Protocol Mode: Custom -When protocol mode set to Custom, the example tries to negotiate protocol with -configured parameters: Attempts, Width, Heighs, FPS, Frame Coding format. -After all attemts result in an error, the example displays the error message and -suggests to try another USB UVC Device. - +When the protocol mode set to Custom, the example tries to negotiate the protocol using user provided values for the following parameters: Attempts, Width, Height, FPS, and Frame Coding format. After all attempts result in an error, the example displays the error message and suggests to try another USB UVC device. ### Build and Flash Build the project and flash it to the board, then run the monitor tool to view the serial output: -Run `idf.py set-target esp32s2` to set target chip. +Run `idf.py set-target esp32xx` to set target chip. Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. @@ -90,14 +85,14 @@ See the Getting Started Guide for all the steps to configure and use the ESP-IDF ## Known limitations -Having only Full Speed USB peripheral and hardware limited MPS (maximum packet size) to 512 bytes, ESP32-S2/S3 is capable of reading about 0.5 MB of data per second. When connected to Full Speed USB host, cameras normally provide resolution no larger than 640x480 pixels. -Following two supported formats are the most common (both encoded in MJPEG): - * 320x240 30 FPS - * 640x480 15 FPS +Having only a Full Speed USB peripheral and hardware limited MPS (maximum packet size) to 512 bytes, the ESP32-S2/S3 is capable of reading data at approximately 0.5 MB/s. When connected to Full Speed USB host, cameras normally provide resolution no larger than 640x480 pixels. The following two formats are the most commonly supported at Full Speed (both encoded in MJPEG): +* 320x240 30 FPS +* 640x480 15 FPS ## Tested cameras - * Logitech C980 - * CANYON CNE-CWC2 +* Logitech C980 +* Logitech C270 +* CANYON CNE-CWC2 ## Example Output @@ -108,89 +103,89 @@ I (1606) example: Device found DEVICE CONFIGURATION (0c45:6340/ S) --- Status: idle VideoControl: - bcdUVC: 0x0100 + bcdUVC: 0x0100 VideoStreaming(1): - bEndpointAddress: 129 - Formats: - MJPEGFormat(1) - bits per pixel: 0 - GUID: 4d4a5047000000000000000000000000 (MJPG) - default frame: 1 - aspect ratio: 0x0 - interlace flags: 00 - copy protect: 00 - FrameDescriptor(1) - capabilities: 00 - size: 640x480 - bit rate: 24576000-147456000 - max frame size: 614400 - default interval: 1/30 - interval[0]: 1/30 - interval[1]: 1/25 - interval[2]: 1/20 - interval[3]: 1/15 - interval[4]: 1/10 - interval[5]: 1/5 - FrameDescriptor(2) - capabilities: 00 - size: 352x288 - bit rate: 8110080-48660480 - max frame size: 202752 - default interval: 1/30 - interval[0]: 1/30 - interval[1]: 1/25 - interval[2]: 1/20 - interval[3]: 1/15 - interval[4]: 1/10 - interval[5]: 1/5 - FrameDescriptor(3) - capabilities: 00 - size: 320x240 - bit rate: 6144000-36864000 - max frame size: 153600 - default interval: 1/30 - interval[0]: 1/30 - interval[1]: 1/25 - interval[2]: 1/20 - interval[3]: 1/15 - interval[4]: 1/10 - interval[5]: 1/5 - FrameDescriptor(4) - capabilities: 00 - size: 176x144 - bit rate: 2027520-12165120 - max frame size: 50688 - default interval: 1/30 - interval[0]: 1/30 - interval[1]: 1/25 - interval[2]: 1/20 - interval[3]: 1/15 - interval[4]: 1/10 - interval[5]: 1/5 - FrameDescriptor(5) - capabilities: 00 - size: 160x120 - bit rate: 1536000-9216000 - max frame size: 38400 - default interval: 1/30 - interval[0]: 1/30 - interval[1]: 1/25 - interval[2]: 1/20 - interval[3]: 1/15 - interval[4]: 1/10 - interval[5]: 1/5 - StillFrameDescriptor - bEndPointAddress: 00 - wWidth(1) = 640 - wHeight(1) = 480 - wWidth(2) = 352 - wHeight(2) = 288 - wWidth(3) = 320 - wHeight(3) = 240 - wWidth(4) = 176 - wHeight(4) = 144 - wWidth(5) = 160 - wHeight(5) = 120 + bEndpointAddress: 129 + Formats: + MJPEGFormat(1) + bits per pixel: 0 + GUID: 4d4a5047000000000000000000000000 (MJPG) + default frame: 1 + aspect ratio: 0x0 + interlace flags: 00 + copy protect: 00 + FrameDescriptor(1) + capabilities: 00 + size: 640x480 + bit rate: 24576000-147456000 + max frame size: 614400 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(2) + capabilities: 00 + size: 352x288 + bit rate: 8110080-48660480 + max frame size: 202752 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(3) + capabilities: 00 + size: 320x240 + bit rate: 6144000-36864000 + max frame size: 153600 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(4) + capabilities: 00 + size: 176x144 + bit rate: 2027520-12165120 + max frame size: 50688 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(5) + capabilities: 00 + size: 160x120 + bit rate: 1536000-9216000 + max frame size: 38400 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + StillFrameDescriptor + bEndPointAddress: 00 + wWidth(1) = 640 + wHeight(1) = 480 + wWidth(2) = 352 + wHeight(2) = 288 + wWidth(3) = 320 + wHeight(3) = 240 + wWidth(4) = 176 + wHeight(4) = 144 + wWidth(5) = 160 + wHeight(5) = 120 END DEVICE CONFIGURATION I (1796) example: Negotiate streaming profile 640x480, fps 15 ... I (1816) example: Negotiation complete. diff --git a/examples/peripherals/usb/host/uvc/main/CMakeLists.txt b/examples/peripherals/usb/host/uvc/main/CMakeLists.txt index ba600886a1b..48b187a50bf 100644 --- a/examples/peripherals/usb/host/uvc/main/CMakeLists.txt +++ b/examples/peripherals/usb/host/uvc/main/CMakeLists.txt @@ -1,3 +1,11 @@ idf_component_register(SRCS "main.c" "tcp_server.c" INCLUDE_DIRS "" - PRIV_REQUIRES protocol_examples_common nvs_flash usb mdns esp_ringbuf esp_timer esp_wifi driver) + PRIV_REQUIRES + nvs_flash + usb + esp_ringbuf + esp_psram # Required for CONFIG_SPIRAM + esp_timer + esp_wifi + esp_driver_gpio + ) diff --git a/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild b/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild index 33c2002c078..ae1312d0584 100644 --- a/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild +++ b/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild @@ -30,15 +30,15 @@ menu "Example Configuration" endchoice - menu "UVC Protocol parameters" - depends on EXAMPLE_UVC_PROTOCOL_MODE_CUSTOM - - config EXAMPLE_NEGOTIATION_ATTEMPTS - int "Attempts" + config EXAMPLE_NEGOTIATION_ATTEMPTS + int "Negotiation attempts" default 3 help Number of attempts to negotiate custom protocol parameters. + menu "UVC Protocol parameters" + depends on EXAMPLE_UVC_PROTOCOL_MODE_CUSTOM + config EXAMPLE_WIDTH_PARAM int "Width resolution in pixels" default 320 diff --git a/examples/peripherals/usb/host/uvc/main/idf_component.yml b/examples/peripherals/usb/host/uvc/main/idf_component.yml index 09a14cfce76..7165e510cd4 100644 --- a/examples/peripherals/usb/host/uvc/main/idf_component.yml +++ b/examples/peripherals/usb/host/uvc/main/idf_component.yml @@ -1,9 +1,7 @@ ## IDF Component Manager Manifest File dependencies: - idf: ">=4.4" - usb_host_uvc: "1.0.0" - mdns: - rules: - - if: "idf_version >= 5.0" + idf: ">=5.0" + usb_host_uvc: "^1.0.0" + mdns: "^1.2.0" protocol_examples_common: path: ${IDF_PATH}/examples/common_components/protocol_examples_common diff --git a/examples/peripherals/usb/host/uvc/main/main.c b/examples/peripherals/usb/host/uvc/main/main.c index 9ed07612916..cc996727c59 100644 --- a/examples/peripherals/usb/host/uvc/main/main.c +++ b/examples/peripherals/usb/host/uvc/main/main.c @@ -170,34 +170,36 @@ static uvc_error_t uvc_negotiate_stream_profile(uvc_device_handle_t *devh, uvc_stream_ctrl_t *ctrl) { uvc_error_t res; + int attempt = CONFIG_EXAMPLE_NEGOTIATION_ATTEMPTS; #if (CONFIG_EXAMPLE_UVC_PROTOCOL_MODE_AUTO) for (int idx = 0; idx < EXAMPLE_UVC_PROTOCOL_AUTO_COUNT; idx++) { - ESP_LOGI(TAG, "Negotiate streaming profile %s ...", uvc_stream_profiles[idx].name); - res = uvc_get_stream_ctrl_format_size(devh, - ctrl, - uvc_stream_profiles[idx].format, - uvc_stream_profiles[idx].width, - uvc_stream_profiles[idx].height, - uvc_stream_profiles[idx].fps); - + do { + /* + The uvc_get_stream_ctrl_format_size() function will attempt to set the desired format size. + On first attempt, some cameras would reject the format, even if they support it. + So we ask 3x by default. The second attempt is usually successful. + */ + ESP_LOGI(TAG, "Negotiate streaming profile %s ...", uvc_stream_profiles[idx].name); + res = uvc_get_stream_ctrl_format_size(devh, + ctrl, + uvc_stream_profiles[idx].format, + uvc_stream_profiles[idx].width, + uvc_stream_profiles[idx].height, + uvc_stream_profiles[idx].fps); + } while (--attempt && !(UVC_SUCCESS == res)); if (UVC_SUCCESS == res) { - break; // stream profile negotiated + break; } - sleep(1); - ESP_LOGE(TAG, "Negotiation failed with error %d.", res); } #endif // CONFIG_EXAMPLE_UVC_PROTOCOL_MODE_AUTO #if (CONFIG_EXAMPLE_UVC_PROTOCOL_MODE_CUSTOM) - int attempt = CONFIG_EXAMPLE_NEGOTIATION_ATTEMPTS; while (attempt--) { ESP_LOGI(TAG, "Negotiate streaming profile %dx%d, %d fps ...", WIDTH, HEIGHT, FPS); res = uvc_get_stream_ctrl_format_size(devh, ctrl, FORMAT, WIDTH, HEIGHT, FPS); if (UVC_SUCCESS == res) { break; } - sleep(1); - ESP_LOGE(TAG, "Negotiation failed. Try again (%d) ...", attempt); } #endif // CONFIG_EXAMPLE_UVC_PROTOCOL_MODE_CUSTOM diff --git a/examples/peripherals/usb/host/uvc/sdkconfig.defaults b/examples/peripherals/usb/host/uvc/sdkconfig.defaults index dc1dcc1c7cf..5d25a8f16c8 100644 --- a/examples/peripherals/usb/host/uvc/sdkconfig.defaults +++ b/examples/peripherals/usb/host/uvc/sdkconfig.defaults @@ -4,11 +4,17 @@ CONFIG_SPIRAM=y CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=150000 CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y +CONFIG_SPIRAM_SPEED_80M=y + +# +# SYSTEM +# +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y # # USB # -CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=1024 +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=3000 CONFIG_USB_HOST_HW_BUFFER_BIAS_IN=y # diff --git a/examples/bluetooth/esp_ble_mesh/coex_test/CMakeLists.txt b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/CMakeLists.txt similarity index 87% rename from examples/bluetooth/esp_ble_mesh/coex_test/CMakeLists.txt rename to examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/CMakeLists.txt index 5ba2c074ec4..3b5cf5be013 100644 --- a/examples/bluetooth/esp_ble_mesh/coex_test/CMakeLists.txt +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/CMakeLists.txt @@ -2,6 +2,5 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) - include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(coex_test) +project(usb_serial_jtag_echo) diff --git a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md new file mode 100644 index 00000000000..1b053da468f --- /dev/null +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md @@ -0,0 +1,60 @@ +| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | + +# USB SERIAL JTAG Echo Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example demonstrates how to utilize USB_SERIAL_JTAG interfaces by echoing back to the sender any data received on USB_SERIAL_JTAG. + +## How to use example + +### Hardware Required + +The example can be run on development board that supports usb_serial_jtag, that is based on the Espressif SoC. The board shall be connected to a computer with a single USB cable for flashing and monitoring with UART port. The usb_serial_jtag port on board can be be connected to computer with another USB cable to get the echo. + +### Configure the project + +Use the command below to configure project using Kconfig menu as showed in the table above. +The default Kconfig values can be changed such as disable the `ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG` +``` +idf.py menuconfig +``` + +### Build and Flash + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +Type some characters in the terminal connected to the external serial interface. As result you should see echo in the same terminal which you used for typing the characters. + +For example, If I type `hi espressif`, `See you again!`, `Echo a very long buffer. Assume this buffer is very large and you can see whole buffer` + +And you can get the log with: + +``` +I (296) main_task: Started on CPU0 +I (296) main_task: Calling app_main() +I (296) main_task: Returned from app_main() +I (13346) Recv str: : 0x408117b8 68 69 20 65 73 70 72 65 73 73 69 66 0d 0a |hi espressif..| +I (16606) Recv str: : 0x408117b8 53 65 65 20 79 6f 75 20 61 67 61 69 6e 21 0d 0a |See you again!..| +I (18726) Recv str: : 0x408117b8 45 63 68 6f 20 61 20 76 65 72 79 20 6c 6f 6e 67 |Echo a very long| +I (18726) Recv str: : 0x408117c8 20 62 75 66 66 65 72 2e 20 41 73 73 75 6d 65 20 | buffer. Assume | +I (18726) Recv str: : 0x408117d8 74 68 69 73 20 62 75 66 66 65 72 20 69 73 20 76 |this buffer is v| +I (18736) Recv str: : 0x408117e8 65 72 79 20 6c 61 72 67 65 20 61 6e 64 20 79 6f |ery large and yo| +I (18746) Recv str: : 0x408117b8 75 20 63 61 6e 20 73 65 65 20 77 68 6f 6c 65 20 |u can see whole | +I (18756) Recv str: : 0x408117c8 62 75 66 66 65 72 0d 0a |buffer..| +``` + +## Troubleshooting + +Note that you are not supposed to see the echo in the terminal if usb_serial_jtag port is used for flashing and monitoring. diff --git a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/main/CMakeLists.txt b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/main/CMakeLists.txt new file mode 100644 index 00000000000..5134a910802 --- /dev/null +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "usb_serial_echo_main.c" + INCLUDE_DIRS ".") diff --git a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/main/usb_serial_echo_main.c b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/main/usb_serial_echo_main.c new file mode 100644 index 00000000000..8a774408438 --- /dev/null +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/main/usb_serial_echo_main.c @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/usb_serial_jtag.h" +#include "sdkconfig.h" +#include "esp_log.h" +#include "esp_check.h" + +#define BUF_SIZE (1024) +#define ECHO_TASK_STACK_SIZE (2048) + +static void echo_task(void *arg) +{ + // Configure USB SERIAL JTAG + usb_serial_jtag_driver_config_t usb_serial_jtag_config = { + .rx_buffer_size = BUF_SIZE, + .tx_buffer_size = BUF_SIZE, + }; + + ESP_ERROR_CHECK(usb_serial_jtag_driver_install(&usb_serial_jtag_config)); + ESP_LOGI("usb_serial_jtag echo", "USB_SERIAL_JTAG init done"); + + // Configure a temporary buffer for the incoming data + uint8_t *data = (uint8_t *) malloc(BUF_SIZE); + if (data == NULL) { + ESP_LOGE("usb_serial_jtag echo", "no memory for data"); + return; + } + + while (1) { + + int len = usb_serial_jtag_read_bytes(data, (BUF_SIZE - 1), 20 / portTICK_PERIOD_MS); + + // Write data back to the USB SERIAL JTAG + if (len) { + usb_serial_jtag_write_bytes((const char *) data, len, 20 / portTICK_PERIOD_MS); + data[len] = '\0'; + ESP_LOG_BUFFER_HEXDUMP("Recv str: ", data, len, ESP_LOG_INFO); + } + } +} + +void app_main(void) +{ + xTaskCreate(echo_task, "USB SERIAL JTAG_echo_task", ECHO_TASK_STACK_SIZE, NULL, 10, NULL); +} diff --git a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/pytest_usj_echo_example.py b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/pytest_usj_echo_example.py new file mode 100644 index 00000000000..5ffc6746148 --- /dev/null +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/pytest_usj_echo_example.py @@ -0,0 +1,49 @@ +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +from time import sleep + +import pytest +import serial +import serial.tools.list_ports +from pytest_embedded import Dut + + +@pytest.mark.esp32c6 # usb_serial_jtag is very similar, test C6 is enough. +@pytest.mark.usj_device +def test_usb_device_serial_example(dut: Dut) -> None: + dut.expect_exact('USB_SERIAL_JTAG init done') + sleep(2) + + ports = list(serial.tools.list_ports.comports()) + for p in ports: + if (p.device == '/dev/ttyACM0'): # Get the usb_serial_jtag port + with serial.Serial(p.device) as s: + s.write(b'hi, espressif\n') + sleep(1) + dut.expect_exact('hi, espressif') + res = s.readline() + assert b'hi, espressif' in res + s.write(b'See you again!\n') + sleep(1) + dut.expect_exact('See you again!') + res = s.readline() + assert b'See you again!' in res + s.write(b'Echo a very long buffer. Assume this buffer is very large and you can see whole buffer\n') + sleep(1) + dut.expect_exact('Echo a very long') # 16 bytes a line because we use `ESP_LOG_BUFFER_HEXDUMP` in code. + dut.expect_exact(' buffer. Assume ') + dut.expect_exact('this buffer is v') + dut.expect_exact('ery large and yo') + dut.expect_exact('u can see whole ') + dut.expect_exact('buffer') + res = s.readline() + assert b'Echo a very long buffer. Assume this buffer is very large and you can see whole buffer' in res + s.write(b'64 bytes buffer:-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-\n') + sleep(1) + res = s.readline() + assert b'64 bytes buffer:-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-' in res + + return + + raise Exception('usb_serial_jtag port not found') diff --git a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/sdkconfig.defaults b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/sdkconfig.defaults new file mode 100644 index 00000000000..44bd84822e5 --- /dev/null +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/sdkconfig.defaults @@ -0,0 +1 @@ +CONFIG_ESP_CONSOLE_SECONDARY_NONE=y diff --git a/examples/protocols/esp_http_client/main/esp_http_client_example.c b/examples/protocols/esp_http_client/main/esp_http_client_example.c index 870f859c650..b0bafef2e04 100644 --- a/examples/protocols/esp_http_client/main/esp_http_client_example.c +++ b/examples/protocols/esp_http_client/main/esp_http_client_example.c @@ -375,7 +375,7 @@ static void http_auth_basic_redirect(void) #endif #if CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH -static void http_auth_digest(void) +static void http_auth_digest_md5(void) { esp_http_client_config_t config = { .url = "http://user:passwd@"CONFIG_EXAMPLE_HTTP_ENDPOINT"/digest-auth/auth/user/passwd/MD5/never", @@ -385,11 +385,31 @@ static void http_auth_digest(void) esp_err_t err = esp_http_client_perform(client); if (err == ESP_OK) { - ESP_LOGI(TAG, "HTTP Digest Auth Status = %d, content_length = %"PRId64, + ESP_LOGI(TAG, "HTTP MD5 Digest Auth Status = %d, content_length = %"PRId64, esp_http_client_get_status_code(client), esp_http_client_get_content_length(client)); } else { - ESP_LOGE(TAG, "Error perform http request %s", esp_err_to_name(err)); + ESP_LOGE(TAG, "Error performing http request %s", esp_err_to_name(err)); + } + esp_http_client_cleanup(client); +} + +static void http_auth_digest_sha256(void) +{ + esp_http_client_config_t config = { + .url = "http://user:passwd@"CONFIG_EXAMPLE_HTTP_ENDPOINT"/digest-auth/auth/user/passwd/SHA-256/never", + .event_handler = _http_event_handler, + .buffer_size_tx = 1024, // Increase buffer size as header size will increase as it contains SHA-256. + }; + esp_http_client_handle_t client = esp_http_client_init(&config); + esp_err_t err = esp_http_client_perform(client); + + if (err == ESP_OK) { + ESP_LOGI(TAG, "HTTP SHA256 Digest Auth Status = %d, content_length = %"PRId64, + esp_http_client_get_status_code(client), + esp_http_client_get_content_length(client)); + } else { + ESP_LOGE(TAG, "Error performing http request %s", esp_err_to_name(err)); } esp_http_client_cleanup(client); } @@ -779,7 +799,8 @@ static void http_test_task(void *pvParameters) http_auth_basic_redirect(); #endif #if CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH - http_auth_digest(); + http_auth_digest_md5(); + http_auth_digest_sha256(); #endif http_encoded_query(); http_relative_redirect(); diff --git a/examples/protocols/esp_http_client/pytest_esp_http_client.py b/examples/protocols/esp_http_client/pytest_esp_http_client.py index 716524c920e..853d7f8a4ed 100644 --- a/examples/protocols/esp_http_client/pytest_esp_http_client.py +++ b/examples/protocols/esp_http_client/pytest_esp_http_client.py @@ -34,7 +34,8 @@ def test_examples_protocol_esp_http_client(dut: Dut) -> None: dut.expect(r'HTTP HEAD Status = 200, content_length = (\d)') dut.expect(r'HTTP Basic Auth Status = 200, content_length = (\d)') dut.expect(r'HTTP Basic Auth redirect Status = 200, content_length = (\d)') - dut.expect(r'HTTP Digest Auth Status = 200, content_length = (\d)') + dut.expect(r'HTTP MD5 Digest Auth Status = 200, content_length = (\d)') + dut.expect(r'HTTP SHA256 Digest Auth Status = 200, content_length = (\d)') dut.expect(r'HTTP Relative path redirect Status = 200, content_length = (\d)') dut.expect(r'HTTP Absolute path redirect Status = 200, content_length = (\d)') dut.expect(r'HTTP Absolute path redirect \(manual\) Status = 200, content_length = (\d)') diff --git a/examples/protocols/esp_local_ctrl/main/Kconfig.projbuild b/examples/protocols/esp_local_ctrl/main/Kconfig.projbuild index 0e6d06c3b18..661ac8fa7b0 100644 --- a/examples/protocols/esp_local_ctrl/main/Kconfig.projbuild +++ b/examples/protocols/esp_local_ctrl/main/Kconfig.projbuild @@ -1,5 +1,22 @@ menu "Example Configuration" + choice EXAMPLE_LOCAL_CTRL_TRANSPORT + bool "Local Control Transport" + default EXAMPLE_LOCAL_CTRL_TRANSPORT_BLE if !SOC_WIFI_SUPPORTED + default EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP + help + Local Control component offers both, SoftAP and BLE transports. Choose any one. + + config EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP + bool "Soft AP" + select LWIP_IPV4 + depends on SOC_WIFI_SUPPORTED + + config EXAMPLE_LOCAL_CTRL_TRANSPORT_BLE + bool "BLE" + select BT_ENABLED + endchoice + choice EXAMPLE_PROTOCOMM_SECURITY_VERSION bool "Protocomm security version" default EXAMPLE_PROTOCOMM_SECURITY_VERSION_2 @@ -41,4 +58,13 @@ menu "Example Configuration" security version 2. endchoice + config EXAMPLE_LOCAL_CTRL_USING_BLUEDROID + bool + depends on (BT_BLUEDROID_ENABLED && !IDF_TARGET_ESP32) + select BT_BLE_42_FEATURES_SUPPORTED + default y + help + This enables BLE 4.2 features for Bluedroid which are required for + the API definitions that are present in the esp_gap_ble_api header. + endmenu diff --git a/examples/protocols/esp_local_ctrl/main/app_main.c b/examples/protocols/esp_local_ctrl/main/app_main.c index 1fd98fd219a..ee2a2ff224e 100644 --- a/examples/protocols/esp_local_ctrl/main/app_main.c +++ b/examples/protocols/esp_local_ctrl/main/app_main.c @@ -38,12 +38,17 @@ void app_main(void) ret = nvs_flash_init(); } ESP_ERROR_CHECK(ret); + +#ifdef CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP ESP_ERROR_CHECK(esp_netif_init()); ESP_ERROR_CHECK(esp_event_loop_create_default()); - if (example_connect() == ESP_OK) { - start_esp_local_ctrl_service(); - } else { + if (example_connect() != ESP_OK) { ESP_LOGI(TAG, "Connection failed, not starting esp_local_ctrl service"); + vTaskDelay(portMAX_DELAY); } +#endif /* CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP */ + + start_esp_local_ctrl_service(); + ESP_LOGI(TAG, "esp_local_ctrl service started"); } diff --git a/examples/protocols/esp_local_ctrl/main/esp_local_ctrl_service.c b/examples/protocols/esp_local_ctrl/main/esp_local_ctrl_service.c index 6b38202effb..595952d06ae 100644 --- a/examples/protocols/esp_local_ctrl/main/esp_local_ctrl_service.c +++ b/examples/protocols/esp_local_ctrl/main/esp_local_ctrl_service.c @@ -20,6 +20,7 @@ #include #include #include +#include static const char *TAG = "control"; @@ -224,6 +225,7 @@ static void free_str(void *arg) /* Function used by app_main to start the esp_local_ctrl service */ void start_esp_local_ctrl_service(void) { +#ifdef CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP #ifdef CONFIG_ESP_HTTPS_SERVER_ENABLE /* Set the configuration */ httpd_ssl_config_t https_conf = HTTPD_SSL_CONFIG_DEFAULT(); @@ -242,6 +244,26 @@ void start_esp_local_ctrl_service(void) #else httpd_config_t http_conf = HTTPD_DEFAULT_CONFIG(); #endif +#else /* CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_BLE */ + protocomm_ble_config_t *ble_conf = & (protocomm_ble_config_t) { + .device_name = SERVICE_NAME, + /* Set a random 128 bit UUID which will be included in the BLE advertisement + * and will correspond to the primary GATT service that provides provisioning + * endpoints as GATT characteristics. Each GATT characteristic will be + * formed using the primary service UUID as base, with different auto assigned + * 12th and 13th bytes (assume counting starts from 0th byte). The client side + * applications must identify the endpoints by reading the User Characteristic + * Description descriptor (0x2901) for each characteristic, which contains the + * endpoint name of the characteristic */ + .service_uuid = { + /* LSB <--------------------------------------- + * ---------------------------------------> MSB */ + 0x21, 0xd5, 0x3b, 0x8d, 0xbd, 0x75, 0x68, 0x8a, + 0xb4, 0x42, 0xeb, 0x31, 0x4a, 0x1e, 0x98, 0x3d, + } + }; +#endif /* CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP */ + #ifdef CONFIG_EXAMPLE_PROTOCOMM_SECURITY_VERSION_1 /* What is the security level that we want (0, 1, 2): * - PROTOCOMM_SECURITY_0 is simply plain text communication. @@ -284,6 +306,7 @@ void start_esp_local_ctrl_service(void) #endif esp_local_ctrl_config_t config = { +#ifdef CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP .transport = ESP_LOCAL_CTRL_TRANSPORT_HTTPD, .transport_config = { #ifdef CONFIG_ESP_HTTPS_SERVER_ENABLE @@ -292,6 +315,12 @@ void start_esp_local_ctrl_service(void) .httpd = &http_conf, #endif }, +#else /* CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_BLE */ + .transport = ESP_LOCAL_CTRL_TRANSPORT_BLE, + .transport_config = { + .ble = ble_conf, + }, +#endif /* CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP */ .proto_sec = { .version = security, .custom_handle = NULL, @@ -308,8 +337,10 @@ void start_esp_local_ctrl_service(void) .max_properties = 10 }; +#ifdef CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_SOFTAP mdns_init(); mdns_hostname_set(SERVICE_NAME); +#endif /* Start esp_local_ctrl service */ ESP_ERROR_CHECK(esp_local_ctrl_start(&config)); diff --git a/examples/protocols/esp_local_ctrl/scripts/esp_local_ctrl.py b/examples/protocols/esp_local_ctrl/scripts/esp_local_ctrl.py index dbbd6297249..597a977634a 100644 --- a/examples/protocols/esp_local_ctrl/scripts/esp_local_ctrl.py +++ b/examples/protocols/esp_local_ctrl/scripts/esp_local_ctrl.py @@ -136,7 +136,7 @@ async def get_transport(sel_transport, service_name, check_hostname): tp = esp_prov.transport.Transport_HTTP(service_name, ssl_ctx) elif (sel_transport == 'ble'): tp = esp_prov.transport.Transport_BLE( - devname=service_name, service_uuid='0000ffff-0000-1000-8000-00805f9b34fb', + service_uuid='3d981e4a-31eb-42b4-8a68-75bd8d3bd521', nu_lookup={'esp_local_ctrl/version': '0001', 'esp_local_ctrl/session': '0002', 'esp_local_ctrl/control': '0003'} diff --git a/examples/protocols/esp_local_ctrl/scripts/proto_lc.py b/examples/protocols/esp_local_ctrl/scripts/proto_lc.py index a42e1ad0359..5186372e762 100644 --- a/examples/protocols/esp_local_ctrl/scripts/proto_lc.py +++ b/examples/protocols/esp_local_ctrl/scripts/proto_lc.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # @@ -36,7 +36,7 @@ def get_prop_count_request(security_ctx): payload = local_ctrl_pb2.CmdGetPropertyCount() req.cmd_get_prop_count.MergeFrom(payload) enc_cmd = security_ctx.encrypt_data(req.SerializeToString()) - return enc_cmd + return enc_cmd.decode('latin-1') def get_prop_count_response(security_ctx, response_data): @@ -56,7 +56,7 @@ def get_prop_vals_request(security_ctx, indices): payload.indices.extend(indices) req.cmd_get_prop_vals.MergeFrom(payload) enc_cmd = security_ctx.encrypt_data(req.SerializeToString()) - return enc_cmd + return enc_cmd.decode('latin-1') def get_prop_vals_response(security_ctx, response_data): @@ -85,7 +85,7 @@ def set_prop_vals_request(security_ctx, indices, values): prop.value = v req.cmd_set_prop_vals.MergeFrom(payload) enc_cmd = security_ctx.encrypt_data(req.SerializeToString()) - return enc_cmd + return enc_cmd.decode('latin-1') def set_prop_vals_response(security_ctx, response_data): diff --git a/examples/protocols/esp_local_ctrl/sdkconfig.defaults.esp32h2 b/examples/protocols/esp_local_ctrl/sdkconfig.defaults.esp32h2 new file mode 100644 index 00000000000..1a95b7094c3 --- /dev/null +++ b/examples/protocols/esp_local_ctrl/sdkconfig.defaults.esp32h2 @@ -0,0 +1,5 @@ +# Override some defaults so BT stack is enabled and +CONFIG_BT_ENABLED=y +CONFIG_BT_NIMBLE_ENABLED=y + +CONFIG_EXAMPLE_LOCAL_CTRL_TRANSPORT_BLE=y diff --git a/examples/security/.build-test-rules.yml b/examples/security/.build-test-rules.yml index 084469e45fb..e24e4496914 100644 --- a/examples/security/.build-test-rules.yml +++ b/examples/security/.build-test-rules.yml @@ -2,7 +2,7 @@ examples/security/flash_encryption: disable_test: - - if: IDF_TARGET in ["esp32s2", "esp32s3", "esp32c6", "esp32h2", "esp32c2"] + - if: IDF_TARGET in ["esp32s2", "esp32s3", "esp32c6", "esp32h2", "esp32c2", "esp32p4"] temporary: true reason: lack of runners diff --git a/examples/security/flash_encryption/sdkconfig.defaults b/examples/security/flash_encryption/sdkconfig.defaults index 3300ebfb1a0..1aa06bec6c1 100644 --- a/examples/security/flash_encryption/sdkconfig.defaults +++ b/examples/security/flash_encryption/sdkconfig.defaults @@ -2,4 +2,4 @@ CONFIG_PARTITION_TABLE_CUSTOM=y CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv" CONFIG_PARTITION_TABLE_FILENAME="partitions_example.csv" -CONFIG_PARTITION_TABLE_OFFSET=0x9000 +CONFIG_PARTITION_TABLE_OFFSET=0xD000 diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index 7840ae2ad70..985ea2f47fa 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -10,10 +10,11 @@ examples/storage/custom_flash_driver: examples/storage/emmc: depends_components: - - sdmmc - - driver - fatfs - vfs + - sdmmc + - esp_driver_sdmmc + - esp_driver_sdspi enable: - if: IDF_TARGET == "esp32s3" reason: only support on esp32s3 @@ -107,7 +108,7 @@ examples/storage/perf_benchmark: - spiffs - wear_levelling - esp_partition - - driver + - esp_driver_sdmmc disable: - if: IDF_TARGET == "esp32p4" and CONFIG_NAME in ["sdmmc_1line", "sdmmc_4line", "sdspi_1line"] temporary: true @@ -121,7 +122,7 @@ examples/storage/sd_card/sdmmc: depends_components: - vfs - sdmmc - - driver + - esp_driver_sdmmc disable: - if: SOC_SDMMC_HOST_SUPPORTED != 1 disable_test: @@ -133,7 +134,7 @@ examples/storage/sd_card/sdspi: depends_components: - vfs - sdmmc - - driver + - esp_driver_sdspi disable: - if: SOC_GPSPI_SUPPORTED != 1 disable_test: diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 812425a15b7..4e89f045e8a 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -24,7 +24,7 @@ examples/system/console/advanced: examples/system/console/advanced_usb_cdc: disable: - - if: SOC_USB_PERIPH_NUM == 0 + - if: SOC_USB_OTG_SUPPORTED != 1 depends_components: - console - vfs @@ -54,8 +54,8 @@ examples/system/deep_sleep_wake_stub: reason: target(s) is not supported yet examples/system/efuse: - enable: - - if: IDF_TARGET == "esp32" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - efuse @@ -74,11 +74,9 @@ examples/system/esp_timer: - esp_timer examples/system/eventfd: - enable: - - if: IDF_TARGET == "esp32" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") - reason: no target specific functionality, testing on a single target is sufficient disable: - - if: SOC_GPTIMER_SUPPORTED != 1 + - if: SOC_GPTIMER_SUPPORTED != 1 and (IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux")) + reason: no target specific functionality, testing on a single target is sufficient depends_components: - vfs - esp_driver_gptimer @@ -90,8 +88,8 @@ examples/system/flash_suspend: reason: the other targets are not tested yet examples/system/freertos: - enable: - - if: IDF_TARGET == "esp32" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - freertos @@ -109,8 +107,8 @@ examples/system/gdbstub: reason: not supported yet #TODO: IDF-7510 examples/system/heap_task_tracking: - enable: - - if: IDF_TARGET == "esp32c3" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32c3" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - heap @@ -201,15 +199,15 @@ examples/system/perfmon: - perfmon examples/system/pthread: - enable: - - if: IDF_TARGET == "esp32" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - pthread examples/system/select: - enable: - - if: IDF_TARGET == "esp32c3" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32c3" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - vfs @@ -237,8 +235,8 @@ examples/system/sysview_tracing_heap_log: reason: lack of runners examples/system/task_watchdog: - enable: - - if: IDF_TARGET == "esp32" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - esp_system @@ -246,24 +244,38 @@ examples/system/task_watchdog: examples/system/ulp/lp_core/gpio: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: target esp32p4 is not supported yet, TODO IDF-7536 depends_components: - ulp examples/system/ulp/lp_core/lp_i2c: enable: - if: SOC_LP_I2C_SUPPORTED == 1 + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: target esp32p4 is not supported yet, TODO IDF-7540 depends_components: - ulp examples/system/ulp/lp_core/lp_uart/lp_uart_echo: disable: - if: SOC_ULP_LP_UART_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: target esp32p4 is not supported yet TODO IDF-7533 depends_components: - ulp examples/system/ulp/lp_core/lp_uart/lp_uart_print: disable: - if: SOC_ULP_LP_UART_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: target esp32p4 is not supported yet TODO IDF-7533 depends_components: - ulp @@ -326,8 +338,8 @@ examples/system/ulp/ulp_riscv/uart_print: - ulp examples/system/unit_test/: - enable: - - if: IDF_TARGET == "esp32" or (NIGHTLY_RUN == "1" and IDF_TARGET != "linux") + disable: + - if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient depends_components: - unity diff --git a/examples/system/app_trace_basic/pytest_app_trace_basic.py b/examples/system/app_trace_basic/pytest_app_trace_basic.py index 9027eb41819..2d7d18241a4 100644 --- a/examples/system/app_trace_basic/pytest_app_trace_basic.py +++ b/examples/system/app_trace_basic/pytest_app_trace_basic.py @@ -47,7 +47,7 @@ def test_examples_app_trace_basic(dut: IdfDut, openocd: OpenOcd) -> None: apptrace_wait_stop(dut.openocd) with open(openocd._logfile) as oocd_log: # pylint: disable=protected-access - cores = 1 if dut.app.sdkconfig.get('FREERTOS_UNICORE') is True else 2 + cores = 1 if dut.app.sdkconfig.get('ESP_SYSTEM_SINGLE_CORE_MODE') is True else 2 params_str = 'App trace params: from {} cores,'.format(cores) found = False for line in oocd_log: diff --git a/examples/system/console/advanced/components/cmd_system/cmd_system_sleep.c b/examples/system/console/advanced/components/cmd_system/cmd_system_sleep.c index e656e5207ef..0dd3ef9a186 100644 --- a/examples/system/console/advanced/components/cmd_system/cmd_system_sleep.c +++ b/examples/system/console/advanced/components/cmd_system/cmd_system_sleep.c @@ -82,7 +82,7 @@ static int deep_sleep(int argc, char **argv) ESP_LOGI(TAG, "Enabling wakeup on GPIO%d, wakeup on %s level", io_num, level ? "HIGH" : "LOW"); - ESP_ERROR_CHECK( esp_sleep_enable_ext1_wakeup(1ULL << io_num, level) ); + ESP_ERROR_CHECK( esp_sleep_enable_ext1_wakeup_io(1ULL << io_num, level) ); ESP_LOGE(TAG, "GPIO wakeup from deep sleep currently unsupported on ESP32-C3"); } #endif // SOC_PM_SUPPORT_EXT1_WAKEUP diff --git a/examples/system/console/advanced/main/console_example_main.c b/examples/system/console/advanced/main/console_example_main.c index dba157f544b..3151803fd9c 100644 --- a/examples/system/console/advanced/main/console_example_main.c +++ b/examples/system/console/advanced/main/console_example_main.c @@ -9,10 +9,11 @@ #include #include +#include #include "esp_system.h" #include "esp_log.h" #include "esp_console.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" #include "linenoise/linenoise.h" #include "argtable3/argtable3.h" @@ -90,9 +91,9 @@ static void initialize_console(void) setvbuf(stdin, NULL, _IONBF, 0); /* Minicom, screen, idf_monitor send CR when ENTER key is pressed */ - esp_vfs_dev_uart_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); + uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); /* Move the caret to the beginning of the next line on '\n' */ - esp_vfs_dev_uart_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); /* Configure UART. Note that REF_TICK is used so that the baud rate remains * correct while APB frequency is changing in light sleep mode. @@ -114,7 +115,7 @@ static void initialize_console(void) ESP_ERROR_CHECK( uart_param_config(CONFIG_ESP_CONSOLE_UART_NUM, &uart_config) ); /* Tell VFS to use UART driver */ - esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); + uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); /* Initialize the console */ esp_console_config_t console_config = { diff --git a/examples/system/deep_sleep/README.md b/examples/system/deep_sleep/README.md index 45cc87ad920..d88548380d7 100644 --- a/examples/system/deep_sleep/README.md +++ b/examples/system/deep_sleep/README.md @@ -11,8 +11,8 @@ The following wake up sources are demonstrated in this example (refer to the [Wa - **Timer:** An RTC timer that can be programmed to trigger a wake up after a preset time. This example will trigger a wake up every 20 seconds. - **EXT0:** External wake up 0 can trigger wakeup when one predefined RTC GPIO is at a predefined logic level. This example uses GPIO25 in ESP32 or GPIO3 in ESP32-S2/S3 to trigger a wake up when the pin is HIGH. (This wake up source is only available on ESP32, ESP32-S2, and ESP32-S3.) -- **EXT1:** External wake up 1 which is tied to multiple RTC GPIOs. This example uses GPIO2 and GPIO4 to trigger a wake up with any one of the two pins are HIGH. (This wake up source is available on ESP32, ESP32-S2, ESP32-S3 and ESP32-C6.) -- **GPIO:** Pads powered by VDD3P3_RTC can be used to trigger a wake up from deep sleep. You may choose the pin and trigger level in menuconfig. (This wake up source is unavailable on ESP32, ESP32-S2, and ESP32-S3.) +- **EXT1:** External wake up 1 which is tied to multiple RTC GPIOs. This example uses GPIO2 and GPIO4 to trigger a wake up with any one of the two pins are HIGH. (This wake up source is available on ESP32, ESP32-S2, ESP32-S3, ESP32-C6 and ESP32-H2.) +- **GPIO:** Pads powered by VDD3P3_RTC can be used to trigger a wake up from deep sleep. You may choose the pin and trigger level in menuconfig. (This wake up source is unavailable on ESP32, ESP32-S2, ESP32-S3 and ESP32-H2.) - **Touch:** Touch pad sensor interrupt. This example uses touch pads connected to GPIO32, GPIO33 in ESP32 or GPIO9 in ESP32-S2/S3 to trigger a wake up when any of the pads are pressed. - **ULP:** Ultra Low Power Coprocessor which can continue to run during deep sleep. This example utilizes the ULP and constantly sample the chip's temperature and trigger a wake up if the chips temperature exceeds ~5 degrees Celsius. diff --git a/examples/system/deep_sleep/main/ext_wakeup.c b/examples/system/deep_sleep/main/ext_wakeup.c index de329b69735..35dcaf4b942 100644 --- a/examples/system/deep_sleep/main/ext_wakeup.c +++ b/examples/system/deep_sleep/main/ext_wakeup.c @@ -40,12 +40,10 @@ void example_deep_sleep_register_ext1_wakeup(void) printf("Enabling EXT1 wakeup on pins GPIO%d, GPIO%d\n", ext_wakeup_pin_1, ext_wakeup_pin_2); #if SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN - const uint64_t ext_wakeup_mode = CONFIG_EXAMPLE_EXT1_WAKEUP_MODE_PIN_1 << ext_wakeup_pin_1 | \ - CONFIG_EXAMPLE_EXT1_WAKEUP_MODE_PIN_2 << ext_wakeup_pin_2; - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_with_level_mask(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ext_wakeup_mode)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(ext_wakeup_pin_1_mask, CONFIG_EXAMPLE_EXT1_WAKEUP_MODE_PIN_1)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(ext_wakeup_pin_2_mask, CONFIG_EXAMPLE_EXT1_WAKEUP_MODE_PIN_2)); #else - const esp_sleep_ext1_wakeup_mode_t ext_wakeup_mode = CONFIG_EXAMPLE_EXT1_WAKEUP_MODE; - ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ext_wakeup_mode)); + ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, CONFIG_EXAMPLE_EXT1_WAKEUP_MODE)); #endif /* If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO diff --git a/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32p4 b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32p4 new file mode 100644 index 00000000000..8df40e73f4d --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32p4 @@ -0,0 +1,18 @@ +# FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32p4" + +CONFIG_PARTITION_TABLE_OFFSET=0xD000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem" +CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE=y + +CONFIG_SECURE_FLASH_ENC_ENABLED=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/ota/advanced_https_ota/main/ble_helper/bluedroid_gatts.c b/examples/system/ota/advanced_https_ota/main/ble_helper/bluedroid_gatts.c index ac4bdfa91cf..22e64be4d87 100644 --- a/examples/system/ota/advanced_https_ota/main/ble_helper/bluedroid_gatts.c +++ b/examples/system/ota/advanced_https_ota/main/ble_helper/bluedroid_gatts.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -99,43 +99,59 @@ void example_exec_write_event_env(prepare_type_env_t *prepare_write_env, esp_ble void example_write_event_env(esp_gatt_if_t gatts_if, prepare_type_env_t *prepare_write_env, esp_ble_gatts_cb_param_t *param) { esp_gatt_status_t status = ESP_GATT_OK; + + // Check if a response is needed if (param->write.need_rsp) { + // Check if the write operation is a prepared write if (param->write.is_prep) { - if (prepare_write_env->prepare_buf == NULL) { + // Check for invalid offset or attribute length + if (param->write.offset > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + } + // Allocate memory for the prepare buffer if not already allocated + if (status == ESP_GATT_OK && prepare_write_env->prepare_buf == NULL) { prepare_write_env->prepare_buf = (uint8_t *)malloc(PREPARE_BUF_MAX_SIZE * sizeof(uint8_t)); prepare_write_env->prepare_len = 0; + + // Check for allocation failure if (prepare_write_env->prepare_buf == NULL) { ESP_LOGE(TAG, "Gatt_server prep no mem"); status = ESP_GATT_NO_RESOURCES; } - } else { - if (param->write.offset > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_OFFSET; - } else if ((param->write.offset + param->write.len) > PREPARE_BUF_MAX_SIZE) { - status = ESP_GATT_INVALID_ATTR_LEN; - } } + // Allocate and configure the GATT response esp_gatt_rsp_t *gatt_rsp = (esp_gatt_rsp_t *)malloc(sizeof(esp_gatt_rsp_t)); - gatt_rsp->attr_value.len = param->write.len; - gatt_rsp->attr_value.handle = param->write.handle; - gatt_rsp->attr_value.offset = param->write.offset; - gatt_rsp->attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; - memcpy(gatt_rsp->attr_value.value, param->write.value, param->write.len); - esp_err_t response_err = esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, gatt_rsp); - if (response_err != ESP_OK) { - ESP_LOGE(TAG, "Send response error"); + if (gatt_rsp != NULL) { + gatt_rsp->attr_value.len = param->write.len; + gatt_rsp->attr_value.handle = param->write.handle; + gatt_rsp->attr_value.offset = param->write.offset; + gatt_rsp->attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; + memcpy(gatt_rsp->attr_value.value, param->write.value, param->write.len); + esp_err_t response_err = esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, gatt_rsp); + if (response_err != ESP_OK) { + ESP_LOGE(TAG, "Send response error"); + } + free(gatt_rsp); + } else { + ESP_LOGE(TAG, "%s, malloc failed, and no resource to send response", __func__); + status = ESP_GATT_NO_RESOURCES; } - free(gatt_rsp); + if (status != ESP_GATT_OK) { return; } + + // Update the prepare buffer with the received data memcpy(prepare_write_env->prepare_buf + param->write.offset, param->write.value, param->write.len); prepare_write_env->prepare_len += param->write.len; } else { + // Send a response for non-prepared write esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, NULL); } } diff --git a/examples/system/select/main/select_example.c b/examples/system/select/main/select_example.c index 4de3a006977..01f63599980 100644 --- a/examples/system/select/main/select_example.c +++ b/examples/system/select/main/select_example.c @@ -15,8 +15,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_log.h" -#include "esp_vfs.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" #include "esp_netif.h" #include "lwip/sockets.h" @@ -107,7 +106,7 @@ static void uart1_init(void) uart1_deinit(); } - esp_vfs_dev_uart_use_driver(1); + uart_vfs_dev_use_driver(1); } static void uart1_write_task(void *param) diff --git a/examples/wifi/.build-test-rules.yml b/examples/wifi/.build-test-rules.yml index d7aab698ee2..1a6e8bc6d67 100644 --- a/examples/wifi/.build-test-rules.yml +++ b/examples/wifi/.build-test-rules.yml @@ -65,8 +65,8 @@ examples/wifi/power_save: <<: *wifi_depends_default disable: - if: SOC_WIFI_SUPPORTED != 1 - depends_filepatterns: - - components/driver/uart/**/* + depends_components: + - esp_driver_uart examples/wifi/wifi_aware: disable: diff --git a/examples/wifi/power_save/main/get_ap_info.c b/examples/wifi/power_save/main/get_ap_info.c index 00c9558464d..233c2c2a40b 100644 --- a/examples/wifi/power_save/main/get_ap_info.c +++ b/examples/wifi/power_save/main/get_ap_info.c @@ -6,7 +6,7 @@ #include #include "sdkconfig.h" #include "esp_log.h" -#include "esp_vfs_dev.h" +#include "driver/uart_vfs.h" #include "driver/uart.h" #if CONFIG_EXAMPLE_GET_AP_INFO_FROM_STDIN @@ -23,10 +23,10 @@ void get_ap_info_from_stdin(void) 256, 0, 0, NULL, 0) ); /* Tell VFS to use UART driver */ - esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); - esp_vfs_dev_uart_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); + uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); + uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); /* Move the caret to the beginning of the next line on '\n' */ - esp_vfs_dev_uart_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); ESP_LOGI(TAG, "Input SSID:"); @@ -44,7 +44,7 @@ void get_ap_info_from_stdin(void) } /* Back to use non-blocking vfs console*/ - esp_vfs_dev_uart_use_nonblocking(CONFIG_ESP_CONSOLE_UART_NUM); + uart_vfs_dev_use_nonblocking(CONFIG_ESP_CONSOLE_UART_NUM); uart_driver_delete(CONFIG_ESP_CONSOLE_UART_NUM); } #endif diff --git a/examples/zigbee/.build-test-rules.yml b/examples/zigbee/.build-test-rules.yml index bd0f8f99ece..d733dc017fd 100644 --- a/examples/zigbee/.build-test-rules.yml +++ b/examples/zigbee/.build-test-rules.yml @@ -6,22 +6,19 @@ - examples/zigbee/light_sample/**/* examples/zigbee/esp_zigbee_gateway: - disable: - - if: IDF_TARGET in ["esp32c2", "esp32h2", "esp32p4"] - temporary: true - reason: target(s) not supported yet + enable: + - if: SOC_WIFI_SUPPORTED == 1 and IDF_TARGET != "esp32c2" + reason: not supported esp32c2 <<: *zigbee_dependencies examples/zigbee/esp_zigbee_rcp: enable: - - if: IDF_TARGET in ["esp32c6", "esp32h2"] - reason: should able to run on esp32h2 and esp32c6 + - if: SOC_IEEE802154_SUPPORTED == 1 <<: *zigbee_dependencies examples/zigbee/light_sample: enable: - - if: IDF_TARGET in ["esp32c6", "esp32h2"] - reason: should able to run on esp32h2 and esp32c6 + - if: SOC_IEEE802154_SUPPORTED == 1 disable_test: - if: IDF_TARGET == "esp32c6" temporary: true diff --git a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c index 4c034b2e058..d1731af3c07 100644 --- a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c +++ b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c @@ -46,6 +46,7 @@ #include "esp_vfs_eventfd.h" #include "esp_vfs_dev.h" #include "esp_vfs_usb_serial_jtag.h" +#include "driver/uart_vfs.h" #include "esp_wifi.h" #include "nvs_flash.h" #include "protocol_examples_common.h" @@ -77,7 +78,7 @@ esp_err_t esp_zb_gateway_console_init(void) usb_serial_jtag_driver_config_t usb_serial_jtag_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(); ret = usb_serial_jtag_driver_install(&usb_serial_jtag_config); esp_vfs_usb_serial_jtag_use_driver(); - esp_vfs_dev_uart_register(); + uart_vfs_dev_register(); return ret; } #endif diff --git a/examples/zigbee/esp_zigbee_gateway/partitions.csv b/examples/zigbee/esp_zigbee_gateway/partitions.csv index c6e1d03bfa6..b7bdb05faa3 100644 --- a/examples/zigbee/esp_zigbee_gateway/partitions.csv +++ b/examples/zigbee/esp_zigbee_gateway/partitions.csv @@ -2,6 +2,6 @@ # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, -factory, app, factory, 0x10000, 1150K, +factory, app, factory, 0x10000, 1148K, zb_storage, data, fat, , 16K, zb_fct, data, fat, , 1K, diff --git a/examples/zigbee/light_sample/HA_on_off_light/partitions.csv b/examples/zigbee/light_sample/HA_on_off_light/partitions.csv index 24bb3132a40..9bf5a13c90c 100644 --- a/examples/zigbee/light_sample/HA_on_off_light/partitions.csv +++ b/examples/zigbee/light_sample/HA_on_off_light/partitions.csv @@ -2,6 +2,6 @@ # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, -factory, app, factory, 0x10000, 650K, +factory, app, factory, 0x10000, 652K, zb_storage, data, fat, 0xb3000, 16K, zb_fct, data, fat, 0xb7000, 1K, diff --git a/examples/zigbee/light_sample/HA_on_off_switch/partitions.csv b/examples/zigbee/light_sample/HA_on_off_switch/partitions.csv index 24bb3132a40..9bf5a13c90c 100644 --- a/examples/zigbee/light_sample/HA_on_off_switch/partitions.csv +++ b/examples/zigbee/light_sample/HA_on_off_switch/partitions.csv @@ -2,6 +2,6 @@ # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, -factory, app, factory, 0x10000, 650K, +factory, app, factory, 0x10000, 652K, zb_storage, data, fat, 0xb3000, 16K, zb_fct, data, fat, 0xb7000, 1K, diff --git a/tools/ci/artifacts_handler.py b/tools/ci/artifacts_handler.py index 496e88e6b89..73930a3a050 100644 --- a/tools/ci/artifacts_handler.py +++ b/tools/ci/artifacts_handler.py @@ -22,6 +22,7 @@ class ArtifactType(str, Enum): LOGS = 'logs' SIZE_REPORTS = 'size_reports' JUNIT_REPORTS = 'junit_reports' + MODIFIED_FILES_AND_COMPONENTS_REPORT = 'modified_files_and_components_report' TYPE_PATTERNS_DICT = { @@ -52,6 +53,9 @@ class ArtifactType(str, Enum): ArtifactType.JUNIT_REPORTS: [ 'XUNIT_RESULT.xml', ], + ArtifactType.MODIFIED_FILES_AND_COMPONENTS_REPORT: [ + 'pipeline.env', + ], } diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml index 98ff84a0f64..d2866b02a7f 100644 --- a/tools/ci/astyle-rules.yml +++ b/tools/ci/astyle-rules.yml @@ -14,6 +14,7 @@ submodules: - "/components/bt/controller/lib_esp32c6/esp32c6-bt-lib/" - "/components/bt/controller/lib_esp32h2/esp32h2-bt-lib/" - "/components/bt/host/nimble/nimble/" + - "/components/bt/esp_ble_mesh/lib/lib/" - "/components/cmock/CMock/" - "/components/esp_coex/lib/" - "/components/esp_phy/lib/" @@ -108,7 +109,6 @@ components_not_formatted_temporary: - "/components/touch_element/" - "/components/ulp/" - "/components/unity/" - - "/components/usb/" - "/components/vfs/" - "/components/wear_levelling/" - "/components/wifi_provisioning/" diff --git a/tools/ci/check_build_test_rules.py b/tools/ci/check_build_test_rules.py index 080ce2ad550..f204f0702ab 100755 --- a/tools/ci/check_build_test_rules.py +++ b/tools/ci/check_build_test_rules.py @@ -31,6 +31,7 @@ 'esp32c3': 'ESP32-C3', 'esp32c2': 'ESP32-C2', 'esp32c6': 'ESP32-C6', + 'esp32c5': 'ESP32-C5', 'esp32h2': 'ESP32-H2', 'esp32p4': 'ESP32-P4', 'linux': 'Linux', @@ -43,6 +44,7 @@ 'ESP32-C3': 'esp32c3', 'ESP32-C2': 'esp32c2', 'ESP32-C6': 'esp32c6', + 'ESP32-C5': 'esp32c5', 'ESP32-H2': 'esp32h2', 'ESP32-P4': 'esp32p4', 'Linux': 'linux', diff --git a/tools/ci/check_copyright_config.yaml b/tools/ci/check_copyright_config.yaml index 2d4e49f4939..1401cfac26c 100644 --- a/tools/ci/check_copyright_config.yaml +++ b/tools/ci/check_copyright_config.yaml @@ -121,7 +121,7 @@ spiffs: sdmmc: include: - - 'components/driver/sdmmc/include/driver/' + - 'components/esp_driver_sdmmc/include/driver/' - 'components/sdmmc/' allowed_licenses: - Apache-2.0 diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 0dd14e756db..b0ef4234adb 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -412,13 +412,9 @@ components/esp_hid/include/esp_hidd_transport.h components/esp_hid/include/esp_hidh.h components/esp_hid/include/esp_hidh_bluedroid.h components/esp_hid/include/esp_hidh_gattc.h -components/esp_hid/include/esp_hidh_transport.h -components/esp_hid/private/ble_hidd.h -components/esp_hid/private/ble_hidh.h components/esp_hid/private/bt_hidd.h components/esp_hid/private/bt_hidh.h components/esp_hid/private/esp_hidd_private.h -components/esp_hid/src/esp_hid_common.c components/esp_local_ctrl/src/esp_local_ctrl_handler.c components/esp_local_ctrl/src/esp_local_ctrl_priv.h components/esp_local_ctrl/src/esp_local_ctrl_transport_ble.c @@ -502,7 +498,6 @@ components/esp_system/test_eh_frame_parser/linker.ld components/esp_system/ubsan.c components/esp_wifi/include/esp_private/esp_wifi_types_private.h components/esp_wifi/include/esp_private/wifi_types.h -components/esp_wifi/include/smartconfig_ack.h components/esp_wifi/src/mesh_event.c components/fatfs/diskio/diskio.c components/fatfs/diskio/diskio_impl.h @@ -561,7 +556,6 @@ components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/test_gen_crt_bundle.py components/mbedtls/port/aes/block/esp_aes.c components/mbedtls/port/aes/dma/esp_aes.c components/mbedtls/port/aes/dma/esp_aes_crypto_dma_impl.c -components/mbedtls/port/aes/dma/include/esp_aes_dma_priv.h components/mbedtls/port/aes/esp_aes_xts.c components/mbedtls/port/include/aes/esp_aes.h components/mbedtls/port/include/aes/esp_aes_internal.h @@ -584,8 +578,6 @@ components/mbedtls/port/sha/parallel_engine/sha.c components/nvs_flash/include/nvs_handle.hpp components/nvs_flash/src/nvs_cxx_api.cpp components/nvs_flash/src/nvs_encrypted_partition.hpp -components/nvs_flash/src/nvs_handle_locked.cpp -components/nvs_flash/src/nvs_handle_locked.hpp components/nvs_flash/src/nvs_item_hash_list.cpp components/nvs_flash/src/nvs_pagemanager.hpp components/nvs_flash/src/nvs_partition_lookup.cpp @@ -676,7 +668,6 @@ components/soc/esp32c3/include/soc/sensitive_struct.h components/soc/esp32c3/include/soc/soc_pins.h components/soc/esp32c3/include/soc/spi_mem_reg.h components/soc/esp32c3/include/soc/spi_pins.h -components/soc/esp32c3/include/soc/spi_reg.h components/soc/esp32c3/include/soc/systimer_reg.h components/soc/esp32c3/include/soc/systimer_struct.h components/soc/esp32c3/include/soc/uart_pins.h @@ -713,9 +704,7 @@ components/soc/esp32s2/include/soc/rtc_io_reg.h components/soc/esp32s2/include/soc/sens_reg.h components/soc/esp32s2/include/soc/sensitive_reg.h components/soc/esp32s2/include/soc/soc_ulp.h -components/soc/esp32s2/include/soc/spi_mem_reg.h components/soc/esp32s2/include/soc/spi_pins.h -components/soc/esp32s2/include/soc/spi_reg.h components/soc/esp32s2/include/soc/systimer_reg.h components/soc/esp32s2/include/soc/systimer_struct.h components/soc/esp32s2/include/soc/touch_sensor_channel.h @@ -1257,7 +1246,6 @@ examples/system/ota/otatool/main/otatool_main.c examples/system/ota/otatool/otatool_example.py examples/system/ota/simple_ota_example/main/simple_ota_example.c examples/system/perfmon/main/perfmon_example_main.c -examples/system/pthread/main/pthread_example.c examples/system/select/main/select_example.c examples/system/startup_time/main/hello_world_main.c examples/system/sysview_tracing/main/sysview_tracing.c diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 88de916a087..c3190053699 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -88,7 +88,6 @@ components/esp_hw_support/include/esp_private/esp_memprot_internal.h ### Here are the files that use CONFIG_XXX values but don't include sdkconfig.h # -components/esp_wifi/include/esp_private/wifi_os_adapter.h components/esp_coex/include/private/esp_coexist_adapter.h components/esp_coex/include/esp_coex_i154.h ### To be fixed: headers that rely on implicit inclusion @@ -101,6 +100,7 @@ components/esp_rom/include/esp32c2/rom/rtc.h components/esp_rom/include/esp32c6/rom/rtc.h components/esp_rom/include/esp32h2/rom/rtc.h components/esp_rom/include/esp32p4/rom/rtc.h +components/esp_rom/include/esp32c5/rom/rtc.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/secure_boot.h components/esp_rom/include/esp32c3/rom/spi_flash.h @@ -110,10 +110,6 @@ components/esp_rom/include/esp32s2/rom/secure_boot.h components/esp_rom/include/esp32s2/rom/opi_flash.h components/esp_rom/include/esp32s2/rom/efuse.h components/esp_ringbuf/include/freertos/ringbuf.h -components/esp_wifi/include/esp_wifi_crypto_types.h -components/esp_wifi/include/esp_wifi_netif.h -components/esp_wifi/include/smartconfig_ack.h -components/esp_wifi/include/esp_wifi_default.h components/esp_netif/include/esp_netif_defaults.h components/esp_netif/include/esp_netif_net_stack.h components/esp_netif/include/esp_netif_ppp.h @@ -121,7 +117,6 @@ components/protocomm/include/transports/protocomm_httpd.h components/fatfs/src/diskio.h components/fatfs/diskio/diskio_sdmmc.h components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h -components/wifi_provisioning/include/wifi_provisioning/scheme_softap.h components/usb/include/esp_private/usb_phy.h components/usb/include/usb/usb_types_stack.h diff --git a/tools/ci/ci_get_mr_info.py b/tools/ci/ci_get_mr_info.py index 4df7a05ab38..95a15a368e4 100644 --- a/tools/ci/ci_get_mr_info.py +++ b/tools/ci/ci_get_mr_info.py @@ -59,9 +59,17 @@ def get_mr_commits(source_branch: str) -> t.List['ProjectCommit']: return list(mr.commits()) -def get_mr_components(source_branch: str) -> t.List[str]: +def get_mr_components( + source_branch: t.Optional[str] = None, modified_files: t.Optional[t.List[str]] = None +) -> t.List[str]: components: t.Set[str] = set() - for f in get_mr_changed_files(source_branch): + if modified_files is None: + if not source_branch: + raise RuntimeError('--src-branch is required if --modified-files is not provided') + + modified_files = get_mr_changed_files(source_branch) + + for f in modified_files: file = Path(f) if ( file.parts[0] == 'components' @@ -92,10 +100,14 @@ def _print_list(_list: t.List[str], separator: str = '\n') -> None: actions = parser.add_subparsers(dest='action', help='info type', required=True) common_args = argparse.ArgumentParser(add_help=False) - common_args.add_argument('src_branch', help='source branch') + common_args.add_argument('--src-branch', help='source branch') + common_args.add_argument( + '--modified-files', + nargs='+', + help='space-separated list specifies the modified files. will be detected by --src-branch if not provided', + ) actions.add_parser('id', parents=[common_args]) - actions.add_parser('files', parents=[common_args]) actions.add_parser('commits', parents=[common_args]) actions.add_parser('components', parents=[common_args]) target = actions.add_parser('target_in_tags') @@ -104,13 +116,15 @@ def _print_list(_list: t.List[str], separator: str = '\n') -> None: args = parser.parse_args() if args.action == 'id': + if not args.src_branch: + raise RuntimeError('--src-branch is required') print(get_mr_iid(args.src_branch)) - elif args.action == 'files': - _print_list(get_mr_changed_files(args.src_branch)) elif args.action == 'commits': + if not args.src_branch: + raise RuntimeError('--src-branch is required') _print_list([commit.id for commit in get_mr_commits(args.src_branch)]) elif args.action == 'components': - _print_list(get_mr_components(args.src_branch)) + _print_list(get_mr_components(args.src_branch, args.modified_files)) elif args.action == 'target_in_tags': print(get_target_in_tags(args.tags)) else: diff --git a/tools/ci/exclude_check_tools_files.txt b/tools/ci/exclude_check_tools_files.txt index 01f0f5a95c7..c801f3f43c1 100644 --- a/tools/ci/exclude_check_tools_files.txt +++ b/tools/ci/exclude_check_tools_files.txt @@ -5,7 +5,6 @@ tools/ci/check_*.txt tools/ci/check_*.sh tools/ci/check_copyright_config.yaml tools/ci/get_all_test_results.py -tools/ci/idf_unity_tester.py tools/gdb_panic_server.py tools/check_term.py tools/check_python_dependencies.py diff --git a/tools/ci/executable-list.txt b/tools/ci/executable-list.txt index f0a4a6691da..04d372832e4 100644 --- a/tools/ci/executable-list.txt +++ b/tools/ci/executable-list.txt @@ -77,7 +77,7 @@ tools/ci/get_supported_examples.sh tools/ci/mirror-submodule-update.sh tools/ci/multirun_with_pyenv.sh tools/ci/push_to_github.sh -tools/ci/test_autocomplete.py +tools/ci/test_autocomplete/test_autocomplete.py tools/ci/test_configure_ci_environment.sh tools/ci/test_reproducible_build.sh tools/docker/entrypoint.sh @@ -109,5 +109,6 @@ tools/set-submodules-to-github.sh tools/test_apps/system/no_embedded_paths/check_for_file_paths.py tools/test_idf_py/test_hints.py tools/test_idf_py/test_idf_py.py +tools/test_idf_py/test_idf_qemu.py tools/test_idf_tools/test_idf_tools.py tools/test_mkdfu/test_mkdfu.py diff --git a/tools/ci/idf_pytest/constants.py b/tools/ci/idf_pytest/constants.py index 918ce54a2ad..a933333adc9 100644 --- a/tools/ci/idf_pytest/constants.py +++ b/tools/ci/idf_pytest/constants.py @@ -77,9 +77,10 @@ 'xtal_26mhz': 'runner with 26MHz xtal on board', 'xtal_40mhz': 'runner with 40MHz xtal on board', 'external_flash': 'external flash memory connected via VSPI (FSPI)', - 'sdcard_sdmode': 'sdcard running in SD mode', + 'sdcard_sdmode': 'sdcard running in SD mode, to be removed after test migration', 'sdcard_spimode': 'sdcard running in SPI mode', 'emmc': 'eMMC card', + 'sdcard': 'sdcard runner', 'MSPI_F8R8': 'runner with Octal Flash and Octal PSRAM', 'MSPI_F4R8': 'runner with Quad Flash and Octal PSRAM', 'MSPI_F4R4': 'runner with Quad Flash and Quad PSRAM', @@ -105,7 +106,9 @@ 'wifi_two_dut': 'tests should be run on runners which has two wifi duts connected.', 'generic_multi_device': 'generic multiple devices whose corresponding gpio pins are connected to each other.', 'twai_network': 'multiple runners form a TWAI network.', - 'sdio_master_slave': 'Test sdio multi board.', + 'sdio_master_slave': 'Test sdio multi board, esp32+esp32', + 'sdio_multidev_32_c6': 'Test sdio multi board, esp32+esp32c6', + 'usj_device': 'Test usb_serial_jtag and usb_serial_jtag is used as serial only (not console)' } diff --git a/tools/ci/idf_unity_tester.py b/tools/ci/idf_unity_tester.py deleted file mode 100644 index fdd781268bf..00000000000 --- a/tools/ci/idf_unity_tester.py +++ /dev/null @@ -1,397 +0,0 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -import logging -import os -import time -from multiprocessing import Manager, Process, Semaphore -from multiprocessing.managers import SyncManager -from typing import List, Union - -from pexpect.exceptions import TIMEOUT -from pytest_embedded import Dut, unity, utils -from pytest_embedded_idf.dut import UnittestMenuCase - - -class BaseTester: - """ - The base class that providing shared methods - - Attributes: - dut (Dut): Object of the Device under test - test_menu (List[UnittestMenuCase]): The list of the cases - retry_times (int): The retry times when failed to start a case - args (Any): Not used - """ - - # The patterns that indicate the runner is ready come from 'unity_runner.c' - ready_pattern_list = ['Press ENTER to see the list of tests', - 'Enter test for running', - 'Enter next test, or \'enter\' to see menu'] - - def __init__(self, dut: Union[Dut, List[Dut]], **kwargs) -> None: # type: ignore - self.retry_times = 30 - if isinstance(dut, List): - for item in dut: - if isinstance(item, Dut): - self.dut = item - break - else: - self.dut = dut - for k, v in kwargs.items(): - setattr(self, k, v) - if 'test_menu' not in kwargs: - self.get_test_menu() - - def get_test_menu(self) -> None: - """ - Get the test menu of this test app - - Notes: - It will do a hard reset after getting the test menu to ensure - the patterns that indicate the case is ready not taken by the parser. - Please use this function to get the test menu while using this script - """ - self.dut.write('') - self.test_menu = self.dut.parse_test_menu() - self.dut.serial.hard_reset() - - -class NormalCaseTester(BaseTester): - """ - Tester of normal type case - - Attributes: - dut (Dut): Object of the Device under test - test_menu (List[UnittestMenuCase]): The list of the cases - retry_times (int): The retry times when failed to start a case - args (Any): Not used - """ - - def run_all_normal_cases(self, reset: bool = False, timeout: int = 90) -> None: - """ - Run all normal cases - - Args: - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - for case in self.test_menu: - self.run_normal_case(case, reset, timeout=timeout) - - def run_normal_case(self, case: UnittestMenuCase, reset: bool = False, timeout: int = 90) -> None: - """ - Run a specific normal case - - Notes: - Will skip if the case type is not normal - - Args: - case: the specific case that parsed in test menu - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - if case.type == 'normal': - if reset: - self.dut.serial.hard_reset() - self.dut.expect(self.ready_pattern_list, timeout=timeout) - # Retry if write not success - for retry in range(self.retry_times): - self.dut.write(str(case.index)) - try: - self.dut.expect_exact('Running {}...'.format(case.name), timeout=1) - break - except TIMEOUT as e: - if retry >= self.retry_times - 1: - raise e - self.dut.expect_unity_test_output(timeout=timeout) - - -class MultiStageCaseTester(BaseTester): - """ - Tester of multiple stage type case - - Attributes: - dut (Dut): Object of the Device under test - test_menu (List[UnittestMenuCase]): The list of the cases - retry_times (int): The retry times when failed to start a case - args (Any): Not used - """ - - def run_all_multi_stage_cases(self, reset: bool = False, timeout: int = 90) -> None: - """ - Run all multi_stage cases - - Args: - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - for case in self.test_menu: - self.run_multi_stage_case(case, reset, timeout=timeout) - - def run_multi_stage_case(self, case: UnittestMenuCase, reset: bool = False, timeout: int = 90) -> None: - """ - Run a specific multi_stage case - - Notes: - Will skip if the case type is not multi_stage - - Args: - case: the specific case that parsed in test menu - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - if case.type == 'multi_stage': - if reset: - self.dut.serial.hard_reset() - for sub_case in case.subcases: - self.dut.expect(self.ready_pattern_list, timeout=timeout) - # Retry if write not success - for retry in range(self.retry_times): - self.dut.write(str(case.index)) - try: - self.dut.expect_exact('Running {}...'.format(case.name), timeout=1) - break - except TIMEOUT as e: - if retry >= self.retry_times - 1: - raise e - self.dut.write(str(sub_case['index'])) - - self.dut.expect_unity_test_output(timeout=timeout) - - -class MultiDevResource: - """ - Resources of multi_dev dut - - Attributes: - dut (Dut): Object of the Device under test - sem (Semaphore): Semaphore of monitoring whether the case finished - recv_sig (List[str]): The list of received signals from other dut - thread (Process): The thread of monitoring the signals - """ - - def __init__(self, dut: Dut, manager: SyncManager) -> None: - self.dut = dut - self.sem = Semaphore() - self.recv_sig = manager.list() # type: list[str] - self.process: Process = None # type: ignore - - -class MultiDevCaseTester(BaseTester): - """ - Tester of multi_device case - - Attributes: - group (List[MultiDevResource]): The group of the devices' resources - dut (Dut): The first dut, mainly used to get the test menu only - test_menu (List[UnittestMenuCase]): The list of the cases - retry_times (int): The retry times when failed to start a case - """ - - # The signal pattens come from 'test_utils.c' - SEND_SIGNAL_PREFIX = 'Send signal: ' - WAIT_SIGNAL_PREFIX = 'Waiting for signal: ' - UNITY_SEND_SIGNAL_REGEX = SEND_SIGNAL_PREFIX + r'\[(.*?)\]!' - UNITY_WAIT_SIGNAL_REGEX = WAIT_SIGNAL_PREFIX + r'\[(.*?)\]!' - - def __init__(self, dut: Union[Dut, List[Dut]], **kwargs) -> None: # type: ignore - """ - Create the object for every dut and put them into the group - """ - super().__init__(dut, **kwargs) - self._manager = Manager() - self.group: List[MultiDevResource] = [] - if isinstance(dut, List): - for item in dut: - if isinstance(item, Dut): - dev_res = MultiDevResource(item, self._manager) - self.group.append(dev_res) - else: - dev_res = MultiDevResource(dut, self._manager) - self.group.append(dev_res) - - def _wait_multi_dev_case_finish(self, timeout: int = 60) -> None: - """ - Wait until all the sub-cases of this multi_device case finished - """ - for d in self.group: - if d.sem.acquire(timeout=timeout): - d.sem.release() - else: - raise TimeoutError('Wait case to finish timeout') - - def _start_sub_case_process(self, dev_res: MultiDevResource, case: UnittestMenuCase, sub_case_index: int, timeout: int = 60) -> None: - """ - Start the thread monitoring on the corresponding dut of the sub-case - """ - # Allocate the kwargs that pass to '_run' - _kwargs = {} - _kwargs['dut'] = dev_res.dut - _kwargs['dev_res'] = dev_res - _kwargs['case'] = case - _kwargs['sub_case_index'] = sub_case_index - _kwargs['timeout'] = timeout - - # Create the thread of the sub-case - dev_res.process = Process(target=self._run, kwargs=_kwargs, daemon=True) - dev_res.process.start() - # Process starts, acquire the semaphore to block '_wait_multi_dev_case_finish' - dev_res.sem.acquire() - - def _run(self, **kwargs) -> None: # type: ignore - """ - The thread target function - Will run for each case on each dut - - Call the wrapped function to trigger the case - Then keep listening on the dut for the signal - - - If the dut send a signal, it will be put into others' recv_sig - - If the dut waits for a signal, it block and keep polling for the recv_sig until get the signal it requires - - If the dut finished running the case, it will quite the loop and terminate the thread - """ - signal_pattern_list = [ - self.UNITY_SEND_SIGNAL_REGEX, # The dut send a signal - self.UNITY_WAIT_SIGNAL_REGEX, # The dut is blocked and waiting for a signal - unity.UNITY_SUMMARY_LINE_REGEX, # Means the case finished - ] - dut = kwargs['dut'] - dev_res = kwargs['dev_res'] - case = kwargs['case'] - sub_case_index = kwargs['sub_case_index'] - timeout = kwargs['timeout'] - # Start the case - dut.expect(self.ready_pattern_list) - # Retry at most 30 times if not write successfully - for retry in range(self.retry_times): - dut.write(str(case.index)) - try: - dut.expect_exact('Running {}...'.format(case.name), timeout=10) - break - except TIMEOUT as e: - if retry >= self.retry_times - 1: - dev_res.sem.release() - raise e - - dut.write(str(sub_case_index)) - - # Wait for the specific patterns, only exist when the sub-case finished - while True: - pat = dut.expect(signal_pattern_list, timeout=timeout) - if pat is not None: - match_str = pat.group().decode('utf-8') - - # Send a signal - if match_str.find(self.SEND_SIGNAL_PREFIX) >= 0: - send_sig = pat.group(1).decode('utf-8') - for d in self.group: - d.recv_sig.append(send_sig) - - # Waiting for a signal - elif match_str.find(self.WAIT_SIGNAL_PREFIX) >= 0: - wait_sig = pat.group(1).decode('utf-8') - while True: - if wait_sig in dev_res.recv_sig: - dev_res.recv_sig.remove(wait_sig) - dut.write('') - break - # Keep waiting the signal - else: - time.sleep(0.1) - - # Case finished - elif match_str.find('Tests') >= 0: - log = utils.remove_asci_color_code(dut.pexpect_proc.before) - dut.testsuite.add_unity_test_cases(log) - break - - # The case finished, release the semaphore to unblock the '_wait_multi_dev_case_finish' - # - # Manually to create the real test case junit report - # The child process attributes won't be reflected to the parent one. - junit_report = os.path.splitext(dut.logfile)[0] + f'_{case.index}_{sub_case_index}.xml' - dut.testsuite.dump(junit_report) - logging.info(f'Created unity output junit report: {junit_report}') - - dev_res.sem.release() - - def run_all_multi_dev_cases(self, reset: bool = False, timeout: int = 60) -> None: - """ - Run only multi_device cases - - Args: - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - for case in self.test_menu: - # Run multi_device case on every device - self.run_multi_dev_case(case, reset, timeout) - - def run_multi_dev_case(self, case: UnittestMenuCase, reset: bool = False, timeout: int = 60) -> None: - """ - Run a specific multi_device case - - Notes: - Will skip if the case type is not multi_device - - Args: - case: the specific case that parsed in test menu - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - if case.type == 'multi_device' and len(self.group) > 1: - if reset: - for dev_res in self.group: - dev_res.dut.serial.hard_reset() - # delay a few seconds to make sure the duts are ready. - time.sleep(5) - for sub_case in case.subcases: - if isinstance(sub_case['index'], str): - index = int(sub_case['index'], 10) - else: - index = sub_case['index'] - self._start_sub_case_process(dev_res=self.group[index - 1], case=case, - sub_case_index=index, timeout=timeout) - # Waiting all the devices to finish their test cases - self._wait_multi_dev_case_finish(timeout=timeout) - - -class CaseTester(NormalCaseTester, MultiStageCaseTester, MultiDevCaseTester): - """ - The Generic tester of all the types - - Attributes: - group (List[MultiDevResource]): The group of the devices' resources - dut (Dut): The first dut if there is more than one - test_menu (List[UnittestMenuCase]): The list of the cases - """ - - def run_all_cases(self, reset: bool = False, timeout: int = 60) -> None: - """ - Run all cases - - Args: - reset: whether do a hardware reset before running the case - timeout: timeout in second - """ - for case in self.test_menu: - self.run_case(case, reset, timeout=timeout) - - def run_case(self, case: UnittestMenuCase, reset: bool = False, timeout: int = 60) -> None: - """ - Run a specific case - - Args: - case: the specific case that parsed in test menu - reset: whether do a hardware reset before running the case - timeout: timeout in second, the case's timeout attribute has a higher priority than this param. - """ - _timeout = int(case.attributes.get('timeout', timeout)) - if case.type == 'normal': - self.run_normal_case(case, reset, timeout=_timeout) - elif case.type == 'multi_stage': - self.run_multi_stage_case(case, reset, timeout=_timeout) - elif case.type == 'multi_device': - # here we always do a hard reset between test cases - # since the buffer can't be kept between test cases (which run in different processes) - self.run_multi_dev_case(case, reset=True, timeout=_timeout) diff --git a/tools/ci/ignore_build_warnings.txt b/tools/ci/ignore_build_warnings.txt index 301da338fa9..fc5ac452abe 100644 --- a/tools/ci/ignore_build_warnings.txt +++ b/tools/ci/ignore_build_warnings.txt @@ -15,88 +15,58 @@ CryptographyDeprecationWarning Warning: \d+/\d+ app partitions are too small for binary CMake Deprecation Warning at main/lib/tinyxml2/CMakeLists\.txt:11 \(cmake_policy\) The smallest .+ partition is nearly full \(\d+% free space left\)! -warning: unknown kconfig symbol 'A2DP_SINK_ENABLE' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults -warning: unknown kconfig symbol 'A2DP_SRC_ENABLE' assigned to 'n' in /builds/espressif/esp-idf/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults -warning: unknown kconfig symbol 'APP_OFFSET' assigned to '0x10000' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'BLE_ENABLE_SRVCHG_REG' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/sdkconfig.defaults -warning: unknown kconfig symbol 'BT_CTRL_BLE_MESH_SCAN_DUPL_EN' assigned to* warning: unknown kconfig symbol 'BT_CTRL_COEX_PARAMETERS_ENABLE' assigned to* warning: unknown kconfig symbol 'BT_CTRL_COEX_USE_HOOKS' assigned to* -warning: unknown kconfig symbol 'BT_CTRL_SCAN_DUPL_TYPE_DATA_DEVICE' assigned to* warning: unknown kconfig symbol 'BT_LE_50_FEATURE_SUPPORT' assigned to* warning: unknown kconfig symbol 'BT_LE_MAX_EXT_ADV_INSTANCES' assigned to* -warning: unknown kconfig symbol 'BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER' assigned to 'n' in /builds/espressif/esp-idf/examples/bluetooth/nimble/power_save/sdkconfig.defaults.* warning: unknown kconfig symbol 'BTDM_BLE_MESH_SCAN_DUPL_EN' assigned to* -warning: unknown kconfig symbol 'BTDM_CTRL_HCI_MODE_VHCI' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_hid_device/sdkconfig.defaults -warning: unknown kconfig symbol 'BTDM_CTRL_HCI_MODE_VHCI' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_hid_host/sdkconfig.defaults warning: unknown kconfig symbol 'BTDM_CTRL_MODE_BLE_ONLY' assigned to* warning: unknown kconfig symbol 'BTDM_CTRL_MODE_BR_EDR_ONLY' assigned to* warning: unknown kconfig symbol 'BTDM_CTRL_MODE_BTDM' assigned to* -warning: unknown kconfig symbol 'BTDM_MODEM_SLEEP' assigned to* warning: unknown kconfig symbol 'BTDM_SCAN_DUPL_TYPE_DATA_DEVICE' assigned to* warning: unknown kconfig symbol 'CTRL_BTDM_MODEM_SLEEP' assigned to* -warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_240' assigned to 'y' in /builds/espressif/esp-idf/components/vfs/test_apps/* -warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_240' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/wifi_coexist/ -warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_80' assigned to 'y' in /builds/espressif/esp-idf/examples/system/deep_sleep/* -warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_80' assigned to 'y' in /builds/espressif/esp-idf/examples/system/light_sleep/* -warning: unknown kconfig symbol 'ESP_WIFI_SW_COEXIST_PREFERENCE_BALANCE' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESP_WIFI_SW_COEXIST_PREFERENCE_VALUE' assigned to '2' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.iram -warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/fast_provisioninging/fast_prov_server/sdkconfig.ci.iram -warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/nimble/ble_htp/htp_prph/sdkconfig.ci -warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/sdkconfig.ci -warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/nimble/blehr/sdkconfig.ci -warning: unknown kconfig symbol 'ESP32_REV_MIN_3' assigned to 'y' in /builds/espressif/esp-idf/examples/system/ota/simple_ota_example/sdkconfig.ci.on_update_no_sb_rsa -warning: unknown kconfig symbol 'ESP32_REV_MIN' assigned to '3' in /builds/espressif/esp-idf/examples/system/ota/simple_ota_example/sdkconfig.ci.on_update_no_sb_rsa -warning: unknown kconfig symbol 'ESP32H4_RTC_CLK_CAL_CYCLES' assigned to '576' in /builds/espressif/esp-idf/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 -warning: unknown kconfig symbol 'ESP32H4_RTC_CLK_SRC_EXT_CRYS' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 -warning: unknown kconfig symbol 'ESPTOOLPY_BAUD_921600B' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE_4MB' assigned to 'y' in /builds/espressif/esp-idf/components/esp_partition/host_test/partition_api_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE_4MB' assigned to 'y' in /builds/espressif/esp-idf/components/spiffs/host_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"4MB"' in /builds/espressif/esp-idf/components/esp_partition/host_test/partition_api_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"4MB"' in /builds/espressif/esp-idf/components/spiffs/host_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"8MB"' in /builds/espressif/esp-idf/components/wear_levelling/host_test/sdkconfig.defaults -warning: unknown kconfig symbol 'ESPTOOLPY_MONITOR_BAUD_921600B' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/vendor_models/* -warning: unknown kconfig symbol 'FMB_TIMER_GROUP' assigned to '0' in /builds/espressif/esp-idf/examples/protocols/modbus/tcp/* -warning: unknown kconfig symbol 'FMB_TIMER_INDEX' assigned to '0' in /builds/espressif/esp-idf/examples/protocols/modbus/tcp/* -warning: unknown kconfig symbol 'FMB_TIMER_ISR_IN_IRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/protocols/modbus/* -warning: unknown kconfig symbol 'LIBSODIUM_USE_MBEDTLS_SHA' assigned to 'y' in /builds/espressif/esp-idf/examples/openthread/ot_br/* -warning: unknown kconfig symbol 'LIBSODIUM_USE_MBEDTLS_SHA' assigned to 'y' in /builds/espressif/esp-idf/examples/openthread/ot_cli/* -warning: unknown kconfig symbol 'LIBSODIUM_USE_MBEDTLS_SHA' assigned to 'y' in /builds/espressif/esp-idf/examples/openthread/ot_rcp/* -warning: unknown kconfig symbol 'LWIP_ETHARP_TRUST_IP_MAC' assigned to 'n' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/* -warning: unknown kconfig symbol 'LWIP_ETHARP_TRUST_IP_MAC' assigned to 'n' in /builds/espressif/esp-idf/examples/wifi/iperf/* -warning: unknown kconfig symbol 'LWIP_ETHARP_TRUST_IP_MAC' assigned to 'n' in /builds/espressif/esp-idf/idf-app-test/apps/iperf/* -warning: unknown kconfig symbol 'LWIP_IP_FRAG' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'LWIP_IP_REASSEMBLY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'MB_SLAVE_IP_FROM_STDIN' assigned to 'y' in /builds/espressif/esp-idf/examples/protocols/modbus/* -warning: unknown kconfig symbol 'MDNS_STRICT_MODE' assigned to 'y' in /builds/espressif/esp-idf/examples/openthread/ot_br/* -warning: unknown kconfig symbol 'OPENTHREAD_TREL' assigned to 'y' in /builds/espressif/esp-idf/examples/openthread/ot_br/* -warning: unknown kconfig symbol 'PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET' assigned to '0x10000' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'SDK_MAKE_WARN_UNDEFINED_VARIABLES' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/coex_test/sdkconfig.defaults -warning: unknown kconfig symbol 'SPI_FLASH_USE_LEGACY_IMPL' assigned to '1' in /builds/espressif/esp-idf/components/wear_levelling/host_test/sdkconfig.defaults -warning: unknown kconfig symbol 'SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM_FETCH_INSTRUCTIONS' assigned to 'y' in /builds/espressif/esp-idf/components/spi_flash/test_apps/mspi_test/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM_IGNORE_NOTFOUND' assigned to 'y' in /builds/espressif/esp-idf/examples/network/simple_sniffer/sdkconfig.ci.mem -warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in /builds/espressif/esp-idf/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in /builds/espressif/esp-idf/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in /builds/espressif/esp-idf/components/spiffs/test_apps/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in /builds/espressif/esp-idf/components/vfs/test_apps/* -warning: unknown kconfig symbol 'SPIRAM_MALLOC_RESERVE_INTERNAL' assigned to '150000' in /builds/espressif/esp-idf/examples/peripherals/usb/host/uvc/sdkconfig.defaults -warning: unknown kconfig symbol 'SPIRAM_RODATA' assigned to 'y' in /builds/espressif/esp-idf/components/spi_flash/test_apps/mspi_test/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM_TRY_ALLOCATE_WIFI_LWIP' assigned to 'y' in /builds/espressif/esp-idf/examples/peripherals/usb/host/uvc/sdkconfig.defaults -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/components/spiffs/test_apps/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/components/vfs/test_apps/* -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.psram -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/network/simple_sniffer/sdkconfig.ci.mem -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/peripherals/usb/host/uvc/sdkconfig.defaults -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/protocols/http2_request/sdkconfig.ci -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/protocols/https_mbedtls/sdkconfig.ci -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/protocols/https_request/sdkconfig.ci -warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in /builds/espressif/esp-idf/examples/protocols/https_request/sdkconfig.ci.ssldyn -warning: unknown kconfig symbol 'TINYUSB' assigned to 'y' in /builds/espressif/esp-idf/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/sdkconfig.defaults -warning: unknown kconfig symbol 'UNITY_FREERTOS_STACK_SIZE' assigned to '12288' in /builds/espressif/esp-idf/components/bt/test_apps/sdkconfig.defaults -warning: unknown kconfig symbol 'WIFI_ENABLED' assigned to 'n' in /builds/espressif/esp-idf/examples/bluetooth/bluedroid/classic_bt/* -warning: unknown kconfig symbol 'WPA3_SAE' assigned to 'y' in /builds/espressif/esp-idf/components/wpa_supplicant/test_apps/sdkconfig.defaults -warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_80' assigned to 'y' in /builds/espressif/esp-idf/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults +warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_240' assigned to 'y' in .*/components/vfs/test_apps/* +warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_240' assigned to 'y' in .*/examples/bluetooth/esp_ble_mesh/wifi_coexist/ +warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_80' assigned to 'y' in .*/examples/system/deep_sleep/* +warning: unknown kconfig symbol 'ESP_DEFAULT_CPU_FREQ_MHZ_80' assigned to 'y' in .*/examples/system/light_sleep/* +warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in .*/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.iram +warning: unknown kconfig symbol 'ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY' assigned to 'y' in .*/examples/bluetooth/esp_ble_mesh/fast_provisioninging/fast_prov_server/sdkconfig.ci.iram +warning: unknown kconfig symbol 'ESP32_REV_MIN_3' assigned to 'y' in .*/examples/system/ota/simple_ota_example/sdkconfig.ci.on_update_no_sb_rsa +warning: unknown kconfig symbol 'ESP32_REV_MIN' assigned to '3' in .*/examples/system/ota/simple_ota_example/sdkconfig.ci.on_update_no_sb_rsa +warning: unknown kconfig symbol 'ESP32H4_RTC_CLK_CAL_CYCLES' assigned to '576' in .*/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 +warning: unknown kconfig symbol 'ESP32H4_RTC_CLK_SRC_EXT_CRYS' assigned to 'y' in .*/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 +warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE_4MB' assigned to 'y' in .*/components/esp_partition/host_test/partition_api_test/sdkconfig.defaults +warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE_4MB' assigned to 'y' in .*/components/spiffs/host_test/sdkconfig.defaults +warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"4MB"' in .*/components/esp_partition/host_test/partition_api_test/sdkconfig.defaults +warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"4MB"' in .*/components/spiffs/host_test/sdkconfig.defaults +warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"8MB"' in .*/components/wear_levelling/host_test/sdkconfig.defaults +warning: unknown kconfig symbol 'ESPTOOLPY_FLASHSIZE' assigned to '"8MB"' in .*/components/fatfs/host_test/sdkconfig.defaults +warning: unknown kconfig symbol 'ESPTOOLPY_MONITOR_BAUD_921600B' assigned to 'y' in .*/examples/bluetooth/esp_ble_mesh/vendor_models/* +warning: unknown kconfig symbol 'FMB_TIMER_GROUP' assigned to '0' in .*/examples/protocols/modbus/tcp/* +warning: unknown kconfig symbol 'FMB_TIMER_INDEX' assigned to '0' in .*/examples/protocols/modbus/tcp/* +warning: unknown kconfig symbol 'FMB_TIMER_ISR_IN_IRAM' assigned to 'y' in .*/examples/protocols/modbus/* +warning: unknown kconfig symbol 'LWIP_ETHARP_TRUST_IP_MAC' assigned to 'n' in .*/examples/bluetooth/esp_ble_mesh/* +warning: unknown kconfig symbol 'LWIP_ETHARP_TRUST_IP_MAC' assigned to 'n' in .*/examples/wifi/iperf/* +warning: unknown kconfig symbol 'LWIP_ETHARP_TRUST_IP_MAC' assigned to 'n' in .*/idf-app-test/apps/iperf/* +warning: unknown kconfig symbol 'MB_SLAVE_IP_FROM_STDIN' assigned to 'y' in .*/examples/protocols/modbus/* +warning: unknown kconfig symbol 'SPI_FLASH_USE_LEGACY_IMPL' assigned to '1' in .*/components/wear_levelling/host_test/sdkconfig.defaults +warning: unknown kconfig symbol 'SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY' assigned to 'y' in .*/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM_FETCH_INSTRUCTIONS' assigned to 'y' in .*/components/spi_flash/test_apps/mspi_test/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM_IGNORE_NOTFOUND' assigned to 'y' in .*/examples/network/simple_sniffer/sdkconfig.ci.mem +warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in .*/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in .*/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in .*/components/spiffs/test_apps/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM_MALLOC_ALWAYSINTERNAL' assigned to '0' in .*/components/vfs/test_apps/* +warning: unknown kconfig symbol 'SPIRAM_RODATA' assigned to 'y' in .*/components/spi_flash/test_apps/mspi_test/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/components/spiffs/test_apps/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/components/vfs/test_apps/* +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.ci.psram +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/examples/network/simple_sniffer/sdkconfig.ci.mem +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/examples/protocols/http2_request/sdkconfig.ci +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/examples/protocols/https_mbedtls/sdkconfig.ci +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/examples/protocols/https_request/sdkconfig.ci +warning: unknown kconfig symbol 'SPIRAM' assigned to 'y' in .*/examples/protocols/https_request/sdkconfig.ci.ssldyn +warning: unknown kconfig symbol 'UNITY_FREERTOS_STACK_SIZE' assigned to '12288' in .*/components/bt/test_apps/sdkconfig.defaults +warning: unknown kconfig symbol 'WPA3_SAE' assigned to 'y' in .*/components/wpa_supplicant/test_apps/sdkconfig.defaults diff --git a/tools/ci/mypy_ignore_list.txt b/tools/ci/mypy_ignore_list.txt index b7227a91a27..0edb5e3aca5 100644 --- a/tools/ci/mypy_ignore_list.txt +++ b/tools/ci/mypy_ignore_list.txt @@ -4,7 +4,6 @@ components/efuse/test_efuse_host/efuse_tests.py components/esp_local_ctrl/python/esp_local_ctrl_pb2.py components/mbedtls/esp_crt_bundle/gen_crt_bundle.py components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/test_gen_crt_bundle.py -components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py components/partition_table/gen_empty_partition.py components/partition_table/gen_esp32part.py components/partition_table/parttool.py @@ -34,7 +33,6 @@ tools/ci/python_packages/idf_iperf_test_util/LineChart.py tools/ci/python_packages/idf_iperf_test_util/PowerControl.py tools/ci/python_packages/idf_iperf_test_util/TestReport.py tools/ci/python_packages/wifi_tools.py -tools/ci/test_autocomplete.py tools/esp_app_trace/espytrace/apptrace.py tools/esp_app_trace/espytrace/sysview.py tools/esp_app_trace/logtrace_proc.py diff --git a/tools/ci/python_packages/gitlab_api.py b/tools/ci/python_packages/gitlab_api.py index b9f3d326cef..1482ddd52fa 100644 --- a/tools/ci/python_packages/gitlab_api.py +++ b/tools/ci/python_packages/gitlab_api.py @@ -4,6 +4,7 @@ import logging import os import re +import sys import tarfile import tempfile import time @@ -230,9 +231,19 @@ def download_archive(self, ref: str, destination: str, project_id: Optional[int] @staticmethod def decompress_archive(path: str, destination: str) -> str: - with tarfile.open(path, 'r') as archive_file: - root_name = archive_file.getnames()[0] - archive_file.extractall(destination) + full_destination = os.path.abspath(destination) + # By default max path lenght is set to 260 characters + # Prefix `\\?\` extends it to 32,767 characters + if sys.platform == 'win32': + full_destination = '\\\\?\\' + full_destination + + try: + with tarfile.open(path, 'r') as archive_file: + root_name = archive_file.getnames()[0] + archive_file.extractall(full_destination) + except tarfile.TarError as e: + logging.error(f'Error while decompressing archive {path}') + raise e return os.path.join(os.path.realpath(destination), root_name) diff --git a/tools/ci/test_autocomplete.py b/tools/ci/test_autocomplete.py deleted file mode 100755 index acff514d017..00000000000 --- a/tools/ci/test_autocomplete.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -import os -import sys -import unittest - -import pexpect - - -class Test(unittest.TestCase): - def test_fish(self): - os.environ['TERM'] = 'vt100' - child = pexpect.spawn('fish -i') - with open(os.environ['IDF_PATH'] + '/fish' + str(sys.version_info.major) + '.out', 'wb') as output: - child.logfile = output - child.sendline('. ./export.fish') - result = child.expect( - ['Go to the project directory and run.*idf\\.py build', pexpect.EOF, - pexpect.TIMEOUT], timeout=40) - self.assertEqual(result, 0, 'Export was not successful!') - child.send('idf.py \t\t') - result = child.expect(['all.*app.*app-flash.*bootloader.*', pexpect.EOF, pexpect.TIMEOUT], timeout=40) - self.assertEqual(result, 0, 'Autocompletion for idf.py failed in fish!') - - def test_bash(self): - os.environ['TERM'] = 'xterm-256color' - child = pexpect.spawn('bash -i') - with open(os.environ['IDF_PATH'] + '/bash' + str(sys.version_info.major) + '.out', 'wb') as output: - child.logfile = output - child.sendline('. ./export.sh') - child.send('idf.py \t\t') - result = child.expect( - ['Go to the project directory and run.*idf\\.py build', pexpect.EOF, - pexpect.TIMEOUT], timeout=40) - self.assertEqual(result, 0, 'Export was not successful!') - result = child.expect( - ['all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', pexpect.EOF, - pexpect.TIMEOUT], timeout=40) - self.assertEqual(result, 0, 'Autocompletion for idf.py failed in bash!') - - def test_zsh(self): - child = pexpect.spawn('zsh -i') - with open(os.environ['IDF_PATH'] + '/zsh' + str(sys.version_info.major) + '.out', 'wb') as output: - child.logfile = output - child.sendline('. ./export.sh') - result = child.expect( - ['Go to the project directory and run.*idf\\.py build', pexpect.EOF, - pexpect.TIMEOUT], timeout=40) - self.assertEqual(result, 0, 'Export was not successful!') - child.send('idf.py \t\t') - result = child.expect( - ['all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', pexpect.EOF, - pexpect.TIMEOUT], timeout=40) - self.assertEqual(result, 0, 'Autocompletion for idf.py failed in zsh!') - - -if __name__ == '__main__': - unittest.main() diff --git a/tools/test_sbom/pytest.ini b/tools/ci/test_autocomplete/pytest.ini similarity index 100% rename from tools/test_sbom/pytest.ini rename to tools/ci/test_autocomplete/pytest.ini diff --git a/tools/ci/test_autocomplete/test_autocomplete.py b/tools/ci/test_autocomplete/test_autocomplete.py new file mode 100755 index 00000000000..49fe24be62e --- /dev/null +++ b/tools/ci/test_autocomplete/test_autocomplete.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import collections +import os +import unittest + +import pexpect + +Test = collections.namedtuple('Test', ['name', 'term', 'pattern', 'ext']) + + +TESTS = (Test('fish', 'vt100', 'all.*app.*app-flash.*bootloader.*', 'fish'), + Test('bash', 'xterm-256color', 'all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', 'sh'), + Test('zsh', '', 'all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', 'sh')) + + +# Additional positional arguments for all child.expect() calls are constant so we can rely on the order and print message +# about which pattern was matched +pargs = (pexpect.EOF, pexpect.TIMEOUT) + + +def get_fail_msg(pproc: pexpect.spawn, msg: str, index: int) -> str: + try: + buf = pproc._buffer.getvalue() + except AttributeError: + # _buffer is an internal of pexpect.spawn and is not part of the API. + # Either there is no _buffer or it is not io.BytesIO() anymore. + buf = '' + + return '{} ({}) buffer: "{}"'.format(msg, 'EOF - child has exited' if index == 1 else 'TIMEOUT', buf) + + +class UTTest(unittest.TestCase): + + def test_shell(self) -> None: + idf_path = os.environ['IDF_PATH'] + env = os.environ.copy() + for test in TESTS: + with self.subTest(): + with open(os.path.join(idf_path, f'{test.name}.out'), 'wb') as o: + env['TERM'] = test.term + with pexpect.spawn(f'{test.name} -i', env=env, logfile=o, timeout=200) as pproc: + pproc.sendline(f'. {idf_path}/export.{test.ext}') + i = pproc.expect(['Go to the project directory and run.*idf\\.py build', *pargs]) + self.assertEqual(i, 0, get_fail_msg(pproc, 'Export was not successful!', i)) + pproc.send('idf.py \t\t') + i = pproc.expect([test.pattern, *pargs], timeout=100) + self.assertEqual(i, 0, get_fail_msg(pproc, f'Autocompletion for idf.py failed in {test.name}!', i)) + + +if __name__ == '__main__': + unittest.main() diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake index b2dc61c8eb4..64358153530 100644 --- a/tools/cmake/build.cmake +++ b/tools/cmake/build.cmake @@ -23,7 +23,7 @@ endfunction() # also added to the internal list of build properties if it isn't there already. # # @param[in] property the property to set the value of -# @param[out] value value of the property +# @param[in] value value of the property # # @param[in, optional] APPEND (option) append the value to the current value of the # property instead of replacing it @@ -129,7 +129,7 @@ function(__build_set_lang_version) if(NOT IDF_TARGET STREQUAL "linux") # Building for chip targets: we use a known version of the toolchain. # Use latest supported versions. - # Please update docs/en/api-guides/cplusplus.rst and + # Please update docs/en/api-guides/c.rst, docs/en/api-guides/cplusplus.rst and # tools/test_apps/system/cxx_build_test/main/test_cxx_standard.cpp when changing this. set(c_std gnu17) set(cxx_std gnu++2b) diff --git a/tools/cmake/dfu.cmake b/tools/cmake/dfu.cmake index ead9bac1e10..4f58cd283d1 100644 --- a/tools/cmake/dfu.cmake +++ b/tools/cmake/dfu.cmake @@ -15,6 +15,8 @@ function(__add_dfu_targets) return() elseif("${target}" STREQUAL "esp32c6") return() + elseif("${target}" STREQUAL "esp32c5") + return() elseif("${target}" STREQUAL "esp32h2") return() elseif("${target}" STREQUAL "esp32p4") diff --git a/tools/cmake/git_submodules.cmake b/tools/cmake/git_submodules.cmake index e36ee919f73..1e1e3967f82 100644 --- a/tools/cmake/git_submodules.cmake +++ b/tools/cmake/git_submodules.cmake @@ -49,8 +49,8 @@ else() endif() elseif(NOT "${status}" STREQUAL " ") - message(WARNING "Git submodule ${submodule_path} is out of date. " - "Run 'git submodule update --init --recursive' to fix.") + message(WARNING "Git submodule ${submodule_path} is out of date. Run the following command to fix: " + "git submodule update --init --recursive") endif() # Force a re-run of cmake if the submodule's .git file changes or is changed (ie accidental deinit) diff --git a/tools/cmake/project.cmake b/tools/cmake/project.cmake index 2ebb31ff35c..e92e5855d5a 100644 --- a/tools/cmake/project.cmake +++ b/tools/cmake/project.cmake @@ -64,29 +64,87 @@ endif() idf_build_set_property(__COMPONENT_MANAGER_INTERFACE_VERSION 2) # -# Get the project version from either a version file or the Git revision. This is passed -# to the idf_build_process call. Dependencies are also set here for when the version file -# changes (if it is used). +# Parse and store the VERSION argument provided to the project() command. # -function(__project_get_revision var) - set(_project_path "${CMAKE_CURRENT_LIST_DIR}") - if(NOT DEFINED PROJECT_VER) - if(EXISTS "${_project_path}/version.txt") - file(STRINGS "${_project_path}/version.txt" PROJECT_VER) - set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS "${_project_path}/version.txt") - else() - git_describe(PROJECT_VER_GIT "${_project_path}") - if(PROJECT_VER_GIT) - set(PROJECT_VER ${PROJECT_VER_GIT}) - else() - message(STATUS "Could not use 'git describe' to determine PROJECT_VER.") - set(PROJECT_VER 1) - endif() +function(__parse_and_store_version_arg) + # The project_name is the fisrt argument that was passed to the project() command + set(project_name ${ARGV0}) + + # Parse other arguments passed to the project() call + set(options) + set(oneValueArgs VERSION) + set(multiValueArgs) + cmake_parse_arguments(PROJECT "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + # If the VERSION keyword exists but no version string is provided then raise a warning + if((NOT PROJECT_VERSION + OR PROJECT_VERSION STREQUAL "NOTFOUND") + AND NOT PROJECT_VERSION STREQUAL "0") + message(STATUS "VERSION keyword not followed by a value or was followed by a value that expanded to nothing.") + # Default the version to 1 in this case + set(project_ver 1) + else() + # Check if version is valid. cmake allows the version to be in the format [.[.[.]]]] + string(REGEX MATCH "^([0-9]+(\\.[0-9]+(\\.[0-9]+(\\.[0-9]+)?)?)?)?$" version_valid ${PROJECT_VERSION}) + if(NOT version_valid AND NOT PROJECT_VERSION STREQUAL "0") + message(SEND_ERROR "Version \"${PROJECT_VERSION}\" format invalid.") + return() + endif() + + # Split the version string into major, minor, patch, and tweak components + string(REPLACE "." ";" version_components ${PROJECT_VERSION}) + list(GET version_components 0 PROJECT_VERSION_MAJOR) + list(LENGTH version_components version_length) + if(version_length GREATER 1) + list(GET version_components 1 PROJECT_VERSION_MINOR) + endif() + if(version_length GREATER 2) + list(GET version_components 2 PROJECT_VERSION_PATCH) + endif() + if(version_length GREATER 3) + list(GET version_components 3 PROJECT_VERSION_TWEAK) + endif() + + # Store the version string in cmake specified variables to access the version + set(PROJECT_VERSION ${PROJECT_VERSION} PARENT_SCOPE) + set(PROJECT_VERSION_MAJOR ${PROJECT_VERSION_MAJOR} PARENT_SCOPE) + if(PROJECT_VERSION_MINOR) + set(PROJECT_VERSION_MINOR ${PROJECT_VERSION_MINOR} PARENT_SCOPE) + endif() + if(PROJECT_VERSION_PATCH) + set(PROJECT_VERSION_PATCH ${PROJECT_VERSION_PATCH} PARENT_SCOPE) + endif() + if(PROJECT_VERSION_TWEAK) + set(PROJECT_VERSION_TWEAK ${PROJECT_VERSION_TWEAK} PARENT_SCOPE) + endif() + + # Also store the version string in the specified variables for the project_name + set(${project_name}_VERSION ${PROJECT_VERSION} PARENT_SCOPE) + set(${project_name}_VERSION_MAJOR ${PROJECT_VERSION_MAJOR} PARENT_SCOPE) + if(PROJECT_VERSION_MINOR) + set(${project_name}_VERSION_MINOR ${PROJECT_VERSION_MINOR} PARENT_SCOPE) + endif() + if(PROJECT_VERSION_PATCH) + set(${project_name}_VERSION_PATCH ${PROJECT_VERSION_PATCH} PARENT_SCOPE) + endif() + if(PROJECT_VERSION_TWEAK) + set(${project_name}_VERSION_TWEAK ${PROJECT_VERSION_TWEAK} PARENT_SCOPE) endif() endif() - set(${var} "${PROJECT_VER}" PARENT_SCOPE) endfunction() +# +# Get the project version from a version file. This is passed to the idf_build_process call. +# Dependencies are also set here for when the version file changes (if it is used). +# +function(__project_get_revision_from_version_file var) + set(_project_path "${CMAKE_CURRENT_LIST_DIR}") + if(EXISTS "${_project_path}/version.txt") + file(STRINGS "${_project_path}/version.txt" PROJECT_VER) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS "${_project_path}/version.txt") + endif() + set(${var} "${PROJECT_VER}" PARENT_SCOPE) +endfunction() # paths_with_spaces_to_list # @@ -598,7 +656,54 @@ macro(project project_name) set(build_dir ${CMAKE_BINARY_DIR}) endif() - __project_get_revision(project_ver) + # If PROJECT_VER has not been set yet, look for the version from various sources in the following order of priority: + # + # 1. version.txt file in the top level project directory + # 2. From the VERSION argument if passed to the project() macro + # 3. git describe if the project is in a git repository + # 4. Default to 1 if none of the above conditions are true + # + # PS: PROJECT_VER will get overidden later if CONFIG_APP_PROJECT_VER_FROM_CONFIG is defined. + # See components/esp_app_format/CMakeLists.txt. + if(NOT DEFINED PROJECT_VER) + # Read the version information from the version.txt file if it is present + __project_get_revision_from_version_file(project_ver) + + # If the version is not set from the version.txt file, check other sources for the version information + if(NOT project_ver) + # Check if version information was passed to project() via the VERSION argument + set(version_keyword_present FALSE) + foreach(arg ${ARGN}) + if(${arg} STREQUAL "VERSION") + set(version_keyword_present TRUE) + endif() + endforeach() + + if(version_keyword_present) + __parse_and_store_version_arg(${project_name} ${ARGN}) + set(project_ver ${PROJECT_VERSION}) + + # If the project() command is called from the top-level CMakeLists.txt, + # store the version in CMAKE_PROJECT_VERSION. + if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + set(CMAKE_PROJECT_VERSION ${PROJECT_VERSION}) + endif() + else() + # Use git describe to determine the version + git_describe(PROJECT_VER_GIT "${CMAKE_CURRENT_LIST_DIR}") + if(PROJECT_VER_GIT) + set(project_ver ${PROJECT_VER_GIT}) + else() + message(STATUS "Could not use 'git describe' to determine PROJECT_VER.") + # None of sources contain the version information. Default PROJECT_VER to 1. + set(project_ver 1) + endif() #if(PROJECT_VER_GIT) + endif() #if(version_keyword_present) + endif() #if(NOT project_ver) + else() + # PROJECT_VER has been set before calling project(). Copy it into project_ver for idf_build_process() later. + set(project_ver ${PROJECT_VER}) + endif() #if(NOT DEFINED PROJECT_VER) message(STATUS "Building ESP-IDF components for target ${IDF_TARGET}") diff --git a/tools/cmake/scripts/data_file_embed_asm.cmake b/tools/cmake/scripts/data_file_embed_asm.cmake index 5a86d703355..fbfaf3bedbb 100644 --- a/tools/cmake/scripts/data_file_embed_asm.cmake +++ b/tools/cmake/scripts/data_file_embed_asm.cmake @@ -71,7 +71,9 @@ endif() append_line(" */") append_line(".data") +append_line("#if !defined (__APPLE__) && !defined (__linux__)") append_line(".section .rodata.embedded") +append_line("#endif") make_and_append_identifier("${varname}") make_and_append_identifier("_binary_${varname}_start" "for objcopy compatibility") append("${data}") @@ -83,4 +85,4 @@ if(FILE_TYPE STREQUAL "TEXT") else() make_and_append_identifier("${varname}_length") endif() -append_line(".word ${data_len}") +append_line(".long ${data_len}") diff --git a/tools/cmake/toolchain-esp32c5.cmake b/tools/cmake/toolchain-esp32c5.cmake new file mode 100644 index 00000000000..6415daa59b7 --- /dev/null +++ b/tools/cmake/toolchain-esp32c5.cmake @@ -0,0 +1,18 @@ +include($ENV{IDF_PATH}/tools/cmake/utilities.cmake) + +set(CMAKE_SYSTEM_NAME Generic) + +set(CMAKE_C_COMPILER riscv32-esp-elf-gcc) +set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) +set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) +set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) + +remove_duplicated_flags("-march=rv32imac_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) +remove_duplicated_flags("-march=rv32imac_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) + +remove_duplicated_flags("-nostartfiles -march=rv32imac_zicsr_zifencei --specs=nosys.specs \ + ${CMAKE_EXE_LINKER_FLAGS}" + UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) +set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index f81ede10675..e9f4516882c 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -22,6 +22,7 @@ RUN : \ libglib2.0-0 \ libncurses-dev \ libpixman-1-0 \ + libsdl2-2.0-0 \ libslirp0 \ libusb-1.0-0-dev \ make \ @@ -44,12 +45,14 @@ RUN : \ # IDF_CLONE_BRANCH_OR_TAG=release/vX.Y # IDF_CHECKOUT_REF=. # Use IDF_CLONE_SHALLOW=1 to peform shallow clone (i.e. --depth=1 --shallow-submodules) +# Use IDF_CLONE_SHALLOW_DEPTH=X to define the depth if IDF_CLONE_SHALLOW is used (i.e. --depth=X) # Use IDF_INSTALL_TARGETS to install tools only for selected chip targets (CSV) ARG IDF_CLONE_URL=https://github.com/espressif/esp-idf.git ARG IDF_CLONE_BRANCH_OR_TAG=master ARG IDF_CHECKOUT_REF= ARG IDF_CLONE_SHALLOW= +ARG IDF_CLONE_SHALLOW_DEPTH=1 ARG IDF_INSTALL_TARGETS=all ENV IDF_PATH=/opt/esp/idf @@ -65,14 +68,14 @@ RUN if [ "$IDF_INSTALL_TARGETS" = "all" ]; then \ RUN echo IDF_CHECKOUT_REF=$IDF_CHECKOUT_REF IDF_CLONE_BRANCH_OR_TAG=$IDF_CLONE_BRANCH_OR_TAG && \ git clone --recursive \ - ${IDF_CLONE_SHALLOW:+--depth=1 --shallow-submodules} \ + ${IDF_CLONE_SHALLOW:+--depth=${IDF_CLONE_SHALLOW_DEPTH} --shallow-submodules} \ ${IDF_CLONE_BRANCH_OR_TAG:+-b $IDF_CLONE_BRANCH_OR_TAG} \ $IDF_CLONE_URL $IDF_PATH && \ git config --system --add safe.directory $IDF_PATH && \ if [ -n "$IDF_CHECKOUT_REF" ]; then \ cd $IDF_PATH && \ if [ -n "$IDF_CLONE_SHALLOW" ]; then \ - git fetch origin --depth=1 --recurse-submodules ${IDF_CHECKOUT_REF}; \ + git fetch origin --depth=${IDF_CLONE_SHALLOW_DEPTH} --recurse-submodules ${IDF_CHECKOUT_REF}; \ fi && \ git checkout $IDF_CHECKOUT_REF && \ git submodule update --init --recursive; \ diff --git a/tools/docker/entrypoint.sh b/tools/docker/entrypoint.sh index 7cf15f1917e..513b3ba00d2 100755 --- a/tools/docker/entrypoint.sh +++ b/tools/docker/entrypoint.sh @@ -1,6 +1,20 @@ #!/usr/bin/env bash set -e +# IDF_GIT_SAFE_DIR has the same format as system PATH environment variable. +# All path specified in IDF_GIT_SAFE_DIR will be added to user's +# global git config as safe.directory paths. For more information +# see git-config manual page. +if [ -n "${IDF_GIT_SAFE_DIR+x}" ] +then + echo "Adding following directories into git's safe.directory" + echo "$IDF_GIT_SAFE_DIR" | tr ':' '\n' | while read -r dir + do + git config --global --add safe.directory "$dir" + echo " $dir" + done +fi + . $IDF_PATH/export.sh exec "$@" diff --git a/tools/gen_esp_err_to_name.py b/tools/gen_esp_err_to_name.py index c28edc0b4d3..80dcb76c8bc 100755 --- a/tools/gen_esp_err_to_name.py +++ b/tools/gen_esp_err_to_name.py @@ -17,8 +17,7 @@ ignore_files: list = list() # add directories here which should not be parsed, this is a tuple since it will be used with *.startswith() -ignore_dirs = (os.path.join('examples'), - os.path.join('components', 'cmock', 'CMock', 'test'), +ignore_dirs = (os.path.join('components', 'cmock', 'CMock', 'test'), os.path.join('components', 'spi_flash', 'sim')) # macros from here have higher priorities in case of collisions @@ -312,7 +311,7 @@ def main() -> None: include_as_pattern = re.compile(r'\s*//\s*{}: [^"]* "([^"]+)"'.format(os.path.basename(__file__))) define_pattern = re.compile(r'\s*#define\s+(ESP_ERR_|ESP_OK|ESP_FAIL)') - for root, dirnames, filenames in os.walk(idf_path, topdown=True): + for root, dirnames, filenames in os.walk(os.path.join(idf_path, 'components'), topdown=True): # When topdown is True, we can modify the dirnames list in-place # walk() will only recurse into the subdirectories whose names remain in dirnames dirnames[:] = [d for d in dirnames if d not in exclude_search_dirs] diff --git a/tools/gen_soc_caps_kconfig/README.md b/tools/gen_soc_caps_kconfig/README.md index dc1d38ccfa1..2238c47531e 100644 --- a/tools/gen_soc_caps_kconfig/README.md +++ b/tools/gen_soc_caps_kconfig/README.md @@ -4,9 +4,9 @@ The script will automatically run as part of the pre-commit hook if any of the `soc_caps` related files have been modified. -To run it manually from IDF_PATH run: +To run it manually, navigate to `${IDF_PATH}` and execute: - `python tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/*/include/soc/'` + `python tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py -d 'components/soc/*/include/soc/'` The results are `kconfig.soc_caps.in`-files containing the bool/int/hex/string values defined in the `soc_caps.h` file. diff --git a/tools/idf.py b/tools/idf.py index 1ddf6b0c95b..8059c42cca3 100755 --- a/tools/idf.py +++ b/tools/idf.py @@ -441,9 +441,9 @@ def get_command(self, ctx: click.core.Context, name: str) -> Optional[Action]: return None def _print_closing_message(self, args: PropertyDict, actions: _OrderedDictKeysView) -> None: - # print a closing message of some kind - # - if any(t in str(actions) for t in ('flash', 'dfu', 'uf2', 'uf2-app')): + # print a closing message of some kind, + # except if any of the following actions were requested + if any(t in str(actions) for t in ('flash', 'dfu', 'uf2', 'uf2-app', 'qemu')): print('Done') return diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py index 42d5cbe0d9f..6a7835835e7 100644 --- a/tools/idf_py_actions/constants.py +++ b/tools/idf_py_actions/constants.py @@ -33,7 +33,7 @@ URL_TO_DOC = 'https://docs.espressif.com/projects/esp-idf' SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2'] -PREVIEW_TARGETS = ['linux', 'esp32p4'] +PREVIEW_TARGETS = ['linux', 'esp32p4', 'esp32c5'] OPENOCD_TAGET_CONFIG_DEFAULT = '-f interface/ftdi/esp32_devkitj_v1.cfg -f target/{target}.cfg' OPENOCD_TAGET_CONFIG: Dict[str, str] = { @@ -42,5 +42,6 @@ 'esp32c3': '-f board/esp32c3-builtin.cfg', 'esp32s3': '-f board/esp32s3-builtin.cfg', 'esp32c6': '-f board/esp32c6-builtin.cfg', + 'esp32c5': '-f board/esp32c5-builtin.cfg', 'esp32h2': '-f board/esp32h2-builtin.cfg', } diff --git a/tools/idf_py_actions/core_ext.py b/tools/idf_py_actions/core_ext.py index 3466b0e9534..2b1fc96daaf 100644 --- a/tools/idf_py_actions/core_ext.py +++ b/tools/idf_py_actions/core_ext.py @@ -19,7 +19,7 @@ from idf_py_actions.errors import FatalError from idf_py_actions.global_options import global_options from idf_py_actions.tools import (PropertyDict, TargetChoice, ensure_build_directory, generate_hints, get_target, - idf_version, merge_action_lists, run_target, yellow_print) + idf_version, merge_action_lists, print_warning, run_target, yellow_print) def action_extensions(base_actions: Dict, project_path: str) -> Any: @@ -33,7 +33,8 @@ def build_target(target_name: str, ctx: Context, args: PropertyDict) -> None: ensure_build_directory(args, ctx.info_name) run_target(target_name, args, force_progression=GENERATORS[args.generator].get('force_progression', False)) - def size_target(target_name: str, ctx: Context, args: PropertyDict, output_format: str, output_file: str) -> None: + def size_target(target_name: str, ctx: Context, args: PropertyDict, output_format: str, + output_file: str, legacy: bool) -> None: """ Builds the app and then executes a size-related target passed in 'target_name'. `tool_error_handler` handler is used to suppress errors during the build, @@ -44,6 +45,27 @@ def tool_error_handler(e: int, stdout: str, stderr: str) -> None: for hint in generate_hints(stdout, stderr): yellow_print(hint) + if not legacy and output_format != 'json': + try: + import esp_idf_size.ng # noqa: F401 + except ImportError: + print_warning('WARNING: refactored esp-idf-size not installed, using legacy mode') + legacy = True + else: + # Legacy mode is used only when explicitly requested with --legacy option + # or when "--format json" option is specified. Here we enable the + # esp-idf-size refactored version with ESP_IDF_SIZE_NG env. variable. + os.environ['ESP_IDF_SIZE_NG'] = '1' + # ESP_IDF_SIZE_FORCE_TERMINAL is set to force terminal control codes even + # if stdout is not attached to terminal. This is set to pass color codes + # from esp-idf-size to idf.py. + os.environ['ESP_IDF_SIZE_FORCE_TERMINAL'] = '1' + + if legacy and output_format in ['json2', 'raw', 'tree']: + # These formats are supported in new version only. + # We would get error from the esp-idf-size anyway, so print error early. + raise FatalError(f'Legacy esp-idf-size does not support {output_format} format') + os.environ['SIZE_OUTPUT_FORMAT'] = output_format if output_file: os.environ['SIZE_OUTPUT_FILE'] = os.path.abspath(output_file) @@ -354,9 +376,13 @@ def help_and_exit(action: str, ctx: Context, param: List, json_option: bool, add # if the user explicitly specified the format or not. If the format is not specified, then # the legacy OUTPUT_JSON CMake variable will be taken into account. size_options = [{'names': ['--format', 'output_format'], - 'type': click.Choice(['default', 'text', 'csv', 'json']), - 'help': 'Specify output format: text (same as "default"), csv or json.', + 'type': click.Choice(['default', 'text', 'csv', 'json', 'json2', 'tree', 'raw']), + 'help': 'Specify output format: text (same as "default"), csv, json, json2, tree or raw.', 'default': 'default'}, + {'names': ['--legacy', '-l'], + 'is_flag': True, + 'default': os.environ.get('ESP_IDF_SIZE_LEGACY', '0') == '1', + 'help': 'Use legacy esp-idf-size version'}, {'names': ['--output-file', 'output_file'], 'help': 'Print output to the specified file instead of to the standard output'}] diff --git a/tools/idf_py_actions/debug_ext.py b/tools/idf_py_actions/debug_ext.py index db7083c4696..5e4974beb70 100644 --- a/tools/idf_py_actions/debug_ext.py +++ b/tools/idf_py_actions/debug_ext.py @@ -9,7 +9,6 @@ import sys import threading import time -from base64 import b64decode from textwrap import indent from threading import Thread from typing import Any, Dict, List, Optional, Union @@ -159,7 +158,6 @@ def _get_espcoredump_instance(ctx: Context, coredump_to_flash = coredump_to_flash_config.rstrip().endswith('y') if coredump_to_flash_config else False prog = os.path.join(project_desc['build_dir'], project_desc['app_elf']) - args.port = args.port or get_default_serial_port() espcoredump_kwargs = dict() @@ -173,12 +171,10 @@ def _get_espcoredump_instance(ctx: Context, if extra_gdbinit_file: espcoredump_kwargs['extra_gdbinit_file'] = extra_gdbinit_file - core_format = None - if core: espcoredump_kwargs['core'] = core + espcoredump_kwargs['core_format'] = 'auto' espcoredump_kwargs['chip'] = get_sdkconfig_value(project_desc['config_file'], 'CONFIG_IDF_TARGET') - core_format = get_core_file_format(core) elif coredump_to_flash: # If the core dump is read from flash, we don't need to specify the --core-format argument at all. # The format will be determined automatically @@ -192,9 +188,6 @@ def _get_espcoredump_instance(ctx: Context, espcoredump_kwargs['parttable_off'] = get_sdkconfig_value(project_desc['config_file'], 'CONFIG_PARTITION_TABLE_OFFSET') - if core_format: - espcoredump_kwargs['core_format'] = core_format - if save_core: espcoredump_kwargs['save_core'] = save_core @@ -213,34 +206,6 @@ def _get_espcoredump_instance(ctx: Context, raise return coredump - def get_core_file_format(core_file: str) -> str: - bin_v1 = 1 - bin_v2 = 2 - elf_crc32 = 256 - elf_sha256 = 257 - - with open(core_file, 'rb') as f: - coredump_bytes = f.read(16) - - if coredump_bytes.startswith(b'\x7fELF'): - return 'elf' - - core_version = int.from_bytes(coredump_bytes[4:7], 'little') - if core_version in [bin_v1, bin_v2, elf_crc32, elf_sha256]: - # esp-coredump will determine automatically the core format (ELF or BIN) - return 'raw' - with open(core_file) as c: - coredump_str = c.read() - try: - b64decode(coredump_str) - except Exception: - print('The format of the provided core-file is not recognized. ' - 'Please ensure that the core-format matches one of the following: ELF (“elf”), ' - 'raw (raw) or base64-encoded (b64) binary') - sys.exit(1) - else: - return 'b64' - def is_gdb_with_python(gdb: str) -> bool: # execute simple python command to check is it supported return subprocess.run([gdb, '--batch-silent', '--ex', 'python import os'], @@ -308,7 +273,7 @@ def generate_gdbinit_files(gdb: str, gdbinit: Optional[str], project_desc: Dict[ raise FatalError('ELF file not found. You need to build & flash the project before running debug targets') # Recreate empty 'gdbinit' directory - gdbinit_dir = os.path.join(project_desc['build_dir'], 'gdbinit') + gdbinit_dir = '/'.join([project_desc['build_dir'], 'gdbinit']) if os.path.isfile(gdbinit_dir): os.remove(gdbinit_dir) elif os.path.isdir(gdbinit_dir): @@ -316,7 +281,7 @@ def generate_gdbinit_files(gdb: str, gdbinit: Optional[str], project_desc: Dict[ os.mkdir(gdbinit_dir) # Prepare gdbinit for Python GDB extensions import - py_extensions = os.path.join(gdbinit_dir, 'py_extensions') + py_extensions = '/'.join([gdbinit_dir, 'py_extensions']) with open(py_extensions, 'w') as f: if is_gdb_with_python(gdb): f.write(GDBINIT_PYTHON_TEMPLATE.format(sys_path=sys.path)) @@ -324,7 +289,7 @@ def generate_gdbinit_files(gdb: str, gdbinit: Optional[str], project_desc: Dict[ f.write(GDBINIT_PYTHON_NOT_SUPPORTED) # Prepare gdbinit for related ELFs symbols load - symbols = os.path.join(gdbinit_dir, 'symbols') + symbols = '/'.join([gdbinit_dir, 'symbols']) with open(symbols, 'w') as f: boot_elf = get_normalized_path(project_desc['bootloader_elf']) if 'bootloader_elf' in project_desc else None if boot_elf and os.path.exists(boot_elf): @@ -336,7 +301,7 @@ def generate_gdbinit_files(gdb: str, gdbinit: Optional[str], project_desc: Dict[ # Generate the gdbinit for target connect if no custom gdbinit is present if not gdbinit: - gdbinit = os.path.join(gdbinit_dir, 'connect') + gdbinit = '/'.join([gdbinit_dir, 'connect']) with open(gdbinit, 'w') as f: f.write(GDBINIT_CONNECT) diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index 05585eed9bf..9cb3dd3845d 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -55,8 +55,8 @@ hint_variables: ['esp_spiram_get_chip_size and esp_spiram_get_size', 'esp_psram_get_size()'] - - re: "error: implicit declaration of function 'esp_secure_boot_verify_sbv2_signature_block|esp_secure_boot_verify_rsa_signature_block'" - hint: "'esp_secure_boot_verify_sbv2_signature_block()' and 'esp_secure_boot_verify_rsa_signature_block()' and have been made private and are no longer available." + re: "error: implicit declaration of function 'esp_secure_boot_verify_rsa_signature_block'" + hint: "'esp_secure_boot_verify_rsa_signature_block()' has been made private and is no longer available." - re: "error: implicit declaration of function '{}'" diff --git a/tools/idf_py_actions/qemu_ext.py b/tools/idf_py_actions/qemu_ext.py new file mode 100644 index 00000000000..27797e087a8 --- /dev/null +++ b/tools/idf_py_actions/qemu_ext.py @@ -0,0 +1,273 @@ +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import atexit +import binascii +import json +import os +import shutil +import socket +import subprocess +import sys +import time +from dataclasses import dataclass +from typing import Any, Dict, List + +from click.core import Context + +try: + from idf_py_actions.tools import PropertyDict, ensure_build_directory, red_print, yellow_print +except ImportError: + PropertyDict = Any + +from idf_py_actions.tools import get_sdkconfig_value + +# Some ports used by QEMU. Could be made configurable, if necessary. +# Note that port 3333 is also assumed by gdb extension. +QEMU_PORT_SERIAL = 5555 +PYSERIAL_PORT = f'socket://localhost:{QEMU_PORT_SERIAL}' +QEMU_PORT_GDB = 3333 +GBD_PORT = f'localhost:{QEMU_PORT_GDB}' + + +@dataclass +class QemuTarget: + """ + Target-specific information related to QEMU. + """ + target: str # chip name, e.g. esp32, esp32c3 + qemu_prog: str # name of the QEMU binary, e.g. qemu-system-xtensa + install_package: str # name of the tools.json package from which to install the QEMU binary + qemu_args: str # chip-specific arguments to pass to QEMU + default_efuse: bytes # default efuse values for the target + + +# To generate the default eFuse values, follow the instructions in +# https://github.com/espressif/esp-toolchain-docs/blob/main/qemu/esp32/README.md#using-esptoolpy-and-espefusepy-to-interact-with-qemu +# and burn the eFuses which should be set by default. Then take the binary file, convert it to hex, and paste it here. +QEMU_TARGETS: Dict[str, QemuTarget] = { + 'esp32': QemuTarget( + 'esp32', + 'qemu-system-xtensa', + 'qemu-xtensa', + '-M esp32 -m 4M', + # Chip revision 3 + binascii.unhexlify( + '00000000000000000000000000800000000000000000100000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000')), + + 'esp32c3': QemuTarget( + 'esp32c3', + 'qemu-system-riscv32', + 'qemu-riscv32', + '-M esp32c3', + # Chip revision 0.3 + binascii.unhexlify( + '00000000000000000000000000000000000000000000000000000000000000000000000000000c00' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '00000000000000000000000000000000000000000000000000000000000000000000000000000000' + '000000000000000000000000000000000000000000000000')), +} + + +class QemuTaskRunOptions: + """ + Some options related to QEMU execution, which depend on the presence of other tasks: gdb and monitor. + """ + def __init__(self) -> None: + self.bg_mode = False + self.wait_for_gdb = False + self.wait_for_monitor = False + + +def wait_for_socket(port: int, timeout_sec: float = 10.0) -> None: + """ + Helper function, waits for a socket to be open. + Used to detect that QEMU has started up and ready to receive connections. + """ + start_time = time.time() + end_time = start_time + timeout_sec + while time.time() < end_time: + try: + with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: + s.connect(('localhost', port)) + return # connection successful + except OSError: + time.sleep(0.1) + continue + red_print(f'Timed out waiting for port {port} to be open') + raise SystemExit(1) + + +def action_extensions(base_actions: Dict, project_path: str) -> Dict: + # Shared state between "global_callback" and "qemu" action. + # Stores options which depend on the presence of other tasks. + options = QemuTaskRunOptions() + + def global_callback(ctx: Context, global_args: Dict, tasks: List) -> None: + # This callback lets us customize QEMU launch arguments depending on the presence of other tasks. + def have_task(name: str) -> bool: + return any(task.name == name for task in tasks) + + have_qemu = have_task('qemu') + have_gdb = have_task('gdb') + have_monitor = have_task('monitor') + + if have_qemu: + if have_gdb and have_monitor: + red_print('Cannot run qemu with both gdb and monitor in the same terminal') + raise SystemExit(1) + if have_gdb: + options.wait_for_gdb = True + options.bg_mode = True + if have_monitor: + options.wait_for_monitor = True + options.bg_mode = True + yellow_print(f'Running qemu on {PYSERIAL_PORT}') + global_args['port'] = PYSERIAL_PORT + + def _get_project_desc(args: PropertyDict, ctx: Context) -> Any: + desc_path = os.path.join(args.build_dir, 'project_description.json') + if not os.path.exists(desc_path): + ensure_build_directory(args, ctx.info_name) + with open(desc_path, 'r') as f: + project_desc = json.load(f) + return project_desc + + def qemu(action: str, ctx: Context, args: PropertyDict, qemu_extra_args: str, gdb: bool, graphics: bool) -> None: + project_desc = _get_project_desc(args, ctx) + + # Determine the target and check if we have the necessary QEMU binary + target = project_desc['target'] + qemu_target_info = QEMU_TARGETS.get(target) + if not qemu_target_info: + red_print(f'QEMU is not supported for target {target}') + raise SystemExit(1) + if not shutil.which(qemu_target_info.qemu_prog): + red_print(f'{qemu_target_info.qemu_prog} is not installed. Please install it using ' + f'"python $IDF_PATH/tools/idf_tools.py install {qemu_target_info.install_package}" ' + 'or build it from source if the pre-built version is not available for your platform.') + raise SystemExit(1) + + # Generate flash image and efuse image + flash_size = get_sdkconfig_value(project_desc['config_file'], 'CONFIG_ESPTOOLPY_FLASHSIZE') + bin_path = os.path.join(args.build_dir, 'flash_image.bin') + yellow_print(f'Generating flash image: {bin_path}') + subprocess.check_call([ + sys.executable, '-m', 'esptool', f'--chip={target}', 'merge_bin', f'--output={bin_path}', + f'--fill-flash-size={flash_size}', '@flash_args'], cwd=args.build_dir) + + efuse_bin_path = os.path.join(args.build_dir, 'qemu_efuse.bin') + yellow_print(f'Generating efuse image: {efuse_bin_path}') + with open(efuse_bin_path, 'wb') as f: + f.write(qemu_target_info.default_efuse) + + # Prepare QEMU launch arguments + qemu_args = [qemu_target_info.qemu_prog] + qemu_args += qemu_target_info.qemu_args.split(' ') + qemu_args += [ + '-drive', f'file={bin_path},if=mtd,format=raw', + '-drive', f'file={efuse_bin_path},if=none,format=raw,id=efuse', '-global', f'driver=nvram.{target}.efuse,property=drive,value=efuse', + '-global', f'driver=timer.{target}.timg,property=wdt_disable,value=true', + ] + if '-nic' not in qemu_extra_args: + qemu_args += ['-nic', 'user,model=open_eth'] + + if options.wait_for_gdb or gdb: + qemu_args += ['-gdb', f'tcp::{QEMU_PORT_GDB}', '-S'] + + if qemu_extra_args: + qemu_args += qemu_extra_args.split(' ') + + if graphics: + qemu_args += ['-display', 'sdl'] + else: + qemu_args += ['-nographic'] + + # Launch QEMU! + if not options.bg_mode: + qemu_args += ['-serial', 'mon:stdio'] + yellow_print('Running qemu (fg): ' + ' '.join(qemu_args)) + subprocess.run(qemu_args) + else: + if options.wait_for_monitor: + qemu_args += ['-serial', f'tcp::{QEMU_PORT_SERIAL},server'] + else: + qemu_args += ['-serial', f'tcp::{QEMU_PORT_SERIAL},server,nowait'] + + yellow_print('Running qemu (bg): ' + ' '.join(qemu_args)) + qemu_proc = subprocess.Popen(qemu_args, stdout=subprocess.PIPE, stderr=subprocess.PIPE, stdin=subprocess.PIPE) + wait_for_socket(QEMU_PORT_SERIAL) + + def cleanup_qemu() -> None: + if qemu_proc: + qemu_proc.terminate() + qemu_proc.wait() + atexit.register(cleanup_qemu) + if qemu_proc.poll() is not None: + yellow_print('QEMU exited with error') + if qemu_proc.stderr is not None: + yellow_print('Stderr output was:') + yellow_print(qemu_proc.stderr.read().decode('utf-8')) + sys.exit(1) + + if gdb and not options.wait_for_gdb: + yellow_print('Waiting for GDB to connect. You can now run "idf.py gdb" in another terminal window.') + + qemu_actions = { + 'global_action_callbacks': [global_callback], + 'actions': { + 'qemu': { + 'callback': qemu, + 'help': 'Run QEMU.', + 'dependencies': ['all'], + 'options': [ + { + 'names': ['--qemu-extra-args'], + 'help': 'Extra arguments to pass to QEMU', + 'hidden': False, + 'is_flag': False, + 'default': '', + }, + { + 'names': ['-d', '--gdb'], + 'help': ('Wait for gdb to connect. ' + 'Use this option to run "idf.py qemu --gdb monitor" in one terminal window ' + 'and "idf.py gdb" in another. The program will start running when gdb connects.'), + 'is_flag': True, + 'default': False, + }, + { + 'names': ['-g', '--graphics'], + 'help': 'Enable graphical window', + 'is_flag': True, + 'default': False, + } + ] + } + } + } + return qemu_actions diff --git a/tools/idf_py_actions/tools.py b/tools/idf_py_actions/tools.py index c90da90fa9d..246f560abb1 100644 --- a/tools/idf_py_actions/tools.py +++ b/tools/idf_py_actions/tools.py @@ -626,7 +626,7 @@ def ensure_build_directory(args: 'PropertyDict', prog_name: str, always_run_cmak try: python = cache['PYTHON'] - if python != sys.executable: + if os.path.normcase(python) != os.path.normcase(sys.executable): raise FatalError( "'{}' is currently active in the environment while the project was configured with '{}'. " "Run '{} fullclean' to start again.".format(sys.executable, python, prog_name)) diff --git a/tools/idf_size.py b/tools/idf_size.py index 322d527f6f0..342340002ca 100755 --- a/tools/idf_size.py +++ b/tools/idf_size.py @@ -5,8 +5,30 @@ # SPDX-License-Identifier: Apache-2.0 # +import argparse +import os import subprocess import sys if __name__ == '__main__': - sys.exit(subprocess.run([sys.executable, '-m', 'esp_idf_size'] + sys.argv[1:]).returncode) + parser = argparse.ArgumentParser() + parser.add_argument('--format') + parser.add_argument('-l', '--legacy', action='store_true', default=os.environ.get('ESP_IDF_SIZE_LEGACY', '0') == '1') + args, rest = parser.parse_known_args() + + if not args.legacy and args.format != 'json': + try: + import esp_idf_size.ng # noqa: F401 + except ImportError: + print('warning: refactored esp-idf-size not installed, using legacy mode', file=sys.stderr) + args.legacy = True + else: + os.environ['ESP_IDF_SIZE_NG'] = '1' + + if args.legacy and args.format in ['json2', 'raw', 'tree']: + sys.exit(f'Legacy esp-idf-size does not support {args.format} format') + + if args.format is not None: + rest = ['--format', args.format] + rest + + sys.exit(subprocess.run([sys.executable, '-m', 'esp_idf_size'] + rest).returncode) diff --git a/tools/idf_tools.py b/tools/idf_tools.py index f55a8811f1f..42bbdb0ba1c 100755 --- a/tools/idf_tools.py +++ b/tools/idf_tools.py @@ -1700,6 +1700,94 @@ def action_check(args): # type: ignore raise SystemExit(1) +# The following functions are used in process_tool which is a part of the action_export. +def handle_recommended_version_to_use( + tool, + tool_name, + version_to_use, + prefer_system_hint, +): # type: (IDFTool, str, str, str) -> Tuple[list, dict] + tool_export_paths = tool.get_export_paths(version_to_use) + tool_export_vars = tool.get_export_vars(version_to_use) + if tool.version_in_path and tool.version_in_path not in tool.versions: + info('Not using an unsupported version of tool {} found in PATH: {}.'.format( + tool.name, tool.version_in_path) + prefer_system_hint, f=sys.stderr) + return tool_export_paths, tool_export_vars + + +def handle_supported_or_deprecated_version(tool, tool_name): # type: (IDFTool, str) -> None + version_obj: IDFToolVersion = tool.versions[tool.version_in_path] # type: ignore + if version_obj.status == IDFToolVersion.STATUS_SUPPORTED: + info('Using a supported version of tool {} found in PATH: {}.'.format(tool_name, tool.version_in_path), + f=sys.stderr) + info('However the recommended version is {}.'.format(tool.get_recommended_version()), + f=sys.stderr) + elif version_obj.status == IDFToolVersion.STATUS_DEPRECATED: + warn('using a deprecated version of tool {} found in PATH: {}'.format(tool_name, tool.version_in_path)) + + +def handle_missing_versions( + tool, + tool_name, + install_cmd, + prefer_system_hint +): # type: (IDFTool, str, str, str) -> None + fatal('tool {} has no installed versions. Please run \'{}\' to install it.'.format( + tool.name, install_cmd)) + if tool.version_in_path and tool.version_in_path not in tool.versions: + info('An unsupported version of tool {} was found in PATH: {}. '.format(tool_name, tool.version_in_path) + + prefer_system_hint, f=sys.stderr) + + +def process_tool( + tool, + tool_name, + args, + install_cmd, + prefer_system_hint +): # type: (IDFTool, str, argparse.Namespace, str, str) -> Tuple[list, dict, bool] + tool_found: bool = True + tool_export_paths: List[str] = [] + tool_export_vars: Dict[str, str] = {} + + tool.find_installed_versions() + recommended_version_to_use = tool.get_preferred_installed_version() + + if not tool.is_executable and recommended_version_to_use: + tool_export_vars = tool.get_export_vars(recommended_version_to_use) + return tool_export_paths, tool_export_vars, tool_found + + if recommended_version_to_use and not args.prefer_system: + tool_export_paths, tool_export_vars = handle_recommended_version_to_use( + tool, tool_name, recommended_version_to_use, prefer_system_hint + ) + return tool_export_paths, tool_export_vars, tool_found + + if tool.version_in_path: + if tool.version_in_path not in tool.versions: + # unsupported version + if args.prefer_system: # type: ignore + warn('using an unsupported version of tool {} found in PATH: {}'.format( + tool.name, tool.version_in_path)) + return tool_export_paths, tool_export_vars, tool_found + else: + # unsupported version in path + pass + else: + # supported/deprecated version in PATH, use it + handle_supported_or_deprecated_version(tool, tool_name) + return tool_export_paths, tool_export_vars, tool_found + + if not tool.versions_installed: + if tool.get_install_type() == IDFTool.INSTALL_ALWAYS: + handle_missing_versions(tool, tool_name, install_cmd, prefer_system_hint) + tool_found = False + # If a tool found, but it is optional and does not have versions installed, use whatever is in PATH. + return tool_export_paths, tool_export_vars, tool_found + + return tool_export_paths, tool_export_vars, tool_found + + def action_export(args): # type: ignore if args.deactivate and different_idf_detected(): deactivate_statement(args) @@ -1719,58 +1807,10 @@ def action_export(args): # type: ignore for name, tool in tools_info.items(): if tool.get_install_type() == IDFTool.INSTALL_NEVER: continue - tool.find_installed_versions() - version_to_use = tool.get_preferred_installed_version() - - if not tool.is_executable and version_to_use: - tool_export_vars = tool.get_export_vars(version_to_use) - export_vars = {**export_vars, **tool_export_vars} - continue - - if tool.version_in_path: - if tool.version_in_path not in tool.versions: - # unsupported version - if args.prefer_system: # type: ignore - warn('using an unsupported version of tool {} found in PATH: {}'.format( - tool.name, tool.version_in_path)) - continue - else: - # unsupported version in path - pass - else: - # supported/deprecated version in PATH, use it - version_obj = tool.versions[tool.version_in_path] - if version_obj.status == IDFToolVersion.STATUS_SUPPORTED: - info('Using a supported version of tool {} found in PATH: {}.'.format(name, tool.version_in_path), - f=sys.stderr) - info('However the recommended version is {}.'.format(tool.get_recommended_version()), - f=sys.stderr) - elif version_obj.status == IDFToolVersion.STATUS_DEPRECATED: - warn('using a deprecated version of tool {} found in PATH: {}'.format(name, tool.version_in_path)) - continue - - if not tool.versions_installed: - if tool.get_install_type() == IDFTool.INSTALL_ALWAYS: - all_tools_found = False - fatal('tool {} has no installed versions. Please run \'{}\' to install it.'.format( - tool.name, install_cmd)) - if tool.version_in_path and tool.version_in_path not in tool.versions: - info('An unsupported version of tool {} was found in PATH: {}. '.format(name, tool.version_in_path) + - prefer_system_hint, f=sys.stderr) - continue - else: - # tool is optional, and does not have versions installed - # use whatever is available in PATH - continue - - if tool.version_in_path and tool.version_in_path not in tool.versions: - info('Not using an unsupported version of tool {} found in PATH: {}.'.format( - tool.name, tool.version_in_path) + prefer_system_hint, f=sys.stderr) - - export_paths = tool.get_export_paths(version_to_use) - if export_paths: - paths_to_export += export_paths - tool_export_vars = tool.get_export_vars(version_to_use) + tool_export_paths, tool_export_vars, tool_found = process_tool(tool, name, args, install_cmd, prefer_system_hint) + if not tool_found: + all_tools_found = False + paths_to_export += tool_export_paths export_vars = {**export_vars, **tool_export_vars} current_path = os.getenv('PATH') diff --git a/tools/ldgen/samples/sdkconfig b/tools/ldgen/samples/sdkconfig index a43ae9db5d3..602129ddc28 100644 --- a/tools/ldgen/samples/sdkconfig +++ b/tools/ldgen/samples/sdkconfig @@ -184,7 +184,7 @@ CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_RTC_CLK_SRC_EXT_CRYS= CONFIG_RTC_CLK_CAL_CYCLES=1024 CONFIG_RTC_XTAL_BOOTSTRAP_CYCLES=100 -CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=2000 CONFIG_XTAL_FREQ_40=y CONFIG_XTAL_FREQ_26= CONFIG_XTAL_FREQ_AUTO= diff --git a/tools/mass_mfg/mfg_gen.py b/tools/mass_mfg/mfg_gen.py index 5f05a7b1a61..b3a9e0b1884 100644 --- a/tools/mass_mfg/mfg_gen.py +++ b/tools/mass_mfg/mfg_gen.py @@ -1,6 +1,6 @@ #!/usr/bin/env python # -# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # @@ -8,16 +8,9 @@ import csv import distutils.dir_util import os -import sys from itertools import zip_longest -try: - idf_path = os.environ['IDF_PATH'] - sys.path.insert(0, idf_path + '/components/nvs_flash/nvs_partition_generator/') - import nvs_partition_gen -except Exception as e: - print(e) - sys.exit('Please check IDF_PATH') +import esp_idf_nvs_partition_gen.nvs_partition_gen as nvs_partition_gen def create_temp_files(args): diff --git a/tools/mocks/driver/CMakeLists.txt b/tools/mocks/driver/CMakeLists.txt index 5733e1b34c8..0a5490f7436 100644 --- a/tools/mocks/driver/CMakeLists.txt +++ b/tools/mocks/driver/CMakeLists.txt @@ -7,27 +7,26 @@ idf_component_get_property(original_driver_dir driver COMPONENT_OVERRIDEN_DIR) set(include_dirs "${IDF_PATH}/components/esp_driver_gpio/include/driver" "${IDF_PATH}/components/esp_driver_gpio/include" + "${IDF_PATH}/components/esp_driver_spi/include/driver" + "${IDF_PATH}/components/esp_driver_spi/include" + "${IDF_PATH}/components/esp_driver_rmt/include/driver" + "${IDF_PATH}/components/esp_driver_rmt/include" "${original_driver_dir}/i2c/include/driver" - "${original_driver_dir}/spi/include/driver" - "${original_driver_dir}/rmt/include/driver" "${original_driver_dir}/usb_serial_jtag/include/driver" "${original_driver_dir}/i2c/include" - "${original_driver_dir}/spi/include" - "${original_driver_dir}/rmt/include" - "${original_driver_dir}/usb_serial_jtag/include" - "${CMAKE_CURRENT_SOURCE_DIR}/../hal/include") + "${original_driver_dir}/usb_serial_jtag/include") +# Note: "hal" and "soc" are only required for corresponding header files and their definitions +# here, they don't provide functionality when built for running on the host. idf_component_mock(INCLUDE_DIRS ${include_dirs} - REQUIRES freertos + REQUIRES freertos hal soc MOCK_HEADER_FILES ${IDF_PATH}/components/esp_driver_gpio/include/driver/gpio.h - ${original_driver_dir}/spi/include/driver/spi_master.h - ${original_driver_dir}/spi/include/driver/spi_common.h + ${IDF_PATH}/components/esp_driver_spi/include/driver/spi_master.h + ${IDF_PATH}/components/esp_driver_spi/include/driver/spi_common.h + ${IDF_PATH}/components/esp_driver_rmt/include/driver/rmt_rx.h + ${IDF_PATH}/components/esp_driver_rmt/include/driver/rmt_tx.h + ${IDF_PATH}/components/esp_driver_rmt/include/driver/rmt_common.h + ${IDF_PATH}/components/esp_driver_rmt/include/driver/rmt_encoder.h ${original_driver_dir}/i2c/include/driver/i2c.h - ${original_driver_dir}/rmt/include/driver/rmt_rx.h - ${original_driver_dir}/rmt/include/driver/rmt_tx.h - ${original_driver_dir}/rmt/include/driver/rmt_common.h - ${original_driver_dir}/rmt/include/driver/rmt_encoder.h ${original_driver_dir}/usb_serial_jtag/include/driver/usb_serial_jtag.h) - -target_compile_definitions(${COMPONENT_LIB} PUBLIC SOC_I2C_NUM=2) diff --git a/tools/mocks/esp_wifi/global_symbols_mock.c b/tools/mocks/esp_wifi/global_symbols_mock.c index aa515dfec51..3a00a433177 100644 --- a/tools/mocks/esp_wifi/global_symbols_mock.c +++ b/tools/mocks/esp_wifi/global_symbols_mock.c @@ -13,5 +13,3 @@ const wpa_crypto_funcs_t g_wifi_default_wpa_crypto_funcs = { }; wifi_osi_funcs_t g_wifi_osi_funcs = { }; - -uint64_t g_wifi_feature_caps = 0; diff --git a/tools/mocks/hal/include/hal/i2c_types.h b/tools/mocks/hal/include/hal/i2c_types.h deleted file mode 100644 index ad76ed43e70..00000000000 --- a/tools/mocks/hal/include/hal/i2c_types.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * NOTE: this is not the original header file from the hal component. It is a stripped-down copy to support mocking. - */ - -#pragma once - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief I2C port number, can be I2C_NUM_0 ~ (I2C_NUM_MAX-1). - */ -typedef enum { - I2C_NUM_0 = 0, /*!< I2C port 0 */ -#if SOC_I2C_NUM >= 2 - I2C_NUM_1, /*!< I2C port 1 */ -#endif - I2C_NUM_MAX, /*!< I2C port max */ -} i2c_port_t; - -typedef enum{ - I2C_MODE_SLAVE = 0, /*!< I2C slave mode */ - I2C_MODE_MASTER, /*!< I2C master mode */ - I2C_MODE_MAX, -} i2c_mode_t; - -typedef enum { - I2C_MASTER_WRITE = 0, /*!< I2C write data */ - I2C_MASTER_READ, /*!< I2C read data */ -} i2c_rw_t; - -typedef enum { - I2C_DATA_MODE_MSB_FIRST = 0, /*!< I2C data msb first */ - I2C_DATA_MODE_LSB_FIRST = 1, /*!< I2C data lsb first */ - I2C_DATA_MODE_MAX -} i2c_trans_mode_t; - -typedef enum { - I2C_ADDR_BIT_7 = 0, /*!< I2C 7bit address for slave mode */ - I2C_ADDR_BIT_10, /*!< I2C 10bit address for slave mode */ - I2C_ADDR_BIT_MAX, -} i2c_addr_mode_t; - -typedef enum { - I2C_MASTER_ACK = 0x0, /*!< I2C ack for each byte read */ - I2C_MASTER_NACK = 0x1, /*!< I2C nack for each byte read */ - I2C_MASTER_LAST_NACK = 0x2, /*!< I2C nack for the last byte*/ - I2C_MASTER_ACK_MAX, -} i2c_ack_type_t; - -#ifdef __cplusplus -} -#endif diff --git a/tools/mocks/hal/include/hal/rmt_types.h b/tools/mocks/hal/include/hal/rmt_types.h deleted file mode 100644 index 12df5fa1c80..00000000000 --- a/tools/mocks/hal/include/hal/rmt_types.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * NOTE: this is not the original header file from the hal component. It is a stripped-down copy to support mocking. - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -typedef int rmt_clock_source_t; - -typedef union { - struct { - unsigned int duration0 : 15; /*!< Duration of level0 */ - unsigned int level0 : 1; /*!< Level of the first part */ - unsigned int duration1 : 15; /*!< Duration of level1 */ - unsigned int level1 : 1; /*!< Level of the second part */ - }; - unsigned int val; /*!< Equivalent unsigned value for the RMT symbol */ -} rmt_symbol_word_t; - -#ifdef __cplusplus -} -#endif diff --git a/tools/mocks/hal/include/hal/spi_types.h b/tools/mocks/hal/include/hal/spi_types.h deleted file mode 100644 index 42b59406f7d..00000000000 --- a/tools/mocks/hal/include/hal/spi_types.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * NOTE: this is not the original header file from the hal component. It is a stripped-down copy to support mocking. - */ - -#pragma once - -/** - * @brief Enum with the three SPI peripherals that are software-accessible in it - */ -typedef enum { -// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 - SPI1_HOST=0, ///< SPI1 - SPI2_HOST=1, ///< SPI2 - SPI3_HOST=2, ///< SPI3 - SPI_HOST_MAX=3, ///< invalid host value -} spi_host_device_t; - -/** - * @brief Type of SPI clock source. - */ -typedef enum { - SPI_CLK_SRC_DEFAULT, /*!< Select PLL as SPI source clock */ - SPI_CLK_SRC_PLL_F40M, /*!< Select PLL as SPI source clock */ - SPI_CLK_SRC_PLL_F80M, /*!< Select PLL as SPI source clock */ - SPI_CLK_SRC_APB, /*!< Select APB as SPI source clock */ - SPI_CLK_SRC_XTAL, /*!< Select XTAL as SPI source clock */ - SPI_CLK_SRC_RC_FAST, /*!< Select RC_FAST as SPI source clock */ -} spi_clock_source_t; diff --git a/tools/mocks/soc/include/soc/gpio_pins.h b/tools/mocks/soc/include/soc/gpio_pins.h deleted file mode 100644 index f2a04970867..00000000000 --- a/tools/mocks/soc/include/soc/gpio_pins.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * NOTE: this is not the original header file from the soc component. It is a stripped-down copy to support mocking. - */ diff --git a/tools/mocks/tcp_transport/mock/mock_config.yaml b/tools/mocks/tcp_transport/mock/mock_config.yaml index fcf2722bc1d..0d7150e2017 100644 --- a/tools/mocks/tcp_transport/mock/mock_config.yaml +++ b/tools/mocks/tcp_transport/mock/mock_config.yaml @@ -7,3 +7,5 @@ - ignore_arg - callback :when_ptr: :compare_ptr + :strippables: + - '(?:esp_transport_ssl_session_ticket_operation\s*\(+.*?\)+)' diff --git a/tools/requirements/requirements.core.txt b/tools/requirements/requirements.core.txt index d1d4c930c22..e1bac0b056c 100644 --- a/tools/requirements/requirements.core.txt +++ b/tools/requirements/requirements.core.txt @@ -14,9 +14,11 @@ esp-coredump esptool esp-idf-kconfig esp-idf-monitor +esp-idf-nvs-partition-gen esp-idf-size esp-idf-panic-decoder pyclang +construct # gdb extensions dependencies freertos_gdb diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml index faef23a9e21..1d1eb33bac2 100644 --- a/tools/test_apps/.build-test-rules.yml +++ b/tools/test_apps/.build-test-rules.yml @@ -87,6 +87,20 @@ tools/test_apps/storage/partition_table_readonly: - fatfs - spiffs +tools/test_apps/storage/sdmmc_console: + disable: + - if: IDF_TARGET in ["esp32h2"] + temporary: true + reason: Console component not supported on H2 yet + disable_test: + - if: IDF_TARGET not in ["esp32", "esp32s2", "esp32c3"] + temporary: true + reason: No runners for other targets yet + depends_components: + - sdmmc + - esp_driver_sdmmc + - esp_driver_sdspi + tools/test_apps/system/bootloader_sections: disable: - if: IDF_TARGET == "esp32c2" @@ -101,9 +115,7 @@ tools/test_apps/system/build_test: - if: CONFIG_NAME == "no_rvfplib" and ESP_ROM_HAS_RVFPLIB != 1 - if: CONFIG_NAME == "usb_serial_jtag" AND SOC_USB_SERIAL_JTAG_SUPPORTED != 1 - if: CONFIG_NAME == "usb_console_ets_printf" AND SOC_USB_OTG_SUPPORTED != 1 - - if: IDF_TARGET in ["esp32p4"] - temporary: true - reason: target(s) not supported yet #TODO: IDF-8119 + - if: CONFIG_NAME == "phy_multiple_init_data" AND IDF_TARGET == "esp32p4" # Update with caps here when IDF-7460 is resolved tools/test_apps/system/cxx_no_except: enable: @@ -125,7 +137,7 @@ tools/test_apps/system/eh_frame: tools/test_apps/system/g0_components: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c5"] # preview targets tools/test_apps/system/g1_components: diff --git a/tools/test_apps/configs/sdkconfig.debug_helpers b/tools/test_apps/configs/sdkconfig.debug_helpers index 4bd42af97d9..9bb49614b9a 100644 --- a/tools/test_apps/configs/sdkconfig.debug_helpers +++ b/tools/test_apps/configs/sdkconfig.debug_helpers @@ -4,3 +4,4 @@ CONFIG_COMPILER_WARN_WRITE_STRINGS=y CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y CONFIG_COMPILER_STACK_CHECK=y +CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES=y diff --git a/tools/test_apps/linux_compatible/driver_mock/main/driver_mock_main.c b/tools/test_apps/linux_compatible/driver_mock/main/driver_mock_main.c index f36d705f898..8c47f3016c9 100644 --- a/tools/test_apps/linux_compatible/driver_mock/main/driver_mock_main.c +++ b/tools/test_apps/linux_compatible/driver_mock/main/driver_mock_main.c @@ -17,7 +17,7 @@ #include "Mockrmt_tx.h" #include "Mockrmt_rx.h" -/*Test that mock functions exist*/ +/* Test that mock functions exist and that required definitions are available */ void app_main(void) { i2c_driver_delete(0); @@ -26,6 +26,42 @@ void app_main(void) int gpio_num = GPIO_NUM_39; (void)gpio_num; + spi_host_device_t spi_dev = SPI1_HOST; + spi_dev = SPI2_HOST; + (void)spi_dev; + spi_clock_source_t spi_default_clock = SPI_CLK_SRC_DEFAULT; + (void)spi_default_clock; + soc_periph_spi_clk_src_t soc_periph_spi_clk_src = 0; + (void)soc_periph_spi_clk_src; + + rmt_clock_source_t rmt_clk_source = 0; + (void)rmt_clk_source; + rmt_symbol_word_t rm_symbol_word = { .duration0 = 47, .level0 = 0, .duration1 = 47, .level1 = 1 }; + (void)rm_symbol_word; + + i2c_port_t i2c_port = I2C_NUM_0; + (void)i2c_port; + i2c_mode_t i2c_mode = I2C_MODE_MASTER; + i2c_mode = I2C_MODE_SLAVE; + (void)i2c_mode; + i2c_rw_t i2c_rw = I2C_MASTER_WRITE; + i2c_rw = I2C_MASTER_READ; + (void)i2c_rw; + i2c_trans_mode_t i2c = I2C_DATA_MODE_MSB_FIRST; + i2c = I2C_DATA_MODE_LSB_FIRST; + (void)i2c; + i2c_addr_bit_len_t i2c_addr_bit_len = I2C_ADDR_BIT_LEN_7; + + #if SOC_I2C_SUPPORT_10BIT_ADDR + i2c_addr_bit_len = I2C_ADDR_BIT_LEN_10; + #endif + + (void)i2c_addr_bit_len; + i2c_ack_type_t i2c_ack = I2C_MASTER_ACK; + i2c_ack = I2C_MASTER_NACK; + i2c_ack = I2C_MASTER_LAST_NACK; + (void)i2c_ack; + rmt_channel_handle_t channel = 0; rmt_new_bytes_encoder(NULL, NULL); rmt_new_rx_channel(NULL, NULL); diff --git a/tools/test_apps/linux_compatible/linux_freertos/components/kernel_tests/stream_buffer/test_stream_buffers.c b/tools/test_apps/linux_compatible/linux_freertos/components/kernel_tests/stream_buffer/test_stream_buffers.c index 51216d134b4..82007c309ae 100644 --- a/tools/test_apps/linux_compatible/linux_freertos/components/kernel_tests/stream_buffer/test_stream_buffers.c +++ b/tools/test_apps/linux_compatible/linux_freertos/components/kernel_tests/stream_buffer/test_stream_buffers.c @@ -60,8 +60,16 @@ TEST_CASE("Stream Buffer: Send-receive tasks", "[freertos]") test_args.done_sem = xSemaphoreCreateCounting(2, 0); TEST_ASSERT_NOT_NULL(test_args.stream_buffer); TEST_ASSERT_NOT_NULL(test_args.done_sem); - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(sender_task, "sender", 4096, &test_args, CONFIG_UNITY_FREERTOS_PRIORITY + 2, NULL, 0)); - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(receiver_task, "receiver", 4096, &test_args, CONFIG_UNITY_FREERTOS_PRIORITY + 1, NULL, 1)); + BaseType_t sender_core_id; + BaseType_t receiver_core_id; + sender_core_id = 0; + #if CONFIG_FREERTOS_UNICORE + receiver_core_id = 0; + #else + receiver_core_id = 1; + #endif + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(sender_task, "sender", 4096, &test_args, CONFIG_UNITY_FREERTOS_PRIORITY + 2, NULL, sender_core_id)); + TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(receiver_task, "receiver", 4096, &test_args, CONFIG_UNITY_FREERTOS_PRIORITY + 1, NULL, receiver_core_id)); // Wait for both tasks to complete for (int i = 0; i < 2; i++) { diff --git a/tools/test_apps/linux_compatible/linux_freertos/main/Kconfig.projbuild b/tools/test_apps/linux_compatible/linux_freertos/main/Kconfig.projbuild index eb5770cea79..1b68b3ea6d5 100644 --- a/tools/test_apps/linux_compatible/linux_freertos/main/Kconfig.projbuild +++ b/tools/test_apps/linux_compatible/linux_freertos/main/Kconfig.projbuild @@ -18,7 +18,7 @@ menu "IDF unit test" config UNITY_CRITICAL_LEAK_LEVEL_GENERAL int "Critical leak" - default 1024 + default 1200 config UNITY_CRITICAL_LEAK_LEVEL_LWIP int "Critical leak for UT which use LWIP component" diff --git a/tools/test_apps/protocols/network_tests/main/stdinout.c b/tools/test_apps/protocols/network_tests/main/stdinout.c index 719c8ff5282..a257bea4604 100644 --- a/tools/test_apps/protocols/network_tests/main/stdinout.c +++ b/tools/test_apps/protocols/network_tests/main/stdinout.c @@ -3,11 +3,12 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include #include "esp_netif.h" #include "esp_log.h" #include "driver/uart.h" +#include "driver/uart_vfs.h" #include "esp_console.h" -#include "esp_vfs_dev.h" #include "linenoise/linenoise.h" // @@ -139,10 +140,10 @@ void * netsuite_io_new(void) ESP_ERROR_CHECK( uart_driver_install( (uart_port_t)CONFIG_ESP_CONSOLE_UART_NUM, 256, 0, 0, NULL, 0) ); /* Tell VFS to use UART driver */ - esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); - esp_vfs_dev_uart_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); + uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM); + uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR); /* Move the caret to the beginning of the next line on '\n' */ - esp_vfs_dev_uart_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); + uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF); linenoiseSetDumbMode(1); return (void *)&s_driver_base; } diff --git a/tools/test_apps/storage/sdmmc_console/CMakeLists.txt b/tools/test_apps/storage/sdmmc_console/CMakeLists.txt new file mode 100644 index 00000000000..caa12a6306f --- /dev/null +++ b/tools/test_apps/storage/sdmmc_console/CMakeLists.txt @@ -0,0 +1,11 @@ +cmake_minimum_required(VERSION 3.16) + +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/examples/system/console/advanced/components") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/components/esp_driver_sdmmc/test_apps/sd_test_utils/components") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests") +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests") +set(COMPONENTS main) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(sdmmc_test_console) diff --git a/components/sdmmc/test_apps/sdmmc_console/README.md b/tools/test_apps/storage/sdmmc_console/README.md similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/README.md rename to tools/test_apps/storage/sdmmc_console/README.md diff --git a/tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/CMakeLists.txt b/tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/CMakeLists.txt new file mode 100644 index 00000000000..aca698445f8 --- /dev/null +++ b/tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/CMakeLists.txt @@ -0,0 +1,6 @@ +idf_component_register(SRCS cmd_sdmmc.c + INCLUDE_DIRS . + PRIV_REQUIRES console sdmmc esp_driver_sdmmc esp_driver_gpio esp_driver_sdspi + sdmmc_test_boards + +) diff --git a/components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.c b/tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.c similarity index 98% rename from components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.c rename to tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.c index b5ec6976177..4a41fbd7c89 100644 --- a/components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.c +++ b/tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.c @@ -11,8 +11,8 @@ #include "esp_check.h" #include "esp_console.h" #include "soc/soc_caps.h" -#include "driver/sdmmc_defs.h" -#include "driver/sdmmc_types.h" +#include "sd_protocol_defs.h" +#include "sd_protocol_types.h" #include "sdmmc_cmd.h" #ifdef SOC_SDMMC_HOST_SUPPORTED #include "driver/sdmmc_host.h" diff --git a/components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.h b/tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.h similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.h rename to tools/test_apps/storage/sdmmc_console/components/cmd_sdmmc/cmd_sdmmc.h diff --git a/components/sdmmc/test_apps/sdmmc_console/components/cmd_unity/CMakeLists.txt b/tools/test_apps/storage/sdmmc_console/components/cmd_unity/CMakeLists.txt similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/components/cmd_unity/CMakeLists.txt rename to tools/test_apps/storage/sdmmc_console/components/cmd_unity/CMakeLists.txt diff --git a/components/sdmmc/test_apps/sdmmc_console/components/cmd_unity/cmd_unity.c b/tools/test_apps/storage/sdmmc_console/components/cmd_unity/cmd_unity.c similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/components/cmd_unity/cmd_unity.c rename to tools/test_apps/storage/sdmmc_console/components/cmd_unity/cmd_unity.c diff --git a/components/sdmmc/test_apps/sdmmc_console/components/cmd_unity/cmd_unity.h b/tools/test_apps/storage/sdmmc_console/components/cmd_unity/cmd_unity.h similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/components/cmd_unity/cmd_unity.h rename to tools/test_apps/storage/sdmmc_console/components/cmd_unity/cmd_unity.h diff --git a/components/sdmmc/test_apps/sdmmc_console/main/CMakeLists.txt b/tools/test_apps/storage/sdmmc_console/main/CMakeLists.txt similarity index 87% rename from components/sdmmc/test_apps/sdmmc_console/main/CMakeLists.txt rename to tools/test_apps/storage/sdmmc_console/main/CMakeLists.txt index 042ef43441b..45d9ea026fd 100644 --- a/components/sdmmc/test_apps/sdmmc_console/main/CMakeLists.txt +++ b/tools/test_apps/storage/sdmmc_console/main/CMakeLists.txt @@ -4,7 +4,7 @@ set(requires # for console history vfs fatfs # sdmmc tests, themselves - sdmmc_test_board sdmmc_tests + sdmmc_test_boards sdmmc_tests sdspi_tests # various console comamnds cmd_unity cmd_system cmd_sdmmc ) diff --git a/components/sdmmc/test_apps/sdmmc_console/main/sdmmc_console_main.c b/tools/test_apps/storage/sdmmc_console/main/sdmmc_console_main.c similarity index 100% rename from components/sdmmc/test_apps/sdmmc_console/main/sdmmc_console_main.c rename to tools/test_apps/storage/sdmmc_console/main/sdmmc_console_main.c diff --git a/components/sdmmc/test_apps/sdmmc_console/partitions.csv b/tools/test_apps/storage/sdmmc_console/partitions.csv similarity index 87% rename from components/sdmmc/test_apps/sdmmc_console/partitions.csv rename to tools/test_apps/storage/sdmmc_console/partitions.csv index 1c79321a107..d4fe8bd49f8 100644 --- a/components/sdmmc/test_apps/sdmmc_console/partitions.csv +++ b/tools/test_apps/storage/sdmmc_console/partitions.csv @@ -3,4 +3,4 @@ nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, factory, app, factory, 0x10000, 1M, -storage, data, fat, , 1M, +storage, data, fat, , 528K, diff --git a/components/sdmmc/test_apps/sdmmc_console/sdkconfig.defaults b/tools/test_apps/storage/sdmmc_console/sdkconfig.defaults similarity index 92% rename from components/sdmmc/test_apps/sdmmc_console/sdkconfig.defaults rename to tools/test_apps/storage/sdmmc_console/sdkconfig.defaults index 051b5e29ecb..b5480d96ba3 100644 --- a/components/sdmmc/test_apps/sdmmc_console/sdkconfig.defaults +++ b/tools/test_apps/storage/sdmmc_console/sdkconfig.defaults @@ -1,5 +1,5 @@ CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y -CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y CONFIG_HEAP_POISONING_COMPREHENSIVE=y CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y diff --git a/tools/test_apps/storage/sdmmc_console/sdkconfig.defaults.esp32h2 b/tools/test_apps/storage/sdmmc_console/sdkconfig.defaults.esp32h2 new file mode 100644 index 00000000000..bd38a2886da --- /dev/null +++ b/tools/test_apps/storage/sdmmc_console/sdkconfig.defaults.esp32h2 @@ -0,0 +1,5 @@ +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +CONFIG_SDMMC_BOARD_CUSTOM_MISO=0 +CONFIG_SDMMC_BOARD_CUSTOM_MOSI=5 +CONFIG_SDMMC_BOARD_CUSTOM_SCK=4 +CONFIG_SDMMC_BOARD_CUSTOM_CS=1 diff --git a/tools/test_apps/system/build_test/README.md b/tools/test_apps/system/build_test/README.md index ff948772002..8253a41e8ba 100644 --- a/tools/test_apps/system/build_test/README.md +++ b/tools/test_apps/system/build_test/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | This project is for testing if the application can be built with a particular sdkconfig setting. diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.custom_mac b/tools/test_apps/system/build_test/sdkconfig.ci.custom_mac new file mode 100644 index 00000000000..a10cda2c780 --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.custom_mac @@ -0,0 +1 @@ +CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC=y diff --git a/tools/test_apps/system/esp_intr_dump/main/test_esp_intr_dump_main.c b/tools/test_apps/system/esp_intr_dump/main/test_esp_intr_dump_main.c index 6c96c0312b3..b32ad8e6430 100644 --- a/tools/test_apps/system/esp_intr_dump/main/test_esp_intr_dump_main.c +++ b/tools/test_apps/system/esp_intr_dump/main/test_esp_intr_dump_main.c @@ -27,6 +27,10 @@ static void start_console(void) { esp_console_repl_t *repl = NULL; esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + + /* Pin repl task to ensure all interrupts are allocated on the same core */ + repl_config.task_core_id = 0; + /* Prompt to be printed before each line. * This can be customized, made dynamic, etc. */ @@ -136,6 +140,9 @@ static int cmd_intr_alloc(int argc, char **argv) printf("Failed to allocate interrupt (source: %d, flags: 0x%x): %s\n", source_num, flags, esp_err_to_name(ret)); return 1; } + + printf("Allocated %s %s\n", source_str, flags_str); + return 0; } diff --git a/tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py b/tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py index 161b6ef7d0c..2b807d80d2c 100644 --- a/tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py +++ b/tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py @@ -15,6 +15,7 @@ def test_esp_intr_dump_nonshared(dut: Dut) -> None: dut.expect_exact(PROMPT, timeout=10) dut.write('intr_alloc GPIO LEVEL3\n') + dut.expect_exact('Allocated GPIO LEVEL3') dut.expect_exact(PROMPT) dut.write('intr_dump\n') @@ -27,6 +28,7 @@ def test_esp_intr_dump_shared(dut: Dut) -> None: dut.expect_exact(PROMPT, timeout=10) dut.write('intr_alloc GPIO SHARED\n') + dut.expect_exact('Allocated GPIO SHARED') dut.expect_exact(PROMPT) dut.write('intr_dump\n') @@ -34,6 +36,7 @@ def test_esp_intr_dump_shared(dut: Dut) -> None: dut.expect_exact(PROMPT) dut.write('intr_alloc UART1 SHARED\n') + dut.expect_exact('Allocated UART1 SHARED') dut.expect_exact(PROMPT) dut.write('intr_dump\n') diff --git a/tools/test_apps/system/g0_components/README.md b/tools/test_apps/system/g0_components/README.md index 51f5cec15ec..5c05ed3a70c 100644 --- a/tools/test_apps/system/g0_components/README.md +++ b/tools/test_apps/system/g0_components/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # "G0"-components-only app diff --git a/tools/test_apps/system/g1_components/CMakeLists.txt b/tools/test_apps/system/g1_components/CMakeLists.txt index 582efb40ad0..09757deb181 100644 --- a/tools/test_apps/system/g1_components/CMakeLists.txt +++ b/tools/test_apps/system/g1_components/CMakeLists.txt @@ -33,9 +33,9 @@ set(extra_components_which_shouldnt_be_included bootloader_support # [refactor-todo]: should cxx be in G1? Can it exist without FreeRTOS? cxx - # [refactor-todo]: driver is a dependency of esp_pm, spi_flash, vfs, esp_wifi - # all of these should be removed from G1 except for spi_flash. - driver esp_driver_gpio esp_driver_pcnt esp_driver_gptimer + # [refactor-todo]: esp_driver_gpio is a dependency of esp_pm (should be removed from g1 builds), + # spi_flash, esp_hw_support + esp_driver_gpio # esp_app_format is dependency of bootloader_support, app_update esp_app_format # esp_bootloader_format is dependency of bootloader_support, app_update @@ -48,8 +48,6 @@ set(extra_components_which_shouldnt_be_included # conditional on related Kconfig option. It is also used by esp_wifi, driver, mbedtls, # all of which should be removed from G1-only build. esp_pm - # esp_ringbuf is a dependency of driver, which should be removed. - esp_ringbuf # esp_timer is a dependency of freertos, esp_event, esp_wifi, driver. # For freertos, it can be made a weak dependency conditional on FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER esp_timer diff --git a/tools/test_apps/system/memprot/main/esp32c3/test_panic.c b/tools/test_apps/system/memprot/main/esp32c3/test_panic.c index f75450ef2c0..cd28a8b2120 100644 --- a/tools/test_apps/system/memprot/main/esp32c3/test_panic.c +++ b/tools/test_apps/system/memprot/main/esp32c3/test_panic.c @@ -6,8 +6,8 @@ #include "riscv/rvruntime-frames.h" #include "esp_private/panic_internal.h" +#include "esp_private/panic_reason.h" -#define MCAUSE_ILLEGAL_INSTRUCTION 2 extern void esp_panic_handler(panic_info_t *info); volatile bool g_override_illegal_instruction = false; diff --git a/tools/test_apps/system/memprot/main/esp32s2/test_panic.c b/tools/test_apps/system/memprot/main/esp32s2/test_panic.c index 0cd853205b1..4f26cc86a72 100644 --- a/tools/test_apps/system/memprot/main/esp32s2/test_panic.c +++ b/tools/test_apps/system/memprot/main/esp32s2/test_panic.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_private/panic_internal.h" extern void esp_panic_handler(panic_info_t *info); diff --git a/tools/test_apps/system/memprot/main/esp32s3/test_panic.c b/tools/test_apps/system/memprot/main/esp32s3/test_panic.c index b126e537d2b..a1071aa00c5 100644 --- a/tools/test_apps/system/memprot/main/esp32s3/test_panic.c +++ b/tools/test_apps/system/memprot/main/esp32s3/test_panic.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "freertos/xtensa_context.h" +#include "xtensa_context.h" #include "esp_private/panic_internal.h" #include "hal/wdt_hal.h" diff --git a/tools/test_apps/system/panic/main/panic_utils/memprot_panic_utils_xtensa.c b/tools/test_apps/system/panic/main/panic_utils/memprot_panic_utils_xtensa.c index f67e81aed79..13de733dc7d 100644 --- a/tools/test_apps/system/panic/main/panic_utils/memprot_panic_utils_xtensa.c +++ b/tools/test_apps/system/panic/main/panic_utils/memprot_panic_utils_xtensa.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "freertos/xtensa_context.h" #include "esp_private/panic_internal.h" #include "esp_rom_sys.h" diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py index 3f110d4e018..2e24df2d972 100644 --- a/tools/test_apps/system/panic/pytest_panic.py +++ b/tools/test_apps/system/panic/pytest_panic.py @@ -123,10 +123,19 @@ def test_task_wdt_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> N dut.expect_elf_sha256() dut.expect_none('Guru Meditation') + coredump_pattern = (PANIC_ABORT_PREFIX + + 'Task watchdog got triggered. ' + 'The following tasks/users did not reset the watchdog in time:\n - ') + if dut.is_multi_core: + coredump_pattern += 'IDLE0 (CPU 0)' + else: + coredump_pattern += 'IDLE (CPU 0)' + common_test( dut, config, expected_backtrace=get_default_backtrace(test_func_name), + expected_coredump=[coredump_pattern] ) @@ -151,10 +160,14 @@ def test_task_wdt_cpu1(dut: PanicTestDut, config: str, test_func_name: str) -> N dut.expect_elf_sha256() dut.expect_none('Guru Meditation') + coredump_pattern = (PANIC_ABORT_PREFIX + + 'Task watchdog got triggered. ' + 'The following tasks/users did not reset the watchdog in time:\n - IDLE1 (CPU 1)') common_test( dut, config, expected_backtrace=expected_backtrace, + expected_coredump=[coredump_pattern] ) @@ -183,10 +196,14 @@ def test_task_wdt_both_cpus(dut: PanicTestDut, config: str, test_func_name: str) dut.expect_elf_sha256() dut.expect_none('Guru Meditation') + coredump_pattern = (PANIC_ABORT_PREFIX + + 'Task watchdog got triggered. ' + 'The following tasks/users did not reset the watchdog in time:\n - IDLE1 (CPU 1)\n - IDLE0 (CPU 0)') common_test( dut, config, expected_backtrace=expected_backtrace, + expected_coredump=[coredump_pattern] ) @@ -260,9 +277,12 @@ def test_int_wdt_cache_disabled( @pytest.mark.generic def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) - if dut.target in ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2']: - # Cache error interrupt is not raised, IDF-6398 - dut.expect_gme('Illegal instruction') + if dut.target in ['esp32c3', 'esp32c2']: + dut.expect_gme('Cache error') + dut.expect_exact('Cached memory region accessed while ibus or cache is disabled') + elif dut.target in ['esp32c6', 'esp32h2']: + dut.expect_gme('Cache error') + dut.expect_exact('Cache access error') elif dut.target in ['esp32s2']: # Cache error interrupt is not enabled, IDF-1558 dut.expect_gme('IllegalInstruction') diff --git a/tools/test_apps/system/panic/test_panic_util/panic_dut.py b/tools/test_apps/system/panic/test_panic_util/panic_dut.py index 8593934c38e..61a5d134b0c 100644 --- a/tools/test_apps/system/panic/test_panic_util/panic_dut.py +++ b/tools/test_apps/system/panic/test_panic_util/panic_dut.py @@ -51,6 +51,10 @@ def revert_log_level(self) -> None: def is_xtensa(self) -> bool: return self.target in self.XTENSA_TARGETS + @property + def is_multi_core(self) -> bool: + return self.target in ['esp32', 'esp32s3'] + def run_test_func(self, test_func_name: str) -> None: self.expect_exact('Enter test name:') self.write(test_func_name) @@ -184,10 +188,9 @@ def start_gdb(self) -> None: """ gdb_args = ['--nx', '--quiet', '--interpreter=mi2'] if self.is_xtensa: - gdb_path = 'xtensa-esp-elf-gdb-no-python' # TODO: GCC-311 - gdb_args = [f'--mcpu={self.target}'] + gdb_args + gdb_path = f'xtensa-{self.target}-elf-gdb' else: - gdb_path = 'riscv32-esp-elf-gdb-no-python' # TODO: GCC-311 + gdb_path = 'riscv32-esp-elf-gdb' try: from pygdbmi.constants import GdbTimeoutError gdb_command = [gdb_path] + gdb_args diff --git a/tools/test_apps/system/ram_loadable_app/README.md b/tools/test_apps/system/ram_loadable_app/README.md index 0283938f981..76930508c72 100644 --- a/tools/test_apps/system/ram_loadable_app/README.md +++ b/tools/test_apps/system/ram_loadable_app/README.md @@ -37,13 +37,13 @@ idf.py build esptool.py -p PORT --no-stub load_ram build/ram_loadable_app.bin -idf.py -p PORT monitor +idf.py -p PORT monitor --no-reset ``` (Replace PORT with the name of the serial port to use.) (To exit the serial monitor, type ``Ctrl-]``.) -(For ram_loadable_app, after the chip is reset, it will start from flash by default, so the program will be executed directly after loading to ram. Therefore, manually open idf.py monitor will lose part of the log at startup because the serial port cannot be opened in time, so it is recommended to use a separate serial converter to monitor the output of the UART TX pin) +(For ram_loadable_app, after the chip is reset, it will start from flash by default, so the program will be executed directly after loading to ram. This is the reason why we use `--no-reset`. Besides, manually opening idf.py monitor will lose part of the log at startup because the serial port cannot be opened in time, so it is recommended to use a separate serial converter to monitor the output of the UART TX pin) See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. diff --git a/tools/test_build_system/conftest.py b/tools/test_build_system/conftest.py index 94e0348ffb7..7c84fe39872 100644 --- a/tools/test_build_system/conftest.py +++ b/tools/test_build_system/conftest.py @@ -38,21 +38,44 @@ def pytest_addoption(parser: pytest.Parser) -> None: ) -@pytest.fixture(name='session_work_dir', scope='session', autouse=True) -def fixture_session_work_dir(request: FixtureRequest) -> typing.Generator[Path, None, None]: +@pytest.fixture(scope='session') +def _session_work_dir(request: FixtureRequest) -> typing.Generator[typing.Tuple[Path, bool], None, None]: work_dir = request.config.getoption('--work-dir') + if work_dir: work_dir = os.path.join(work_dir, datetime.datetime.utcnow().strftime('%Y-%m-%d_%H-%M-%S')) logging.debug(f'using work directory: {work_dir}') os.makedirs(work_dir, exist_ok=True) clean_dir = None + is_temp_dir = False else: work_dir = mkdtemp() logging.debug(f'created temporary work directory: {work_dir}') clean_dir = work_dir + is_temp_dir = True + + # resolve allows using relative paths with --work-dir option + yield Path(work_dir).resolve(), is_temp_dir + + if clean_dir: + logging.debug(f'cleaning up {clean_dir}') + shutil.rmtree(clean_dir, ignore_errors=True) + + +@pytest.fixture(name='func_work_dir', autouse=True) +def work_dir(request: FixtureRequest, _session_work_dir: typing.Tuple[Path, bool]) -> typing.Generator[Path, None, None]: + session_work_dir, is_temp_dir = _session_work_dir + + if request._pyfuncitem.keywords.get('force_temp_work_dir') and not is_temp_dir: + work_dir = Path(mkdtemp()).resolve() + logging.debug('Force using temporary work directory') + clean_dir = work_dir + else: + work_dir = session_work_dir + clean_dir = None - # resolve allows to use relative paths with --work-dir option - yield Path(work_dir).resolve() + # resolve allows using relative paths with --work-dir option + yield work_dir if clean_dir: logging.debug(f'cleaning up {clean_dir}') @@ -60,7 +83,7 @@ def fixture_session_work_dir(request: FixtureRequest) -> typing.Generator[Path, @pytest.fixture -def test_app_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: +def test_app_copy(func_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: # by default, use hello_world app and copy it to a temporary directory with # the name resembling that of the test copy_from = 'tools/test_build_system/build_test_app' @@ -74,7 +97,7 @@ def test_app_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Gen copy_to = mark.args[1] path_from = Path(os.environ['IDF_PATH']) / copy_from - path_to = session_work_dir / copy_to + path_to = func_work_dir / copy_to # if the new directory inside the original directory, # make sure not to go into recursion. @@ -99,13 +122,13 @@ def test_app_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Gen @pytest.fixture -def test_git_template_app(session_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: +def test_git_template_app(func_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: copy_to = request.node.name + '_app' - path_to = session_work_dir / copy_to + path_to = func_work_dir / copy_to - logging.debug(f'clonning git-teplate app to {path_to}') + logging.debug(f'cloning git-template app to {path_to}') path_to.mkdir() - # No need to clone full repository, just single master branch + # No need to clone full repository, just a single master branch subprocess.run(['git', 'clone', '--single-branch', '-b', 'master', '--depth', '1', 'https://github.com/espressif/esp-idf-template.git', '.'], cwd=path_to, stdout=subprocess.PIPE, stderr=subprocess.PIPE) @@ -122,7 +145,7 @@ def test_git_template_app(session_work_dir: Path, request: FixtureRequest) -> ty @pytest.fixture -def idf_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: +def idf_copy(func_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: copy_to = request.node.name + '_idf' # allow overriding the destination via pytest.mark.idf_copy() @@ -131,7 +154,7 @@ def idf_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Generato copy_to = mark.args[0] path_from = EXT_IDF_PATH - path_to = session_work_dir / copy_to + path_to = func_work_dir / copy_to # if the new directory inside the original directory, # make sure not to go into recursion. diff --git a/tools/test_build_system/pytest.ini b/tools/test_build_system/pytest.ini index fad075f0bba..0db692d0487 100644 --- a/tools/test_build_system/pytest.ini +++ b/tools/test_build_system/pytest.ini @@ -16,3 +16,4 @@ junit_log_passing_tests = False markers = test_app_copy: specify relative path of the app to copy, and the prefix of the destination directory name idf_copy: specify the prefix of the destination directory where IDF should be copied + force_temp_work_dir: force temporary folder as the working directory diff --git a/tools/test_build_system/test_bootloader.py b/tools/test_build_system/test_bootloader.py index 4f90d7d0040..4e7abc07dbe 100644 --- a/tools/test_build_system/test_bootloader.py +++ b/tools/test_build_system/test_bootloader.py @@ -28,7 +28,7 @@ def test_bootloader_custom_overrides_original(test_app_copy: Path, idf_py: IdfPy shutil.copytree(idf_path / 'components' / 'esp_bootloader_format', test_app_copy / 'components' / 'esp_bootloader_format') idf_py('bootloader') assert file_contains(test_app_copy / 'build' / 'bootloader' / 'compile_commands.json', - str(test_app_copy / 'components' / 'bootloader' / 'subproject' / 'main' / 'bootloader_start.c')) + (test_app_copy / 'components' / 'bootloader' / 'subproject' / 'main' / 'bootloader_start.c')) def test_bootloader_custom_ignores_extra_component(test_app_copy: Path, idf_py: IdfPyFunc, default_idf_env: EnvDict) -> None: diff --git a/tools/test_build_system/test_build.py b/tools/test_build_system/test_build.py index 6b206fbd2e0..5529aab2779 100644 --- a/tools/test_build_system/test_build.py +++ b/tools/test_build_system/test_build.py @@ -19,9 +19,9 @@ def assert_built(paths: Union[List[str], List[Path]]) -> None: assert os.path.exists(path) -def test_build_alternative_directories(idf_py: IdfPyFunc, session_work_dir: Path, test_app_copy: Path) -> None: +def test_build_alternative_directories(idf_py: IdfPyFunc, func_work_dir: Path, test_app_copy: Path) -> None: logging.info('Moving BUILD_DIR_BASE out of tree') - alt_build_dir = session_work_dir / 'alt_build' + alt_build_dir = func_work_dir / 'alt_build' idf_py('-B', str(alt_build_dir), 'build') assert os.listdir(alt_build_dir) != [], 'No files found in new build directory!' default_build_dir = test_app_copy / 'build' @@ -201,3 +201,10 @@ def change_files_to_crlf(path: Path) -> None: change_files_to_crlf(idf_copy) idf_py('build') assert_built(BOOTLOADER_BINS + APP_BINS + PARTITION_BIN) + + +def test_build_cmake_executable_suffix(idf_py: IdfPyFunc, test_app_copy: Path) -> None: + logging.info('idf.py can build with CMAKE_EXECUTABLE_SUFFIX set') + append_to_file((test_app_copy / 'CMakeLists.txt'), 'set(CMAKE_EXECUTABLE_SUFFIX_CXX ".ext")') + ret = idf_py('build') + assert 'Project build complete' in ret.stdout, 'Build with CMAKE_EXECUTABLE_SUFFIX set failed' diff --git a/tools/test_build_system/test_build_system_helpers/idf_utils.py b/tools/test_build_system/test_build_system_helpers/idf_utils.py index c4eacdd12a3..bec2df14eae 100644 --- a/tools/test_build_system/test_build_system_helpers/idf_utils.py +++ b/tools/test_build_system/test_build_system_helpers/idf_utils.py @@ -7,7 +7,7 @@ import subprocess import sys import typing -from pathlib import Path +from pathlib import Path, WindowsPath from typing import Pattern, Union try: @@ -137,7 +137,7 @@ def run_cmake_and_build(*cmake_args: str, env: typing.Optional[EnvDict] = None) run_cmake('--build', '.') -def file_contains(filename: Union[str, Path], what: Union[str, Pattern]) -> bool: +def file_contains(filename: Union[str, Path], what: Union[Union[str, Path], Pattern]) -> bool: """ Returns true if file contains required object :param filename: path to file where lookup is executed @@ -145,10 +145,16 @@ def file_contains(filename: Union[str, Path], what: Union[str, Pattern]) -> bool """ with open(filename, 'r', encoding='utf-8') as f: data = f.read() - if isinstance(what, str): - return what in data - else: + if isinstance(what, Pattern): return re.search(what, data) is not None + else: + what_str = str(what) + # In case of windows path, try both single-slash `\` and double-slash '\\' paths + if isinstance(what, WindowsPath): + what_double_slash = what_str.replace('\\', '\\\\') + return what_str in data or what_double_slash in data + + return what_str in data def bin_file_contains(filename: Union[str, Path], what: bytearray) -> bool: diff --git a/tools/test_build_system/test_cmake.py b/tools/test_build_system/test_cmake.py index 107b854bcb7..0a677db8ed0 100644 --- a/tools/test_build_system/test_cmake.py +++ b/tools/test_build_system/test_cmake.py @@ -4,12 +4,14 @@ import os import re import shutil +import sys from pathlib import Path import pytest from test_build_system_helpers import EnvDict, IdfPyFunc, append_to_file, file_contains, run_cmake, run_cmake_and_build +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_build_custom_cmake_project(test_app_copy: Path) -> None: for target in ['esp32', 'esp32s3', 'esp32c6', 'esp32h2']: logging.info(f'Test build ESP-IDF as a library to a custom CMake projects for {target}') @@ -50,6 +52,7 @@ def test_build_cmake_library_psram_strategies(idf_py: IdfPyFunc, test_app_copy: (test_app_copy / 'sdkconfig').unlink() +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') @pytest.mark.usefixtures('test_app_copy') @pytest.mark.usefixtures('idf_copy') def test_defaults_for_unspecified_idf_build_process_args(default_idf_env: EnvDict) -> None: diff --git a/tools/test_build_system/test_common.py b/tools/test_build_system/test_common.py index cc55c5df351..2d922890aef 100644 --- a/tools/test_build_system/test_common.py +++ b/tools/test_build_system/test_common.py @@ -207,6 +207,7 @@ def test_fallback_to_build_system_target(idf_py: IdfPyFunc, test_app_copy: Path) assert msg in ret.stdout, 'Custom target did not produce expected output' +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_create_component_and_project_plus_build(idf_copy: Path) -> None: logging.info('Create project and component using idf.py and build it') run_idf_py('-C', 'projects', 'create-project', 'temp_test_project', workdir=idf_copy) diff --git a/tools/test_build_system/test_components.py b/tools/test_build_system/test_components.py index 56fc9d479e2..630697e18dd 100644 --- a/tools/test_build_system/test_components.py +++ b/tools/test_build_system/test_components.py @@ -4,12 +4,14 @@ import json import logging import shutil +import sys from pathlib import Path import pytest from test_build_system_helpers import EnvDict, IdfPyFunc, append_to_file, replace_in_file +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_component_extra_dirs(idf_py: IdfPyFunc, test_app_copy: Path) -> None: logging.info('Setting EXTRA_COMPONENT_DIRS works') shutil.move(test_app_copy / 'main', test_app_copy / 'different_main' / 'main') @@ -42,6 +44,7 @@ def test_component_can_not_be_empty_dir(idf_py: IdfPyFunc, test_app_copy: Path) assert str(empty_component_dir) not in data.get('build_component_paths') +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_component_subdirs_not_added_to_component_dirs(idf_py: IdfPyFunc, test_app_copy: Path) -> None: logging.info('If a component directory is added to COMPONENT_DIRS, its subdirectories are not added') (test_app_copy / 'main' / 'test').mkdir(parents=True) @@ -52,6 +55,7 @@ def test_component_subdirs_not_added_to_component_dirs(idf_py: IdfPyFunc, test_a assert str(test_app_copy / 'main') in data.get('build_component_paths') +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_component_sibling_dirs_not_added_to_component_dirs(idf_py: IdfPyFunc, test_app_copy: Path) -> None: logging.info('If a component directory is added to COMPONENT_DIRS, its sibling directories are not added') mycomponents_subdir = (test_app_copy / 'mycomponents') @@ -76,6 +80,7 @@ def test_component_sibling_dirs_not_added_to_component_dirs(idf_py: IdfPyFunc, t assert str(mycomponents_subdir / 'mycomponent') in data.get('build_component_paths') +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_component_properties_are_set(idf_py: IdfPyFunc, test_app_copy: Path) -> None: logging.info('Component properties are set') append_to_file(test_app_copy / 'CMakeLists.txt', '\n'.join(['', @@ -85,6 +90,7 @@ def test_component_properties_are_set(idf_py: IdfPyFunc, test_app_copy: Path) -> assert 'SRCS:{}'.format(test_app_copy / 'main' / 'build_test_app.c') in ret.stdout, 'Component properties should be set' +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_component_overriden_dir(idf_py: IdfPyFunc, test_app_copy: Path, default_idf_env: EnvDict) -> None: logging.info('Getting component overriden dir') (test_app_copy / 'components' / 'hal').mkdir(parents=True) @@ -104,6 +110,7 @@ def test_component_overriden_dir(idf_py: IdfPyFunc, test_app_copy: Path, default assert 'kconfig:{}'.format(idf_path / 'components' / 'hal') in ret.stdout, 'Failed to verify original `main` directory' +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_components_prioritizer_over_extra_components_dir(idf_py: IdfPyFunc, test_app_copy: Path) -> None: logging.info('Project components prioritized over EXTRA_COMPONENT_DIRS') (test_app_copy / 'extra_dir' / 'my_component').mkdir(parents=True) diff --git a/tools/test_build_system/test_git.py b/tools/test_build_system/test_git.py index 25109c0ce13..57cdf3e4317 100644 --- a/tools/test_build_system/test_git.py +++ b/tools/test_build_system/test_git.py @@ -8,7 +8,7 @@ import typing from pathlib import Path -from test_build_system_helpers import EnvDict, IdfPyFunc, run_idf_py +from test_build_system_helpers import EnvDict, run_idf_py def run_git_cmd(*args: str, @@ -25,13 +25,6 @@ def run_git_cmd(*args: str, stdout=subprocess.PIPE, stderr=subprocess.PIPE) -def test_get_version_from_git_describe(test_git_template_app: Path, idf_py: IdfPyFunc) -> None: - logging.info('Get the version of app from git describe. Project is not inside IDF and do not have a tag only a hash commit.') - idf_ret = idf_py('reconfigure') - git_ret = run_git_cmd('describe', '--always', '--tags', '--dirty', workdir=test_git_template_app) - assert f'App "app-template" version: {git_ret.stdout.decode("utf-8")}' in idf_ret.stdout, 'Project version should have a hash commit' - - # In this test, the action needs to be performed in ESP-IDF that is valid git directory # Copying ESP-IDF is not possible def test_git_custom_tag() -> None: diff --git a/tools/test_build_system/test_kconfig.py b/tools/test_build_system/test_kconfig.py index 4db2dfdf0a4..ddcdba2132f 100644 --- a/tools/test_build_system/test_kconfig.py +++ b/tools/test_build_system/test_kconfig.py @@ -124,12 +124,3 @@ def test_kconfig_multiple_and_target_specific_options(idf_py: IdfPyFunc, test_ap idf_py('set-target', 'esp32s2') assert all([file_contains((test_app_copy / 'sdkconfig'), x) for x in ['CONFIG_TEST_NEW_OPTION=y', 'CONFIG_TEST_OLD_OPTION=y']]) - - -def test_kconfig_get_version_from_describe(idf_py: IdfPyFunc, test_app_copy: Path) -> None: - logging.info('Get the version of app from Kconfig option') - (test_app_copy / 'version.txt').write_text('project_version_from_txt') - (test_app_copy / 'sdkconfig.defaults').write_text('\n'.join(['CONFIG_APP_PROJECT_VER_FROM_CONFIG=y', - 'CONFIG_APP_PROJECT_VER="project_version_from_Kconfig"'])) - ret = idf_py('build') - assert 'App "build_test_app" version: project_version_from_Kconfig' in ret.stdout diff --git a/tools/test_build_system/test_non_default_target.py b/tools/test_build_system/test_non_default_target.py index f1efb79e560..0a445d7bd53 100644 --- a/tools/test_build_system/test_non_default_target.py +++ b/tools/test_build_system/test_non_default_target.py @@ -3,6 +3,7 @@ import logging import shutil +import sys from pathlib import Path from typing import List, Optional @@ -31,6 +32,7 @@ def test_target_from_environment_cmake(default_idf_env: EnvDict) -> None: assert file_contains('build/CMakeCache.txt', 'IDF_TARGET:STRING={}'.format(ESP32S2_TARGET)) +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_target_from_environment_idf_py(idf_py: IdfPyFunc, default_idf_env: EnvDict, test_app_copy: Path) -> None: def reconfigure_and_check_return_values(errmsg: str, opts: Optional[List[str]] = None) -> None: opts = opts or [] @@ -72,6 +74,7 @@ def reconfigure_and_check_return_values(errmsg: str, opts: Optional[List[str]] = ['-D', 'IDF_TARGET={}'.format(ESP32_TARGET)]) +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') def test_target_consistency_cmake(default_idf_env: EnvDict, test_app_copy: Path) -> None: def reconfigure_and_check_return_values(errmsg: str, opts: Optional[List[str]] = None) -> None: opts = opts or [] diff --git a/tools/test_build_system/test_partition.py b/tools/test_build_system/test_partition.py index acbcb413312..b8947cba922 100644 --- a/tools/test_build_system/test_partition.py +++ b/tools/test_build_system/test_partition.py @@ -31,9 +31,9 @@ def test_partition_nearly_full_warning(idf_py: IdfPyFunc, test_app_copy: Path, d ret = idf_py('build') # Build a first time to get the binary size and to check that no warning is issued. assert 'partition is nearly full' not in ret.stdout, 'Warning for nearly full smallest partition was given when the condition is not fulfilled' - # Get the size of the binary, in KB. Add 1 to the total. + # Get the size of the binary, in KB. Convert it to next multiple of 4. # The goal is to create an app partition which is slightly bigger than the binary itself - updated_file_size = int(os.stat(test_app_copy / 'build' / 'build_test_app.bin').st_size / 1024) + 1 + updated_file_size = int((os.stat(test_app_copy / 'build' / 'build_test_app.bin').st_size + 4095) / 4096) * 4 idf_path = Path(default_idf_env['IDF_PATH']) shutil.copy2(idf_path / 'components' / 'partition_table' / 'partitions_singleapp.csv', test_app_copy / 'partitions.csv') replace_in_file(test_app_copy / 'partitions.csv', diff --git a/tools/test_build_system/test_spaces.py b/tools/test_build_system/test_spaces.py index 0271da86b4d..2fd93a93249 100644 --- a/tools/test_build_system/test_spaces.py +++ b/tools/test_build_system/test_spaces.py @@ -20,6 +20,7 @@ def clean_app_dir(app_path: Path) -> None: shutil.rmtree(app_path / 'build', ignore_errors=True) +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') @pytest.mark.idf_copy('esp idf with spaces') def test_spaces_bundle1(idf_copy: Path) -> None: logging.info('Running test spaces bundle 1') @@ -33,6 +34,7 @@ def test_spaces_bundle1(idf_copy: Path) -> None: run_idf_py('build', workdir=(idf_copy / 'examples' / 'storage' / 'spiffsgen')) +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') @pytest.mark.idf_copy('esp idf with spaces') def test_spaces_bundle2(idf_copy: Path) -> None: logging.info('Running test spaces bundle 2') @@ -48,6 +50,7 @@ def test_spaces_bundle2(idf_copy: Path) -> None: run_idf_py('uf2', workdir=hello_world_app_path) +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') @pytest.mark.idf_copy('esp idf with spaces') def test_spaces_bundle3(idf_copy: Path) -> None: logging.info('Running test spaces bundle 3') @@ -86,6 +89,7 @@ def test_install_export_unix(idf_copy: Path) -> None: subprocess.check_call(export_cmd, env=env, shell=True, cwd=idf_copy, executable='/bin/bash') +@pytest.mark.skipif(sys.platform == 'win32', reason='Failing on Windows runner. TODO') @pytest.mark.skipif(sys.platform != 'win32', reason='Windows test') @pytest.mark.idf_copy('esp idf with spaces') def test_install_export_win(idf_copy: Path) -> None: diff --git a/tools/test_build_system/test_versions.py b/tools/test_build_system/test_versions.py new file mode 100644 index 00000000000..b4109fd5744 --- /dev/null +++ b/tools/test_build_system/test_versions.py @@ -0,0 +1,182 @@ +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import logging +import os +import subprocess +import typing +from pathlib import Path + +import pytest +from test_build_system_helpers import EnvDict, IdfPyFunc, append_to_file, replace_in_file + + +############################################################################################# +# Test Case: Test that the build-system can set the default version for an IDF app +# +# Test Steps: +# 1. Copy the base build_test_app +# 2. Run idf.py reconfigure +# 3. Verify that the app version takes the default value of 1 +# +# Note: This test must run outside a git repository for it to pass. Hence we force the test +# to use a temporary work directory. +############################################################################################# +@pytest.mark.force_temp_work_dir +def test_versions_get_default_version(idf_py: IdfPyFunc, test_app_copy: Path) -> None: + logging.info('Verify the default version of an app') + ret = idf_py('reconfigure') + assert 'App "build_test_app" version: 1' in ret.stdout + + +############################################################################################# +# Test Case: Test that the build-system can set the version of an IDF app from git describe +# +# Test Steps: +# 1. Clone the idf template app from https://github.com/espressif/esp-idf-template.git +# 2. Run idf.py reconfigure +# 3. Run git describe in the cloned app git repository +# 4. Verify that the app version is picked up from the git describe command +# +############################################################################################# +def test_versions_get_version_from_git_describe(idf_py: IdfPyFunc, + test_git_template_app: Path, + env: typing.Optional[EnvDict] = None) -> None: + logging.info('Verify that the version of app can be set from git describe') + idf_ret = idf_py('reconfigure') + env_dict = dict(**os.environ) + if env: + env_dict.update(env) + git_ret = subprocess.run(['git', 'describe', '--always', '--tags', '--dirty'], + cwd=test_git_template_app, env=env_dict, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + assert f'App "app-template" version: {git_ret.stdout.decode("utf-8")}' in idf_ret.stdout + + +############################################################################################# +# Test Case: Test that the build-system can set the version for an IDF app from the VERSION argument +# +# Test Steps: +# 1. Clone the idf template app from https://github.com/espressif/esp-idf-template.git +# 2. Replace the default project() command in the top level CMakeLists.txt file to call the version parsing +# function __parse_and_store_version_arg() +# 3. Append several calls to __parse_and_store_version_arg() with different inputs for the VERSION argument +# 4. Append a project() call with valid arguments at the end of the CMakeLists.txt file +# 5. Run idf.py reconfigure +# 6. Verify that cmake correctly flags invalid inputs for the VERSION argument and accepts valid inputs for the same +# +############################################################################################# +def test_versions_get_version_from_version_arg(idf_py: IdfPyFunc, test_git_template_app: Path) -> None: + logging.info('Verify that the VERSION argument in project() is correctly parsed by cmake') + + # empty VERSION argument + replace_in_file((test_git_template_app / 'CMakeLists.txt'), 'project(app-template)', + '__parse_and_store_version_arg(app-template VERSION)') + # Invalid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-tempplate VERSION 1..2)') + # Invalid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-template VERSION version_text)') + # Invalid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-template VERSION 1.2.3.4.5)') + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-template VERSION 0)') + # Valid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-template VERSION 0.1)') + # Valid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-template VERSION 0.1.2)') + # Valid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\n__parse_and_store_version_arg(app-template VERSION 0.1.2.3)') + # project() call with valid VERSION argument format + append_to_file((test_git_template_app / 'CMakeLists.txt'), + '\nproject(app-template VERSION 0.1.2.3)') + + with pytest.raises(subprocess.CalledProcessError) as e: + idf_py('reconfigure') + + assert 'VERSION keyword not followed by a value or was followed by a value that expanded to nothing.' in e.stdout + assert 'Version "1..2" format invalid' in e.stderr + assert 'Version "version_text" format invalid' in e.stderr + assert 'Version "1.2.3.4.5" format invalid' in e.stderr + assert 'Version "1.2.3.4.5" format invalid' in e.stderr + assert 'Version "0" format invalid' not in e.stderr + assert 'Version "0.1" format invalid' not in e.stderr + assert 'Version "0.1.2" format invalid' not in e.stderr + assert 'Version "0.1.2.3" format invalid' not in e.stderr + assert 'App "app-template" version: 0.1.2.3' in e.stdout + + +############################################################################################# +# Test Case: Test that the build-system can set the version of an IDF app from version.txt file +# +# Test Steps: +# 1. Clone the idf template app from https://github.com/espressif/esp-idf-template.git +# 2. Replace the default project() command in the top level CMakeLists.txt file to include VERSION argument +# 3. Copy version.txt file into the cloned app repository +# 4. Updated the version in version.txt file to a known value +# 5. Run idf.py reconfigure +# 6. Verify that the app version is picked up from the version.txt file +# +############################################################################################# +def test_versions_get_version_from_version_file(idf_py: IdfPyFunc, test_git_template_app: Path) -> None: + logging.info('Verify that the version of app can be set from version.txt file') + replace_in_file((test_git_template_app / 'CMakeLists.txt'), 'project(app-template)', + 'project(app-template VERSION 0.1.2.3)') + (test_git_template_app / 'version.txt').write_text('project_version_from_txt') + idf_ret = idf_py('reconfigure') + + assert f'App "app-template" version: project_version_from_txt' in idf_ret.stdout + + +############################################################################################# +# Test Case: Test that the build-system can set the version of an IDF app if PROJECT_VER is set in the CMakeLists.txt +# +# Test Steps: +# 1. Clone the idf template app from https://github.com/espressif/esp-idf-template.git +# 2. Update CMakeLists.txt file to set PROJECT_VER before calling project() +# 3. Replace the default project() command in the top level CMakeLists.txt file to include VERSION argument +# 4. Copy version.txt file into the cloned app repository +# 5. Updated the version in version.txt file to a known value +# 6. Run idf.py reconfigure +# 7. Verify that the app version is picked up from the CMakeLists.txt file +# +############################################################################################# +def test_versions_get_version_from_top_level_cmake(idf_py: IdfPyFunc, test_git_template_app: Path) -> None: + logging.info('Verify that the version of app can be set from PROJECT_VER in CMakeLists.txt') + replace_in_file((test_git_template_app / 'CMakeLists.txt'), 'project(app-template)', + 'set(PROJECT_VER project_version_from_CMakeLists)') + append_to_file((test_git_template_app / 'CMakeLists.txt'), 'project(app-template VERSION 0.1.2.3)') + (test_git_template_app / 'version.txt').write_text('project_version_from_txt') + idf_ret = idf_py('reconfigure') + + assert f'App "app-template" version: project_version_from_CMakeLists' in idf_ret.stdout + + +############################################################################################# +# Test Case: Test that the build-system can set the version of an IDF app from Kconfig option +# +# Test Steps: +# 1. Clone the idf template app from https://github.com/espressif/esp-idf-template.git +# 2. Update CMakeLists.txt file to set PROJECT_VER before calling project() +# 3. Replace the default project() command in the top level CMakeLists.txt file to include VERSION argument +# 4. Copy version.txt file into the cloned app repository +# 5. Updated the version in version.txt file to a known value +# 6. Run idf.py reconfigure +# 7. Updated sdkconfig.defaults to configure CONFIG_APP_PROJECT_VER_FROM_CONFIG and CONFIG_APP_PROJECT_VER +# 8. Run idf.py reconfigure +# 9. Verify that the app version is picked up from the Kconfig option +# +############################################################################################# +def test_versions_get_version_from_kconfig_option(idf_py: IdfPyFunc, test_git_template_app: Path) -> None: + logging.info('Verify that the version of app can be set from Kconfig option') + replace_in_file((test_git_template_app / 'CMakeLists.txt'), 'project(app-template)', + 'set(PROJECT_VER project_version_from_CMakeLists)') + append_to_file((test_git_template_app / 'CMakeLists.txt'), 'project(app-template VERSION 0.1.2.3)') + (test_git_template_app / 'sdkconfig.defaults').write_text('\n'.join(['CONFIG_APP_PROJECT_VER_FROM_CONFIG=y', + 'CONFIG_APP_PROJECT_VER="project_version_from_Kconfig"'])) + idf_ret = idf_py('reconfigure') + + assert f'App "app-template" version: project_version_from_Kconfig' in idf_ret.stdout diff --git a/tools/test_idf_py/pytest.ini b/tools/test_idf_py/pytest.ini new file mode 100644 index 00000000000..d95e773e5cd --- /dev/null +++ b/tools/test_idf_py/pytest.ini @@ -0,0 +1,12 @@ +[pytest] +addopts = -s -p no:pytest_embedded + +# log related +log_cli = True +log_cli_level = INFO +log_cli_format = %(asctime)s %(levelname)s %(message)s +log_cli_date_format = %Y-%m-%d %H:%M:%S + +## log all to `system-out` when case fail +junit_logging = stdout +junit_log_passing_tests = False diff --git a/tools/test_idf_py/test_idf_qemu.py b/tools/test_idf_py/test_idf_qemu.py new file mode 100755 index 00000000000..3188d1b6c4d --- /dev/null +++ b/tools/test_idf_py/test_idf_qemu.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 + +import logging +import os +import sys +import tempfile +import unittest + +import pexpect + + +class IdfPyQemuTest(unittest.TestCase): + def test_idf_qemu(self) -> None: + build_dir = tempfile.mkdtemp() + idf_path = os.environ['IDF_PATH'] + hello_world_dir = os.path.join(idf_path, 'examples', 'get-started', 'hello_world') + idf_py = os.path.join(idf_path, 'tools', 'idf.py') + args = [idf_py, '-C', hello_world_dir, '-B', build_dir, + 'qemu', '--qemu-extra-args', '-no-reboot', 'monitor'] + logfile_name = os.path.join(os.environ['IDF_PATH'], 'qemu_log.out') + with open(logfile_name, 'w+b') as logfile, \ + pexpect.spawn(sys.executable, args=args, logfile=logfile) as child: + child.expect('Executing action: all') + logging.info('Waiting for the build to finish...') + child.expect('Executing action: qemu', timeout=120) + child.expect('Generating flash image:') + child.expect('Generating efuse image:') + child.expect('Executing action: monitor') + child.expect('Hello world!') + child.expect('Restarting in 0 seconds', timeout=20) + child.expect('Restarting now.') + + +if __name__ == '__main__': + unittest.main() diff --git a/tools/test_idf_tools/test_idf_tools.py b/tools/test_idf_tools/test_idf_tools.py index 2c21e46cba2..699eb89191f 100755 --- a/tools/test_idf_tools/test_idf_tools.py +++ b/tools/test_idf_tools/test_idf_tools.py @@ -85,14 +85,15 @@ def get_version_dict(): XTENSA_ELF_ARCHIVE_PATTERN = XTENSA_ELF + '-' \ + (XTENSA_ELF_VERSION[len('esp-'):] if XTENSA_ELF_VERSION.startswith('esp-') else XTENSA_ELF_VERSION) -QEMU_RISCV_ARCHIVE_PATTERN = 'esp-' + QEMU_RISCV -QEMU_XTENSA_ARCHIVE_PATTERN = 'esp-' + QEMU_XTENSA - class TestUsage(unittest.TestCase): @classmethod def setUpClass(cls): + with open(os.path.join(os.getenv('IDF_PATH'), 'tools/tools.json'), 'r') as json_file: + tools_dict = json.load(json_file) + cls.tools_dict = tools_dict + old_tools_dir = os.environ.get('IDF_TOOLS_PATH') or os.path.expanduser(idf_tools.IDF_TOOLS_PATH_DEFAULT) mirror_prefix_map = None @@ -375,8 +376,8 @@ def test_tools_for_qemu_with_required(self): self.assert_tool_installed(output, XTENSA_ESP_GDB, XTENSA_ESP_GDB_VERSION) self.assert_tool_installed(output, RISCV_ESP_GDB, RISCV_ESP_GDB_VERSION) self.assert_tool_installed(output, ESP_ROM_ELFS, ESP_ROM_ELFS_VERSION) - self.assert_tool_installed(output, QEMU_RISCV, QEMU_RISCV_VERSION, QEMU_RISCV_ARCHIVE_PATTERN) - self.assert_tool_installed(output, QEMU_XTENSA, QEMU_XTENSA_VERSION, QEMU_XTENSA_ARCHIVE_PATTERN) + self.assert_tool_installed(output, QEMU_RISCV, QEMU_RISCV_VERSION) + self.assert_tool_installed(output, QEMU_XTENSA, QEMU_XTENSA_VERSION) self.assertIn('Destination: {}'.format(os.path.join(self.temp_tools_dir, 'dist')), output) self.assertEqual(required_tools_installed, output.count('Done')) @@ -455,6 +456,57 @@ def test_deactivate(self): self.assertTrue(os.path.isfile(deactivate_file), 'File {} was not found. '.format(deactivate_file)) self.assertNotEqual(os.stat(self.idf_env_json).st_size, 0, 'File {} is empty. '.format(deactivate_file)) + def test_export_recommended_version(self): + always_install_and_recommended_tools = [] + for tool in self.tools_dict['tools']: + if tool['install'] != 'always': + continue + for version in tool['versions']: + if version['status'] != 'recommended': + continue + always_install_and_recommended_tools.append({ + 'name': tool['name'], + 'version': version['name'] + }) + self.run_idf_tools_with_action(['install']) + output = self.run_idf_tools_with_action(['export']) + + for tool in always_install_and_recommended_tools: + self.assertIn(f"{tool['name']}/{tool['version']}", output) + + def test_export_recommended_version_cmake(self): + tool_to_test = 'cmake' + tool_version = '' + for tool in self.tools_dict['tools']: + if tool['name'] != tool_to_test: + continue + for version in tool['versions']: + if version['status'] == 'recommended': + tool_version = version['name'] + break + + self.run_idf_tools_with_action(['install']) + self.run_idf_tools_with_action(['install', tool_to_test]) + output = self.run_idf_tools_with_action(['export']) + + self.assertIn(f'{tool_to_test}/{tool_version}', output) + + def test_export_prefer_system_cmake(self): + tool_to_test = 'cmake' + self.run_idf_tools_with_action(['install']) + self.run_idf_tools_with_action(['install', tool_to_test]) + # cmake is installed via apt + output = self.run_idf_tools_with_action(['export', '--prefer-system']) + + self.assertNotIn(tool_to_test, output) + + def test_export_supported_version_cmake(self): + tool_to_test = 'cmake' + self.run_idf_tools_with_action(['install']) + output = self.run_idf_tools_with_action(['export']) + + self.assertNotIn(tool_to_test, output) + class TestMaintainer(unittest.TestCase): diff --git a/tools/test_mkdfu/pytest.ini b/tools/test_mkdfu/pytest.ini new file mode 100644 index 00000000000..d95e773e5cd --- /dev/null +++ b/tools/test_mkdfu/pytest.ini @@ -0,0 +1,12 @@ +[pytest] +addopts = -s -p no:pytest_embedded + +# log related +log_cli = True +log_cli_level = INFO +log_cli_format = %(asctime)s %(levelname)s %(message)s +log_cli_date_format = %Y-%m-%d %H:%M:%S + +## log all to `system-out` when case fail +junit_logging = stdout +junit_log_passing_tests = False diff --git a/tools/test_sbom/test_submodules.py b/tools/test_sbom/test_submodules.py deleted file mode 100644 index 85f76ab8502..00000000000 --- a/tools/test_sbom/test_submodules.py +++ /dev/null @@ -1,74 +0,0 @@ -# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -import os -from subprocess import run -from typing import Dict, List - - -def run_cmd(cmd: List[str]) -> str: - """Simple helper to run command and return it's stdout.""" - proc = run(cmd, capture_output=True, check=True, text=True) - return proc.stdout.strip() - - -def get_gitwdir() -> str: - """Return absolute path to the current git working tree.""" - return run_cmd(['git', 'rev-parse', '--show-toplevel']) - - -def get_submodules_config() -> Dict[str,Dict[str,str]]: - """Return dictionary, where key is submodule name and value - is a dictionary with variable:value pairs.""" - gitmodules_fn = os.path.join(get_gitwdir(), '.gitmodules') - gitmodules_data = run_cmd(['git', 'config', '--list', '--file', gitmodules_fn]) - prefix = 'submodule.' - config: Dict[str, Dict[str,str]] = {} - for line in gitmodules_data.splitlines(): - if not line.startswith(prefix): - continue - splitted = line.split('=', maxsplit=1) - if len(splitted) != 2: - continue - section, val = splitted - # remove "submodule." prefix - section = section[len(prefix):] - # split section into module name and variable - splitted = section.rsplit('.', maxsplit=1) - if len(splitted) != 2: - continue - module_name, var = splitted - if module_name not in config: - config[module_name] = {} - config[module_name][var] = val - - return config - - -def test_sha() -> None: - """ Check that submodule SHA in git-tree and .gitmodules match - if sbom-hash variable is available in the .gitmodules file. - """ - submodules = get_submodules_config() - - for name, variables in submodules.items(): - sbom_hash = variables.get('sbom-hash') - if not sbom_hash: - continue - module_path = variables.get('path') - if not module_path: - continue - output = run_cmd(['git', 'ls-tree', 'HEAD', module_path]) - if not output: - continue - module_hash = output.split()[2] - msg = (f'Submodule \"{name}\" SHA \"{module_hash}\" in git ' - f'tree does not match SHA \"{sbom_hash}\" recorded in .gitmodules. ' - f'Please update \"sbom-hash\" in .gitmodules for \"{name}\" ' - f'and also please do not forget to update version and other submodule ' - f'information if necessary. It is important to keep this information ' - f'up-to-date for SBOM generation.') - assert module_hash == sbom_hash, msg - - -if __name__ == '__main__': - test_sha() diff --git a/tools/tools.json b/tools/tools.json index bb87e25aafe..a1e844dfe13 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -26,51 +26,51 @@ "versions": [ { "linux-amd64": { - "sha256": "d056f2435ef05cccadac5d8fcefa3efd8f8c456c3d853f5eba1edb501acfe4f7", - "size": 32006939, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/xtensa-esp-elf-gdb-12.1_20221002-x86_64-linux-gnu.tar.gz" + "sha256": "d0743ec43cd92c35452a9097f7863281de4e72f04120d63cfbcf9d591a373529", + "size": 36942094, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/xtensa-esp-elf-gdb-12.1_20231023-x86_64-linux-gnu.tar.gz" }, "linux-arm64": { - "sha256": "7fc9674cc4f4c5e7bc94ca05bc5deaaa4c4bbcc972a9caee6fcd6a872c804c02", - "size": 32227425, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/xtensa-esp-elf-gdb-12.1_20221002-aarch64-linux-gnu.tar.gz" + "sha256": "bc1fac0366c6a08e26c45896ca21c8c90efc2cdd431b8ba084e8772e15502d0e", + "size": 37134601, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/xtensa-esp-elf-gdb-12.1_20231023-aarch64-linux-gnu.tar.gz" }, "linux-armel": { - "sha256": "68118ff36e9dd2284d92a7a529d0e2a8d20f6426036a0736fa1147935614ece2", - "size": 29960020, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/xtensa-esp-elf-gdb-12.1_20221002-arm-linux-gnueabi.tar.gz" + "sha256": "25efc51d52b71f097ccec763c5c885c8f5026b432fec4b5badd6a5f36fe34d04", + "size": 34579556, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/xtensa-esp-elf-gdb-12.1_20231023-arm-linux-gnueabi.tar.gz" }, "linux-armhf": { - "sha256": "72d75d9bb9a09d0696aa86628b2dd1851755216b1b315743189ea37228e5c72f", - "size": 27932265, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/xtensa-esp-elf-gdb-12.1_20221002-arm-linux-gnueabihf.tar.gz" + "sha256": "0f9ff39fdec4d8c9c1ef33149a3fcdd2cf1bae121529c507817c994d5ac38ca4", + "size": 32257457, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/xtensa-esp-elf-gdb-12.1_20231023-arm-linux-gnueabihf.tar.gz" }, "linux-i686": { - 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"sha256": "2d958570ff6aa69ed32cbb076cbaf303349a26b3301a7c4628be8d7ad39cf9f1", - "size": 29561472, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/xtensa-esp-elf-gdb-12.1_20221002-x86_64-w64-mingw32.zip" + "sha256": "13bb97f39173948d1cfb6e651d9b335ea9d52f1fdd0dda1eda3a2d23d8c63644", + "size": 33514906, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/xtensa-esp-elf-gdb-12.1_20231023-x86_64-w64-mingw32.zip" } } ] @@ -92,6 +92,7 @@ "esp32c3", "esp32c2", "esp32c6", + "esp32c5", "esp32h2", "esp32p4" ], @@ -103,51 +104,51 @@ "versions": [ { "linux-amd64": { - "sha256": "f0cf0821eaac7e8cf2c63b14f2b69d612f4f8c266b29d02d5547b7d7cbbd0e11", - "size": 32035173, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/riscv32-esp-elf-gdb-12.1_20221002-x86_64-linux-gnu.tar.gz" + "sha256": "2c78b806be176b1e449e07ff83429d38dfc39a13f89a127ac1ffa6c1230537a0", + "size": 36630145, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/riscv32-esp-elf-gdb-12.1_20231023-x86_64-linux-gnu.tar.gz" }, "linux-arm64": { - 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"name": "12.1_20221002", + "name": "12.1_20231023", "status": "recommended", "win32": { - "sha256": "8287fa2891e8d032e8283210048d653705791cda31504369418288d3e4753dd6", - "size": 27839143, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/riscv32-esp-elf-gdb-12.1_20221002-i686-w64-mingw32.zip" + "sha256": "4b42149a99dd87ee7e6dde25c99bad966c7f964253fa8f771593d7cef69f5602", + "size": 31635103, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/riscv32-esp-elf-gdb-12.1_20231023-i686-w64-mingw32.zip" }, "win64": { - "sha256": "9debae1135df8f5868a9d945468f0480cdaab25f77ead6a55cc85142c4487abd", - "size": 29404989, - "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20221002/riscv32-esp-elf-gdb-12.1_20221002-x86_64-w64-mingw32.zip" + "sha256": "728231546ad5006d34463f972658b2a89e52f660a42abab08a29bedd4a8046ad", + "size": 33400816, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v12.1_20231023/riscv32-esp-elf-gdb-12.1_20231023-x86_64-w64-mingw32.zip" } } ] @@ -247,6 +248,7 @@ "esp32c3", "esp32c2", "esp32c6", + "esp32c5", "esp32h2" ], "version_cmd": [ @@ -311,6 +313,7 @@ "esp32c3", "esp32c2", "esp32c6", + "esp32c5", "esp32h2" ], "version_cmd": [ @@ -885,16 +888,36 @@ "qemu-system-xtensa", "--version" ], - "version_regex": "QEMU emulator version ([a-z0-9.-_]+)", + "version_regex": "QEMU emulator version [0-9.]+ \\(([a-z0-9.-_]+)\\)", "versions": [ { "linux-amd64": { - "sha256": "a7e5e779fd593cb15f6d197034dc2fb427ed9165a4743e2febc6f6a47dfcc618", - "size": 45962695, - "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.0.0-20230522/esp-qemu-xtensa-softmmu-develop_8.0.0_20230522-x86_64-linux-gnu.tar.bz2" + "sha256": "88176f41c2fb17448372b4a120109275270c0e6bc49af4938f9f82d48e02f126", + "size": 14537932, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-xtensa-softmmu-esp_develop_8.1.3_20231206-x86_64-linux-gnu.tar.xz" }, - "name": "8.0.0", - "status": "recommended" + "linux-arm64": { + "sha256": "37e15a038456e9692394e7ab7faf4d8e04b937476bb22c346e7ce0aaa579a003", + "size": 14084300, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-xtensa-softmmu-esp_develop_8.1.3_20231206-aarch64-linux-gnu.tar.xz" + }, + "macos": { + "sha256": "e9321b29f59aa5c5f8d713ddcde301e46348493cdbf2dc12df2e047e6f456b58", + "size": 3345216, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-xtensa-softmmu-esp_develop_8.1.3_20231206-x86_64-apple-darwin.tar.xz" + }, + "macos-arm64": { + "sha256": "ab5f2c0c7f9428dfdd970f1cd9cac66e9d455e4ba87308d42882f43580433cd6", + "size": 3150564, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-xtensa-softmmu-esp_develop_8.1.3_20231206-aarch64-apple-darwin.tar.xz" + }, + "name": "esp_develop_8.1.3_20231206", + "status": "recommended", + "win64": { + "sha256": "cc1b0f87317e92aad71b40c409f404ce6df83bec0752feb6429eae65af606ae5", + "size": 32314176, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-xtensa-softmmu-esp_develop_8.1.3_20231206-x86_64-w64-mingw32.tar.xz" + } } ] }, @@ -918,16 +941,36 @@ "qemu-system-riscv32", "--version" ], - "version_regex": "QEMU emulator version ([a-z0-9.-_]+)", + "version_regex": "QEMU emulator version [0-9.]+ \\(([a-z0-9.-_]+)\\)", "versions": [ { "linux-amd64": { - "sha256": "bc7607720ff3d7e3d39f3e1810b8795f376f4b9cf3783c8f2ed3f7f14ba74717", - "size": 47175493, - "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.0.0-20230522/esp-qemu-riscv32-softmmu-develop_8.0.0_20230522-x86_64-linux-gnu.tar.bz2" + "sha256": "88373441ce34d598da372e313f2ff0d6a6bed9a11f8152a2dde0be1cc89b917f", + "size": 15931252, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-riscv32-softmmu-esp_develop_8.1.3_20231206-x86_64-linux-gnu.tar.xz" }, - "name": "8.0.0", - "status": "recommended" + "linux-arm64": { + "sha256": "925be5f64c27fad9b982fb24870119fe2af7d1aa36b3607044f5db4d83633f8c", + "size": 15433748, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-riscv32-softmmu-esp_develop_8.1.3_20231206-aarch64-linux-gnu.tar.xz" + }, + "macos": { + "sha256": "02fb7a928fe2f35debb561a1531458ef756c1b7dc2226afdb464eba81392920b", + "size": 3431904, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-riscv32-softmmu-esp_develop_8.1.3_20231206-x86_64-apple-darwin.tar.xz" + }, + "macos-arm64": { + "sha256": "2a5836a02070964d05b947220906575e2f6a88dd68473eea72622705cb18105b", + "size": 3152032, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-riscv32-softmmu-esp_develop_8.1.3_20231206-aarch64-apple-darwin.tar.xz" + }, + "name": "esp_develop_8.1.3_20231206", + "status": "recommended", + "win64": { + "sha256": "8ecef3ccb770cce5b82c0683c318eedd6da288d878151c7d002d89ae64e7c1bb", + "size": 34976352, + "url": "https://github.com/espressif/qemu/releases/download/esp-develop-8.1.3-20231206/qemu-riscv32-softmmu-esp_develop_8.1.3_20231206-x86_64-w64-mingw32.tar.xz" + } } ] } diff --git a/tools/unit-test-app/components/test_utils/CMakeLists.txt b/tools/unit-test-app/components/test_utils/CMakeLists.txt index 860cbf717fb..9ce3a99d9e3 100644 --- a/tools/unit-test-app/components/test_utils/CMakeLists.txt +++ b/tools/unit-test-app/components/test_utils/CMakeLists.txt @@ -16,7 +16,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS include REQUIRES esp_partition idf_test cmock - PRIV_REQUIRES perfmon esp_driver_pcnt esp_driver_gptimer esp_netif - driver # TODO: replace with esp_driver_rmt - ) + PRIV_REQUIRES perfmon esp_driver_pcnt esp_driver_gptimer esp_driver_rmt esp_netif) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/tools/unit-test-app/components/test_utils/Kconfig b/tools/unit-test-app/components/test_utils/Kconfig index eb5770cea79..1b68b3ea6d5 100644 --- a/tools/unit-test-app/components/test_utils/Kconfig +++ b/tools/unit-test-app/components/test_utils/Kconfig @@ -18,7 +18,7 @@ menu "IDF unit test" config UNITY_CRITICAL_LEAK_LEVEL_GENERAL int "Critical leak" - default 1024 + default 1200 config UNITY_CRITICAL_LEAK_LEVEL_LWIP int "Critical leak for UT which use LWIP component" diff --git a/tools/unit-test-app/components/test_utils/include/memory_checks.h b/tools/unit-test-app/components/test_utils/include/memory_checks.h index 636757e246a..2546e1a0a54 100644 --- a/tools/unit-test-app/components/test_utils/include/memory_checks.h +++ b/tools/unit-test-app/components/test_utils/include/memory_checks.h @@ -36,7 +36,7 @@ typedef enum { * @brief Adjust the memory leak thresholds for unit tests. * * Usually, unit tests will check if memory is leaked. Some functionality used by unit tests may unavoidably - * leak memory. This is why there is a default threshold for memory leaks (currently 1024 bytes). + * leak memory. This is why there is a default threshold for memory leaks (currently 1200 bytes). * Within this range, the number of bytes leaked will be visually reported on the terminal, but no test failure will * be triggered. Any memory leak above the default threshold will trigger a unit test failure. * This function allows to adjust that memory leak threshold.