From f6aadd1e399c5eeb929815f922c8ce211d5888c2 Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Thu, 13 Apr 2023 14:17:15 +0530 Subject: [PATCH 1/2] esp_hw_support: Update memory ptr location/property checks - to acknowledge the unused DCACHE added to DRAM for ESP32-S3 - For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB (from 0x3C000000). - But, if we try allocating memory from the 16 kB block and run an `esp_ptr_internal` check on that memory pointer, it fails as the address block from 0x3C000000 corresponds to the external memory symbols SOC_DROM_LOW and SOC_EXTRAM_DATA_LOW. (E.g. freertos - If the IDLE task stack buffer gets allocated from this region, the firmware will abort due to this failure). - Thus, the checks `esp_ptr_internal`, `esp_ptr_in_drom` and `esp_ptr_byte_accessible` have been updated to acknowledge this memory as a part of the DRAM. Co-authored-by: Mahavir Jain --- components/esp_hw_support/esp_memory_utils.c | 9 ++++++++ .../esp_hw_support/include/esp_memory_utils.h | 23 ++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/components/esp_hw_support/esp_memory_utils.c b/components/esp_hw_support/esp_memory_utils.c index cf12a11f6aec..766ca5a2c183 100644 --- a/components/esp_hw_support/esp_memory_utils.c +++ b/components/esp_hw_support/esp_memory_utils.c @@ -42,6 +42,15 @@ bool esp_ptr_byte_accessible(const void *p) #endif #if CONFIG_SPIRAM r |= esp_psram_check_ptr_addr(p); +#endif +#if CONFIG_ESP32S3_DATA_CACHE_16KB + /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is + * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB + * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000). + * Though this memory lies in the external memory vaddr, it is no different + * from the internal RAM in terms of hardware attributes. It is a part of + * the internal RAM when added to the heap and is byte-accessible .*/ + r |= (ip >= SOC_DROM_LOW && ip < (SOC_DROM_LOW + 0x4000)); #endif return r; } diff --git a/components/esp_hw_support/include/esp_memory_utils.h b/components/esp_hw_support/include/esp_memory_utils.h index 4326a4f6f42f..188f14ea34d2 100644 --- a/components/esp_hw_support/include/esp_memory_utils.h +++ b/components/esp_hw_support/include/esp_memory_utils.h @@ -256,6 +256,17 @@ inline static bool esp_ptr_internal(const void *p) { * additional check is required */ r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH); #endif + +#if CONFIG_ESP32S3_DATA_CACHE_16KB + /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is + * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB + * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000). + * Though this memory lies in the external memory vaddr, it is no different + * from the internal RAM in terms of hardware attributes and it is a part of + * the internal RAM when added to the heap.*/ + r |= ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < (SOC_DROM_LOW + 0x4000)); +#endif + return r; } @@ -277,7 +288,17 @@ bool esp_ptr_external_ram(const void *p); */ __attribute__((always_inline)) inline static bool esp_ptr_in_drom(const void *p) { - return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH); + uint32_t drom_start_addr = SOC_DROM_LOW; +#if CONFIG_ESP32S3_DATA_CACHE_16KB + /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is + * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB + * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000). + * The drom_start_addr has to be moved by 0x4000 (16kB) to accomodate + * this addition. */ + drom_start_addr += 0x4000; +#endif + + return ((intptr_t)p >= drom_start_addr && (intptr_t)p < SOC_DROM_HIGH); } /** From 11d5550da3dd40dab8839ea1ed228d29f4e0c0cb Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Mon, 17 Apr 2023 10:49:06 +0530 Subject: [PATCH 2/2] soc/esp32s3: Fix the `SOC_MEM_INTERNAL_HIGH` value - As per the memory block diagram for ESP32-S3, the internal memory address ranges as follows: DRAM: 0x3FC88000 (== SOC_MEM_INTERNAL_LOW) <-> 0x3FCF0000 IRAM: 0x40378000 <-> 0x403E0000 (== SOC_MEM_INTERNAL_HIGH) --- components/soc/esp32s3/include/soc/soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index db00b6b87075..38c0ae248086 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -218,7 +218,7 @@ //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). #define SOC_MEM_INTERNAL_LOW 0x3FC88000 -#define SOC_MEM_INTERNAL_HIGH 0x403E2000 +#define SOC_MEM_INTERNAL_HIGH 0x403E0000 // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3fceb710