From 2f3d77162f1736f5afca81ab50de165cf20354ca Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 3 Nov 2022 10:53:53 -0700 Subject: [PATCH 1/4] Add new SVD for ESP32-C2 and regenerate --- esp32c2/src/dma/in_conf0_ch0.rs | 83 +++-- esp32c2/src/dma/in_conf1_ch0.rs | 17 +- esp32c2/src/dma/in_dscr_bf0_ch0.rs | 8 +- esp32c2/src/dma/in_dscr_bf1_ch0.rs | 8 +- esp32c2/src/dma/in_dscr_ch0.rs | 8 +- esp32c2/src/dma/in_err_eof_des_addr_ch0.rs | 8 +- esp32c2/src/dma/in_link_ch0.rs | 90 +++--- esp32c2/src/dma/in_peri_sel_ch0.rs | 16 +- esp32c2/src/dma/in_pop_ch0.rs | 24 +- esp32c2/src/dma/in_pri_ch0.rs | 16 +- esp32c2/src/dma/in_state_ch0.rs | 24 +- esp32c2/src/dma/in_suc_eof_des_addr_ch0.rs | 8 +- esp32c2/src/dma/infifo_status_ch0.rs | 64 ++-- esp32c2/src/dma/int_clr_ch0.rs | 117 +++---- esp32c2/src/dma/int_ena_ch0.rs | 221 ++++++------- esp32c2/src/dma/int_raw_ch0.rs | 104 +++--- esp32c2/src/dma/int_st_ch0.rs | 104 +++--- esp32c2/src/dma/out_conf0_ch0.rs | 98 +++--- esp32c2/src/dma/out_conf1_ch0.rs | 16 +- esp32c2/src/dma/out_dscr_bf0_ch0.rs | 8 +- esp32c2/src/dma/out_dscr_bf1_ch0.rs | 8 +- esp32c2/src/dma/out_dscr_ch0.rs | 8 +- esp32c2/src/dma/out_eof_bfr_des_addr_ch0.rs | 8 +- esp32c2/src/dma/out_eof_des_addr_ch0.rs | 8 +- esp32c2/src/dma/out_link_ch0.rs | 75 +++-- esp32c2/src/dma/out_peri_sel_ch0.rs | 16 +- esp32c2/src/dma/out_pri_ch0.rs | 17 +- esp32c2/src/dma/out_push_ch0.rs | 33 +- esp32c2/src/dma/out_state_ch0.rs | 24 +- esp32c2/src/dma/outfifo_status_ch0.rs | 56 ++-- esp32c2/src/i2c0.rs | 4 +- esp32c2/src/i2c0/rxfifo_start_addr.rs | 43 +-- esp32c2/src/i2c0/txfifo_start_addr.rs | 43 +-- esp32c2/src/spi0.rs | 8 +- esp32c2/src/spi0/din_mode.rs | 63 +--- esp32c2/src/spi0/din_num.rs | 63 +--- esp32c2/src/spi0/dout_mode.rs | 63 +--- esp32c2/src/spi0/timing_cali.rs | 57 +--- esp32c2/src/spi1.rs | 2 +- esp32c2/src/spi1/timing_cali.rs | 50 +-- esp32c2/src/spi2.rs | 6 +- esp32c2/src/spi2/ctrl.rs | 21 -- esp32c2/src/spi2/din_mode.rs | 98 +----- esp32c2/src/spi2/din_num.rs | 91 +----- esp32c2/src/spi2/dout_mode.rs | 98 +----- esp32c2/src/spi2/misc.rs | 35 -- esp32c2/src/spi2/user.rs | 14 - esp32c2/svd/esp32c2.base.svd | 337 ++++++++++++-------- 48 files changed, 844 insertions(+), 1547 deletions(-) diff --git a/esp32c2/src/dma/in_conf0_ch0.rs b/esp32c2/src/dma/in_conf0_ch0.rs index 7df2eb5398..5f1c0183e0 100644 --- a/esp32c2/src/dma/in_conf0_ch0.rs +++ b/esp32c2/src/dma/in_conf0_ch0.rs @@ -34,82 +34,79 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_RST_CH0` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH0_R = crate::BitReader; -#[doc = "Field `IN_RST_CH0` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `IN_LOOP_TEST_CH0` reader - reserved"] -pub type IN_LOOP_TEST_CH0_R = crate::BitReader; -#[doc = "Field `IN_LOOP_TEST_CH0` writer - reserved"] -pub type IN_LOOP_TEST_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `INDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `INDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DATA_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `IN_DATA_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `MEM_TRANS_EN_CH0` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH0_R = crate::BitReader; -#[doc = "Field `MEM_TRANS_EN_CH0` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH0_W<'a, const O: u8> = +#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `IN_LOOP_TEST` reader - reserved"] +pub type IN_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST` writer - reserved"] +pub type IN_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch0(&self) -> IN_RST_CH0_R { - IN_RST_CH0_R::new((self.bits & 1) != 0) + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch0(&self) -> IN_LOOP_TEST_CH0_R { - IN_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_loop_test(&self) -> IN_LOOP_TEST_R { + IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch0(&self) -> INDSCR_BURST_EN_CH0_R { - INDSCR_BURST_EN_CH0_R::new(((self.bits >> 2) & 1) != 0) + pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R { + INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch0(&self) -> IN_DATA_BURST_EN_CH0_R { - IN_DATA_BURST_EN_CH0_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R { + IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch0(&self) -> MEM_TRANS_EN_CH0_R { - MEM_TRANS_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R { + MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch0(&mut self) -> IN_RST_CH0_W<0> { - IN_RST_CH0_W::new(self) + pub fn in_rst(&mut self) -> IN_RST_W<0> { + IN_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch0(&mut self) -> IN_LOOP_TEST_CH0_W<1> { - IN_LOOP_TEST_CH0_W::new(self) + pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<1> { + IN_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch0(&mut self) -> INDSCR_BURST_EN_CH0_W<2> { - INDSCR_BURST_EN_CH0_W::new(self) + pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<2> { + INDSCR_BURST_EN_W::new(self) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch0(&mut self) -> IN_DATA_BURST_EN_CH0_W<3> { - IN_DATA_BURST_EN_CH0_W::new(self) + pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<3> { + IN_DATA_BURST_EN_W::new(self) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch0(&mut self) -> MEM_TRANS_EN_CH0_W<4> { - MEM_TRANS_EN_CH0_W::new(self) + pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<4> { + MEM_TRANS_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/in_conf1_ch0.rs b/esp32c2/src/dma/in_conf1_ch0.rs index 4a0361e357..9c3aad2cdd 100644 --- a/esp32c2/src/dma/in_conf1_ch0.rs +++ b/esp32c2/src/dma/in_conf1_ch0.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH0_R = crate::BitReader; -#[doc = "Field `IN_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF1_CH0_SPEC, bool, O>; +#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF1_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch0(&self) -> IN_CHECK_OWNER_CH0_R { - IN_CHECK_OWNER_CH0_R::new(((self.bits >> 12) & 1) != 0) + pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R { + IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch0(&mut self) -> IN_CHECK_OWNER_CH0_W<12> { - IN_CHECK_OWNER_CH0_W::new(self) + pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<12> { + IN_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/in_dscr_bf0_ch0.rs b/esp32c2/src/dma/in_dscr_bf0_ch0.rs index 9366e4d475..12c6135371 100644 --- a/esp32c2/src/dma/in_dscr_bf0_ch0.rs +++ b/esp32c2/src/dma/in_dscr_bf0_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF0_CH0` reader - The address of the last inlink descriptor x-1."] -pub type INLINK_DSCR_BF0_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] #[inline(always)] - pub fn inlink_dscr_bf0_ch0(&self) -> INLINK_DSCR_BF0_CH0_R { - INLINK_DSCR_BF0_CH0_R::new(self.bits) + pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R { + INLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF0_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf0_ch0](index.html) module"] diff --git a/esp32c2/src/dma/in_dscr_bf1_ch0.rs b/esp32c2/src/dma/in_dscr_bf1_ch0.rs index b0a20e860b..eb5866359c 100644 --- a/esp32c2/src/dma/in_dscr_bf1_ch0.rs +++ b/esp32c2/src/dma/in_dscr_bf1_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF1_CH0` reader - The address of the second-to-last inlink descriptor x-2."] -pub type INLINK_DSCR_BF1_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn inlink_dscr_bf1_ch0(&self) -> INLINK_DSCR_BF1_CH0_R { - INLINK_DSCR_BF1_CH0_R::new(self.bits) + pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R { + INLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF1_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf1_ch0](index.html) module"] diff --git a/esp32c2/src/dma/in_dscr_ch0.rs b/esp32c2/src/dma/in_dscr_ch0.rs index 25c4e20c25..dbcd90aed0 100644 --- a/esp32c2/src/dma/in_dscr_ch0.rs +++ b/esp32c2/src/dma/in_dscr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_CH0` reader - The address of the current inlink descriptor x."] -pub type INLINK_DSCR_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] #[inline(always)] - pub fn inlink_dscr_ch0(&self) -> INLINK_DSCR_CH0_R { - INLINK_DSCR_CH0_R::new(self.bits) + pub fn inlink_dscr(&self) -> INLINK_DSCR_R { + INLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_ch0](index.html) module"] diff --git a/esp32c2/src/dma/in_err_eof_des_addr_ch0.rs b/esp32c2/src/dma/in_err_eof_des_addr_ch0.rs index 33ad6dad0c..7ea488fb6c 100644 --- a/esp32c2/src/dma/in_err_eof_des_addr_ch0.rs +++ b/esp32c2/src/dma/in_err_eof_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] -pub type IN_ERR_EOF_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] #[inline(always)] - pub fn in_err_eof_des_addr_ch0(&self) -> IN_ERR_EOF_DES_ADDR_CH0_R { - IN_ERR_EOF_DES_ADDR_CH0_R::new(self.bits) + pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R { + IN_ERR_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_err_eof_des_addr_ch0](index.html) module"] diff --git a/esp32c2/src/dma/in_link_ch0.rs b/esp32c2/src/dma/in_link_ch0.rs index e6765036f3..bdd2862d31 100644 --- a/esp32c2/src/dma/in_link_ch0.rs +++ b/esp32c2/src/dma/in_link_ch0.rs @@ -34,88 +34,86 @@ impl From> for W { W(writer) } } -#[doc = "Field `INLINK_ADDR_CH0` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `INLINK_ADDR_CH0` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH0_W<'a, const O: u8> = +#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_LINK_CH0_SPEC, u32, u32, 20, O>; -#[doc = "Field `INLINK_AUTO_RET_CH0` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_AUTO_RET_CH0` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_STOP_CH0` reader - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_STOP_CH0` writer - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_START_CH0` reader - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_START_CH0` writer - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_RESTART_CH0` reader - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_RESTART_CH0` writer - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_PARK_CH0` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] -pub type INLINK_PARK_CH0_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_START` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_PARK` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch0(&self) -> INLINK_ADDR_CH0_R { - INLINK_ADDR_CH0_R::new((self.bits & 0x000f_ffff) as u32) + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch0(&self) -> INLINK_AUTO_RET_CH0_R { - INLINK_AUTO_RET_CH0_R::new(((self.bits >> 20) & 1) != 0) + pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R { + INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch0(&self) -> INLINK_STOP_CH0_R { - INLINK_STOP_CH0_R::new(((self.bits >> 21) & 1) != 0) + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch0(&self) -> INLINK_START_CH0_R { - INLINK_START_CH0_R::new(((self.bits >> 22) & 1) != 0) + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch0(&self) -> INLINK_RESTART_CH0_R { - INLINK_RESTART_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] #[inline(always)] - pub fn inlink_park_ch0(&self) -> INLINK_PARK_CH0_R { - INLINK_PARK_CH0_R::new(((self.bits >> 24) & 1) != 0) + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 24) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch0(&mut self) -> INLINK_ADDR_CH0_W<0> { - INLINK_ADDR_CH0_W::new(self) + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<0> { + INLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch0(&mut self) -> INLINK_AUTO_RET_CH0_W<20> { - INLINK_AUTO_RET_CH0_W::new(self) + pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<20> { + INLINK_AUTO_RET_W::new(self) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch0(&mut self) -> INLINK_STOP_CH0_W<21> { - INLINK_STOP_CH0_W::new(self) + pub fn inlink_stop(&mut self) -> INLINK_STOP_W<21> { + INLINK_STOP_W::new(self) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch0(&mut self) -> INLINK_START_CH0_W<22> { - INLINK_START_CH0_W::new(self) + pub fn inlink_start(&mut self) -> INLINK_START_W<22> { + INLINK_START_W::new(self) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch0(&mut self) -> INLINK_RESTART_CH0_W<23> { - INLINK_RESTART_CH0_W::new(self) + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<23> { + INLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/in_peri_sel_ch0.rs b/esp32c2/src/dma/in_peri_sel_ch0.rs index 1ff573e489..767077803f 100644 --- a/esp32c2/src/dma/in_peri_sel_ch0.rs +++ b/esp32c2/src/dma/in_peri_sel_ch0.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_IN_SEL_CH0` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH0_R = crate::FieldReader; -#[doc = "Field `PERI_IN_SEL_CH0` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH0_W<'a, const O: u8> = +#[doc = "Field `PERI_IN_SEL` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PERI_SEL_CH0_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch0(&self) -> PERI_IN_SEL_CH0_R { - PERI_IN_SEL_CH0_R::new((self.bits & 0x3f) as u8) + pub fn peri_in_sel(&self) -> PERI_IN_SEL_R { + PERI_IN_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch0(&mut self) -> PERI_IN_SEL_CH0_W<0> { - PERI_IN_SEL_CH0_W::new(self) + pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<0> { + PERI_IN_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/in_pop_ch0.rs b/esp32c2/src/dma/in_pop_ch0.rs index 2cffd56ebf..6b5dccd344 100644 --- a/esp32c2/src/dma/in_pop_ch0.rs +++ b/esp32c2/src/dma/in_pop_ch0.rs @@ -34,29 +34,29 @@ impl From> for W { W(writer) } } -#[doc = "Field `INFIFO_RDATA_CH0` reader - This register stores the data popping from DMA FIFO."] -pub type INFIFO_RDATA_CH0_R = crate::FieldReader; -#[doc = "Field `INFIFO_POP_CH0` reader - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH0_R = crate::BitReader; -#[doc = "Field `INFIFO_POP_CH0` writer - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_RDATA` reader - This register stores the data popping from DMA FIFO."] +pub type INFIFO_RDATA_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP` reader - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_R = crate::BitReader; +#[doc = "Field `INFIFO_POP` writer - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH0_SPEC, bool, O>; impl R { #[doc = "Bits 0:11 - This register stores the data popping from DMA FIFO."] #[inline(always)] - pub fn infifo_rdata_ch0(&self) -> INFIFO_RDATA_CH0_R { - INFIFO_RDATA_CH0_R::new((self.bits & 0x0fff) as u16) + pub fn infifo_rdata(&self) -> INFIFO_RDATA_R { + INFIFO_RDATA_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch0(&self) -> INFIFO_POP_CH0_R { - INFIFO_POP_CH0_R::new(((self.bits >> 12) & 1) != 0) + pub fn infifo_pop(&self) -> INFIFO_POP_R { + INFIFO_POP_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch0(&mut self) -> INFIFO_POP_CH0_W<12> { - INFIFO_POP_CH0_W::new(self) + pub fn infifo_pop(&mut self) -> INFIFO_POP_W<12> { + INFIFO_POP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/in_pri_ch0.rs b/esp32c2/src/dma/in_pri_ch0.rs index 8bd43615d1..842e23c300 100644 --- a/esp32c2/src/dma/in_pri_ch0.rs +++ b/esp32c2/src/dma/in_pri_ch0.rs @@ -34,22 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `RX_PRI_CH0` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH0_R = crate::FieldReader; -#[doc = "Field `RX_PRI_CH0` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH0_SPEC, u8, u8, 4, O>; +#[doc = "Field `RX_PRI` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."] +pub type RX_PRI_R = crate::FieldReader; +#[doc = "Field `RX_PRI` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."] +pub type RX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH0_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch0(&self) -> RX_PRI_CH0_R { - RX_PRI_CH0_R::new((self.bits & 0x0f) as u8) + pub fn rx_pri(&self) -> RX_PRI_R { + RX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch0(&mut self) -> RX_PRI_CH0_W<0> { - RX_PRI_CH0_W::new(self) + pub fn rx_pri(&mut self) -> RX_PRI_W<0> { + RX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/in_state_ch0.rs b/esp32c2/src/dma/in_state_ch0.rs index 939a0c6ed1..8c3c533008 100644 --- a/esp32c2/src/dma/in_state_ch0.rs +++ b/esp32c2/src/dma/in_state_ch0.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_ADDR_CH0` reader - This register stores the current inlink descriptor's address."] -pub type INLINK_DSCR_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `IN_DSCR_STATE_CH0` reader - reserved"] -pub type IN_DSCR_STATE_CH0_R = crate::FieldReader; -#[doc = "Field `IN_STATE_CH0` reader - reserved"] -pub type IN_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - reserved"] +pub type IN_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] #[inline(always)] - pub fn inlink_dscr_addr_ch0(&self) -> INLINK_DSCR_ADDR_CH0_R { - INLINK_DSCR_ADDR_CH0_R::new((self.bits & 0x0003_ffff) as u32) + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn in_dscr_state_ch0(&self) -> IN_DSCR_STATE_CH0_R { - IN_DSCR_STATE_CH0_R::new(((self.bits >> 18) & 3) as u8) + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn in_state_ch0(&self) -> IN_STATE_CH0_R { - IN_STATE_CH0_R::new(((self.bits >> 20) & 7) as u8) + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_IN_STATE_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_state_ch0](index.html) module"] diff --git a/esp32c2/src/dma/in_suc_eof_des_addr_ch0.rs b/esp32c2/src/dma/in_suc_eof_des_addr_ch0.rs index ef3b4236e0..085ce1cdd5 100644 --- a/esp32c2/src/dma/in_suc_eof_des_addr_ch0.rs +++ b/esp32c2/src/dma/in_suc_eof_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] -pub type IN_SUC_EOF_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn in_suc_eof_des_addr_ch0(&self) -> IN_SUC_EOF_DES_ADDR_CH0_R { - IN_SUC_EOF_DES_ADDR_CH0_R::new(self.bits) + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_suc_eof_des_addr_ch0](index.html) module"] diff --git a/esp32c2/src/dma/infifo_status_ch0.rs b/esp32c2/src/dma/infifo_status_ch0.rs index 55394874ab..15fd809309 100644 --- a/esp32c2/src/dma/infifo_status_ch0.rs +++ b/esp32c2/src/dma/infifo_status_ch0.rs @@ -13,62 +13,62 @@ impl From> for R { R(reader) } } -#[doc = "Field `INFIFO_FULL_CH0` reader - L1 Rx FIFO full signal for Rx channel 0."] -pub type INFIFO_FULL_CH0_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_CH0` reader - L1 Rx FIFO empty signal for Rx channel 0."] -pub type INFIFO_EMPTY_CH0_R = crate::BitReader; -#[doc = "Field `INFIFO_CNT_CH0` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] -pub type INFIFO_CNT_CH0_R = crate::FieldReader; -#[doc = "Field `IN_REMAIN_UNDER_1B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_1B_CH0_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_2B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_2B_CH0_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_3B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_3B_CH0_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_4B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_4B_CH0_R = crate::BitReader; -#[doc = "Field `IN_BUF_HUNGRY_CH0` reader - reserved"] -pub type IN_BUF_HUNGRY_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL` reader - L1 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_FULL_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY` reader - L1 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] +pub type INFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `IN_REMAIN_UNDER_1B` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY` reader - reserved"] +pub type IN_BUF_HUNGRY_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 0."] #[inline(always)] - pub fn infifo_full_ch0(&self) -> INFIFO_FULL_CH0_R { - INFIFO_FULL_CH0_R::new((self.bits & 1) != 0) + pub fn infifo_full(&self) -> INFIFO_FULL_R { + INFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 0."] #[inline(always)] - pub fn infifo_empty_ch0(&self) -> INFIFO_EMPTY_CH0_R { - INFIFO_EMPTY_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn infifo_empty(&self) -> INFIFO_EMPTY_R { + INFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] #[inline(always)] - pub fn infifo_cnt_ch0(&self) -> INFIFO_CNT_CH0_R { - INFIFO_CNT_CH0_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn infifo_cnt(&self) -> INFIFO_CNT_R { + INFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn in_remain_under_1b_ch0(&self) -> IN_REMAIN_UNDER_1B_CH0_R { - IN_REMAIN_UNDER_1B_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn in_remain_under_1b(&self) -> IN_REMAIN_UNDER_1B_R { + IN_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn in_remain_under_2b_ch0(&self) -> IN_REMAIN_UNDER_2B_CH0_R { - IN_REMAIN_UNDER_2B_CH0_R::new(((self.bits >> 24) & 1) != 0) + pub fn in_remain_under_2b(&self) -> IN_REMAIN_UNDER_2B_R { + IN_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn in_remain_under_3b_ch0(&self) -> IN_REMAIN_UNDER_3B_CH0_R { - IN_REMAIN_UNDER_3B_CH0_R::new(((self.bits >> 25) & 1) != 0) + pub fn in_remain_under_3b(&self) -> IN_REMAIN_UNDER_3B_R { + IN_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn in_remain_under_4b_ch0(&self) -> IN_REMAIN_UNDER_4B_CH0_R { - IN_REMAIN_UNDER_4B_CH0_R::new(((self.bits >> 26) & 1) != 0) + pub fn in_remain_under_4b(&self) -> IN_REMAIN_UNDER_4B_R { + IN_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - reserved"] #[inline(always)] - pub fn in_buf_hungry_ch0(&self) -> IN_BUF_HUNGRY_CH0_R { - IN_BUF_HUNGRY_CH0_R::new(((self.bits >> 27) & 1) != 0) + pub fn in_buf_hungry(&self) -> IN_BUF_HUNGRY_R { + IN_BUF_HUNGRY_R::new(((self.bits >> 27) & 1) != 0) } } #[doc = "DMA_INFIFO_STATUS_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [infifo_status_ch0](index.html) module"] diff --git a/esp32c2/src/dma/int_clr_ch0.rs b/esp32c2/src/dma/int_clr_ch0.rs index 8ebe2e6e31..f4fdd0ea07 100644 --- a/esp32c2/src/dma/int_clr_ch0.rs +++ b/esp32c2/src/dma/int_clr_ch0.rs @@ -19,110 +19,97 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH0_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH0_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH0_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH0_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH0_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; impl W { #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_clr(&mut self) -> IN_DONE_CH0_INT_CLR_W<0> { - IN_DONE_CH0_INT_CLR_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_clr(&mut self) -> IN_SUC_EOF_CH0_INT_CLR_W<1> { - IN_SUC_EOF_CH0_INT_CLR_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_clr(&mut self) -> IN_ERR_EOF_CH0_INT_CLR_W<2> { - IN_ERR_EOF_CH0_INT_CLR_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_clr(&mut self) -> OUT_DONE_CH0_INT_CLR_W<3> { - OUT_DONE_CH0_INT_CLR_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_clr(&mut self) -> OUT_EOF_CH0_INT_CLR_W<4> { - OUT_EOF_CH0_INT_CLR_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_clr(&mut self) -> IN_DSCR_ERR_CH0_INT_CLR_W<5> { - IN_DSCR_ERR_CH0_INT_CLR_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_clr(&mut self) -> OUT_DSCR_ERR_CH0_INT_CLR_W<6> { - OUT_DSCR_ERR_CH0_INT_CLR_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_clr(&mut self) -> IN_DSCR_EMPTY_CH0_INT_CLR_W<7> { - IN_DSCR_EMPTY_CH0_INT_CLR_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_clr(&mut self) -> OUT_TOTAL_EOF_CH0_INT_CLR_W<8> { - OUT_TOTAL_EOF_CH0_INT_CLR_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_clr(&mut self) -> INFIFO_OVF_CH0_INT_CLR_W<9> { - INFIFO_OVF_CH0_INT_CLR_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_clr(&mut self) -> INFIFO_UDF_CH0_INT_CLR_W<10> { - INFIFO_UDF_CH0_INT_CLR_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_clr(&mut self) -> OUTFIFO_OVF_CH0_INT_CLR_W<11> { - OUTFIFO_OVF_CH0_INT_CLR_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_clr(&mut self) -> OUTFIFO_UDF_CH0_INT_CLR_W<12> { - OUTFIFO_UDF_CH0_INT_CLR_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/int_ena_ch0.rs b/esp32c2/src/dma/int_ena_ch0.rs index a64fb12eb0..da49b3e694 100644 --- a/esp32c2/src/dma/int_ena_ch0.rs +++ b/esp32c2/src/dma/int_ena_ch0.rs @@ -34,203 +34,190 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DONE_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_ena(&self) -> IN_DONE_CH0_INT_ENA_R { - IN_DONE_CH0_INT_ENA_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_ena(&self) -> IN_SUC_EOF_CH0_INT_ENA_R { - IN_SUC_EOF_CH0_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_ena(&self) -> IN_ERR_EOF_CH0_INT_ENA_R { - IN_ERR_EOF_CH0_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_ena(&self) -> OUT_DONE_CH0_INT_ENA_R { - OUT_DONE_CH0_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_ena(&self) -> OUT_EOF_CH0_INT_ENA_R { - OUT_EOF_CH0_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_ena(&self) -> IN_DSCR_ERR_CH0_INT_ENA_R { - IN_DSCR_ERR_CH0_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_ena(&self) -> OUT_DSCR_ERR_CH0_INT_ENA_R { - OUT_DSCR_ERR_CH0_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_ena(&self) -> IN_DSCR_EMPTY_CH0_INT_ENA_R { - IN_DSCR_EMPTY_CH0_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_ena(&self) -> OUT_TOTAL_EOF_CH0_INT_ENA_R { - OUT_TOTAL_EOF_CH0_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_ena(&self) -> INFIFO_OVF_CH0_INT_ENA_R { - INFIFO_OVF_CH0_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_ena(&self) -> INFIFO_UDF_CH0_INT_ENA_R { - INFIFO_UDF_CH0_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_ena(&self) -> OUTFIFO_OVF_CH0_INT_ENA_R { - OUTFIFO_OVF_CH0_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_ena(&self) -> OUTFIFO_UDF_CH0_INT_ENA_R { - OUTFIFO_UDF_CH0_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_ena(&mut self) -> IN_DONE_CH0_INT_ENA_W<0> { - IN_DONE_CH0_INT_ENA_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_ena(&mut self) -> IN_SUC_EOF_CH0_INT_ENA_W<1> { - IN_SUC_EOF_CH0_INT_ENA_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_ena(&mut self) -> IN_ERR_EOF_CH0_INT_ENA_W<2> { - IN_ERR_EOF_CH0_INT_ENA_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_ena(&mut self) -> OUT_DONE_CH0_INT_ENA_W<3> { - OUT_DONE_CH0_INT_ENA_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_ena(&mut self) -> OUT_EOF_CH0_INT_ENA_W<4> { - OUT_EOF_CH0_INT_ENA_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_ena(&mut self) -> IN_DSCR_ERR_CH0_INT_ENA_W<5> { - IN_DSCR_ERR_CH0_INT_ENA_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_ena(&mut self) -> OUT_DSCR_ERR_CH0_INT_ENA_W<6> { - OUT_DSCR_ERR_CH0_INT_ENA_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_ena(&mut self) -> IN_DSCR_EMPTY_CH0_INT_ENA_W<7> { - IN_DSCR_EMPTY_CH0_INT_ENA_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_ena(&mut self) -> OUT_TOTAL_EOF_CH0_INT_ENA_W<8> { - OUT_TOTAL_EOF_CH0_INT_ENA_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_ena(&mut self) -> INFIFO_OVF_CH0_INT_ENA_W<9> { - INFIFO_OVF_CH0_INT_ENA_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_ena(&mut self) -> INFIFO_UDF_CH0_INT_ENA_W<10> { - INFIFO_UDF_CH0_INT_ENA_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_ena(&mut self) -> OUTFIFO_OVF_CH0_INT_ENA_W<11> { - OUTFIFO_OVF_CH0_INT_ENA_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_ena(&mut self) -> OUTFIFO_UDF_CH0_INT_ENA_W<12> { - OUTFIFO_UDF_CH0_INT_ENA_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/int_raw_ch0.rs b/esp32c2/src/dma/int_raw_ch0.rs index dfe856e5f6..0566103b95 100644 --- a/esp32c2/src/dma/int_raw_ch0.rs +++ b/esp32c2/src/dma/int_raw_ch0.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] -pub type IN_DONE_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] -pub type IN_SUC_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] -pub type IN_ERR_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] -pub type OUT_DONE_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] -pub type OUT_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] -pub type IN_DSCR_ERR_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] -pub type OUT_DSCR_ERR_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] -pub type IN_DSCR_EMPTY_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] -pub type OUT_TOTAL_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] -pub type INFIFO_OVF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] -pub type INFIFO_UDF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] -pub type OUTFIFO_OVF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] -pub type OUTFIFO_UDF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] #[inline(always)] - pub fn in_done_ch0_int_raw(&self) -> IN_DONE_CH0_INT_RAW_R { - IN_DONE_CH0_INT_RAW_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] #[inline(always)] - pub fn in_suc_eof_ch0_int_raw(&self) -> IN_SUC_EOF_CH0_INT_RAW_R { - IN_SUC_EOF_CH0_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] #[inline(always)] - pub fn in_err_eof_ch0_int_raw(&self) -> IN_ERR_EOF_CH0_INT_RAW_R { - IN_ERR_EOF_CH0_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] #[inline(always)] - pub fn out_done_ch0_int_raw(&self) -> OUT_DONE_CH0_INT_RAW_R { - OUT_DONE_CH0_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] #[inline(always)] - pub fn out_eof_ch0_int_raw(&self) -> OUT_EOF_CH0_INT_RAW_R { - OUT_EOF_CH0_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] #[inline(always)] - pub fn in_dscr_err_ch0_int_raw(&self) -> IN_DSCR_ERR_CH0_INT_RAW_R { - IN_DSCR_ERR_CH0_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] #[inline(always)] - pub fn out_dscr_err_ch0_int_raw(&self) -> OUT_DSCR_ERR_CH0_INT_RAW_R { - OUT_DSCR_ERR_CH0_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_raw(&self) -> IN_DSCR_EMPTY_CH0_INT_RAW_R { - IN_DSCR_EMPTY_CH0_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] #[inline(always)] - pub fn out_total_eof_ch0_int_raw(&self) -> OUT_TOTAL_EOF_CH0_INT_RAW_R { - OUT_TOTAL_EOF_CH0_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] #[inline(always)] - pub fn infifo_ovf_ch0_int_raw(&self) -> INFIFO_OVF_CH0_INT_RAW_R { - INFIFO_OVF_CH0_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] #[inline(always)] - pub fn infifo_udf_ch0_int_raw(&self) -> INFIFO_UDF_CH0_INT_RAW_R { - INFIFO_UDF_CH0_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_raw(&self) -> OUTFIFO_OVF_CH0_INT_RAW_R { - OUTFIFO_OVF_CH0_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] #[inline(always)] - pub fn outfifo_udf_ch0_int_raw(&self) -> OUTFIFO_UDF_CH0_INT_RAW_R { - OUTFIFO_UDF_CH0_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_RAW_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_raw_ch0](index.html) module"] diff --git a/esp32c2/src/dma/int_st_ch0.rs b/esp32c2/src/dma/int_st_ch0.rs index e5291f100b..6f85717045 100644 --- a/esp32c2/src/dma/int_st_ch0.rs +++ b/esp32c2/src/dma/int_st_ch0.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_st(&self) -> IN_DONE_CH0_INT_ST_R { - IN_DONE_CH0_INT_ST_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_st(&self) -> IN_SUC_EOF_CH0_INT_ST_R { - IN_SUC_EOF_CH0_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_st(&self) -> IN_ERR_EOF_CH0_INT_ST_R { - IN_ERR_EOF_CH0_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_st(&self) -> OUT_DONE_CH0_INT_ST_R { - OUT_DONE_CH0_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_st(&self) -> OUT_EOF_CH0_INT_ST_R { - OUT_EOF_CH0_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_st(&self) -> IN_DSCR_ERR_CH0_INT_ST_R { - IN_DSCR_ERR_CH0_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_st(&self) -> OUT_DSCR_ERR_CH0_INT_ST_R { - OUT_DSCR_ERR_CH0_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_st(&self) -> IN_DSCR_EMPTY_CH0_INT_ST_R { - IN_DSCR_EMPTY_CH0_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_st(&self) -> OUT_TOTAL_EOF_CH0_INT_ST_R { - OUT_TOTAL_EOF_CH0_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_st(&self) -> INFIFO_OVF_CH0_INT_ST_R { - INFIFO_OVF_CH0_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_st(&self) -> INFIFO_UDF_CH0_INT_ST_R { - INFIFO_UDF_CH0_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_st(&self) -> OUTFIFO_OVF_CH0_INT_ST_R { - OUTFIFO_OVF_CH0_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_st(&self) -> OUTFIFO_UDF_CH0_INT_ST_R { - OUTFIFO_UDF_CH0_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_ST_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_st_ch0](index.html) module"] diff --git a/esp32c2/src/dma/out_conf0_ch0.rs b/esp32c2/src/dma/out_conf0_ch0.rs index fbb33881ae..0861900968 100644 --- a/esp32c2/src/dma/out_conf0_ch0.rs +++ b/esp32c2/src/dma/out_conf0_ch0.rs @@ -34,97 +34,95 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_RST_CH0` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH0_R = crate::BitReader; -#[doc = "Field `OUT_RST_CH0` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_LOOP_TEST_CH0` reader - reserved"] -pub type OUT_LOOP_TEST_CH0_R = crate::BitReader; -#[doc = "Field `OUT_LOOP_TEST_CH0` writer - reserved"] -pub type OUT_LOOP_TEST_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_LOOP_TEST` reader - reserved"] +pub type OUT_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST` writer - reserved"] +pub type OUT_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_AUTO_WRBACK_CH0` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH0_R = crate::BitReader; -#[doc = "Field `OUT_AUTO_WRBACK_CH0` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_MODE_CH0` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH0_R = crate::BitReader; -#[doc = "Field `OUT_EOF_MODE_CH0` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUTDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `OUTDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DATA_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `OUT_DATA_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch0(&self) -> OUT_RST_CH0_R { - OUT_RST_CH0_R::new((self.bits & 1) != 0) + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch0(&self) -> OUT_LOOP_TEST_CH0_R { - OUT_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R { + OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch0(&self) -> OUT_AUTO_WRBACK_CH0_R { - OUT_AUTO_WRBACK_CH0_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch0(&self) -> OUT_EOF_MODE_CH0_R { - OUT_EOF_MODE_CH0_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R { + OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch0(&self) -> OUTDSCR_BURST_EN_CH0_R { - OUTDSCR_BURST_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R { + OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch0(&self) -> OUT_DATA_BURST_EN_CH0_R { - OUT_DATA_BURST_EN_CH0_R::new(((self.bits >> 5) & 1) != 0) + pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R { + OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch0(&mut self) -> OUT_RST_CH0_W<0> { - OUT_RST_CH0_W::new(self) + pub fn out_rst(&mut self) -> OUT_RST_W<0> { + OUT_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch0(&mut self) -> OUT_LOOP_TEST_CH0_W<1> { - OUT_LOOP_TEST_CH0_W::new(self) + pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<1> { + OUT_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch0(&mut self) -> OUT_AUTO_WRBACK_CH0_W<2> { - OUT_AUTO_WRBACK_CH0_W::new(self) + pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<2> { + OUT_AUTO_WRBACK_W::new(self) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch0(&mut self) -> OUT_EOF_MODE_CH0_W<3> { - OUT_EOF_MODE_CH0_W::new(self) + pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<3> { + OUT_EOF_MODE_W::new(self) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch0(&mut self) -> OUTDSCR_BURST_EN_CH0_W<4> { - OUTDSCR_BURST_EN_CH0_W::new(self) + pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<4> { + OUTDSCR_BURST_EN_W::new(self) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch0(&mut self) -> OUT_DATA_BURST_EN_CH0_W<5> { - OUT_DATA_BURST_EN_CH0_W::new(self) + pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<5> { + OUT_DATA_BURST_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/out_conf1_ch0.rs b/esp32c2/src/dma/out_conf1_ch0.rs index ac54027fed..a6904b8d47 100644 --- a/esp32c2/src/dma/out_conf1_ch0.rs +++ b/esp32c2/src/dma/out_conf1_ch0.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH0_R = crate::BitReader; -#[doc = "Field `OUT_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF1_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch0(&self) -> OUT_CHECK_OWNER_CH0_R { - OUT_CHECK_OWNER_CH0_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_check_owner(&self) -> OUT_CHECK_OWNER_R { + OUT_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch0(&mut self) -> OUT_CHECK_OWNER_CH0_W<12> { - OUT_CHECK_OWNER_CH0_W::new(self) + pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<12> { + OUT_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/out_dscr_bf0_ch0.rs b/esp32c2/src/dma/out_dscr_bf0_ch0.rs index 611104a0f1..3f61fdee2a 100644 --- a/esp32c2/src/dma/out_dscr_bf0_ch0.rs +++ b/esp32c2/src/dma/out_dscr_bf0_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF0_CH0` reader - The address of the last outlink descriptor y-1."] -pub type OUTLINK_DSCR_BF0_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] #[inline(always)] - pub fn outlink_dscr_bf0_ch0(&self) -> OUTLINK_DSCR_BF0_CH0_R { - OUTLINK_DSCR_BF0_CH0_R::new(self.bits) + pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R { + OUTLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF0_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf0_ch0](index.html) module"] diff --git a/esp32c2/src/dma/out_dscr_bf1_ch0.rs b/esp32c2/src/dma/out_dscr_bf1_ch0.rs index 291ad971c4..d06bd723c5 100644 --- a/esp32c2/src/dma/out_dscr_bf1_ch0.rs +++ b/esp32c2/src/dma/out_dscr_bf1_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF1_CH0` reader - The address of the second-to-last inlink descriptor x-2."] -pub type OUTLINK_DSCR_BF1_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn outlink_dscr_bf1_ch0(&self) -> OUTLINK_DSCR_BF1_CH0_R { - OUTLINK_DSCR_BF1_CH0_R::new(self.bits) + pub fn outlink_dscr_bf1(&self) -> OUTLINK_DSCR_BF1_R { + OUTLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF1_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf1_ch0](index.html) module"] diff --git a/esp32c2/src/dma/out_dscr_ch0.rs b/esp32c2/src/dma/out_dscr_ch0.rs index 583bc7fb3d..cc02002e38 100644 --- a/esp32c2/src/dma/out_dscr_ch0.rs +++ b/esp32c2/src/dma/out_dscr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_CH0` reader - The address of the current outlink descriptor y."] -pub type OUTLINK_DSCR_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] #[inline(always)] - pub fn outlink_dscr_ch0(&self) -> OUTLINK_DSCR_CH0_R { - OUTLINK_DSCR_CH0_R::new(self.bits) + pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R { + OUTLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_ch0](index.html) module"] diff --git a/esp32c2/src/dma/out_eof_bfr_des_addr_ch0.rs b/esp32c2/src/dma/out_eof_bfr_des_addr_ch0.rs index ae1ad3ec5e..94b06d3bf3 100644 --- a/esp32c2/src/dma/out_eof_bfr_des_addr_ch0.rs +++ b/esp32c2/src/dma/out_eof_bfr_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH0` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] -pub type OUT_EOF_BFR_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] #[inline(always)] - pub fn out_eof_bfr_des_addr_ch0(&self) -> OUT_EOF_BFR_DES_ADDR_CH0_R { - OUT_EOF_BFR_DES_ADDR_CH0_R::new(self.bits) + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_bfr_des_addr_ch0](index.html) module"] diff --git a/esp32c2/src/dma/out_eof_des_addr_ch0.rs b/esp32c2/src/dma/out_eof_des_addr_ch0.rs index 371d95647d..d5e778bf01 100644 --- a/esp32c2/src/dma/out_eof_des_addr_ch0.rs +++ b/esp32c2/src/dma/out_eof_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_DES_ADDR_CH0` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] -pub type OUT_EOF_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn out_eof_des_addr_ch0(&self) -> OUT_EOF_DES_ADDR_CH0_R { - OUT_EOF_DES_ADDR_CH0_R::new(self.bits) + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_des_addr_ch0](index.html) module"] diff --git a/esp32c2/src/dma/out_link_ch0.rs b/esp32c2/src/dma/out_link_ch0.rs index 66579d55e7..9b659381ef 100644 --- a/esp32c2/src/dma/out_link_ch0.rs +++ b/esp32c2/src/dma/out_link_ch0.rs @@ -34,75 +34,72 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTLINK_ADDR_CH0` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `OUTLINK_ADDR_CH0` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH0_W<'a, const O: u8> = +#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_LINK_CH0_SPEC, u32, u32, 20, O>; -#[doc = "Field `OUTLINK_STOP_CH0` reader - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH0_R = crate::BitReader; -#[doc = "Field `OUTLINK_STOP_CH0` writer - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `OUTLINK_START_CH0` reader - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH0_R = crate::BitReader; -#[doc = "Field `OUTLINK_START_CH0` writer - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `OUTLINK_RESTART_CH0` reader - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH0_R = crate::BitReader; -#[doc = "Field `OUTLINK_RESTART_CH0` writer - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `OUTLINK_PARK_CH0` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] -pub type OUTLINK_PARK_CH0_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `OUTLINK_PARK` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch0(&self) -> OUTLINK_ADDR_CH0_R { - OUTLINK_ADDR_CH0_R::new((self.bits & 0x000f_ffff) as u32) + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch0(&self) -> OUTLINK_STOP_CH0_R { - OUTLINK_STOP_CH0_R::new(((self.bits >> 20) & 1) != 0) + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch0(&self) -> OUTLINK_START_CH0_R { - OUTLINK_START_CH0_R::new(((self.bits >> 21) & 1) != 0) + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch0(&self) -> OUTLINK_RESTART_CH0_R { - OUTLINK_RESTART_CH0_R::new(((self.bits >> 22) & 1) != 0) + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] #[inline(always)] - pub fn outlink_park_ch0(&self) -> OUTLINK_PARK_CH0_R { - OUTLINK_PARK_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch0(&mut self) -> OUTLINK_ADDR_CH0_W<0> { - OUTLINK_ADDR_CH0_W::new(self) + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<0> { + OUTLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch0(&mut self) -> OUTLINK_STOP_CH0_W<20> { - OUTLINK_STOP_CH0_W::new(self) + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<20> { + OUTLINK_STOP_W::new(self) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch0(&mut self) -> OUTLINK_START_CH0_W<21> { - OUTLINK_START_CH0_W::new(self) + pub fn outlink_start(&mut self) -> OUTLINK_START_W<21> { + OUTLINK_START_W::new(self) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch0(&mut self) -> OUTLINK_RESTART_CH0_W<22> { - OUTLINK_RESTART_CH0_W::new(self) + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<22> { + OUTLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/out_peri_sel_ch0.rs b/esp32c2/src/dma/out_peri_sel_ch0.rs index f8f4c76479..4851630534 100644 --- a/esp32c2/src/dma/out_peri_sel_ch0.rs +++ b/esp32c2/src/dma/out_peri_sel_ch0.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_OUT_SEL_CH0` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH0_R = crate::FieldReader; -#[doc = "Field `PERI_OUT_SEL_CH0` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH0_W<'a, const O: u8> = +#[doc = "Field `PERI_OUT_SEL` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PERI_SEL_CH0_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch0(&self) -> PERI_OUT_SEL_CH0_R { - PERI_OUT_SEL_CH0_R::new((self.bits & 0x3f) as u8) + pub fn peri_out_sel(&self) -> PERI_OUT_SEL_R { + PERI_OUT_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch0(&mut self) -> PERI_OUT_SEL_CH0_W<0> { - PERI_OUT_SEL_CH0_W::new(self) + pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<0> { + PERI_OUT_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/out_pri_ch0.rs b/esp32c2/src/dma/out_pri_ch0.rs index e271fe425a..31967b6bce 100644 --- a/esp32c2/src/dma/out_pri_ch0.rs +++ b/esp32c2/src/dma/out_pri_ch0.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `TX_PRI_CH0` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH0_R = crate::FieldReader; -#[doc = "Field `TX_PRI_CH0` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, OUT_PRI_CH0_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_PRI` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."] +pub type TX_PRI_R = crate::FieldReader; +#[doc = "Field `TX_PRI` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."] +pub type TX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PRI_CH0_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch0(&self) -> TX_PRI_CH0_R { - TX_PRI_CH0_R::new((self.bits & 0x0f) as u8) + pub fn tx_pri(&self) -> TX_PRI_R { + TX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch0(&mut self) -> TX_PRI_CH0_W<0> { - TX_PRI_CH0_W::new(self) + pub fn tx_pri(&mut self) -> TX_PRI_W<0> { + TX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/out_push_ch0.rs b/esp32c2/src/dma/out_push_ch0.rs index 96107cecd8..7f8a770c68 100644 --- a/esp32c2/src/dma/out_push_ch0.rs +++ b/esp32c2/src/dma/out_push_ch0.rs @@ -34,38 +34,37 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTFIFO_WDATA_CH0` reader - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH0_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_WDATA_CH0` writer - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH0_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_WDATA` reader - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA` writer - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PUSH_CH0_SPEC, u16, u16, 9, O>; -#[doc = "Field `OUTFIFO_PUSH_CH0` reader - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH0_R = crate::BitReader; -#[doc = "Field `OUTFIFO_PUSH_CH0` writer - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_PUSH_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_PUSH` reader - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH` writer - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_PUSH_CH0_SPEC, bool, O>; impl R { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch0(&self) -> OUTFIFO_WDATA_CH0_R { - OUTFIFO_WDATA_CH0_R::new((self.bits & 0x01ff) as u16) + pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R { + OUTFIFO_WDATA_R::new((self.bits & 0x01ff) as u16) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch0(&self) -> OUTFIFO_PUSH_CH0_R { - OUTFIFO_PUSH_CH0_R::new(((self.bits >> 9) & 1) != 0) + pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R { + OUTFIFO_PUSH_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch0(&mut self) -> OUTFIFO_WDATA_CH0_W<0> { - OUTFIFO_WDATA_CH0_W::new(self) + pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<0> { + OUTFIFO_WDATA_W::new(self) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch0(&mut self) -> OUTFIFO_PUSH_CH0_W<9> { - OUTFIFO_PUSH_CH0_W::new(self) + pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<9> { + OUTFIFO_PUSH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c2/src/dma/out_state_ch0.rs b/esp32c2/src/dma/out_state_ch0.rs index df67af9dc4..08e4f5cd83 100644 --- a/esp32c2/src/dma/out_state_ch0.rs +++ b/esp32c2/src/dma/out_state_ch0.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_ADDR_CH0` reader - This register stores the current outlink descriptor's address."] -pub type OUTLINK_DSCR_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `OUT_DSCR_STATE_CH0` reader - reserved"] -pub type OUT_DSCR_STATE_CH0_R = crate::FieldReader; -#[doc = "Field `OUT_STATE_CH0` reader - reserved"] -pub type OUT_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - reserved"] +pub type OUT_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] #[inline(always)] - pub fn outlink_dscr_addr_ch0(&self) -> OUTLINK_DSCR_ADDR_CH0_R { - OUTLINK_DSCR_ADDR_CH0_R::new((self.bits & 0x0003_ffff) as u32) + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn out_dscr_state_ch0(&self) -> OUT_DSCR_STATE_CH0_R { - OUT_DSCR_STATE_CH0_R::new(((self.bits >> 18) & 3) as u8) + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn out_state_ch0(&self) -> OUT_STATE_CH0_R { - OUT_STATE_CH0_R::new(((self.bits >> 20) & 7) as u8) + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_OUT_STATE_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_state_ch0](index.html) module"] diff --git a/esp32c2/src/dma/outfifo_status_ch0.rs b/esp32c2/src/dma/outfifo_status_ch0.rs index d931c12860..2447d03de1 100644 --- a/esp32c2/src/dma/outfifo_status_ch0.rs +++ b/esp32c2/src/dma/outfifo_status_ch0.rs @@ -13,55 +13,55 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTFIFO_FULL_CH0` reader - L1 Tx FIFO full signal for Tx channel 0."] -pub type OUTFIFO_FULL_CH0_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_CH0` reader - L1 Tx FIFO empty signal for Tx channel 0."] -pub type OUTFIFO_EMPTY_CH0_R = crate::BitReader; -#[doc = "Field `OUTFIFO_CNT_CH0` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] -pub type OUTFIFO_CNT_CH0_R = crate::FieldReader; -#[doc = "Field `OUT_REMAIN_UNDER_1B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_1B_CH0_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_2B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_2B_CH0_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_3B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_3B_CH0_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_4B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_4B_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL` reader - L1 Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY` reader - L1 Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_full_ch0(&self) -> OUTFIFO_FULL_CH0_R { - OUTFIFO_FULL_CH0_R::new((self.bits & 1) != 0) + pub fn outfifo_full(&self) -> OUTFIFO_FULL_R { + OUTFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_empty_ch0(&self) -> OUTFIFO_EMPTY_CH0_R { - OUTFIFO_EMPTY_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn outfifo_empty(&self) -> OUTFIFO_EMPTY_R { + OUTFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] #[inline(always)] - pub fn outfifo_cnt_ch0(&self) -> OUTFIFO_CNT_CH0_R { - OUTFIFO_CNT_CH0_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn outfifo_cnt(&self) -> OUTFIFO_CNT_R { + OUTFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn out_remain_under_1b_ch0(&self) -> OUT_REMAIN_UNDER_1B_CH0_R { - OUT_REMAIN_UNDER_1B_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn out_remain_under_1b(&self) -> OUT_REMAIN_UNDER_1B_R { + OUT_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn out_remain_under_2b_ch0(&self) -> OUT_REMAIN_UNDER_2B_CH0_R { - OUT_REMAIN_UNDER_2B_CH0_R::new(((self.bits >> 24) & 1) != 0) + pub fn out_remain_under_2b(&self) -> OUT_REMAIN_UNDER_2B_R { + OUT_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn out_remain_under_3b_ch0(&self) -> OUT_REMAIN_UNDER_3B_CH0_R { - OUT_REMAIN_UNDER_3B_CH0_R::new(((self.bits >> 25) & 1) != 0) + pub fn out_remain_under_3b(&self) -> OUT_REMAIN_UNDER_3B_R { + OUT_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn out_remain_under_4b_ch0(&self) -> OUT_REMAIN_UNDER_4B_CH0_R { - OUT_REMAIN_UNDER_4B_CH0_R::new(((self.bits >> 26) & 1) != 0) + pub fn out_remain_under_4b(&self) -> OUT_REMAIN_UNDER_4B_R { + OUT_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } } #[doc = "DMA_OUTFIFO_STATUS_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outfifo_status_ch0](index.html) module"] diff --git a/esp32c2/src/i2c0.rs b/esp32c2/src/i2c0.rs index d5f86d54b4..4e319b7f2b 100644 --- a/esp32c2/src/i2c0.rs +++ b/esp32c2/src/i2c0.rs @@ -161,11 +161,11 @@ pub mod scl_sp_conf; pub type DATE = crate::Reg; #[doc = "Version register"] pub mod date; -#[doc = "TXFIFO_START_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "TXFIFO_START_ADDR (r) register accessor: an alias for `Reg`"] pub type TXFIFO_START_ADDR = crate::Reg; #[doc = "I2C TXFIFO base address register"] pub mod txfifo_start_addr; -#[doc = "RXFIFO_START_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "RXFIFO_START_ADDR (r) register accessor: an alias for `Reg`"] pub type RXFIFO_START_ADDR = crate::Reg; #[doc = "I2C RXFIFO base address register"] pub mod rxfifo_start_addr; diff --git a/esp32c2/src/i2c0/rxfifo_start_addr.rs b/esp32c2/src/i2c0/rxfifo_start_addr.rs index 1d15c5549a..afc01a54fb 100644 --- a/esp32c2/src/i2c0/rxfifo_start_addr.rs +++ b/esp32c2/src/i2c0/rxfifo_start_addr.rs @@ -13,32 +13,8 @@ impl From> for R { R(reader) } } -#[doc = "Register `RXFIFO_START_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `RXFIFO_START_ADDR` reader - This is the I2C rxfifo first address."] pub type RXFIFO_START_ADDR_R = crate::FieldReader; -#[doc = "Field `RXFIFO_START_ADDR` writer - This is the I2C rxfifo first address."] -pub type RXFIFO_START_ADDR_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, RXFIFO_START_ADDR_SPEC, u32, u32, 32, O>; impl R { #[doc = "Bits 0:31 - This is the I2C rxfifo first address."] #[inline(always)] @@ -46,20 +22,7 @@ impl R { RXFIFO_START_ADDR_R::new(self.bits) } } -impl W { - #[doc = "Bits 0:31 - This is the I2C rxfifo first address."] - #[inline(always)] - pub fn rxfifo_start_addr(&mut self) -> RXFIFO_START_ADDR_W<0> { - RXFIFO_START_ADDR_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "I2C RXFIFO base address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifo_start_addr](index.html) module"] +#[doc = "I2C RXFIFO base address register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifo_start_addr](index.html) module"] pub struct RXFIFO_START_ADDR_SPEC; impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC { type Ux = u32; @@ -68,10 +31,6 @@ impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC { impl crate::Readable for RXFIFO_START_ADDR_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [rxfifo_start_addr::W](W) writer structure"] -impl crate::Writable for RXFIFO_START_ADDR_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets RXFIFO_START_ADDR to value 0"] impl crate::Resettable for RXFIFO_START_ADDR_SPEC { #[inline(always)] diff --git a/esp32c2/src/i2c0/txfifo_start_addr.rs b/esp32c2/src/i2c0/txfifo_start_addr.rs index f89fae9cfb..b191483170 100644 --- a/esp32c2/src/i2c0/txfifo_start_addr.rs +++ b/esp32c2/src/i2c0/txfifo_start_addr.rs @@ -13,32 +13,8 @@ impl From> for R { R(reader) } } -#[doc = "Register `TXFIFO_START_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `TXFIFO_START_ADDR` reader - This is the I2C txfifo first address."] pub type TXFIFO_START_ADDR_R = crate::FieldReader; -#[doc = "Field `TXFIFO_START_ADDR` writer - This is the I2C txfifo first address."] -pub type TXFIFO_START_ADDR_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TXFIFO_START_ADDR_SPEC, u32, u32, 32, O>; impl R { #[doc = "Bits 0:31 - This is the I2C txfifo first address."] #[inline(always)] @@ -46,20 +22,7 @@ impl R { TXFIFO_START_ADDR_R::new(self.bits) } } -impl W { - #[doc = "Bits 0:31 - This is the I2C txfifo first address."] - #[inline(always)] - pub fn txfifo_start_addr(&mut self) -> TXFIFO_START_ADDR_W<0> { - TXFIFO_START_ADDR_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "I2C TXFIFO base address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifo_start_addr](index.html) module"] +#[doc = "I2C TXFIFO base address register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifo_start_addr](index.html) module"] pub struct TXFIFO_START_ADDR_SPEC; impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC { type Ux = u32; @@ -68,10 +31,6 @@ impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC { impl crate::Readable for TXFIFO_START_ADDR_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [txfifo_start_addr::W](W) writer structure"] -impl crate::Writable for TXFIFO_START_ADDR_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets TXFIFO_START_ADDR to value 0"] impl crate::Resettable for TXFIFO_START_ADDR_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi0.rs b/esp32c2/src/spi0.rs index 2b1d1afc3b..e6e3a51f49 100644 --- a/esp32c2/src/spi0.rs +++ b/esp32c2/src/spi0.rs @@ -90,19 +90,19 @@ pub mod cache_fctrl; pub type FSM = crate::Reg; #[doc = "SPI0 FSM status register"] pub mod fsm; -#[doc = "TIMING_CALI (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMING_CALI (r) register accessor: an alias for `Reg`"] pub type TIMING_CALI = crate::Reg; #[doc = "SPI0 timing calibration register"] pub mod timing_cali; -#[doc = "DIN_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "DIN_MODE (r) register accessor: an alias for `Reg`"] pub type DIN_MODE = crate::Reg; #[doc = "SPI0 input delay mode control register"] pub mod din_mode; -#[doc = "DIN_NUM (rw) register accessor: an alias for `Reg`"] +#[doc = "DIN_NUM (r) register accessor: an alias for `Reg`"] pub type DIN_NUM = crate::Reg; #[doc = "SPI0 input delay number control register"] pub mod din_num; -#[doc = "DOUT_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "DOUT_MODE (r) register accessor: an alias for `Reg`"] pub type DOUT_MODE = crate::Reg; #[doc = "SPI0 output delay mode control register"] pub mod dout_mode; diff --git a/esp32c2/src/spi0/din_mode.rs b/esp32c2/src/spi0/din_mode.rs index e5ade65fba..a3618f2b24 100644 --- a/esp32c2/src/spi0/din_mode.rs +++ b/esp32c2/src/spi0/din_mode.rs @@ -13,43 +13,14 @@ impl From> for R { R(reader) } } -#[doc = "Register `DIN_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `DIN0_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] pub type DIN0_MODE_R = crate::FieldReader; -#[doc = "Field `DIN0_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] -pub type DIN0_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN1_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] pub type DIN1_MODE_R = crate::FieldReader; -#[doc = "Field `DIN1_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] -pub type DIN1_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN2_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] pub type DIN2_MODE_R = crate::FieldReader; -#[doc = "Field `DIN2_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] -pub type DIN2_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN3_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] pub type DIN3_MODE_R = crate::FieldReader; -#[doc = "Field `DIN3_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] -pub type DIN3_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; impl R { #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] #[inline(always)] @@ -72,35 +43,7 @@ impl R { DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8) } } -impl W { - #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] - #[inline(always)] - pub fn din0_mode(&mut self) -> DIN0_MODE_W<0> { - DIN0_MODE_W::new(self) - } - #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] - #[inline(always)] - pub fn din1_mode(&mut self) -> DIN1_MODE_W<2> { - DIN1_MODE_W::new(self) - } - #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] - #[inline(always)] - pub fn din2_mode(&mut self) -> DIN2_MODE_W<4> { - DIN2_MODE_W::new(self) - } - #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] - #[inline(always)] - pub fn din3_mode(&mut self) -> DIN3_MODE_W<6> { - DIN3_MODE_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI0 input delay mode control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_mode](index.html) module"] +#[doc = "SPI0 input delay mode control register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_mode](index.html) module"] pub struct DIN_MODE_SPEC; impl crate::RegisterSpec for DIN_MODE_SPEC { type Ux = u32; @@ -109,10 +52,6 @@ impl crate::RegisterSpec for DIN_MODE_SPEC { impl crate::Readable for DIN_MODE_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [din_mode::W](W) writer structure"] -impl crate::Writable for DIN_MODE_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets DIN_MODE to value 0"] impl crate::Resettable for DIN_MODE_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi0/din_num.rs b/esp32c2/src/spi0/din_num.rs index c1c5c3fdb5..f062373b25 100644 --- a/esp32c2/src/spi0/din_num.rs +++ b/esp32c2/src/spi0/din_num.rs @@ -13,43 +13,14 @@ impl From> for R { R(reader) } } -#[doc = "Register `DIN_NUM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `DIN0_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] pub type DIN0_NUM_R = crate::BitReader; -#[doc = "Field `DIN0_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] -pub type DIN0_NUM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIN_NUM_SPEC, bool, O>; #[doc = "Field `DIN1_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] pub type DIN1_NUM_R = crate::BitReader; -#[doc = "Field `DIN1_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] -pub type DIN1_NUM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIN_NUM_SPEC, bool, O>; #[doc = "Field `DIN2_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] pub type DIN2_NUM_R = crate::BitReader; -#[doc = "Field `DIN2_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] -pub type DIN2_NUM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIN_NUM_SPEC, bool, O>; #[doc = "Field `DIN3_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] pub type DIN3_NUM_R = crate::BitReader; -#[doc = "Field `DIN3_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] -pub type DIN3_NUM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIN_NUM_SPEC, bool, O>; impl R { #[doc = "Bit 0 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] #[inline(always)] @@ -72,35 +43,7 @@ impl R { DIN3_NUM_R::new(((self.bits >> 3) & 1) != 0) } } -impl W { - #[doc = "Bit 0 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] - #[inline(always)] - pub fn din0_num(&mut self) -> DIN0_NUM_W<0> { - DIN0_NUM_W::new(self) - } - #[doc = "Bit 1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] - #[inline(always)] - pub fn din1_num(&mut self) -> DIN1_NUM_W<1> { - DIN1_NUM_W::new(self) - } - #[doc = "Bit 2 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] - #[inline(always)] - pub fn din2_num(&mut self) -> DIN2_NUM_W<2> { - DIN2_NUM_W::new(self) - } - #[doc = "Bit 3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] - #[inline(always)] - pub fn din3_num(&mut self) -> DIN3_NUM_W<3> { - DIN3_NUM_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI0 input delay number control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_num](index.html) module"] +#[doc = "SPI0 input delay number control register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_num](index.html) module"] pub struct DIN_NUM_SPEC; impl crate::RegisterSpec for DIN_NUM_SPEC { type Ux = u32; @@ -109,10 +52,6 @@ impl crate::RegisterSpec for DIN_NUM_SPEC { impl crate::Readable for DIN_NUM_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [din_num::W](W) writer structure"] -impl crate::Writable for DIN_NUM_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets DIN_NUM to value 0"] impl crate::Resettable for DIN_NUM_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi0/dout_mode.rs b/esp32c2/src/spi0/dout_mode.rs index cc698b07dd..a06930a2d4 100644 --- a/esp32c2/src/spi0/dout_mode.rs +++ b/esp32c2/src/spi0/dout_mode.rs @@ -13,43 +13,14 @@ impl From> for R { R(reader) } } -#[doc = "Register `DOUT_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `DOUT0_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] pub type DOUT0_MODE_R = crate::BitReader; -#[doc = "Field `DOUT0_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] -pub type DOUT0_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT1_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] pub type DOUT1_MODE_R = crate::BitReader; -#[doc = "Field `DOUT1_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] -pub type DOUT1_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT2_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] pub type DOUT2_MODE_R = crate::BitReader; -#[doc = "Field `DOUT2_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] -pub type DOUT2_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT3_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] pub type DOUT3_MODE_R = crate::BitReader; -#[doc = "Field `DOUT3_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] -pub type DOUT3_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; impl R { #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] #[inline(always)] @@ -72,35 +43,7 @@ impl R { DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0) } } -impl W { - #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] - #[inline(always)] - pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<0> { - DOUT0_MODE_W::new(self) - } - #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] - #[inline(always)] - pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<1> { - DOUT1_MODE_W::new(self) - } - #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] - #[inline(always)] - pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<2> { - DOUT2_MODE_W::new(self) - } - #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] - #[inline(always)] - pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<3> { - DOUT3_MODE_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI0 output delay mode control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dout_mode](index.html) module"] +#[doc = "SPI0 output delay mode control register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dout_mode](index.html) module"] pub struct DOUT_MODE_SPEC; impl crate::RegisterSpec for DOUT_MODE_SPEC { type Ux = u32; @@ -109,10 +52,6 @@ impl crate::RegisterSpec for DOUT_MODE_SPEC { impl crate::Readable for DOUT_MODE_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [dout_mode::W](W) writer structure"] -impl crate::Writable for DOUT_MODE_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets DOUT_MODE to value 0"] impl crate::Resettable for DOUT_MODE_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi0/timing_cali.rs b/esp32c2/src/spi0/timing_cali.rs index c55d6dc985..74e8fa99bf 100644 --- a/esp32c2/src/spi0/timing_cali.rs +++ b/esp32c2/src/spi0/timing_cali.rs @@ -13,40 +13,12 @@ impl From> for R { R(reader) } } -#[doc = "Register `TIMING_CALI` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `TIMING_CLK_ENA` reader - The bit is used to enable timing adjust clock for all reading operations."] pub type TIMING_CLK_ENA_R = crate::BitReader; -#[doc = "Field `TIMING_CLK_ENA` writer - The bit is used to enable timing adjust clock for all reading operations."] -pub type TIMING_CLK_ENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMING_CALI_SPEC, bool, O>; #[doc = "Field `TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."] pub type TIMING_CALI_R = crate::BitReader; -#[doc = "Field `TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."] -pub type TIMING_CALI_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMING_CALI_SPEC, bool, O>; #[doc = "Field `EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."] pub type EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."] -pub type EXTRA_DUMMY_CYCLELEN_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TIMING_CALI_SPEC, u8, u8, 3, O>; impl R { #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."] #[inline(always)] @@ -64,30 +36,7 @@ impl R { EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8) } } -impl W { - #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."] - #[inline(always)] - pub fn timing_clk_ena(&mut self) -> TIMING_CLK_ENA_W<0> { - TIMING_CLK_ENA_W::new(self) - } - #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] - #[inline(always)] - pub fn timing_cali(&mut self) -> TIMING_CALI_W<1> { - TIMING_CALI_W::new(self) - } - #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."] - #[inline(always)] - pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<2> { - EXTRA_DUMMY_CYCLELEN_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI0 timing calibration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timing_cali](index.html) module"] +#[doc = "SPI0 timing calibration register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timing_cali](index.html) module"] pub struct TIMING_CALI_SPEC; impl crate::RegisterSpec for TIMING_CALI_SPEC { type Ux = u32; @@ -96,10 +45,6 @@ impl crate::RegisterSpec for TIMING_CALI_SPEC { impl crate::Readable for TIMING_CALI_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [timing_cali::W](W) writer structure"] -impl crate::Writable for TIMING_CALI_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets TIMING_CALI to value 0"] impl crate::Resettable for TIMING_CALI_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi1.rs b/esp32c2/src/spi1.rs index d0cfc3694d..aa4ab1a871 100644 --- a/esp32c2/src/spi1.rs +++ b/esp32c2/src/spi1.rs @@ -231,7 +231,7 @@ pub mod flash_sus_cmd; pub type SUS_STATUS = crate::Reg; #[doc = "SPI1 flash suspend status register"] pub mod sus_status; -#[doc = "TIMING_CALI (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMING_CALI (r) register accessor: an alias for `Reg`"] pub type TIMING_CALI = crate::Reg; #[doc = "SPI1 timing control register"] pub mod timing_cali; diff --git a/esp32c2/src/spi1/timing_cali.rs b/esp32c2/src/spi1/timing_cali.rs index 3e76df0a99..99975aa901 100644 --- a/esp32c2/src/spi1/timing_cali.rs +++ b/esp32c2/src/spi1/timing_cali.rs @@ -13,36 +13,10 @@ impl From> for R { R(reader) } } -#[doc = "Register `TIMING_CALI` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."] pub type TIMING_CALI_R = crate::BitReader; -#[doc = "Field `TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."] -pub type TIMING_CALI_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMING_CALI_SPEC, bool, O>; #[doc = "Field `EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."] pub type EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."] -pub type EXTRA_DUMMY_CYCLELEN_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TIMING_CALI_SPEC, u8, u8, 3, O>; impl R { #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] #[inline(always)] @@ -55,25 +29,7 @@ impl R { EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8) } } -impl W { - #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] - #[inline(always)] - pub fn timing_cali(&mut self) -> TIMING_CALI_W<1> { - TIMING_CALI_W::new(self) - } - #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."] - #[inline(always)] - pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<2> { - EXTRA_DUMMY_CYCLELEN_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI1 timing control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timing_cali](index.html) module"] +#[doc = "SPI1 timing control register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timing_cali](index.html) module"] pub struct TIMING_CALI_SPEC; impl crate::RegisterSpec for TIMING_CALI_SPEC { type Ux = u32; @@ -82,10 +38,6 @@ impl crate::RegisterSpec for TIMING_CALI_SPEC { impl crate::Readable for TIMING_CALI_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [timing_cali::W](W) writer structure"] -impl crate::Writable for TIMING_CALI_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets TIMING_CALI to value 0"] impl crate::Resettable for TIMING_CALI_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi2.rs b/esp32c2/src/spi2.rs index cd7bbe60a0..08427dc8e1 100644 --- a/esp32c2/src/spi2.rs +++ b/esp32c2/src/spi2.rs @@ -117,15 +117,15 @@ pub mod ms_dlen; pub type MISC = crate::Reg; #[doc = "SPI misc register"] pub mod misc; -#[doc = "DIN_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "DIN_MODE (r) register accessor: an alias for `Reg`"] pub type DIN_MODE = crate::Reg; #[doc = "SPI input delay mode configuration"] pub mod din_mode; -#[doc = "DIN_NUM (rw) register accessor: an alias for `Reg`"] +#[doc = "DIN_NUM (r) register accessor: an alias for `Reg`"] pub type DIN_NUM = crate::Reg; #[doc = "SPI input delay number configuration"] pub mod din_num; -#[doc = "DOUT_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "DOUT_MODE (r) register accessor: an alias for `Reg`"] pub type DOUT_MODE = crate::Reg; #[doc = "SPI output delay mode configuration"] pub mod dout_mode; diff --git a/esp32c2/src/spi2/ctrl.rs b/esp32c2/src/spi2/ctrl.rs index 58ca09194a..e300e97006 100644 --- a/esp32c2/src/spi2/ctrl.rs +++ b/esp32c2/src/spi2/ctrl.rs @@ -48,8 +48,6 @@ pub type FADDR_QUAD_R = crate::BitReader; pub type FADDR_QUAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>; #[doc = "Field `FADDR_OCT` reader - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] pub type FADDR_OCT_R = crate::BitReader; -#[doc = "Field `FADDR_OCT` writer - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] -pub type FADDR_OCT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>; #[doc = "Field `FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] pub type FCMD_DUAL_R = crate::BitReader; #[doc = "Field `FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] @@ -60,8 +58,6 @@ pub type FCMD_QUAD_R = crate::BitReader; pub type FCMD_QUAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>; #[doc = "Field `FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] pub type FCMD_OCT_R = crate::BitReader; -#[doc = "Field `FCMD_OCT` writer - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] -pub type FCMD_OCT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>; #[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] pub type FREAD_DUAL_R = crate::BitReader; #[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] @@ -72,8 +68,6 @@ pub type FREAD_QUAD_R = crate::BitReader; pub type FREAD_QUAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>; #[doc = "Field `FREAD_OCT` reader - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] pub type FREAD_OCT_R = crate::BitReader; -#[doc = "Field `FREAD_OCT` writer - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] -pub type FREAD_OCT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>; #[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] pub type Q_POL_R = crate::BitReader; #[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] @@ -196,11 +190,6 @@ impl W { pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<6> { FADDR_QUAD_W::new(self) } - #[doc = "Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] - #[inline(always)] - pub fn faddr_oct(&mut self) -> FADDR_OCT_W<7> { - FADDR_OCT_W::new(self) - } #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] #[inline(always)] pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<8> { @@ -211,11 +200,6 @@ impl W { pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<9> { FCMD_QUAD_W::new(self) } - #[doc = "Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] - #[inline(always)] - pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<10> { - FCMD_OCT_W::new(self) - } #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] #[inline(always)] pub fn fread_dual(&mut self) -> FREAD_DUAL_W<14> { @@ -226,11 +210,6 @@ impl W { pub fn fread_quad(&mut self) -> FREAD_QUAD_W<15> { FREAD_QUAD_W::new(self) } - #[doc = "Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] - #[inline(always)] - pub fn fread_oct(&mut self) -> FREAD_OCT_W<16> { - FREAD_OCT_W::new(self) - } #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] #[inline(always)] pub fn q_pol(&mut self) -> Q_POL_W<18> { diff --git a/esp32c2/src/spi2/din_mode.rs b/esp32c2/src/spi2/din_mode.rs index 6ba1c3eab1..b854878072 100644 --- a/esp32c2/src/spi2/din_mode.rs +++ b/esp32c2/src/spi2/din_mode.rs @@ -13,63 +13,24 @@ impl From> for R { R(reader) } } -#[doc = "Register `DIN_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `DIN0_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN0_MODE_R = crate::FieldReader; -#[doc = "Field `DIN0_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN0_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN1_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN1_MODE_R = crate::FieldReader; -#[doc = "Field `DIN1_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN1_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN2_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN2_MODE_R = crate::FieldReader; -#[doc = "Field `DIN2_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN2_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN3_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN3_MODE_R = crate::FieldReader; -#[doc = "Field `DIN3_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN3_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN4_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN4_MODE_R = crate::FieldReader; -#[doc = "Field `DIN4_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN4_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN5_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN5_MODE_R = crate::FieldReader; -#[doc = "Field `DIN5_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN5_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN6_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN6_MODE_R = crate::FieldReader; -#[doc = "Field `DIN6_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN6_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN7_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] pub type DIN7_MODE_R = crate::FieldReader; -#[doc = "Field `DIN7_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] -pub type DIN7_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_MODE_SPEC, u8, u8, 2, O>; #[doc = "Field `TIMING_HCLK_ACTIVE` reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] pub type TIMING_HCLK_ACTIVE_R = crate::BitReader; -#[doc = "Field `TIMING_HCLK_ACTIVE` writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] -pub type TIMING_HCLK_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIN_MODE_SPEC, bool, O>; impl R { #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] #[inline(always)] @@ -117,60 +78,7 @@ impl R { TIMING_HCLK_ACTIVE_R::new(((self.bits >> 16) & 1) != 0) } } -impl W { - #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din0_mode(&mut self) -> DIN0_MODE_W<0> { - DIN0_MODE_W::new(self) - } - #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din1_mode(&mut self) -> DIN1_MODE_W<2> { - DIN1_MODE_W::new(self) - } - #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din2_mode(&mut self) -> DIN2_MODE_W<4> { - DIN2_MODE_W::new(self) - } - #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din3_mode(&mut self) -> DIN3_MODE_W<6> { - DIN3_MODE_W::new(self) - } - #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din4_mode(&mut self) -> DIN4_MODE_W<8> { - DIN4_MODE_W::new(self) - } - #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din5_mode(&mut self) -> DIN5_MODE_W<10> { - DIN5_MODE_W::new(self) - } - #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din6_mode(&mut self) -> DIN6_MODE_W<12> { - DIN6_MODE_W::new(self) - } - #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] - #[inline(always)] - pub fn din7_mode(&mut self) -> DIN7_MODE_W<14> { - DIN7_MODE_W::new(self) - } - #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] - #[inline(always)] - pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<16> { - TIMING_HCLK_ACTIVE_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI input delay mode configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_mode](index.html) module"] +#[doc = "SPI input delay mode configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_mode](index.html) module"] pub struct DIN_MODE_SPEC; impl crate::RegisterSpec for DIN_MODE_SPEC { type Ux = u32; @@ -179,10 +87,6 @@ impl crate::RegisterSpec for DIN_MODE_SPEC { impl crate::Readable for DIN_MODE_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [din_mode::W](W) writer structure"] -impl crate::Writable for DIN_MODE_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets DIN_MODE to value 0"] impl crate::Resettable for DIN_MODE_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi2/din_num.rs b/esp32c2/src/spi2/din_num.rs index 15267b6c56..b6bed71368 100644 --- a/esp32c2/src/spi2/din_num.rs +++ b/esp32c2/src/spi2/din_num.rs @@ -13,59 +13,22 @@ impl From> for R { R(reader) } } -#[doc = "Register `DIN_NUM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `DIN0_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN0_NUM_R = crate::FieldReader; -#[doc = "Field `DIN0_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN0_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN1_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN1_NUM_R = crate::FieldReader; -#[doc = "Field `DIN1_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN1_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN2_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN2_NUM_R = crate::FieldReader; -#[doc = "Field `DIN2_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN2_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN3_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN3_NUM_R = crate::FieldReader; -#[doc = "Field `DIN3_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN3_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN4_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN4_NUM_R = crate::FieldReader; -#[doc = "Field `DIN4_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN4_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN5_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN5_NUM_R = crate::FieldReader; -#[doc = "Field `DIN5_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN5_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN6_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN6_NUM_R = crate::FieldReader; -#[doc = "Field `DIN6_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN6_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; #[doc = "Field `DIN7_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] pub type DIN7_NUM_R = crate::FieldReader; -#[doc = "Field `DIN7_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] -pub type DIN7_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIN_NUM_SPEC, u8, u8, 2, O>; impl R { #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] #[inline(always)] @@ -108,55 +71,7 @@ impl R { DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8) } } -impl W { - #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din0_num(&mut self) -> DIN0_NUM_W<0> { - DIN0_NUM_W::new(self) - } - #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din1_num(&mut self) -> DIN1_NUM_W<2> { - DIN1_NUM_W::new(self) - } - #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din2_num(&mut self) -> DIN2_NUM_W<4> { - DIN2_NUM_W::new(self) - } - #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din3_num(&mut self) -> DIN3_NUM_W<6> { - DIN3_NUM_W::new(self) - } - #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din4_num(&mut self) -> DIN4_NUM_W<8> { - DIN4_NUM_W::new(self) - } - #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din5_num(&mut self) -> DIN5_NUM_W<10> { - DIN5_NUM_W::new(self) - } - #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din6_num(&mut self) -> DIN6_NUM_W<12> { - DIN6_NUM_W::new(self) - } - #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] - #[inline(always)] - pub fn din7_num(&mut self) -> DIN7_NUM_W<14> { - DIN7_NUM_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI input delay number configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_num](index.html) module"] +#[doc = "SPI input delay number configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [din_num](index.html) module"] pub struct DIN_NUM_SPEC; impl crate::RegisterSpec for DIN_NUM_SPEC { type Ux = u32; @@ -165,10 +80,6 @@ impl crate::RegisterSpec for DIN_NUM_SPEC { impl crate::Readable for DIN_NUM_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [din_num::W](W) writer structure"] -impl crate::Writable for DIN_NUM_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets DIN_NUM to value 0"] impl crate::Resettable for DIN_NUM_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi2/dout_mode.rs b/esp32c2/src/spi2/dout_mode.rs index 488d25a4a7..b95211e194 100644 --- a/esp32c2/src/spi2/dout_mode.rs +++ b/esp32c2/src/spi2/dout_mode.rs @@ -13,63 +13,24 @@ impl From> for R { R(reader) } } -#[doc = "Register `DOUT_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} #[doc = "Field `DOUT0_MODE` reader - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT0_MODE_R = crate::BitReader; -#[doc = "Field `DOUT0_MODE` writer - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT0_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT1_MODE` reader - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT1_MODE_R = crate::BitReader; -#[doc = "Field `DOUT1_MODE` writer - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT1_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT2_MODE` reader - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT2_MODE_R = crate::BitReader; -#[doc = "Field `DOUT2_MODE` writer - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT2_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT3_MODE` reader - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT3_MODE_R = crate::BitReader; -#[doc = "Field `DOUT3_MODE` writer - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT3_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT4_MODE` reader - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT4_MODE_R = crate::BitReader; -#[doc = "Field `DOUT4_MODE` writer - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT4_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT5_MODE` reader - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT5_MODE_R = crate::BitReader; -#[doc = "Field `DOUT5_MODE` writer - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT5_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT6_MODE` reader - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT6_MODE_R = crate::BitReader; -#[doc = "Field `DOUT6_MODE` writer - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT6_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `DOUT7_MODE` reader - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type DOUT7_MODE_R = crate::BitReader; -#[doc = "Field `DOUT7_MODE` writer - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type DOUT7_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; #[doc = "Field `D_DQS_MODE` reader - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] pub type D_DQS_MODE_R = crate::BitReader; -#[doc = "Field `D_DQS_MODE` writer - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] -pub type D_DQS_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOUT_MODE_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] #[inline(always)] @@ -117,60 +78,7 @@ impl R { D_DQS_MODE_R::new(((self.bits >> 8) & 1) != 0) } } -impl W { - #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<0> { - DOUT0_MODE_W::new(self) - } - #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<1> { - DOUT1_MODE_W::new(self) - } - #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<2> { - DOUT2_MODE_W::new(self) - } - #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<3> { - DOUT3_MODE_W::new(self) - } - #[doc = "Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout4_mode(&mut self) -> DOUT4_MODE_W<4> { - DOUT4_MODE_W::new(self) - } - #[doc = "Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout5_mode(&mut self) -> DOUT5_MODE_W<5> { - DOUT5_MODE_W::new(self) - } - #[doc = "Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout6_mode(&mut self) -> DOUT6_MODE_W<6> { - DOUT6_MODE_W::new(self) - } - #[doc = "Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn dout7_mode(&mut self) -> DOUT7_MODE_W<7> { - DOUT7_MODE_W::new(self) - } - #[doc = "Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] - #[inline(always)] - pub fn d_dqs_mode(&mut self) -> D_DQS_MODE_W<8> { - D_DQS_MODE_W::new(self) - } - #[doc = "Writes raw bits to the register."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); - self - } -} -#[doc = "SPI output delay mode configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dout_mode](index.html) module"] +#[doc = "SPI output delay mode configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dout_mode](index.html) module"] pub struct DOUT_MODE_SPEC; impl crate::RegisterSpec for DOUT_MODE_SPEC { type Ux = u32; @@ -179,10 +87,6 @@ impl crate::RegisterSpec for DOUT_MODE_SPEC { impl crate::Readable for DOUT_MODE_SPEC { type Reader = R; } -#[doc = "`write(|w| ..)` method takes [dout_mode::W](W) writer structure"] -impl crate::Writable for DOUT_MODE_SPEC { - type Writer = W; -} #[doc = "`reset()` method sets DOUT_MODE to value 0"] impl crate::Resettable for DOUT_MODE_SPEC { #[inline(always)] diff --git a/esp32c2/src/spi2/misc.rs b/esp32c2/src/spi2/misc.rs index 29a02dd4ef..3dfa473954 100644 --- a/esp32c2/src/spi2/misc.rs +++ b/esp32c2/src/spi2/misc.rs @@ -68,28 +68,18 @@ pub type MASTER_CS_POL_R = crate::FieldReader; pub type MASTER_CS_POL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MISC_SPEC, u8, u8, 6, O>; #[doc = "Field `CLK_DATA_DTR_EN` reader - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] pub type CLK_DATA_DTR_EN_R = crate::BitReader; -#[doc = "Field `CLK_DATA_DTR_EN` writer - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] -pub type CLK_DATA_DTR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>; #[doc = "Field `DATA_DTR_EN` reader - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] pub type DATA_DTR_EN_R = crate::BitReader; -#[doc = "Field `DATA_DTR_EN` writer - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] -pub type DATA_DTR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>; #[doc = "Field `ADDR_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] pub type ADDR_DTR_EN_R = crate::BitReader; -#[doc = "Field `ADDR_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] -pub type ADDR_DTR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>; #[doc = "Field `CMD_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] pub type CMD_DTR_EN_R = crate::BitReader; -#[doc = "Field `CMD_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] -pub type CMD_DTR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>; #[doc = "Field `SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] pub type SLAVE_CS_POL_R = crate::BitReader; #[doc = "Field `SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] pub type SLAVE_CS_POL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>; #[doc = "Field `DQS_IDLE_EDGE` reader - The default value of spi_dqs. Can be configured in CONF state."] pub type DQS_IDLE_EDGE_R = crate::BitReader; -#[doc = "Field `DQS_IDLE_EDGE` writer - The default value of spi_dqs. Can be configured in CONF state."] -pub type DQS_IDLE_EDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>; #[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] pub type CK_IDLE_EDGE_R = crate::BitReader; #[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] @@ -230,36 +220,11 @@ impl W { pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<7> { MASTER_CS_POL_W::new(self) } - #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] - #[inline(always)] - pub fn clk_data_dtr_en(&mut self) -> CLK_DATA_DTR_EN_W<16> { - CLK_DATA_DTR_EN_W::new(self) - } - #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] - #[inline(always)] - pub fn data_dtr_en(&mut self) -> DATA_DTR_EN_W<17> { - DATA_DTR_EN_W::new(self) - } - #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] - #[inline(always)] - pub fn addr_dtr_en(&mut self) -> ADDR_DTR_EN_W<18> { - ADDR_DTR_EN_W::new(self) - } - #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] - #[inline(always)] - pub fn cmd_dtr_en(&mut self) -> CMD_DTR_EN_W<19> { - CMD_DTR_EN_W::new(self) - } #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] #[inline(always)] pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<23> { SLAVE_CS_POL_W::new(self) } - #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."] - #[inline(always)] - pub fn dqs_idle_edge(&mut self) -> DQS_IDLE_EDGE_W<24> { - DQS_IDLE_EDGE_W::new(self) - } #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] #[inline(always)] pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<29> { diff --git a/esp32c2/src/spi2/user.rs b/esp32c2/src/spi2/user.rs index 70052f193e..77822a1a49 100644 --- a/esp32c2/src/spi2/user.rs +++ b/esp32c2/src/spi2/user.rs @@ -44,8 +44,6 @@ pub type QPI_MODE_R = crate::BitReader; pub type QPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, USER_SPEC, bool, O>; #[doc = "Field `OPI_MODE` reader - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] pub type OPI_MODE_R = crate::BitReader; -#[doc = "Field `OPI_MODE` writer - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] -pub type OPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, USER_SPEC, bool, O>; #[doc = "Field `TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] pub type TSCK_I_EDGE_R = crate::BitReader; #[doc = "Field `TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] @@ -76,8 +74,6 @@ pub type FWRITE_QUAD_R = crate::BitReader; pub type FWRITE_QUAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, USER_SPEC, bool, O>; #[doc = "Field `FWRITE_OCT` reader - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] pub type FWRITE_OCT_R = crate::BitReader; -#[doc = "Field `FWRITE_OCT` writer - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] -pub type FWRITE_OCT_W<'a, const O: u8> = crate::BitWriter<'a, u32, USER_SPEC, bool, O>; #[doc = "Field `USR_CONF_NXT` reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] pub type USR_CONF_NXT_R = crate::BitReader; #[doc = "Field `USR_CONF_NXT` writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] @@ -236,11 +232,6 @@ impl W { pub fn qpi_mode(&mut self) -> QPI_MODE_W<3> { QPI_MODE_W::new(self) } - #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] - #[inline(always)] - pub fn opi_mode(&mut self) -> OPI_MODE_W<4> { - OPI_MODE_W::new(self) - } #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] #[inline(always)] pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<5> { @@ -276,11 +267,6 @@ impl W { pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<13> { FWRITE_QUAD_W::new(self) } - #[doc = "Bit 14 - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] - #[inline(always)] - pub fn fwrite_oct(&mut self) -> FWRITE_OCT_W<14> { - FWRITE_OCT_W::new(self) - } #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] #[inline(always)] pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<15> { diff --git a/esp32c2/svd/esp32c2.base.svd b/esp32c2/svd/esp32c2.base.svd index d65cea4dc9..59e05295df 100644 --- a/esp32c2/svd/esp32c2.base.svd +++ b/esp32c2/svd/esp32c2.base.svd @@ -4,7 +4,7 @@ ESPRESSIF ESP32-C2 ESP32-C2 - 3 + 4 32-bit RISC-V MCU Copyright 2022 Espressif Systems (Shanghai) PTE LTD @@ -2142,91 +2142,91 @@ 0x20 - IN_DONE_CH0_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 read-only - IN_SUC_EOF_CH0_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-only - IN_ERR_EOF_CH0_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 read-only - OUT_DONE_CH0_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 read-only - OUT_EOF_CH0_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 read-only - IN_DSCR_ERR_CH0_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 read-only - INFIFO_OVF_CH0_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 read-only - INFIFO_UDF_CH0_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 read-only - OUTFIFO_OVF_CH0_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 read-only - OUTFIFO_UDF_CH0_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 @@ -2241,91 +2241,91 @@ 0x20 - IN_DONE_CH0_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH0_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH0_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH0_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH0_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH0_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH0_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH0_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH0_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH0_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -2340,91 +2340,91 @@ 0x20 - IN_DONE_CH0_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH0_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH0_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH0_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH0_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH0_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH0_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH0_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH0_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH0_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH0_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH0_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH0_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -2439,91 +2439,91 @@ 0x20 - IN_DONE_CH0_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH0_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH0_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH0_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH0_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH0_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH0_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH0_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH0_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH0_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH0_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH0_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH0_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -2605,35 +2605,35 @@ 0x20 - IN_RST_CH0 + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH0 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH0 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH0 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH0 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -2648,7 +2648,7 @@ 0x20 - IN_CHECK_OWNER_CH0 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -2664,56 +2664,56 @@ 0x07800003 - INFIFO_FULL_CH0 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_CH0 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_CNT_CH0 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only - IN_REMAIN_UNDER_1B_CH0 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH0 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH0 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH0 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH0 + IN_BUF_HUNGRY reserved 27 1 @@ -2729,14 +2729,14 @@ 0x00000800 - INFIFO_RDATA_CH0 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH0 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -2752,42 +2752,42 @@ 0x01100000 - INLINK_ADDR_CH0 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH0 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH0 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH0 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH0 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH0 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -2802,21 +2802,21 @@ 0x20 - INLINK_DSCR_ADDR_CH0 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH0 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH0 + IN_STATE reserved 20 3 @@ -2831,7 +2831,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH0 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -2846,7 +2846,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH0 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -2861,7 +2861,7 @@ 0x20 - INLINK_DSCR_CH0 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -2876,7 +2876,7 @@ 0x20 - INLINK_DSCR_BF0_CH0 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -2891,7 +2891,7 @@ 0x20 - INLINK_DSCR_BF1_CH0 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -2906,7 +2906,7 @@ 0x20 - RX_PRI_CH0 + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -2922,7 +2922,7 @@ 0x0000003F - PERI_IN_SEL_CH0 + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -2938,42 +2938,42 @@ 0x00000008 - OUT_RST_CH0 + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH0 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH0 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH0 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH0 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH0 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -2988,7 +2988,7 @@ 0x20 - OUT_CHECK_OWNER_CH0 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -3004,49 +3004,49 @@ 0x07800002 - OUTFIFO_FULL_CH0 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_CH0 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_CNT_CH0 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH0 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH0 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH0 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH0 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -3061,14 +3061,14 @@ 0x20 - OUTFIFO_WDATA_CH0 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH0 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -3084,35 +3084,35 @@ 0x00800000 - OUTLINK_ADDR_CH0 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH0 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH0 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH0 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH0 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -3127,21 +3127,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH0 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH0 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH0 + OUT_STATE reserved 20 3 @@ -3156,7 +3156,7 @@ 0x20 - OUT_EOF_DES_ADDR_CH0 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -3171,7 +3171,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH0 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -3186,7 +3186,7 @@ 0x20 - OUTLINK_DSCR_CH0 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -3201,7 +3201,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH0 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -3216,7 +3216,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH0 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -3231,7 +3231,7 @@ 0x20 - TX_PRI_CH0 + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -3247,7 +3247,7 @@ 0x0000003F - PERI_OUT_SEL_CH0 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -7130,6 +7130,7 @@ level. This is the I2C txfifo first address. 0 32 + read-only @@ -7144,6 +7145,7 @@ level. This is the I2C rxfifo first address. 0 32 + read-only @@ -8595,7 +8597,7 @@ level. 0x20 - TIMER_SEL_CH0 + TIMER_SEL This field is used to select one of timers for channel %s. 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3 @@ -8604,28 +8606,28 @@ level. read-write - SIG_OUT_EN_CH0 + SIG_OUT_EN Set this bit to enable signal output on channel %s. 2 1 read-write - IDLE_LV_CH0 + IDLE_LV This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 read-write - PARA_UP_CH0 + PARA_UP This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only - OVF_NUM_CH0 + OVF_NUM This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. @@ -8634,14 +8636,14 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows read-write - OVF_CNT_EN_CH0 + OVF_CNT_EN This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write - OVF_CNT_RESET_CH0 + OVF_CNT_RESET Set this bit to reset the ovf_cnt of channel %s. 16 1 @@ -8658,7 +8660,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - HPOINT_CH0 + HPOINT The output value changes to high when the selected timers has reached the value specified by this register. 0 14 @@ -8675,7 +8677,7 @@ The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows 0x20 - DUTY_CH0 + DUTY This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. @@ -8695,35 +8697,35 @@ The output value turns to low when the selected timers has reached the Lpoint.0x40000000 - DUTY_SCALE_CH0 + DUTY_SCALE This register is used to configure the changing step scale of duty on channel %s. 0 10 read-write - DUTY_CYCLE_CH0 + DUTY_CYCLE The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. 10 10 read-write - DUTY_NUM_CH0 + DUTY_NUM This register is used to control the number of times the duty cycle will be changed. 20 10 read-write - DUTY_INC_CH0 + DUTY_INC This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. 30 1 read-write - DUTY_START_CH0 + DUTY_START Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 @@ -8758,14 +8760,14 @@ The output value turns to low when the selected timers has reached the Lpoint.0x00800000 - TIMER0_DUTY_RES + DUTY_RES This register is used to control the range of the counter in timer %s. 0 4 read-write - CLK_DIV_TIMER0 + CLK_DIV This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. @@ -8774,21 +8776,21 @@ The least significant eight bits represent the fractional part. read-write - TIMER0_PAUSE + PAUSE This bit is used to suspend the counter in timer %s. 22 1 read-write - TIMER0_RST + RST This bit is used to reset timer %s. The counter will show 0 after reset. 23 1 read-write - TICK_SEL_TIMER0 + TICK_SEL This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK @@ -8797,7 +8799,7 @@ The least significant eight bits represent the fractional part. read-write - TIMER0_PARA_UP + PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 25 1 @@ -8814,7 +8816,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_CNT + CNT This register stores the current counter value of timer %s. 0 14 @@ -8829,7 +8831,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_RAW + OVF_INT_RAW Triggered when the timer0 has reached its maximum counter value. 0 1 @@ -8949,7 +8951,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_ST + OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. 0 1 @@ -9069,7 +9071,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_ENA + OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. 0 1 @@ -9189,7 +9191,7 @@ The least significant eight bits represent the fractional part. 0x20 - TIMER0_OVF_INT_CLR + OVF_INT_CLR Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. 0 1 @@ -13019,18 +13021,21 @@ The least significant eight bits represent the fractional part. The bit is used to enable timing adjust clock for all reading operations. 0 1 + read-only TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 + read-only EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 + read-only @@ -13045,24 +13050,28 @@ The least significant eight bits represent the fractional part. the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 0 2 + read-only DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 2 2 + read-only DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 4 2 + read-only DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 6 2 + read-only @@ -13077,24 +13086,28 @@ The least significant eight bits represent the fractional part. the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 0 1 + read-only DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 1 1 + read-only DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 2 1 + read-only DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 3 1 + read-only @@ -13109,24 +13122,28 @@ The least significant eight bits represent the fractional part. the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 0 1 + read-only DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 1 1 + read-only DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 2 1 + read-only DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 3 1 + read-only @@ -14290,12 +14307,14 @@ The least significant eight bits represent the fractional part. The bit is used to enable timing auto-calibration for all reading operations. 1 1 + read-only EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 + read-only @@ -14629,6 +14648,7 @@ The least significant eight bits represent the fractional part. Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 7 1 + read-only FCMD_DUAL @@ -14649,6 +14669,7 @@ The least significant eight bits represent the fractional part. Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 10 1 + read-only FREAD_DUAL @@ -14669,6 +14690,7 @@ The least significant eight bits represent the fractional part. In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. 16 1 + read-only Q_POL @@ -14784,6 +14806,7 @@ The least significant eight bits represent the fractional part. Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. 4 1 + read-only TSCK_I_EDGE @@ -14839,6 +14862,7 @@ The least significant eight bits represent the fractional part. In the write operations read-data phase apply 8 signals. Can be configured in CONF state. 14 1 + read-only USR_CONF_NXT @@ -15069,24 +15093,28 @@ The least significant eight bits represent the fractional part. 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 16 1 + read-only DATA_DTR_EN 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. 17 1 + read-only ADDR_DTR_EN 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. 18 1 + read-only CMD_DTR_EN 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. 19 1 + read-only SLAVE_CS_POL @@ -15100,6 +15128,7 @@ The least significant eight bits represent the fractional part. The default value of spi_dqs. Can be configured in CONF state. 24 1 + read-only CK_IDLE_EDGE @@ -15135,54 +15164,63 @@ The least significant eight bits represent the fractional part. the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 2 + read-only DIN1_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 2 2 + read-only DIN2_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 4 2 + read-only DIN3_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 2 + read-only DIN4_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 8 2 + read-only DIN5_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 10 2 + read-only DIN6_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 12 2 + read-only DIN7_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 14 2 + read-only TIMING_HCLK_ACTIVE 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. 16 1 + read-only @@ -15197,48 +15235,56 @@ The least significant eight bits represent the fractional part. the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 + read-only DIN1_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 + read-only DIN2_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 + read-only DIN3_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 + read-only DIN4_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 + read-only DIN5_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 + read-only DIN6_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 + read-only DIN7_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 + read-only @@ -15253,54 +15299,63 @@ The least significant eight bits represent the fractional part. The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 0 1 + read-only DOUT1_MODE The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 1 1 + read-only DOUT2_MODE The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 2 1 + read-only DOUT3_MODE The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 3 1 + read-only DOUT4_MODE The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 4 1 + read-only DOUT5_MODE The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 5 1 + read-only DOUT6_MODE The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 6 1 + read-only DOUT7_MODE The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 7 1 + read-only D_DQS_MODE The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 8 1 + read-only From 8cdd9c8463c8161bb0ec86aae2947283170b1b98 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 3 Nov 2022 10:54:16 -0700 Subject: [PATCH 2/4] Add new SVD for ESP32-C3 and regenerate --- esp32c3/src/dma/in_conf0_ch0.rs | 83 ++- esp32c3/src/dma/in_conf0_ch1.rs | 83 ++- esp32c3/src/dma/in_conf0_ch2.rs | 83 ++- esp32c3/src/dma/in_conf1_ch0.rs | 17 +- esp32c3/src/dma/in_conf1_ch1.rs | 17 +- esp32c3/src/dma/in_conf1_ch2.rs | 17 +- esp32c3/src/dma/in_dscr_bf0_ch0.rs | 8 +- esp32c3/src/dma/in_dscr_bf0_ch1.rs | 8 +- esp32c3/src/dma/in_dscr_bf0_ch2.rs | 8 +- esp32c3/src/dma/in_dscr_bf1_ch0.rs | 8 +- esp32c3/src/dma/in_dscr_bf1_ch1.rs | 8 +- esp32c3/src/dma/in_dscr_bf1_ch2.rs | 8 +- esp32c3/src/dma/in_dscr_ch0.rs | 8 +- esp32c3/src/dma/in_dscr_ch1.rs | 8 +- esp32c3/src/dma/in_dscr_ch2.rs | 8 +- esp32c3/src/dma/in_err_eof_des_addr_ch0.rs | 8 +- esp32c3/src/dma/in_err_eof_des_addr_ch1.rs | 8 +- esp32c3/src/dma/in_err_eof_des_addr_ch2.rs | 8 +- esp32c3/src/dma/in_link_ch0.rs | 90 ++- esp32c3/src/dma/in_link_ch1.rs | 90 ++- esp32c3/src/dma/in_link_ch2.rs | 90 ++- esp32c3/src/dma/in_peri_sel_ch0.rs | 16 +- esp32c3/src/dma/in_peri_sel_ch1.rs | 16 +- esp32c3/src/dma/in_peri_sel_ch2.rs | 16 +- esp32c3/src/dma/in_pop_ch0.rs | 24 +- esp32c3/src/dma/in_pop_ch1.rs | 24 +- esp32c3/src/dma/in_pop_ch2.rs | 24 +- esp32c3/src/dma/in_pri_ch0.rs | 16 +- esp32c3/src/dma/in_pri_ch1.rs | 16 +- esp32c3/src/dma/in_pri_ch2.rs | 16 +- esp32c3/src/dma/in_state_ch0.rs | 24 +- esp32c3/src/dma/in_state_ch1.rs | 24 +- esp32c3/src/dma/in_state_ch2.rs | 24 +- esp32c3/src/dma/in_suc_eof_des_addr_ch0.rs | 8 +- esp32c3/src/dma/in_suc_eof_des_addr_ch1.rs | 8 +- esp32c3/src/dma/in_suc_eof_des_addr_ch2.rs | 8 +- esp32c3/src/dma/infifo_status_ch0.rs | 64 +- esp32c3/src/dma/infifo_status_ch1.rs | 64 +- esp32c3/src/dma/infifo_status_ch2.rs | 64 +- esp32c3/src/dma/int_clr_ch0.rs | 117 ++-- esp32c3/src/dma/int_clr_ch1.rs | 117 ++-- esp32c3/src/dma/int_clr_ch2.rs | 117 ++-- esp32c3/src/dma/int_ena_ch0.rs | 221 +++--- esp32c3/src/dma/int_ena_ch1.rs | 221 +++--- esp32c3/src/dma/int_ena_ch2.rs | 221 +++--- esp32c3/src/dma/int_raw_ch0.rs | 104 +-- esp32c3/src/dma/int_raw_ch1.rs | 104 +-- esp32c3/src/dma/int_raw_ch2.rs | 104 +-- esp32c3/src/dma/int_st_ch0.rs | 104 +-- esp32c3/src/dma/int_st_ch1.rs | 104 +-- esp32c3/src/dma/int_st_ch2.rs | 104 +-- esp32c3/src/dma/out_conf0_ch0.rs | 98 ++- esp32c3/src/dma/out_conf0_ch1.rs | 98 ++- esp32c3/src/dma/out_conf0_ch2.rs | 98 ++- esp32c3/src/dma/out_conf1_ch0.rs | 16 +- esp32c3/src/dma/out_conf1_ch1.rs | 16 +- esp32c3/src/dma/out_conf1_ch2.rs | 16 +- esp32c3/src/dma/out_dscr_bf0_ch0.rs | 8 +- esp32c3/src/dma/out_dscr_bf0_ch1.rs | 8 +- esp32c3/src/dma/out_dscr_bf0_ch2.rs | 8 +- esp32c3/src/dma/out_dscr_bf1_ch0.rs | 8 +- esp32c3/src/dma/out_dscr_bf1_ch1.rs | 8 +- esp32c3/src/dma/out_dscr_bf1_ch2.rs | 8 +- esp32c3/src/dma/out_dscr_ch0.rs | 8 +- esp32c3/src/dma/out_dscr_ch1.rs | 8 +- esp32c3/src/dma/out_dscr_ch2.rs | 8 +- esp32c3/src/dma/out_eof_bfr_des_addr_ch0.rs | 8 +- esp32c3/src/dma/out_eof_bfr_des_addr_ch1.rs | 8 +- esp32c3/src/dma/out_eof_bfr_des_addr_ch2.rs | 8 +- esp32c3/src/dma/out_eof_des_addr_ch0.rs | 8 +- esp32c3/src/dma/out_eof_des_addr_ch1.rs | 8 +- esp32c3/src/dma/out_eof_des_addr_ch2.rs | 8 +- esp32c3/src/dma/out_link_ch0.rs | 75 +-- esp32c3/src/dma/out_link_ch1.rs | 75 +-- esp32c3/src/dma/out_link_ch2.rs | 75 +-- esp32c3/src/dma/out_peri_sel_ch0.rs | 16 +- esp32c3/src/dma/out_peri_sel_ch1.rs | 16 +- esp32c3/src/dma/out_peri_sel_ch2.rs | 16 +- esp32c3/src/dma/out_pri_ch0.rs | 17 +- esp32c3/src/dma/out_pri_ch1.rs | 17 +- esp32c3/src/dma/out_pri_ch2.rs | 17 +- esp32c3/src/dma/out_push_ch0.rs | 33 +- esp32c3/src/dma/out_push_ch1.rs | 33 +- esp32c3/src/dma/out_push_ch2.rs | 33 +- esp32c3/src/dma/out_state_ch0.rs | 24 +- esp32c3/src/dma/out_state_ch1.rs | 24 +- esp32c3/src/dma/out_state_ch2.rs | 24 +- esp32c3/src/dma/outfifo_status_ch0.rs | 56 +- esp32c3/src/dma/outfifo_status_ch1.rs | 56 +- esp32c3/src/dma/outfifo_status_ch2.rs | 56 +- esp32c3/svd/esp32c3.base.svd | 701 ++++++++++---------- 91 files changed, 2239 insertions(+), 2347 deletions(-) diff --git a/esp32c3/src/dma/in_conf0_ch0.rs b/esp32c3/src/dma/in_conf0_ch0.rs index 7df2eb5398..5f1c0183e0 100644 --- a/esp32c3/src/dma/in_conf0_ch0.rs +++ b/esp32c3/src/dma/in_conf0_ch0.rs @@ -34,82 +34,79 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_RST_CH0` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH0_R = crate::BitReader; -#[doc = "Field `IN_RST_CH0` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `IN_LOOP_TEST_CH0` reader - reserved"] -pub type IN_LOOP_TEST_CH0_R = crate::BitReader; -#[doc = "Field `IN_LOOP_TEST_CH0` writer - reserved"] -pub type IN_LOOP_TEST_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `INDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `INDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DATA_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `IN_DATA_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `MEM_TRANS_EN_CH0` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH0_R = crate::BitReader; -#[doc = "Field `MEM_TRANS_EN_CH0` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH0_W<'a, const O: u8> = +#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `IN_LOOP_TEST` reader - reserved"] +pub type IN_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST` writer - reserved"] +pub type IN_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch0(&self) -> IN_RST_CH0_R { - IN_RST_CH0_R::new((self.bits & 1) != 0) + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch0(&self) -> IN_LOOP_TEST_CH0_R { - IN_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_loop_test(&self) -> IN_LOOP_TEST_R { + IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch0(&self) -> INDSCR_BURST_EN_CH0_R { - INDSCR_BURST_EN_CH0_R::new(((self.bits >> 2) & 1) != 0) + pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R { + INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch0(&self) -> IN_DATA_BURST_EN_CH0_R { - IN_DATA_BURST_EN_CH0_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R { + IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch0(&self) -> MEM_TRANS_EN_CH0_R { - MEM_TRANS_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R { + MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch0(&mut self) -> IN_RST_CH0_W<0> { - IN_RST_CH0_W::new(self) + pub fn in_rst(&mut self) -> IN_RST_W<0> { + IN_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch0(&mut self) -> IN_LOOP_TEST_CH0_W<1> { - IN_LOOP_TEST_CH0_W::new(self) + pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<1> { + IN_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch0(&mut self) -> INDSCR_BURST_EN_CH0_W<2> { - INDSCR_BURST_EN_CH0_W::new(self) + pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<2> { + INDSCR_BURST_EN_W::new(self) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch0(&mut self) -> IN_DATA_BURST_EN_CH0_W<3> { - IN_DATA_BURST_EN_CH0_W::new(self) + pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<3> { + IN_DATA_BURST_EN_W::new(self) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch0(&mut self) -> MEM_TRANS_EN_CH0_W<4> { - MEM_TRANS_EN_CH0_W::new(self) + pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<4> { + MEM_TRANS_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_conf0_ch1.rs b/esp32c3/src/dma/in_conf0_ch1.rs index 140590089a..0b71103c4d 100644 --- a/esp32c3/src/dma/in_conf0_ch1.rs +++ b/esp32c3/src/dma/in_conf0_ch1.rs @@ -34,82 +34,79 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_RST_CH1` reader - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH1_R = crate::BitReader; -#[doc = "Field `IN_RST_CH1` writer - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `IN_LOOP_TEST_CH1` reader - reserved"] -pub type IN_LOOP_TEST_CH1_R = crate::BitReader; -#[doc = "Field `IN_LOOP_TEST_CH1` writer - reserved"] -pub type IN_LOOP_TEST_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `INDSCR_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH1_R = crate::BitReader; -#[doc = "Field `INDSCR_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `IN_DATA_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH1_R = crate::BitReader; -#[doc = "Field `IN_DATA_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `MEM_TRANS_EN_CH1` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH1_R = crate::BitReader; -#[doc = "Field `MEM_TRANS_EN_CH1` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH1_W<'a, const O: u8> = +#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `IN_LOOP_TEST` reader - reserved"] +pub type IN_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST` writer - reserved"] +pub type IN_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH1_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch1(&self) -> IN_RST_CH1_R { - IN_RST_CH1_R::new((self.bits & 1) != 0) + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch1(&self) -> IN_LOOP_TEST_CH1_R { - IN_LOOP_TEST_CH1_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_loop_test(&self) -> IN_LOOP_TEST_R { + IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch1(&self) -> INDSCR_BURST_EN_CH1_R { - INDSCR_BURST_EN_CH1_R::new(((self.bits >> 2) & 1) != 0) + pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R { + INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch1(&self) -> IN_DATA_BURST_EN_CH1_R { - IN_DATA_BURST_EN_CH1_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R { + IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch1(&self) -> MEM_TRANS_EN_CH1_R { - MEM_TRANS_EN_CH1_R::new(((self.bits >> 4) & 1) != 0) + pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R { + MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch1(&mut self) -> IN_RST_CH1_W<0> { - IN_RST_CH1_W::new(self) + pub fn in_rst(&mut self) -> IN_RST_W<0> { + IN_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch1(&mut self) -> IN_LOOP_TEST_CH1_W<1> { - IN_LOOP_TEST_CH1_W::new(self) + pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<1> { + IN_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch1(&mut self) -> INDSCR_BURST_EN_CH1_W<2> { - INDSCR_BURST_EN_CH1_W::new(self) + pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<2> { + INDSCR_BURST_EN_W::new(self) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch1(&mut self) -> IN_DATA_BURST_EN_CH1_W<3> { - IN_DATA_BURST_EN_CH1_W::new(self) + pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<3> { + IN_DATA_BURST_EN_W::new(self) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch1(&mut self) -> MEM_TRANS_EN_CH1_W<4> { - MEM_TRANS_EN_CH1_W::new(self) + pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<4> { + MEM_TRANS_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_conf0_ch2.rs b/esp32c3/src/dma/in_conf0_ch2.rs index 2edd195918..9d6b087f4a 100644 --- a/esp32c3/src/dma/in_conf0_ch2.rs +++ b/esp32c3/src/dma/in_conf0_ch2.rs @@ -34,82 +34,79 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_RST_CH2` reader - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH2_R = crate::BitReader; -#[doc = "Field `IN_RST_CH2` writer - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `IN_LOOP_TEST_CH2` reader - reserved"] -pub type IN_LOOP_TEST_CH2_R = crate::BitReader; -#[doc = "Field `IN_LOOP_TEST_CH2` writer - reserved"] -pub type IN_LOOP_TEST_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `INDSCR_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH2_R = crate::BitReader; -#[doc = "Field `INDSCR_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `IN_DATA_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH2_R = crate::BitReader; -#[doc = "Field `IN_DATA_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `MEM_TRANS_EN_CH2` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH2_R = crate::BitReader; -#[doc = "Field `MEM_TRANS_EN_CH2` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH2_W<'a, const O: u8> = +#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `IN_LOOP_TEST` reader - reserved"] +pub type IN_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST` writer - reserved"] +pub type IN_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH2_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch2(&self) -> IN_RST_CH2_R { - IN_RST_CH2_R::new((self.bits & 1) != 0) + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch2(&self) -> IN_LOOP_TEST_CH2_R { - IN_LOOP_TEST_CH2_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_loop_test(&self) -> IN_LOOP_TEST_R { + IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch2(&self) -> INDSCR_BURST_EN_CH2_R { - INDSCR_BURST_EN_CH2_R::new(((self.bits >> 2) & 1) != 0) + pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R { + INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch2(&self) -> IN_DATA_BURST_EN_CH2_R { - IN_DATA_BURST_EN_CH2_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R { + IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch2(&self) -> MEM_TRANS_EN_CH2_R { - MEM_TRANS_EN_CH2_R::new(((self.bits >> 4) & 1) != 0) + pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R { + MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch2(&mut self) -> IN_RST_CH2_W<0> { - IN_RST_CH2_W::new(self) + pub fn in_rst(&mut self) -> IN_RST_W<0> { + IN_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch2(&mut self) -> IN_LOOP_TEST_CH2_W<1> { - IN_LOOP_TEST_CH2_W::new(self) + pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<1> { + IN_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch2(&mut self) -> INDSCR_BURST_EN_CH2_W<2> { - INDSCR_BURST_EN_CH2_W::new(self) + pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<2> { + INDSCR_BURST_EN_W::new(self) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch2(&mut self) -> IN_DATA_BURST_EN_CH2_W<3> { - IN_DATA_BURST_EN_CH2_W::new(self) + pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<3> { + IN_DATA_BURST_EN_W::new(self) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch2(&mut self) -> MEM_TRANS_EN_CH2_W<4> { - MEM_TRANS_EN_CH2_W::new(self) + pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<4> { + MEM_TRANS_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_conf1_ch0.rs b/esp32c3/src/dma/in_conf1_ch0.rs index 4a0361e357..9c3aad2cdd 100644 --- a/esp32c3/src/dma/in_conf1_ch0.rs +++ b/esp32c3/src/dma/in_conf1_ch0.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH0_R = crate::BitReader; -#[doc = "Field `IN_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF1_CH0_SPEC, bool, O>; +#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF1_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch0(&self) -> IN_CHECK_OWNER_CH0_R { - IN_CHECK_OWNER_CH0_R::new(((self.bits >> 12) & 1) != 0) + pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R { + IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch0(&mut self) -> IN_CHECK_OWNER_CH0_W<12> { - IN_CHECK_OWNER_CH0_W::new(self) + pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<12> { + IN_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_conf1_ch1.rs b/esp32c3/src/dma/in_conf1_ch1.rs index 200d148ac6..cac852e291 100644 --- a/esp32c3/src/dma/in_conf1_ch1.rs +++ b/esp32c3/src/dma/in_conf1_ch1.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_CHECK_OWNER_CH1` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH1_R = crate::BitReader; -#[doc = "Field `IN_CHECK_OWNER_CH1` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF1_CH1_SPEC, bool, O>; +#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF1_CH1_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch1(&self) -> IN_CHECK_OWNER_CH1_R { - IN_CHECK_OWNER_CH1_R::new(((self.bits >> 12) & 1) != 0) + pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R { + IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch1(&mut self) -> IN_CHECK_OWNER_CH1_W<12> { - IN_CHECK_OWNER_CH1_W::new(self) + pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<12> { + IN_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_conf1_ch2.rs b/esp32c3/src/dma/in_conf1_ch2.rs index 6bcf487479..efc5764c6d 100644 --- a/esp32c3/src/dma/in_conf1_ch2.rs +++ b/esp32c3/src/dma/in_conf1_ch2.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_CHECK_OWNER_CH2` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH2_R = crate::BitReader; -#[doc = "Field `IN_CHECK_OWNER_CH2` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF1_CH2_SPEC, bool, O>; +#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF1_CH2_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch2(&self) -> IN_CHECK_OWNER_CH2_R { - IN_CHECK_OWNER_CH2_R::new(((self.bits >> 12) & 1) != 0) + pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R { + IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch2(&mut self) -> IN_CHECK_OWNER_CH2_W<12> { - IN_CHECK_OWNER_CH2_W::new(self) + pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<12> { + IN_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_dscr_bf0_ch0.rs b/esp32c3/src/dma/in_dscr_bf0_ch0.rs index 9366e4d475..12c6135371 100644 --- a/esp32c3/src/dma/in_dscr_bf0_ch0.rs +++ b/esp32c3/src/dma/in_dscr_bf0_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF0_CH0` reader - The address of the last inlink descriptor x-1."] -pub type INLINK_DSCR_BF0_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] #[inline(always)] - pub fn inlink_dscr_bf0_ch0(&self) -> INLINK_DSCR_BF0_CH0_R { - INLINK_DSCR_BF0_CH0_R::new(self.bits) + pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R { + INLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF0_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf0_ch0](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_bf0_ch1.rs b/esp32c3/src/dma/in_dscr_bf0_ch1.rs index 2829e90141..b481d0b6af 100644 --- a/esp32c3/src/dma/in_dscr_bf0_ch1.rs +++ b/esp32c3/src/dma/in_dscr_bf0_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF0_CH1` reader - The address of the last inlink descriptor x-1."] -pub type INLINK_DSCR_BF0_CH1_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] #[inline(always)] - pub fn inlink_dscr_bf0_ch1(&self) -> INLINK_DSCR_BF0_CH1_R { - INLINK_DSCR_BF0_CH1_R::new(self.bits) + pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R { + INLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF0_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf0_ch1](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_bf0_ch2.rs b/esp32c3/src/dma/in_dscr_bf0_ch2.rs index 72e9340c11..3904816949 100644 --- a/esp32c3/src/dma/in_dscr_bf0_ch2.rs +++ b/esp32c3/src/dma/in_dscr_bf0_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF0_CH2` reader - The address of the last inlink descriptor x-1."] -pub type INLINK_DSCR_BF0_CH2_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] #[inline(always)] - pub fn inlink_dscr_bf0_ch2(&self) -> INLINK_DSCR_BF0_CH2_R { - INLINK_DSCR_BF0_CH2_R::new(self.bits) + pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R { + INLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF0_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf0_ch2](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_bf1_ch0.rs b/esp32c3/src/dma/in_dscr_bf1_ch0.rs index b0a20e860b..eb5866359c 100644 --- a/esp32c3/src/dma/in_dscr_bf1_ch0.rs +++ b/esp32c3/src/dma/in_dscr_bf1_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF1_CH0` reader - The address of the second-to-last inlink descriptor x-2."] -pub type INLINK_DSCR_BF1_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn inlink_dscr_bf1_ch0(&self) -> INLINK_DSCR_BF1_CH0_R { - INLINK_DSCR_BF1_CH0_R::new(self.bits) + pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R { + INLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF1_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf1_ch0](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_bf1_ch1.rs b/esp32c3/src/dma/in_dscr_bf1_ch1.rs index a31daf0a5d..171f28d294 100644 --- a/esp32c3/src/dma/in_dscr_bf1_ch1.rs +++ b/esp32c3/src/dma/in_dscr_bf1_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF1_CH1` reader - The address of the second-to-last inlink descriptor x-2."] -pub type INLINK_DSCR_BF1_CH1_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn inlink_dscr_bf1_ch1(&self) -> INLINK_DSCR_BF1_CH1_R { - INLINK_DSCR_BF1_CH1_R::new(self.bits) + pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R { + INLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF1_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf1_ch1](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_bf1_ch2.rs b/esp32c3/src/dma/in_dscr_bf1_ch2.rs index 7a7a1721d0..e561ed0bd6 100644 --- a/esp32c3/src/dma/in_dscr_bf1_ch2.rs +++ b/esp32c3/src/dma/in_dscr_bf1_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF1_CH2` reader - The address of the second-to-last inlink descriptor x-2."] -pub type INLINK_DSCR_BF1_CH2_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn inlink_dscr_bf1_ch2(&self) -> INLINK_DSCR_BF1_CH2_R { - INLINK_DSCR_BF1_CH2_R::new(self.bits) + pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R { + INLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_BF1_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf1_ch2](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_ch0.rs b/esp32c3/src/dma/in_dscr_ch0.rs index 25c4e20c25..dbcd90aed0 100644 --- a/esp32c3/src/dma/in_dscr_ch0.rs +++ b/esp32c3/src/dma/in_dscr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_CH0` reader - The address of the current inlink descriptor x."] -pub type INLINK_DSCR_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] #[inline(always)] - pub fn inlink_dscr_ch0(&self) -> INLINK_DSCR_CH0_R { - INLINK_DSCR_CH0_R::new(self.bits) + pub fn inlink_dscr(&self) -> INLINK_DSCR_R { + INLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_ch0](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_ch1.rs b/esp32c3/src/dma/in_dscr_ch1.rs index 389d052804..539e493042 100644 --- a/esp32c3/src/dma/in_dscr_ch1.rs +++ b/esp32c3/src/dma/in_dscr_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_CH1` reader - The address of the current inlink descriptor x."] -pub type INLINK_DSCR_CH1_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] #[inline(always)] - pub fn inlink_dscr_ch1(&self) -> INLINK_DSCR_CH1_R { - INLINK_DSCR_CH1_R::new(self.bits) + pub fn inlink_dscr(&self) -> INLINK_DSCR_R { + INLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_ch1](index.html) module"] diff --git a/esp32c3/src/dma/in_dscr_ch2.rs b/esp32c3/src/dma/in_dscr_ch2.rs index a36c735ee6..dcb080bce0 100644 --- a/esp32c3/src/dma/in_dscr_ch2.rs +++ b/esp32c3/src/dma/in_dscr_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_CH2` reader - The address of the current inlink descriptor x."] -pub type INLINK_DSCR_CH2_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] #[inline(always)] - pub fn inlink_dscr_ch2(&self) -> INLINK_DSCR_CH2_R { - INLINK_DSCR_CH2_R::new(self.bits) + pub fn inlink_dscr(&self) -> INLINK_DSCR_R { + INLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_IN_DSCR_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_ch2](index.html) module"] diff --git a/esp32c3/src/dma/in_err_eof_des_addr_ch0.rs b/esp32c3/src/dma/in_err_eof_des_addr_ch0.rs index 33ad6dad0c..7ea488fb6c 100644 --- a/esp32c3/src/dma/in_err_eof_des_addr_ch0.rs +++ b/esp32c3/src/dma/in_err_eof_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] -pub type IN_ERR_EOF_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] #[inline(always)] - pub fn in_err_eof_des_addr_ch0(&self) -> IN_ERR_EOF_DES_ADDR_CH0_R { - IN_ERR_EOF_DES_ADDR_CH0_R::new(self.bits) + pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R { + IN_ERR_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_err_eof_des_addr_ch0](index.html) module"] diff --git a/esp32c3/src/dma/in_err_eof_des_addr_ch1.rs b/esp32c3/src/dma/in_err_eof_des_addr_ch1.rs index 6f1315a6cf..6e98654afa 100644 --- a/esp32c3/src/dma/in_err_eof_des_addr_ch1.rs +++ b/esp32c3/src/dma/in_err_eof_des_addr_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH1` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] -pub type IN_ERR_EOF_DES_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] #[inline(always)] - pub fn in_err_eof_des_addr_ch1(&self) -> IN_ERR_EOF_DES_ADDR_CH1_R { - IN_ERR_EOF_DES_ADDR_CH1_R::new(self.bits) + pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R { + IN_ERR_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_err_eof_des_addr_ch1](index.html) module"] diff --git a/esp32c3/src/dma/in_err_eof_des_addr_ch2.rs b/esp32c3/src/dma/in_err_eof_des_addr_ch2.rs index 412256b8f1..ba8292bd7c 100644 --- a/esp32c3/src/dma/in_err_eof_des_addr_ch2.rs +++ b/esp32c3/src/dma/in_err_eof_des_addr_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH2` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] -pub type IN_ERR_EOF_DES_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] #[inline(always)] - pub fn in_err_eof_des_addr_ch2(&self) -> IN_ERR_EOF_DES_ADDR_CH2_R { - IN_ERR_EOF_DES_ADDR_CH2_R::new(self.bits) + pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R { + IN_ERR_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_err_eof_des_addr_ch2](index.html) module"] diff --git a/esp32c3/src/dma/in_link_ch0.rs b/esp32c3/src/dma/in_link_ch0.rs index e6765036f3..bdd2862d31 100644 --- a/esp32c3/src/dma/in_link_ch0.rs +++ b/esp32c3/src/dma/in_link_ch0.rs @@ -34,88 +34,86 @@ impl From> for W { W(writer) } } -#[doc = "Field `INLINK_ADDR_CH0` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `INLINK_ADDR_CH0` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH0_W<'a, const O: u8> = +#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_LINK_CH0_SPEC, u32, u32, 20, O>; -#[doc = "Field `INLINK_AUTO_RET_CH0` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_AUTO_RET_CH0` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_STOP_CH0` reader - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_STOP_CH0` writer - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_START_CH0` reader - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_START_CH0` writer - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_RESTART_CH0` reader - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH0_R = crate::BitReader; -#[doc = "Field `INLINK_RESTART_CH0` writer - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `INLINK_PARK_CH0` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] -pub type INLINK_PARK_CH0_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_START` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `INLINK_PARK` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch0(&self) -> INLINK_ADDR_CH0_R { - INLINK_ADDR_CH0_R::new((self.bits & 0x000f_ffff) as u32) + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch0(&self) -> INLINK_AUTO_RET_CH0_R { - INLINK_AUTO_RET_CH0_R::new(((self.bits >> 20) & 1) != 0) + pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R { + INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch0(&self) -> INLINK_STOP_CH0_R { - INLINK_STOP_CH0_R::new(((self.bits >> 21) & 1) != 0) + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch0(&self) -> INLINK_START_CH0_R { - INLINK_START_CH0_R::new(((self.bits >> 22) & 1) != 0) + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch0(&self) -> INLINK_RESTART_CH0_R { - INLINK_RESTART_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] #[inline(always)] - pub fn inlink_park_ch0(&self) -> INLINK_PARK_CH0_R { - INLINK_PARK_CH0_R::new(((self.bits >> 24) & 1) != 0) + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 24) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch0(&mut self) -> INLINK_ADDR_CH0_W<0> { - INLINK_ADDR_CH0_W::new(self) + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<0> { + INLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch0(&mut self) -> INLINK_AUTO_RET_CH0_W<20> { - INLINK_AUTO_RET_CH0_W::new(self) + pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<20> { + INLINK_AUTO_RET_W::new(self) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch0(&mut self) -> INLINK_STOP_CH0_W<21> { - INLINK_STOP_CH0_W::new(self) + pub fn inlink_stop(&mut self) -> INLINK_STOP_W<21> { + INLINK_STOP_W::new(self) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch0(&mut self) -> INLINK_START_CH0_W<22> { - INLINK_START_CH0_W::new(self) + pub fn inlink_start(&mut self) -> INLINK_START_W<22> { + INLINK_START_W::new(self) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch0(&mut self) -> INLINK_RESTART_CH0_W<23> { - INLINK_RESTART_CH0_W::new(self) + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<23> { + INLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_link_ch1.rs b/esp32c3/src/dma/in_link_ch1.rs index d0742d2344..07e6bb70e3 100644 --- a/esp32c3/src/dma/in_link_ch1.rs +++ b/esp32c3/src/dma/in_link_ch1.rs @@ -34,88 +34,86 @@ impl From> for W { W(writer) } } -#[doc = "Field `INLINK_ADDR_CH1` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH1_R = crate::FieldReader; -#[doc = "Field `INLINK_ADDR_CH1` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH1_W<'a, const O: u8> = +#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_LINK_CH1_SPEC, u32, u32, 20, O>; -#[doc = "Field `INLINK_AUTO_RET_CH1` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH1_R = crate::BitReader; -#[doc = "Field `INLINK_AUTO_RET_CH1` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `INLINK_STOP_CH1` reader - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH1_R = crate::BitReader; -#[doc = "Field `INLINK_STOP_CH1` writer - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `INLINK_START_CH1` reader - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH1_R = crate::BitReader; -#[doc = "Field `INLINK_START_CH1` writer - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `INLINK_RESTART_CH1` reader - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH1_R = crate::BitReader; -#[doc = "Field `INLINK_RESTART_CH1` writer - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `INLINK_PARK_CH1` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] -pub type INLINK_PARK_CH1_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `INLINK_START` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `INLINK_PARK` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch1(&self) -> INLINK_ADDR_CH1_R { - INLINK_ADDR_CH1_R::new((self.bits & 0x000f_ffff) as u32) + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch1(&self) -> INLINK_AUTO_RET_CH1_R { - INLINK_AUTO_RET_CH1_R::new(((self.bits >> 20) & 1) != 0) + pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R { + INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch1(&self) -> INLINK_STOP_CH1_R { - INLINK_STOP_CH1_R::new(((self.bits >> 21) & 1) != 0) + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch1(&self) -> INLINK_START_CH1_R { - INLINK_START_CH1_R::new(((self.bits >> 22) & 1) != 0) + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch1(&self) -> INLINK_RESTART_CH1_R { - INLINK_RESTART_CH1_R::new(((self.bits >> 23) & 1) != 0) + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] #[inline(always)] - pub fn inlink_park_ch1(&self) -> INLINK_PARK_CH1_R { - INLINK_PARK_CH1_R::new(((self.bits >> 24) & 1) != 0) + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 24) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch1(&mut self) -> INLINK_ADDR_CH1_W<0> { - INLINK_ADDR_CH1_W::new(self) + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<0> { + INLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch1(&mut self) -> INLINK_AUTO_RET_CH1_W<20> { - INLINK_AUTO_RET_CH1_W::new(self) + pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<20> { + INLINK_AUTO_RET_W::new(self) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch1(&mut self) -> INLINK_STOP_CH1_W<21> { - INLINK_STOP_CH1_W::new(self) + pub fn inlink_stop(&mut self) -> INLINK_STOP_W<21> { + INLINK_STOP_W::new(self) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch1(&mut self) -> INLINK_START_CH1_W<22> { - INLINK_START_CH1_W::new(self) + pub fn inlink_start(&mut self) -> INLINK_START_W<22> { + INLINK_START_W::new(self) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch1(&mut self) -> INLINK_RESTART_CH1_W<23> { - INLINK_RESTART_CH1_W::new(self) + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<23> { + INLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_link_ch2.rs b/esp32c3/src/dma/in_link_ch2.rs index 3c1be277f5..24df35ff39 100644 --- a/esp32c3/src/dma/in_link_ch2.rs +++ b/esp32c3/src/dma/in_link_ch2.rs @@ -34,88 +34,86 @@ impl From> for W { W(writer) } } -#[doc = "Field `INLINK_ADDR_CH2` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH2_R = crate::FieldReader; -#[doc = "Field `INLINK_ADDR_CH2` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH2_W<'a, const O: u8> = +#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_LINK_CH2_SPEC, u32, u32, 20, O>; -#[doc = "Field `INLINK_AUTO_RET_CH2` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH2_R = crate::BitReader; -#[doc = "Field `INLINK_AUTO_RET_CH2` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `INLINK_STOP_CH2` reader - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH2_R = crate::BitReader; -#[doc = "Field `INLINK_STOP_CH2` writer - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `INLINK_START_CH2` reader - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH2_R = crate::BitReader; -#[doc = "Field `INLINK_START_CH2` writer - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `INLINK_RESTART_CH2` reader - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH2_R = crate::BitReader; -#[doc = "Field `INLINK_RESTART_CH2` writer - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `INLINK_PARK_CH2` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] -pub type INLINK_PARK_CH2_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `INLINK_START` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `INLINK_PARK` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch2(&self) -> INLINK_ADDR_CH2_R { - INLINK_ADDR_CH2_R::new((self.bits & 0x000f_ffff) as u32) + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch2(&self) -> INLINK_AUTO_RET_CH2_R { - INLINK_AUTO_RET_CH2_R::new(((self.bits >> 20) & 1) != 0) + pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R { + INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch2(&self) -> INLINK_STOP_CH2_R { - INLINK_STOP_CH2_R::new(((self.bits >> 21) & 1) != 0) + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch2(&self) -> INLINK_START_CH2_R { - INLINK_START_CH2_R::new(((self.bits >> 22) & 1) != 0) + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch2(&self) -> INLINK_RESTART_CH2_R { - INLINK_RESTART_CH2_R::new(((self.bits >> 23) & 1) != 0) + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] #[inline(always)] - pub fn inlink_park_ch2(&self) -> INLINK_PARK_CH2_R { - INLINK_PARK_CH2_R::new(((self.bits >> 24) & 1) != 0) + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 24) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch2(&mut self) -> INLINK_ADDR_CH2_W<0> { - INLINK_ADDR_CH2_W::new(self) + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<0> { + INLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch2(&mut self) -> INLINK_AUTO_RET_CH2_W<20> { - INLINK_AUTO_RET_CH2_W::new(self) + pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<20> { + INLINK_AUTO_RET_W::new(self) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch2(&mut self) -> INLINK_STOP_CH2_W<21> { - INLINK_STOP_CH2_W::new(self) + pub fn inlink_stop(&mut self) -> INLINK_STOP_W<21> { + INLINK_STOP_W::new(self) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch2(&mut self) -> INLINK_START_CH2_W<22> { - INLINK_START_CH2_W::new(self) + pub fn inlink_start(&mut self) -> INLINK_START_W<22> { + INLINK_START_W::new(self) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch2(&mut self) -> INLINK_RESTART_CH2_W<23> { - INLINK_RESTART_CH2_W::new(self) + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<23> { + INLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_peri_sel_ch0.rs b/esp32c3/src/dma/in_peri_sel_ch0.rs index 1ff573e489..767077803f 100644 --- a/esp32c3/src/dma/in_peri_sel_ch0.rs +++ b/esp32c3/src/dma/in_peri_sel_ch0.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_IN_SEL_CH0` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH0_R = crate::FieldReader; -#[doc = "Field `PERI_IN_SEL_CH0` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH0_W<'a, const O: u8> = +#[doc = "Field `PERI_IN_SEL` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PERI_SEL_CH0_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch0(&self) -> PERI_IN_SEL_CH0_R { - PERI_IN_SEL_CH0_R::new((self.bits & 0x3f) as u8) + pub fn peri_in_sel(&self) -> PERI_IN_SEL_R { + PERI_IN_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch0(&mut self) -> PERI_IN_SEL_CH0_W<0> { - PERI_IN_SEL_CH0_W::new(self) + pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<0> { + PERI_IN_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_peri_sel_ch1.rs b/esp32c3/src/dma/in_peri_sel_ch1.rs index fc9ba87619..b53da095bb 100644 --- a/esp32c3/src/dma/in_peri_sel_ch1.rs +++ b/esp32c3/src/dma/in_peri_sel_ch1.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_IN_SEL_CH1` reader - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH1_R = crate::FieldReader; -#[doc = "Field `PERI_IN_SEL_CH1` writer - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH1_W<'a, const O: u8> = +#[doc = "Field `PERI_IN_SEL` reader - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL` writer - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PERI_SEL_CH1_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch1(&self) -> PERI_IN_SEL_CH1_R { - PERI_IN_SEL_CH1_R::new((self.bits & 0x3f) as u8) + pub fn peri_in_sel(&self) -> PERI_IN_SEL_R { + PERI_IN_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch1(&mut self) -> PERI_IN_SEL_CH1_W<0> { - PERI_IN_SEL_CH1_W::new(self) + pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<0> { + PERI_IN_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_peri_sel_ch2.rs b/esp32c3/src/dma/in_peri_sel_ch2.rs index b91ed07ece..c49fc98f15 100644 --- a/esp32c3/src/dma/in_peri_sel_ch2.rs +++ b/esp32c3/src/dma/in_peri_sel_ch2.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_IN_SEL_CH2` reader - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH2_R = crate::FieldReader; -#[doc = "Field `PERI_IN_SEL_CH2` writer - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_IN_SEL_CH2_W<'a, const O: u8> = +#[doc = "Field `PERI_IN_SEL` reader - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL` writer - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_IN_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PERI_SEL_CH2_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch2(&self) -> PERI_IN_SEL_CH2_R { - PERI_IN_SEL_CH2_R::new((self.bits & 0x3f) as u8) + pub fn peri_in_sel(&self) -> PERI_IN_SEL_R { + PERI_IN_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_in_sel_ch2(&mut self) -> PERI_IN_SEL_CH2_W<0> { - PERI_IN_SEL_CH2_W::new(self) + pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<0> { + PERI_IN_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_pop_ch0.rs b/esp32c3/src/dma/in_pop_ch0.rs index 2cffd56ebf..6b5dccd344 100644 --- a/esp32c3/src/dma/in_pop_ch0.rs +++ b/esp32c3/src/dma/in_pop_ch0.rs @@ -34,29 +34,29 @@ impl From> for W { W(writer) } } -#[doc = "Field `INFIFO_RDATA_CH0` reader - This register stores the data popping from DMA FIFO."] -pub type INFIFO_RDATA_CH0_R = crate::FieldReader; -#[doc = "Field `INFIFO_POP_CH0` reader - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH0_R = crate::BitReader; -#[doc = "Field `INFIFO_POP_CH0` writer - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_RDATA` reader - This register stores the data popping from DMA FIFO."] +pub type INFIFO_RDATA_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP` reader - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_R = crate::BitReader; +#[doc = "Field `INFIFO_POP` writer - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH0_SPEC, bool, O>; impl R { #[doc = "Bits 0:11 - This register stores the data popping from DMA FIFO."] #[inline(always)] - pub fn infifo_rdata_ch0(&self) -> INFIFO_RDATA_CH0_R { - INFIFO_RDATA_CH0_R::new((self.bits & 0x0fff) as u16) + pub fn infifo_rdata(&self) -> INFIFO_RDATA_R { + INFIFO_RDATA_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch0(&self) -> INFIFO_POP_CH0_R { - INFIFO_POP_CH0_R::new(((self.bits >> 12) & 1) != 0) + pub fn infifo_pop(&self) -> INFIFO_POP_R { + INFIFO_POP_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch0(&mut self) -> INFIFO_POP_CH0_W<12> { - INFIFO_POP_CH0_W::new(self) + pub fn infifo_pop(&mut self) -> INFIFO_POP_W<12> { + INFIFO_POP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_pop_ch1.rs b/esp32c3/src/dma/in_pop_ch1.rs index d84fd8371f..92ddbde041 100644 --- a/esp32c3/src/dma/in_pop_ch1.rs +++ b/esp32c3/src/dma/in_pop_ch1.rs @@ -34,29 +34,29 @@ impl From> for W { W(writer) } } -#[doc = "Field `INFIFO_RDATA_CH1` reader - This register stores the data popping from DMA FIFO."] -pub type INFIFO_RDATA_CH1_R = crate::FieldReader; -#[doc = "Field `INFIFO_POP_CH1` reader - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH1_R = crate::BitReader; -#[doc = "Field `INFIFO_POP_CH1` writer - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH1_SPEC, bool, O>; +#[doc = "Field `INFIFO_RDATA` reader - This register stores the data popping from DMA FIFO."] +pub type INFIFO_RDATA_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP` reader - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_R = crate::BitReader; +#[doc = "Field `INFIFO_POP` writer - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH1_SPEC, bool, O>; impl R { #[doc = "Bits 0:11 - This register stores the data popping from DMA FIFO."] #[inline(always)] - pub fn infifo_rdata_ch1(&self) -> INFIFO_RDATA_CH1_R { - INFIFO_RDATA_CH1_R::new((self.bits & 0x0fff) as u16) + pub fn infifo_rdata(&self) -> INFIFO_RDATA_R { + INFIFO_RDATA_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch1(&self) -> INFIFO_POP_CH1_R { - INFIFO_POP_CH1_R::new(((self.bits >> 12) & 1) != 0) + pub fn infifo_pop(&self) -> INFIFO_POP_R { + INFIFO_POP_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch1(&mut self) -> INFIFO_POP_CH1_W<12> { - INFIFO_POP_CH1_W::new(self) + pub fn infifo_pop(&mut self) -> INFIFO_POP_W<12> { + INFIFO_POP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_pop_ch2.rs b/esp32c3/src/dma/in_pop_ch2.rs index 0d17c6c449..84248e3c29 100644 --- a/esp32c3/src/dma/in_pop_ch2.rs +++ b/esp32c3/src/dma/in_pop_ch2.rs @@ -34,29 +34,29 @@ impl From> for W { W(writer) } } -#[doc = "Field `INFIFO_RDATA_CH2` reader - This register stores the data popping from DMA FIFO."] -pub type INFIFO_RDATA_CH2_R = crate::FieldReader; -#[doc = "Field `INFIFO_POP_CH2` reader - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH2_R = crate::BitReader; -#[doc = "Field `INFIFO_POP_CH2` writer - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH2_SPEC, bool, O>; +#[doc = "Field `INFIFO_RDATA` reader - This register stores the data popping from DMA FIFO."] +pub type INFIFO_RDATA_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP` reader - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_R = crate::BitReader; +#[doc = "Field `INFIFO_POP` writer - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH2_SPEC, bool, O>; impl R { #[doc = "Bits 0:11 - This register stores the data popping from DMA FIFO."] #[inline(always)] - pub fn infifo_rdata_ch2(&self) -> INFIFO_RDATA_CH2_R { - INFIFO_RDATA_CH2_R::new((self.bits & 0x0fff) as u16) + pub fn infifo_rdata(&self) -> INFIFO_RDATA_R { + INFIFO_RDATA_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch2(&self) -> INFIFO_POP_CH2_R { - INFIFO_POP_CH2_R::new(((self.bits >> 12) & 1) != 0) + pub fn infifo_pop(&self) -> INFIFO_POP_R { + INFIFO_POP_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch2(&mut self) -> INFIFO_POP_CH2_W<12> { - INFIFO_POP_CH2_W::new(self) + pub fn infifo_pop(&mut self) -> INFIFO_POP_W<12> { + INFIFO_POP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_pri_ch0.rs b/esp32c3/src/dma/in_pri_ch0.rs index 8bd43615d1..842e23c300 100644 --- a/esp32c3/src/dma/in_pri_ch0.rs +++ b/esp32c3/src/dma/in_pri_ch0.rs @@ -34,22 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `RX_PRI_CH0` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH0_R = crate::FieldReader; -#[doc = "Field `RX_PRI_CH0` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH0_SPEC, u8, u8, 4, O>; +#[doc = "Field `RX_PRI` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."] +pub type RX_PRI_R = crate::FieldReader; +#[doc = "Field `RX_PRI` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."] +pub type RX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH0_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch0(&self) -> RX_PRI_CH0_R { - RX_PRI_CH0_R::new((self.bits & 0x0f) as u8) + pub fn rx_pri(&self) -> RX_PRI_R { + RX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch0(&mut self) -> RX_PRI_CH0_W<0> { - RX_PRI_CH0_W::new(self) + pub fn rx_pri(&mut self) -> RX_PRI_W<0> { + RX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_pri_ch1.rs b/esp32c3/src/dma/in_pri_ch1.rs index 161a24a0d7..c558f5913f 100644 --- a/esp32c3/src/dma/in_pri_ch1.rs +++ b/esp32c3/src/dma/in_pri_ch1.rs @@ -34,22 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `RX_PRI_CH1` reader - The priority of Rx channel 1. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH1_R = crate::FieldReader; -#[doc = "Field `RX_PRI_CH1` writer - The priority of Rx channel 1. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH1_SPEC, u8, u8, 4, O>; +#[doc = "Field `RX_PRI` reader - The priority of Rx channel 1. The larger of the value, the higher of the priority."] +pub type RX_PRI_R = crate::FieldReader; +#[doc = "Field `RX_PRI` writer - The priority of Rx channel 1. The larger of the value, the higher of the priority."] +pub type RX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH1_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Rx channel 1. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch1(&self) -> RX_PRI_CH1_R { - RX_PRI_CH1_R::new((self.bits & 0x0f) as u8) + pub fn rx_pri(&self) -> RX_PRI_R { + RX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Rx channel 1. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch1(&mut self) -> RX_PRI_CH1_W<0> { - RX_PRI_CH1_W::new(self) + pub fn rx_pri(&mut self) -> RX_PRI_W<0> { + RX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_pri_ch2.rs b/esp32c3/src/dma/in_pri_ch2.rs index b8e64103bc..6849c72eb0 100644 --- a/esp32c3/src/dma/in_pri_ch2.rs +++ b/esp32c3/src/dma/in_pri_ch2.rs @@ -34,22 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `RX_PRI_CH2` reader - The priority of Rx channel 2. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH2_R = crate::FieldReader; -#[doc = "Field `RX_PRI_CH2` writer - The priority of Rx channel 2. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH2_SPEC, u8, u8, 4, O>; +#[doc = "Field `RX_PRI` reader - The priority of Rx channel 2. The larger of the value, the higher of the priority."] +pub type RX_PRI_R = crate::FieldReader; +#[doc = "Field `RX_PRI` writer - The priority of Rx channel 2. The larger of the value, the higher of the priority."] +pub type RX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH2_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Rx channel 2. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch2(&self) -> RX_PRI_CH2_R { - RX_PRI_CH2_R::new((self.bits & 0x0f) as u8) + pub fn rx_pri(&self) -> RX_PRI_R { + RX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Rx channel 2. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch2(&mut self) -> RX_PRI_CH2_W<0> { - RX_PRI_CH2_W::new(self) + pub fn rx_pri(&mut self) -> RX_PRI_W<0> { + RX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/in_state_ch0.rs b/esp32c3/src/dma/in_state_ch0.rs index 939a0c6ed1..8c3c533008 100644 --- a/esp32c3/src/dma/in_state_ch0.rs +++ b/esp32c3/src/dma/in_state_ch0.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_ADDR_CH0` reader - This register stores the current inlink descriptor's address."] -pub type INLINK_DSCR_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `IN_DSCR_STATE_CH0` reader - reserved"] -pub type IN_DSCR_STATE_CH0_R = crate::FieldReader; -#[doc = "Field `IN_STATE_CH0` reader - reserved"] -pub type IN_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - reserved"] +pub type IN_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] #[inline(always)] - pub fn inlink_dscr_addr_ch0(&self) -> INLINK_DSCR_ADDR_CH0_R { - INLINK_DSCR_ADDR_CH0_R::new((self.bits & 0x0003_ffff) as u32) + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn in_dscr_state_ch0(&self) -> IN_DSCR_STATE_CH0_R { - IN_DSCR_STATE_CH0_R::new(((self.bits >> 18) & 3) as u8) + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn in_state_ch0(&self) -> IN_STATE_CH0_R { - IN_STATE_CH0_R::new(((self.bits >> 20) & 7) as u8) + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_IN_STATE_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_state_ch0](index.html) module"] diff --git a/esp32c3/src/dma/in_state_ch1.rs b/esp32c3/src/dma/in_state_ch1.rs index a8806da746..2557724289 100644 --- a/esp32c3/src/dma/in_state_ch1.rs +++ b/esp32c3/src/dma/in_state_ch1.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_ADDR_CH1` reader - This register stores the current inlink descriptor's address."] -pub type INLINK_DSCR_ADDR_CH1_R = crate::FieldReader; -#[doc = "Field `IN_DSCR_STATE_CH1` reader - reserved"] -pub type IN_DSCR_STATE_CH1_R = crate::FieldReader; -#[doc = "Field `IN_STATE_CH1` reader - reserved"] -pub type IN_STATE_CH1_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - reserved"] +pub type IN_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] #[inline(always)] - pub fn inlink_dscr_addr_ch1(&self) -> INLINK_DSCR_ADDR_CH1_R { - INLINK_DSCR_ADDR_CH1_R::new((self.bits & 0x0003_ffff) as u32) + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn in_dscr_state_ch1(&self) -> IN_DSCR_STATE_CH1_R { - IN_DSCR_STATE_CH1_R::new(((self.bits >> 18) & 3) as u8) + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn in_state_ch1(&self) -> IN_STATE_CH1_R { - IN_STATE_CH1_R::new(((self.bits >> 20) & 7) as u8) + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_IN_STATE_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_state_ch1](index.html) module"] diff --git a/esp32c3/src/dma/in_state_ch2.rs b/esp32c3/src/dma/in_state_ch2.rs index 26fea9e3f9..0eac2fc93d 100644 --- a/esp32c3/src/dma/in_state_ch2.rs +++ b/esp32c3/src/dma/in_state_ch2.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_ADDR_CH2` reader - This register stores the current inlink descriptor's address."] -pub type INLINK_DSCR_ADDR_CH2_R = crate::FieldReader; -#[doc = "Field `IN_DSCR_STATE_CH2` reader - reserved"] -pub type IN_DSCR_STATE_CH2_R = crate::FieldReader; -#[doc = "Field `IN_STATE_CH2` reader - reserved"] -pub type IN_STATE_CH2_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - reserved"] +pub type IN_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] #[inline(always)] - pub fn inlink_dscr_addr_ch2(&self) -> INLINK_DSCR_ADDR_CH2_R { - INLINK_DSCR_ADDR_CH2_R::new((self.bits & 0x0003_ffff) as u32) + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn in_dscr_state_ch2(&self) -> IN_DSCR_STATE_CH2_R { - IN_DSCR_STATE_CH2_R::new(((self.bits >> 18) & 3) as u8) + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn in_state_ch2(&self) -> IN_STATE_CH2_R { - IN_STATE_CH2_R::new(((self.bits >> 20) & 7) as u8) + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_IN_STATE_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_state_ch2](index.html) module"] diff --git a/esp32c3/src/dma/in_suc_eof_des_addr_ch0.rs b/esp32c3/src/dma/in_suc_eof_des_addr_ch0.rs index ef3b4236e0..085ce1cdd5 100644 --- a/esp32c3/src/dma/in_suc_eof_des_addr_ch0.rs +++ b/esp32c3/src/dma/in_suc_eof_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] -pub type IN_SUC_EOF_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn in_suc_eof_des_addr_ch0(&self) -> IN_SUC_EOF_DES_ADDR_CH0_R { - IN_SUC_EOF_DES_ADDR_CH0_R::new(self.bits) + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_suc_eof_des_addr_ch0](index.html) module"] diff --git a/esp32c3/src/dma/in_suc_eof_des_addr_ch1.rs b/esp32c3/src/dma/in_suc_eof_des_addr_ch1.rs index 4a1bc7e4c0..2ccbb287c6 100644 --- a/esp32c3/src/dma/in_suc_eof_des_addr_ch1.rs +++ b/esp32c3/src/dma/in_suc_eof_des_addr_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH1` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] -pub type IN_SUC_EOF_DES_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn in_suc_eof_des_addr_ch1(&self) -> IN_SUC_EOF_DES_ADDR_CH1_R { - IN_SUC_EOF_DES_ADDR_CH1_R::new(self.bits) + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_suc_eof_des_addr_ch1](index.html) module"] diff --git a/esp32c3/src/dma/in_suc_eof_des_addr_ch2.rs b/esp32c3/src/dma/in_suc_eof_des_addr_ch2.rs index 8ff6c0b907..9612187c6b 100644 --- a/esp32c3/src/dma/in_suc_eof_des_addr_ch2.rs +++ b/esp32c3/src/dma/in_suc_eof_des_addr_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH2` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] -pub type IN_SUC_EOF_DES_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn in_suc_eof_des_addr_ch2(&self) -> IN_SUC_EOF_DES_ADDR_CH2_R { - IN_SUC_EOF_DES_ADDR_CH2_R::new(self.bits) + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_suc_eof_des_addr_ch2](index.html) module"] diff --git a/esp32c3/src/dma/infifo_status_ch0.rs b/esp32c3/src/dma/infifo_status_ch0.rs index 55394874ab..15fd809309 100644 --- a/esp32c3/src/dma/infifo_status_ch0.rs +++ b/esp32c3/src/dma/infifo_status_ch0.rs @@ -13,62 +13,62 @@ impl From> for R { R(reader) } } -#[doc = "Field `INFIFO_FULL_CH0` reader - L1 Rx FIFO full signal for Rx channel 0."] -pub type INFIFO_FULL_CH0_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_CH0` reader - L1 Rx FIFO empty signal for Rx channel 0."] -pub type INFIFO_EMPTY_CH0_R = crate::BitReader; -#[doc = "Field `INFIFO_CNT_CH0` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] -pub type INFIFO_CNT_CH0_R = crate::FieldReader; -#[doc = "Field `IN_REMAIN_UNDER_1B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_1B_CH0_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_2B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_2B_CH0_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_3B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_3B_CH0_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_4B_CH0` reader - reserved"] -pub type IN_REMAIN_UNDER_4B_CH0_R = crate::BitReader; -#[doc = "Field `IN_BUF_HUNGRY_CH0` reader - reserved"] -pub type IN_BUF_HUNGRY_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL` reader - L1 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_FULL_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY` reader - L1 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] +pub type INFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `IN_REMAIN_UNDER_1B` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY` reader - reserved"] +pub type IN_BUF_HUNGRY_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 0."] #[inline(always)] - pub fn infifo_full_ch0(&self) -> INFIFO_FULL_CH0_R { - INFIFO_FULL_CH0_R::new((self.bits & 1) != 0) + pub fn infifo_full(&self) -> INFIFO_FULL_R { + INFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 0."] #[inline(always)] - pub fn infifo_empty_ch0(&self) -> INFIFO_EMPTY_CH0_R { - INFIFO_EMPTY_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn infifo_empty(&self) -> INFIFO_EMPTY_R { + INFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] #[inline(always)] - pub fn infifo_cnt_ch0(&self) -> INFIFO_CNT_CH0_R { - INFIFO_CNT_CH0_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn infifo_cnt(&self) -> INFIFO_CNT_R { + INFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn in_remain_under_1b_ch0(&self) -> IN_REMAIN_UNDER_1B_CH0_R { - IN_REMAIN_UNDER_1B_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn in_remain_under_1b(&self) -> IN_REMAIN_UNDER_1B_R { + IN_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn in_remain_under_2b_ch0(&self) -> IN_REMAIN_UNDER_2B_CH0_R { - IN_REMAIN_UNDER_2B_CH0_R::new(((self.bits >> 24) & 1) != 0) + pub fn in_remain_under_2b(&self) -> IN_REMAIN_UNDER_2B_R { + IN_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn in_remain_under_3b_ch0(&self) -> IN_REMAIN_UNDER_3B_CH0_R { - IN_REMAIN_UNDER_3B_CH0_R::new(((self.bits >> 25) & 1) != 0) + pub fn in_remain_under_3b(&self) -> IN_REMAIN_UNDER_3B_R { + IN_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn in_remain_under_4b_ch0(&self) -> IN_REMAIN_UNDER_4B_CH0_R { - IN_REMAIN_UNDER_4B_CH0_R::new(((self.bits >> 26) & 1) != 0) + pub fn in_remain_under_4b(&self) -> IN_REMAIN_UNDER_4B_R { + IN_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - reserved"] #[inline(always)] - pub fn in_buf_hungry_ch0(&self) -> IN_BUF_HUNGRY_CH0_R { - IN_BUF_HUNGRY_CH0_R::new(((self.bits >> 27) & 1) != 0) + pub fn in_buf_hungry(&self) -> IN_BUF_HUNGRY_R { + IN_BUF_HUNGRY_R::new(((self.bits >> 27) & 1) != 0) } } #[doc = "DMA_INFIFO_STATUS_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [infifo_status_ch0](index.html) module"] diff --git a/esp32c3/src/dma/infifo_status_ch1.rs b/esp32c3/src/dma/infifo_status_ch1.rs index 98ca7a1e3f..cf75070585 100644 --- a/esp32c3/src/dma/infifo_status_ch1.rs +++ b/esp32c3/src/dma/infifo_status_ch1.rs @@ -13,62 +13,62 @@ impl From> for R { R(reader) } } -#[doc = "Field `INFIFO_FULL_CH1` reader - L1 Rx FIFO full signal for Rx channel 1."] -pub type INFIFO_FULL_CH1_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_CH1` reader - L1 Rx FIFO empty signal for Rx channel 1."] -pub type INFIFO_EMPTY_CH1_R = crate::BitReader; -#[doc = "Field `INFIFO_CNT_CH1` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1."] -pub type INFIFO_CNT_CH1_R = crate::FieldReader; -#[doc = "Field `IN_REMAIN_UNDER_1B_CH1` reader - reserved"] -pub type IN_REMAIN_UNDER_1B_CH1_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_2B_CH1` reader - reserved"] -pub type IN_REMAIN_UNDER_2B_CH1_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_3B_CH1` reader - reserved"] -pub type IN_REMAIN_UNDER_3B_CH1_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_4B_CH1` reader - reserved"] -pub type IN_REMAIN_UNDER_4B_CH1_R = crate::BitReader; -#[doc = "Field `IN_BUF_HUNGRY_CH1` reader - reserved"] -pub type IN_BUF_HUNGRY_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL` reader - L1 Rx FIFO full signal for Rx channel 1."] +pub type INFIFO_FULL_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY` reader - L1 Rx FIFO empty signal for Rx channel 1."] +pub type INFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1."] +pub type INFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `IN_REMAIN_UNDER_1B` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY` reader - reserved"] +pub type IN_BUF_HUNGRY_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 1."] #[inline(always)] - pub fn infifo_full_ch1(&self) -> INFIFO_FULL_CH1_R { - INFIFO_FULL_CH1_R::new((self.bits & 1) != 0) + pub fn infifo_full(&self) -> INFIFO_FULL_R { + INFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 1."] #[inline(always)] - pub fn infifo_empty_ch1(&self) -> INFIFO_EMPTY_CH1_R { - INFIFO_EMPTY_CH1_R::new(((self.bits >> 1) & 1) != 0) + pub fn infifo_empty(&self) -> INFIFO_EMPTY_R { + INFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1."] #[inline(always)] - pub fn infifo_cnt_ch1(&self) -> INFIFO_CNT_CH1_R { - INFIFO_CNT_CH1_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn infifo_cnt(&self) -> INFIFO_CNT_R { + INFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn in_remain_under_1b_ch1(&self) -> IN_REMAIN_UNDER_1B_CH1_R { - IN_REMAIN_UNDER_1B_CH1_R::new(((self.bits >> 23) & 1) != 0) + pub fn in_remain_under_1b(&self) -> IN_REMAIN_UNDER_1B_R { + IN_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn in_remain_under_2b_ch1(&self) -> IN_REMAIN_UNDER_2B_CH1_R { - IN_REMAIN_UNDER_2B_CH1_R::new(((self.bits >> 24) & 1) != 0) + pub fn in_remain_under_2b(&self) -> IN_REMAIN_UNDER_2B_R { + IN_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn in_remain_under_3b_ch1(&self) -> IN_REMAIN_UNDER_3B_CH1_R { - IN_REMAIN_UNDER_3B_CH1_R::new(((self.bits >> 25) & 1) != 0) + pub fn in_remain_under_3b(&self) -> IN_REMAIN_UNDER_3B_R { + IN_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn in_remain_under_4b_ch1(&self) -> IN_REMAIN_UNDER_4B_CH1_R { - IN_REMAIN_UNDER_4B_CH1_R::new(((self.bits >> 26) & 1) != 0) + pub fn in_remain_under_4b(&self) -> IN_REMAIN_UNDER_4B_R { + IN_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - reserved"] #[inline(always)] - pub fn in_buf_hungry_ch1(&self) -> IN_BUF_HUNGRY_CH1_R { - IN_BUF_HUNGRY_CH1_R::new(((self.bits >> 27) & 1) != 0) + pub fn in_buf_hungry(&self) -> IN_BUF_HUNGRY_R { + IN_BUF_HUNGRY_R::new(((self.bits >> 27) & 1) != 0) } } #[doc = "DMA_INFIFO_STATUS_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [infifo_status_ch1](index.html) module"] diff --git a/esp32c3/src/dma/infifo_status_ch2.rs b/esp32c3/src/dma/infifo_status_ch2.rs index 5a830c0171..9d9c59a4b3 100644 --- a/esp32c3/src/dma/infifo_status_ch2.rs +++ b/esp32c3/src/dma/infifo_status_ch2.rs @@ -13,62 +13,62 @@ impl From> for R { R(reader) } } -#[doc = "Field `INFIFO_FULL_CH2` reader - L1 Rx FIFO full signal for Rx channel 2."] -pub type INFIFO_FULL_CH2_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_CH2` reader - L1 Rx FIFO empty signal for Rx channel 2."] -pub type INFIFO_EMPTY_CH2_R = crate::BitReader; -#[doc = "Field `INFIFO_CNT_CH2` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2."] -pub type INFIFO_CNT_CH2_R = crate::FieldReader; -#[doc = "Field `IN_REMAIN_UNDER_1B_CH2` reader - reserved"] -pub type IN_REMAIN_UNDER_1B_CH2_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_2B_CH2` reader - reserved"] -pub type IN_REMAIN_UNDER_2B_CH2_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_3B_CH2` reader - reserved"] -pub type IN_REMAIN_UNDER_3B_CH2_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_4B_CH2` reader - reserved"] -pub type IN_REMAIN_UNDER_4B_CH2_R = crate::BitReader; -#[doc = "Field `IN_BUF_HUNGRY_CH2` reader - reserved"] -pub type IN_BUF_HUNGRY_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL` reader - L1 Rx FIFO full signal for Rx channel 2."] +pub type INFIFO_FULL_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY` reader - L1 Rx FIFO empty signal for Rx channel 2."] +pub type INFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2."] +pub type INFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `IN_REMAIN_UNDER_1B` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY` reader - reserved"] +pub type IN_BUF_HUNGRY_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 2."] #[inline(always)] - pub fn infifo_full_ch2(&self) -> INFIFO_FULL_CH2_R { - INFIFO_FULL_CH2_R::new((self.bits & 1) != 0) + pub fn infifo_full(&self) -> INFIFO_FULL_R { + INFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 2."] #[inline(always)] - pub fn infifo_empty_ch2(&self) -> INFIFO_EMPTY_CH2_R { - INFIFO_EMPTY_CH2_R::new(((self.bits >> 1) & 1) != 0) + pub fn infifo_empty(&self) -> INFIFO_EMPTY_R { + INFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2."] #[inline(always)] - pub fn infifo_cnt_ch2(&self) -> INFIFO_CNT_CH2_R { - INFIFO_CNT_CH2_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn infifo_cnt(&self) -> INFIFO_CNT_R { + INFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn in_remain_under_1b_ch2(&self) -> IN_REMAIN_UNDER_1B_CH2_R { - IN_REMAIN_UNDER_1B_CH2_R::new(((self.bits >> 23) & 1) != 0) + pub fn in_remain_under_1b(&self) -> IN_REMAIN_UNDER_1B_R { + IN_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn in_remain_under_2b_ch2(&self) -> IN_REMAIN_UNDER_2B_CH2_R { - IN_REMAIN_UNDER_2B_CH2_R::new(((self.bits >> 24) & 1) != 0) + pub fn in_remain_under_2b(&self) -> IN_REMAIN_UNDER_2B_R { + IN_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn in_remain_under_3b_ch2(&self) -> IN_REMAIN_UNDER_3B_CH2_R { - IN_REMAIN_UNDER_3B_CH2_R::new(((self.bits >> 25) & 1) != 0) + pub fn in_remain_under_3b(&self) -> IN_REMAIN_UNDER_3B_R { + IN_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn in_remain_under_4b_ch2(&self) -> IN_REMAIN_UNDER_4B_CH2_R { - IN_REMAIN_UNDER_4B_CH2_R::new(((self.bits >> 26) & 1) != 0) + pub fn in_remain_under_4b(&self) -> IN_REMAIN_UNDER_4B_R { + IN_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - reserved"] #[inline(always)] - pub fn in_buf_hungry_ch2(&self) -> IN_BUF_HUNGRY_CH2_R { - IN_BUF_HUNGRY_CH2_R::new(((self.bits >> 27) & 1) != 0) + pub fn in_buf_hungry(&self) -> IN_BUF_HUNGRY_R { + IN_BUF_HUNGRY_R::new(((self.bits >> 27) & 1) != 0) } } #[doc = "DMA_INFIFO_STATUS_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [infifo_status_ch2](index.html) module"] diff --git a/esp32c3/src/dma/int_clr_ch0.rs b/esp32c3/src/dma/int_clr_ch0.rs index 8ebe2e6e31..f4fdd0ea07 100644 --- a/esp32c3/src/dma/int_clr_ch0.rs +++ b/esp32c3/src/dma/int_clr_ch0.rs @@ -19,110 +19,97 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH0_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH0_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH0_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH0_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH0_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH0_SPEC, bool, O>; impl W { #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_clr(&mut self) -> IN_DONE_CH0_INT_CLR_W<0> { - IN_DONE_CH0_INT_CLR_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_clr(&mut self) -> IN_SUC_EOF_CH0_INT_CLR_W<1> { - IN_SUC_EOF_CH0_INT_CLR_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_clr(&mut self) -> IN_ERR_EOF_CH0_INT_CLR_W<2> { - IN_ERR_EOF_CH0_INT_CLR_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_clr(&mut self) -> OUT_DONE_CH0_INT_CLR_W<3> { - OUT_DONE_CH0_INT_CLR_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_clr(&mut self) -> OUT_EOF_CH0_INT_CLR_W<4> { - OUT_EOF_CH0_INT_CLR_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_clr(&mut self) -> IN_DSCR_ERR_CH0_INT_CLR_W<5> { - IN_DSCR_ERR_CH0_INT_CLR_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_clr(&mut self) -> OUT_DSCR_ERR_CH0_INT_CLR_W<6> { - OUT_DSCR_ERR_CH0_INT_CLR_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_clr(&mut self) -> IN_DSCR_EMPTY_CH0_INT_CLR_W<7> { - IN_DSCR_EMPTY_CH0_INT_CLR_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_clr(&mut self) -> OUT_TOTAL_EOF_CH0_INT_CLR_W<8> { - OUT_TOTAL_EOF_CH0_INT_CLR_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_clr(&mut self) -> INFIFO_OVF_CH0_INT_CLR_W<9> { - INFIFO_OVF_CH0_INT_CLR_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_clr(&mut self) -> INFIFO_UDF_CH0_INT_CLR_W<10> { - INFIFO_UDF_CH0_INT_CLR_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_clr(&mut self) -> OUTFIFO_OVF_CH0_INT_CLR_W<11> { - OUTFIFO_OVF_CH0_INT_CLR_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_clr(&mut self) -> OUTFIFO_UDF_CH0_INT_CLR_W<12> { - OUTFIFO_UDF_CH0_INT_CLR_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/int_clr_ch1.rs b/esp32c3/src/dma/int_clr_ch1.rs index bee3895e63..f7b71be62a 100644 --- a/esp32c3/src/dma/int_clr_ch1.rs +++ b/esp32c3/src/dma/int_clr_ch1.rs @@ -19,110 +19,97 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH1_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH1_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH1_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH1_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH1_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH1_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH1_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH1_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH1_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH1_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH1_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH1_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH1_SPEC, bool, O>; impl W { #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch1_int_clr(&mut self) -> IN_DONE_CH1_INT_CLR_W<0> { - IN_DONE_CH1_INT_CLR_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch1_int_clr(&mut self) -> IN_SUC_EOF_CH1_INT_CLR_W<1> { - IN_SUC_EOF_CH1_INT_CLR_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch1_int_clr(&mut self) -> IN_ERR_EOF_CH1_INT_CLR_W<2> { - IN_ERR_EOF_CH1_INT_CLR_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch1_int_clr(&mut self) -> OUT_DONE_CH1_INT_CLR_W<3> { - OUT_DONE_CH1_INT_CLR_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch1_int_clr(&mut self) -> OUT_EOF_CH1_INT_CLR_W<4> { - OUT_EOF_CH1_INT_CLR_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch1_int_clr(&mut self) -> IN_DSCR_ERR_CH1_INT_CLR_W<5> { - IN_DSCR_ERR_CH1_INT_CLR_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch1_int_clr(&mut self) -> OUT_DSCR_ERR_CH1_INT_CLR_W<6> { - OUT_DSCR_ERR_CH1_INT_CLR_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch1_int_clr(&mut self) -> IN_DSCR_EMPTY_CH1_INT_CLR_W<7> { - IN_DSCR_EMPTY_CH1_INT_CLR_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch1_int_clr(&mut self) -> OUT_TOTAL_EOF_CH1_INT_CLR_W<8> { - OUT_TOTAL_EOF_CH1_INT_CLR_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch1_int_clr(&mut self) -> INFIFO_OVF_CH1_INT_CLR_W<9> { - INFIFO_OVF_CH1_INT_CLR_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch1_int_clr(&mut self) -> INFIFO_UDF_CH1_INT_CLR_W<10> { - INFIFO_UDF_CH1_INT_CLR_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch1_int_clr(&mut self) -> OUTFIFO_OVF_CH1_INT_CLR_W<11> { - OUTFIFO_OVF_CH1_INT_CLR_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch1_int_clr(&mut self) -> OUTFIFO_UDF_CH1_INT_CLR_W<12> { - OUTFIFO_UDF_CH1_INT_CLR_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/int_clr_ch2.rs b/esp32c3/src/dma/int_clr_ch2.rs index 85503b3220..9c4a69c2bf 100644 --- a/esp32c3/src/dma/int_clr_ch2.rs +++ b/esp32c3/src/dma/int_clr_ch2.rs @@ -19,110 +19,97 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH2_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH2_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH2_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH2_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH2_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH2_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH2_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH2_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH2_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH2_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH2_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH2_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_CH2_SPEC, bool, O>; impl W { #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch2_int_clr(&mut self) -> IN_DONE_CH2_INT_CLR_W<0> { - IN_DONE_CH2_INT_CLR_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch2_int_clr(&mut self) -> IN_SUC_EOF_CH2_INT_CLR_W<1> { - IN_SUC_EOF_CH2_INT_CLR_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch2_int_clr(&mut self) -> IN_ERR_EOF_CH2_INT_CLR_W<2> { - IN_ERR_EOF_CH2_INT_CLR_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch2_int_clr(&mut self) -> OUT_DONE_CH2_INT_CLR_W<3> { - OUT_DONE_CH2_INT_CLR_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch2_int_clr(&mut self) -> OUT_EOF_CH2_INT_CLR_W<4> { - OUT_EOF_CH2_INT_CLR_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch2_int_clr(&mut self) -> IN_DSCR_ERR_CH2_INT_CLR_W<5> { - IN_DSCR_ERR_CH2_INT_CLR_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch2_int_clr(&mut self) -> OUT_DSCR_ERR_CH2_INT_CLR_W<6> { - OUT_DSCR_ERR_CH2_INT_CLR_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch2_int_clr(&mut self) -> IN_DSCR_EMPTY_CH2_INT_CLR_W<7> { - IN_DSCR_EMPTY_CH2_INT_CLR_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch2_int_clr(&mut self) -> OUT_TOTAL_EOF_CH2_INT_CLR_W<8> { - OUT_TOTAL_EOF_CH2_INT_CLR_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch2_int_clr(&mut self) -> INFIFO_OVF_CH2_INT_CLR_W<9> { - INFIFO_OVF_CH2_INT_CLR_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch2_int_clr(&mut self) -> INFIFO_UDF_CH2_INT_CLR_W<10> { - INFIFO_UDF_CH2_INT_CLR_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch2_int_clr(&mut self) -> OUTFIFO_OVF_CH2_INT_CLR_W<11> { - OUTFIFO_OVF_CH2_INT_CLR_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch2_int_clr(&mut self) -> OUTFIFO_UDF_CH2_INT_CLR_W<12> { - OUTFIFO_UDF_CH2_INT_CLR_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/int_ena_ch0.rs b/esp32c3/src/dma/int_ena_ch0.rs index a64fb12eb0..da49b3e694 100644 --- a/esp32c3/src/dma/int_ena_ch0.rs +++ b/esp32c3/src/dma/int_ena_ch0.rs @@ -34,203 +34,190 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DONE_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_ena(&self) -> IN_DONE_CH0_INT_ENA_R { - IN_DONE_CH0_INT_ENA_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_ena(&self) -> IN_SUC_EOF_CH0_INT_ENA_R { - IN_SUC_EOF_CH0_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_ena(&self) -> IN_ERR_EOF_CH0_INT_ENA_R { - IN_ERR_EOF_CH0_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_ena(&self) -> OUT_DONE_CH0_INT_ENA_R { - OUT_DONE_CH0_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_ena(&self) -> OUT_EOF_CH0_INT_ENA_R { - OUT_EOF_CH0_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_ena(&self) -> IN_DSCR_ERR_CH0_INT_ENA_R { - IN_DSCR_ERR_CH0_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_ena(&self) -> OUT_DSCR_ERR_CH0_INT_ENA_R { - OUT_DSCR_ERR_CH0_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_ena(&self) -> IN_DSCR_EMPTY_CH0_INT_ENA_R { - IN_DSCR_EMPTY_CH0_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_ena(&self) -> OUT_TOTAL_EOF_CH0_INT_ENA_R { - OUT_TOTAL_EOF_CH0_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_ena(&self) -> INFIFO_OVF_CH0_INT_ENA_R { - INFIFO_OVF_CH0_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_ena(&self) -> INFIFO_UDF_CH0_INT_ENA_R { - INFIFO_UDF_CH0_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_ena(&self) -> OUTFIFO_OVF_CH0_INT_ENA_R { - OUTFIFO_OVF_CH0_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_ena(&self) -> OUTFIFO_UDF_CH0_INT_ENA_R { - OUTFIFO_UDF_CH0_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_ena(&mut self) -> IN_DONE_CH0_INT_ENA_W<0> { - IN_DONE_CH0_INT_ENA_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_ena(&mut self) -> IN_SUC_EOF_CH0_INT_ENA_W<1> { - IN_SUC_EOF_CH0_INT_ENA_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_ena(&mut self) -> IN_ERR_EOF_CH0_INT_ENA_W<2> { - IN_ERR_EOF_CH0_INT_ENA_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_ena(&mut self) -> OUT_DONE_CH0_INT_ENA_W<3> { - OUT_DONE_CH0_INT_ENA_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_ena(&mut self) -> OUT_EOF_CH0_INT_ENA_W<4> { - OUT_EOF_CH0_INT_ENA_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_ena(&mut self) -> IN_DSCR_ERR_CH0_INT_ENA_W<5> { - IN_DSCR_ERR_CH0_INT_ENA_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_ena(&mut self) -> OUT_DSCR_ERR_CH0_INT_ENA_W<6> { - OUT_DSCR_ERR_CH0_INT_ENA_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_ena(&mut self) -> IN_DSCR_EMPTY_CH0_INT_ENA_W<7> { - IN_DSCR_EMPTY_CH0_INT_ENA_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_ena(&mut self) -> OUT_TOTAL_EOF_CH0_INT_ENA_W<8> { - OUT_TOTAL_EOF_CH0_INT_ENA_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_ena(&mut self) -> INFIFO_OVF_CH0_INT_ENA_W<9> { - INFIFO_OVF_CH0_INT_ENA_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_ena(&mut self) -> INFIFO_UDF_CH0_INT_ENA_W<10> { - INFIFO_UDF_CH0_INT_ENA_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_ena(&mut self) -> OUTFIFO_OVF_CH0_INT_ENA_W<11> { - OUTFIFO_OVF_CH0_INT_ENA_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_ena(&mut self) -> OUTFIFO_UDF_CH0_INT_ENA_W<12> { - OUTFIFO_UDF_CH0_INT_ENA_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/int_ena_ch1.rs b/esp32c3/src/dma/int_ena_ch1.rs index 9a3a331769..1afdeec32d 100644 --- a/esp32c3/src/dma/int_ena_ch1.rs +++ b/esp32c3/src/dma/int_ena_ch1.rs @@ -34,203 +34,190 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DONE_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH1_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH1_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH1_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH1_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH1_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH1_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH1_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH1_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH1_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH1_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH1_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch1_int_ena(&self) -> IN_DONE_CH1_INT_ENA_R { - IN_DONE_CH1_INT_ENA_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch1_int_ena(&self) -> IN_SUC_EOF_CH1_INT_ENA_R { - IN_SUC_EOF_CH1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch1_int_ena(&self) -> IN_ERR_EOF_CH1_INT_ENA_R { - IN_ERR_EOF_CH1_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch1_int_ena(&self) -> OUT_DONE_CH1_INT_ENA_R { - OUT_DONE_CH1_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch1_int_ena(&self) -> OUT_EOF_CH1_INT_ENA_R { - OUT_EOF_CH1_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch1_int_ena(&self) -> IN_DSCR_ERR_CH1_INT_ENA_R { - IN_DSCR_ERR_CH1_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch1_int_ena(&self) -> OUT_DSCR_ERR_CH1_INT_ENA_R { - OUT_DSCR_ERR_CH1_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch1_int_ena(&self) -> IN_DSCR_EMPTY_CH1_INT_ENA_R { - IN_DSCR_EMPTY_CH1_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch1_int_ena(&self) -> OUT_TOTAL_EOF_CH1_INT_ENA_R { - OUT_TOTAL_EOF_CH1_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch1_int_ena(&self) -> INFIFO_OVF_CH1_INT_ENA_R { - INFIFO_OVF_CH1_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch1_int_ena(&self) -> INFIFO_UDF_CH1_INT_ENA_R { - INFIFO_UDF_CH1_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch1_int_ena(&self) -> OUTFIFO_OVF_CH1_INT_ENA_R { - OUTFIFO_OVF_CH1_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch1_int_ena(&self) -> OUTFIFO_UDF_CH1_INT_ENA_R { - OUTFIFO_UDF_CH1_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch1_int_ena(&mut self) -> IN_DONE_CH1_INT_ENA_W<0> { - IN_DONE_CH1_INT_ENA_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch1_int_ena(&mut self) -> IN_SUC_EOF_CH1_INT_ENA_W<1> { - IN_SUC_EOF_CH1_INT_ENA_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch1_int_ena(&mut self) -> IN_ERR_EOF_CH1_INT_ENA_W<2> { - IN_ERR_EOF_CH1_INT_ENA_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch1_int_ena(&mut self) -> OUT_DONE_CH1_INT_ENA_W<3> { - OUT_DONE_CH1_INT_ENA_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch1_int_ena(&mut self) -> OUT_EOF_CH1_INT_ENA_W<4> { - OUT_EOF_CH1_INT_ENA_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch1_int_ena(&mut self) -> IN_DSCR_ERR_CH1_INT_ENA_W<5> { - IN_DSCR_ERR_CH1_INT_ENA_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch1_int_ena(&mut self) -> OUT_DSCR_ERR_CH1_INT_ENA_W<6> { - OUT_DSCR_ERR_CH1_INT_ENA_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch1_int_ena(&mut self) -> IN_DSCR_EMPTY_CH1_INT_ENA_W<7> { - IN_DSCR_EMPTY_CH1_INT_ENA_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch1_int_ena(&mut self) -> OUT_TOTAL_EOF_CH1_INT_ENA_W<8> { - OUT_TOTAL_EOF_CH1_INT_ENA_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch1_int_ena(&mut self) -> INFIFO_OVF_CH1_INT_ENA_W<9> { - INFIFO_OVF_CH1_INT_ENA_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch1_int_ena(&mut self) -> INFIFO_UDF_CH1_INT_ENA_W<10> { - INFIFO_UDF_CH1_INT_ENA_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch1_int_ena(&mut self) -> OUTFIFO_OVF_CH1_INT_ENA_W<11> { - OUTFIFO_OVF_CH1_INT_ENA_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch1_int_ena(&mut self) -> OUTFIFO_UDF_CH1_INT_ENA_W<12> { - OUTFIFO_UDF_CH1_INT_ENA_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/int_ena_ch2.rs b/esp32c3/src/dma/int_ena_ch2.rs index 20dbaff2cc..3aea4a31b1 100644 --- a/esp32c3/src/dma/int_ena_ch2.rs +++ b/esp32c3/src/dma/int_ena_ch2.rs @@ -34,203 +34,190 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DONE_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_DONE_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_CH2_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH2_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_CH2_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH2_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_CH2_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH2_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_CH2_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH2_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH2_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH2_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_UDF` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_ENA_CH2_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch2_int_ena(&self) -> IN_DONE_CH2_INT_ENA_R { - IN_DONE_CH2_INT_ENA_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch2_int_ena(&self) -> IN_SUC_EOF_CH2_INT_ENA_R { - IN_SUC_EOF_CH2_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch2_int_ena(&self) -> IN_ERR_EOF_CH2_INT_ENA_R { - IN_ERR_EOF_CH2_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch2_int_ena(&self) -> OUT_DONE_CH2_INT_ENA_R { - OUT_DONE_CH2_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch2_int_ena(&self) -> OUT_EOF_CH2_INT_ENA_R { - OUT_EOF_CH2_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch2_int_ena(&self) -> IN_DSCR_ERR_CH2_INT_ENA_R { - IN_DSCR_ERR_CH2_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch2_int_ena(&self) -> OUT_DSCR_ERR_CH2_INT_ENA_R { - OUT_DSCR_ERR_CH2_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch2_int_ena(&self) -> IN_DSCR_EMPTY_CH2_INT_ENA_R { - IN_DSCR_EMPTY_CH2_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch2_int_ena(&self) -> OUT_TOTAL_EOF_CH2_INT_ENA_R { - OUT_TOTAL_EOF_CH2_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch2_int_ena(&self) -> INFIFO_OVF_CH2_INT_ENA_R { - INFIFO_OVF_CH2_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch2_int_ena(&self) -> INFIFO_UDF_CH2_INT_ENA_R { - INFIFO_UDF_CH2_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch2_int_ena(&self) -> OUTFIFO_OVF_CH2_INT_ENA_R { - OUTFIFO_OVF_CH2_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch2_int_ena(&self) -> OUTFIFO_UDF_CH2_INT_ENA_R { - OUTFIFO_UDF_CH2_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch2_int_ena(&mut self) -> IN_DONE_CH2_INT_ENA_W<0> { - IN_DONE_CH2_INT_ENA_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch2_int_ena(&mut self) -> IN_SUC_EOF_CH2_INT_ENA_W<1> { - IN_SUC_EOF_CH2_INT_ENA_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch2_int_ena(&mut self) -> IN_ERR_EOF_CH2_INT_ENA_W<2> { - IN_ERR_EOF_CH2_INT_ENA_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch2_int_ena(&mut self) -> OUT_DONE_CH2_INT_ENA_W<3> { - OUT_DONE_CH2_INT_ENA_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<3> { + OUT_DONE_W::new(self) } #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch2_int_ena(&mut self) -> OUT_EOF_CH2_INT_ENA_W<4> { - OUT_EOF_CH2_INT_ENA_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<4> { + OUT_EOF_W::new(self) } #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch2_int_ena(&mut self) -> IN_DSCR_ERR_CH2_INT_ENA_W<5> { - IN_DSCR_ERR_CH2_INT_ENA_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<5> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch2_int_ena(&mut self) -> OUT_DSCR_ERR_CH2_INT_ENA_W<6> { - OUT_DSCR_ERR_CH2_INT_ENA_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<6> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch2_int_ena(&mut self) -> IN_DSCR_EMPTY_CH2_INT_ENA_W<7> { - IN_DSCR_EMPTY_CH2_INT_ENA_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<7> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch2_int_ena(&mut self) -> OUT_TOTAL_EOF_CH2_INT_ENA_W<8> { - OUT_TOTAL_EOF_CH2_INT_ENA_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<8> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch2_int_ena(&mut self) -> INFIFO_OVF_CH2_INT_ENA_W<9> { - INFIFO_OVF_CH2_INT_ENA_W::new(self) + pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<9> { + INFIFO_OVF_W::new(self) } #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch2_int_ena(&mut self) -> INFIFO_UDF_CH2_INT_ENA_W<10> { - INFIFO_UDF_CH2_INT_ENA_W::new(self) + pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<10> { + INFIFO_UDF_W::new(self) } #[doc = "Bit 11 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch2_int_ena(&mut self) -> OUTFIFO_OVF_CH2_INT_ENA_W<11> { - OUTFIFO_OVF_CH2_INT_ENA_W::new(self) + pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<11> { + OUTFIFO_OVF_W::new(self) } #[doc = "Bit 12 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch2_int_ena(&mut self) -> OUTFIFO_UDF_CH2_INT_ENA_W<12> { - OUTFIFO_UDF_CH2_INT_ENA_W::new(self) + pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<12> { + OUTFIFO_UDF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/int_raw_ch0.rs b/esp32c3/src/dma/int_raw_ch0.rs index dfe856e5f6..0566103b95 100644 --- a/esp32c3/src/dma/int_raw_ch0.rs +++ b/esp32c3/src/dma/int_raw_ch0.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] -pub type IN_DONE_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] -pub type IN_SUC_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] -pub type IN_ERR_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] -pub type OUT_DONE_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] -pub type OUT_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] -pub type IN_DSCR_ERR_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] -pub type OUT_DSCR_ERR_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] -pub type IN_DSCR_EMPTY_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] -pub type OUT_TOTAL_EOF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] -pub type INFIFO_OVF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] -pub type INFIFO_UDF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] -pub type OUTFIFO_OVF_CH0_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] -pub type OUTFIFO_UDF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] #[inline(always)] - pub fn in_done_ch0_int_raw(&self) -> IN_DONE_CH0_INT_RAW_R { - IN_DONE_CH0_INT_RAW_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] #[inline(always)] - pub fn in_suc_eof_ch0_int_raw(&self) -> IN_SUC_EOF_CH0_INT_RAW_R { - IN_SUC_EOF_CH0_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] #[inline(always)] - pub fn in_err_eof_ch0_int_raw(&self) -> IN_ERR_EOF_CH0_INT_RAW_R { - IN_ERR_EOF_CH0_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] #[inline(always)] - pub fn out_done_ch0_int_raw(&self) -> OUT_DONE_CH0_INT_RAW_R { - OUT_DONE_CH0_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] #[inline(always)] - pub fn out_eof_ch0_int_raw(&self) -> OUT_EOF_CH0_INT_RAW_R { - OUT_EOF_CH0_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] #[inline(always)] - pub fn in_dscr_err_ch0_int_raw(&self) -> IN_DSCR_ERR_CH0_INT_RAW_R { - IN_DSCR_ERR_CH0_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] #[inline(always)] - pub fn out_dscr_err_ch0_int_raw(&self) -> OUT_DSCR_ERR_CH0_INT_RAW_R { - OUT_DSCR_ERR_CH0_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_raw(&self) -> IN_DSCR_EMPTY_CH0_INT_RAW_R { - IN_DSCR_EMPTY_CH0_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] #[inline(always)] - pub fn out_total_eof_ch0_int_raw(&self) -> OUT_TOTAL_EOF_CH0_INT_RAW_R { - OUT_TOTAL_EOF_CH0_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] #[inline(always)] - pub fn infifo_ovf_ch0_int_raw(&self) -> INFIFO_OVF_CH0_INT_RAW_R { - INFIFO_OVF_CH0_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] #[inline(always)] - pub fn infifo_udf_ch0_int_raw(&self) -> INFIFO_UDF_CH0_INT_RAW_R { - INFIFO_UDF_CH0_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_raw(&self) -> OUTFIFO_OVF_CH0_INT_RAW_R { - OUTFIFO_OVF_CH0_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] #[inline(always)] - pub fn outfifo_udf_ch0_int_raw(&self) -> OUTFIFO_UDF_CH0_INT_RAW_R { - OUTFIFO_UDF_CH0_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_RAW_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_raw_ch0](index.html) module"] diff --git a/esp32c3/src/dma/int_raw_ch1.rs b/esp32c3/src/dma/int_raw_ch1.rs index 739adf598f..eb1754cf13 100644 --- a/esp32c3/src/dma/int_raw_ch1.rs +++ b/esp32c3/src/dma/int_raw_ch1.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1."] -pub type IN_DONE_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] -pub type IN_SUC_EOF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved."] -pub type IN_ERR_EOF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1."] -pub type OUT_DONE_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1."] -pub type OUT_EOF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] -pub type IN_DSCR_ERR_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1."] -pub type OUT_DSCR_ERR_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1."] -pub type IN_DSCR_EMPTY_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1."] -pub type OUT_TOTAL_EOF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow."] -pub type INFIFO_OVF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow."] -pub type INFIFO_UDF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow."] -pub type OUTFIFO_OVF_CH1_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow."] -pub type OUTFIFO_UDF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1."] #[inline(always)] - pub fn in_done_ch1_int_raw(&self) -> IN_DONE_CH1_INT_RAW_R { - IN_DONE_CH1_INT_RAW_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] #[inline(always)] - pub fn in_suc_eof_ch1_int_raw(&self) -> IN_SUC_EOF_CH1_INT_RAW_R { - IN_SUC_EOF_CH1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved."] #[inline(always)] - pub fn in_err_eof_ch1_int_raw(&self) -> IN_ERR_EOF_CH1_INT_RAW_R { - IN_ERR_EOF_CH1_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1."] #[inline(always)] - pub fn out_done_ch1_int_raw(&self) -> OUT_DONE_CH1_INT_RAW_R { - OUT_DONE_CH1_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1."] #[inline(always)] - pub fn out_eof_ch1_int_raw(&self) -> OUT_EOF_CH1_INT_RAW_R { - OUT_EOF_CH1_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] #[inline(always)] - pub fn in_dscr_err_ch1_int_raw(&self) -> IN_DSCR_ERR_CH1_INT_RAW_R { - IN_DSCR_ERR_CH1_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1."] #[inline(always)] - pub fn out_dscr_err_ch1_int_raw(&self) -> OUT_DSCR_ERR_CH1_INT_RAW_R { - OUT_DSCR_ERR_CH1_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1."] #[inline(always)] - pub fn in_dscr_empty_ch1_int_raw(&self) -> IN_DSCR_EMPTY_CH1_INT_RAW_R { - IN_DSCR_EMPTY_CH1_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1."] #[inline(always)] - pub fn out_total_eof_ch1_int_raw(&self) -> OUT_TOTAL_EOF_CH1_INT_RAW_R { - OUT_TOTAL_EOF_CH1_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow."] #[inline(always)] - pub fn infifo_ovf_ch1_int_raw(&self) -> INFIFO_OVF_CH1_INT_RAW_R { - INFIFO_OVF_CH1_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow."] #[inline(always)] - pub fn infifo_udf_ch1_int_raw(&self) -> INFIFO_UDF_CH1_INT_RAW_R { - INFIFO_UDF_CH1_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow."] #[inline(always)] - pub fn outfifo_ovf_ch1_int_raw(&self) -> OUTFIFO_OVF_CH1_INT_RAW_R { - OUTFIFO_OVF_CH1_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow."] #[inline(always)] - pub fn outfifo_udf_ch1_int_raw(&self) -> OUTFIFO_UDF_CH1_INT_RAW_R { - OUTFIFO_UDF_CH1_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_RAW_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_raw_ch1](index.html) module"] diff --git a/esp32c3/src/dma/int_raw_ch2.rs b/esp32c3/src/dma/int_raw_ch2.rs index cc0a711e92..612e501c1d 100644 --- a/esp32c3/src/dma/int_raw_ch2.rs +++ b/esp32c3/src/dma/int_raw_ch2.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2."] -pub type IN_DONE_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2."] -pub type IN_SUC_EOF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved."] -pub type IN_ERR_EOF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2."] -pub type OUT_DONE_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2."] -pub type OUT_EOF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2."] -pub type IN_DSCR_ERR_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2."] -pub type OUT_DSCR_ERR_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2."] -pub type IN_DSCR_EMPTY_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2."] -pub type OUT_TOTAL_EOF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow."] -pub type INFIFO_OVF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow."] -pub type INFIFO_UDF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow."] -pub type OUTFIFO_OVF_CH2_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow."] -pub type OUTFIFO_UDF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2."] #[inline(always)] - pub fn in_done_ch2_int_raw(&self) -> IN_DONE_CH2_INT_RAW_R { - IN_DONE_CH2_INT_RAW_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2."] #[inline(always)] - pub fn in_suc_eof_ch2_int_raw(&self) -> IN_SUC_EOF_CH2_INT_RAW_R { - IN_SUC_EOF_CH2_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved."] #[inline(always)] - pub fn in_err_eof_ch2_int_raw(&self) -> IN_ERR_EOF_CH2_INT_RAW_R { - IN_ERR_EOF_CH2_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2."] #[inline(always)] - pub fn out_done_ch2_int_raw(&self) -> OUT_DONE_CH2_INT_RAW_R { - OUT_DONE_CH2_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2."] #[inline(always)] - pub fn out_eof_ch2_int_raw(&self) -> OUT_EOF_CH2_INT_RAW_R { - OUT_EOF_CH2_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2."] #[inline(always)] - pub fn in_dscr_err_ch2_int_raw(&self) -> IN_DSCR_ERR_CH2_INT_RAW_R { - IN_DSCR_ERR_CH2_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2."] #[inline(always)] - pub fn out_dscr_err_ch2_int_raw(&self) -> OUT_DSCR_ERR_CH2_INT_RAW_R { - OUT_DSCR_ERR_CH2_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2."] #[inline(always)] - pub fn in_dscr_empty_ch2_int_raw(&self) -> IN_DSCR_EMPTY_CH2_INT_RAW_R { - IN_DSCR_EMPTY_CH2_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2."] #[inline(always)] - pub fn out_total_eof_ch2_int_raw(&self) -> OUT_TOTAL_EOF_CH2_INT_RAW_R { - OUT_TOTAL_EOF_CH2_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow."] #[inline(always)] - pub fn infifo_ovf_ch2_int_raw(&self) -> INFIFO_OVF_CH2_INT_RAW_R { - INFIFO_OVF_CH2_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow."] #[inline(always)] - pub fn infifo_udf_ch2_int_raw(&self) -> INFIFO_UDF_CH2_INT_RAW_R { - INFIFO_UDF_CH2_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow."] #[inline(always)] - pub fn outfifo_ovf_ch2_int_raw(&self) -> OUTFIFO_OVF_CH2_INT_RAW_R { - OUTFIFO_OVF_CH2_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow."] #[inline(always)] - pub fn outfifo_udf_ch2_int_raw(&self) -> OUTFIFO_UDF_CH2_INT_RAW_R { - OUTFIFO_UDF_CH2_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_RAW_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_raw_ch2](index.html) module"] diff --git a/esp32c3/src/dma/int_st_ch0.rs b/esp32c3/src/dma/int_st_ch0.rs index e5291f100b..6f85717045 100644 --- a/esp32c3/src/dma/int_st_ch0.rs +++ b/esp32c3/src/dma/int_st_ch0.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH0_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch0_int_st(&self) -> IN_DONE_CH0_INT_ST_R { - IN_DONE_CH0_INT_ST_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch0_int_st(&self) -> IN_SUC_EOF_CH0_INT_ST_R { - IN_SUC_EOF_CH0_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch0_int_st(&self) -> IN_ERR_EOF_CH0_INT_ST_R { - IN_ERR_EOF_CH0_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch0_int_st(&self) -> OUT_DONE_CH0_INT_ST_R { - OUT_DONE_CH0_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch0_int_st(&self) -> OUT_EOF_CH0_INT_ST_R { - OUT_EOF_CH0_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch0_int_st(&self) -> IN_DSCR_ERR_CH0_INT_ST_R { - IN_DSCR_ERR_CH0_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch0_int_st(&self) -> OUT_DSCR_ERR_CH0_INT_ST_R { - OUT_DSCR_ERR_CH0_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch0_int_st(&self) -> IN_DSCR_EMPTY_CH0_INT_ST_R { - IN_DSCR_EMPTY_CH0_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch0_int_st(&self) -> OUT_TOTAL_EOF_CH0_INT_ST_R { - OUT_TOTAL_EOF_CH0_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch0_int_st(&self) -> INFIFO_OVF_CH0_INT_ST_R { - INFIFO_OVF_CH0_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch0_int_st(&self) -> INFIFO_UDF_CH0_INT_ST_R { - INFIFO_UDF_CH0_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch0_int_st(&self) -> OUTFIFO_OVF_CH0_INT_ST_R { - OUTFIFO_OVF_CH0_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch0_int_st(&self) -> OUTFIFO_UDF_CH0_INT_ST_R { - OUTFIFO_UDF_CH0_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_ST_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_st_ch0](index.html) module"] diff --git a/esp32c3/src/dma/int_st_ch1.rs b/esp32c3/src/dma/int_st_ch1.rs index 3d79d54201..66b87d718e 100644 --- a/esp32c3/src/dma/int_st_ch1.rs +++ b/esp32c3/src/dma/int_st_ch1.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH1_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH1_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH1_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH1_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH1_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch1_int_st(&self) -> IN_DONE_CH1_INT_ST_R { - IN_DONE_CH1_INT_ST_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch1_int_st(&self) -> IN_SUC_EOF_CH1_INT_ST_R { - IN_SUC_EOF_CH1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch1_int_st(&self) -> IN_ERR_EOF_CH1_INT_ST_R { - IN_ERR_EOF_CH1_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch1_int_st(&self) -> OUT_DONE_CH1_INT_ST_R { - OUT_DONE_CH1_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch1_int_st(&self) -> OUT_EOF_CH1_INT_ST_R { - OUT_EOF_CH1_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch1_int_st(&self) -> IN_DSCR_ERR_CH1_INT_ST_R { - IN_DSCR_ERR_CH1_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch1_int_st(&self) -> OUT_DSCR_ERR_CH1_INT_ST_R { - OUT_DSCR_ERR_CH1_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch1_int_st(&self) -> IN_DSCR_EMPTY_CH1_INT_ST_R { - IN_DSCR_EMPTY_CH1_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch1_int_st(&self) -> OUT_TOTAL_EOF_CH1_INT_ST_R { - OUT_TOTAL_EOF_CH1_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch1_int_st(&self) -> INFIFO_OVF_CH1_INT_ST_R { - INFIFO_OVF_CH1_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch1_int_st(&self) -> INFIFO_UDF_CH1_INT_ST_R { - INFIFO_UDF_CH1_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch1_int_st(&self) -> OUTFIFO_OVF_CH1_INT_ST_R { - OUTFIFO_OVF_CH1_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch1_int_st(&self) -> OUTFIFO_UDF_CH1_INT_ST_R { - OUTFIFO_UDF_CH1_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_ST_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_st_ch1](index.html) module"] diff --git a/esp32c3/src/dma/int_st_ch2.rs b/esp32c3/src/dma/int_st_ch2.rs index 62eabd0392..02037efef7 100644 --- a/esp32c3/src/dma/int_st_ch2.rs +++ b/esp32c3/src/dma/int_st_ch2.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_CH2_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_CH2_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_CH2_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_CH2_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_CH2_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch2_int_st(&self) -> IN_DONE_CH2_INT_ST_R { - IN_DONE_CH2_INT_ST_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch2_int_st(&self) -> IN_SUC_EOF_CH2_INT_ST_R { - IN_SUC_EOF_CH2_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch2_int_st(&self) -> IN_ERR_EOF_CH2_INT_ST_R { - IN_ERR_EOF_CH2_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch2_int_st(&self) -> OUT_DONE_CH2_INT_ST_R { - OUT_DONE_CH2_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch2_int_st(&self) -> OUT_EOF_CH2_INT_ST_R { - OUT_EOF_CH2_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch2_int_st(&self) -> IN_DSCR_ERR_CH2_INT_ST_R { - IN_DSCR_ERR_CH2_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch2_int_st(&self) -> OUT_DSCR_ERR_CH2_INT_ST_R { - OUT_DSCR_ERR_CH2_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch2_int_st(&self) -> IN_DSCR_EMPTY_CH2_INT_ST_R { - IN_DSCR_EMPTY_CH2_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch2_int_st(&self) -> OUT_TOTAL_EOF_CH2_INT_ST_R { - OUT_TOTAL_EOF_CH2_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_ch2_int_st(&self) -> INFIFO_OVF_CH2_INT_ST_R { - INFIFO_OVF_CH2_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_ovf(&self) -> INFIFO_OVF_R { + INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_ch2_int_st(&self) -> INFIFO_UDF_CH2_INT_ST_R { - INFIFO_UDF_CH2_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn infifo_udf(&self) -> INFIFO_UDF_R { + INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_ch2_int_st(&self) -> OUTFIFO_OVF_CH2_INT_ST_R { - OUTFIFO_OVF_CH2_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R { + OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_ch2_int_st(&self) -> OUTFIFO_UDF_CH2_INT_ST_R { - OUTFIFO_UDF_CH2_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R { + OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } } #[doc = "DMA_INT_ST_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_st_ch2](index.html) module"] diff --git a/esp32c3/src/dma/out_conf0_ch0.rs b/esp32c3/src/dma/out_conf0_ch0.rs index fbb33881ae..0861900968 100644 --- a/esp32c3/src/dma/out_conf0_ch0.rs +++ b/esp32c3/src/dma/out_conf0_ch0.rs @@ -34,97 +34,95 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_RST_CH0` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH0_R = crate::BitReader; -#[doc = "Field `OUT_RST_CH0` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_LOOP_TEST_CH0` reader - reserved"] -pub type OUT_LOOP_TEST_CH0_R = crate::BitReader; -#[doc = "Field `OUT_LOOP_TEST_CH0` writer - reserved"] -pub type OUT_LOOP_TEST_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_LOOP_TEST` reader - reserved"] +pub type OUT_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST` writer - reserved"] +pub type OUT_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_AUTO_WRBACK_CH0` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH0_R = crate::BitReader; -#[doc = "Field `OUT_AUTO_WRBACK_CH0` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; +#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_MODE_CH0` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH0_R = crate::BitReader; -#[doc = "Field `OUT_EOF_MODE_CH0` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUTDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `OUTDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; -#[doc = "Field `OUT_DATA_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH0_R = crate::BitReader; -#[doc = "Field `OUT_DATA_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch0(&self) -> OUT_RST_CH0_R { - OUT_RST_CH0_R::new((self.bits & 1) != 0) + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch0(&self) -> OUT_LOOP_TEST_CH0_R { - OUT_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R { + OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch0(&self) -> OUT_AUTO_WRBACK_CH0_R { - OUT_AUTO_WRBACK_CH0_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch0(&self) -> OUT_EOF_MODE_CH0_R { - OUT_EOF_MODE_CH0_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R { + OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch0(&self) -> OUTDSCR_BURST_EN_CH0_R { - OUTDSCR_BURST_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R { + OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch0(&self) -> OUT_DATA_BURST_EN_CH0_R { - OUT_DATA_BURST_EN_CH0_R::new(((self.bits >> 5) & 1) != 0) + pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R { + OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch0(&mut self) -> OUT_RST_CH0_W<0> { - OUT_RST_CH0_W::new(self) + pub fn out_rst(&mut self) -> OUT_RST_W<0> { + OUT_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch0(&mut self) -> OUT_LOOP_TEST_CH0_W<1> { - OUT_LOOP_TEST_CH0_W::new(self) + pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<1> { + OUT_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch0(&mut self) -> OUT_AUTO_WRBACK_CH0_W<2> { - OUT_AUTO_WRBACK_CH0_W::new(self) + pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<2> { + OUT_AUTO_WRBACK_W::new(self) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch0(&mut self) -> OUT_EOF_MODE_CH0_W<3> { - OUT_EOF_MODE_CH0_W::new(self) + pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<3> { + OUT_EOF_MODE_W::new(self) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch0(&mut self) -> OUTDSCR_BURST_EN_CH0_W<4> { - OUTDSCR_BURST_EN_CH0_W::new(self) + pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<4> { + OUTDSCR_BURST_EN_W::new(self) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch0(&mut self) -> OUT_DATA_BURST_EN_CH0_W<5> { - OUT_DATA_BURST_EN_CH0_W::new(self) + pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<5> { + OUT_DATA_BURST_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_conf0_ch1.rs b/esp32c3/src/dma/out_conf0_ch1.rs index 64031ca572..d7eb2d38f0 100644 --- a/esp32c3/src/dma/out_conf0_ch1.rs +++ b/esp32c3/src/dma/out_conf0_ch1.rs @@ -34,97 +34,95 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_RST_CH1` reader - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH1_R = crate::BitReader; -#[doc = "Field `OUT_RST_CH1` writer - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_LOOP_TEST_CH1` reader - reserved"] -pub type OUT_LOOP_TEST_CH1_R = crate::BitReader; -#[doc = "Field `OUT_LOOP_TEST_CH1` writer - reserved"] -pub type OUT_LOOP_TEST_CH1_W<'a, const O: u8> = +#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_LOOP_TEST` reader - reserved"] +pub type OUT_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST` writer - reserved"] +pub type OUT_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_AUTO_WRBACK_CH1` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH1_R = crate::BitReader; -#[doc = "Field `OUT_AUTO_WRBACK_CH1` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH1_W<'a, const O: u8> = +#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; +#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_MODE_CH1` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH1_R = crate::BitReader; -#[doc = "Field `OUT_EOF_MODE_CH1` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `OUTDSCR_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH1_R = crate::BitReader; -#[doc = "Field `OUTDSCR_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; -#[doc = "Field `OUT_DATA_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH1_R = crate::BitReader; -#[doc = "Field `OUT_DATA_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH1_W<'a, const O: u8> = +#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH1_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch1(&self) -> OUT_RST_CH1_R { - OUT_RST_CH1_R::new((self.bits & 1) != 0) + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch1(&self) -> OUT_LOOP_TEST_CH1_R { - OUT_LOOP_TEST_CH1_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R { + OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch1(&self) -> OUT_AUTO_WRBACK_CH1_R { - OUT_AUTO_WRBACK_CH1_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch1(&self) -> OUT_EOF_MODE_CH1_R { - OUT_EOF_MODE_CH1_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R { + OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch1(&self) -> OUTDSCR_BURST_EN_CH1_R { - OUTDSCR_BURST_EN_CH1_R::new(((self.bits >> 4) & 1) != 0) + pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R { + OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch1(&self) -> OUT_DATA_BURST_EN_CH1_R { - OUT_DATA_BURST_EN_CH1_R::new(((self.bits >> 5) & 1) != 0) + pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R { + OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch1(&mut self) -> OUT_RST_CH1_W<0> { - OUT_RST_CH1_W::new(self) + pub fn out_rst(&mut self) -> OUT_RST_W<0> { + OUT_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch1(&mut self) -> OUT_LOOP_TEST_CH1_W<1> { - OUT_LOOP_TEST_CH1_W::new(self) + pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<1> { + OUT_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch1(&mut self) -> OUT_AUTO_WRBACK_CH1_W<2> { - OUT_AUTO_WRBACK_CH1_W::new(self) + pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<2> { + OUT_AUTO_WRBACK_W::new(self) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch1(&mut self) -> OUT_EOF_MODE_CH1_W<3> { - OUT_EOF_MODE_CH1_W::new(self) + pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<3> { + OUT_EOF_MODE_W::new(self) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch1(&mut self) -> OUTDSCR_BURST_EN_CH1_W<4> { - OUTDSCR_BURST_EN_CH1_W::new(self) + pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<4> { + OUTDSCR_BURST_EN_W::new(self) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch1(&mut self) -> OUT_DATA_BURST_EN_CH1_W<5> { - OUT_DATA_BURST_EN_CH1_W::new(self) + pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<5> { + OUT_DATA_BURST_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_conf0_ch2.rs b/esp32c3/src/dma/out_conf0_ch2.rs index 6babf3e8b0..1f198ef33d 100644 --- a/esp32c3/src/dma/out_conf0_ch2.rs +++ b/esp32c3/src/dma/out_conf0_ch2.rs @@ -34,97 +34,95 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_RST_CH2` reader - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH2_R = crate::BitReader; -#[doc = "Field `OUT_RST_CH2` writer - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_LOOP_TEST_CH2` reader - reserved"] -pub type OUT_LOOP_TEST_CH2_R = crate::BitReader; -#[doc = "Field `OUT_LOOP_TEST_CH2` writer - reserved"] -pub type OUT_LOOP_TEST_CH2_W<'a, const O: u8> = +#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_LOOP_TEST` reader - reserved"] +pub type OUT_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST` writer - reserved"] +pub type OUT_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_AUTO_WRBACK_CH2` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH2_R = crate::BitReader; -#[doc = "Field `OUT_AUTO_WRBACK_CH2` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH2_W<'a, const O: u8> = +#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; +#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_MODE_CH2` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH2_R = crate::BitReader; -#[doc = "Field `OUT_EOF_MODE_CH2` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `OUTDSCR_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH2_R = crate::BitReader; -#[doc = "Field `OUTDSCR_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; -#[doc = "Field `OUT_DATA_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH2_R = crate::BitReader; -#[doc = "Field `OUT_DATA_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH2_W<'a, const O: u8> = +#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH2_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch2(&self) -> OUT_RST_CH2_R { - OUT_RST_CH2_R::new((self.bits & 1) != 0) + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch2(&self) -> OUT_LOOP_TEST_CH2_R { - OUT_LOOP_TEST_CH2_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R { + OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch2(&self) -> OUT_AUTO_WRBACK_CH2_R { - OUT_AUTO_WRBACK_CH2_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch2(&self) -> OUT_EOF_MODE_CH2_R { - OUT_EOF_MODE_CH2_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R { + OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch2(&self) -> OUTDSCR_BURST_EN_CH2_R { - OUTDSCR_BURST_EN_CH2_R::new(((self.bits >> 4) & 1) != 0) + pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R { + OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch2(&self) -> OUT_DATA_BURST_EN_CH2_R { - OUT_DATA_BURST_EN_CH2_R::new(((self.bits >> 5) & 1) != 0) + pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R { + OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch2(&mut self) -> OUT_RST_CH2_W<0> { - OUT_RST_CH2_W::new(self) + pub fn out_rst(&mut self) -> OUT_RST_W<0> { + OUT_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch2(&mut self) -> OUT_LOOP_TEST_CH2_W<1> { - OUT_LOOP_TEST_CH2_W::new(self) + pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<1> { + OUT_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch2(&mut self) -> OUT_AUTO_WRBACK_CH2_W<2> { - OUT_AUTO_WRBACK_CH2_W::new(self) + pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<2> { + OUT_AUTO_WRBACK_W::new(self) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch2(&mut self) -> OUT_EOF_MODE_CH2_W<3> { - OUT_EOF_MODE_CH2_W::new(self) + pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<3> { + OUT_EOF_MODE_W::new(self) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch2(&mut self) -> OUTDSCR_BURST_EN_CH2_W<4> { - OUTDSCR_BURST_EN_CH2_W::new(self) + pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<4> { + OUTDSCR_BURST_EN_W::new(self) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch2(&mut self) -> OUT_DATA_BURST_EN_CH2_W<5> { - OUT_DATA_BURST_EN_CH2_W::new(self) + pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<5> { + OUT_DATA_BURST_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_conf1_ch0.rs b/esp32c3/src/dma/out_conf1_ch0.rs index ac54027fed..a6904b8d47 100644 --- a/esp32c3/src/dma/out_conf1_ch0.rs +++ b/esp32c3/src/dma/out_conf1_ch0.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH0_R = crate::BitReader; -#[doc = "Field `OUT_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH0_W<'a, const O: u8> = +#[doc = "Field `OUT_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF1_CH0_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch0(&self) -> OUT_CHECK_OWNER_CH0_R { - OUT_CHECK_OWNER_CH0_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_check_owner(&self) -> OUT_CHECK_OWNER_R { + OUT_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch0(&mut self) -> OUT_CHECK_OWNER_CH0_W<12> { - OUT_CHECK_OWNER_CH0_W::new(self) + pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<12> { + OUT_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_conf1_ch1.rs b/esp32c3/src/dma/out_conf1_ch1.rs index f037849569..c1b6b14aa5 100644 --- a/esp32c3/src/dma/out_conf1_ch1.rs +++ b/esp32c3/src/dma/out_conf1_ch1.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_CHECK_OWNER_CH1` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH1_R = crate::BitReader; -#[doc = "Field `OUT_CHECK_OWNER_CH1` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH1_W<'a, const O: u8> = +#[doc = "Field `OUT_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF1_CH1_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch1(&self) -> OUT_CHECK_OWNER_CH1_R { - OUT_CHECK_OWNER_CH1_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_check_owner(&self) -> OUT_CHECK_OWNER_R { + OUT_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch1(&mut self) -> OUT_CHECK_OWNER_CH1_W<12> { - OUT_CHECK_OWNER_CH1_W::new(self) + pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<12> { + OUT_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_conf1_ch2.rs b/esp32c3/src/dma/out_conf1_ch2.rs index f86dbc3b31..b63dbd2471 100644 --- a/esp32c3/src/dma/out_conf1_ch2.rs +++ b/esp32c3/src/dma/out_conf1_ch2.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_CHECK_OWNER_CH2` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH2_R = crate::BitReader; -#[doc = "Field `OUT_CHECK_OWNER_CH2` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH2_W<'a, const O: u8> = +#[doc = "Field `OUT_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF1_CH2_SPEC, bool, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch2(&self) -> OUT_CHECK_OWNER_CH2_R { - OUT_CHECK_OWNER_CH2_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_check_owner(&self) -> OUT_CHECK_OWNER_R { + OUT_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch2(&mut self) -> OUT_CHECK_OWNER_CH2_W<12> { - OUT_CHECK_OWNER_CH2_W::new(self) + pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<12> { + OUT_CHECK_OWNER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_dscr_bf0_ch0.rs b/esp32c3/src/dma/out_dscr_bf0_ch0.rs index 611104a0f1..3f61fdee2a 100644 --- a/esp32c3/src/dma/out_dscr_bf0_ch0.rs +++ b/esp32c3/src/dma/out_dscr_bf0_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF0_CH0` reader - The address of the last outlink descriptor y-1."] -pub type OUTLINK_DSCR_BF0_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] #[inline(always)] - pub fn outlink_dscr_bf0_ch0(&self) -> OUTLINK_DSCR_BF0_CH0_R { - OUTLINK_DSCR_BF0_CH0_R::new(self.bits) + pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R { + OUTLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF0_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf0_ch0](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_bf0_ch1.rs b/esp32c3/src/dma/out_dscr_bf0_ch1.rs index 20c2d565a0..ea485b5788 100644 --- a/esp32c3/src/dma/out_dscr_bf0_ch1.rs +++ b/esp32c3/src/dma/out_dscr_bf0_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF0_CH1` reader - The address of the last outlink descriptor y-1."] -pub type OUTLINK_DSCR_BF0_CH1_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] #[inline(always)] - pub fn outlink_dscr_bf0_ch1(&self) -> OUTLINK_DSCR_BF0_CH1_R { - OUTLINK_DSCR_BF0_CH1_R::new(self.bits) + pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R { + OUTLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF0_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf0_ch1](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_bf0_ch2.rs b/esp32c3/src/dma/out_dscr_bf0_ch2.rs index 221aeb83f2..51639f6d28 100644 --- a/esp32c3/src/dma/out_dscr_bf0_ch2.rs +++ b/esp32c3/src/dma/out_dscr_bf0_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF0_CH2` reader - The address of the last outlink descriptor y-1."] -pub type OUTLINK_DSCR_BF0_CH2_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] #[inline(always)] - pub fn outlink_dscr_bf0_ch2(&self) -> OUTLINK_DSCR_BF0_CH2_R { - OUTLINK_DSCR_BF0_CH2_R::new(self.bits) + pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R { + OUTLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF0_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf0_ch2](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_bf1_ch0.rs b/esp32c3/src/dma/out_dscr_bf1_ch0.rs index 291ad971c4..d06bd723c5 100644 --- a/esp32c3/src/dma/out_dscr_bf1_ch0.rs +++ b/esp32c3/src/dma/out_dscr_bf1_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF1_CH0` reader - The address of the second-to-last inlink descriptor x-2."] -pub type OUTLINK_DSCR_BF1_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn outlink_dscr_bf1_ch0(&self) -> OUTLINK_DSCR_BF1_CH0_R { - OUTLINK_DSCR_BF1_CH0_R::new(self.bits) + pub fn outlink_dscr_bf1(&self) -> OUTLINK_DSCR_BF1_R { + OUTLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF1_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf1_ch0](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_bf1_ch1.rs b/esp32c3/src/dma/out_dscr_bf1_ch1.rs index 760594bb25..9033266d1c 100644 --- a/esp32c3/src/dma/out_dscr_bf1_ch1.rs +++ b/esp32c3/src/dma/out_dscr_bf1_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF1_CH1` reader - The address of the second-to-last inlink descriptor x-2."] -pub type OUTLINK_DSCR_BF1_CH1_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn outlink_dscr_bf1_ch1(&self) -> OUTLINK_DSCR_BF1_CH1_R { - OUTLINK_DSCR_BF1_CH1_R::new(self.bits) + pub fn outlink_dscr_bf1(&self) -> OUTLINK_DSCR_BF1_R { + OUTLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF1_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf1_ch1](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_bf1_ch2.rs b/esp32c3/src/dma/out_dscr_bf1_ch2.rs index 5db583b661..0f89f521f8 100644 --- a/esp32c3/src/dma/out_dscr_bf1_ch2.rs +++ b/esp32c3/src/dma/out_dscr_bf1_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF1_CH2` reader - The address of the second-to-last inlink descriptor x-2."] -pub type OUTLINK_DSCR_BF1_CH2_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn outlink_dscr_bf1_ch2(&self) -> OUTLINK_DSCR_BF1_CH2_R { - OUTLINK_DSCR_BF1_CH2_R::new(self.bits) + pub fn outlink_dscr_bf1(&self) -> OUTLINK_DSCR_BF1_R { + OUTLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_BF1_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf1_ch2](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_ch0.rs b/esp32c3/src/dma/out_dscr_ch0.rs index 583bc7fb3d..cc02002e38 100644 --- a/esp32c3/src/dma/out_dscr_ch0.rs +++ b/esp32c3/src/dma/out_dscr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_CH0` reader - The address of the current outlink descriptor y."] -pub type OUTLINK_DSCR_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] #[inline(always)] - pub fn outlink_dscr_ch0(&self) -> OUTLINK_DSCR_CH0_R { - OUTLINK_DSCR_CH0_R::new(self.bits) + pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R { + OUTLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_ch0](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_ch1.rs b/esp32c3/src/dma/out_dscr_ch1.rs index 8a757656aa..af0ac1014c 100644 --- a/esp32c3/src/dma/out_dscr_ch1.rs +++ b/esp32c3/src/dma/out_dscr_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_CH1` reader - The address of the current outlink descriptor y."] -pub type OUTLINK_DSCR_CH1_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] #[inline(always)] - pub fn outlink_dscr_ch1(&self) -> OUTLINK_DSCR_CH1_R { - OUTLINK_DSCR_CH1_R::new(self.bits) + pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R { + OUTLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_ch1](index.html) module"] diff --git a/esp32c3/src/dma/out_dscr_ch2.rs b/esp32c3/src/dma/out_dscr_ch2.rs index 5c9a934e5e..9d633a4601 100644 --- a/esp32c3/src/dma/out_dscr_ch2.rs +++ b/esp32c3/src/dma/out_dscr_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_CH2` reader - The address of the current outlink descriptor y."] -pub type OUTLINK_DSCR_CH2_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] #[inline(always)] - pub fn outlink_dscr_ch2(&self) -> OUTLINK_DSCR_CH2_R { - OUTLINK_DSCR_CH2_R::new(self.bits) + pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R { + OUTLINK_DSCR_R::new(self.bits) } } #[doc = "DMA_OUT_DSCR_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_ch2](index.html) module"] diff --git a/esp32c3/src/dma/out_eof_bfr_des_addr_ch0.rs b/esp32c3/src/dma/out_eof_bfr_des_addr_ch0.rs index ae1ad3ec5e..94b06d3bf3 100644 --- a/esp32c3/src/dma/out_eof_bfr_des_addr_ch0.rs +++ b/esp32c3/src/dma/out_eof_bfr_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH0` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] -pub type OUT_EOF_BFR_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] #[inline(always)] - pub fn out_eof_bfr_des_addr_ch0(&self) -> OUT_EOF_BFR_DES_ADDR_CH0_R { - OUT_EOF_BFR_DES_ADDR_CH0_R::new(self.bits) + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_bfr_des_addr_ch0](index.html) module"] diff --git a/esp32c3/src/dma/out_eof_bfr_des_addr_ch1.rs b/esp32c3/src/dma/out_eof_bfr_des_addr_ch1.rs index 334bae7e0f..8497fc3c21 100644 --- a/esp32c3/src/dma/out_eof_bfr_des_addr_ch1.rs +++ b/esp32c3/src/dma/out_eof_bfr_des_addr_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH1` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] -pub type OUT_EOF_BFR_DES_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] #[inline(always)] - pub fn out_eof_bfr_des_addr_ch1(&self) -> OUT_EOF_BFR_DES_ADDR_CH1_R { - OUT_EOF_BFR_DES_ADDR_CH1_R::new(self.bits) + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_bfr_des_addr_ch1](index.html) module"] diff --git a/esp32c3/src/dma/out_eof_bfr_des_addr_ch2.rs b/esp32c3/src/dma/out_eof_bfr_des_addr_ch2.rs index 4994c22373..ef267e9d83 100644 --- a/esp32c3/src/dma/out_eof_bfr_des_addr_ch2.rs +++ b/esp32c3/src/dma/out_eof_bfr_des_addr_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH2` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] -pub type OUT_EOF_BFR_DES_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] #[inline(always)] - pub fn out_eof_bfr_des_addr_ch2(&self) -> OUT_EOF_BFR_DES_ADDR_CH2_R { - OUT_EOF_BFR_DES_ADDR_CH2_R::new(self.bits) + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_bfr_des_addr_ch2](index.html) module"] diff --git a/esp32c3/src/dma/out_eof_des_addr_ch0.rs b/esp32c3/src/dma/out_eof_des_addr_ch0.rs index 371d95647d..d5e778bf01 100644 --- a/esp32c3/src/dma/out_eof_des_addr_ch0.rs +++ b/esp32c3/src/dma/out_eof_des_addr_ch0.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_DES_ADDR_CH0` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] -pub type OUT_EOF_DES_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn out_eof_des_addr_ch0(&self) -> OUT_EOF_DES_ADDR_CH0_R { - OUT_EOF_DES_ADDR_CH0_R::new(self.bits) + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_DES_ADDR_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_des_addr_ch0](index.html) module"] diff --git a/esp32c3/src/dma/out_eof_des_addr_ch1.rs b/esp32c3/src/dma/out_eof_des_addr_ch1.rs index 5e865a29f3..002af704b4 100644 --- a/esp32c3/src/dma/out_eof_des_addr_ch1.rs +++ b/esp32c3/src/dma/out_eof_des_addr_ch1.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_DES_ADDR_CH1` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] -pub type OUT_EOF_DES_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn out_eof_des_addr_ch1(&self) -> OUT_EOF_DES_ADDR_CH1_R { - OUT_EOF_DES_ADDR_CH1_R::new(self.bits) + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_DES_ADDR_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_des_addr_ch1](index.html) module"] diff --git a/esp32c3/src/dma/out_eof_des_addr_ch2.rs b/esp32c3/src/dma/out_eof_des_addr_ch2.rs index c132f02668..7dd278b3dc 100644 --- a/esp32c3/src/dma/out_eof_des_addr_ch2.rs +++ b/esp32c3/src/dma/out_eof_des_addr_ch2.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_DES_ADDR_CH2` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] -pub type OUT_EOF_DES_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn out_eof_des_addr_ch2(&self) -> OUT_EOF_DES_ADDR_CH2_R { - OUT_EOF_DES_ADDR_CH2_R::new(self.bits) + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "DMA_OUT_EOF_DES_ADDR_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_des_addr_ch2](index.html) module"] diff --git a/esp32c3/src/dma/out_link_ch0.rs b/esp32c3/src/dma/out_link_ch0.rs index 66579d55e7..9b659381ef 100644 --- a/esp32c3/src/dma/out_link_ch0.rs +++ b/esp32c3/src/dma/out_link_ch0.rs @@ -34,75 +34,72 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTLINK_ADDR_CH0` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `OUTLINK_ADDR_CH0` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH0_W<'a, const O: u8> = +#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_LINK_CH0_SPEC, u32, u32, 20, O>; -#[doc = "Field `OUTLINK_STOP_CH0` reader - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH0_R = crate::BitReader; -#[doc = "Field `OUTLINK_STOP_CH0` writer - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `OUTLINK_START_CH0` reader - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH0_R = crate::BitReader; -#[doc = "Field `OUTLINK_START_CH0` writer - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `OUTLINK_RESTART_CH0` reader - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH0_R = crate::BitReader; -#[doc = "Field `OUTLINK_RESTART_CH0` writer - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; -#[doc = "Field `OUTLINK_PARK_CH0` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] -pub type OUTLINK_PARK_CH0_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH0_SPEC, bool, O>; +#[doc = "Field `OUTLINK_PARK` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch0(&self) -> OUTLINK_ADDR_CH0_R { - OUTLINK_ADDR_CH0_R::new((self.bits & 0x000f_ffff) as u32) + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch0(&self) -> OUTLINK_STOP_CH0_R { - OUTLINK_STOP_CH0_R::new(((self.bits >> 20) & 1) != 0) + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch0(&self) -> OUTLINK_START_CH0_R { - OUTLINK_START_CH0_R::new(((self.bits >> 21) & 1) != 0) + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch0(&self) -> OUTLINK_RESTART_CH0_R { - OUTLINK_RESTART_CH0_R::new(((self.bits >> 22) & 1) != 0) + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] #[inline(always)] - pub fn outlink_park_ch0(&self) -> OUTLINK_PARK_CH0_R { - OUTLINK_PARK_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch0(&mut self) -> OUTLINK_ADDR_CH0_W<0> { - OUTLINK_ADDR_CH0_W::new(self) + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<0> { + OUTLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch0(&mut self) -> OUTLINK_STOP_CH0_W<20> { - OUTLINK_STOP_CH0_W::new(self) + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<20> { + OUTLINK_STOP_W::new(self) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch0(&mut self) -> OUTLINK_START_CH0_W<21> { - OUTLINK_START_CH0_W::new(self) + pub fn outlink_start(&mut self) -> OUTLINK_START_W<21> { + OUTLINK_START_W::new(self) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch0(&mut self) -> OUTLINK_RESTART_CH0_W<22> { - OUTLINK_RESTART_CH0_W::new(self) + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<22> { + OUTLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_link_ch1.rs b/esp32c3/src/dma/out_link_ch1.rs index 47c0a5d4b9..bc994f947a 100644 --- a/esp32c3/src/dma/out_link_ch1.rs +++ b/esp32c3/src/dma/out_link_ch1.rs @@ -34,75 +34,72 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTLINK_ADDR_CH1` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH1_R = crate::FieldReader; -#[doc = "Field `OUTLINK_ADDR_CH1` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH1_W<'a, const O: u8> = +#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_LINK_CH1_SPEC, u32, u32, 20, O>; -#[doc = "Field `OUTLINK_STOP_CH1` reader - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH1_R = crate::BitReader; -#[doc = "Field `OUTLINK_STOP_CH1` writer - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `OUTLINK_START_CH1` reader - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH1_R = crate::BitReader; -#[doc = "Field `OUTLINK_START_CH1` writer - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `OUTLINK_RESTART_CH1` reader - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH1_R = crate::BitReader; -#[doc = "Field `OUTLINK_RESTART_CH1` writer - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH1_SPEC, bool, O>; -#[doc = "Field `OUTLINK_PARK_CH1` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] -pub type OUTLINK_PARK_CH1_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH1_SPEC, bool, O>; +#[doc = "Field `OUTLINK_PARK` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch1(&self) -> OUTLINK_ADDR_CH1_R { - OUTLINK_ADDR_CH1_R::new((self.bits & 0x000f_ffff) as u32) + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch1(&self) -> OUTLINK_STOP_CH1_R { - OUTLINK_STOP_CH1_R::new(((self.bits >> 20) & 1) != 0) + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch1(&self) -> OUTLINK_START_CH1_R { - OUTLINK_START_CH1_R::new(((self.bits >> 21) & 1) != 0) + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch1(&self) -> OUTLINK_RESTART_CH1_R { - OUTLINK_RESTART_CH1_R::new(((self.bits >> 22) & 1) != 0) + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] #[inline(always)] - pub fn outlink_park_ch1(&self) -> OUTLINK_PARK_CH1_R { - OUTLINK_PARK_CH1_R::new(((self.bits >> 23) & 1) != 0) + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch1(&mut self) -> OUTLINK_ADDR_CH1_W<0> { - OUTLINK_ADDR_CH1_W::new(self) + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<0> { + OUTLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch1(&mut self) -> OUTLINK_STOP_CH1_W<20> { - OUTLINK_STOP_CH1_W::new(self) + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<20> { + OUTLINK_STOP_W::new(self) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch1(&mut self) -> OUTLINK_START_CH1_W<21> { - OUTLINK_START_CH1_W::new(self) + pub fn outlink_start(&mut self) -> OUTLINK_START_W<21> { + OUTLINK_START_W::new(self) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch1(&mut self) -> OUTLINK_RESTART_CH1_W<22> { - OUTLINK_RESTART_CH1_W::new(self) + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<22> { + OUTLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_link_ch2.rs b/esp32c3/src/dma/out_link_ch2.rs index 72f92e1d37..1f5c3e63a6 100644 --- a/esp32c3/src/dma/out_link_ch2.rs +++ b/esp32c3/src/dma/out_link_ch2.rs @@ -34,75 +34,72 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTLINK_ADDR_CH2` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH2_R = crate::FieldReader; -#[doc = "Field `OUTLINK_ADDR_CH2` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH2_W<'a, const O: u8> = +#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_LINK_CH2_SPEC, u32, u32, 20, O>; -#[doc = "Field `OUTLINK_STOP_CH2` reader - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH2_R = crate::BitReader; -#[doc = "Field `OUTLINK_STOP_CH2` writer - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `OUTLINK_START_CH2` reader - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH2_R = crate::BitReader; -#[doc = "Field `OUTLINK_START_CH2` writer - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `OUTLINK_RESTART_CH2` reader - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH2_R = crate::BitReader; -#[doc = "Field `OUTLINK_RESTART_CH2` writer - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH2_SPEC, bool, O>; -#[doc = "Field `OUTLINK_PARK_CH2` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] -pub type OUTLINK_PARK_CH2_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH2_SPEC, bool, O>; +#[doc = "Field `OUTLINK_PARK` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch2(&self) -> OUTLINK_ADDR_CH2_R { - OUTLINK_ADDR_CH2_R::new((self.bits & 0x000f_ffff) as u32) + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch2(&self) -> OUTLINK_STOP_CH2_R { - OUTLINK_STOP_CH2_R::new(((self.bits >> 20) & 1) != 0) + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch2(&self) -> OUTLINK_START_CH2_R { - OUTLINK_START_CH2_R::new(((self.bits >> 21) & 1) != 0) + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch2(&self) -> OUTLINK_RESTART_CH2_R { - OUTLINK_RESTART_CH2_R::new(((self.bits >> 22) & 1) != 0) + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] #[inline(always)] - pub fn outlink_park_ch2(&self) -> OUTLINK_PARK_CH2_R { - OUTLINK_PARK_CH2_R::new(((self.bits >> 23) & 1) != 0) + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch2(&mut self) -> OUTLINK_ADDR_CH2_W<0> { - OUTLINK_ADDR_CH2_W::new(self) + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<0> { + OUTLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch2(&mut self) -> OUTLINK_STOP_CH2_W<20> { - OUTLINK_STOP_CH2_W::new(self) + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<20> { + OUTLINK_STOP_W::new(self) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch2(&mut self) -> OUTLINK_START_CH2_W<21> { - OUTLINK_START_CH2_W::new(self) + pub fn outlink_start(&mut self) -> OUTLINK_START_W<21> { + OUTLINK_START_W::new(self) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch2(&mut self) -> OUTLINK_RESTART_CH2_W<22> { - OUTLINK_RESTART_CH2_W::new(self) + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<22> { + OUTLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_peri_sel_ch0.rs b/esp32c3/src/dma/out_peri_sel_ch0.rs index f8f4c76479..4851630534 100644 --- a/esp32c3/src/dma/out_peri_sel_ch0.rs +++ b/esp32c3/src/dma/out_peri_sel_ch0.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_OUT_SEL_CH0` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH0_R = crate::FieldReader; -#[doc = "Field `PERI_OUT_SEL_CH0` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH0_W<'a, const O: u8> = +#[doc = "Field `PERI_OUT_SEL` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PERI_SEL_CH0_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch0(&self) -> PERI_OUT_SEL_CH0_R { - PERI_OUT_SEL_CH0_R::new((self.bits & 0x3f) as u8) + pub fn peri_out_sel(&self) -> PERI_OUT_SEL_R { + PERI_OUT_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch0(&mut self) -> PERI_OUT_SEL_CH0_W<0> { - PERI_OUT_SEL_CH0_W::new(self) + pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<0> { + PERI_OUT_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_peri_sel_ch1.rs b/esp32c3/src/dma/out_peri_sel_ch1.rs index c7f4968b70..8af42c70ba 100644 --- a/esp32c3/src/dma/out_peri_sel_ch1.rs +++ b/esp32c3/src/dma/out_peri_sel_ch1.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_OUT_SEL_CH1` reader - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH1_R = crate::FieldReader; -#[doc = "Field `PERI_OUT_SEL_CH1` writer - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH1_W<'a, const O: u8> = +#[doc = "Field `PERI_OUT_SEL` reader - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL` writer - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PERI_SEL_CH1_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch1(&self) -> PERI_OUT_SEL_CH1_R { - PERI_OUT_SEL_CH1_R::new((self.bits & 0x3f) as u8) + pub fn peri_out_sel(&self) -> PERI_OUT_SEL_R { + PERI_OUT_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch1(&mut self) -> PERI_OUT_SEL_CH1_W<0> { - PERI_OUT_SEL_CH1_W::new(self) + pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<0> { + PERI_OUT_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_peri_sel_ch2.rs b/esp32c3/src/dma/out_peri_sel_ch2.rs index b33cf33051..8fbaabf741 100644 --- a/esp32c3/src/dma/out_peri_sel_ch2.rs +++ b/esp32c3/src/dma/out_peri_sel_ch2.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_OUT_SEL_CH2` reader - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH2_R = crate::FieldReader; -#[doc = "Field `PERI_OUT_SEL_CH2` writer - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] -pub type PERI_OUT_SEL_CH2_W<'a, const O: u8> = +#[doc = "Field `PERI_OUT_SEL` reader - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL` writer - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] +pub type PERI_OUT_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PERI_SEL_CH2_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch2(&self) -> PERI_OUT_SEL_CH2_R { - PERI_OUT_SEL_CH2_R::new((self.bits & 0x3f) as u8) + pub fn peri_out_sel(&self) -> PERI_OUT_SEL_R { + PERI_OUT_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."] #[inline(always)] - pub fn peri_out_sel_ch2(&mut self) -> PERI_OUT_SEL_CH2_W<0> { - PERI_OUT_SEL_CH2_W::new(self) + pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<0> { + PERI_OUT_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_pri_ch0.rs b/esp32c3/src/dma/out_pri_ch0.rs index e271fe425a..31967b6bce 100644 --- a/esp32c3/src/dma/out_pri_ch0.rs +++ b/esp32c3/src/dma/out_pri_ch0.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `TX_PRI_CH0` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH0_R = crate::FieldReader; -#[doc = "Field `TX_PRI_CH0` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, OUT_PRI_CH0_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_PRI` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."] +pub type TX_PRI_R = crate::FieldReader; +#[doc = "Field `TX_PRI` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."] +pub type TX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PRI_CH0_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch0(&self) -> TX_PRI_CH0_R { - TX_PRI_CH0_R::new((self.bits & 0x0f) as u8) + pub fn tx_pri(&self) -> TX_PRI_R { + TX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch0(&mut self) -> TX_PRI_CH0_W<0> { - TX_PRI_CH0_W::new(self) + pub fn tx_pri(&mut self) -> TX_PRI_W<0> { + TX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_pri_ch1.rs b/esp32c3/src/dma/out_pri_ch1.rs index 3d9aa18a0d..4560ceb5da 100644 --- a/esp32c3/src/dma/out_pri_ch1.rs +++ b/esp32c3/src/dma/out_pri_ch1.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `TX_PRI_CH1` reader - The priority of Tx channel 1. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH1_R = crate::FieldReader; -#[doc = "Field `TX_PRI_CH1` writer - The priority of Tx channel 1. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, OUT_PRI_CH1_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_PRI` reader - The priority of Tx channel 1. The larger of the value, the higher of the priority."] +pub type TX_PRI_R = crate::FieldReader; +#[doc = "Field `TX_PRI` writer - The priority of Tx channel 1. The larger of the value, the higher of the priority."] +pub type TX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PRI_CH1_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Tx channel 1. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch1(&self) -> TX_PRI_CH1_R { - TX_PRI_CH1_R::new((self.bits & 0x0f) as u8) + pub fn tx_pri(&self) -> TX_PRI_R { + TX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Tx channel 1. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch1(&mut self) -> TX_PRI_CH1_W<0> { - TX_PRI_CH1_W::new(self) + pub fn tx_pri(&mut self) -> TX_PRI_W<0> { + TX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_pri_ch2.rs b/esp32c3/src/dma/out_pri_ch2.rs index b45cd602c3..31bb527b38 100644 --- a/esp32c3/src/dma/out_pri_ch2.rs +++ b/esp32c3/src/dma/out_pri_ch2.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `TX_PRI_CH2` reader - The priority of Tx channel 2. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH2_R = crate::FieldReader; -#[doc = "Field `TX_PRI_CH2` writer - The priority of Tx channel 2. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, OUT_PRI_CH2_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_PRI` reader - The priority of Tx channel 2. The larger of the value, the higher of the priority."] +pub type TX_PRI_R = crate::FieldReader; +#[doc = "Field `TX_PRI` writer - The priority of Tx channel 2. The larger of the value, the higher of the priority."] +pub type TX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PRI_CH2_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Tx channel 2. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch2(&self) -> TX_PRI_CH2_R { - TX_PRI_CH2_R::new((self.bits & 0x0f) as u8) + pub fn tx_pri(&self) -> TX_PRI_R { + TX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Tx channel 2. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch2(&mut self) -> TX_PRI_CH2_W<0> { - TX_PRI_CH2_W::new(self) + pub fn tx_pri(&mut self) -> TX_PRI_W<0> { + TX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_push_ch0.rs b/esp32c3/src/dma/out_push_ch0.rs index 96107cecd8..7f8a770c68 100644 --- a/esp32c3/src/dma/out_push_ch0.rs +++ b/esp32c3/src/dma/out_push_ch0.rs @@ -34,38 +34,37 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTFIFO_WDATA_CH0` reader - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH0_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_WDATA_CH0` writer - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH0_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_WDATA` reader - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA` writer - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PUSH_CH0_SPEC, u16, u16, 9, O>; -#[doc = "Field `OUTFIFO_PUSH_CH0` reader - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH0_R = crate::BitReader; -#[doc = "Field `OUTFIFO_PUSH_CH0` writer - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_PUSH_CH0_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_PUSH` reader - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH` writer - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_PUSH_CH0_SPEC, bool, O>; impl R { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch0(&self) -> OUTFIFO_WDATA_CH0_R { - OUTFIFO_WDATA_CH0_R::new((self.bits & 0x01ff) as u16) + pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R { + OUTFIFO_WDATA_R::new((self.bits & 0x01ff) as u16) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch0(&self) -> OUTFIFO_PUSH_CH0_R { - OUTFIFO_PUSH_CH0_R::new(((self.bits >> 9) & 1) != 0) + pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R { + OUTFIFO_PUSH_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch0(&mut self) -> OUTFIFO_WDATA_CH0_W<0> { - OUTFIFO_WDATA_CH0_W::new(self) + pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<0> { + OUTFIFO_WDATA_W::new(self) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch0(&mut self) -> OUTFIFO_PUSH_CH0_W<9> { - OUTFIFO_PUSH_CH0_W::new(self) + pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<9> { + OUTFIFO_PUSH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_push_ch1.rs b/esp32c3/src/dma/out_push_ch1.rs index 145edaabc4..bcd3fd73ad 100644 --- a/esp32c3/src/dma/out_push_ch1.rs +++ b/esp32c3/src/dma/out_push_ch1.rs @@ -34,38 +34,37 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTFIFO_WDATA_CH1` reader - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH1_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_WDATA_CH1` writer - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH1_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_WDATA` reader - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA` writer - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PUSH_CH1_SPEC, u16, u16, 9, O>; -#[doc = "Field `OUTFIFO_PUSH_CH1` reader - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH1_R = crate::BitReader; -#[doc = "Field `OUTFIFO_PUSH_CH1` writer - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_PUSH_CH1_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_PUSH` reader - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH` writer - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_PUSH_CH1_SPEC, bool, O>; impl R { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch1(&self) -> OUTFIFO_WDATA_CH1_R { - OUTFIFO_WDATA_CH1_R::new((self.bits & 0x01ff) as u16) + pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R { + OUTFIFO_WDATA_R::new((self.bits & 0x01ff) as u16) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch1(&self) -> OUTFIFO_PUSH_CH1_R { - OUTFIFO_PUSH_CH1_R::new(((self.bits >> 9) & 1) != 0) + pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R { + OUTFIFO_PUSH_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch1(&mut self) -> OUTFIFO_WDATA_CH1_W<0> { - OUTFIFO_WDATA_CH1_W::new(self) + pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<0> { + OUTFIFO_WDATA_W::new(self) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch1(&mut self) -> OUTFIFO_PUSH_CH1_W<9> { - OUTFIFO_PUSH_CH1_W::new(self) + pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<9> { + OUTFIFO_PUSH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_push_ch2.rs b/esp32c3/src/dma/out_push_ch2.rs index 0848e8e9fc..319e436557 100644 --- a/esp32c3/src/dma/out_push_ch2.rs +++ b/esp32c3/src/dma/out_push_ch2.rs @@ -34,38 +34,37 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTFIFO_WDATA_CH2` reader - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH2_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_WDATA_CH2` writer - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH2_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_WDATA` reader - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA` writer - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PUSH_CH2_SPEC, u16, u16, 9, O>; -#[doc = "Field `OUTFIFO_PUSH_CH2` reader - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH2_R = crate::BitReader; -#[doc = "Field `OUTFIFO_PUSH_CH2` writer - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_PUSH_CH2_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_PUSH` reader - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH` writer - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_PUSH_CH2_SPEC, bool, O>; impl R { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch2(&self) -> OUTFIFO_WDATA_CH2_R { - OUTFIFO_WDATA_CH2_R::new((self.bits & 0x01ff) as u16) + pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R { + OUTFIFO_WDATA_R::new((self.bits & 0x01ff) as u16) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch2(&self) -> OUTFIFO_PUSH_CH2_R { - OUTFIFO_PUSH_CH2_R::new(((self.bits >> 9) & 1) != 0) + pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R { + OUTFIFO_PUSH_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch2(&mut self) -> OUTFIFO_WDATA_CH2_W<0> { - OUTFIFO_WDATA_CH2_W::new(self) + pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<0> { + OUTFIFO_WDATA_W::new(self) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch2(&mut self) -> OUTFIFO_PUSH_CH2_W<9> { - OUTFIFO_PUSH_CH2_W::new(self) + pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<9> { + OUTFIFO_PUSH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32c3/src/dma/out_state_ch0.rs b/esp32c3/src/dma/out_state_ch0.rs index df67af9dc4..08e4f5cd83 100644 --- a/esp32c3/src/dma/out_state_ch0.rs +++ b/esp32c3/src/dma/out_state_ch0.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_ADDR_CH0` reader - This register stores the current outlink descriptor's address."] -pub type OUTLINK_DSCR_ADDR_CH0_R = crate::FieldReader; -#[doc = "Field `OUT_DSCR_STATE_CH0` reader - reserved"] -pub type OUT_DSCR_STATE_CH0_R = crate::FieldReader; -#[doc = "Field `OUT_STATE_CH0` reader - reserved"] -pub type OUT_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - reserved"] +pub type OUT_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] #[inline(always)] - pub fn outlink_dscr_addr_ch0(&self) -> OUTLINK_DSCR_ADDR_CH0_R { - OUTLINK_DSCR_ADDR_CH0_R::new((self.bits & 0x0003_ffff) as u32) + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn out_dscr_state_ch0(&self) -> OUT_DSCR_STATE_CH0_R { - OUT_DSCR_STATE_CH0_R::new(((self.bits >> 18) & 3) as u8) + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn out_state_ch0(&self) -> OUT_STATE_CH0_R { - OUT_STATE_CH0_R::new(((self.bits >> 20) & 7) as u8) + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_OUT_STATE_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_state_ch0](index.html) module"] diff --git a/esp32c3/src/dma/out_state_ch1.rs b/esp32c3/src/dma/out_state_ch1.rs index e7ee9f8cd6..8b04dbc172 100644 --- a/esp32c3/src/dma/out_state_ch1.rs +++ b/esp32c3/src/dma/out_state_ch1.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_ADDR_CH1` reader - This register stores the current outlink descriptor's address."] -pub type OUTLINK_DSCR_ADDR_CH1_R = crate::FieldReader; -#[doc = "Field `OUT_DSCR_STATE_CH1` reader - reserved"] -pub type OUT_DSCR_STATE_CH1_R = crate::FieldReader; -#[doc = "Field `OUT_STATE_CH1` reader - reserved"] -pub type OUT_STATE_CH1_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - reserved"] +pub type OUT_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] #[inline(always)] - pub fn outlink_dscr_addr_ch1(&self) -> OUTLINK_DSCR_ADDR_CH1_R { - OUTLINK_DSCR_ADDR_CH1_R::new((self.bits & 0x0003_ffff) as u32) + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn out_dscr_state_ch1(&self) -> OUT_DSCR_STATE_CH1_R { - OUT_DSCR_STATE_CH1_R::new(((self.bits >> 18) & 3) as u8) + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn out_state_ch1(&self) -> OUT_STATE_CH1_R { - OUT_STATE_CH1_R::new(((self.bits >> 20) & 7) as u8) + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_OUT_STATE_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_state_ch1](index.html) module"] diff --git a/esp32c3/src/dma/out_state_ch2.rs b/esp32c3/src/dma/out_state_ch2.rs index 07f74bbb9b..712ba721a0 100644 --- a/esp32c3/src/dma/out_state_ch2.rs +++ b/esp32c3/src/dma/out_state_ch2.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_ADDR_CH2` reader - This register stores the current outlink descriptor's address."] -pub type OUTLINK_DSCR_ADDR_CH2_R = crate::FieldReader; -#[doc = "Field `OUT_DSCR_STATE_CH2` reader - reserved"] -pub type OUT_DSCR_STATE_CH2_R = crate::FieldReader; -#[doc = "Field `OUT_STATE_CH2` reader - reserved"] -pub type OUT_STATE_CH2_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - reserved"] +pub type OUT_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] #[inline(always)] - pub fn outlink_dscr_addr_ch2(&self) -> OUTLINK_DSCR_ADDR_CH2_R { - OUTLINK_DSCR_ADDR_CH2_R::new((self.bits & 0x0003_ffff) as u32) + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn out_dscr_state_ch2(&self) -> OUT_DSCR_STATE_CH2_R { - OUT_DSCR_STATE_CH2_R::new(((self.bits >> 18) & 3) as u8) + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn out_state_ch2(&self) -> OUT_STATE_CH2_R { - OUT_STATE_CH2_R::new(((self.bits >> 20) & 7) as u8) + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "DMA_OUT_STATE_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_state_ch2](index.html) module"] diff --git a/esp32c3/src/dma/outfifo_status_ch0.rs b/esp32c3/src/dma/outfifo_status_ch0.rs index d931c12860..2447d03de1 100644 --- a/esp32c3/src/dma/outfifo_status_ch0.rs +++ b/esp32c3/src/dma/outfifo_status_ch0.rs @@ -13,55 +13,55 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTFIFO_FULL_CH0` reader - L1 Tx FIFO full signal for Tx channel 0."] -pub type OUTFIFO_FULL_CH0_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_CH0` reader - L1 Tx FIFO empty signal for Tx channel 0."] -pub type OUTFIFO_EMPTY_CH0_R = crate::BitReader; -#[doc = "Field `OUTFIFO_CNT_CH0` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] -pub type OUTFIFO_CNT_CH0_R = crate::FieldReader; -#[doc = "Field `OUT_REMAIN_UNDER_1B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_1B_CH0_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_2B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_2B_CH0_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_3B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_3B_CH0_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_4B_CH0` reader - reserved"] -pub type OUT_REMAIN_UNDER_4B_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL` reader - L1 Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY` reader - L1 Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_full_ch0(&self) -> OUTFIFO_FULL_CH0_R { - OUTFIFO_FULL_CH0_R::new((self.bits & 1) != 0) + pub fn outfifo_full(&self) -> OUTFIFO_FULL_R { + OUTFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_empty_ch0(&self) -> OUTFIFO_EMPTY_CH0_R { - OUTFIFO_EMPTY_CH0_R::new(((self.bits >> 1) & 1) != 0) + pub fn outfifo_empty(&self) -> OUTFIFO_EMPTY_R { + OUTFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] #[inline(always)] - pub fn outfifo_cnt_ch0(&self) -> OUTFIFO_CNT_CH0_R { - OUTFIFO_CNT_CH0_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn outfifo_cnt(&self) -> OUTFIFO_CNT_R { + OUTFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn out_remain_under_1b_ch0(&self) -> OUT_REMAIN_UNDER_1B_CH0_R { - OUT_REMAIN_UNDER_1B_CH0_R::new(((self.bits >> 23) & 1) != 0) + pub fn out_remain_under_1b(&self) -> OUT_REMAIN_UNDER_1B_R { + OUT_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn out_remain_under_2b_ch0(&self) -> OUT_REMAIN_UNDER_2B_CH0_R { - OUT_REMAIN_UNDER_2B_CH0_R::new(((self.bits >> 24) & 1) != 0) + pub fn out_remain_under_2b(&self) -> OUT_REMAIN_UNDER_2B_R { + OUT_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn out_remain_under_3b_ch0(&self) -> OUT_REMAIN_UNDER_3B_CH0_R { - OUT_REMAIN_UNDER_3B_CH0_R::new(((self.bits >> 25) & 1) != 0) + pub fn out_remain_under_3b(&self) -> OUT_REMAIN_UNDER_3B_R { + OUT_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn out_remain_under_4b_ch0(&self) -> OUT_REMAIN_UNDER_4B_CH0_R { - OUT_REMAIN_UNDER_4B_CH0_R::new(((self.bits >> 26) & 1) != 0) + pub fn out_remain_under_4b(&self) -> OUT_REMAIN_UNDER_4B_R { + OUT_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } } #[doc = "DMA_OUTFIFO_STATUS_CH0_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outfifo_status_ch0](index.html) module"] diff --git a/esp32c3/src/dma/outfifo_status_ch1.rs b/esp32c3/src/dma/outfifo_status_ch1.rs index 29dd299d1c..b6b8ce54f9 100644 --- a/esp32c3/src/dma/outfifo_status_ch1.rs +++ b/esp32c3/src/dma/outfifo_status_ch1.rs @@ -13,55 +13,55 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTFIFO_FULL_CH1` reader - L1 Tx FIFO full signal for Tx channel 1."] -pub type OUTFIFO_FULL_CH1_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_CH1` reader - L1 Tx FIFO empty signal for Tx channel 1."] -pub type OUTFIFO_EMPTY_CH1_R = crate::BitReader; -#[doc = "Field `OUTFIFO_CNT_CH1` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1."] -pub type OUTFIFO_CNT_CH1_R = crate::FieldReader; -#[doc = "Field `OUT_REMAIN_UNDER_1B_CH1` reader - reserved"] -pub type OUT_REMAIN_UNDER_1B_CH1_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_2B_CH1` reader - reserved"] -pub type OUT_REMAIN_UNDER_2B_CH1_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_3B_CH1` reader - reserved"] -pub type OUT_REMAIN_UNDER_3B_CH1_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_4B_CH1` reader - reserved"] -pub type OUT_REMAIN_UNDER_4B_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL` reader - L1 Tx FIFO full signal for Tx channel 1."] +pub type OUTFIFO_FULL_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY` reader - L1 Tx FIFO empty signal for Tx channel 1."] +pub type OUTFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1."] +pub type OUTFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 1."] #[inline(always)] - pub fn outfifo_full_ch1(&self) -> OUTFIFO_FULL_CH1_R { - OUTFIFO_FULL_CH1_R::new((self.bits & 1) != 0) + pub fn outfifo_full(&self) -> OUTFIFO_FULL_R { + OUTFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 1."] #[inline(always)] - pub fn outfifo_empty_ch1(&self) -> OUTFIFO_EMPTY_CH1_R { - OUTFIFO_EMPTY_CH1_R::new(((self.bits >> 1) & 1) != 0) + pub fn outfifo_empty(&self) -> OUTFIFO_EMPTY_R { + OUTFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1."] #[inline(always)] - pub fn outfifo_cnt_ch1(&self) -> OUTFIFO_CNT_CH1_R { - OUTFIFO_CNT_CH1_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn outfifo_cnt(&self) -> OUTFIFO_CNT_R { + OUTFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn out_remain_under_1b_ch1(&self) -> OUT_REMAIN_UNDER_1B_CH1_R { - OUT_REMAIN_UNDER_1B_CH1_R::new(((self.bits >> 23) & 1) != 0) + pub fn out_remain_under_1b(&self) -> OUT_REMAIN_UNDER_1B_R { + OUT_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn out_remain_under_2b_ch1(&self) -> OUT_REMAIN_UNDER_2B_CH1_R { - OUT_REMAIN_UNDER_2B_CH1_R::new(((self.bits >> 24) & 1) != 0) + pub fn out_remain_under_2b(&self) -> OUT_REMAIN_UNDER_2B_R { + OUT_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn out_remain_under_3b_ch1(&self) -> OUT_REMAIN_UNDER_3B_CH1_R { - OUT_REMAIN_UNDER_3B_CH1_R::new(((self.bits >> 25) & 1) != 0) + pub fn out_remain_under_3b(&self) -> OUT_REMAIN_UNDER_3B_R { + OUT_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn out_remain_under_4b_ch1(&self) -> OUT_REMAIN_UNDER_4B_CH1_R { - OUT_REMAIN_UNDER_4B_CH1_R::new(((self.bits >> 26) & 1) != 0) + pub fn out_remain_under_4b(&self) -> OUT_REMAIN_UNDER_4B_R { + OUT_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } } #[doc = "DMA_OUTFIFO_STATUS_CH1_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outfifo_status_ch1](index.html) module"] diff --git a/esp32c3/src/dma/outfifo_status_ch2.rs b/esp32c3/src/dma/outfifo_status_ch2.rs index 52f9bd372f..85741ee049 100644 --- a/esp32c3/src/dma/outfifo_status_ch2.rs +++ b/esp32c3/src/dma/outfifo_status_ch2.rs @@ -13,55 +13,55 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTFIFO_FULL_CH2` reader - L1 Tx FIFO full signal for Tx channel 2."] -pub type OUTFIFO_FULL_CH2_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_CH2` reader - L1 Tx FIFO empty signal for Tx channel 2."] -pub type OUTFIFO_EMPTY_CH2_R = crate::BitReader; -#[doc = "Field `OUTFIFO_CNT_CH2` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2."] -pub type OUTFIFO_CNT_CH2_R = crate::FieldReader; -#[doc = "Field `OUT_REMAIN_UNDER_1B_CH2` reader - reserved"] -pub type OUT_REMAIN_UNDER_1B_CH2_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_2B_CH2` reader - reserved"] -pub type OUT_REMAIN_UNDER_2B_CH2_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_3B_CH2` reader - reserved"] -pub type OUT_REMAIN_UNDER_3B_CH2_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_4B_CH2` reader - reserved"] -pub type OUT_REMAIN_UNDER_4B_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL` reader - L1 Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY` reader - L1 Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 2."] #[inline(always)] - pub fn outfifo_full_ch2(&self) -> OUTFIFO_FULL_CH2_R { - OUTFIFO_FULL_CH2_R::new((self.bits & 1) != 0) + pub fn outfifo_full(&self) -> OUTFIFO_FULL_R { + OUTFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 2."] #[inline(always)] - pub fn outfifo_empty_ch2(&self) -> OUTFIFO_EMPTY_CH2_R { - OUTFIFO_EMPTY_CH2_R::new(((self.bits >> 1) & 1) != 0) + pub fn outfifo_empty(&self) -> OUTFIFO_EMPTY_R { + OUTFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bits 2:7 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2."] #[inline(always)] - pub fn outfifo_cnt_ch2(&self) -> OUTFIFO_CNT_CH2_R { - OUTFIFO_CNT_CH2_R::new(((self.bits >> 2) & 0x3f) as u8) + pub fn outfifo_cnt(&self) -> OUTFIFO_CNT_R { + OUTFIFO_CNT_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn out_remain_under_1b_ch2(&self) -> OUT_REMAIN_UNDER_1B_CH2_R { - OUT_REMAIN_UNDER_1B_CH2_R::new(((self.bits >> 23) & 1) != 0) + pub fn out_remain_under_1b(&self) -> OUT_REMAIN_UNDER_1B_R { + OUT_REMAIN_UNDER_1B_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn out_remain_under_2b_ch2(&self) -> OUT_REMAIN_UNDER_2B_CH2_R { - OUT_REMAIN_UNDER_2B_CH2_R::new(((self.bits >> 24) & 1) != 0) + pub fn out_remain_under_2b(&self) -> OUT_REMAIN_UNDER_2B_R { + OUT_REMAIN_UNDER_2B_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn out_remain_under_3b_ch2(&self) -> OUT_REMAIN_UNDER_3B_CH2_R { - OUT_REMAIN_UNDER_3B_CH2_R::new(((self.bits >> 25) & 1) != 0) + pub fn out_remain_under_3b(&self) -> OUT_REMAIN_UNDER_3B_R { + OUT_REMAIN_UNDER_3B_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn out_remain_under_4b_ch2(&self) -> OUT_REMAIN_UNDER_4B_CH2_R { - OUT_REMAIN_UNDER_4B_CH2_R::new(((self.bits >> 26) & 1) != 0) + pub fn out_remain_under_4b(&self) -> OUT_REMAIN_UNDER_4B_R { + OUT_REMAIN_UNDER_4B_R::new(((self.bits >> 26) & 1) != 0) } } #[doc = "DMA_OUTFIFO_STATUS_CH2_REG.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outfifo_status_ch2](index.html) module"] diff --git a/esp32c3/svd/esp32c3.base.svd b/esp32c3/svd/esp32c3.base.svd index eec0704ab2..532b90bd66 100644 --- a/esp32c3/svd/esp32c3.base.svd +++ b/esp32c3/svd/esp32c3.base.svd @@ -4,7 +4,7 @@ ESPRESSIF ESP32-C3 ESP32-C3 - 9 + 10 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) Copyright 2022 Espressif Systems (Shanghai) PTE LTD @@ -3385,91 +3385,91 @@ 0x20 - IN_DONE_CH0_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 read-only - IN_SUC_EOF_CH0_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-only - IN_ERR_EOF_CH0_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 read-only - OUT_DONE_CH0_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 read-only - OUT_EOF_CH0_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 read-only - IN_DSCR_ERR_CH0_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 read-only - INFIFO_OVF_CH0_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 read-only - INFIFO_UDF_CH0_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 read-only - OUTFIFO_OVF_CH0_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 read-only - OUTFIFO_UDF_CH0_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 @@ -3484,91 +3484,91 @@ 0x20 - IN_DONE_CH0_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH0_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH0_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH0_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH0_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH0_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH0_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH0_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH0_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH0_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3583,91 +3583,91 @@ 0x20 - IN_DONE_CH0_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH0_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH0_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH0_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH0_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH0_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH0_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH0_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH0_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH0_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH0_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH0_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH0_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3682,91 +3682,91 @@ 0x20 - IN_DONE_CH0_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH0_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH0_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH0_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH0_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH0_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH0_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH0_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH0_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH0_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH0_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH0_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH0_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3781,91 +3781,91 @@ 0x20 - IN_DONE_CH1_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. 0 1 read-only - IN_SUC_EOF_CH1_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. 1 1 read-only - IN_ERR_EOF_CH1_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved. 2 1 read-only - OUT_DONE_CH1_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1. 3 1 read-only - OUT_EOF_CH1_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1. 4 1 read-only - IN_DSCR_ERR_CH1_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. 5 1 read-only - OUT_DSCR_ERR_CH1_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1. 6 1 read-only - IN_DSCR_EMPTY_CH1_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1. 7 1 read-only - OUT_TOTAL_EOF_CH1_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1. 8 1 read-only - INFIFO_OVF_CH1_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow. 9 1 read-only - INFIFO_UDF_CH1_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow. 10 1 read-only - OUTFIFO_OVF_CH1_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow. 11 1 read-only - OUTFIFO_UDF_CH1_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow. 12 1 @@ -3880,91 +3880,91 @@ 0x20 - IN_DONE_CH1_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH1_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH1_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH1_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH1_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH1_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH1_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH1_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH1_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH1_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH1_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH1_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH1_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3979,91 +3979,91 @@ 0x20 - IN_DONE_CH1_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH1_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH1_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH1_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH1_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH1_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH1_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH1_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH1_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH1_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH1_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH1_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH1_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4078,91 +4078,91 @@ 0x20 - IN_DONE_CH1_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH1_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH1_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH1_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH1_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH1_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH1_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH1_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH1_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH1_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH1_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH1_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH1_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4177,91 +4177,91 @@ 0x20 - IN_DONE_CH2_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. 0 1 read-only - IN_SUC_EOF_CH2_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2. 1 1 read-only - IN_ERR_EOF_CH2_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved. 2 1 read-only - OUT_DONE_CH2_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2. 3 1 read-only - OUT_EOF_CH2_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2. 4 1 read-only - IN_DSCR_ERR_CH2_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2. 5 1 read-only - OUT_DSCR_ERR_CH2_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2. 6 1 read-only - IN_DSCR_EMPTY_CH2_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2. 7 1 read-only - OUT_TOTAL_EOF_CH2_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2. 8 1 read-only - INFIFO_OVF_CH2_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow. 9 1 read-only - INFIFO_UDF_CH2_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow. 10 1 read-only - OUTFIFO_OVF_CH2_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow. 11 1 read-only - OUTFIFO_UDF_CH2_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow. 12 1 @@ -4276,91 +4276,91 @@ 0x20 - IN_DONE_CH2_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH2_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH2_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH2_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH2_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH2_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH2_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH2_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH2_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH2_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH2_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH2_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH2_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4375,91 +4375,91 @@ 0x20 - IN_DONE_CH2_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH2_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH2_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH2_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH2_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH2_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH2_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH2_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH2_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH2_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH2_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH2_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH2_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4474,91 +4474,91 @@ 0x20 - IN_DONE_CH2_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH2_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH2_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH2_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH2_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH2_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH2_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH2_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH2_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH2_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH2_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH2_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH2_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4640,35 +4640,35 @@ 0x20 - IN_RST_CH0 + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH0 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH0 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH0 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH0 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -4683,7 +4683,7 @@ 0x20 - IN_CHECK_OWNER_CH0 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -4699,56 +4699,56 @@ 0x07800003 - INFIFO_FULL_CH0 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_CH0 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_CNT_CH0 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only - IN_REMAIN_UNDER_1B_CH0 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH0 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH0 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH0 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH0 + IN_BUF_HUNGRY reserved 27 1 @@ -4764,14 +4764,14 @@ 0x00000800 - INFIFO_RDATA_CH0 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH0 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -4787,42 +4787,42 @@ 0x01100000 - INLINK_ADDR_CH0 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH0 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH0 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH0 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH0 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH0 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -4837,21 +4837,21 @@ 0x20 - INLINK_DSCR_ADDR_CH0 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH0 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH0 + IN_STATE reserved 20 3 @@ -4866,7 +4866,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH0 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -4881,7 +4881,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH0 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -4896,7 +4896,7 @@ 0x20 - INLINK_DSCR_CH0 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -4911,7 +4911,7 @@ 0x20 - INLINK_DSCR_BF0_CH0 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -4926,7 +4926,7 @@ 0x20 - INLINK_DSCR_BF1_CH0 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -4941,7 +4941,7 @@ 0x20 - RX_PRI_CH0 + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -4957,7 +4957,7 @@ 0x0000003F - PERI_IN_SEL_CH0 + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -4973,42 +4973,42 @@ 0x00000008 - OUT_RST_CH0 + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH0 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH0 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH0 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH0 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH0 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -5023,7 +5023,7 @@ 0x20 - OUT_CHECK_OWNER_CH0 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5039,49 +5039,49 @@ 0x07800002 - OUTFIFO_FULL_CH0 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_CH0 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_CNT_CH0 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH0 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH0 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH0 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH0 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -5096,14 +5096,14 @@ 0x20 - OUTFIFO_WDATA_CH0 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH0 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5119,35 +5119,35 @@ 0x00800000 - OUTLINK_ADDR_CH0 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH0 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH0 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH0 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH0 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -5162,21 +5162,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH0 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH0 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH0 + OUT_STATE reserved 20 3 @@ -5191,7 +5191,7 @@ 0x20 - OUT_EOF_DES_ADDR_CH0 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5206,7 +5206,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH0 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5221,7 +5221,7 @@ 0x20 - OUTLINK_DSCR_CH0 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5236,7 +5236,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH0 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5251,7 +5251,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH0 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5266,7 +5266,7 @@ 0x20 - TX_PRI_CH0 + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5282,7 +5282,7 @@ 0x0000003F - PERI_OUT_SEL_CH0 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -5297,35 +5297,35 @@ 0x20 - IN_RST_CH1 + IN_RST This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH1 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH1 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH1 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH1 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -5340,7 +5340,7 @@ 0x20 - IN_CHECK_OWNER_CH1 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5356,56 +5356,56 @@ 0x07800003 - INFIFO_FULL_CH1 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 1. 0 1 read-only - INFIFO_EMPTY_CH1 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 1. 1 1 read-only - INFIFO_CNT_CH1 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. 2 6 read-only - IN_REMAIN_UNDER_1B_CH1 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH1 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH1 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH1 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH1 + IN_BUF_HUNGRY reserved 27 1 @@ -5421,14 +5421,14 @@ 0x00000800 - INFIFO_RDATA_CH1 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH1 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -5444,42 +5444,42 @@ 0x01100000 - INLINK_ADDR_CH1 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH1 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH1 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH1 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH1 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH1 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -5494,21 +5494,21 @@ 0x20 - INLINK_DSCR_ADDR_CH1 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH1 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH1 + IN_STATE reserved 20 3 @@ -5523,7 +5523,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH1 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5538,7 +5538,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH1 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -5553,7 +5553,7 @@ 0x20 - INLINK_DSCR_CH1 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -5568,7 +5568,7 @@ 0x20 - INLINK_DSCR_BF0_CH1 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -5583,7 +5583,7 @@ 0x20 - INLINK_DSCR_BF1_CH1 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5598,7 +5598,7 @@ 0x20 - RX_PRI_CH1 + RX_PRI The priority of Rx channel 1. The larger of the value, the higher of the priority. 0 4 @@ -5614,7 +5614,7 @@ 0x0000003F - PERI_IN_SEL_CH1 + PERI_IN_SEL This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -5630,42 +5630,42 @@ 0x00000008 - OUT_RST_CH1 + OUT_RST This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH1 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH1 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH1 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH1 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH1 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. 5 1 @@ -5680,7 +5680,7 @@ 0x20 - OUT_CHECK_OWNER_CH1 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5696,49 +5696,49 @@ 0x07800002 - OUTFIFO_FULL_CH1 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 1. 0 1 read-only - OUTFIFO_EMPTY_CH1 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 1. 1 1 read-only - OUTFIFO_CNT_CH1 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH1 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH1 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH1 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH1 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -5753,14 +5753,14 @@ 0x20 - OUTFIFO_WDATA_CH1 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH1 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5776,35 +5776,35 @@ 0x00800000 - OUTLINK_ADDR_CH1 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH1 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH1 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH1 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH1 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -5819,21 +5819,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH1 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH1 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH1 + OUT_STATE reserved 20 3 @@ -5848,7 +5848,7 @@ 0x20 - OUT_EOF_DES_ADDR_CH1 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5863,7 +5863,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH1 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5878,7 +5878,7 @@ 0x20 - OUTLINK_DSCR_CH1 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5893,7 +5893,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH1 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5908,7 +5908,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH1 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5923,7 +5923,7 @@ 0x20 - TX_PRI_CH1 + TX_PRI The priority of Tx channel 1. The larger of the value, the higher of the priority. 0 4 @@ -5939,7 +5939,7 @@ 0x0000003F - PERI_OUT_SEL_CH1 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -5954,35 +5954,35 @@ 0x20 - IN_RST_CH2 + IN_RST This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH2 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH2 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH2 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH2 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -5997,7 +5997,7 @@ 0x20 - IN_CHECK_OWNER_CH2 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -6013,56 +6013,56 @@ 0x07800003 - INFIFO_FULL_CH2 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 2. 0 1 read-only - INFIFO_EMPTY_CH2 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 2. 1 1 read-only - INFIFO_CNT_CH2 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. 2 6 read-only - IN_REMAIN_UNDER_1B_CH2 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH2 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH2 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH2 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH2 + IN_BUF_HUNGRY reserved 27 1 @@ -6078,14 +6078,14 @@ 0x00000800 - INFIFO_RDATA_CH2 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH2 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -6101,42 +6101,42 @@ 0x01100000 - INLINK_ADDR_CH2 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH2 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH2 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH2 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH2 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH2 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -6151,21 +6151,21 @@ 0x20 - INLINK_DSCR_ADDR_CH2 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH2 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH2 + IN_STATE reserved 20 3 @@ -6180,7 +6180,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH2 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -6195,7 +6195,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH2 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -6210,7 +6210,7 @@ 0x20 - INLINK_DSCR_CH2 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -6225,7 +6225,7 @@ 0x20 - INLINK_DSCR_BF0_CH2 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -6240,7 +6240,7 @@ 0x20 - INLINK_DSCR_BF1_CH2 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -6255,7 +6255,7 @@ 0x20 - RX_PRI_CH2 + RX_PRI The priority of Rx channel 2. The larger of the value, the higher of the priority. 0 4 @@ -6271,7 +6271,7 @@ 0x0000003F - PERI_IN_SEL_CH2 + PERI_IN_SEL This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -6287,42 +6287,42 @@ 0x00000008 - OUT_RST_CH2 + OUT_RST This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH2 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH2 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH2 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH2 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH2 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM. 5 1 @@ -6337,7 +6337,7 @@ 0x20 - OUT_CHECK_OWNER_CH2 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -6353,49 +6353,49 @@ 0x07800002 - OUTFIFO_FULL_CH2 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 2. 0 1 read-only - OUTFIFO_EMPTY_CH2 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 2. 1 1 read-only - OUTFIFO_CNT_CH2 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH2 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH2 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH2 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH2 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -6410,14 +6410,14 @@ 0x20 - OUTFIFO_WDATA_CH2 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH2 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -6433,35 +6433,35 @@ 0x00800000 - OUTLINK_ADDR_CH2 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH2 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH2 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH2 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH2 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -6476,21 +6476,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH2 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH2 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH2 + OUT_STATE reserved 20 3 @@ -6505,7 +6505,7 @@ 0x20 - OUT_EOF_DES_ADDR_CH2 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -6520,7 +6520,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH2 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -6535,7 +6535,7 @@ 0x20 - OUTLINK_DSCR_CH2 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -6550,7 +6550,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH2 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -6565,7 +6565,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH2 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -6580,7 +6580,7 @@ 0x20 - TX_PRI_CH2 + TX_PRI The priority of Tx channel 2. The larger of the value, the higher of the priority. 0 4 @@ -6596,7 +6596,7 @@ 0x0000003F - PERI_OUT_SEL_CH2 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -32025,12 +32025,14 @@ Baud Rate Prescaler, determines the frequency dividing ratio. 0 14 + read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 + read-write @@ -32045,18 +32047,21 @@ The width of PBS1. 0 4 + read-write TIME_SEG2 The width of PBS2. 4 3 + read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 + read-write @@ -32116,6 +32121,7 @@ Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 + read-write @@ -32130,6 +32136,7 @@ The RX error counter register, reflects value changes under reception status. 0 8 + read-write @@ -32144,6 +32151,7 @@ The TX error counter register, reflects value changes under transmission status. 0 8 + read-write @@ -32375,6 +32383,7 @@ This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 + read-write From e45a2dd62b3b941f1fe99aaa37b88ca6c460b781 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 3 Nov 2022 10:54:28 -0700 Subject: [PATCH 3/4] Add new SVD for ESP32-S3 and regenerate --- esp32s3/src/dma/in_conf0_ch.rs | 82 +++--- esp32s3/src/dma/in_conf1_ch.rs | 49 ++-- esp32s3/src/dma/in_dscr_bf0_ch.rs | 8 +- esp32s3/src/dma/in_dscr_bf1_ch.rs | 8 +- esp32s3/src/dma/in_dscr_ch.rs | 8 +- esp32s3/src/dma/in_err_eof_des_addr_ch.rs | 8 +- esp32s3/src/dma/in_int_clr_ch.rs | 89 +++--- esp32s3/src/dma/in_int_ena_ch.rs | 170 ++++++----- esp32s3/src/dma/in_int_raw_ch.rs | 80 +++--- esp32s3/src/dma/in_int_st_ch.rs | 80 +++--- esp32s3/src/dma/in_link_ch.rs | 89 +++--- esp32s3/src/dma/in_peri_sel_ch.rs | 16 +- esp32s3/src/dma/in_pop_ch.rs | 24 +- esp32s3/src/dma/in_pri_ch.rs | 16 +- esp32s3/src/dma/in_sram_size_ch.rs | 16 +- esp32s3/src/dma/in_state_ch.rs | 24 +- esp32s3/src/dma/in_suc_eof_des_addr_ch.rs | 8 +- esp32s3/src/dma/in_wight_ch.rs | 17 +- esp32s3/src/dma/infifo_status_ch.rs | 112 ++++---- esp32s3/src/dma/out_conf0_ch.rs | 98 ++++--- esp32s3/src/dma/out_conf1_ch.rs | 33 ++- esp32s3/src/dma/out_dscr_bf0_ch.rs | 8 +- esp32s3/src/dma/out_dscr_bf1_ch.rs | 8 +- esp32s3/src/dma/out_dscr_ch.rs | 8 +- esp32s3/src/dma/out_eof_bfr_des_addr_ch.rs | 8 +- esp32s3/src/dma/out_eof_des_addr_ch.rs | 8 +- esp32s3/src/dma/out_int_clr_ch.rs | 68 +++-- esp32s3/src/dma/out_int_ena_ch.rs | 132 +++++---- esp32s3/src/dma/out_int_raw_ch.rs | 64 ++--- esp32s3/src/dma/out_int_st_ch.rs | 64 ++--- esp32s3/src/dma/out_link_ch.rs | 73 +++-- esp32s3/src/dma/out_peri_sel_ch.rs | 16 +- esp32s3/src/dma/out_pri_ch.rs | 16 +- esp32s3/src/dma/out_push_ch.rs | 32 +-- esp32s3/src/dma/out_sram_size_ch.rs | 16 +- esp32s3/src/dma/out_state_ch.rs | 24 +- esp32s3/src/dma/out_wight_ch.rs | 16 +- esp32s3/src/dma/outfifo_status_ch.rs | 104 +++---- esp32s3/svd/esp32s3.base.svd | 310 ++++++++++----------- 39 files changed, 987 insertions(+), 1023 deletions(-) diff --git a/esp32s3/src/dma/in_conf0_ch.rs b/esp32s3/src/dma/in_conf0_ch.rs index bdd35387de..d3d02b186a 100644 --- a/esp32s3/src/dma/in_conf0_ch.rs +++ b/esp32s3/src/dma/in_conf0_ch.rs @@ -34,80 +34,78 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_RST_CH` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH_R = crate::BitReader; -#[doc = "Field `IN_RST_CH` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] -pub type IN_RST_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `IN_LOOP_TEST_CH` reader - reserved"] -pub type IN_LOOP_TEST_CH_R = crate::BitReader; -#[doc = "Field `IN_LOOP_TEST_CH` writer - reserved"] -pub type IN_LOOP_TEST_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `INDSCR_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH_R = crate::BitReader; -#[doc = "Field `INDSCR_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] -pub type INDSCR_BURST_EN_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `IN_DATA_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH_R = crate::BitReader; -#[doc = "Field `IN_DATA_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] -pub type IN_DATA_BURST_EN_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `MEM_TRANS_EN_CH` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH_R = crate::BitReader; -#[doc = "Field `MEM_TRANS_EN_CH` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] -pub type MEM_TRANS_EN_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `IN_LOOP_TEST` reader - reserved"] +pub type IN_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST` writer - reserved"] +pub type IN_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] +pub type IN_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF0_CH_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch(&self) -> IN_RST_CH_R { - IN_RST_CH_R::new((self.bits & 1) != 0) + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch(&self) -> IN_LOOP_TEST_CH_R { - IN_LOOP_TEST_CH_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_loop_test(&self) -> IN_LOOP_TEST_R { + IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch(&self) -> INDSCR_BURST_EN_CH_R { - INDSCR_BURST_EN_CH_R::new(((self.bits >> 2) & 1) != 0) + pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R { + INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch(&self) -> IN_DATA_BURST_EN_CH_R { - IN_DATA_BURST_EN_CH_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R { + IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch(&self) -> MEM_TRANS_EN_CH_R { - MEM_TRANS_EN_CH_R::new(((self.bits >> 4) & 1) != 0) + pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R { + MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."] #[inline(always)] - pub fn in_rst_ch(&mut self) -> IN_RST_CH_W<0> { - IN_RST_CH_W::new(self) + pub fn in_rst(&mut self) -> IN_RST_W<0> { + IN_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn in_loop_test_ch(&mut self) -> IN_LOOP_TEST_CH_W<1> { - IN_LOOP_TEST_CH_W::new(self) + pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<1> { + IN_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn indscr_burst_en_ch(&mut self) -> INDSCR_BURST_EN_CH_W<2> { - INDSCR_BURST_EN_CH_W::new(self) + pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<2> { + INDSCR_BURST_EN_W::new(self) } #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."] #[inline(always)] - pub fn in_data_burst_en_ch(&mut self) -> IN_DATA_BURST_EN_CH_W<3> { - IN_DATA_BURST_EN_CH_W::new(self) + pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<3> { + IN_DATA_BURST_EN_W::new(self) } #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."] #[inline(always)] - pub fn mem_trans_en_ch(&mut self) -> MEM_TRANS_EN_CH_W<4> { - MEM_TRANS_EN_CH_W::new(self) + pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<4> { + MEM_TRANS_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_conf1_ch.rs b/esp32s3/src/dma/in_conf1_ch.rs index 7a81561fac..6b7639f105 100644 --- a/esp32s3/src/dma/in_conf1_ch.rs +++ b/esp32s3/src/dma/in_conf1_ch.rs @@ -34,53 +34,52 @@ impl From> for W { W(writer) } } -#[doc = "Field `DMA_INFIFO_FULL_THRS_CH` reader - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."] -pub type DMA_INFIFO_FULL_THRS_CH_R = crate::FieldReader; -#[doc = "Field `DMA_INFIFO_FULL_THRS_CH` writer - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."] -pub type DMA_INFIFO_FULL_THRS_CH_W<'a, const O: u8> = +#[doc = "Field `DMA_INFIFO_FULL_THRS` reader - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."] +pub type DMA_INFIFO_FULL_THRS_R = crate::FieldReader; +#[doc = "Field `DMA_INFIFO_FULL_THRS` writer - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."] +pub type DMA_INFIFO_FULL_THRS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_CONF1_CH_SPEC, u16, u16, 12, O>; -#[doc = "Field `IN_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH_R = crate::BitReader; -#[doc = "Field `IN_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type IN_CHECK_OWNER_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_CONF1_CH_SPEC, bool, O>; -#[doc = "Field `IN_EXT_MEM_BK_SIZE_CH` reader - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] -pub type IN_EXT_MEM_BK_SIZE_CH_R = crate::FieldReader; -#[doc = "Field `IN_EXT_MEM_BK_SIZE_CH` writer - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] -pub type IN_EXT_MEM_BK_SIZE_CH_W<'a, const O: u8> = +#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_CONF1_CH_SPEC, bool, O>; +#[doc = "Field `IN_EXT_MEM_BK_SIZE` reader - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] +pub type IN_EXT_MEM_BK_SIZE_R = crate::FieldReader; +#[doc = "Field `IN_EXT_MEM_BK_SIZE` writer - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] +pub type IN_EXT_MEM_BK_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_CONF1_CH_SPEC, u8, u8, 2, O>; impl R { #[doc = "Bits 0:11 - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."] #[inline(always)] - pub fn dma_infifo_full_thrs_ch(&self) -> DMA_INFIFO_FULL_THRS_CH_R { - DMA_INFIFO_FULL_THRS_CH_R::new((self.bits & 0x0fff) as u16) + pub fn dma_infifo_full_thrs(&self) -> DMA_INFIFO_FULL_THRS_R { + DMA_INFIFO_FULL_THRS_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch(&self) -> IN_CHECK_OWNER_CH_R { - IN_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0) + pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R { + IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bits 13:14 - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] #[inline(always)] - pub fn in_ext_mem_bk_size_ch(&self) -> IN_EXT_MEM_BK_SIZE_CH_R { - IN_EXT_MEM_BK_SIZE_CH_R::new(((self.bits >> 13) & 3) as u8) + pub fn in_ext_mem_bk_size(&self) -> IN_EXT_MEM_BK_SIZE_R { + IN_EXT_MEM_BK_SIZE_R::new(((self.bits >> 13) & 3) as u8) } } impl W { #[doc = "Bits 0:11 - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."] #[inline(always)] - pub fn dma_infifo_full_thrs_ch(&mut self) -> DMA_INFIFO_FULL_THRS_CH_W<0> { - DMA_INFIFO_FULL_THRS_CH_W::new(self) + pub fn dma_infifo_full_thrs(&mut self) -> DMA_INFIFO_FULL_THRS_W<0> { + DMA_INFIFO_FULL_THRS_W::new(self) } #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn in_check_owner_ch(&mut self) -> IN_CHECK_OWNER_CH_W<12> { - IN_CHECK_OWNER_CH_W::new(self) + pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<12> { + IN_CHECK_OWNER_W::new(self) } #[doc = "Bits 13:14 - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] #[inline(always)] - pub fn in_ext_mem_bk_size_ch(&mut self) -> IN_EXT_MEM_BK_SIZE_CH_W<13> { - IN_EXT_MEM_BK_SIZE_CH_W::new(self) + pub fn in_ext_mem_bk_size(&mut self) -> IN_EXT_MEM_BK_SIZE_W<13> { + IN_EXT_MEM_BK_SIZE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_dscr_bf0_ch.rs b/esp32s3/src/dma/in_dscr_bf0_ch.rs index 640e5332c4..d111b58c7d 100644 --- a/esp32s3/src/dma/in_dscr_bf0_ch.rs +++ b/esp32s3/src/dma/in_dscr_bf0_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF0_CH` reader - The address of the last inlink descriptor x-1."] -pub type INLINK_DSCR_BF0_CH_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] #[inline(always)] - pub fn inlink_dscr_bf0_ch(&self) -> INLINK_DSCR_BF0_CH_R { - INLINK_DSCR_BF0_CH_R::new(self.bits) + pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R { + INLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "The last inlink descriptor address of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf0_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_dscr_bf1_ch.rs b/esp32s3/src/dma/in_dscr_bf1_ch.rs index e1e983645a..a9acdf72bd 100644 --- a/esp32s3/src/dma/in_dscr_bf1_ch.rs +++ b/esp32s3/src/dma/in_dscr_bf1_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_BF1_CH` reader - The address of the second-to-last inlink descriptor x-2."] -pub type INLINK_DSCR_BF1_CH_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn inlink_dscr_bf1_ch(&self) -> INLINK_DSCR_BF1_CH_R { - INLINK_DSCR_BF1_CH_R::new(self.bits) + pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R { + INLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_bf1_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_dscr_ch.rs b/esp32s3/src/dma/in_dscr_ch.rs index 1ea72335f4..708657ff5e 100644 --- a/esp32s3/src/dma/in_dscr_ch.rs +++ b/esp32s3/src/dma/in_dscr_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_CH` reader - The address of the current inlink descriptor x."] -pub type INLINK_DSCR_CH_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] #[inline(always)] - pub fn inlink_dscr_ch(&self) -> INLINK_DSCR_CH_R { - INLINK_DSCR_CH_R::new(self.bits) + pub fn inlink_dscr(&self) -> INLINK_DSCR_R { + INLINK_DSCR_R::new(self.bits) } } #[doc = "Current inlink descriptor address of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_dscr_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_err_eof_des_addr_ch.rs b/esp32s3/src/dma/in_err_eof_des_addr_ch.rs index 4e4b526f02..eba19737d1 100644 --- a/esp32s3/src/dma/in_err_eof_des_addr_ch.rs +++ b/esp32s3/src/dma/in_err_eof_des_addr_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] -pub type IN_ERR_EOF_DES_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] #[inline(always)] - pub fn in_err_eof_des_addr_ch(&self) -> IN_ERR_EOF_DES_ADDR_CH_R { - IN_ERR_EOF_DES_ADDR_CH_R::new(self.bits) + pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R { + IN_ERR_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_err_eof_des_addr_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_int_clr_ch.rs b/esp32s3/src/dma/in_int_clr_ch.rs index 7cfded6e61..d1c816342f 100644 --- a/esp32s3/src/dma/in_int_clr_ch.rs +++ b/esp32s3/src/dma/in_int_clr_ch.rs @@ -19,86 +19,77 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `DMA_INFIFO_FULL_WM_CH_INT_CLR` writer - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."] -pub type DMA_INFIFO_FULL_WM_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_L1_CH_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_L1_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_L1_CH_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_L1_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_L3_CH_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."] -pub type INFIFO_OVF_L3_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_L3_CH_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."] -pub type INFIFO_UDF_L3_CH_INT_CLR_W<'a, const O: u8> = +#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `DMA_INFIFO_FULL_WM` writer - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."] +pub type DMA_INFIFO_FULL_WM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF_L1` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF_L1` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF_L3` writer - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_OVF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF_L3` writer - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_UDF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_CLR_CH_SPEC, bool, O>; impl W { #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch_int_clr(&mut self) -> IN_DONE_CH_INT_CLR_W<0> { - IN_DONE_CH_INT_CLR_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch_int_clr(&mut self) -> IN_SUC_EOF_CH_INT_CLR_W<1> { - IN_SUC_EOF_CH_INT_CLR_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch_int_clr(&mut self) -> IN_ERR_EOF_CH_INT_CLR_W<2> { - IN_ERR_EOF_CH_INT_CLR_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch_int_clr(&mut self) -> IN_DSCR_ERR_CH_INT_CLR_W<3> { - IN_DSCR_ERR_CH_INT_CLR_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<3> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch_int_clr(&mut self) -> IN_DSCR_EMPTY_CH_INT_CLR_W<4> { - IN_DSCR_EMPTY_CH_INT_CLR_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<4> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 5 - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."] #[inline(always)] - pub fn dma_infifo_full_wm_ch_int_clr(&mut self) -> DMA_INFIFO_FULL_WM_CH_INT_CLR_W<5> { - DMA_INFIFO_FULL_WM_CH_INT_CLR_W::new(self) + pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<5> { + DMA_INFIFO_FULL_WM_W::new(self) } #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l1_ch_int_clr(&mut self) -> INFIFO_OVF_L1_CH_INT_CLR_W<6> { - INFIFO_OVF_L1_CH_INT_CLR_W::new(self) + pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<6> { + INFIFO_OVF_L1_W::new(self) } #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l1_ch_int_clr(&mut self) -> INFIFO_UDF_L1_CH_INT_CLR_W<7> { - INFIFO_UDF_L1_CH_INT_CLR_W::new(self) + pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<7> { + INFIFO_UDF_L1_W::new(self) } #[doc = "Bit 8 - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l3_ch_int_clr(&mut self) -> INFIFO_OVF_L3_CH_INT_CLR_W<8> { - INFIFO_OVF_L3_CH_INT_CLR_W::new(self) + pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<8> { + INFIFO_OVF_L3_W::new(self) } #[doc = "Bit 9 - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l3_ch_int_clr(&mut self) -> INFIFO_UDF_L3_CH_INT_CLR_W<9> { - INFIFO_UDF_L3_CH_INT_CLR_W::new(self) + pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<9> { + INFIFO_UDF_L3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_int_ena_ch.rs b/esp32s3/src/dma/in_int_ena_ch.rs index 2a82c67cd4..c1c01dd0a6 100644 --- a/esp32s3/src/dma/in_int_ena_ch.rs +++ b/esp32s3/src/dma/in_int_ena_ch.rs @@ -34,158 +34,148 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_DONE_CH_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DONE_CH_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `IN_SUC_EOF_CH_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `IN_ERR_EOF_CH_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_ERR_CH_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_FULL_WM_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."] -pub type INFIFO_FULL_WM_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_FULL_WM_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."] -pub type INFIFO_FULL_WM_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_L1_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_L1_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_L1_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_L1_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_L1_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_L1_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_L1_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_L1_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_OVF_L3_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] -pub type INFIFO_OVF_L3_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_L3_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] -pub type INFIFO_OVF_L3_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `INFIFO_UDF_L3_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] -pub type INFIFO_UDF_L3_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_L3_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] -pub type INFIFO_UDF_L3_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_FULL_WM` reader - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."] +pub type INFIFO_FULL_WM_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_WM` writer - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."] +pub type INFIFO_FULL_WM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF_L1` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF_L1` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_OVF_L3` reader - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_OVF_L3_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L3` writer - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_OVF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_UDF_L3` reader - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_UDF_L3_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L3` writer - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_UDF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_INT_ENA_CH_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch_int_ena(&self) -> IN_DONE_CH_INT_ENA_R { - IN_DONE_CH_INT_ENA_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch_int_ena(&self) -> IN_SUC_EOF_CH_INT_ENA_R { - IN_SUC_EOF_CH_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch_int_ena(&self) -> IN_ERR_EOF_CH_INT_ENA_R { - IN_ERR_EOF_CH_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch_int_ena(&self) -> IN_DSCR_ERR_CH_INT_ENA_R { - IN_DSCR_ERR_CH_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch_int_ena(&self) -> IN_DSCR_EMPTY_CH_INT_ENA_R { - IN_DSCR_EMPTY_CH_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."] #[inline(always)] - pub fn infifo_full_wm_ch_int_ena(&self) -> INFIFO_FULL_WM_CH_INT_ENA_R { - INFIFO_FULL_WM_CH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R { + INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l1_ch_int_ena(&self) -> INFIFO_OVF_L1_CH_INT_ENA_R { - INFIFO_OVF_L1_CH_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R { + INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l1_ch_int_ena(&self) -> INFIFO_UDF_L1_CH_INT_ENA_R { - INFIFO_UDF_L1_CH_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R { + INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l3_ch_int_ena(&self) -> INFIFO_OVF_L3_CH_INT_ENA_R { - INFIFO_OVF_L3_CH_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R { + INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l3_ch_int_ena(&self) -> INFIFO_UDF_L3_CH_INT_ENA_R { - INFIFO_UDF_L3_CH_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R { + INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch_int_ena(&mut self) -> IN_DONE_CH_INT_ENA_W<0> { - IN_DONE_CH_INT_ENA_W::new(self) + pub fn in_done(&mut self) -> IN_DONE_W<0> { + IN_DONE_W::new(self) } #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch_int_ena(&mut self) -> IN_SUC_EOF_CH_INT_ENA_W<1> { - IN_SUC_EOF_CH_INT_ENA_W::new(self) + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<1> { + IN_SUC_EOF_W::new(self) } #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch_int_ena(&mut self) -> IN_ERR_EOF_CH_INT_ENA_W<2> { - IN_ERR_EOF_CH_INT_ENA_W::new(self) + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<2> { + IN_ERR_EOF_W::new(self) } #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch_int_ena(&mut self) -> IN_DSCR_ERR_CH_INT_ENA_W<3> { - IN_DSCR_ERR_CH_INT_ENA_W::new(self) + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<3> { + IN_DSCR_ERR_W::new(self) } #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch_int_ena(&mut self) -> IN_DSCR_EMPTY_CH_INT_ENA_W<4> { - IN_DSCR_EMPTY_CH_INT_ENA_W::new(self) + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<4> { + IN_DSCR_EMPTY_W::new(self) } #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."] #[inline(always)] - pub fn infifo_full_wm_ch_int_ena(&mut self) -> INFIFO_FULL_WM_CH_INT_ENA_W<5> { - INFIFO_FULL_WM_CH_INT_ENA_W::new(self) + pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W<5> { + INFIFO_FULL_WM_W::new(self) } #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l1_ch_int_ena(&mut self) -> INFIFO_OVF_L1_CH_INT_ENA_W<6> { - INFIFO_OVF_L1_CH_INT_ENA_W::new(self) + pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<6> { + INFIFO_OVF_L1_W::new(self) } #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l1_ch_int_ena(&mut self) -> INFIFO_UDF_L1_CH_INT_ENA_W<7> { - INFIFO_UDF_L1_CH_INT_ENA_W::new(self) + pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<7> { + INFIFO_UDF_L1_W::new(self) } #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l3_ch_int_ena(&mut self) -> INFIFO_OVF_L3_CH_INT_ENA_W<8> { - INFIFO_OVF_L3_CH_INT_ENA_W::new(self) + pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<8> { + INFIFO_OVF_L3_W::new(self) } #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l3_ch_int_ena(&mut self) -> INFIFO_UDF_L3_CH_INT_ENA_W<9> { - INFIFO_UDF_L3_CH_INT_ENA_W::new(self) + pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<9> { + INFIFO_UDF_L3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_int_raw_ch.rs b/esp32s3/src/dma/in_int_raw_ch.rs index bd901d8777..d8ff8293e1 100644 --- a/esp32s3/src/dma/in_int_raw_ch.rs +++ b/esp32s3/src/dma/in_int_raw_ch.rs @@ -13,76 +13,76 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] -pub type IN_DONE_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] -pub type IN_SUC_EOF_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] -pub type IN_ERR_EOF_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] -pub type IN_DSCR_ERR_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] -pub type IN_DSCR_EMPTY_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_FULL_WM_CH_INT_RAW` reader - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."] -pub type INFIFO_FULL_WM_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_L1_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] -pub type INFIFO_OVF_L1_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_L1_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] -pub type INFIFO_UDF_L1_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_L3_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."] -pub type INFIFO_OVF_L3_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_L3_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."] -pub type INFIFO_UDF_L3_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_WM` reader - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."] +pub type INFIFO_FULL_WM_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_OVF_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_UDF_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."] +pub type INFIFO_OVF_L3_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."] +pub type INFIFO_UDF_L3_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] #[inline(always)] - pub fn in_done_ch_int_raw(&self) -> IN_DONE_CH_INT_RAW_R { - IN_DONE_CH_INT_RAW_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] #[inline(always)] - pub fn in_suc_eof_ch_int_raw(&self) -> IN_SUC_EOF_CH_INT_RAW_R { - IN_SUC_EOF_CH_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."] #[inline(always)] - pub fn in_err_eof_ch_int_raw(&self) -> IN_ERR_EOF_CH_INT_RAW_R { - IN_ERR_EOF_CH_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] #[inline(always)] - pub fn in_dscr_err_ch_int_raw(&self) -> IN_DSCR_ERR_CH_INT_RAW_R { - IN_DSCR_ERR_CH_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."] #[inline(always)] - pub fn in_dscr_empty_ch_int_raw(&self) -> IN_DSCR_EMPTY_CH_INT_RAW_R { - IN_DSCR_EMPTY_CH_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."] #[inline(always)] - pub fn infifo_full_wm_ch_int_raw(&self) -> INFIFO_FULL_WM_CH_INT_RAW_R { - INFIFO_FULL_WM_CH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R { + INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] #[inline(always)] - pub fn infifo_ovf_l1_ch_int_raw(&self) -> INFIFO_OVF_L1_CH_INT_RAW_R { - INFIFO_OVF_L1_CH_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R { + INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] #[inline(always)] - pub fn infifo_udf_l1_ch_int_raw(&self) -> INFIFO_UDF_L1_CH_INT_RAW_R { - INFIFO_UDF_L1_CH_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R { + INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."] #[inline(always)] - pub fn infifo_ovf_l3_ch_int_raw(&self) -> INFIFO_OVF_L3_CH_INT_RAW_R { - INFIFO_OVF_L3_CH_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R { + INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."] #[inline(always)] - pub fn infifo_udf_l3_ch_int_raw(&self) -> INFIFO_UDF_L3_CH_INT_RAW_R { - INFIFO_UDF_L3_CH_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R { + INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0) } } #[doc = "Raw status interrupt of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_int_raw_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_int_st_ch.rs b/esp32s3/src/dma/in_int_st_ch.rs index 609d56f2eb..4b5a082cf5 100644 --- a/esp32s3/src/dma/in_int_st_ch.rs +++ b/esp32s3/src/dma/in_int_st_ch.rs @@ -13,76 +13,76 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_DONE_CH_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_SUC_EOF_CH_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_ERR_EOF_CH_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_ERR_CH_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_FULL_WM_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt."] -pub type INFIFO_FULL_WM_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_L1_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_L1_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_L1_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_L1_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_OVF_L3_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."] -pub type INFIFO_OVF_L3_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `INFIFO_UDF_L3_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."] -pub type INFIFO_UDF_L3_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DONE` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_WM` reader - The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt."] +pub type INFIFO_FULL_WM_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L3` reader - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_OVF_L3_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L3` reader - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_UDF_L3_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] #[inline(always)] - pub fn in_done_ch_int_st(&self) -> IN_DONE_CH_INT_ST_R { - IN_DONE_CH_INT_ST_R::new((self.bits & 1) != 0) + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_suc_eof_ch_int_st(&self) -> IN_SUC_EOF_CH_INT_ST_R { - IN_SUC_EOF_CH_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] #[inline(always)] - pub fn in_err_eof_ch_int_st(&self) -> IN_ERR_EOF_CH_INT_ST_R { - IN_ERR_EOF_CH_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_err_ch_int_st(&self) -> IN_DSCR_ERR_CH_INT_ST_R { - IN_DSCR_ERR_CH_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] #[inline(always)] - pub fn in_dscr_empty_ch_int_st(&self) -> IN_DSCR_EMPTY_CH_INT_ST_R { - IN_DSCR_EMPTY_CH_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt."] #[inline(always)] - pub fn infifo_full_wm_ch_int_st(&self) -> INFIFO_FULL_WM_CH_INT_ST_R { - INFIFO_FULL_WM_CH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R { + INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l1_ch_int_st(&self) -> INFIFO_OVF_L1_CH_INT_ST_R { - INFIFO_OVF_L1_CH_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R { + INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l1_ch_int_st(&self) -> INFIFO_UDF_L1_CH_INT_ST_R { - INFIFO_UDF_L1_CH_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R { + INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_ovf_l3_ch_int_st(&self) -> INFIFO_OVF_L3_CH_INT_ST_R { - INFIFO_OVF_L3_CH_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R { + INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn infifo_udf_l3_ch_int_st(&self) -> INFIFO_UDF_L3_CH_INT_ST_R { - INFIFO_UDF_L3_CH_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R { + INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0) } } #[doc = "Masked interrupt of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_int_st_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_link_ch.rs b/esp32s3/src/dma/in_link_ch.rs index 202b4fea7c..e003007606 100644 --- a/esp32s3/src/dma/in_link_ch.rs +++ b/esp32s3/src/dma/in_link_ch.rs @@ -34,87 +34,86 @@ impl From> for W { W(writer) } } -#[doc = "Field `INLINK_ADDR_CH` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH_R = crate::FieldReader; -#[doc = "Field `INLINK_ADDR_CH` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] -pub type INLINK_ADDR_CH_W<'a, const O: u8> = +#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_LINK_CH_SPEC, u32, u32, 20, O>; -#[doc = "Field `INLINK_AUTO_RET_CH` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH_R = crate::BitReader; -#[doc = "Field `INLINK_AUTO_RET_CH` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] -pub type INLINK_AUTO_RET_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; -#[doc = "Field `INLINK_STOP_CH` reader - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH_R = crate::BitReader; -#[doc = "Field `INLINK_STOP_CH` writer - Set this bit to stop dealing with the inlink descriptors."] -pub type INLINK_STOP_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; -#[doc = "Field `INLINK_START_CH` reader - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH_R = crate::BitReader; -#[doc = "Field `INLINK_START_CH` writer - Set this bit to start dealing with the inlink descriptors."] -pub type INLINK_START_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; -#[doc = "Field `INLINK_RESTART_CH` reader - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH_R = crate::BitReader; -#[doc = "Field `INLINK_RESTART_CH` writer - Set this bit to mount a new inlink descriptor."] -pub type INLINK_RESTART_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; -#[doc = "Field `INLINK_PARK_CH` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] -pub type INLINK_PARK_CH_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; +#[doc = "Field `INLINK_START` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_LINK_CH_SPEC, bool, O>; +#[doc = "Field `INLINK_PARK` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch(&self) -> INLINK_ADDR_CH_R { - INLINK_ADDR_CH_R::new((self.bits & 0x000f_ffff) as u32) + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch(&self) -> INLINK_AUTO_RET_CH_R { - INLINK_AUTO_RET_CH_R::new(((self.bits >> 20) & 1) != 0) + pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R { + INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch(&self) -> INLINK_STOP_CH_R { - INLINK_STOP_CH_R::new(((self.bits >> 21) & 1) != 0) + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch(&self) -> INLINK_START_CH_R { - INLINK_START_CH_R::new(((self.bits >> 22) & 1) != 0) + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch(&self) -> INLINK_RESTART_CH_R { - INLINK_RESTART_CH_R::new(((self.bits >> 23) & 1) != 0) + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] #[inline(always)] - pub fn inlink_park_ch(&self) -> INLINK_PARK_CH_R { - INLINK_PARK_CH_R::new(((self.bits >> 24) & 1) != 0) + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 24) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."] #[inline(always)] - pub fn inlink_addr_ch(&mut self) -> INLINK_ADDR_CH_W<0> { - INLINK_ADDR_CH_W::new(self) + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<0> { + INLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] #[inline(always)] - pub fn inlink_auto_ret_ch(&mut self) -> INLINK_AUTO_RET_CH_W<20> { - INLINK_AUTO_RET_CH_W::new(self) + pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<20> { + INLINK_AUTO_RET_W::new(self) } #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_stop_ch(&mut self) -> INLINK_STOP_CH_W<21> { - INLINK_STOP_CH_W::new(self) + pub fn inlink_stop(&mut self) -> INLINK_STOP_W<21> { + INLINK_STOP_W::new(self) } #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] #[inline(always)] - pub fn inlink_start_ch(&mut self) -> INLINK_START_CH_W<22> { - INLINK_START_CH_W::new(self) + pub fn inlink_start(&mut self) -> INLINK_START_W<22> { + INLINK_START_W::new(self) } #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] #[inline(always)] - pub fn inlink_restart_ch(&mut self) -> INLINK_RESTART_CH_W<23> { - INLINK_RESTART_CH_W::new(self) + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<23> { + INLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_peri_sel_ch.rs b/esp32s3/src/dma/in_peri_sel_ch.rs index ed37299c42..75d6ced29e 100644 --- a/esp32s3/src/dma/in_peri_sel_ch.rs +++ b/esp32s3/src/dma/in_peri_sel_ch.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_IN_SEL_CH` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] -pub type PERI_IN_SEL_CH_R = crate::FieldReader; -#[doc = "Field `PERI_IN_SEL_CH` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] -pub type PERI_IN_SEL_CH_W<'a, const O: u8> = +#[doc = "Field `PERI_IN_SEL` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] +pub type PERI_IN_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] +pub type PERI_IN_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PERI_SEL_CH_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] #[inline(always)] - pub fn peri_in_sel_ch(&self) -> PERI_IN_SEL_CH_R { - PERI_IN_SEL_CH_R::new((self.bits & 0x3f) as u8) + pub fn peri_in_sel(&self) -> PERI_IN_SEL_R { + PERI_IN_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] #[inline(always)] - pub fn peri_in_sel_ch(&mut self) -> PERI_IN_SEL_CH_W<0> { - PERI_IN_SEL_CH_W::new(self) + pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<0> { + PERI_IN_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_pop_ch.rs b/esp32s3/src/dma/in_pop_ch.rs index 1c9952d551..c07cf5e61f 100644 --- a/esp32s3/src/dma/in_pop_ch.rs +++ b/esp32s3/src/dma/in_pop_ch.rs @@ -34,29 +34,29 @@ impl From> for W { W(writer) } } -#[doc = "Field `INFIFO_RDATA_CH` reader - This register stores the data popping from DMA FIFO."] -pub type INFIFO_RDATA_CH_R = crate::FieldReader; -#[doc = "Field `INFIFO_POP_CH` reader - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_POP_CH` writer - Set this bit to pop data from DMA FIFO."] -pub type INFIFO_POP_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH_SPEC, bool, O>; +#[doc = "Field `INFIFO_RDATA` reader - This register stores the data popping from DMA FIFO."] +pub type INFIFO_RDATA_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP` reader - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_R = crate::BitReader; +#[doc = "Field `INFIFO_POP` writer - Set this bit to pop data from DMA FIFO."] +pub type INFIFO_POP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IN_POP_CH_SPEC, bool, O>; impl R { #[doc = "Bits 0:11 - This register stores the data popping from DMA FIFO."] #[inline(always)] - pub fn infifo_rdata_ch(&self) -> INFIFO_RDATA_CH_R { - INFIFO_RDATA_CH_R::new((self.bits & 0x0fff) as u16) + pub fn infifo_rdata(&self) -> INFIFO_RDATA_R { + INFIFO_RDATA_R::new((self.bits & 0x0fff) as u16) } #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch(&self) -> INFIFO_POP_CH_R { - INFIFO_POP_CH_R::new(((self.bits >> 12) & 1) != 0) + pub fn infifo_pop(&self) -> INFIFO_POP_R { + INFIFO_POP_R::new(((self.bits >> 12) & 1) != 0) } } impl W { #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."] #[inline(always)] - pub fn infifo_pop_ch(&mut self) -> INFIFO_POP_CH_W<12> { - INFIFO_POP_CH_W::new(self) + pub fn infifo_pop(&mut self) -> INFIFO_POP_W<12> { + INFIFO_POP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_pri_ch.rs b/esp32s3/src/dma/in_pri_ch.rs index 2d5fa604f1..1bf27ceb5d 100644 --- a/esp32s3/src/dma/in_pri_ch.rs +++ b/esp32s3/src/dma/in_pri_ch.rs @@ -34,22 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `RX_PRI_CH` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH_R = crate::FieldReader; -#[doc = "Field `RX_PRI_CH` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."] -pub type RX_PRI_CH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH_SPEC, u8, u8, 4, O>; +#[doc = "Field `RX_PRI` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."] +pub type RX_PRI_R = crate::FieldReader; +#[doc = "Field `RX_PRI` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."] +pub type RX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_PRI_CH_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch(&self) -> RX_PRI_CH_R { - RX_PRI_CH_R::new((self.bits & 0x0f) as u8) + pub fn rx_pri(&self) -> RX_PRI_R { + RX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn rx_pri_ch(&mut self) -> RX_PRI_CH_W<0> { - RX_PRI_CH_W::new(self) + pub fn rx_pri(&mut self) -> RX_PRI_W<0> { + RX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_sram_size_ch.rs b/esp32s3/src/dma/in_sram_size_ch.rs index 65f55bc63f..f158cca196 100644 --- a/esp32s3/src/dma/in_sram_size_ch.rs +++ b/esp32s3/src/dma/in_sram_size_ch.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `IN_SIZE_CH` reader - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] -pub type IN_SIZE_CH_R = crate::FieldReader; -#[doc = "Field `IN_SIZE_CH` writer - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] -pub type IN_SIZE_CH_W<'a, const O: u8> = +#[doc = "Field `IN_SIZE` reader - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] +pub type IN_SIZE_R = crate::FieldReader; +#[doc = "Field `IN_SIZE` writer - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] +pub type IN_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_SRAM_SIZE_CH_SPEC, u8, u8, 7, O>; impl R { #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] #[inline(always)] - pub fn in_size_ch(&self) -> IN_SIZE_CH_R { - IN_SIZE_CH_R::new((self.bits & 0x7f) as u8) + pub fn in_size(&self) -> IN_SIZE_R { + IN_SIZE_R::new((self.bits & 0x7f) as u8) } } impl W { #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] #[inline(always)] - pub fn in_size_ch(&mut self) -> IN_SIZE_CH_W<0> { - IN_SIZE_CH_W::new(self) + pub fn in_size(&mut self) -> IN_SIZE_W<0> { + IN_SIZE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/in_state_ch.rs b/esp32s3/src/dma/in_state_ch.rs index e27f766c8b..2a592e9c15 100644 --- a/esp32s3/src/dma/in_state_ch.rs +++ b/esp32s3/src/dma/in_state_ch.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `INLINK_DSCR_ADDR_CH` reader - This register stores the current inlink descriptor's address."] -pub type INLINK_DSCR_ADDR_CH_R = crate::FieldReader; -#[doc = "Field `IN_DSCR_STATE_CH` reader - reserved"] -pub type IN_DSCR_STATE_CH_R = crate::FieldReader; -#[doc = "Field `IN_STATE_CH` reader - reserved"] -pub type IN_STATE_CH_R = crate::FieldReader; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - reserved"] +pub type IN_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] #[inline(always)] - pub fn inlink_dscr_addr_ch(&self) -> INLINK_DSCR_ADDR_CH_R { - INLINK_DSCR_ADDR_CH_R::new((self.bits & 0x0003_ffff) as u32) + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn in_dscr_state_ch(&self) -> IN_DSCR_STATE_CH_R { - IN_DSCR_STATE_CH_R::new(((self.bits >> 18) & 3) as u8) + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn in_state_ch(&self) -> IN_STATE_CH_R { - IN_STATE_CH_R::new(((self.bits >> 20) & 7) as u8) + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "Receive status of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_state_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_suc_eof_des_addr_ch.rs b/esp32s3/src/dma/in_suc_eof_des_addr_ch.rs index eb279a2319..9428b16341 100644 --- a/esp32s3/src/dma/in_suc_eof_des_addr_ch.rs +++ b/esp32s3/src/dma/in_suc_eof_des_addr_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] -pub type IN_SUC_EOF_DES_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn in_suc_eof_des_addr_ch(&self) -> IN_SUC_EOF_DES_ADDR_CH_R { - IN_SUC_EOF_DES_ADDR_CH_R::new(self.bits) + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_suc_eof_des_addr_ch](index.html) module"] diff --git a/esp32s3/src/dma/in_wight_ch.rs b/esp32s3/src/dma/in_wight_ch.rs index 360fb4563f..0c3296faff 100644 --- a/esp32s3/src/dma/in_wight_ch.rs +++ b/esp32s3/src/dma/in_wight_ch.rs @@ -34,23 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `RX_WEIGHT_CH` reader - The weight of Rx channel 0."] -pub type RX_WEIGHT_CH_R = crate::FieldReader; -#[doc = "Field `RX_WEIGHT_CH` writer - The weight of Rx channel 0."] -pub type RX_WEIGHT_CH_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, IN_WIGHT_CH_SPEC, u8, u8, 4, O>; +#[doc = "Field `RX_WEIGHT` reader - The weight of Rx channel 0."] +pub type RX_WEIGHT_R = crate::FieldReader; +#[doc = "Field `RX_WEIGHT` writer - The weight of Rx channel 0."] +pub type RX_WEIGHT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IN_WIGHT_CH_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 8:11 - The weight of Rx channel 0."] #[inline(always)] - pub fn rx_weight_ch(&self) -> RX_WEIGHT_CH_R { - RX_WEIGHT_CH_R::new(((self.bits >> 8) & 0x0f) as u8) + pub fn rx_weight(&self) -> RX_WEIGHT_R { + RX_WEIGHT_R::new(((self.bits >> 8) & 0x0f) as u8) } } impl W { #[doc = "Bits 8:11 - The weight of Rx channel 0."] #[inline(always)] - pub fn rx_weight_ch(&mut self) -> RX_WEIGHT_CH_W<8> { - RX_WEIGHT_CH_W::new(self) + pub fn rx_weight(&mut self) -> RX_WEIGHT_W<8> { + RX_WEIGHT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/infifo_status_ch.rs b/esp32s3/src/dma/infifo_status_ch.rs index 4a99326dd6..a1cfc05ad1 100644 --- a/esp32s3/src/dma/infifo_status_ch.rs +++ b/esp32s3/src/dma/infifo_status_ch.rs @@ -13,104 +13,104 @@ impl From> for R { R(reader) } } -#[doc = "Field `INFIFO_FULL_L1_CH` reader - L1 Rx FIFO full signal for Rx channel 0."] -pub type INFIFO_FULL_L1_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_L1_CH` reader - L1 Rx FIFO empty signal for Rx channel 0."] -pub type INFIFO_EMPTY_L1_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_FULL_L2_CH` reader - L2 Rx FIFO full signal for Rx channel 0."] -pub type INFIFO_FULL_L2_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_L2_CH` reader - L2 Rx FIFO empty signal for Rx channel 0."] -pub type INFIFO_EMPTY_L2_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_FULL_L3_CH` reader - L3 Rx FIFO full signal for Rx channel 0."] -pub type INFIFO_FULL_L3_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_EMPTY_L3_CH` reader - L3 Rx FIFO empty signal for Rx channel 0."] -pub type INFIFO_EMPTY_L3_CH_R = crate::BitReader; -#[doc = "Field `INFIFO_CNT_L1_CH` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] -pub type INFIFO_CNT_L1_CH_R = crate::FieldReader; -#[doc = "Field `INFIFO_CNT_L2_CH` reader - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."] -pub type INFIFO_CNT_L2_CH_R = crate::FieldReader; -#[doc = "Field `INFIFO_CNT_L3_CH` reader - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."] -pub type INFIFO_CNT_L3_CH_R = crate::FieldReader; -#[doc = "Field `IN_REMAIN_UNDER_1B_L3_CH` reader - reserved"] -pub type IN_REMAIN_UNDER_1B_L3_CH_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_2B_L3_CH` reader - reserved"] -pub type IN_REMAIN_UNDER_2B_L3_CH_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_3B_L3_CH` reader - reserved"] -pub type IN_REMAIN_UNDER_3B_L3_CH_R = crate::BitReader; -#[doc = "Field `IN_REMAIN_UNDER_4B_L3_CH` reader - reserved"] -pub type IN_REMAIN_UNDER_4B_L3_CH_R = crate::BitReader; -#[doc = "Field `IN_BUF_HUNGRY_CH` reader - reserved"] -pub type IN_BUF_HUNGRY_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_L1` reader - L1 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_FULL_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1` reader - L1 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_EMPTY_L1_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_L2` reader - L2 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_FULL_L2_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L2` reader - L2 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_EMPTY_L2_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_L3` reader - L3 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_FULL_L3_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L3` reader - L3 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_EMPTY_L3_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] +pub type INFIFO_CNT_L1_R = crate::FieldReader; +#[doc = "Field `INFIFO_CNT_L2` reader - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."] +pub type INFIFO_CNT_L2_R = crate::FieldReader; +#[doc = "Field `INFIFO_CNT_L3` reader - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."] +pub type INFIFO_CNT_L3_R = crate::FieldReader; +#[doc = "Field `IN_REMAIN_UNDER_1B_L3` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_L3_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B_L3` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_L3_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B_L3` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_L3_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B_L3` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_L3_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY` reader - reserved"] +pub type IN_BUF_HUNGRY_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 0."] #[inline(always)] - pub fn infifo_full_l1_ch(&self) -> INFIFO_FULL_L1_CH_R { - INFIFO_FULL_L1_CH_R::new((self.bits & 1) != 0) + pub fn infifo_full_l1(&self) -> INFIFO_FULL_L1_R { + INFIFO_FULL_L1_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 0."] #[inline(always)] - pub fn infifo_empty_l1_ch(&self) -> INFIFO_EMPTY_L1_CH_R { - INFIFO_EMPTY_L1_CH_R::new(((self.bits >> 1) & 1) != 0) + pub fn infifo_empty_l1(&self) -> INFIFO_EMPTY_L1_R { + INFIFO_EMPTY_L1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - L2 Rx FIFO full signal for Rx channel 0."] #[inline(always)] - pub fn infifo_full_l2_ch(&self) -> INFIFO_FULL_L2_CH_R { - INFIFO_FULL_L2_CH_R::new(((self.bits >> 2) & 1) != 0) + pub fn infifo_full_l2(&self) -> INFIFO_FULL_L2_R { + INFIFO_FULL_L2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - L2 Rx FIFO empty signal for Rx channel 0."] #[inline(always)] - pub fn infifo_empty_l2_ch(&self) -> INFIFO_EMPTY_L2_CH_R { - INFIFO_EMPTY_L2_CH_R::new(((self.bits >> 3) & 1) != 0) + pub fn infifo_empty_l2(&self) -> INFIFO_EMPTY_L2_R { + INFIFO_EMPTY_L2_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - L3 Rx FIFO full signal for Rx channel 0."] #[inline(always)] - pub fn infifo_full_l3_ch(&self) -> INFIFO_FULL_L3_CH_R { - INFIFO_FULL_L3_CH_R::new(((self.bits >> 4) & 1) != 0) + pub fn infifo_full_l3(&self) -> INFIFO_FULL_L3_R { + INFIFO_FULL_L3_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - L3 Rx FIFO empty signal for Rx channel 0."] #[inline(always)] - pub fn infifo_empty_l3_ch(&self) -> INFIFO_EMPTY_L3_CH_R { - INFIFO_EMPTY_L3_CH_R::new(((self.bits >> 5) & 1) != 0) + pub fn infifo_empty_l3(&self) -> INFIFO_EMPTY_L3_R { + INFIFO_EMPTY_L3_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bits 6:11 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] #[inline(always)] - pub fn infifo_cnt_l1_ch(&self) -> INFIFO_CNT_L1_CH_R { - INFIFO_CNT_L1_CH_R::new(((self.bits >> 6) & 0x3f) as u8) + pub fn infifo_cnt_l1(&self) -> INFIFO_CNT_L1_R { + INFIFO_CNT_L1_R::new(((self.bits >> 6) & 0x3f) as u8) } #[doc = "Bits 12:18 - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."] #[inline(always)] - pub fn infifo_cnt_l2_ch(&self) -> INFIFO_CNT_L2_CH_R { - INFIFO_CNT_L2_CH_R::new(((self.bits >> 12) & 0x7f) as u8) + pub fn infifo_cnt_l2(&self) -> INFIFO_CNT_L2_R { + INFIFO_CNT_L2_R::new(((self.bits >> 12) & 0x7f) as u8) } #[doc = "Bits 19:23 - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."] #[inline(always)] - pub fn infifo_cnt_l3_ch(&self) -> INFIFO_CNT_L3_CH_R { - INFIFO_CNT_L3_CH_R::new(((self.bits >> 19) & 0x1f) as u8) + pub fn infifo_cnt_l3(&self) -> INFIFO_CNT_L3_R { + INFIFO_CNT_L3_R::new(((self.bits >> 19) & 0x1f) as u8) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn in_remain_under_1b_l3_ch(&self) -> IN_REMAIN_UNDER_1B_L3_CH_R { - IN_REMAIN_UNDER_1B_L3_CH_R::new(((self.bits >> 24) & 1) != 0) + pub fn in_remain_under_1b_l3(&self) -> IN_REMAIN_UNDER_1B_L3_R { + IN_REMAIN_UNDER_1B_L3_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn in_remain_under_2b_l3_ch(&self) -> IN_REMAIN_UNDER_2B_L3_CH_R { - IN_REMAIN_UNDER_2B_L3_CH_R::new(((self.bits >> 25) & 1) != 0) + pub fn in_remain_under_2b_l3(&self) -> IN_REMAIN_UNDER_2B_L3_R { + IN_REMAIN_UNDER_2B_L3_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn in_remain_under_3b_l3_ch(&self) -> IN_REMAIN_UNDER_3B_L3_CH_R { - IN_REMAIN_UNDER_3B_L3_CH_R::new(((self.bits >> 26) & 1) != 0) + pub fn in_remain_under_3b_l3(&self) -> IN_REMAIN_UNDER_3B_L3_R { + IN_REMAIN_UNDER_3B_L3_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - reserved"] #[inline(always)] - pub fn in_remain_under_4b_l3_ch(&self) -> IN_REMAIN_UNDER_4B_L3_CH_R { - IN_REMAIN_UNDER_4B_L3_CH_R::new(((self.bits >> 27) & 1) != 0) + pub fn in_remain_under_4b_l3(&self) -> IN_REMAIN_UNDER_4B_L3_R { + IN_REMAIN_UNDER_4B_L3_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - reserved"] #[inline(always)] - pub fn in_buf_hungry_ch(&self) -> IN_BUF_HUNGRY_CH_R { - IN_BUF_HUNGRY_CH_R::new(((self.bits >> 28) & 1) != 0) + pub fn in_buf_hungry(&self) -> IN_BUF_HUNGRY_R { + IN_BUF_HUNGRY_R::new(((self.bits >> 28) & 1) != 0) } } #[doc = "Receive FIFO status of Rx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [infifo_status_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_conf0_ch.rs b/esp32s3/src/dma/out_conf0_ch.rs index 1ad6d38519..13d7e843a6 100644 --- a/esp32s3/src/dma/out_conf0_ch.rs +++ b/esp32s3/src/dma/out_conf0_ch.rs @@ -34,96 +34,94 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_RST_CH` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH_R = crate::BitReader; -#[doc = "Field `OUT_RST_CH` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `OUT_LOOP_TEST_CH` reader - reserved"] -pub type OUT_LOOP_TEST_CH_R = crate::BitReader; -#[doc = "Field `OUT_LOOP_TEST_CH` writer - reserved"] -pub type OUT_LOOP_TEST_CH_W<'a, const O: u8> = +#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `OUT_LOOP_TEST` reader - reserved"] +pub type OUT_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST` writer - reserved"] +pub type OUT_LOOP_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; +#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `OUT_AUTO_WRBACK_CH` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH_R = crate::BitReader; -#[doc = "Field `OUT_AUTO_WRBACK_CH` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] -pub type OUT_AUTO_WRBACK_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_MODE_CH` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH_R = crate::BitReader; -#[doc = "Field `OUT_EOF_MODE_CH` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] -pub type OUT_EOF_MODE_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `OUTDSCR_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH_R = crate::BitReader; -#[doc = "Field `OUTDSCR_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] -pub type OUTDSCR_BURST_EN_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; -#[doc = "Field `OUT_DATA_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH_R = crate::BitReader; -#[doc = "Field `OUT_DATA_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] -pub type OUT_DATA_BURST_EN_CH_W<'a, const O: u8> = +#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] +pub type OUT_DATA_BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF0_CH_SPEC, bool, O>; impl R { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch(&self) -> OUT_RST_CH_R { - OUT_RST_CH_R::new((self.bits & 1) != 0) + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch(&self) -> OUT_LOOP_TEST_CH_R { - OUT_LOOP_TEST_CH_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R { + OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch(&self) -> OUT_AUTO_WRBACK_CH_R { - OUT_AUTO_WRBACK_CH_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch(&self) -> OUT_EOF_MODE_CH_R { - OUT_EOF_MODE_CH_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R { + OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch(&self) -> OUTDSCR_BURST_EN_CH_R { - OUTDSCR_BURST_EN_CH_R::new(((self.bits >> 4) & 1) != 0) + pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R { + OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch(&self) -> OUT_DATA_BURST_EN_CH_R { - OUT_DATA_BURST_EN_CH_R::new(((self.bits >> 5) & 1) != 0) + pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R { + OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0) } } impl W { #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_ch(&mut self) -> OUT_RST_CH_W<0> { - OUT_RST_CH_W::new(self) + pub fn out_rst(&mut self) -> OUT_RST_W<0> { + OUT_RST_W::new(self) } #[doc = "Bit 1 - reserved"] #[inline(always)] - pub fn out_loop_test_ch(&mut self) -> OUT_LOOP_TEST_CH_W<1> { - OUT_LOOP_TEST_CH_W::new(self) + pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<1> { + OUT_LOOP_TEST_W::new(self) } #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] #[inline(always)] - pub fn out_auto_wrback_ch(&mut self) -> OUT_AUTO_WRBACK_CH_W<2> { - OUT_AUTO_WRBACK_CH_W::new(self) + pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<2> { + OUT_AUTO_WRBACK_W::new(self) } #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"] #[inline(always)] - pub fn out_eof_mode_ch(&mut self) -> OUT_EOF_MODE_CH_W<3> { - OUT_EOF_MODE_CH_W::new(self) + pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<3> { + OUT_EOF_MODE_W::new(self) } #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] #[inline(always)] - pub fn outdscr_burst_en_ch(&mut self) -> OUTDSCR_BURST_EN_CH_W<4> { - OUTDSCR_BURST_EN_CH_W::new(self) + pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<4> { + OUTDSCR_BURST_EN_W::new(self) } #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."] #[inline(always)] - pub fn out_data_burst_en_ch(&mut self) -> OUT_DATA_BURST_EN_CH_W<5> { - OUT_DATA_BURST_EN_CH_W::new(self) + pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<5> { + OUT_DATA_BURST_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_conf1_ch.rs b/esp32s3/src/dma/out_conf1_ch.rs index 143c109390..5e07c0cc6e 100644 --- a/esp32s3/src/dma/out_conf1_ch.rs +++ b/esp32s3/src/dma/out_conf1_ch.rs @@ -34,38 +34,37 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH_R = crate::BitReader; -#[doc = "Field `OUT_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."] -pub type OUT_CHECK_OWNER_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_CONF1_CH_SPEC, bool, O>; -#[doc = "Field `OUT_EXT_MEM_BK_SIZE_CH` reader - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] -pub type OUT_EXT_MEM_BK_SIZE_CH_R = crate::FieldReader; -#[doc = "Field `OUT_EXT_MEM_BK_SIZE_CH` writer - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] -pub type OUT_EXT_MEM_BK_SIZE_CH_W<'a, const O: u8> = +#[doc = "Field `OUT_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_CONF1_CH_SPEC, bool, O>; +#[doc = "Field `OUT_EXT_MEM_BK_SIZE` reader - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] +pub type OUT_EXT_MEM_BK_SIZE_R = crate::FieldReader; +#[doc = "Field `OUT_EXT_MEM_BK_SIZE` writer - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] +pub type OUT_EXT_MEM_BK_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_CONF1_CH_SPEC, u8, u8, 2, O>; impl R { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch(&self) -> OUT_CHECK_OWNER_CH_R { - OUT_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_check_owner(&self) -> OUT_CHECK_OWNER_R { + OUT_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bits 13:14 - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] #[inline(always)] - pub fn out_ext_mem_bk_size_ch(&self) -> OUT_EXT_MEM_BK_SIZE_CH_R { - OUT_EXT_MEM_BK_SIZE_CH_R::new(((self.bits >> 13) & 3) as u8) + pub fn out_ext_mem_bk_size(&self) -> OUT_EXT_MEM_BK_SIZE_R { + OUT_EXT_MEM_BK_SIZE_R::new(((self.bits >> 13) & 3) as u8) } } impl W { #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] #[inline(always)] - pub fn out_check_owner_ch(&mut self) -> OUT_CHECK_OWNER_CH_W<12> { - OUT_CHECK_OWNER_CH_W::new(self) + pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<12> { + OUT_CHECK_OWNER_W::new(self) } #[doc = "Bits 13:14 - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"] #[inline(always)] - pub fn out_ext_mem_bk_size_ch(&mut self) -> OUT_EXT_MEM_BK_SIZE_CH_W<13> { - OUT_EXT_MEM_BK_SIZE_CH_W::new(self) + pub fn out_ext_mem_bk_size(&mut self) -> OUT_EXT_MEM_BK_SIZE_W<13> { + OUT_EXT_MEM_BK_SIZE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_dscr_bf0_ch.rs b/esp32s3/src/dma/out_dscr_bf0_ch.rs index 867abd48b7..a6d682399c 100644 --- a/esp32s3/src/dma/out_dscr_bf0_ch.rs +++ b/esp32s3/src/dma/out_dscr_bf0_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF0_CH` reader - The address of the last outlink descriptor y-1."] -pub type OUTLINK_DSCR_BF0_CH_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] #[inline(always)] - pub fn outlink_dscr_bf0_ch(&self) -> OUTLINK_DSCR_BF0_CH_R { - OUTLINK_DSCR_BF0_CH_R::new(self.bits) + pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R { + OUTLINK_DSCR_BF0_R::new(self.bits) } } #[doc = "The last inlink descriptor address of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf0_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_dscr_bf1_ch.rs b/esp32s3/src/dma/out_dscr_bf1_ch.rs index 077bbcae41..0f341e8870 100644 --- a/esp32s3/src/dma/out_dscr_bf1_ch.rs +++ b/esp32s3/src/dma/out_dscr_bf1_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_BF1_CH` reader - The address of the second-to-last inlink descriptor x-2."] -pub type OUTLINK_DSCR_BF1_CH_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] #[inline(always)] - pub fn outlink_dscr_bf1_ch(&self) -> OUTLINK_DSCR_BF1_CH_R { - OUTLINK_DSCR_BF1_CH_R::new(self.bits) + pub fn outlink_dscr_bf1(&self) -> OUTLINK_DSCR_BF1_R { + OUTLINK_DSCR_BF1_R::new(self.bits) } } #[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_bf1_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_dscr_ch.rs b/esp32s3/src/dma/out_dscr_ch.rs index a14cd0a4a2..5148b84280 100644 --- a/esp32s3/src/dma/out_dscr_ch.rs +++ b/esp32s3/src/dma/out_dscr_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_CH` reader - The address of the current outlink descriptor y."] -pub type OUTLINK_DSCR_CH_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] #[inline(always)] - pub fn outlink_dscr_ch(&self) -> OUTLINK_DSCR_CH_R { - OUTLINK_DSCR_CH_R::new(self.bits) + pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R { + OUTLINK_DSCR_R::new(self.bits) } } #[doc = "Current inlink descriptor address of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_dscr_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_eof_bfr_des_addr_ch.rs b/esp32s3/src/dma/out_eof_bfr_des_addr_ch.rs index 3fed73dc6c..f1383c8bde 100644 --- a/esp32s3/src/dma/out_eof_bfr_des_addr_ch.rs +++ b/esp32s3/src/dma/out_eof_bfr_des_addr_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] -pub type OUT_EOF_BFR_DES_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] #[inline(always)] - pub fn out_eof_bfr_des_addr_ch(&self) -> OUT_EOF_BFR_DES_ADDR_CH_R { - OUT_EOF_BFR_DES_ADDR_CH_R::new(self.bits) + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) } } #[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_bfr_des_addr_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_eof_des_addr_ch.rs b/esp32s3/src/dma/out_eof_des_addr_ch.rs index f6ab39a1cc..a66ab056c1 100644 --- a/esp32s3/src/dma/out_eof_des_addr_ch.rs +++ b/esp32s3/src/dma/out_eof_des_addr_ch.rs @@ -13,13 +13,13 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_EOF_DES_ADDR_CH` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] -pub type OUT_EOF_DES_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; impl R { #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] #[inline(always)] - pub fn out_eof_des_addr_ch(&self) -> OUT_EOF_DES_ADDR_CH_R { - OUT_EOF_DES_ADDR_CH_R::new(self.bits) + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) } } #[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_eof_des_addr_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_int_clr_ch.rs b/esp32s3/src/dma/out_int_clr_ch.rs index e06e6960e0..2b6b60dea2 100644 --- a/esp32s3/src/dma/out_int_clr_ch.rs +++ b/esp32s3/src/dma/out_int_clr_ch.rs @@ -19,70 +19,66 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_DONE_CH_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH_INT_CLR_W<'a, const O: u8> = +#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF_L1` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH_INT_CLR_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_UDF_L1` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH_INT_CLR_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_OVF_L3` writer - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_OVF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_L1_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_L1_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_L1_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_L1_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_L3_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."] -pub type OUTFIFO_OVF_L3_CH_INT_CLR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_L3_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."] -pub type OUTFIFO_UDF_L3_CH_INT_CLR_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_UDF_L3` writer - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_UDF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_CLR_CH_SPEC, bool, O>; impl W { #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch_int_clr(&mut self) -> OUT_DONE_CH_INT_CLR_W<0> { - OUT_DONE_CH_INT_CLR_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<0> { + OUT_DONE_W::new(self) } #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch_int_clr(&mut self) -> OUT_EOF_CH_INT_CLR_W<1> { - OUT_EOF_CH_INT_CLR_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<1> { + OUT_EOF_W::new(self) } #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch_int_clr(&mut self) -> OUT_DSCR_ERR_CH_INT_CLR_W<2> { - OUT_DSCR_ERR_CH_INT_CLR_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<2> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch_int_clr(&mut self) -> OUT_TOTAL_EOF_CH_INT_CLR_W<3> { - OUT_TOTAL_EOF_CH_INT_CLR_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<3> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l1_ch_int_clr(&mut self) -> OUTFIFO_OVF_L1_CH_INT_CLR_W<4> { - OUTFIFO_OVF_L1_CH_INT_CLR_W::new(self) + pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<4> { + OUTFIFO_OVF_L1_W::new(self) } #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l1_ch_int_clr(&mut self) -> OUTFIFO_UDF_L1_CH_INT_CLR_W<5> { - OUTFIFO_UDF_L1_CH_INT_CLR_W::new(self) + pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<5> { + OUTFIFO_UDF_L1_W::new(self) } #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l3_ch_int_clr(&mut self) -> OUTFIFO_OVF_L3_CH_INT_CLR_W<6> { - OUTFIFO_OVF_L3_CH_INT_CLR_W::new(self) + pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<6> { + OUTFIFO_OVF_L3_W::new(self) } #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l3_ch_int_clr(&mut self) -> OUTFIFO_UDF_L3_CH_INT_CLR_W<7> { - OUTFIFO_UDF_L3_CH_INT_CLR_W::new(self) + pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<7> { + OUTFIFO_UDF_L3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_int_ena_ch.rs b/esp32s3/src/dma/out_int_ena_ch.rs index 705f74ea9b..b756cee791 100644 --- a/esp32s3/src/dma/out_int_ena_ch.rs +++ b/esp32s3/src/dma/out_int_ena_ch.rs @@ -34,128 +34,124 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_DONE_CH_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DONE_CH_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH_INT_ENA_W<'a, const O: u8> = +#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_OVF_L1` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUT_EOF_CH_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH_INT_ENA_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_UDF_L1` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUT_DSCR_ERR_CH_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH_INT_ENA_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_OVF_L3` reader - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_OVF_L3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L3` writer - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_OVF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_L1_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_L1_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_L1_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_L1_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_L1_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_L1_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_L1_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_L1_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_OVF_L3_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] -pub type OUTFIFO_OVF_L3_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_L3_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] -pub type OUTFIFO_OVF_L3_CH_INT_ENA_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; -#[doc = "Field `OUTFIFO_UDF_L3_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] -pub type OUTFIFO_UDF_L3_CH_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_L3_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] -pub type OUTFIFO_UDF_L3_CH_INT_ENA_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_UDF_L3` reader - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_UDF_L3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L3` writer - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_UDF_L3_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INT_ENA_CH_SPEC, bool, O>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch_int_ena(&self) -> OUT_DONE_CH_INT_ENA_R { - OUT_DONE_CH_INT_ENA_R::new((self.bits & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch_int_ena(&self) -> OUT_EOF_CH_INT_ENA_R { - OUT_EOF_CH_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch_int_ena(&self) -> OUT_DSCR_ERR_CH_INT_ENA_R { - OUT_DSCR_ERR_CH_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch_int_ena(&self) -> OUT_TOTAL_EOF_CH_INT_ENA_R { - OUT_TOTAL_EOF_CH_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l1_ch_int_ena(&self) -> OUTFIFO_OVF_L1_CH_INT_ENA_R { - OUTFIFO_OVF_L1_CH_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R { + OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l1_ch_int_ena(&self) -> OUTFIFO_UDF_L1_CH_INT_ENA_R { - OUTFIFO_UDF_L1_CH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R { + OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l3_ch_int_ena(&self) -> OUTFIFO_OVF_L3_CH_INT_ENA_R { - OUTFIFO_OVF_L3_CH_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn outfifo_ovf_l3(&self) -> OUTFIFO_OVF_L3_R { + OUTFIFO_OVF_L3_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l3_ch_int_ena(&self) -> OUTFIFO_UDF_L3_CH_INT_ENA_R { - OUTFIFO_UDF_L3_CH_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn outfifo_udf_l3(&self) -> OUTFIFO_UDF_L3_R { + OUTFIFO_UDF_L3_R::new(((self.bits >> 7) & 1) != 0) } } impl W { #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch_int_ena(&mut self) -> OUT_DONE_CH_INT_ENA_W<0> { - OUT_DONE_CH_INT_ENA_W::new(self) + pub fn out_done(&mut self) -> OUT_DONE_W<0> { + OUT_DONE_W::new(self) } #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch_int_ena(&mut self) -> OUT_EOF_CH_INT_ENA_W<1> { - OUT_EOF_CH_INT_ENA_W::new(self) + pub fn out_eof(&mut self) -> OUT_EOF_W<1> { + OUT_EOF_W::new(self) } #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch_int_ena(&mut self) -> OUT_DSCR_ERR_CH_INT_ENA_W<2> { - OUT_DSCR_ERR_CH_INT_ENA_W::new(self) + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<2> { + OUT_DSCR_ERR_W::new(self) } #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch_int_ena(&mut self) -> OUT_TOTAL_EOF_CH_INT_ENA_W<3> { - OUT_TOTAL_EOF_CH_INT_ENA_W::new(self) + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<3> { + OUT_TOTAL_EOF_W::new(self) } #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l1_ch_int_ena(&mut self) -> OUTFIFO_OVF_L1_CH_INT_ENA_W<4> { - OUTFIFO_OVF_L1_CH_INT_ENA_W::new(self) + pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<4> { + OUTFIFO_OVF_L1_W::new(self) } #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l1_ch_int_ena(&mut self) -> OUTFIFO_UDF_L1_CH_INT_ENA_W<5> { - OUTFIFO_UDF_L1_CH_INT_ENA_W::new(self) + pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<5> { + OUTFIFO_UDF_L1_W::new(self) } #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l3_ch_int_ena(&mut self) -> OUTFIFO_OVF_L3_CH_INT_ENA_W<6> { - OUTFIFO_OVF_L3_CH_INT_ENA_W::new(self) + pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<6> { + OUTFIFO_OVF_L3_W::new(self) } #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l3_ch_int_ena(&mut self) -> OUTFIFO_UDF_L3_CH_INT_ENA_W<7> { - OUTFIFO_UDF_L3_CH_INT_ENA_W::new(self) + pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<7> { + OUTFIFO_UDF_L3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_int_raw_ch.rs b/esp32s3/src/dma/out_int_raw_ch.rs index 2e34eec9a1..fbe1496d66 100644 --- a/esp32s3/src/dma/out_int_raw_ch.rs +++ b/esp32s3/src/dma/out_int_raw_ch.rs @@ -13,62 +13,62 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_DONE_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] -pub type OUT_DONE_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] -pub type OUT_EOF_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] -pub type OUT_DSCR_ERR_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] -pub type OUT_TOTAL_EOF_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_L1_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] -pub type OUTFIFO_OVF_L1_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_L1_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] -pub type OUTFIFO_UDF_L1_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_L3_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."] -pub type OUTFIFO_OVF_L3_CH_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_L3_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."] -pub type OUTFIFO_UDF_L3_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] +pub type OUTFIFO_OVF_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] +pub type OUTFIFO_UDF_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."] +pub type OUTFIFO_OVF_L3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."] +pub type OUTFIFO_UDF_L3_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] #[inline(always)] - pub fn out_done_ch_int_raw(&self) -> OUT_DONE_CH_INT_RAW_R { - OUT_DONE_CH_INT_RAW_R::new((self.bits & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] #[inline(always)] - pub fn out_eof_ch_int_raw(&self) -> OUT_EOF_CH_INT_RAW_R { - OUT_EOF_CH_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] #[inline(always)] - pub fn out_dscr_err_ch_int_raw(&self) -> OUT_DSCR_ERR_CH_INT_RAW_R { - OUT_DSCR_ERR_CH_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] #[inline(always)] - pub fn out_total_eof_ch_int_raw(&self) -> OUT_TOTAL_EOF_CH_INT_RAW_R { - OUT_TOTAL_EOF_CH_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."] #[inline(always)] - pub fn outfifo_ovf_l1_ch_int_raw(&self) -> OUTFIFO_OVF_L1_CH_INT_RAW_R { - OUTFIFO_OVF_L1_CH_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R { + OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."] #[inline(always)] - pub fn outfifo_udf_l1_ch_int_raw(&self) -> OUTFIFO_UDF_L1_CH_INT_RAW_R { - OUTFIFO_UDF_L1_CH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R { + OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."] #[inline(always)] - pub fn outfifo_ovf_l3_ch_int_raw(&self) -> OUTFIFO_OVF_L3_CH_INT_RAW_R { - OUTFIFO_OVF_L3_CH_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn outfifo_ovf_l3(&self) -> OUTFIFO_OVF_L3_R { + OUTFIFO_OVF_L3_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."] #[inline(always)] - pub fn outfifo_udf_l3_ch_int_raw(&self) -> OUTFIFO_UDF_L3_CH_INT_RAW_R { - OUTFIFO_UDF_L3_CH_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn outfifo_udf_l3(&self) -> OUTFIFO_UDF_L3_R { + OUTFIFO_UDF_L3_R::new(((self.bits >> 7) & 1) != 0) } } #[doc = "Raw status interrupt of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_int_raw_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_int_st_ch.rs b/esp32s3/src/dma/out_int_st_ch.rs index db6d3c09d2..a40d727944 100644 --- a/esp32s3/src/dma/out_int_st_ch.rs +++ b/esp32s3/src/dma/out_int_st_ch.rs @@ -13,62 +13,62 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUT_DONE_CH_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] -pub type OUT_DONE_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_EOF_CH_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] -pub type OUT_EOF_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_DSCR_ERR_CH_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] -pub type OUT_DSCR_ERR_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] -pub type OUT_TOTAL_EOF_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_L1_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] -pub type OUTFIFO_OVF_L1_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_L1_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] -pub type OUTFIFO_UDF_L1_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_OVF_L3_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] -pub type OUTFIFO_OVF_L3_CH_INT_ST_R = crate::BitReader; -#[doc = "Field `OUTFIFO_UDF_L3_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] -pub type OUTFIFO_UDF_L3_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L3` reader - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_OVF_L3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L3` reader - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_UDF_L3_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] #[inline(always)] - pub fn out_done_ch_int_st(&self) -> OUT_DONE_CH_INT_ST_R { - OUT_DONE_CH_INT_ST_R::new((self.bits & 1) != 0) + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_eof_ch_int_st(&self) -> OUT_EOF_CH_INT_ST_R { - OUT_EOF_CH_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] #[inline(always)] - pub fn out_dscr_err_ch_int_st(&self) -> OUT_DSCR_ERR_CH_INT_ST_R { - OUT_DSCR_ERR_CH_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] #[inline(always)] - pub fn out_total_eof_ch_int_st(&self) -> OUT_TOTAL_EOF_CH_INT_ST_R { - OUT_TOTAL_EOF_CH_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l1_ch_int_st(&self) -> OUTFIFO_OVF_L1_CH_INT_ST_R { - OUTFIFO_OVF_L1_CH_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R { + OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l1_ch_int_st(&self) -> OUTFIFO_UDF_L1_CH_INT_ST_R { - OUTFIFO_UDF_L1_CH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R { + OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_ovf_l3_ch_int_st(&self) -> OUTFIFO_OVF_L3_CH_INT_ST_R { - OUTFIFO_OVF_L3_CH_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn outfifo_ovf_l3(&self) -> OUTFIFO_OVF_L3_R { + OUTFIFO_OVF_L3_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] #[inline(always)] - pub fn outfifo_udf_l3_ch_int_st(&self) -> OUTFIFO_UDF_L3_CH_INT_ST_R { - OUTFIFO_UDF_L3_CH_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn outfifo_udf_l3(&self) -> OUTFIFO_UDF_L3_R { + OUTFIFO_UDF_L3_R::new(((self.bits >> 7) & 1) != 0) } } #[doc = "Masked interrupt of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_int_st_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_link_ch.rs b/esp32s3/src/dma/out_link_ch.rs index 74176d7c04..ab990ed832 100644 --- a/esp32s3/src/dma/out_link_ch.rs +++ b/esp32s3/src/dma/out_link_ch.rs @@ -34,73 +34,72 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTLINK_ADDR_CH` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH_R = crate::FieldReader; -#[doc = "Field `OUTLINK_ADDR_CH` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] -pub type OUTLINK_ADDR_CH_W<'a, const O: u8> = +#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_LINK_CH_SPEC, u32, u32, 20, O>; -#[doc = "Field `OUTLINK_STOP_CH` reader - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH_R = crate::BitReader; -#[doc = "Field `OUTLINK_STOP_CH` writer - Set this bit to stop dealing with the outlink descriptors."] -pub type OUTLINK_STOP_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH_SPEC, bool, O>; -#[doc = "Field `OUTLINK_START_CH` reader - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH_R = crate::BitReader; -#[doc = "Field `OUTLINK_START_CH` writer - Set this bit to start dealing with the outlink descriptors."] -pub type OUTLINK_START_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH_SPEC, bool, O>; -#[doc = "Field `OUTLINK_RESTART_CH` reader - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH_R = crate::BitReader; -#[doc = "Field `OUTLINK_RESTART_CH` writer - Set this bit to restart a new outlink from the last address."] -pub type OUTLINK_RESTART_CH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, OUT_LINK_CH_SPEC, bool, O>; -#[doc = "Field `OUTLINK_PARK_CH` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] -pub type OUTLINK_PARK_CH_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH_SPEC, bool, O>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH_SPEC, bool, O>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_LINK_CH_SPEC, bool, O>; +#[doc = "Field `OUTLINK_PARK` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; impl R { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch(&self) -> OUTLINK_ADDR_CH_R { - OUTLINK_ADDR_CH_R::new((self.bits & 0x000f_ffff) as u32) + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch(&self) -> OUTLINK_STOP_CH_R { - OUTLINK_STOP_CH_R::new(((self.bits >> 20) & 1) != 0) + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch(&self) -> OUTLINK_START_CH_R { - OUTLINK_START_CH_R::new(((self.bits >> 21) & 1) != 0) + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch(&self) -> OUTLINK_RESTART_CH_R { - OUTLINK_RESTART_CH_R::new(((self.bits >> 22) & 1) != 0) + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] #[inline(always)] - pub fn outlink_park_ch(&self) -> OUTLINK_PARK_CH_R { - OUTLINK_PARK_CH_R::new(((self.bits >> 23) & 1) != 0) + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 23) & 1) != 0) } } impl W { #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."] #[inline(always)] - pub fn outlink_addr_ch(&mut self) -> OUTLINK_ADDR_CH_W<0> { - OUTLINK_ADDR_CH_W::new(self) + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<0> { + OUTLINK_ADDR_W::new(self) } #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_stop_ch(&mut self) -> OUTLINK_STOP_CH_W<20> { - OUTLINK_STOP_CH_W::new(self) + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<20> { + OUTLINK_STOP_W::new(self) } #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] #[inline(always)] - pub fn outlink_start_ch(&mut self) -> OUTLINK_START_CH_W<21> { - OUTLINK_START_CH_W::new(self) + pub fn outlink_start(&mut self) -> OUTLINK_START_W<21> { + OUTLINK_START_W::new(self) } #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] #[inline(always)] - pub fn outlink_restart_ch(&mut self) -> OUTLINK_RESTART_CH_W<22> { - OUTLINK_RESTART_CH_W::new(self) + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<22> { + OUTLINK_RESTART_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_peri_sel_ch.rs b/esp32s3/src/dma/out_peri_sel_ch.rs index fea4b4559f..073d8f9c1c 100644 --- a/esp32s3/src/dma/out_peri_sel_ch.rs +++ b/esp32s3/src/dma/out_peri_sel_ch.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `PERI_OUT_SEL_CH` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] -pub type PERI_OUT_SEL_CH_R = crate::FieldReader; -#[doc = "Field `PERI_OUT_SEL_CH` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] -pub type PERI_OUT_SEL_CH_W<'a, const O: u8> = +#[doc = "Field `PERI_OUT_SEL` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] +pub type PERI_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] +pub type PERI_OUT_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PERI_SEL_CH_SPEC, u8, u8, 6, O>; impl R { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] #[inline(always)] - pub fn peri_out_sel_ch(&self) -> PERI_OUT_SEL_CH_R { - PERI_OUT_SEL_CH_R::new((self.bits & 0x3f) as u8) + pub fn peri_out_sel(&self) -> PERI_OUT_SEL_R { + PERI_OUT_SEL_R::new((self.bits & 0x3f) as u8) } } impl W { #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."] #[inline(always)] - pub fn peri_out_sel_ch(&mut self) -> PERI_OUT_SEL_CH_W<0> { - PERI_OUT_SEL_CH_W::new(self) + pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<0> { + PERI_OUT_SEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_pri_ch.rs b/esp32s3/src/dma/out_pri_ch.rs index 4f2d73b860..99db49fb8c 100644 --- a/esp32s3/src/dma/out_pri_ch.rs +++ b/esp32s3/src/dma/out_pri_ch.rs @@ -34,22 +34,22 @@ impl From> for W { W(writer) } } -#[doc = "Field `TX_PRI_CH` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH_R = crate::FieldReader; -#[doc = "Field `TX_PRI_CH` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."] -pub type TX_PRI_CH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PRI_CH_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_PRI` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."] +pub type TX_PRI_R = crate::FieldReader; +#[doc = "Field `TX_PRI` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."] +pub type TX_PRI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PRI_CH_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch(&self) -> TX_PRI_CH_R { - TX_PRI_CH_R::new((self.bits & 0x0f) as u8) + pub fn tx_pri(&self) -> TX_PRI_R { + TX_PRI_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."] #[inline(always)] - pub fn tx_pri_ch(&mut self) -> TX_PRI_CH_W<0> { - TX_PRI_CH_W::new(self) + pub fn tx_pri(&mut self) -> TX_PRI_W<0> { + TX_PRI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_push_ch.rs b/esp32s3/src/dma/out_push_ch.rs index 7da42a6660..90fb4cd144 100644 --- a/esp32s3/src/dma/out_push_ch.rs +++ b/esp32s3/src/dma/out_push_ch.rs @@ -34,37 +34,37 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUTFIFO_WDATA_CH` reader - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_WDATA_CH` writer - This register stores the data that need to be pushed into DMA FIFO."] -pub type OUTFIFO_WDATA_CH_W<'a, const O: u8> = +#[doc = "Field `OUTFIFO_WDATA` reader - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA` writer - This register stores the data that need to be pushed into DMA FIFO."] +pub type OUTFIFO_WDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_PUSH_CH_SPEC, u16, u16, 9, O>; -#[doc = "Field `OUTFIFO_PUSH_CH` reader - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_PUSH_CH` writer - Set this bit to push data into DMA FIFO."] -pub type OUTFIFO_PUSH_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_PUSH_CH_SPEC, bool, O>; +#[doc = "Field `OUTFIFO_PUSH` reader - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH` writer - Set this bit to push data into DMA FIFO."] +pub type OUTFIFO_PUSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_PUSH_CH_SPEC, bool, O>; impl R { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch(&self) -> OUTFIFO_WDATA_CH_R { - OUTFIFO_WDATA_CH_R::new((self.bits & 0x01ff) as u16) + pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R { + OUTFIFO_WDATA_R::new((self.bits & 0x01ff) as u16) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch(&self) -> OUTFIFO_PUSH_CH_R { - OUTFIFO_PUSH_CH_R::new(((self.bits >> 9) & 1) != 0) + pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R { + OUTFIFO_PUSH_R::new(((self.bits >> 9) & 1) != 0) } } impl W { #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."] #[inline(always)] - pub fn outfifo_wdata_ch(&mut self) -> OUTFIFO_WDATA_CH_W<0> { - OUTFIFO_WDATA_CH_W::new(self) + pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<0> { + OUTFIFO_WDATA_W::new(self) } #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."] #[inline(always)] - pub fn outfifo_push_ch(&mut self) -> OUTFIFO_PUSH_CH_W<9> { - OUTFIFO_PUSH_CH_W::new(self) + pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<9> { + OUTFIFO_PUSH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_sram_size_ch.rs b/esp32s3/src/dma/out_sram_size_ch.rs index 4615a01f95..8b7f73013d 100644 --- a/esp32s3/src/dma/out_sram_size_ch.rs +++ b/esp32s3/src/dma/out_sram_size_ch.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `OUT_SIZE_CH` reader - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] -pub type OUT_SIZE_CH_R = crate::FieldReader; -#[doc = "Field `OUT_SIZE_CH` writer - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] -pub type OUT_SIZE_CH_W<'a, const O: u8> = +#[doc = "Field `OUT_SIZE` reader - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] +pub type OUT_SIZE_R = crate::FieldReader; +#[doc = "Field `OUT_SIZE` writer - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] +pub type OUT_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_SRAM_SIZE_CH_SPEC, u8, u8, 7, O>; impl R { #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] #[inline(always)] - pub fn out_size_ch(&self) -> OUT_SIZE_CH_R { - OUT_SIZE_CH_R::new((self.bits & 0x7f) as u8) + pub fn out_size(&self) -> OUT_SIZE_R { + OUT_SIZE_R::new((self.bits & 0x7f) as u8) } } impl W { #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."] #[inline(always)] - pub fn out_size_ch(&mut self) -> OUT_SIZE_CH_W<0> { - OUT_SIZE_CH_W::new(self) + pub fn out_size(&mut self) -> OUT_SIZE_W<0> { + OUT_SIZE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/out_state_ch.rs b/esp32s3/src/dma/out_state_ch.rs index b238290663..320933c415 100644 --- a/esp32s3/src/dma/out_state_ch.rs +++ b/esp32s3/src/dma/out_state_ch.rs @@ -13,27 +13,27 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTLINK_DSCR_ADDR_CH` reader - This register stores the current outlink descriptor's address."] -pub type OUTLINK_DSCR_ADDR_CH_R = crate::FieldReader; -#[doc = "Field `OUT_DSCR_STATE_CH` reader - reserved"] -pub type OUT_DSCR_STATE_CH_R = crate::FieldReader; -#[doc = "Field `OUT_STATE_CH` reader - reserved"] -pub type OUT_STATE_CH_R = crate::FieldReader; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - reserved"] +pub type OUT_STATE_R = crate::FieldReader; impl R { #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] #[inline(always)] - pub fn outlink_dscr_addr_ch(&self) -> OUTLINK_DSCR_ADDR_CH_R { - OUTLINK_DSCR_ADDR_CH_R::new((self.bits & 0x0003_ffff) as u32) + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bits 18:19 - reserved"] #[inline(always)] - pub fn out_dscr_state_ch(&self) -> OUT_DSCR_STATE_CH_R { - OUT_DSCR_STATE_CH_R::new(((self.bits >> 18) & 3) as u8) + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:22 - reserved"] #[inline(always)] - pub fn out_state_ch(&self) -> OUT_STATE_CH_R { - OUT_STATE_CH_R::new(((self.bits >> 20) & 7) as u8) + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) } } #[doc = "Transmit status of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_state_ch](index.html) module"] diff --git a/esp32s3/src/dma/out_wight_ch.rs b/esp32s3/src/dma/out_wight_ch.rs index 966fb40d86..62479c60be 100644 --- a/esp32s3/src/dma/out_wight_ch.rs +++ b/esp32s3/src/dma/out_wight_ch.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `TX_WEIGHT_CH` reader - The weight of Tx channel 0."] -pub type TX_WEIGHT_CH_R = crate::FieldReader; -#[doc = "Field `TX_WEIGHT_CH` writer - The weight of Tx channel 0."] -pub type TX_WEIGHT_CH_W<'a, const O: u8> = +#[doc = "Field `TX_WEIGHT` reader - The weight of Tx channel 0."] +pub type TX_WEIGHT_R = crate::FieldReader; +#[doc = "Field `TX_WEIGHT` writer - The weight of Tx channel 0."] +pub type TX_WEIGHT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OUT_WIGHT_CH_SPEC, u8, u8, 4, O>; impl R { #[doc = "Bits 8:11 - The weight of Tx channel 0."] #[inline(always)] - pub fn tx_weight_ch(&self) -> TX_WEIGHT_CH_R { - TX_WEIGHT_CH_R::new(((self.bits >> 8) & 0x0f) as u8) + pub fn tx_weight(&self) -> TX_WEIGHT_R { + TX_WEIGHT_R::new(((self.bits >> 8) & 0x0f) as u8) } } impl W { #[doc = "Bits 8:11 - The weight of Tx channel 0."] #[inline(always)] - pub fn tx_weight_ch(&mut self) -> TX_WEIGHT_CH_W<8> { - TX_WEIGHT_CH_W::new(self) + pub fn tx_weight(&mut self) -> TX_WEIGHT_W<8> { + TX_WEIGHT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32s3/src/dma/outfifo_status_ch.rs b/esp32s3/src/dma/outfifo_status_ch.rs index d1ee7833d0..01abb039a7 100644 --- a/esp32s3/src/dma/outfifo_status_ch.rs +++ b/esp32s3/src/dma/outfifo_status_ch.rs @@ -13,97 +13,97 @@ impl From> for R { R(reader) } } -#[doc = "Field `OUTFIFO_FULL_L1_CH` reader - L1 Tx FIFO full signal for Tx channel 0."] -pub type OUTFIFO_FULL_L1_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_L1_CH` reader - L1 Tx FIFO empty signal for Tx channel 0."] -pub type OUTFIFO_EMPTY_L1_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_FULL_L2_CH` reader - L2 Tx FIFO full signal for Tx channel 0."] -pub type OUTFIFO_FULL_L2_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_L2_CH` reader - L2 Tx FIFO empty signal for Tx channel 0."] -pub type OUTFIFO_EMPTY_L2_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_FULL_L3_CH` reader - L3 Tx FIFO full signal for Tx channel 0."] -pub type OUTFIFO_FULL_L3_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_EMPTY_L3_CH` reader - L3 Tx FIFO empty signal for Tx channel 0."] -pub type OUTFIFO_EMPTY_L3_CH_R = crate::BitReader; -#[doc = "Field `OUTFIFO_CNT_L1_CH` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] -pub type OUTFIFO_CNT_L1_CH_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_CNT_L2_CH` reader - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."] -pub type OUTFIFO_CNT_L2_CH_R = crate::FieldReader; -#[doc = "Field `OUTFIFO_CNT_L3_CH` reader - The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0."] -pub type OUTFIFO_CNT_L3_CH_R = crate::FieldReader; -#[doc = "Field `OUT_REMAIN_UNDER_1B_L3_CH` reader - reserved"] -pub type OUT_REMAIN_UNDER_1B_L3_CH_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_2B_L3_CH` reader - reserved"] -pub type OUT_REMAIN_UNDER_2B_L3_CH_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_3B_L3_CH` reader - reserved"] -pub type OUT_REMAIN_UNDER_3B_L3_CH_R = crate::BitReader; -#[doc = "Field `OUT_REMAIN_UNDER_4B_L3_CH` reader - reserved"] -pub type OUT_REMAIN_UNDER_4B_L3_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL_L1` reader - L1 Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L1` reader - L1 Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_L1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL_L2` reader - L2 Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_L2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L2` reader - L2 Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_L2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_FULL_L3` reader - L3 Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_L3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L3` reader - L3 Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_L3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L1` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_L1_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_CNT_L2` reader - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_L2_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_CNT_L3` reader - The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_L3_R = crate::FieldReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B_L3` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_L3_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B_L3` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_L3_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B_L3` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_L3_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B_L3` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_L3_R = crate::BitReader; impl R { #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_full_l1_ch(&self) -> OUTFIFO_FULL_L1_CH_R { - OUTFIFO_FULL_L1_CH_R::new((self.bits & 1) != 0) + pub fn outfifo_full_l1(&self) -> OUTFIFO_FULL_L1_R { + OUTFIFO_FULL_L1_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_empty_l1_ch(&self) -> OUTFIFO_EMPTY_L1_CH_R { - OUTFIFO_EMPTY_L1_CH_R::new(((self.bits >> 1) & 1) != 0) + pub fn outfifo_empty_l1(&self) -> OUTFIFO_EMPTY_L1_R { + OUTFIFO_EMPTY_L1_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - L2 Tx FIFO full signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_full_l2_ch(&self) -> OUTFIFO_FULL_L2_CH_R { - OUTFIFO_FULL_L2_CH_R::new(((self.bits >> 2) & 1) != 0) + pub fn outfifo_full_l2(&self) -> OUTFIFO_FULL_L2_R { + OUTFIFO_FULL_L2_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - L2 Tx FIFO empty signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_empty_l2_ch(&self) -> OUTFIFO_EMPTY_L2_CH_R { - OUTFIFO_EMPTY_L2_CH_R::new(((self.bits >> 3) & 1) != 0) + pub fn outfifo_empty_l2(&self) -> OUTFIFO_EMPTY_L2_R { + OUTFIFO_EMPTY_L2_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - L3 Tx FIFO full signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_full_l3_ch(&self) -> OUTFIFO_FULL_L3_CH_R { - OUTFIFO_FULL_L3_CH_R::new(((self.bits >> 4) & 1) != 0) + pub fn outfifo_full_l3(&self) -> OUTFIFO_FULL_L3_R { + OUTFIFO_FULL_L3_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - L3 Tx FIFO empty signal for Tx channel 0."] #[inline(always)] - pub fn outfifo_empty_l3_ch(&self) -> OUTFIFO_EMPTY_L3_CH_R { - OUTFIFO_EMPTY_L3_CH_R::new(((self.bits >> 5) & 1) != 0) + pub fn outfifo_empty_l3(&self) -> OUTFIFO_EMPTY_L3_R { + OUTFIFO_EMPTY_L3_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bits 6:10 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] #[inline(always)] - pub fn outfifo_cnt_l1_ch(&self) -> OUTFIFO_CNT_L1_CH_R { - OUTFIFO_CNT_L1_CH_R::new(((self.bits >> 6) & 0x1f) as u8) + pub fn outfifo_cnt_l1(&self) -> OUTFIFO_CNT_L1_R { + OUTFIFO_CNT_L1_R::new(((self.bits >> 6) & 0x1f) as u8) } #[doc = "Bits 11:17 - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."] #[inline(always)] - pub fn outfifo_cnt_l2_ch(&self) -> OUTFIFO_CNT_L2_CH_R { - OUTFIFO_CNT_L2_CH_R::new(((self.bits >> 11) & 0x7f) as u8) + pub fn outfifo_cnt_l2(&self) -> OUTFIFO_CNT_L2_R { + OUTFIFO_CNT_L2_R::new(((self.bits >> 11) & 0x7f) as u8) } #[doc = "Bits 18:22 - The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0."] #[inline(always)] - pub fn outfifo_cnt_l3_ch(&self) -> OUTFIFO_CNT_L3_CH_R { - OUTFIFO_CNT_L3_CH_R::new(((self.bits >> 18) & 0x1f) as u8) + pub fn outfifo_cnt_l3(&self) -> OUTFIFO_CNT_L3_R { + OUTFIFO_CNT_L3_R::new(((self.bits >> 18) & 0x1f) as u8) } #[doc = "Bit 23 - reserved"] #[inline(always)] - pub fn out_remain_under_1b_l3_ch(&self) -> OUT_REMAIN_UNDER_1B_L3_CH_R { - OUT_REMAIN_UNDER_1B_L3_CH_R::new(((self.bits >> 23) & 1) != 0) + pub fn out_remain_under_1b_l3(&self) -> OUT_REMAIN_UNDER_1B_L3_R { + OUT_REMAIN_UNDER_1B_L3_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - reserved"] #[inline(always)] - pub fn out_remain_under_2b_l3_ch(&self) -> OUT_REMAIN_UNDER_2B_L3_CH_R { - OUT_REMAIN_UNDER_2B_L3_CH_R::new(((self.bits >> 24) & 1) != 0) + pub fn out_remain_under_2b_l3(&self) -> OUT_REMAIN_UNDER_2B_L3_R { + OUT_REMAIN_UNDER_2B_L3_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - reserved"] #[inline(always)] - pub fn out_remain_under_3b_l3_ch(&self) -> OUT_REMAIN_UNDER_3B_L3_CH_R { - OUT_REMAIN_UNDER_3B_L3_CH_R::new(((self.bits >> 25) & 1) != 0) + pub fn out_remain_under_3b_l3(&self) -> OUT_REMAIN_UNDER_3B_L3_R { + OUT_REMAIN_UNDER_3B_L3_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - reserved"] #[inline(always)] - pub fn out_remain_under_4b_l3_ch(&self) -> OUT_REMAIN_UNDER_4B_L3_CH_R { - OUT_REMAIN_UNDER_4B_L3_CH_R::new(((self.bits >> 26) & 1) != 0) + pub fn out_remain_under_4b_l3(&self) -> OUT_REMAIN_UNDER_4B_L3_R { + OUT_REMAIN_UNDER_4B_L3_R::new(((self.bits >> 26) & 1) != 0) } } #[doc = "Transmit FIFO status of Tx channel 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outfifo_status_ch](index.html) module"] diff --git a/esp32s3/svd/esp32s3.base.svd b/esp32s3/svd/esp32s3.base.svd index efe53d34e7..b1222ec89b 100644 --- a/esp32s3/svd/esp32s3.base.svd +++ b/esp32s3/svd/esp32s3.base.svd @@ -4,7 +4,7 @@ ESPRESSIF ESP32-S3 ESP32-S3 - 11 + 12 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) Copyright 2022 Espressif Systems (Shanghai) PTE LTD @@ -4444,35 +4444,35 @@ 0x20 - IN_RST_CH + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -4490,21 +4490,21 @@ 0x0000000C - DMA_INFIFO_FULL_THRS_CH + DMA_INFIFO_FULL_THRS This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register. 0 12 read-write - IN_CHECK_OWNER_CH + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write - IN_EXT_MEM_BK_SIZE_CH + IN_EXT_MEM_BK_SIZE Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved 13 2 @@ -4521,70 +4521,70 @@ 0x20 - IN_DONE_CH_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 read-only - IN_SUC_EOF_CH_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-only - IN_ERR_EOF_CH_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 read-only - IN_DSCR_ERR_CH_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 3 1 read-only - IN_DSCR_EMPTY_CH_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 4 1 read-only - INFIFO_FULL_WM_CH_INT_RAW + INFIFO_FULL_WM The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0. 5 1 read-only - INFIFO_OVF_L1_CH_INT_RAW + INFIFO_OVF_L1 This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 6 1 read-only - INFIFO_UDF_L1_CH_INT_RAW + INFIFO_UDF_L1 This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 7 1 read-only - INFIFO_OVF_L3_CH_INT_RAW + INFIFO_OVF_L3 This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. 8 1 read-only - INFIFO_UDF_L3_CH_INT_RAW + INFIFO_UDF_L3 This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. 9 1 @@ -4601,70 +4601,70 @@ 0x20 - IN_DONE_CH_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - IN_DSCR_ERR_CH_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only - IN_DSCR_EMPTY_CH_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-only - INFIFO_FULL_WM_CH_INT_ST + INFIFO_FULL_WM The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt. 5 1 read-only - INFIFO_OVF_L1_CH_INT_ST + INFIFO_OVF_L1 The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 6 1 read-only - INFIFO_UDF_L1_CH_INT_ST + INFIFO_UDF_L1 The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 7 1 read-only - INFIFO_OVF_L3_CH_INT_ST + INFIFO_OVF_L3 The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. 8 1 read-only - INFIFO_UDF_L3_CH_INT_ST + INFIFO_UDF_L3 The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. 9 1 @@ -4681,70 +4681,70 @@ 0x20 - IN_DONE_CH_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - IN_DSCR_ERR_CH_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write - IN_DSCR_EMPTY_CH_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-write - INFIFO_FULL_WM_CH_INT_ENA + INFIFO_FULL_WM The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt. 5 1 read-write - INFIFO_OVF_L1_CH_INT_ENA + INFIFO_OVF_L1 The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 6 1 read-write - INFIFO_UDF_L1_CH_INT_ENA + INFIFO_UDF_L1 The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 7 1 read-write - INFIFO_OVF_L3_CH_INT_ENA + INFIFO_OVF_L3 The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. 8 1 read-write - INFIFO_UDF_L3_CH_INT_ENA + INFIFO_UDF_L3 The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. 9 1 @@ -4761,70 +4761,70 @@ 0x20 - IN_DONE_CH_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - IN_DSCR_ERR_CH_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 3 1 write-only - IN_DSCR_EMPTY_CH_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 write-only - DMA_INFIFO_FULL_WM_CH_INT_CLR + DMA_INFIFO_FULL_WM Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt. 5 1 write-only - INFIFO_OVF_L1_CH_INT_CLR + INFIFO_OVF_L1 Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 6 1 write-only - INFIFO_UDF_L1_CH_INT_CLR + INFIFO_UDF_L1 Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 7 1 write-only - INFIFO_OVF_L3_CH_INT_CLR + INFIFO_OVF_L3 Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. 8 1 write-only - INFIFO_UDF_L3_CH_INT_CLR + INFIFO_UDF_L3 Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. 9 1 @@ -4842,98 +4842,98 @@ 0x0F00003A - INFIFO_FULL_L1_CH + INFIFO_FULL_L1 L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_L1_CH + INFIFO_EMPTY_L1 L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_FULL_L2_CH + INFIFO_FULL_L2 L2 Rx FIFO full signal for Rx channel 0. 2 1 read-only - INFIFO_EMPTY_L2_CH + INFIFO_EMPTY_L2 L2 Rx FIFO empty signal for Rx channel 0. 3 1 read-only - INFIFO_FULL_L3_CH + INFIFO_FULL_L3 L3 Rx FIFO full signal for Rx channel 0. 4 1 read-only - INFIFO_EMPTY_L3_CH + INFIFO_EMPTY_L3 L3 Rx FIFO empty signal for Rx channel 0. 5 1 read-only - INFIFO_CNT_L1_CH + INFIFO_CNT_L1 The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 6 6 read-only - INFIFO_CNT_L2_CH + INFIFO_CNT_L2 The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. 12 7 read-only - INFIFO_CNT_L3_CH + INFIFO_CNT_L3 The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. 19 5 read-only - IN_REMAIN_UNDER_1B_L3_CH + IN_REMAIN_UNDER_1B_L3 reserved 24 1 read-only - IN_REMAIN_UNDER_2B_L3_CH + IN_REMAIN_UNDER_2B_L3 reserved 25 1 read-only - IN_REMAIN_UNDER_3B_L3_CH + IN_REMAIN_UNDER_3B_L3 reserved 26 1 read-only - IN_REMAIN_UNDER_4B_L3_CH + IN_REMAIN_UNDER_4B_L3 reserved 27 1 read-only - IN_BUF_HUNGRY_CH + IN_BUF_HUNGRY reserved 28 1 @@ -4951,14 +4951,14 @@ 0x00000800 - INFIFO_RDATA_CH + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -4976,42 +4976,42 @@ 0x01100000 - INLINK_ADDR_CH + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -5028,21 +5028,21 @@ 0x20 - INLINK_DSCR_ADDR_CH + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH + IN_STATE reserved 20 3 @@ -5059,7 +5059,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5076,7 +5076,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -5093,7 +5093,7 @@ 0x20 - INLINK_DSCR_CH + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -5110,7 +5110,7 @@ 0x20 - INLINK_DSCR_BF0_CH + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -5127,7 +5127,7 @@ 0x20 - INLINK_DSCR_BF1_CH + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5145,7 +5145,7 @@ 0x00000F00 - RX_WEIGHT_CH + RX_WEIGHT The weight of Rx channel 0. 8 4 @@ -5162,7 +5162,7 @@ 0x20 - RX_PRI_CH + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5180,7 +5180,7 @@ 0x0000003F - PERI_IN_SEL_CH + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. 0 6 @@ -5198,42 +5198,42 @@ 0x00000008 - OUT_RST_CH + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -5250,14 +5250,14 @@ 0x20 - OUT_CHECK_OWNER_CH + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write - OUT_EXT_MEM_BK_SIZE_CH + OUT_EXT_MEM_BK_SIZE Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved 13 2 @@ -5274,56 +5274,56 @@ 0x20 - OUT_DONE_CH_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 1 read-only - OUT_EOF_CH_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 1 1 read-only - OUT_DSCR_ERR_CH_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 2 1 read-only - OUT_TOTAL_EOF_CH_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 3 1 read-only - OUTFIFO_OVF_L1_CH_INT_RAW + OUTFIFO_OVF_L1 This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 4 1 read-only - OUTFIFO_UDF_L1_CH_INT_RAW + OUTFIFO_UDF_L1 This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 5 1 read-only - OUTFIFO_OVF_L3_CH_INT_RAW + OUTFIFO_OVF_L3 This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. 6 1 read-only - OUTFIFO_UDF_L3_CH_INT_RAW + OUTFIFO_UDF_L3 This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. 7 1 @@ -5340,56 +5340,56 @@ 0x20 - OUT_DONE_CH_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 read-only - OUT_EOF_CH_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 read-only - OUT_DSCR_ERR_CH_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-only - OUT_TOTAL_EOF_CH_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-only - OUTFIFO_OVF_L1_CH_INT_ST + OUTFIFO_OVF_L1 The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only - OUTFIFO_UDF_L1_CH_INT_ST + OUTFIFO_UDF_L1 The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only - OUTFIFO_OVF_L3_CH_INT_ST + OUTFIFO_OVF_L3 The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. 6 1 read-only - OUTFIFO_UDF_L3_CH_INT_ST + OUTFIFO_UDF_L3 The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. 7 1 @@ -5406,56 +5406,56 @@ 0x20 - OUT_DONE_CH_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 read-write - OUT_EOF_CH_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 1 read-write - OUT_DSCR_ERR_CH_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-write - OUT_TOTAL_EOF_CH_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-write - OUTFIFO_OVF_L1_CH_INT_ENA + OUTFIFO_OVF_L1 The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write - OUTFIFO_UDF_L1_CH_INT_ENA + OUTFIFO_UDF_L1 The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write - OUTFIFO_OVF_L3_CH_INT_ENA + OUTFIFO_OVF_L3 The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. 6 1 read-write - OUTFIFO_UDF_L3_CH_INT_ENA + OUTFIFO_UDF_L3 The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. 7 1 @@ -5472,56 +5472,56 @@ 0x20 - OUT_DONE_CH_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 write-only - OUT_EOF_CH_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 1 write-only - OUT_DSCR_ERR_CH_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 write-only - OUT_TOTAL_EOF_CH_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 write-only - OUTFIFO_OVF_L1_CH_INT_CLR + OUTFIFO_OVF_L1 Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only - OUTFIFO_UDF_L1_CH_INT_CLR + OUTFIFO_UDF_L1 Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only - OUTFIFO_OVF_L3_CH_INT_CLR + OUTFIFO_OVF_L3 Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. 6 1 write-only - OUTFIFO_UDF_L3_CH_INT_CLR + OUTFIFO_UDF_L3 Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. 7 1 @@ -5539,91 +5539,91 @@ 0x0780002A - OUTFIFO_FULL_L1_CH + OUTFIFO_FULL_L1 L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_L1_CH + OUTFIFO_EMPTY_L1 L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_FULL_L2_CH + OUTFIFO_FULL_L2 L2 Tx FIFO full signal for Tx channel 0. 2 1 read-only - OUTFIFO_EMPTY_L2_CH + OUTFIFO_EMPTY_L2 L2 Tx FIFO empty signal for Tx channel 0. 3 1 read-only - OUTFIFO_FULL_L3_CH + OUTFIFO_FULL_L3 L3 Tx FIFO full signal for Tx channel 0. 4 1 read-only - OUTFIFO_EMPTY_L3_CH + OUTFIFO_EMPTY_L3 L3 Tx FIFO empty signal for Tx channel 0. 5 1 read-only - OUTFIFO_CNT_L1_CH + OUTFIFO_CNT_L1 The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 6 5 read-only - OUTFIFO_CNT_L2_CH + OUTFIFO_CNT_L2 The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. 11 7 read-only - OUTFIFO_CNT_L3_CH + OUTFIFO_CNT_L3 The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0. 18 5 read-only - OUT_REMAIN_UNDER_1B_L3_CH + OUT_REMAIN_UNDER_1B_L3 reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_L3_CH + OUT_REMAIN_UNDER_2B_L3 reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_L3_CH + OUT_REMAIN_UNDER_3B_L3 reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_L3_CH + OUT_REMAIN_UNDER_4B_L3 reserved 26 1 @@ -5640,14 +5640,14 @@ 0x20 - OUTFIFO_WDATA_CH + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5665,35 +5665,35 @@ 0x00800000 - OUTLINK_ADDR_CH + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -5710,21 +5710,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH + OUT_STATE reserved 20 3 @@ -5741,7 +5741,7 @@ 0x20 - OUT_EOF_DES_ADDR_CH + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5758,7 +5758,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5775,7 +5775,7 @@ 0x20 - OUTLINK_DSCR_CH + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5792,7 +5792,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5809,7 +5809,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5827,7 +5827,7 @@ 0x00000F00 - TX_WEIGHT_CH + TX_WEIGHT The weight of Tx channel 0. 8 4 @@ -5844,7 +5844,7 @@ 0x20 - TX_PRI_CH + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5862,7 +5862,7 @@ 0x0000003F - PERI_OUT_SEL_CH + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. 0 6 @@ -5968,7 +5968,7 @@ 0x0000000E - IN_SIZE_CH + IN_SIZE This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. 0 7 @@ -5986,7 +5986,7 @@ 0x0000000E - OUT_SIZE_CH + OUT_SIZE This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. 0 7 From a367a3b269c4dafc3f97e8073a3b4d764eff6186 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 3 Nov 2022 10:55:10 -0700 Subject: [PATCH 4/4] Bump version numbers for ESP32-C2/C3/S3 --- esp32c2/Cargo.toml | 2 +- esp32c3/Cargo.toml | 2 +- esp32s3/Cargo.toml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/esp32c2/Cargo.toml b/esp32c2/Cargo.toml index 743bea47f8..5dae678e94 100644 --- a/esp32c2/Cargo.toml +++ b/esp32c2/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "esp32c2" -version = "0.3.0" +version = "0.4.0" authors = ["Jesse Braham "] edition = "2021" description = "Peripheral access crate for the ESP32-C2" diff --git a/esp32c3/Cargo.toml b/esp32c3/Cargo.toml index 33c9190c3d..2d39fd8f9a 100644 --- a/esp32c3/Cargo.toml +++ b/esp32c3/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "esp32c3" -version = "0.6.0" +version = "0.7.0" authors = [ "Samir Shetty ", "Jesse Braham ", diff --git a/esp32s3/Cargo.toml b/esp32s3/Cargo.toml index e3c97a1d86..6d4e10bf9b 100644 --- a/esp32s3/Cargo.toml +++ b/esp32s3/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "esp32s3" -version = "0.6.0" +version = "0.7.0" authors = ["Jesse Braham "] edition = "2021" rust-version = "1.60"