From 1e6165e04b20c81974e2bd7ad9736671410c5408 Mon Sep 17 00:00:00 2001 From: Juraj Sadel Date: Fri, 5 Apr 2024 16:54:13 +0200 Subject: [PATCH] Runtime ISR binding and simple public API docs for RTC (#1405) * Runtime ISR binding and simple public API docs for RTC * changelog * import dependencies instead of using full paths --- esp-hal/CHANGELOG.md | 1 + esp-hal/src/peripheral.rs | 2 +- esp-hal/src/rtc_cntl/mod.rs | 86 +++++++++++++++++++-------- esp-hal/src/soc/esp32/mod.rs | 2 +- esp-hal/src/soc/esp32c2/mod.rs | 2 +- esp-hal/src/soc/esp32c3/mod.rs | 2 +- esp-hal/src/soc/esp32c6/mod.rs | 2 +- esp-hal/src/soc/esp32h2/mod.rs | 2 +- esp-hal/src/soc/esp32s2/mod.rs | 2 +- esp-hal/src/soc/esp32s3/mod.rs | 2 +- esp-hal/src/timer.rs | 2 +- examples/src/bin/clock_monitor.rs | 28 +-------- examples/src/bin/ram.rs | 2 +- examples/src/bin/rtc_time.rs | 2 +- examples/src/bin/rtc_watchdog.rs | 23 +------ examples/src/bin/sleep_timer.rs | 2 +- examples/src/bin/sleep_timer_ext0.rs | 2 +- examples/src/bin/sleep_timer_ext1.rs | 2 +- examples/src/bin/sleep_timer_lpio.rs | 2 +- examples/src/bin/sleep_timer_rtcio.rs | 2 +- 20 files changed, 85 insertions(+), 85 deletions(-) diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index 049cfaaea46..96150e30e03 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -57,6 +57,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - ESP32-C6: The `gpio::lp_gpio` module has been renamed to `gpio::lp_io` to match the peripheral name (#1397) - Runtime ISR binding for assist_debug (#1395) - Runtime ISR binding for software interrupts, software interrupts are split now, interrupt-executor takes the software interrupt to use, interrupt-executor is easier to use (#1398) +- Runtime ISR binding for RTC (#1405) ### Removed diff --git a/esp-hal/src/peripheral.rs b/esp-hal/src/peripheral.rs index ff41c867935..f5b207b0532 100644 --- a/esp-hal/src/peripheral.rs +++ b/esp-hal/src/peripheral.rs @@ -29,7 +29,7 @@ //! ``` //! ### Accessing peripherals //! ```no_run -//! let mut rtc = Rtc::new(peripherals.LPWR); +//! let mut rtc = Rtc::new(peripherals.LPWR, None); //! ``` //! ```no_run //! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index 4b100b15de5..1ffd46c473a 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -51,8 +51,8 @@ //! Where the `LP_WDT` interrupt handler is defined as: //! ```no_run //! // Handle the corresponding interrupt -//! #[interrupt] -//! fn LP_WDT() { +//! #[handler] +//! fn interrupt_handler() { //! critical_section::with(|cs| { //! esp_println::println!("RWDT Interrupt"); //! @@ -86,7 +86,9 @@ use crate::peripherals::{LP_TIMER, LP_WDT}; use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers}; use crate::{ clock::Clock, + interrupt::{self, InterruptHandler}, peripheral::{Peripheral, PeripheralRef}, + peripherals::Interrupt, reset::{SleepSource, WakeupReason}, Cpu, }; @@ -187,7 +189,13 @@ pub struct Rtc<'d> { } impl<'d> Rtc<'d> { - pub fn new(rtc_cntl: impl Peripheral

+ 'd) -> Self { + /// Create a new instance in [crate::Blocking] mode. + /// + /// Optionally an interrupt handler can be bound. + pub fn new( + rtc_cntl: impl Peripheral

+ 'd, + interrupt: Option, + ) -> Self { rtc::init(); rtc::configure_clock(); @@ -201,14 +209,35 @@ impl<'d> Rtc<'d> { #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] RtcSleepConfig::base_settings(&this); + if let Some(interrupt) = interrupt { + unsafe { + interrupt::bind_interrupt( + #[cfg(any(esp32c6, esp32h2))] + Interrupt::LP_WDT, + #[cfg(not(any(esp32c6, esp32h2)))] + Interrupt::RTC_CORE, + interrupt.handler(), + ); + interrupt::enable( + #[cfg(any(esp32c6, esp32h2))] + Interrupt::LP_WDT, + #[cfg(not(any(esp32c6, esp32h2)))] + Interrupt::RTC_CORE, + interrupt.priority(), + ) + .unwrap(); + } + } + this } + /// Return estimated XTAL frequency in MHz. pub fn estimate_xtal_frequency(&mut self) -> u32 { RtcClock::estimate_xtal_frequency() } - /// read the current value of the rtc time registers. + /// Read the current value of the rtc time registers. pub fn get_time_raw(&self) -> u64 { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::ptr() }; @@ -247,17 +276,17 @@ impl<'d> Rtc<'d> { ((h as u64) << 32) | (l as u64) } - /// read the current value of the rtc time registers in microseconds. + /// Read the current value of the rtc time registers in microseconds. pub fn get_time_us(&self) -> u64 { self.get_time_raw() * 1_000_000 / RtcClock::get_slow_freq().frequency().to_Hz() as u64 } - /// read the current value of the rtc time registers in milliseconds + /// Read the current value of the rtc time registers in milliseconds. pub fn get_time_ms(&self) -> u64 { self.get_time_raw() * 1_000 / RtcClock::get_slow_freq().frequency().to_Hz() as u64 } - /// enter deep sleep and wake with the provided `wake_sources` + /// Enter deep sleep and wake with the provided `wake_sources`. #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] pub fn sleep_deep( &mut self, @@ -269,7 +298,7 @@ impl<'d> Rtc<'d> { unreachable!(); } - /// enter light sleep and wake with the provided `wake_sources` + /// Enter light sleep and wake with the provided `wake_sources`. #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] pub fn sleep_light( &mut self, @@ -280,8 +309,8 @@ impl<'d> Rtc<'d> { self.sleep(&config, wake_sources, delay); } - /// enter sleep with the provided `config` and wake with the provided - /// `wake_sources` + /// Enter sleep with the provided `config` and wake with the provided + /// `wake_sources`. #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] pub fn sleep( &mut self, @@ -304,15 +333,15 @@ impl<'d> Rtc<'d> { } #[cfg(not(any(esp32c6, esp32h2)))] -/// RTC Watchdog Timer +/// RTC Watchdog Timer. pub struct RtcClock; #[cfg(not(any(esp32c6, esp32h2)))] -/// RTC Watchdog Timer driver +/// RTC Watchdog Timer driver. impl RtcClock { const CAL_FRACT: u32 = 19; - /// Enable or disable 8 MHz internal oscillator + /// Enable or disable 8 MHz internal oscillator. /// /// Output from 8 MHz internal oscillator is passed into a configurable /// divider, which by default divides the input clock frequency by 256. @@ -352,7 +381,7 @@ impl RtcClock { } } - /// Get main XTAL frequency + /// Get main XTAL frequency. /// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the /// bootloader, as passed to rtc_clk_init function. pub fn get_xtal_freq() -> XtalClock { @@ -380,7 +409,7 @@ impl RtcClock { } } - /// Get the RTC_SLOW_CLK source + /// Get the RTC_SLOW_CLK source. #[cfg(not(any(esp32c6, esp32h2)))] pub fn get_slow_freq() -> RtcSlowClock { let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -393,7 +422,7 @@ impl RtcClock { } } - /// Select source for RTC_SLOW_CLK + /// Select source for RTC_SLOW_CLK. #[cfg(not(any(esp32c6, esp32h2)))] fn set_slow_freq(slow_freq: RtcSlowClock) { unsafe { @@ -416,7 +445,7 @@ impl RtcClock { crate::rom::ets_delay_us(300u32); } - /// Select source for RTC_FAST_CLK + /// Select source for RTC_FAST_CLK. #[cfg(not(any(esp32c6, esp32h2)))] fn set_fast_freq(fast_freq: RtcFastClock) { unsafe { @@ -576,7 +605,7 @@ impl RtcClock { cal_val } - /// Measure ratio between XTAL frequency and RTC slow clock frequency + /// Measure ratio between XTAL frequency and RTC slow clock frequency. fn get_calibration_ratio(cal_clk: RtcCalSel, slowclk_cycles: u32) -> u32 { let xtal_cycles = RtcClock::calibrate_internal(cal_clk, slowclk_cycles) as u64; let ratio = (xtal_cycles << RtcClock::CAL_FRACT) / slowclk_cycles as u64; @@ -584,7 +613,7 @@ impl RtcClock { (ratio & (u32::MAX as u64)) as u32 } - /// Measure RTC slow clock's period, based on main XTAL frequency + /// Measure RTC slow clock's period, based on main XTAL frequency. /// /// This function will time out and return 0 if the time for the given /// number of cycles to be counted exceeds the expected time twice. This @@ -619,6 +648,7 @@ impl RtcClock { } // TODO: implement for ESP32-C6, and H2 + /// Return estimated XTAL frequency in MHz. #[cfg(not(any(esp32c6, esp32h2)))] pub(crate) fn estimate_xtal_frequency() -> u32 { // Number of 8M/256 clock cycles to use for XTAL frequency estimation. @@ -643,7 +673,7 @@ impl RtcClock { } } -/// Behavior of the RWDT stage if it times out +/// Behavior of the RWDT stage if it times out. #[allow(unused)] #[derive(Debug, Clone, Copy)] enum RwdtStageAction { @@ -654,7 +684,7 @@ enum RwdtStageAction { ResetRtc = 4, } -/// RTC Watchdog Timer +/// RTC Watchdog Timer. pub struct Rwdt { stg0_action: RwdtStageAction, stg1_action: RwdtStageAction, @@ -673,18 +703,19 @@ impl Default for Rwdt { } } -/// RTC Watchdog Timer driver +/// RTC Watchdog Timer driver. impl Rwdt { - /// Enable the watchdog timer instance + /// Enable the watchdog timer instance. pub fn enable(&mut self) { self.set_enabled(true); } - /// Disable the watchdog timer instance + /// Disable the watchdog timer instance. pub fn disable(&mut self) { self.set_enabled(false); } + /// Listen for interrupts. pub fn listen(&mut self) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -705,6 +736,7 @@ impl Rwdt { self.set_write_protection(true); } + /// Stop listening for interrupts. pub fn unlisten(&mut self) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -725,6 +757,7 @@ impl Rwdt { self.set_write_protection(true); } + /// Clear interrupt. pub fn clear_interrupt(&mut self) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -738,6 +771,7 @@ impl Rwdt { self.set_write_protection(true); } + /// Check if the interrupt is set. pub fn is_interrupt_set(&self) -> bool { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -747,6 +781,7 @@ impl Rwdt { rtc_cntl.int_st().read().wdt().bit_is_set() } + /// Feed the watchdog timer. pub fn feed(&mut self) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -784,6 +819,7 @@ impl Rwdt { self.set_write_protection(true); } + /// Configure timeout value in ms. pub fn set_timeout(&mut self, timeout: MicrosDurationU64) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*LPWR::PTR }; @@ -924,12 +960,14 @@ impl embedded_hal_02::watchdog::WatchdogDisable for Swd { } } +/// Return reset reason. pub fn get_reset_reason(cpu: Cpu) -> Option { let reason = crate::rom::rtc_get_reset_reason(cpu as u32); SocResetReason::from_repr(reason as usize) } +/// Return wakeup reason. pub fn get_wakeup_cause() -> SleepSource { if get_reset_reason(Cpu::ProCpu) != Some(SocResetReason::CoreDeepSleep) { return SleepSource::Undefined; diff --git a/esp-hal/src/soc/esp32/mod.rs b/esp-hal/src/soc/esp32/mod.rs index 3ea1b95d98e..4ff316f0fbe 100644 --- a/esp-hal/src/soc/esp32/mod.rs +++ b/esp-hal/src/soc/esp32/mod.rs @@ -93,7 +93,7 @@ pub extern "Rust" fn __init_data() -> bool { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.rwdt.disable(); Wdt::::set_wdt_enabled(false); diff --git a/esp-hal/src/soc/esp32c2/mod.rs b/esp-hal/src/soc/esp32c2/mod.rs index a26ebcb1978..42859cbf9d9 100644 --- a/esp-hal/src/soc/esp32c2/mod.rs +++ b/esp-hal/src/soc/esp32c2/mod.rs @@ -27,7 +27,7 @@ pub(crate) mod constants { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.swd.disable(); rtc.rwdt.disable(); diff --git a/esp-hal/src/soc/esp32c3/mod.rs b/esp-hal/src/soc/esp32c3/mod.rs index 36119240ac1..075a647bd9f 100644 --- a/esp-hal/src/soc/esp32c3/mod.rs +++ b/esp-hal/src/soc/esp32c3/mod.rs @@ -39,7 +39,7 @@ pub(crate) mod constants { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.swd.disable(); rtc.rwdt.disable(); diff --git a/esp-hal/src/soc/esp32c6/mod.rs b/esp-hal/src/soc/esp32c6/mod.rs index ff722aa6cb1..649c915015e 100644 --- a/esp-hal/src/soc/esp32c6/mod.rs +++ b/esp-hal/src/soc/esp32c6/mod.rs @@ -45,7 +45,7 @@ pub(crate) mod constants { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.swd.disable(); rtc.rwdt.disable(); diff --git a/esp-hal/src/soc/esp32h2/mod.rs b/esp-hal/src/soc/esp32h2/mod.rs index cddfd2ec939..a6cd8adb0f2 100644 --- a/esp-hal/src/soc/esp32h2/mod.rs +++ b/esp-hal/src/soc/esp32h2/mod.rs @@ -44,7 +44,7 @@ pub(crate) mod constants { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.swd.disable(); rtc.rwdt.disable(); diff --git a/esp-hal/src/soc/esp32s2/mod.rs b/esp-hal/src/soc/esp32s2/mod.rs index b6f0bdab8aa..c1fb8632244 100644 --- a/esp-hal/src/soc/esp32s2/mod.rs +++ b/esp-hal/src/soc/esp32s2/mod.rs @@ -97,7 +97,7 @@ pub extern "Rust" fn __init_data() -> bool { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.rwdt.disable(); Wdt::::set_wdt_enabled(false); diff --git a/esp-hal/src/soc/esp32s3/mod.rs b/esp-hal/src/soc/esp32s3/mod.rs index d1e120f4d53..adbf1569049 100644 --- a/esp-hal/src/soc/esp32s3/mod.rs +++ b/esp-hal/src/soc/esp32s3/mod.rs @@ -131,7 +131,7 @@ pub extern "Rust" fn __init_data() -> bool { #[export_name = "__post_init"] unsafe fn post_init() { // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LPWR::steal()); + let mut rtc = Rtc::new(LPWR::steal(), None); rtc.rwdt.disable(); Wdt::::set_wdt_enabled(false); diff --git a/esp-hal/src/timer.rs b/esp-hal/src/timer.rs index 2a5cfbba652..bb41a4c6165 100644 --- a/esp-hal/src/timer.rs +++ b/esp-hal/src/timer.rs @@ -18,7 +18,7 @@ //! ## Example //! //! ```no_run -//! let mut rtc = Rtc::new(peripherals.LPWR); +//! let mut rtc = Rtc::new(peripherals.LPWR, None); //! //! // Create timer groups //! let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); diff --git a/examples/src/bin/clock_monitor.rs b/examples/src/bin/clock_monitor.rs index c6507d35e23..a72f68608eb 100644 --- a/examples/src/bin/clock_monitor.rs +++ b/examples/src/bin/clock_monitor.rs @@ -11,13 +11,7 @@ use core::cell::RefCell; use critical_section::Mutex; use esp_backtrace as _; -use esp_hal::{ - clock::ClockControl, - interrupt::{self, Priority}, - peripherals::{Interrupt, Peripherals}, - prelude::*, - rtc_cntl::Rtc, -}; +use esp_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, rtc_cntl::Rtc}; use esp_println::println; static RTC: Mutex>> = Mutex::new(RefCell::new(None)); @@ -28,7 +22,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, Some(interrupt_handler)); rtc.rwdt.set_timeout(2000.millis()); rtc.rwdt.listen(); @@ -38,16 +32,12 @@ fn main() -> ! { clocks.xtal_clock.to_MHz() ); - #[cfg(any(feature = "esp32c6", feature = "esp32h2"))] - interrupt::enable(Interrupt::LP_WDT, Priority::Priority1).unwrap(); - #[cfg(not(any(feature = "esp32c6", feature = "esp32h2")))] - interrupt::enable(Interrupt::RTC_CORE, Priority::Priority1).unwrap(); - critical_section::with(|cs| RTC.borrow_ref_mut(cs).replace(rtc)); loop {} } +#[handler(priority = esp_hal::interrupt::Priority::min())] fn interrupt_handler() { critical_section::with(|cs| { let mut rtc = RTC.borrow_ref_mut(cs); @@ -62,15 +52,3 @@ fn interrupt_handler() { rtc.rwdt.clear_interrupt(); }); } - -#[cfg(any(feature = "esp32c6", feature = "esp32h2"))] -#[interrupt] -fn LP_WDT() { - interrupt_handler(); -} - -#[cfg(not(any(feature = "esp32c6", feature = "esp32h2")))] -#[interrupt] -fn RTC_CORE() { - interrupt_handler(); -} diff --git a/examples/src/bin/ram.rs b/examples/src/bin/ram.rs index 0139f34ddb8..045e443514d 100644 --- a/examples/src/bin/ram.rs +++ b/examples/src/bin/ram.rs @@ -46,7 +46,7 @@ fn main() -> ! { // The RWDT flash boot protection must be enabled, as it is triggered as part of // the example. - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, None); rtc.rwdt.enable(); println!( diff --git a/examples/src/bin/rtc_time.rs b/examples/src/bin/rtc_time.rs index ef9ed889666..24ad3f7ee3a 100644 --- a/examples/src/bin/rtc_time.rs +++ b/examples/src/bin/rtc_time.rs @@ -20,7 +20,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let rtc = Rtc::new(peripherals.LPWR); + let rtc = Rtc::new(peripherals.LPWR, None); let delay = Delay::new(&clocks); loop { diff --git a/examples/src/bin/rtc_watchdog.rs b/examples/src/bin/rtc_watchdog.rs index 11c2465c52f..f228fd32c3d 100644 --- a/examples/src/bin/rtc_watchdog.rs +++ b/examples/src/bin/rtc_watchdog.rs @@ -14,8 +14,7 @@ use core::cell::RefCell; use critical_section::Mutex; use esp_backtrace as _; use esp_hal::{ - interrupt::{self, Priority}, - peripherals::{Interrupt, Peripherals}, + peripherals::Peripherals, prelude::*, rtc_cntl::{Rtc, Rwdt}, }; @@ -26,20 +25,16 @@ static RWDT: Mutex>> = Mutex::new(RefCell::new(None)); fn main() -> ! { let peripherals = Peripherals::take(); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, Some(interrupt_handler)); rtc.rwdt.set_timeout(2000.millis()); rtc.rwdt.listen(); critical_section::with(|cs| RWDT.borrow_ref_mut(cs).replace(rtc.rwdt)); - #[cfg(any(feature = "esp32c6", feature = "esp32h2"))] - interrupt::enable(Interrupt::LP_WDT, Priority::Priority1).unwrap(); - #[cfg(not(any(feature = "esp32c6", feature = "esp32h2")))] - interrupt::enable(Interrupt::RTC_CORE, Priority::Priority1).unwrap(); - loop {} } +#[handler(priority = esp_hal::interrupt::Priority::min())] fn interrupt_handler() { critical_section::with(|cs| { esp_println::println!("RWDT Interrupt"); @@ -54,15 +49,3 @@ fn interrupt_handler() { rwdt.unlisten(); }); } - -#[cfg(any(feature = "esp32c6", feature = "esp32h2"))] -#[interrupt] -fn LP_WDT() { - interrupt_handler(); -} - -#[cfg(not(any(feature = "esp32c6", feature = "esp32h2")))] -#[interrupt] -fn RTC_CORE() { - interrupt_handler(); -} diff --git a/examples/src/bin/sleep_timer.rs b/examples/src/bin/sleep_timer.rs index cca26e9bfa3..2c29ce70b3d 100644 --- a/examples/src/bin/sleep_timer.rs +++ b/examples/src/bin/sleep_timer.rs @@ -26,7 +26,7 @@ fn main() -> ! { let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut delay = Delay::new(&clocks); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, None); println!("up and runnning!"); let reason = get_reset_reason(Cpu::ProCpu).unwrap_or(SocResetReason::ChipPowerOn); diff --git a/examples/src/bin/sleep_timer_ext0.rs b/examples/src/bin/sleep_timer_ext0.rs index 7e285d75f58..11dc54a2681 100644 --- a/examples/src/bin/sleep_timer_ext0.rs +++ b/examples/src/bin/sleep_timer_ext0.rs @@ -32,7 +32,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, None); let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); let mut ext0_pin = io.pins.gpio4; diff --git a/examples/src/bin/sleep_timer_ext1.rs b/examples/src/bin/sleep_timer_ext1.rs index 57be04e22e5..f8e2087df4b 100644 --- a/examples/src/bin/sleep_timer_ext1.rs +++ b/examples/src/bin/sleep_timer_ext1.rs @@ -32,7 +32,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, None); let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); let mut pin_0 = io.pins.gpio4; diff --git a/examples/src/bin/sleep_timer_lpio.rs b/examples/src/bin/sleep_timer_lpio.rs index bb9c29445fa..5deb512396c 100644 --- a/examples/src/bin/sleep_timer_lpio.rs +++ b/examples/src/bin/sleep_timer_lpio.rs @@ -32,7 +32,7 @@ fn main() -> ! { let system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, None); let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); let mut pin2 = io.pins.gpio2; diff --git a/examples/src/bin/sleep_timer_rtcio.rs b/examples/src/bin/sleep_timer_rtcio.rs index 4a3ef7009e7..2ca1e39bf3d 100644 --- a/examples/src/bin/sleep_timer_rtcio.rs +++ b/examples/src/bin/sleep_timer_rtcio.rs @@ -35,7 +35,7 @@ fn main() -> ! { let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut io = IO::new(peripherals.GPIO, peripherals.IO_MUX); - let mut rtc = Rtc::new(peripherals.LPWR); + let mut rtc = Rtc::new(peripherals.LPWR, None); println!("up and runnning!"); let reason = get_reset_reason(Cpu::ProCpu).unwrap_or(SocResetReason::ChipPowerOn);