From 17daa464ba14f8b9a1fb8d126887e1525311f44a Mon Sep 17 00:00:00 2001 From: Juraj Sadel Date: Fri, 6 Sep 2024 10:53:27 +0200 Subject: [PATCH] Enable ESP32 HIL (#1977) * Enable ESP32 HIL * RMT fixed * SPI DMA partially works, _pcnt tests not working * bckup * finish * readme and cleanup * rebase + cleanup * RMT S2 pin typo + clean forgotten comments * review comments * update 10000 * indentation * replace cfg gate with cfg_if --- .github/workflows/hil.yml | 6 ++++++ hil-test/README.md | 8 ++++++++ hil-test/src/lib.rs | 8 +++++++- hil-test/tests/embassy_timers_executors.rs | 18 ++++++++++------- hil-test/tests/gpio.rs | 4 ++-- hil-test/tests/i2c.rs | 6 ++++-- hil-test/tests/i2s_async.rs | 22 +++++++++++++++++++-- hil-test/tests/pcnt.rs | 1 + hil-test/tests/qspi_read.rs | 2 +- hil-test/tests/qspi_write.rs | 2 +- hil-test/tests/qspi_write_read.rs | 2 +- hil-test/tests/rmt.rs | 15 ++++++++++---- hil-test/tests/spi_full_duplex.rs | 19 ++++++++---------- hil-test/tests/spi_full_duplex_dma.rs | 10 +++++----- hil-test/tests/spi_full_duplex_dma_async.rs | 8 ++++---- hil-test/tests/spi_full_duplex_dma_pcnt.rs | 8 ++++---- hil-test/tests/spi_half_duplex_read.rs | 4 ++-- hil-test/tests/spi_half_duplex_write.rs | 4 ++-- hil-test/tests/twai.rs | 4 ++-- hil-test/tests/uart.rs | 4 ++-- hil-test/tests/uart_async.rs | 4 ++-- hil-test/tests/uart_tx_rx.rs | 4 ++-- hil-test/tests/uart_tx_rx_async.rs | 4 ++-- 23 files changed, 108 insertions(+), 59 deletions(-) diff --git a/.github/workflows/hil.yml b/.github/workflows/hil.yml index c30091df688..72bd68a7c9b 100644 --- a/.github/workflows/hil.yml +++ b/.github/workflows/hil.yml @@ -86,6 +86,8 @@ jobs: - soc: esp32h2 rust-target: riscv32imac-unknown-none-elf # # Xtensa devices: + - soc: esp32 + rust-target: xtensa-esp32-none-elf - soc: esp32s2 rust-target: xtensa-esp32s2-none-elf - soc: esp32s3 @@ -168,6 +170,10 @@ jobs: host: armv7 hubs: "1-1" # Xtensa devices: + - soc: esp32 + runner: esp32-jtag + host: aarch64 + hubs: "1 3" - soc: esp32s2 runner: esp32s2-jtag host: armv7 diff --git a/hil-test/README.md b/hil-test/README.md index dd3fb541120..39f637b1fd6 100644 --- a/hil-test/README.md +++ b/hil-test/README.md @@ -103,9 +103,17 @@ Our self-hosted runners have the following setup: - `GPIO9` and `GPIO10` are connected. - `GPIO43 (TX)` and `GPIO45` are connected. - RPi: Raspbian 12 configured with the following [setup] +- ESP32 (`esp32-jtag`): + - Devkit: `ESP32-DevKitC-V4` connected via UART. + - `GPIO32` and `GPIO33` are I2C pins. + - `GPIO4` and `GPIO5` are connected. + - `GPIO26` and `GPIO27` are connected. + - Probe: `ESP-Prog` connected with the [following connections][connection_esp32] + - RPi: Raspbian 12 configured with the following [setup] [connection_c2]: https://docs.espressif.com/projects/esp-idf/en/stable/esp32c2/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware [connection_s2]: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware +[connection_esp32]: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware.html#configure-hardware [`hil.yml`]: https://github.com/esp-rs/esp-hal/blob/main/.github/workflows/hil.yml [setup]: #rpi-setup diff --git a/hil-test/src/lib.rs b/hil-test/src/lib.rs index d1c9835c68f..cabe27dcce8 100644 --- a/hil-test/src/lib.rs +++ b/hil-test/src/lib.rs @@ -30,6 +30,8 @@ macro_rules! i2c_pins { cfg_if::cfg_if! { if #[cfg(any(esp32s2, esp32s3))] { ($io.pins.gpio2, $io.pins.gpio3) + } else if #[cfg(esp32)] { + ($io.pins.gpio32, $io.pins.gpio33) } else if #[cfg(esp32c6)] { ($io.pins.gpio6, $io.pins.gpio7) } else if #[cfg(esp32h2)] { @@ -49,7 +51,11 @@ macro_rules! common_test_pins { cfg_if::cfg_if! { if #[cfg(any(esp32s2, esp32s3))] { ($io.pins.gpio9, $io.pins.gpio10) - } else { + } + else if #[cfg(esp32)] { + ($io.pins.gpio26, $io.pins.gpio27) + } + else { ($io.pins.gpio2, $io.pins.gpio3) } } diff --git a/hil-test/tests/embassy_timers_executors.rs b/hil-test/tests/embassy_timers_executors.rs index 4b90569143b..edc8479b6ac 100644 --- a/hil-test/tests/embassy_timers_executors.rs +++ b/hil-test/tests/embassy_timers_executors.rs @@ -8,21 +8,23 @@ #![no_main] use embassy_time::{Duration, Ticker, Timer}; -use esp_hal::{ - interrupt::software::SoftwareInterruptControl, - peripherals::Peripherals, - prelude::*, - timer::{timg::TimerGroup, ErasedTimer, OneShotTimer, PeriodicTimer}, -}; #[cfg(not(feature = "esp32"))] use esp_hal::{ + interrupt::software::SoftwareInterruptControl, interrupt::Priority, timer::systimer::{Alarm, FrozenUnit, Periodic, SystemTimer, Target}, + timer::ErasedTimer, +}; +use esp_hal::{ + peripherals::Peripherals, + prelude::*, + timer::{timg::TimerGroup, OneShotTimer, PeriodicTimer}, }; #[cfg(not(feature = "esp32"))] use esp_hal_embassy::InterruptExecutor; use hil_test as _; +#[cfg(not(feature = "esp32"))] macro_rules! mk_static { ($t:ty,$val:expr) => {{ static STATIC_CELL: static_cell::StaticCell<$t> = static_cell::StaticCell::new(); @@ -123,7 +125,9 @@ fn set_up_embassy_with_systimer(peripherals: Peripherals) { #[embedded_test::tests(executor = esp_hal_embassy::Executor::new())] mod test { use super::*; - use crate::{test_cases::*, test_helpers::*}; + use crate::test_cases::*; + #[cfg(not(feature = "esp32"))] + use crate::test_helpers::*; #[init] fn init() -> Peripherals { diff --git a/hil-test/tests/gpio.rs b/hil-test/tests/gpio.rs index 4caba762a97..288df83c402 100644 --- a/hil-test/tests/gpio.rs +++ b/hil-test/tests/gpio.rs @@ -1,8 +1,8 @@ //! GPIO Test //! //! Folowing pins are used: -//! GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 //% FEATURES: generic-queue diff --git a/hil-test/tests/i2c.rs b/hil-test/tests/i2c.rs index 3e8e1ef4d5d..e85e223241b 100644 --- a/hil-test/tests/i2c.rs +++ b/hil-test/tests/i2c.rs @@ -4,12 +4,14 @@ //! SDA GPIO2 (esp32s2 and esp32s3) //! GPIO6 (esp32c6) //! GPIO18 (esp32c2) -//! GPIO4 (esp32, esp32h2 and esp32c3) +//! GPIO4 (esp32h2 and esp32c3) +//! GPIO32 (esp32) //! //! SCL GPIO3 (esp32s2 and esp32s3) -//! GPIO7 (esp32c6, esp32 and esp32c3) +//! GPIO7 (esp32c6 and esp32c3) //! GPIO22 (esp32h2) //! GPIO19 (esp32c2) +//! GPIO33 (esp32) //% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 diff --git a/hil-test/tests/i2s_async.rs b/hil-test/tests/i2s_async.rs index 0f93b032f64..7a792a5a29e 100644 --- a/hil-test/tests/i2s_async.rs +++ b/hil-test/tests/i2s_async.rs @@ -13,7 +13,7 @@ #![no_main] use esp_hal::{ - dma::{Dma, DmaChannel0, DmaPriority}, + dma::{Dma, DmaPriority}, gpio::Io, i2s::{asynch::*, DataFormat, I2s, I2sTx, Standard}, peripheral::Peripheral, @@ -23,6 +23,17 @@ use esp_hal::{ }; use hil_test as _; +cfg_if::cfg_if! { + if #[cfg(any( + feature = "esp32", + feature = "esp32s2", + ))] { + use esp_hal::dma::Spi2DmaChannel as DmaChannel0; + } else { + use esp_hal::dma::DmaChannel0; + } +} + const BUFFER_SIZE: usize = 2000; #[derive(Clone)] @@ -91,7 +102,14 @@ mod tests { let mut io = Io::new(peripherals.GPIO, peripherals.IO_MUX); let dma = Dma::new(peripherals.DMA); - let dma_channel = dma.channel0; + + cfg_if::cfg_if! { + if #[cfg(any(feature = "esp32", feature = "esp32s2"))] { + let dma_channel = dma.spi2channel; + } else { + let dma_channel = dma.channel0; + } + } let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = esp_hal::dma_circular_buffers!(BUFFER_SIZE, BUFFER_SIZE); diff --git a/hil-test/tests/pcnt.rs b/hil-test/tests/pcnt.rs index f7cdf259fdf..422991640d3 100644 --- a/hil-test/tests/pcnt.rs +++ b/hil-test/tests/pcnt.rs @@ -2,6 +2,7 @@ //! //! It's assumed GPIO2 is connected to GPIO3 //! (GPIO9 and GPIO10 for esp32s2 and esp32s3) +//! (GPIO26 and GPIO27 for esp32) //% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3 diff --git a/hil-test/tests/qspi_read.rs b/hil-test/tests/qspi_read.rs index c6de7c38d8b..8287a89ad40 100644 --- a/hil-test/tests/qspi_read.rs +++ b/hil-test/tests/qspi_read.rs @@ -7,7 +7,7 @@ //! //! Connect MISO and GPIO pins. -//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 +//% CHIPS: esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 #![no_std] #![no_main] diff --git a/hil-test/tests/qspi_write.rs b/hil-test/tests/qspi_write.rs index 441aa315c30..413abb1ec28 100644 --- a/hil-test/tests/qspi_write.rs +++ b/hil-test/tests/qspi_write.rs @@ -9,7 +9,7 @@ //! //! Connect MOSI and PCNT pins. -//% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3 +//% CHIPS: esp32c6 esp32h2 esp32s2 esp32s3 #![no_std] #![no_main] diff --git a/hil-test/tests/qspi_write_read.rs b/hil-test/tests/qspi_write_read.rs index 16f2a65e2cb..5bd05da00a3 100644 --- a/hil-test/tests/qspi_write_read.rs +++ b/hil-test/tests/qspi_write_read.rs @@ -9,7 +9,7 @@ //! //! Connect MOSI/MISO and GPIO pins. -//% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3 +//% CHIPS: esp32c6 esp32h2 esp32s2 esp32s3 #![no_std] #![no_main] diff --git a/hil-test/tests/rmt.rs b/hil-test/tests/rmt.rs index a9696a51e09..1f39f7d6c93 100644 --- a/hil-test/tests/rmt.rs +++ b/hil-test/tests/rmt.rs @@ -2,6 +2,7 @@ //! //! It's assumed GPIO2 is connected to GPIO3 //! (GPIO9 and GPIO10 for esp32s2 and esp32s3) +//! (GPIO26 and GPIO27 for esp32) //% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 @@ -59,11 +60,16 @@ mod tests { }; cfg_if::cfg_if! { - if #[cfg(any(feature = "esp32", feature = "esp32s2"))] { + if #[cfg(feature = "esp32")] { let rx_channel = { use esp_hal::rmt::RxChannelCreator; rmt.channel1.configure(rx, rx_config).unwrap() }; + } else if #[cfg(feature = "esp32s2")] { + let rx_channel = { + use esp_hal::rmt::RxChannelCreator; + rmt.channel1.configure(rx, rx_config).unwrap() + }; } else if #[cfg(feature = "esp32s3")] { let rx_channel = { use esp_hal::rmt::RxChannelCreator; @@ -101,11 +107,12 @@ mod tests { let rx_transaction = rx_channel.receive(&mut rcv_data).unwrap(); let tx_transaction = tx_channel.transmit(&tx_data); - tx_transaction.wait().unwrap(); + rx_transaction.wait().unwrap(); + tx_transaction.wait().unwrap(); - // the last two pulse-codes are the ones which wait for the timeout so they - // can't be equal + // the last two pulse-codes are the ones which wait for the timeout so + // they can't be equal assert_eq!(&tx_data[..18], &rcv_data[..18]); } } diff --git a/hil-test/tests/spi_full_duplex.rs b/hil-test/tests/spi_full_duplex.rs index 87e82a6849d..188b2724fb7 100644 --- a/hil-test/tests/spi_full_duplex.rs +++ b/hil-test/tests/spi_full_duplex.rs @@ -2,9 +2,8 @@ //! //! Folowing pins are used: //! SCLK GPIO0 -//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! MOSI GPIO3 / GPIO10 (esp32s2 and esp32s3) -//! CS GPIO8 +//! MISO GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! MOSI GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect MISO and MOSI pins. @@ -37,16 +36,14 @@ mod tests { let peripherals = esp_hal::init(esp_hal::Config::default()); let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); + let sclk = io.pins.gpio0; let (miso, mosi) = hil_test::common_test_pins!(io); - let cs = io.pins.gpio8; - - let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0).with_pins( - Some(sclk), - Some(mosi), - Some(miso), - Some(cs), - ); + + let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0) + .with_sck(sclk) + .with_mosi(mosi) + .with_miso(miso); Context { spi } } diff --git a/hil-test/tests/spi_full_duplex_dma.rs b/hil-test/tests/spi_full_duplex_dma.rs index b89e91addb2..c341b35cbb8 100644 --- a/hil-test/tests/spi_full_duplex_dma.rs +++ b/hil-test/tests/spi_full_duplex_dma.rs @@ -2,9 +2,8 @@ //! //! Folowing pins are used: //! SCLK GPIO0 -//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! MOSI GPIO3 / GPIO10 (esp32s2 and esp32s3) -//! CS GPIO8 +//! MISO GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! MOSI GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect MISO and MOSI pins. @@ -57,7 +56,6 @@ mod tests { let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); let sclk = io.pins.gpio0; let (miso, mosi) = hil_test::common_test_pins!(io); - let cs = io.pins.gpio8; let dma = Dma::new(peripherals.DMA); @@ -70,7 +68,9 @@ mod tests { } let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) - .with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs)) + .with_sck(sclk) + .with_mosi(mosi) + .with_miso(miso) .with_dma(dma_channel.configure(false, DmaPriority::Priority0)); Context { spi } diff --git a/hil-test/tests/spi_full_duplex_dma_async.rs b/hil-test/tests/spi_full_duplex_dma_async.rs index e41e02fdbbc..4d881eb8baa 100644 --- a/hil-test/tests/spi_full_duplex_dma_async.rs +++ b/hil-test/tests/spi_full_duplex_dma_async.rs @@ -4,7 +4,6 @@ //! SCLK GPIO0 //! MOSI GPIO3 / GPIO10 (esp32s3) //! MISO GPIO4 -//! CS GPIO8 //! //! PCNT GPIO2 / GPIO9 (esp32s3) //! OUTPUT GPIO5 (helper to keep MISO LOW) @@ -14,7 +13,7 @@ //! //! Connect PCNT and MOSI, MISO and GPIO5 pins. -//% CHIPS: esp32 esp32c6 esp32h2 esp32s3 +//% CHIPS: esp32c6 esp32h2 esp32s3 //% FEATURES: generic-queue #![no_std] @@ -78,7 +77,6 @@ mod tests { let (mosi_mirror, mosi) = hil_test::common_test_pins!(io); let miso = io.pins.gpio4; - let cs = io.pins.gpio8; let mosi_mirror = mosi_mirror.degrade(); let mut out_pin = Output::new(io.pins.gpio5, Level::Low); @@ -100,7 +98,9 @@ mod tests { let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap(); let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) - .with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs)) + .with_sck(sclk) + .with_mosi(mosi) + .with_miso(miso) .with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0)) .with_buffers(dma_tx_buf, dma_rx_buf); diff --git a/hil-test/tests/spi_full_duplex_dma_pcnt.rs b/hil-test/tests/spi_full_duplex_dma_pcnt.rs index bbfdd59ec53..e7fb1583a34 100644 --- a/hil-test/tests/spi_full_duplex_dma_pcnt.rs +++ b/hil-test/tests/spi_full_duplex_dma_pcnt.rs @@ -3,7 +3,6 @@ //! Folowing pins are used: //! SCLK GPIO0 //! MOSI GPIO3 / GPIO10 (esp32s3) -//! CS GPIO8 //! PCNT GPIO2 / GPIO9 (esp32s3) //! OUTPUT GPIO5 (helper to keep MISO LOW) //! @@ -12,7 +11,7 @@ //! //! Connect MISO and MOSI pins. -//% CHIPS: esp32 esp32c6 esp32h2 esp32s3 +//% CHIPS: esp32c6 esp32h2 esp32s3 #![no_std] #![no_main] @@ -70,7 +69,6 @@ mod tests { let sclk = io.pins.gpio0; let (mosi_mirror, mosi) = hil_test::common_test_pins!(io); let miso = io.pins.gpio4; - let cs = io.pins.gpio8; let dma = Dma::new(peripherals.DMA); @@ -83,7 +81,9 @@ mod tests { } let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) - .with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs)) + .with_sck(sclk) + .with_mosi(mosi) + .with_miso(miso) .with_dma(dma_channel.configure(false, DmaPriority::Priority0)); let pcnt = Pcnt::new(peripherals.PCNT); diff --git a/hil-test/tests/spi_half_duplex_read.rs b/hil-test/tests/spi_half_duplex_read.rs index 9dd69893b90..0a8f7c7bd1c 100644 --- a/hil-test/tests/spi_half_duplex_read.rs +++ b/hil-test/tests/spi_half_duplex_read.rs @@ -2,9 +2,9 @@ //! //! Folowing pins are used: //! SCLK GPIO0 -//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3) +//! MISO GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) //! -//! GPIO GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! GPIO GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect MISO and GPIO pins. diff --git a/hil-test/tests/spi_half_duplex_write.rs b/hil-test/tests/spi_half_duplex_write.rs index 3779ad7aa64..45475b05abe 100644 --- a/hil-test/tests/spi_half_duplex_write.rs +++ b/hil-test/tests/spi_half_duplex_write.rs @@ -2,9 +2,9 @@ //! //! Following pins are used: //! SCLK GPIO0 -//! MOSI GPIO2 / GPIO9 (esp32s2 and esp32s3) +//! MOSI GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) //! -//! PCNT GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! PCNT GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect MOSI and PCNT pins. diff --git a/hil-test/tests/twai.rs b/hil-test/tests/twai.rs index ef3bf84eba0..1744b321d38 100644 --- a/hil-test/tests/twai.rs +++ b/hil-test/tests/twai.rs @@ -1,8 +1,8 @@ //! TWAI test //! //! Folowing pins are used: -//! TX GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! RX GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect TX and RX pins. diff --git a/hil-test/tests/uart.rs b/hil-test/tests/uart.rs index aa17f08e827..95e7dc4392b 100644 --- a/hil-test/tests/uart.rs +++ b/hil-test/tests/uart.rs @@ -1,8 +1,8 @@ //! UART Test //! //! Folowing pins are used: -//! TX GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! RX GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect TX and RX pins. diff --git a/hil-test/tests/uart_async.rs b/hil-test/tests/uart_async.rs index 357962d90e9..ae74e5c041f 100644 --- a/hil-test/tests/uart_async.rs +++ b/hil-test/tests/uart_async.rs @@ -1,8 +1,8 @@ //! UART Test //! //! Folowing pins are used: -//! TX GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! RX GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect TX and RX pins. diff --git a/hil-test/tests/uart_tx_rx.rs b/hil-test/tests/uart_tx_rx.rs index e5750e8718a..18ac37f99ab 100644 --- a/hil-test/tests/uart_tx_rx.rs +++ b/hil-test/tests/uart_tx_rx.rs @@ -1,8 +1,8 @@ //! UART TX/RX Test //! //! Folowing pins are used: -//! TX GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! RX GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect TX and RX pins. diff --git a/hil-test/tests/uart_tx_rx_async.rs b/hil-test/tests/uart_tx_rx_async.rs index b16bb1d1871..4f11a10d1eb 100644 --- a/hil-test/tests/uart_tx_rx_async.rs +++ b/hil-test/tests/uart_tx_rx_async.rs @@ -1,8 +1,8 @@ //! UART TX/RX Async Test //! //! Folowing pins are used: -//! TX GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! RX GPIO3 / GPIO10 (esp32s2 and esp32s3) +//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32) +//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32) //! //! Connect TX and RX pins.