From 08920778c0484d97a1fe33184ed9b56da82c701a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 4 Sep 2024 13:04:24 +0200 Subject: [PATCH] Erase gpio types by default --- esp-hal/src/gpio/mod.rs | 86 +++++++++++++++++---- hil-test/tests/gpio.rs | 4 +- hil-test/tests/qspi_read.rs | 6 +- hil-test/tests/qspi_write_read.rs | 6 +- hil-test/tests/spi_full_duplex_dma_async.rs | 2 +- hil-test/tests/spi_full_duplex_dma_pcnt.rs | 2 +- hil-test/tests/spi_half_duplex_read.rs | 4 +- 7 files changed, 84 insertions(+), 26 deletions(-) diff --git a/esp-hal/src/gpio/mod.rs b/esp-hal/src/gpio/mod.rs index 2d5194e5bad..0452fd4d257 100644 --- a/esp-hal/src/gpio/mod.rs +++ b/esp-hal/src/gpio/mod.rs @@ -276,7 +276,10 @@ pub trait Pin: private::Sealed { /// This converts pin singletons (`GpioPin<0>`, …), which are all different /// types, into the same type. It is useful for creating arrays of pins, /// or avoiding generics. - fn degrade(self) -> ErasedPin where Self: Sized { + fn degrade(self) -> ErasedPin + where + Self: Sized, + { self.degrade_internal(private::Internal) } @@ -1872,18 +1875,34 @@ macro_rules! touch_common { } /// GPIO output driver. -pub struct Output<'d, P> { +pub struct Output<'d, P = ErasedPin> { pin: Flex<'d, P>, } +impl<'d> Output<'d> { + /// Create GPIO output driver for a [GpioPin] with the provided level + #[inline] + pub fn new( + pin: impl crate::peripheral::Peripheral

+ 'd, + initial_output: Level, + ) -> Self { + let pin = Flex::new(pin); + + Self::new_inner(pin, initial_output) + } +} + impl<'d, P> Output<'d, P> where P: OutputPin, { /// Create GPIO output driver for a [GpioPin] with the provided level #[inline] - pub fn new(pin: impl crate::peripheral::Peripheral

+ 'd, initial_output: Level) -> Self { - let pin = Flex::new(pin); + pub fn new_typed( + pin: impl crate::peripheral::Peripheral

+ 'd, + initial_output: Level, + ) -> Self { + let pin = Flex::new_typed(pin); Self::new_inner(pin, initial_output) } @@ -1946,10 +1965,24 @@ where } /// GPIO input driver. -pub struct Input<'d, P> { +pub struct Input<'d, P = ErasedPin> { pin: Flex<'d, P>, } +impl<'d> Input<'d> { + /// Create GPIO input driver for a [Pin] with the provided [Pull] + /// configuration. + #[inline] + pub fn new( + pin: impl crate::peripheral::Peripheral

+ 'd, + pull: Pull, + ) -> Self { + let pin = Flex::new(pin); + + Self::new_inner(pin, pull) + } +} + impl<'d, P> Input<'d, P> where P: InputPin, @@ -1957,8 +1990,8 @@ where /// Create GPIO input driver for a [Pin] with the provided [Pull] /// configuration. #[inline] - pub fn new(pin: impl crate::peripheral::Peripheral

+ 'd, pull: Pull) -> Self { - let pin = Flex::new(pin); + pub fn new_typed(pin: impl crate::peripheral::Peripheral

+ 'd, pull: Pull) -> Self { + let pin = Flex::new_typed(pin); Self::new_inner(pin, pull) } @@ -2020,10 +2053,25 @@ where } /// GPIO open-drain output driver. -pub struct OutputOpenDrain<'d, P> { +pub struct OutputOpenDrain<'d, P = ErasedPin> { pin: Flex<'d, P>, } +impl<'d> OutputOpenDrain<'d> { + /// Create GPIO open-drain output driver for a [Pin] with the provided + /// initial output-level and [Pull] configuration. + #[inline] + pub fn new( + pin: impl crate::peripheral::Peripheral

+ 'd, + initial_output: Level, + pull: Pull, + ) -> Self { + let pin = Flex::new(pin); + + Self::new_inner(pin, initial_output, pull) + } +} + impl<'d, P> OutputOpenDrain<'d, P> where P: InputPin + OutputPin, @@ -2031,13 +2079,12 @@ where /// Create GPIO open-drain output driver for a [Pin] with the provided /// initial output-level and [Pull] configuration. #[inline] - pub fn new( + pub fn new_typed( pin: impl crate::peripheral::Peripheral

+ 'd, initial_output: Level, pull: Pull, - ) -> Self - { - let pin = Flex::new(pin); + ) -> Self { + let pin = Flex::new_typed(pin); Self::new_inner(pin, initial_output, pull) } @@ -2130,10 +2177,21 @@ where } /// Flexible pin driver. -pub struct Flex<'d, P> { +pub struct Flex<'d, P = ErasedPin> { pin: PeripheralRef<'d, P>, } +impl<'d> Flex<'d> { + /// Create flexible pin driver for a [Pin]. + /// No mode change happens. + #[inline] + pub fn new(pin: impl crate::peripheral::Peripheral

+ 'd) -> Self { + crate::into_ref!(pin); + let pin = pin.degrade_internal(private::Internal); + Self::new_typed(pin) + } +} + impl<'d, P> Flex<'d, P> where P: Pin, @@ -2141,7 +2199,7 @@ where /// Create flexible pin driver for a [Pin]. /// No mode change happens. #[inline] - pub fn new(pin: impl crate::peripheral::Peripheral

+ 'd) -> Self { + pub fn new_typed(pin: impl crate::peripheral::Peripheral

+ 'd) -> Self { crate::into_ref!(pin); Self { pin } } diff --git a/hil-test/tests/gpio.rs b/hil-test/tests/gpio.rs index f8f5325fede..13b457f893e 100644 --- a/hil-test/tests/gpio.rs +++ b/hil-test/tests/gpio.rs @@ -65,8 +65,8 @@ mod tests { esp_hal_embassy::init(&clocks, timg0.timer0); Context { - io2: Input::new(io.pins.gpio2, Pull::Down), - io3: Output::new(io.pins.gpio3, Level::Low), + io2: Input::new_typed(io.pins.gpio2, Pull::Down), + io3: Output::new_typed(io.pins.gpio3, Level::Low), delay, } } diff --git a/hil-test/tests/qspi_read.rs b/hil-test/tests/qspi_read.rs index 6abeab451db..9c446335ec8 100644 --- a/hil-test/tests/qspi_read.rs +++ b/hil-test/tests/qspi_read.rs @@ -42,14 +42,14 @@ cfg_if::cfg_if! { struct Context { spi: esp_hal::peripherals::SPI2, dma_channel: Channel<'static, DmaChannel0, Blocking>, - miso: esp_hal::gpio::GpioPin<2>, - miso_mirror: Output<'static, GpioPin<3>>, + miso: GpioPin<2>, + miso_mirror: Output<'static>, clocks: Clocks<'static>, } fn execute( mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>, - mut miso_mirror: Output<'static, GpioPin<3>>, + mut miso_mirror: Output<'static>, wanted: u8, ) { const DMA_BUFFER_SIZE: usize = 4; diff --git a/hil-test/tests/qspi_write_read.rs b/hil-test/tests/qspi_write_read.rs index 602a6a964f3..ebde545ffe2 100644 --- a/hil-test/tests/qspi_write_read.rs +++ b/hil-test/tests/qspi_write_read.rs @@ -44,14 +44,14 @@ cfg_if::cfg_if! { struct Context { spi: esp_hal::peripherals::SPI2, dma_channel: Channel<'static, DmaChannel0, Blocking>, - mosi: esp_hal::gpio::GpioPin<2>, - mosi_mirror: Output<'static, GpioPin<3>>, + mosi: GpioPin<2>, + mosi_mirror: Output<'static>, clocks: Clocks<'static>, } fn execute( mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>, - mut mosi_mirror: Output<'static, GpioPin<3>>, + mut mosi_mirror: Output<'static>, wanted: u8, ) { const DMA_BUFFER_SIZE: usize = 4; diff --git a/hil-test/tests/spi_full_duplex_dma_async.rs b/hil-test/tests/spi_full_duplex_dma_async.rs index 674ac477e7e..a2fb71de9f5 100644 --- a/hil-test/tests/spi_full_duplex_dma_async.rs +++ b/hil-test/tests/spi_full_duplex_dma_async.rs @@ -57,7 +57,7 @@ const DMA_BUFFER_SIZE: usize = 5; struct Context { spi: SpiDmaBus<'static, SPI2, DmaChannel0, FullDuplexMode, Async>, pcnt_unit: Unit<'static, 0>, - out_pin: Output<'static, GpioPin<5>>, + out_pin: Output<'static>, mosi_mirror: GpioPin<2>, } diff --git a/hil-test/tests/spi_full_duplex_dma_pcnt.rs b/hil-test/tests/spi_full_duplex_dma_pcnt.rs index 0581e8e5746..6d3b77d7dd2 100644 --- a/hil-test/tests/spi_full_duplex_dma_pcnt.rs +++ b/hil-test/tests/spi_full_duplex_dma_pcnt.rs @@ -51,7 +51,7 @@ cfg_if::cfg_if! { struct Context { spi: SpiDma<'static, SPI2, DmaChannel0, FullDuplexMode, Blocking>, pcnt_unit: Unit<'static, 0>, - out_pin: Output<'static, GpioPin<5>>, + out_pin: Output<'static>, mosi_mirror: GpioPin<2>, } diff --git a/hil-test/tests/spi_half_duplex_read.rs b/hil-test/tests/spi_half_duplex_read.rs index b8892c79dd2..d0ec0daec02 100644 --- a/hil-test/tests/spi_half_duplex_read.rs +++ b/hil-test/tests/spi_half_duplex_read.rs @@ -16,7 +16,7 @@ use esp_hal::{ dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf}, dma_buffers, - gpio::{GpioPin, Io, Level, Output}, + gpio::{Io, Level, Output}, peripherals::SPI2, prelude::*, spi::{ @@ -42,7 +42,7 @@ cfg_if::cfg_if! { struct Context { spi: SpiDma<'static, SPI2, DmaChannel0, HalfDuplexMode, Blocking>, - miso_mirror: Output<'static, GpioPin<3>>, + miso_mirror: Output<'static>, } #[cfg(test)]