From fefee1577b2da3ea6da5dd56eeaac2ff2b8c04fc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Sep 2024 18:54:29 +0200 Subject: [PATCH] bench/sim: Update. --- bench/sim.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bench/sim.py b/bench/sim.py index f583c84..f7f2348 100755 --- a/bench/sim.py +++ b/bench/sim.py @@ -34,11 +34,11 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000): # Sampler -------------------------------------------------------------------------------- data = Signal(8) self.sync += data.eq(data + 1) - self.submodules.sampler = Sampler(data) + self.sampler = Sampler(data) # DRAMFIFO --------------------------------------------------------------------------------- from litedram.frontend.fifo import LiteDRAMFIFO - self.submodules.fifo = LiteDRAMFIFO( + self.fifo = LiteDRAMFIFO( data_width = 8, base = 0x00000000, depth = 0x01000000, # 16MB @@ -49,7 +49,7 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000): # UDPStreamer ------------------------------------------------------------------------------ from liteeth.common import convert_ip from liteeth.frontend.stream import LiteEthStream2UDPTX - udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8) + udp_port = self.ethcore_etherbone.udp.crossbar.get_port(host_udp_port, dw=8) udp_streamer = LiteEthStream2UDPTX( ip_address = convert_ip(host_ip), udp_port = host_udp_port,