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PPCPrivateLinkage.cpp
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PPCPrivateLinkage.cpp
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/*******************************************************************************
* Copyright IBM Corp. and others 2000
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at https://www.eclipse.org/legal/epl-2.0/
* or the Apache License, Version 2.0 which accompanies this distribution and
* is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following
* Secondary Licenses when the conditions for such availability set
* forth in the Eclipse Public License, v. 2.0 are satisfied: GNU
* General Public License, version 2 with the GNU Classpath
* Exception [1] and GNU General Public License, version 2 with the
* OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] https://openjdk.org/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0-only WITH Classpath-exception-2.0 OR GPL-2.0-only WITH OpenJDK-assembly-exception-1.0
*******************************************************************************/
#include "codegen/PPCPrivateLinkage.hpp"
#include "codegen/OMRLinkage_inlines.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/VirtualGuard.hpp"
#include "env/CHTable.hpp"
#include "env/CompilerEnv.hpp"
#include "env/J2IThunk.hpp"
#include "env/PersistentCHTable.hpp"
#include "env/VMJ9.h"
#include "env/jittypes.h"
#include "il/LabelSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "p/codegen/CallSnippet.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/PPCEvaluator.hpp"
#include "p/codegen/PPCHelperCallSnippet.hpp"
#include "p/codegen/PPCInstruction.hpp"
#include "p/codegen/PPCTableOfConstants.hpp"
#include "p/codegen/StackCheckFailureSnippet.hpp"
#include "runtime/J9Profiler.hpp"
#include "runtime/J9ValueProfiler.hpp"
#define MIN_PROFILED_CALL_FREQUENCY (.075f)
#define MAX_PROFILED_CALL_FREQUENCY (.90f)
J9::Power::PrivateLinkage::PrivateLinkage(TR::CodeGenerator *cg)
: J9::PrivateLinkage(cg)
{
TR::Compilation *comp = cg->comp();
int i = 0;
bool is32bitLinux = false;
_properties._properties = 0;
_properties._registerFlags[TR::RealRegister::NoReg] = 0;
_properties._registerFlags[TR::RealRegister::gr0] = 0;
_properties._registerFlags[TR::RealRegister::gr1] = Preserved|PPC_Reserved; // system sp
// gr2 is Preserved in 32-bit Linux
if (comp->target().is64Bit())
{
_properties._registerFlags[TR::RealRegister::gr2] = 0;
}
else
{
if (comp->target().isAIX())
{
_properties._registerFlags[TR::RealRegister::gr2] = 0;
}
else if (comp->target().isLinux())
{
_properties._registerFlags[TR::RealRegister::gr2] = Preserved|PPC_Reserved;
is32bitLinux = true;
}
else
{
TR_ASSERT(0, "unsupported target");
}
}
_properties._registerFlags[TR::RealRegister::gr3] = IntegerReturn|IntegerArgument;
if (comp->target().is64Bit())
_properties._registerFlags[TR::RealRegister::gr4] = IntegerArgument;
else
_properties._registerFlags[TR::RealRegister::gr4] = IntegerReturn|IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr5] = IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr6] = IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr7] = IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr8] = IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr9] = IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr10] = IntegerArgument;
_properties._registerFlags[TR::RealRegister::gr11] = 0;
_properties._registerFlags[TR::RealRegister::gr12] = 0;
_properties._registerFlags[TR::RealRegister::gr13] = Preserved|PPC_Reserved; // meta data for 32bit, system for 64bit;
_properties._registerFlags[TR::RealRegister::gr14] = Preserved|PPC_Reserved; // J9 sp
if (comp->target().is64Bit())
{
_properties._registerFlags[TR::RealRegister::gr15] = Preserved|PPC_Reserved; // meta data
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
_properties._registerFlags[TR::RealRegister::gr16] = Preserved; // typical preserved reg
else
_properties._registerFlags[TR::RealRegister::gr16] = Preserved|PPC_Reserved; // JTOC
}
else
{
_properties._registerFlags[TR::RealRegister::gr15] = Preserved;
_properties._registerFlags[TR::RealRegister::gr16] = Preserved;
}
for (i = TR::RealRegister::gr17; i <= TR::RealRegister::LastGPR; i++)
_properties._registerFlags[i] = Preserved; // gr17 - gr31 preserved
_properties._registerFlags[TR::RealRegister::fp0] = FloatReturn|FloatArgument;
_properties._registerFlags[TR::RealRegister::fp1] = FloatArgument;
_properties._registerFlags[TR::RealRegister::fp2] = FloatArgument;
_properties._registerFlags[TR::RealRegister::fp3] = FloatArgument;
_properties._registerFlags[TR::RealRegister::fp4] = FloatArgument;
_properties._registerFlags[TR::RealRegister::fp5] = FloatArgument;
_properties._registerFlags[TR::RealRegister::fp6] = FloatArgument;
_properties._registerFlags[TR::RealRegister::fp7] = FloatArgument;
for (i = TR::RealRegister::fp8; i <= TR::RealRegister::LastFPR; i++)
_properties._registerFlags[i] = 0; // fp8 - fp31 volatile
for (i = TR::RealRegister::vsr32; i <= TR::RealRegister::LastVSR; i++)
_properties._registerFlags[i] = 0; // vsr32 - vsr63 volatile
for (i = TR::RealRegister::FirstCCR; i <= TR::RealRegister::LastCCR; i++)
_properties._registerFlags[i] = 0; // cr0 - cr7 volatile
_properties._numIntegerArgumentRegisters = 8;
_properties._firstIntegerArgumentRegister = 0;
_properties._numFloatArgumentRegisters = 8;
_properties._firstFloatArgumentRegister = 8;
_properties._argumentRegisters[0] = TR::RealRegister::gr3;
_properties._argumentRegisters[1] = TR::RealRegister::gr4;
_properties._argumentRegisters[2] = TR::RealRegister::gr5;
_properties._argumentRegisters[3] = TR::RealRegister::gr6;
_properties._argumentRegisters[4] = TR::RealRegister::gr7;
_properties._argumentRegisters[5] = TR::RealRegister::gr8;
_properties._argumentRegisters[6] = TR::RealRegister::gr9;
_properties._argumentRegisters[7] = TR::RealRegister::gr10;
_properties._argumentRegisters[8] = TR::RealRegister::fp0;
_properties._argumentRegisters[9] = TR::RealRegister::fp1;
_properties._argumentRegisters[10] = TR::RealRegister::fp2;
_properties._argumentRegisters[11] = TR::RealRegister::fp3;
_properties._argumentRegisters[12] = TR::RealRegister::fp4;
_properties._argumentRegisters[13] = TR::RealRegister::fp5;
_properties._argumentRegisters[14] = TR::RealRegister::fp6;
_properties._argumentRegisters[15] = TR::RealRegister::fp7;
_properties._firstIntegerReturnRegister = 0;
_properties._returnRegisters[0] = TR::RealRegister::gr3;
if (comp->target().is64Bit())
{
_properties._firstFloatReturnRegister = 1;
_properties._returnRegisters[1] = TR::RealRegister::fp0;
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
{
_properties._numAllocatableIntegerRegisters = 28; // 64 post-P10
_properties._firstAllocatableFloatArgumentRegister = 41; // 64 post-P10
_properties._lastAllocatableFloatVolatileRegister = 59; // 64 post-P10
}
else
{
_properties._numAllocatableIntegerRegisters = 27; // 64 pre-P10
_properties._firstAllocatableFloatArgumentRegister = 40; // 64 pre-P10
_properties._lastAllocatableFloatVolatileRegister = 58; // 64 pre-P10
}
}
else
{
_properties._firstFloatReturnRegister = 2;
_properties._returnRegisters[1] = TR::RealRegister::gr4;
_properties._returnRegisters[2] = TR::RealRegister::fp0;
if (is32bitLinux)
{
_properties._numAllocatableIntegerRegisters = 28; // 32 linux
_properties._firstAllocatableFloatArgumentRegister = 41; // 32 linux
_properties._lastAllocatableFloatVolatileRegister = 59; // 32 linux
}
else
{
_properties._numAllocatableIntegerRegisters = 29; // 32 non-linux
_properties._firstAllocatableFloatArgumentRegister = 42; // 32 non-linux
_properties._lastAllocatableFloatVolatileRegister = 60; // 32 non-linux
}
}
if (is32bitLinux)
{
_properties._firstAllocatableIntegerArgumentRegister = 8;
_properties._lastAllocatableIntegerVolatileRegister = 10;
}
else
{
_properties._firstAllocatableIntegerArgumentRegister = 9;
_properties._lastAllocatableIntegerVolatileRegister = 11;
}
_properties._numAllocatableFloatRegisters = 32;
_properties._numAllocatableVectorRegisters = 32;
_properties._numAllocatableCCRegisters = 8;
i = 0;
if (!is32bitLinux)
_properties._allocationOrder[i++] = TR::RealRegister::gr2;
_properties._allocationOrder[i++] = TR::RealRegister::gr12;
_properties._allocationOrder[i++] = TR::RealRegister::gr10;
_properties._allocationOrder[i++] = TR::RealRegister::gr9;
_properties._allocationOrder[i++] = TR::RealRegister::gr8;
_properties._allocationOrder[i++] = TR::RealRegister::gr7;
_properties._allocationOrder[i++] = TR::RealRegister::gr6;
_properties._allocationOrder[i++] = TR::RealRegister::gr5;
_properties._allocationOrder[i++] = TR::RealRegister::gr4;
_properties._allocationOrder[i++] = TR::RealRegister::gr3;
_properties._allocationOrder[i++] = TR::RealRegister::gr11;
_properties._allocationOrder[i++] = TR::RealRegister::gr0;
_properties._allocationOrder[i++] = TR::RealRegister::gr31;
_properties._allocationOrder[i++] = TR::RealRegister::gr30;
_properties._allocationOrder[i++] = TR::RealRegister::gr29;
_properties._allocationOrder[i++] = TR::RealRegister::gr28;
_properties._allocationOrder[i++] = TR::RealRegister::gr27;
_properties._allocationOrder[i++] = TR::RealRegister::gr26;
_properties._allocationOrder[i++] = TR::RealRegister::gr25;
_properties._allocationOrder[i++] = TR::RealRegister::gr24;
_properties._allocationOrder[i++] = TR::RealRegister::gr23;
_properties._allocationOrder[i++] = TR::RealRegister::gr22;
_properties._allocationOrder[i++] = TR::RealRegister::gr21;
_properties._allocationOrder[i++] = TR::RealRegister::gr20;
_properties._allocationOrder[i++] = TR::RealRegister::gr19;
_properties._allocationOrder[i++] = TR::RealRegister::gr18;
_properties._allocationOrder[i++] = TR::RealRegister::gr17;
if (comp->target().is64Bit())
{
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
_properties._allocationOrder[i++] = TR::RealRegister::gr16;
}
else
{
_properties._allocationOrder[i++] = TR::RealRegister::gr16;
_properties._allocationOrder[i++] = TR::RealRegister::gr15;
}
_properties._allocationOrder[i++] = TR::RealRegister::fp13;
_properties._allocationOrder[i++] = TR::RealRegister::fp12;
_properties._allocationOrder[i++] = TR::RealRegister::fp11;
_properties._allocationOrder[i++] = TR::RealRegister::fp10;
_properties._allocationOrder[i++] = TR::RealRegister::fp9;
_properties._allocationOrder[i++] = TR::RealRegister::fp8;
_properties._allocationOrder[i++] = TR::RealRegister::fp7;
_properties._allocationOrder[i++] = TR::RealRegister::fp6;
_properties._allocationOrder[i++] = TR::RealRegister::fp5;
_properties._allocationOrder[i++] = TR::RealRegister::fp4;
_properties._allocationOrder[i++] = TR::RealRegister::fp3;
_properties._allocationOrder[i++] = TR::RealRegister::fp2;
_properties._allocationOrder[i++] = TR::RealRegister::fp1;
_properties._allocationOrder[i++] = TR::RealRegister::fp0;
_properties._allocationOrder[i++] = TR::RealRegister::fp31;
_properties._allocationOrder[i++] = TR::RealRegister::fp30;
_properties._allocationOrder[i++] = TR::RealRegister::fp29;
_properties._allocationOrder[i++] = TR::RealRegister::fp28;
_properties._allocationOrder[i++] = TR::RealRegister::fp27;
_properties._allocationOrder[i++] = TR::RealRegister::fp26;
_properties._allocationOrder[i++] = TR::RealRegister::fp25;
_properties._allocationOrder[i++] = TR::RealRegister::fp24;
_properties._allocationOrder[i++] = TR::RealRegister::fp23;
_properties._allocationOrder[i++] = TR::RealRegister::fp22;
_properties._allocationOrder[i++] = TR::RealRegister::fp21;
_properties._allocationOrder[i++] = TR::RealRegister::fp20;
_properties._allocationOrder[i++] = TR::RealRegister::fp19;
_properties._allocationOrder[i++] = TR::RealRegister::fp18;
_properties._allocationOrder[i++] = TR::RealRegister::fp17;
_properties._allocationOrder[i++] = TR::RealRegister::fp16;
_properties._allocationOrder[i++] = TR::RealRegister::fp15;
_properties._allocationOrder[i++] = TR::RealRegister::fp14;
_properties._allocationOrder[i++] = TR::RealRegister::vsr32;
_properties._allocationOrder[i++] = TR::RealRegister::vsr33;
_properties._allocationOrder[i++] = TR::RealRegister::vsr34;
_properties._allocationOrder[i++] = TR::RealRegister::vsr35;
_properties._allocationOrder[i++] = TR::RealRegister::vsr36;
_properties._allocationOrder[i++] = TR::RealRegister::vsr37;
_properties._allocationOrder[i++] = TR::RealRegister::vsr38;
_properties._allocationOrder[i++] = TR::RealRegister::vsr39;
_properties._allocationOrder[i++] = TR::RealRegister::vsr40;
_properties._allocationOrder[i++] = TR::RealRegister::vsr41;
_properties._allocationOrder[i++] = TR::RealRegister::vsr42;
_properties._allocationOrder[i++] = TR::RealRegister::vsr43;
_properties._allocationOrder[i++] = TR::RealRegister::vsr44;
_properties._allocationOrder[i++] = TR::RealRegister::vsr45;
_properties._allocationOrder[i++] = TR::RealRegister::vsr46;
_properties._allocationOrder[i++] = TR::RealRegister::vsr47;
_properties._allocationOrder[i++] = TR::RealRegister::vsr48;
_properties._allocationOrder[i++] = TR::RealRegister::vsr49;
_properties._allocationOrder[i++] = TR::RealRegister::vsr50;
_properties._allocationOrder[i++] = TR::RealRegister::vsr51;
_properties._allocationOrder[i++] = TR::RealRegister::vsr52;
_properties._allocationOrder[i++] = TR::RealRegister::vsr53;
_properties._allocationOrder[i++] = TR::RealRegister::vsr54;
_properties._allocationOrder[i++] = TR::RealRegister::vsr55;
_properties._allocationOrder[i++] = TR::RealRegister::vsr56;
_properties._allocationOrder[i++] = TR::RealRegister::vsr57;
_properties._allocationOrder[i++] = TR::RealRegister::vsr58;
_properties._allocationOrder[i++] = TR::RealRegister::vsr59;
_properties._allocationOrder[i++] = TR::RealRegister::vsr60;
_properties._allocationOrder[i++] = TR::RealRegister::vsr61;
_properties._allocationOrder[i++] = TR::RealRegister::vsr62;
_properties._allocationOrder[i++] = TR::RealRegister::vsr63;
_properties._allocationOrder[i++] = TR::RealRegister::cr7;
_properties._allocationOrder[i++] = TR::RealRegister::cr6;
_properties._allocationOrder[i++] = TR::RealRegister::cr5;
_properties._allocationOrder[i++] = TR::RealRegister::cr1;
_properties._allocationOrder[i++] = TR::RealRegister::cr0;
_properties._allocationOrder[i++] = TR::RealRegister::cr2;
_properties._allocationOrder[i++] = TR::RealRegister::cr3;
_properties._allocationOrder[i++] = TR::RealRegister::cr4;
if (comp->target().is64Bit())
{
if (comp->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
_properties._preservedRegisterMapForGC = 0x0000ffff;
else
_properties._preservedRegisterMapForGC = 0x00007fff;
_properties._methodMetaDataRegister = TR::RealRegister::gr15;
_properties._normalStackPointerRegister = TR::RealRegister::gr14;
_properties._alternateStackPointerRegister = TR::RealRegister::NoReg;
_properties._TOCBaseRegister = TR::RealRegister::gr16;
// Volatile GPR (0,2-12) + FPR (0-31) + CCR (0-7) + VR (0-31)
_properties._numberOfDependencyGPRegisters = 12 + 32 + 8 + 32;
setOffsetToFirstParm(0);
_properties._offsetToFirstLocal = -8;
}
else
{
_properties._preservedRegisterMapForGC = 0x0001ffff;
_properties._methodMetaDataRegister = TR::RealRegister::gr13;
_properties._normalStackPointerRegister = TR::RealRegister::gr14;
_properties._alternateStackPointerRegister = TR::RealRegister::NoReg;
_properties._TOCBaseRegister = TR::RealRegister::NoReg;
if (is32bitLinux)
// Volatile GPR (0,3-12) + FPR (0-31) + CCR (0-7) + VR (0-31)
_properties._numberOfDependencyGPRegisters = 11 + 32 + 8 + 32;
else
// Volatile GPR (0,2-12) + FPR (0-31) + CCR (0-7) + VR (0-31)
_properties._numberOfDependencyGPRegisters = 12 + 32 + 8 + 32;
setOffsetToFirstParm(0);
_properties._offsetToFirstLocal = -4;
}
_properties._computedCallTargetRegister = TR::RealRegister::gr0; // gr11 = interface, gr12 = virtual, so we need something else for computed
_properties._vtableIndexArgumentRegister = TR::RealRegister::gr12;
_properties._j9methodArgumentRegister = TR::RealRegister::gr3; // TODO:JSR292: Confirm
}
const TR::PPCLinkageProperties& J9::Power::PrivateLinkage::getProperties()
{
return _properties;
}
void J9::Power::PrivateLinkage::initPPCRealRegisterLinkage()
{
TR::Machine *machine = cg()->machine();
const TR::PPCLinkageProperties &linkage = getProperties();
int icount, ret_count=0, lockedGPRs = 0;
for (icount=TR::RealRegister::FirstGPR; icount<=TR::RealRegister::gr12;
icount++)
{
if (linkage.getReserved((TR::RealRegister::RegNum)icount))
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setState(TR::RealRegister::Locked);
++lockedGPRs;
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setAssignedRegister(machine->getRealRegister((TR::RealRegister::RegNum)icount));
}
else
{
int weight;
if (linkage.getIntegerReturn((TR::RealRegister::RegNum)icount))
{
weight = ++ret_count;
}
else
{
if (icount < TR::RealRegister::gr3)
{
weight = 2 + icount;
}
else
{
weight = icount;
}
}
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(weight);
}
}
for (icount=TR::RealRegister::LastGPR;
icount>=TR::RealRegister::gr13; icount--)
{
if (linkage.getReserved((TR::RealRegister::RegNum)icount))
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setState(TR::RealRegister::Locked);
++lockedGPRs;
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setAssignedRegister(machine->getRealRegister((TR::RealRegister::RegNum)icount));
}
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000-icount);
}
int lowestFPRWeight = TR::RealRegister::FirstFPR;
for (icount=TR::RealRegister::FirstFPR;
icount<=TR::RealRegister::LastFPR; icount++)
{
if (linkage.getPreserved((TR::RealRegister::RegNum)icount))
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000-icount);
}
else
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(lowestFPRWeight);
}
}
for (icount=TR::RealRegister::FirstVRF;
icount<=TR::RealRegister::LastVRF; icount++)
{
if (linkage.getPreserved((TR::RealRegister::RegNum)icount))
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000-icount);
}
else
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(icount);
}
}
for (icount=TR::RealRegister::FirstCCR;
icount<=TR::RealRegister::LastCCR; icount++)
{
if (linkage.getPreserved((TR::RealRegister::RegNum)icount))
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000-icount);
}
else
{
machine->getRealRegister((TR::RealRegister::RegNum)icount)->setWeight(icount);
}
}
machine->setNumberOfLockedRegisters(TR_GPR, lockedGPRs);
machine->setNumberOfLockedRegisters(TR_FPR, 0);
machine->setNumberOfLockedRegisters(TR_VRF, 0);
}
uint32_t J9::Power::PrivateLinkage::getRightToLeft()
{
return getProperties().getRightToLeft();
}
void J9::Power::PrivateLinkage::mapStack(TR::ResolvedMethodSymbol *method)
{
ListIterator<TR::AutomaticSymbol> automaticIterator(&method->getAutomaticList());
TR::AutomaticSymbol *localCursor = automaticIterator.getFirst();
const TR::PPCLinkageProperties& linkage = getProperties();
TR::RealRegister::RegNum regIndex;
int32_t firstLocalOffset = linkage.getOffsetToFirstLocal();
uint32_t stackIndex = firstLocalOffset;
int32_t lowGCOffset = stackIndex;
TR::GCStackAtlas *atlas = cg()->getStackAtlas();
int32_t firstLocalGCIndex = atlas->getNumberOfParmSlotsMapped();
// map all garbage collected references together so can concisely represent
// stack maps. They must be mapped so that the GC map index in each local
// symbol is honoured.
uint32_t numberOfLocalSlotsMapped = atlas->getNumberOfSlotsMapped() - atlas->getNumberOfParmSlotsMapped();
stackIndex -= numberOfLocalSlotsMapped * TR::Compiler->om.sizeofReferenceAddress();
if (comp()->useCompressedPointers())
{
// If we have any local objects we have to make sure they're aligned properly when compressed pointers are used,
// otherwise pointer compression may clobber part of the pointer.
// Each auto's GC index will have already been aligned, we just need to make sure
// we align the starting stack offset.
uint32_t unalignedStackIndex = stackIndex;
stackIndex &= ~(TR::Compiler->om.getObjectAlignmentInBytes() - 1);
uint32_t paddingBytes = unalignedStackIndex - stackIndex;
if (paddingBytes > 0)
{
TR_ASSERT((paddingBytes & (TR::Compiler->om.sizeofReferenceAddress() - 1)) == 0, "Padding bytes should be a multiple of the slot/pointer size");
uint32_t paddingSlots = paddingBytes / TR::Compiler->om.sizeofReferenceAddress();
atlas->setNumberOfSlotsMapped(atlas->getNumberOfSlotsMapped() + paddingSlots);
}
}
// Map local references again to set the stack position correct according to
// the GC map index.
//
for (localCursor = automaticIterator.getFirst(); localCursor; localCursor = automaticIterator.getNext())
{
if (localCursor->getGCMapIndex() >= 0)
{
localCursor->setOffset(stackIndex + TR::Compiler->om.sizeofReferenceAddress() * (localCursor->getGCMapIndex() - firstLocalGCIndex));
if (localCursor->getGCMapIndex() == atlas->getIndexOfFirstInternalPointer())
{
atlas->setOffsetOfFirstInternalPointer(localCursor->getOffset() - firstLocalOffset);
}
}
}
method->setObjectTempSlots((lowGCOffset - stackIndex) / TR::Compiler->om.sizeofReferenceAddress());
lowGCOffset = stackIndex;
// Now map the rest of the locals
//
automaticIterator.reset();
localCursor = automaticIterator.getFirst();
while (localCursor != NULL)
{
if (comp()->target().is64Bit())
{
if (localCursor->getGCMapIndex() < 0 &&
localCursor->getSize() != 8)
{
mapSingleAutomatic(localCursor, stackIndex);
}
}
else
{
if (localCursor->getGCMapIndex() < 0 &&
localCursor->getDataType() != TR::Double)
{
mapSingleAutomatic(localCursor, stackIndex);
}
}
localCursor = automaticIterator.getNext();
}
automaticIterator.reset();
localCursor = automaticIterator.getFirst();
while (localCursor != NULL)
{
if (comp()->target().is64Bit())
{
if (localCursor->getGCMapIndex() < 0 &&
localCursor->getSize() == 8)
{
stackIndex -= (stackIndex & 0x4)?4:0;
mapSingleAutomatic(localCursor, stackIndex);
}
}
else
{
if (localCursor->getGCMapIndex() < 0 &&
localCursor->getDataType() == TR::Double)
{
stackIndex -= (stackIndex & 0x4)?4:0;
mapSingleAutomatic(localCursor, stackIndex);
}
}
localCursor = automaticIterator.getNext();
}
method->setLocalMappingCursor(stackIndex);
mapIncomingParms(method);
atlas->setLocalBaseOffset(lowGCOffset - firstLocalOffset);
atlas->setParmBaseOffset(atlas->getParmBaseOffset() + getOffsetToFirstParm() - firstLocalOffset);
}
void J9::Power::PrivateLinkage::mapSingleAutomatic(TR::AutomaticSymbol *p, uint32_t &stackIndex)
{
int32_t roundup = (comp()->useCompressedPointers() && p->isLocalObject() ? TR::Compiler->om.getObjectAlignmentInBytes() : TR::Compiler->om.sizeofReferenceAddress()) - 1;
int32_t roundedSize = (p->getSize() + roundup) & (~roundup);
if (roundedSize == 0)
roundedSize = 4;
p->setOffset(stackIndex -= roundedSize);
}
void J9::Power::PrivateLinkage::setParameterLinkageRegisterIndex(TR::ResolvedMethodSymbol *method)
{
ListIterator<TR::ParameterSymbol> paramIterator(&(method->getParameterList()));
TR::ParameterSymbol *paramCursor = paramIterator.getFirst();
int32_t numIntArgs = 0, numFloatArgs = 0;
const TR::PPCLinkageProperties& properties = getProperties();
while ( (paramCursor!=NULL) &&
( (numIntArgs < properties.getNumIntArgRegs()) ||
(numFloatArgs < properties.getNumFloatArgRegs()) ) )
{
int32_t index = -1;
switch (paramCursor->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Address:
if (numIntArgs<properties.getNumIntArgRegs())
{
index = numIntArgs;
}
numIntArgs++;
break;
case TR::Int64:
if (numIntArgs<properties.getNumIntArgRegs())
{
index = numIntArgs;
}
if (comp()->target().is64Bit())
numIntArgs ++;
else
numIntArgs += 2;
break;
case TR::Float:
case TR::Double:
if (numFloatArgs<properties.getNumFloatArgRegs())
{
index = numFloatArgs;
}
numFloatArgs++;
break;
}
paramCursor->setLinkageRegisterIndex(index);
paramCursor = paramIterator.getNext();
}
}
bool J9::Power::PrivateLinkage::hasToBeOnStack(TR::ParameterSymbol *parm)
{
TR::ResolvedMethodSymbol *bodySymbol = comp()->getJittedMethodSymbol();
TR_OpaqueClassBlock *throwableClass;
/* Defect 138664: All synchronized methods can potentially throw an
IllegalMonitorState exception so we must always save the this pointer on
to the stack so the exception handler can unlock the object. Also,
hasCall() does not consider jitNewObject() calls so an OOM exception could
be thrown even when hasCall() returns false */
TR_J9VMBase *fej9 = (TR_J9VMBase *)(fe());
bool result = (parm->getAssignedGlobalRegisterIndex()>=0 &&
( ( parm->getLinkageRegisterIndex()==0 &&
parm->isCollectedReference() &&
!bodySymbol->isStatic() &&
( ( bodySymbol->isSynchronised()
) ||
(
!strncmp(bodySymbol->getResolvedMethod()->nameChars(), "<init>", 6) &&
( (throwableClass = fej9->getClassFromSignature("Ljava/lang/Throwable;", 21, bodySymbol->getResolvedMethod())) == 0 ||
fej9->isInstanceOf(bodySymbol->getResolvedMethod()->containingClass(), throwableClass, true) != TR_no
)
)
)
) ||
parm->isParmHasToBeOnStack()
)
);
// Problem Report 96788:
//
// There is a potential race condition here. Because of the query to the frontend this function could
// possibly return different results at different points in the compilation dependent on whether the
// java/lang/Throwable class is resolved or not. This is a problem because this query is used to
// determine whether we need to generate a GC map for this parameter and whether we need to generate
// a store out to the stack for this parameter. Because these two queries happen at two different points
// in the compilation we could encounter a situation where we generate a GC map for this parameter but
// not generate a store out to the stack. This causes assertions in the VM if we hit a GC point in this
// compilation unit. To avoid this issue we cache the result of this function and directly modify the
// parameter symbol.
// TODO : Where does the java/lang/Throwable code below originate and why is it here? This seems like
// a very hacky fix to a very specific problem. Also why is this code not commoned up with Z and why
// is it missing for X?
if (result)
parm->setParmHasToBeOnStack();
return result;
}
static TR::Instruction *unrollPrologueInitLoop(TR::CodeGenerator *cg, TR::Node *node, int32_t num, int32_t initSlotOffset, TR::Register *nullReg,
TR::RealRegister *gr11, TR::RealRegister *baseInitReg, TR::RealRegister *gr12, TR::RealRegister *cr0, TR::LabelSymbol *loopLabel,
TR::Instruction *cursor)
{
TR_HeapMemory trHeapMemory = cg->trMemory();
int32_t wordsToUnroll = num;
TR::Compilation *comp = cg->comp();
static bool disableVSXMemInit = (feGetEnv("TR_disableVSXMemInit") != NULL); //Disable toggle incase we break in production.
bool use8Bytes = ((cg->is64BitProcessor() && TR::Compiler->om.sizeofReferenceAddress() == 4) || TR::Compiler->om.sizeofReferenceAddress() == 8);
bool useVectorStores = (comp->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && comp->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX) && !disableVSXMemInit);
if (useVectorStores)
{
int32_t wordsUnrolledPerIteration = (128 * 4) / (TR::Compiler->om.sizeofReferenceAddress() * 8); // (number of bits cleared by one iteration using 4 stxvw4x) / (number of bits per word i.e. bits in a java pointer)
if (wordsToUnroll >= wordsUnrolledPerIteration)
{
TR::RealRegister *vectorNullReg = cg->machine()->getRealRegister(TR::RealRegister::vr0);
cursor = generateTrg1Src2Instruction(cg, TR::InstOpCode::xxlxor, node, vectorNullReg, vectorNullReg, vectorNullReg, cursor);
int32_t loopIterations = wordsToUnroll / wordsUnrolledPerIteration;
wordsToUnroll = wordsToUnroll % wordsUnrolledPerIteration;
TR_ASSERT_FATAL( initSlotOffset <= UPPER_IMMED, "initSlotOffset (%d) is too big to fit in a signed immediate field", initSlotOffset);
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, gr12, baseInitReg, initSlotOffset, cursor);
baseInitReg = gr12;
initSlotOffset = 0;
if (loopIterations > 1)
{
cursor = loadConstant(cg, node, loopIterations, gr11, cursor);
cursor = generateSrc1Instruction(cg, TR::InstOpCode::mtctr, node, gr11, 0, cursor);
cursor = loadConstant(cg, node, 16, gr11, cursor); // r11 is now free so we can use it for const 16 offset
cursor = generateLabelInstruction(cg, TR::InstOpCode::label, node, loopLabel, cursor);
}
else
{
cursor = loadConstant(cg, node, 16, gr11, cursor);
}
cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stxvw4x, node, TR::MemoryReference::createWithIndexReg(cg, nullReg, baseInitReg, 16), vectorNullReg, cursor);
cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stxvw4x, node, TR::MemoryReference::createWithIndexReg(cg, gr11 , baseInitReg, 16), vectorNullReg, cursor);
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, baseInitReg, baseInitReg, 32, cursor);
cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stxvw4x, node, TR::MemoryReference::createWithIndexReg(cg, nullReg, baseInitReg, 16), vectorNullReg, cursor);
cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stxvw4x, node, TR::MemoryReference::createWithIndexReg(cg, gr11 , baseInitReg, 16), vectorNullReg, cursor);
if (loopIterations > 1)
{
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, baseInitReg, baseInitReg, 32, cursor);
cursor = generateConditionalBranchInstruction(cg, TR::InstOpCode::bdnz, node, loopLabel, cr0, cursor);
}
else
{
initSlotOffset += 32; // if no loops needed, then no need to generate the addi when we can just increase the offset
}
}
if (use8Bytes && TR::Compiler->om.sizeofReferenceAddress() == 4)
{
// we only need to do half the work since we'll be using std to wipe two 32bit words
// NOTE: we need to do a stw at the end if this is odd since std only stores 8 bytes at a time
// (and we have 4 bytes leftover after the loop)
wordsToUnroll /= 2;
}
// unroll any remaining words
TR::InstOpCode::Mnemonic instruction = (use8Bytes ? TR::InstOpCode::std : TR::InstOpCode::stw);
int32_t storeSize = (use8Bytes ? 8 : 4);
while (wordsToUnroll > 0)
{
cursor = generateMemSrc1Instruction(cg, instruction, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset, storeSize), nullReg, cursor);
initSlotOffset += storeSize;
wordsToUnroll--;
}
// if we had an odd number of words to unroll with a 64bit arch, we need to add one more store to clear it
// (since we used store double word)
if ((use8Bytes && TR::Compiler->om.sizeofReferenceAddress() == 4) && (num % 2 == 1))
{
cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset, 4), nullReg, cursor);
}
}
else
{
if (use8Bytes && TR::Compiler->om.sizeofReferenceAddress() == 4)
wordsToUnroll /= 2;
if (wordsToUnroll >=4)
{
if (wordsToUnroll >=8)
{
if(baseInitReg->getRegisterNumber()== TR::RealRegister::gr14)
{
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, gr12,baseInitReg, 0 , cursor);
baseInitReg = gr12;
}
cursor = loadConstant(cg, node, (int32_t)(wordsToUnroll/4), gr11, cursor);
cursor = generateSrc1Instruction(cg, TR::InstOpCode::mtctr, node, gr11, 0, cursor);
cursor = generateLabelInstruction(cg, TR::InstOpCode::label, node, loopLabel, cursor);
}
// This clears (wordsToUnroll/4) * (use8Bytes ? 32: 16) bytes.
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset, TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset+(use8Bytes?8:4), TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset+(use8Bytes?16:8), TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset+(use8Bytes?24:12), TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
if (wordsToUnroll >=8)
{
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, gr12, gr12, (use8Bytes?32:16), cursor);
cursor = generateConditionalBranchInstruction(cg, TR::InstOpCode::bdnz, node, loopLabel, cr0, cursor);
}
else
{
initSlotOffset += (use8Bytes?32:16);
}
}
// Clears ((use8Bytes ? 8 : 4)* (wordsToUnroll % 4)) bytes
switch (wordsToUnroll % 4)
{
case 3:
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset+(use8Bytes?16:8), TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
case 2:
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset+(use8Bytes?8:4), TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
case 1:
cursor = generateMemSrc1Instruction(cg, use8Bytes? TR::InstOpCode::std : TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset, TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
break;
}
// Last one if needed
if (use8Bytes && TR::Compiler->om.sizeofReferenceAddress() == 4 && num % 2 == 1)
{
if (wordsToUnroll %4)
initSlotOffset += (use8Bytes?8:4)*(wordsToUnroll%4);
cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stw, node, TR::MemoryReference::createWithDisplacement(cg, baseInitReg, initSlotOffset, TR::Compiler->om.sizeofReferenceAddress()), nullReg, cursor);
}
}
return cursor;
}
static int32_t calculateFrameSize(TR::RealRegister::RegNum &intSavedFirst,
int32_t &argSize,
int32_t &size,
int32_t ®SaveOffset,
int32_t &saveSize,
TR::CodeGenerator *cg,
bool &saveLR)
{
TR::Compilation *comp = cg->comp();
TR::Machine *machine = cg->machine();
TR::Linkage* linkage = cg->getLinkage(TR_Private);
const TR::PPCLinkageProperties& properties = cg->getProperties();
int32_t firstLocalOffset = properties.getOffsetToFirstLocal();
int32_t registerSaveDescription = 0;
// Currently no non-volatile FPR's in private linkage
// If we change the private linkage to add non-volatile FPR's or CCR's
// we should clean up this code to be independent of the linkage
// (ie, to test properties.getPreserved).
//
saveLR = (!cg->getSnippetList().empty() ||
comp->getJittedMethodSymbol()->isEHAware() ||
cg->canExceptByTrap() ||
machine->getLinkRegisterKilled());
if (0 && comp->target().is64Bit())
{
argSize = (cg->getLargestOutgoingArgSize() * 2) + linkage->getOffsetToFirstParm();
}
else
{
argSize = cg->getLargestOutgoingArgSize() + linkage->getOffsetToFirstParm();
}
while (intSavedFirst<=TR::RealRegister::LastGPR && !machine->getRealRegister(intSavedFirst)->getHasBeenAssignedInMethod())
intSavedFirst=(TR::RealRegister::RegNum)((uint32_t)intSavedFirst+1);
if (comp->target().is64Bit() && comp->compilePortableCode() &&
!comp->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10) && cg->getSavesNonVolatileGPRsForGC())
{
// When compiling code that contains a Direct-to-JNI call, we need to save all the non-volatile registers
// so the GC will have access to them. If we are compiling portable code (CRIU or PortableAOT) then we
// might be compiling code that will run on PWR10 which allows for R16 to be marked collectible. Therefore
// we need to save&restore R16 for portable code containing a Direct-to-JNI call in case a GC cycle occurs
// while some non-portable code down the stack is using R16 to hold a collectible object.
TR_ASSERT_FATAL( intSavedFirst == TR::RealRegister::gr17, "Portable compile expected first saved GPR to be R17" );
intSavedFirst = TR::RealRegister::gr16;
}
// the registerSaveDescription is emitted as follows:
// 0000 0000 0000 000 0 0000 0000 0000 0000
// <---- ---->
// 17 bits for saved GPRs (r15 - r32)
// so the first bit represents whether r15 is saved & so on
// <--- --->
// 15 bits to represent the save offset from bp
// allowing 2^15 bytes / 8 = 4096 locals in 64-bit
//
for (int32_t i = intSavedFirst; i <= TR::RealRegister::LastGPR; i++)
{
registerSaveDescription |= 1 << (i - TR::RealRegister::gr15);
}
// Currently no non-volatile FPR's in private linkage
saveSize += (TR::RealRegister::LastGPR - intSavedFirst + 1) * TR::Compiler->om.sizeofReferenceAddress();
size += saveSize+argSize;
if (!saveLR && size == -firstLocalOffset) // TODO: have a emptyFrame bool to be used throughout
{
TR_ASSERT(argSize==0, "Wrong descriptor setting");
size = 0;
cg->setFrameSizeInBytes(0);
}
else
{
//Align the stack frame
const uint32_t alignBytes = 16;
size = (size + (alignBytes - 1) & (~(alignBytes - 1)));
regSaveOffset = (size-argSize+firstLocalOffset);
//In MethodMetaData jitAddSpilledRegisters, we lookup the regSaveOffset
//which must match up to what we have here or else the stackwalker will
//run into errors.
//Fail the compilation if we overflow the 15 bits of regSaveOffset.
if(regSaveOffset > 0x7FFF || regSaveOffset < 0 )
{
//Fail if we underflow or overflow.
comp->failCompilation<TR::CompilationInterrupted>("Overflowed or underflowed bounds of regSaveOffset in calculateFrameSize.");
}
if (comp->getOption(TR_TraceCG))
traceMsg(comp, "PPCLinkage calculateFrameSize registerSaveDescription: 0x%x regSaveOffset: %x\n", registerSaveDescription, regSaveOffset);
registerSaveDescription |= (regSaveOffset << 17); // see above for details
cg->setFrameSizeInBytes(size+firstLocalOffset);
TR_ASSERT((size-argSize+firstLocalOffset)<2048*1024, "Descriptor overflowed.\n");
}
return registerSaveDescription;
}
void J9::Power::PrivateLinkage::createPrologue(TR::Instruction *cursor)
{
TR::Machine *machine = cg()->machine();
const TR::PPCLinkageProperties& properties = getProperties();
TR::ResolvedMethodSymbol *bodySymbol = comp()->getJittedMethodSymbol();
TR::RealRegister *stackPtr = cg()->getStackPointerRegister();
TR::RealRegister *metaBase = cg()->getMethodMetaDataRegister();
TR::RealRegister *gr0 = machine->getRealRegister(TR::RealRegister::gr0);
TR::RealRegister *gr11 = machine->getRealRegister(TR::RealRegister::gr11);
TR::RealRegister *gr12 = machine->getRealRegister(TR::RealRegister::gr12);
TR::RealRegister *cr0 = machine->getRealRegister(TR::RealRegister::cr0);
TR::Node *firstNode = comp()->getStartTree()->getNode();
int32_t size = -(bodySymbol->getLocalMappingCursor());
int32_t residualSize, saveSize=0, argSize;
int32_t registerSaveDescription=0;
int32_t firstLocalOffset = properties.getOffsetToFirstLocal();
int i;
TR::RealRegister::RegNum intSavedFirst=TR::RealRegister::gr15;
TR::RealRegister::RegNum regIndex;
int32_t regSaveOffset = 0;
bool saveLR = false;
registerSaveDescription = calculateFrameSize(intSavedFirst, argSize, size, regSaveOffset, saveSize, cg(), saveLR);
cg()->setRegisterSaveDescription(registerSaveDescription);
residualSize = size;
if (comp()->getOption(TR_EntryBreakPoints))
{
cursor = generateInstruction(cg(), TR::InstOpCode::bad, firstNode, cursor);
}
bool fsd = comp()->getOption(TR_FullSpeedDebug);
// If in Full Speed Debug, the parameters have to be saved before the call to Stack Check
// and the stack map and register maps have to be updated accordingly
if (fsd)
{
// Only call saveArguments for pushing the parameters on the stack when we are on Full Speed Debug
cursor = saveArguments(cursor, fsd, true);
}
// Load the stack limit offset for comparison
if (!comp()->isDLT())
cursor = generateTrg1MemInstruction(cg(),TR::InstOpCode::Op_load, firstNode, gr11,
TR::MemoryReference::createWithDisplacement(cg(), metaBase, cg()->getStackLimitOffset(),
TR::Compiler->om.sizeofReferenceAddress()), cursor);
if (cg()->getFrameSizeInBytes() || saveLR)
{
if ((cg()->getFrameSizeInBytes() + TR::Compiler->om.sizeofReferenceAddress()) > (-LOWER_IMMED))
{
// Large Frame Support