diff --git a/cmake/modules/OmrCompilerSupport.cmake b/cmake/modules/OmrCompilerSupport.cmake index 506ba1ac5bb..85724bb3288 100644 --- a/cmake/modules/OmrCompilerSupport.cmake +++ b/cmake/modules/OmrCompilerSupport.cmake @@ -133,8 +133,8 @@ function(ppc_spp2s_files out_var compiler) set(${out_var} "${result}" PARENT_SCOPE) endfunction() -function(aarch64_spp_files out_var compiler) - # Aarch64 .spp files are equivalent to standard .S files +function(common_spp_files out_var compiler) + # AArch64 and RISC-V .spp files are equivalent to standard .S files # ie. assembler + c pre-processor foreach(in_f ${ARGN}) get_filename_component(extension ${in_f} EXT) @@ -155,8 +155,8 @@ function(omr_inject_object_modification_targets result compiler_name) # Handle SPP files if(OMR_ARCH_POWER) ppc_spp2s_files(arg ${compiler_name} ${arg}) - elseif(OMR_ARCH_AARCH64) - aarch64_spp_files(arg ${compiler_name} ${arg}) + elseif(OMR_ARCH_AARCH64 OR OMR_ARCH_RISCV) + common_spp_files(arg ${compiler_name} ${arg}) endif() diff --git a/compiler/env/Processors.hpp b/compiler/env/Processors.hpp index 734569d681b..5f3786a66a0 100644 --- a/compiler/env/Processors.hpp +++ b/compiler/env/Processors.hpp @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) 2000, 2019 IBM Corp. and others + * Copyright (c) 2000, 2020 IBM Corp. and others * * This program and the accompanying materials are made available under * the terms of the Eclipse Public License 2.0 which accompanies this @@ -50,11 +50,16 @@ enum Processor #include "x/env/X86ProcessorEnum.hpp" LastX86ProcessorMark, + FirstRISCVProcessorMark, + #include "riscv/env/RVProcessorEnum.hpp" + LastRISCVProcessorMark, + NumARMProcessors = LastARMProcessorMark-FirstARMProcessorMark-1, NumARM64Processors = LastARM64ProcessorMark-FirstARM64ProcessorMark-1, NumPowerProcessors = LastPowerProcessorMark-FirstPowerProcessorMark-1, NumZProcessors = LastZProcessorMark-FirstZProcessorMark-1, - NumX86Processors = LastX86ProcessorMark-FirstX86ProcessorMark-1 + NumX86Processors = LastX86ProcessorMark-FirstX86ProcessorMark-1, + NumRISCVProcessors = LastRISCVProcessorMark-FirstRISCVProcessorMark-1 }; @@ -159,7 +164,12 @@ enum TR_Processor TR_LastX86Processor, TR_X86ProcessorAMDOpteron = TR_LastX86Processor, - TR_LastProcessor = TR_LastX86Processor, + TR_FirstRISCVProcessor, + TR_RV64G, + TR_DefaultRISCVProcessor = TR_RV64G, + TR_LastRISCVProcessor = TR_RV64G, + + TR_LastProcessor = TR_LastRISCVProcessor, TR_NumberOfProcessors }; diff --git a/compiler/riscv/codegen/OMRCodeGenerator.hpp b/compiler/riscv/codegen/OMRCodeGenerator.hpp index d796c8bcdc1..8b1c5222275 100644 --- a/compiler/riscv/codegen/OMRCodeGenerator.hpp +++ b/compiler/riscv/codegen/OMRCodeGenerator.hpp @@ -61,6 +61,14 @@ extern TR::Instruction *loadConstant32(TR::CodeGenerator *cg, TR::Node *node, in */ extern TR::Instruction *loadConstant64(TR::CodeGenerator *cg, TR::Node *node, int64_t value, TR::Register *trgReg, TR::Instruction *cursor = NULL); +struct TR_RVBinaryEncodingData : public TR_BinaryEncodingData + { + int32_t estimate; + TR::Instruction *cursorInstruction; + TR::Instruction *i2jEntryInstruction; + TR::Recompilation *recomp; + }; + namespace OMR { diff --git a/compiler/riscv/codegen/OMRLinkage.cpp b/compiler/riscv/codegen/OMRLinkage.cpp index 52e1f08ed57..fe2539caaf6 100644 --- a/compiler/riscv/codegen/OMRLinkage.cpp +++ b/compiler/riscv/codegen/OMRLinkage.cpp @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (c) 2019, 2019 IBM Corp. and others + * Copyright (c) 2019, 2020 IBM Corp. and others * * This program and the accompanying materials are made available under * the terms of the Eclipse Public License 2.0 which accompanies this @@ -161,4 +161,4 @@ OMR::RV::Linkage::numArgumentRegisters(TR_RegisterKinds kind) default: return 0; } - } \ No newline at end of file + } diff --git a/compiler/riscv/codegen/OMRLinkage.hpp b/compiler/riscv/codegen/OMRLinkage.hpp index d176bca250b..7f5c9da27d1 100644 --- a/compiler/riscv/codegen/OMRLinkage.hpp +++ b/compiler/riscv/codegen/OMRLinkage.hpp @@ -35,42 +35,22 @@ namespace OMR { typedef OMR::RV::Linkage LinkageConnector; } #include #include -#include "codegen/CodeGenerator.hpp" #include "codegen/InstOpCode.hpp" #include "codegen/RealRegister.hpp" #include "codegen/Register.hpp" -#include "codegen/RegisterDependency.hpp" #include "env/TRMemory.hpp" class TR_FrontEnd; namespace TR { class AutomaticSymbol; } +namespace TR { class CodeGenerator; } namespace TR { class Compilation; } namespace TR { class Instruction; } namespace TR { class MemoryReference; } namespace TR { class Node; } namespace TR { class ParameterSymbol; } +namespace TR { class RegisterDependencyConditions; } namespace TR { class ResolvedMethodSymbol; } -/** - * @brief Adds dependency - */ -inline void -addDependency( - TR::RegisterDependencyConditions *dep, - TR::Register *vreg, - TR::RealRegister::RegNum rnum, - TR_RegisterKinds rk, - TR::CodeGenerator *cg) - { - if (vreg == NULL) - { - vreg = cg->allocateRegister(rk); - } - - dep->addPreCondition(vreg, rnum); - dep->addPostCondition(vreg, rnum); - } - namespace TR { class RVMemoryArgument diff --git a/compiler/riscv/codegen/RVSystemLinkage.cpp b/compiler/riscv/codegen/RVSystemLinkage.cpp index 068e975bef2..9959f4d1807 100644 --- a/compiler/riscv/codegen/RVSystemLinkage.cpp +++ b/compiler/riscv/codegen/RVSystemLinkage.cpp @@ -26,6 +26,7 @@ #include "codegen/Linkage.hpp" #include "codegen/Linkage_inlines.hpp" #include "codegen/MemoryReference.hpp" +#include "codegen/RegisterDependency.hpp" #include "env/StackMemoryRegion.hpp" #include "il/Node_inlines.hpp" #include "il/AutomaticSymbol.hpp" @@ -61,6 +62,26 @@ { block; } \ ) +/** + * @brief Adds dependency + */ +inline void +addDependency( + TR::RegisterDependencyConditions *dep, + TR::Register *vreg, + TR::RealRegister::RegNum rnum, + TR_RegisterKinds rk, + TR::CodeGenerator *cg) + { + if (vreg == NULL) + { + vreg = cg->allocateRegister(rk); + } + + dep->addPreCondition(vreg, rnum); + dep->addPostCondition(vreg, rnum); + } + TR::RVSystemLinkage::RVSystemLinkage(TR::CodeGenerator *cg) : TR::Linkage(cg) { diff --git a/compiler/riscv/env/RVProcessorEnum.hpp b/compiler/riscv/env/RVProcessorEnum.hpp new file mode 100644 index 00000000000..02e22529c06 --- /dev/null +++ b/compiler/riscv/env/RVProcessorEnum.hpp @@ -0,0 +1,27 @@ +/******************************************************************************* + * Copyright (c) 2020, 2020 IBM Corp. and others + * + * This program and the accompanying materials are made available under + * the terms of the Eclipse Public License 2.0 which accompanies this + * distribution and is available at http://eclipse.org/legal/epl-2.0 + * or the Apache License, Version 2.0 which accompanies this distribution + * and is available at https://www.apache.org/licenses/LICENSE-2.0. + * + * This Source Code may also be made available under the following Secondary + * Licenses when the conditions for such availability set forth in the + * Eclipse Public License, v. 2.0 are satisfied: GNU General Public License, + * version 2 with the GNU Classpath Exception [1] and GNU General Public + * License, version 2 with the OpenJDK Assembly Exception [2]. + * + * [1] https://www.gnu.org/software/classpath/license.html + * [2] http://openjdk.java.net/legal/assembly-exception.html + * + * SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception + *******************************************************************************/ + +/* + * This file will be included within an enum. Only comments and enumerator + * definitions are permitted. + */ + + RV64G,