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AArch64: Stop generating instruction for adding 0
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This commit changes addConstant32() and addConstant64() for AArch64 so
that they don't generate instructions when the value to be added is 0.

Signed-off-by: KONNO Kazuhiro <[email protected]>
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knn-k committed Apr 18, 2024
1 parent 0e07ad1 commit 0af60f9
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Showing 2 changed files with 18 additions and 18 deletions.
4 changes: 2 additions & 2 deletions compiler/aarch64/codegen/OMRCodeGenerator.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ extern TR::Instruction *loadAddressConstantInSnippet(TR::CodeGenerator *cg, TR::
* @param[in] srcReg : source register
* @param[in] value : value to be added
*/
TR::Instruction *addConstant64(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int64_t value);
void addConstant64(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int64_t value);

/**
* @brief Generates instructions for adding 32-bit integer value to a register
Expand All @@ -129,7 +129,7 @@ TR::Instruction *addConstant64(TR::CodeGenerator *cg, TR::Node *node, TR::Regist
* @param[in] srcReg : source register
* @param[in] value : value to be added
*/
TR::Instruction *addConstant32(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int32_t value);
void addConstant32(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int32_t value);

/**
* @brief Helper function for encoding immediate value of logic instructions.
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32 changes: 16 additions & 16 deletions compiler/aarch64/codegen/OMRTreeEvaluator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5807,42 +5807,42 @@ TR::Instruction *loadConstant64(TR::CodeGenerator *cg, TR::Node *node, int64_t v
return cursor;
}

TR::Instruction *addConstant64(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int64_t value)
void addConstant64(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int64_t value)
{
TR::Instruction *cursor;

if (constantIsUnsignedImm12(value))
if (value == 0)
{
// Do nothing
}
else if (constantIsUnsignedImm12(value))
{
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addimmx, node, trgReg, srcReg, value);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addimmx, node, trgReg, srcReg, value);
}
else
{
TR::Register *tempReg = cg->allocateRegister();
loadConstant64(cg, node, value, tempReg);
cursor = generateTrg1Src2Instruction(cg, TR::InstOpCode::addx, node, trgReg, srcReg, tempReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::addx, node, trgReg, srcReg, tempReg);
cg->stopUsingRegister(tempReg);
}

return cursor;
}

TR::Instruction *addConstant32(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int32_t value)
void addConstant32(TR::CodeGenerator *cg, TR::Node *node, TR::Register *trgReg, TR::Register *srcReg, int32_t value)
{
TR::Instruction *cursor;

if (constantIsUnsignedImm12(value))
if (value == 0)
{
// Do nothing
}
else if (constantIsUnsignedImm12(value))
{
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addimmw, node, trgReg, srcReg, value);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addimmw, node, trgReg, srcReg, value);
}
else
{
TR::Register *tempReg = cg->allocateRegister();
loadConstant32(cg, node, value, tempReg);
cursor = generateTrg1Src2Instruction(cg, TR::InstOpCode::addw, node, trgReg, srcReg, tempReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::addw, node, trgReg, srcReg, tempReg);
cg->stopUsingRegister(tempReg);
}

return cursor;
}

/**
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