From 4fb3128ff863a4fa8fafe787cd232683667a46c0 Mon Sep 17 00:00:00 2001 From: Eric Liu Date: Thu, 16 Nov 2023 08:36:26 +0000 Subject: [PATCH] update m4 Change-Id: I82bf5f9384f79e09965a0498ad2de45cec6f0a29 --- src/hotspot/cpu/aarch64/aarch64_vector.ad | 11 ++-- src/hotspot/cpu/aarch64/aarch64_vector_ad.m4 | 68 +++++--------------- 2 files changed, 21 insertions(+), 58 deletions(-) diff --git a/src/hotspot/cpu/aarch64/aarch64_vector.ad b/src/hotspot/cpu/aarch64/aarch64_vector.ad index d4fc0611b30e3..25a0f14c4f1f7 100644 --- a/src/hotspot/cpu/aarch64/aarch64_vector.ad +++ b/src/hotspot/cpu/aarch64/aarch64_vector.ad @@ -3763,8 +3763,7 @@ instruct vzeroExtBtoX(vReg dst, vReg src) %{ $src$$FloatRegister, T_BYTE, /* is_unsigned */ true); } else { assert(UseSVE > 0, "must be sve"); - Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt); - __ sve_vector_extend($dst$$FloatRegister, size, + __ sve_vector_extend($dst$$FloatRegister, __ elemType_to_regVariant(bt), $src$$FloatRegister, __ B, /* is_unsigned */ true); } %} @@ -3784,8 +3783,7 @@ instruct vzeroExtStoX(vReg dst, vReg src) %{ $src$$FloatRegister, T_SHORT, /* is_unsigned */ true); } else { assert(UseSVE > 0, "must be sve"); - Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt); - __ sve_vector_extend($dst$$FloatRegister, size, + __ sve_vector_extend($dst$$FloatRegister, __ elemType_to_regVariant(bt), $src$$FloatRegister, __ H, /* is_unsigned */ true); } %} @@ -3796,8 +3794,9 @@ instruct vzeroExtItoX(vReg dst, vReg src) %{ match(Set dst (VectorUCastI2X src)); format %{ "vzeroExtItoX $dst, $src" %} ins_encode %{ - assert(Matcher::vector_element_basic_type(this) == T_LONG, "must be"); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); + BasicType bt = Matcher::vector_element_basic_type(this); + assert(bt == T_LONG, "must be"); + uint length_in_bytes = Matcher::vector_length_in_bytes(this); if (VM_Version::use_neon_for_vector(length_in_bytes)) { // 2I to 2L __ neon_vector_extend($dst$$FloatRegister, T_LONG, length_in_bytes, diff --git a/src/hotspot/cpu/aarch64/aarch64_vector_ad.m4 b/src/hotspot/cpu/aarch64/aarch64_vector_ad.m4 index 41537d0e21178..2094d7a040c34 100644 --- a/src/hotspot/cpu/aarch64/aarch64_vector_ad.m4 +++ b/src/hotspot/cpu/aarch64/aarch64_vector_ad.m4 @@ -2321,67 +2321,31 @@ instruct reinterpret_resize_gt128b(vReg dst, vReg src, pReg ptmp, rFlagsReg cr) %} // ---------------------------- Vector zero extend -------------------------------- - -instruct vzeroExtBtoX(vReg dst, vReg src) %{ - match(Set dst (VectorUCastB2X src)); - format %{ "vzeroExtBtoX $dst, $src" %} +dnl VECTOR_ZERO_EXTEND($1, $2, $3, $4, $5 $6, $7, ) +dnl VECTOR_ZERO_EXTEND(op_name, dst_bt, src_bt, dst_size, src_size, assertion, neon_comment) +define(`VECTOR_ZERO_EXTEND', ` +instruct vzeroExt$1toX(vReg dst, vReg src) %{ + match(Set dst (VectorUCast`$1'2X src)); + format %{ "vzeroExt$1toX $dst, $src" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - assert(bt == T_SHORT || bt == T_INT || bt == T_LONG, "must be"); + assert($6, "must be"); uint length_in_bytes = Matcher::vector_length_in_bytes(this); if (VM_Version::use_neon_for_vector(length_in_bytes)) { - // 4B to 4S/4I, 8B to 8S - __ neon_vector_extend($dst$$FloatRegister, bt, length_in_bytes, - $src$$FloatRegister, T_BYTE, /* is_unsigned */ true); + // $7 + __ neon_vector_extend($dst$$FloatRegister, $2, length_in_bytes, + $src$$FloatRegister, $3, /* is_unsigned */ true); } else { assert(UseSVE > 0, "must be sve"); - Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt); - __ sve_vector_extend($dst$$FloatRegister, size, - $src$$FloatRegister, __ B, /* is_unsigned */ true); + __ sve_vector_extend($dst$$FloatRegister, __ $4, + $src$$FloatRegister, __ $5, /* is_unsigned */ true); } %} ins_pipe(pipe_slow); -%} - -instruct vzeroExtStoX(vReg dst, vReg src) %{ - match(Set dst (VectorUCastS2X src)); - format %{ "vzeroExtStoX $dst, $src" %} - ins_encode %{ - BasicType bt = Matcher::vector_element_basic_type(this); - assert(bt == T_INT || bt == T_LONG, "must be"); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); - if (VM_Version::use_neon_for_vector(length_in_bytes)) { - // 4S to 4I - __ neon_vector_extend($dst$$FloatRegister, T_INT, length_in_bytes, - $src$$FloatRegister, T_SHORT, /* is_unsigned */ true); - } else { - assert(UseSVE > 0, "must be sve"); - Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt); - __ sve_vector_extend($dst$$FloatRegister, size, - $src$$FloatRegister, __ H, /* is_unsigned */ true); - } - %} - ins_pipe(pipe_slow); -%} - -instruct vzeroExtItoX(vReg dst, vReg src) %{ - match(Set dst (VectorUCastI2X src)); - format %{ "vzeroExtItoX $dst, $src" %} - ins_encode %{ - assert(Matcher::vector_element_basic_type(this) == T_LONG, "must be"); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); - if (VM_Version::use_neon_for_vector(length_in_bytes)) { - // 2I to 2L - __ neon_vector_extend($dst$$FloatRegister, T_LONG, length_in_bytes, - $src$$FloatRegister, T_INT, /* is_unsigned */ true); - } else { - assert(UseSVE > 0, "must be sve"); - __ sve_vector_extend($dst$$FloatRegister, __ D, - $src$$FloatRegister, __ S, /* is_unsigned */ true); - } - %} - ins_pipe(pipe_slow); -%} +%}')dnl +VECTOR_ZERO_EXTEND(B, bt, T_BYTE, elemType_to_regVariant(bt), B, bt == T_SHORT || bt == T_INT || bt == T_LONG, `4B to 4S/4I, 8B to 8S') +VECTOR_ZERO_EXTEND(S, T_INT, T_SHORT, elemType_to_regVariant(bt), H, bt == T_INT || bt == T_LONG, `4S to 4I') +VECTOR_ZERO_EXTEND(I, T_LONG, T_INT, D, S, bt == T_LONG, `2I to 2L') // ------------------------------ Vector cast ----------------------------------