From e99a6f2818ad5b0c5bbe3a6f45078c7387831fd9 Mon Sep 17 00:00:00 2001
From: Drew Macrae <drewmacrae@google.com>
Date: Wed, 21 Dec 2022 12:51:40 -0500
Subject: [PATCH] [bazel] allocate 5 cores per verilator test to allow for
 harness and overhead

An alternative to #16913 to prevent harnesses from getting pre-empted by
a simulation load.

Signed-off-by: Drew Macrae <drewmacrae@google.com>
---
 rules/opentitan_test.bzl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rules/opentitan_test.bzl b/rules/opentitan_test.bzl
index 4cabdb4a6b11da..e5a59c0150f041 100644
--- a/rules/opentitan_test.bzl
+++ b/rules/opentitan_test.bzl
@@ -152,7 +152,7 @@ def verilator_params(
         "@//hw:verilator",
         "@//hw:fusesoc_ignore",
     ]
-    required_tags = ["verilator", "cpu:4"]
+    required_tags = ["verilator", "cpu:5"]
     kwargs.update(
         args = default_args + args,
         data = required_data + data,