Add ARM64 encodings for group IF_SVE_CT_3A #98085
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsAdds support for encoding Contributing towards #94549.
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@a74nh @kunalspathak @dotnet/arm64-contrib |
kunalspathak
requested changes
Feb 7, 2024
src/coreclr/jit/emitarm64.cpp
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| @@ -1102,6 +1102,12 @@ void emitter::emitInsSanityCheck(instrDesc* id) | |||
| assert(isPredicateRegister(id->idReg3())); // MMMM | |||
| break; | |||
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| case IF_SVE_CT_3A: // ................ ...gggnnnnnddddd -- SVE reverse doublewords | |||
| assert(isVectorRegister(id->idReg3())); // ddddd | |||
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Have these in order of reg1, reg2 and reg3
| @@ -4754,6 +4754,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() | |||
| theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, | |||
| INS_OPTS_SCALABLE_D); // CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T> | |||
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| // IF_SVE_CT_3A | |||
| theEmitter->emitIns_R_R_R(INS_sve_revd, EA_SCALABLE, REG_V1, REG_P0, REG_V6); // REVD <Zd>.Q, <Pg>/M, <Zn>.Q | |||
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since all the tests are identical, 1 or 2 cases should be sufficient enough.
src/coreclr/jit/emitarm64.cpp
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| @@ -1102,6 +1102,12 @@ void emitter::emitInsSanityCheck(instrDesc* id) | |||
| assert(isPredicateRegister(id->idReg3())); // MMMM | |||
| break; | |||
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| case IF_SVE_CT_3A: // ................ ...gggnnnnnddddd -- SVE reverse doublewords | |||
| assert(isVectorRegister(id->idReg3())); // ddddd | |||
| assert(isPredicateRegister(id->idReg2())); // ggg | |||
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Suggested change
| assert(isPredicateRegister(id->idReg2())); // ggg | |
| assert(isLowPredicateRegister(id->idReg2())); // ggg |
src/coreclr/jit/emitarm64.cpp
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| @@ -10017,6 +10023,13 @@ void emitter::emitIns_R_R_R(instruction ins, | |||
| } | |||
| break; | |||
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| case INS_sve_revd: | |||
| assert(isVectorRegister(reg1)); // ddddd | |||
| assert(isPredicateRegister(reg2)); // ggg | |||
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Suggested change
| assert(isPredicateRegister(reg2)); // ggg | |
| assert(isLowPredicateRegister(reg2)); // ggg |
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Diff results for #98085Throughput diffsThroughput diffs for linux/arm64 ran on linux/x64MinOpts (-0.00% to +0.01%)
Throughput diffs for windows/arm64 ran on linux/x64MinOpts (-0.00% to +0.01%)
Details here |
Diff results for #98085Throughput diffsThroughput diffs for linux/arm64 ran on windows/x64MinOpts (-0.00% to +0.01%)
Throughput diffs for windows/arm64 ran on windows/x64MinOpts (-0.00% to +0.01%)
Details here |
This was referenced Feb 7, 2024
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Adds support for encoding
revd. Matching capstone:Contributing towards #94549.