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JIT: ARM64 SVE format encodings, SVE_ID_2A
to SVE_JH_2A
#98015
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsContributes to #94549 Adds 4 formats
This one is pretty short.
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@dotnet/jit-contrib @dotnet/arm64-contrib @a74nh @kunalspathak this is ready, and it's a short one. |
Diff results for #98015Throughput diffsThroughput diffs for linux/arm64 ran on linux/x64Overall (+0.01%)
MinOpts (+0.01% to +0.02%)
FullOpts (+0.01%)
Details here |
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LGTM
src/coreclr/jit/codegenarm64test.cpp
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// IF_SVE_IE_2A | ||
theEmitter->emitIns_R_R_I(INS_sve_ldr, EA_SCALABLE, REG_V3, REG_R4, 0, INS_OPTS_NONE, | ||
INS_SCALABLE_OPTS_UNPREDICATED); // LDR <Zt>, [<Xn|SP>{, #<imm>, MUL VL}] |
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This isn't exactly the right use of INS_SCALABLE_OPTS_UNPREDICATED
. Currently it's used where a predicate isn't being used to mask the result. Whereas here, the predicate is being used as the result.
But, once register allocation is added, we can get rid of INS_SCALABLE_OPTS_UNPREDICATED
.
Therefore, I'm happy with this change.
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As per https://docsmirror.github.io/A64/2023-06/ldr_z_bi.html, this instruction is "unpredicated" and the use of INS_SCALABLE_OPTS_UNPREDICATED
seems to be appropriate here, unless I am missing something.
src/coreclr/jit/codegenarm64test.cpp
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// IF_SVE_IE_2A | ||
theEmitter->emitIns_R_R_I(INS_sve_ldr, EA_SCALABLE, REG_V3, REG_R4, 0, INS_OPTS_NONE, | ||
INS_SCALABLE_OPTS_UNPREDICATED); // LDR <Zt>, [<Xn|SP>{, #<imm>, MUL VL}] |
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As per https://docsmirror.github.io/A64/2023-06/ldr_z_bi.html, this instruction is "unpredicated" and the use of INS_SCALABLE_OPTS_UNPREDICATED
seems to be appropriate here, unless I am missing something.
@kunalspathak this is ready again. |
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LGTM
Diff results for #98015Throughput diffsThroughput diffs for linux/arm64 ran on linux/x64Overall (+0.01%)
MinOpts (+0.01% to +0.02%)
FullOpts (+0.01%)
Details here |
Contributes to #94549
Adds 4 formats
This one is pretty short.
Left: Capstone,
Right: Jit