From a23c7a19076177d85e4a03a889aa9567db41d52a Mon Sep 17 00:00:00 2001 From: Alexander Soldatov Date: Thu, 13 Jul 2023 00:35:22 +0300 Subject: [PATCH] [RISC-V] Missing defines in GC (#88661) --- src/coreclr/gc/env/gcenv.interlocked.inl | 2 +- src/coreclr/gc/gc.cpp | 2 +- src/coreclr/gc/unix/gcenv.unix.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/coreclr/gc/env/gcenv.interlocked.inl b/src/coreclr/gc/env/gcenv.interlocked.inl index 136348b7fcb76..3e4d761bca0d0 100644 --- a/src/coreclr/gc/env/gcenv.interlocked.inl +++ b/src/coreclr/gc/env/gcenv.interlocked.inl @@ -13,7 +13,7 @@ #ifndef _MSC_VER __forceinline void Interlocked::InterlockedOperationBarrier() { -#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64) +#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64) || defined(HOST_RISCV64) // See PAL_InterlockedOperationBarrier() in the PAL __sync_synchronize(); #endif diff --git a/src/coreclr/gc/gc.cpp b/src/coreclr/gc/gc.cpp index cd1736ad8c9cc..14af5f3befaa8 100644 --- a/src/coreclr/gc/gc.cpp +++ b/src/coreclr/gc/gc.cpp @@ -26240,7 +26240,7 @@ void gc_heap::save_post_plug_info (uint8_t* last_pinned_plug, uint8_t* last_obje } // enable on processors known to have a useful prefetch instruction -#if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM64) +#if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM64) || defined(TARGET_RISCV64) #define PREFETCH #endif diff --git a/src/coreclr/gc/unix/gcenv.unix.cpp b/src/coreclr/gc/unix/gcenv.unix.cpp index a024d3f950fda..285b783485802 100644 --- a/src/coreclr/gc/unix/gcenv.unix.cpp +++ b/src/coreclr/gc/unix/gcenv.unix.cpp @@ -136,7 +136,7 @@ typedef cpuset_t cpu_set_t; #endif #endif // __APPLE__ -#if defined(HOST_ARM) || defined(HOST_ARM64) || defined(HOST_LOONGARCH64) +#if defined(HOST_ARM) || defined(HOST_ARM64) || defined(HOST_LOONGARCH64) || defined(HOST_RISCV64) #define SYSCONF_GET_NUMPROCS _SC_NPROCESSORS_CONF #else #define SYSCONF_GET_NUMPROCS _SC_NPROCESSORS_ONLN